[Bug 205853] amdgpu kernel bug: kernel null pointer dereference
https://bugzilla.kernel.org/show_bug.cgi?id=205853 Janpieter Sollie (janpieter.sol...@dommel.be) changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |DOCUMENTED -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 205853] amdgpu kernel bug: kernel null pointer dereference
https://bugzilla.kernel.org/show_bug.cgi?id=205853 --- Comment #4 from Janpieter Sollie (janpieter.sol...@dommel.be) --- Created attachment 286571 --> https://bugzilla.kernel.org/attachment.cgi?id=286571&action=edit working .config this modified .config file allows the DC driver to get things up and running; however: as the IB ring error still exists, I'll have to look further into that, but that's another bug -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 201957] amdgpu: ring gfx timeout
https://bugzilla.kernel.org/show_bug.cgi?id=201957 Janpieter Sollie (janpieter.sol...@dommel.be) changed: What|Removed |Added CC||janpieter.sol...@dommel.be --- Comment #24 from Janpieter Sollie (janpieter.sol...@dommel.be) --- Hi everyone, I have the same issue with a Fiji Nano GPU: UVD6 and VCE3 timeout in ring buffer test @ boot with the AMDGPU driver. Other rings seem to work correctly. To make sure the hardware functions like it should, and it's not a HW error, where (in the amdgpu driver) can I increase the timeout value? -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] panel: simple: Add Ivo M133NWF4 R0
Hi Bjorn.
On Sat, Dec 28, 2019 at 10:06:58PM -0800, Bjorn Andersson wrote:
> The InfoVision Optoelectronics M133NWF4 R0 panel is a 13.3" 1920x1080
> eDP panel, add support for it in panel-simple.
>
> Signed-off-by: Bjorn Andersson
> ---
> drivers/gpu/drm/panel/panel-simple.c | 31
> 1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index ba3f85f36c2f..d7ae0ede2b6e 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -1806,6 +1806,34 @@ static const struct panel_desc innolux_zj070na_01p = {
> },
> };
>
> +static const struct drm_display_mode ivo_m133nwf4_r0_mode = {
> + .clock = 138778,
> + .hdisplay = 1920,
> + .hsync_start = 1920 + 24,
> + .hsync_end = 1920 + 24 + 48,
> + .htotal = 1920 + 24 + 48 + 88,
> + .vdisplay = 1080,
> + .vsync_start = 1080 + 3,
> + .vsync_end = 1080 + 3 + 12,
> + .vtotal = 1080 + 3 + 12 + 17,
> + .vrefresh = 60,
> + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
> +};
> +
> +static const struct panel_desc ivo_m133nwf4_r0 = {
> + .modes = &ivo_m133nwf4_r0_mode,
> + .num_modes = 1,
> + .bpc = 8,
> + .size = {
> + .width = 294,
> + .height = 165,
> + },
> + .delay = {
> + .hpd_absent_delay = 200,
> + .unprepare = 500,
> + },
> +};
For new bindings - at least add connector_type.
And consider bus_format and bus_flags too.
> +
> static const struct display_timing koe_tx14d24vm1bpa_timing = {
> .pixelclock = { 558, 585, 620 },
> .hactive = { 320, 320, 320 },
> @@ -3266,6 +3294,9 @@ static const struct of_device_id platform_of_match[] = {
> }, {
> .compatible = "innolux,zj070na-01p",
> .data = &innolux_zj070na_01p,
> + }, {
> + .compatible = "ivo,m133nwf4-r0",
Compatible must be documented in a binding file.
We are discussing a new binding format where it is simple to add
a new panel. But no final conclusion yet.
The comments above (in panel_desc and here) also apply for the
other patch you sent.
Sam
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Re: [PATCH v2 1/5] pinctrl: Allow modules to use pinctrl_[un]register_mappings
On Mon, 30 Dec 2019, Linus Walleij wrote: > On Mon, Dec 16, 2019 at 9:51 PM Hans de Goede wrote: > >> Currently only the drivers/pinctrl/devicetree.c code allows registering >> pinctrl-mappings which may later be unregistered, all other mappings >> are assumed to be permanent. >> >> Non-dt platforms may also want to register pinctrl mappings from code which >> is build as a module, which requires being able to unregister the mapping >> when the module is unloaded to avoid dangling pointers. >> >> To allow unregistering the mappings the devicetree code uses 2 internal >> functions: pinctrl_register_map and pinctrl_unregister_map. >> >> pinctrl_register_map allows the devicetree code to tell the core to >> not memdup the mappings as it retains ownership of them and >> pinctrl_unregister_map does the unregistering, note this only works >> when the mappings where not memdupped. >> >> The only code relying on the memdup/shallow-copy done by >> pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit >> replaces the __initdata with const, so that the shallow-copy is no >> longer necessary. >> >> After that we can get rid of the internal pinctrl_unregister_map function >> and just use pinctrl_register_mappings directly everywhere. >> >> This commit also renames pinctrl_unregister_map to >> pinctrl_unregister_mappings so that its naming matches its >> pinctrl_register_mappings counter-part and exports it. >> >> Together these 2 changes will allow non-dt platform code to >> register pinctrl-mappings from modules without breaking things on >> module unload (as they can now unregister the mapping on unload). >> >> Signed-off-by: Hans de Goede > > This v2 works fine for me, I applied it to this immutable branch in the > pinctrl tree: > https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-pinctrl-unreg-mappings > > And pulled that into the pinctrl "devel" branch for v5.6. > > Please pull this immutable branch into the Intel DRM tree and apply > the rest of the stuff on top! Thanks, pulled to drm-intel-next-queued. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 0/6] fixes for atmel-hlcdc
Hi Lee.
How do de handle the two mfd related patches?
> I have few fixes for atmel-hlcdc driver in this series as well
> as two reverts.
> Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
> due to the fix in in patch 2/5.
>
> Thank you,
> Claudiu Beznea
>
> Changes in v3:
> - changes dev_err() message in patch 4/6
> - collect Acked-by tags
>
> Changes in v2:
> - introduce patch 3/6
> - use dev_err() inpatch 4/6
> - introduce patch 5/6 instead of reverting commit f6f7ad323461
> ("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested")
>
> Claudiu Beznea (5):
> drm: atmel-hlcdc: use double rate for pixel clock only if supported
> drm: atmel-hlcdc: enable clock before configuring timing engine
> mfd: atmel-hlcdc: add struct device member to struct
> atmel_hlcdc_regmap
> mfd: atmel-hlcdc: return in case of error
Would it be OK to apply the to drm-misc-next, or shal they go in via
your mfd tree?
Sam
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Re: [PATCH v3 5/6] drm: atmel-hlcdc: prefer a lower pixel-clock than requested
On Wed, Dec 18, 2019 at 02:28:28PM +0200, Claudiu Beznea wrote:
> From: Peter Rosin
>
> The intention was to only select a higher pixel-clock rate than the
> requested, if a slight overclocking would result in a rate significantly
> closer to the requested rate than if the conservative lower pixel-clock
> rate is selected. The fixed patch has the logic the other way around and
> actually prefers the higher frequency. Fix that.
>
> Fixes: f6f7ad323461 ("drm/atmel-hlcdc: allow selecting a higher pixel-clock
> than requested")
The id is wrong here - the right one is:
9946a3a9dbedaaacef8b7e94f6ac144f1daaf1de
The wrong id above was used before - so I think it is a copy'n'paste
thing.
Hint: try "dim fixes 9946a3a9dbedaaacef8b7e94f6ac144f1daaf1de"
If I get a quick response from Lee I can fix it up while applying.
Sam
> Reported-by: Claudiu Beznea
> Tested-by: Claudiu Beznea
> Signed-off-by: Peter Rosin
> ---
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> index 721fa88bf71d..10985134ce0b 100644
> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
> @@ -121,8 +121,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct
> drm_crtc *c)
> int div_low = prate / mode_rate;
>
> if (div_low >= 2 &&
> - ((prate / div_low - mode_rate) <
> - 10 * (mode_rate - prate / div)))
> + (10 * (prate / div_low - mode_rate) <
> + (mode_rate - prate / div)))
> /*
>* At least 10 times better when using a higher
>* frequency than requested, instead of a lower.
> --
> 2.7.4
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[Bug 201957] amdgpu: ring gfx timeout
https://bugzilla.kernel.org/show_bug.cgi?id=201957 --- Comment #25 from Janpieter Sollie (janpieter.sol...@dommel.be) --- Created attachment 286575 --> https://bugzilla.kernel.org/attachment.cgi?id=286575&action=edit kernel config 5.4.7 Fiji Some additional info for my case: - Running kernel 5.4.7 (vanilla), firmware 20191108 on gentoo - Dmesg | grep -E "(drm)|(amdgpu)": [3.930023] [drm] amdgpu kernel modesetting enabled. [3.930217] amdgpu :0a:00.0: remove_conflicting_pci_framebuffers: bar 0: 0xe000 -> 0xefff [3.930219] amdgpu :0a:00.0: remove_conflicting_pci_framebuffers: bar 2: 0xf000 -> 0xf01f [3.930221] amdgpu :0a:00.0: remove_conflicting_pci_framebuffers: bar 5: 0xfce0 -> 0xfce3 [3.930224] fb0: switching to amdgpudrmfb from EFI VGA [3.930475] [drm] initializing kernel modesetting (FIJI 0x1002:0x7300 0x1002:0x0B36 0xCA). [3.930486] [drm] register mmio base: 0xFCE0 [3.930486] [drm] register mmio size: 262144 [3.930495] [drm] add ip block number 0 [3.930495] [drm] add ip block number 1 [3.930496] [drm] add ip block number 2 [3.930497] [drm] add ip block number 3 [3.930498] [drm] add ip block number 4 [3.930498] [drm] add ip block number 5 [3.930499] [drm] add ip block number 6 [3.930500] [drm] add ip block number 7 [3.930500] [drm] add ip block number 8 [3.930715] [drm] UVD is enabled in physical mode [3.930715] [drm] VCE enabled in physical mode [3.930743] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, fragment size is 9-bit [3.930751] amdgpu :0a:00.0: VRAM: 4096M 0x00F4 - 0x00F4 (4096M used) [3.930753] amdgpu :0a:00.0: GART: 1024M 0x00FF - 0x00FF3FFF [3.930758] [drm] Detected VRAM RAM=4096M, BAR=256M [3.930759] [drm] RAM width 512bits HBM [3.930838] [drm] amdgpu: 4096M of VRAM memory ready [3.930841] [drm] amdgpu: 4096M of GTT memory ready. [3.930860] [drm] GART: num cpu pages 262144, num gpu pages 262144 [3.930928] [drm] PCIE GART of 1024M enabled (table at 0x00F4001D5000). [3.934174] [drm] Chained IB support enabled! [3.940198] amdgpu: [powerplay] hwmgr_sw_init smu backed is fiji_smu [3.941748] [drm] Found UVD firmware Version: 1.91 Family ID: 12 [3.941752] [drm] UVD ENC is disabled [3.943542] [drm] Found VCE firmware Version: 55.2 Binary ID: 3 [4.009146] [drm] dce110_link_encoder_construct: Failed to get encoder_cap_info from VBIOS with error code 4! [4.040084] [drm] Display Core initialized with v3.2.48! [4.040542] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [4.040543] [drm] Driver supports precise vblank timestamp query. [4.067774] [drm] UVD initialized successfully. [4.168780] [drm] VCE initialized successfully. [4.170163] [drm] Cannot find any crtc or sizes [4.171948] [drm] Initialized amdgpu 3.35.0 20150101 for :0a:00.0 on minor 0 [7.280062] amdgpu :0a:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on uvd (-110). [8.400365] amdgpu :0a:00.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed on vce0 (-110). [8.400370] [drm:process_one_work] *ERROR* ib ring test failed (-110). -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 3/5] drm/i915/dsi: Init panel-enable GPIO to low when the LCD is initially off (v2)
On Mon, 16 Dec 2019, Hans de Goede wrote:
> When the LCD has not been turned on by the firmware/GOP, because e.g. the
> device was booted with an external monitor connected over HDMI, we should
> not turn on the panel-enable GPIO when we request it.
>
> Turning on the panel-enable GPIO when we request it, means we turn it on
> too early in the init-sequence, which causes some panels to not correctly
> light up.
>
> This commits adds a panel_is_on parameter to intel_dsi_vbt_gpio_init()
> and makes intel_dsi_vbt_gpio_init() set the initial GPIO value accordingly.
>
> This fixes the panel not lighting up on a Thundersoft TST168 tablet when
> booted with an external monitor connected over HDMI.
>
> Changes in v2:
> - Call intel_dsi_get_hw_state() to check if the panel is on instead of
> relying on the current_mode pointer
>
> Reviewed-by: Linus Walleij
> Signed-off-by: Hans de Goede
> ---
> drivers/gpu/drm/i915/display/intel_dsi.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 7 +++
> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +++-
> 3 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h
> b/drivers/gpu/drm/i915/display/intel_dsi.h
> index de7e51cd3460..675771ea91aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -203,7 +203,7 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder,
> enum port port);
>
> /* intel_dsi_vbt.c */
> bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
> -void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi);
> +void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);
> void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi);
> void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
>enum mipi_seq seq_id);
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index 8be7d6c507aa..4210f449553e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -688,17 +688,16 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi,
> u16 panel_id)
> * On some BYT/CHT devs some sequences are incomplete and we need to manually
> * control some GPIOs.
> */
> -void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi)
> +void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on)
> {
> struct drm_device *dev = intel_dsi->base.base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
> + enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> mipi_config->pwm_blc == PPS_BLC_PMIC) {
> - intel_dsi->gpio_panel =
> - gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
> -
> + intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
> if (IS_ERR(intel_dsi->gpio_panel)) {
> DRM_ERROR("Failed to own gpio for panel control\n");
> intel_dsi->gpio_panel = NULL;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index c1edd8857af0..d0efee09c593 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1759,6 +1759,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
> struct drm_connector *connector;
> struct drm_display_mode *current_mode, *fixed_mode;
> enum port port;
> + enum pipe pipe;
>
> DRM_DEBUG_KMS("\n");
>
> @@ -1857,7 +1858,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>
> vlv_dphy_param_init(intel_dsi);
>
> - intel_dsi_vbt_gpio_init(intel_dsi);
> + intel_dsi_vbt_gpio_init(intel_dsi,
> + intel_dsi_get_hw_state(intel_encoder, &pipe));
Feels a bit scary to call into the hooks before everything is
initialized, but this seems safe. Fingers crossed.
Reviewed-by: Jani Nikula
>
> drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
> DRM_MODE_CONNECTOR_DSI);
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
On Mon, 30 Dec 2019, Animesh Manna wrote:
> vswing/pre-emphasis adjustment calculation is needed in processing
> of auto phy compliance request other than link training, so moved
> the same function in intel_dp.c.
I guess I'm still asking why you think this is better located in
intel_dp.c than intel_dp_link_training.c, as the function has been moved
once in the other direction already to split out stuff from intel_dp.c
and to make the file smaller. Even the file name suggests it should
really be in intel_dp_link_training.c, right?
BR,
Jani.
>
> No functional change.
>
> v1: initial patch.
> v2:
> - used "intel_dp" prefix in function name. (Jani)
> - used array notation instead pointer for link_status. (Ville)
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 34 ++
> drivers/gpu/drm/i915/display/intel_dp.h | 4 +++
> .../drm/i915/display/intel_dp_link_training.c | 36 ++-
> 3 files changed, 40 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 991f343579ef..2a27ee106089 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
> }
> }
>
> +void
> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> + u8 v = 0;
> + u8 p = 0;
> + int lane;
> + u8 voltage_max;
> + u8 preemph_max;
> +
> + for (lane = 0; lane < intel_dp->lane_count; lane++) {
> + u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
> + lane);
> + u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> +lane);
> +
> + if (this_v > v)
> + v = this_v;
> + if (this_p > p)
> + p = this_p;
> + }
> +
> + voltage_max = intel_dp_voltage_max(intel_dp);
> + if (v >= voltage_max)
> + v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> +
> + preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> + if (p >= preemph_max)
> + p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> + for (lane = 0; lane < 4; lane++)
> + intel_dp->train_set[lane] = v | p;
> +}
> +
> void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 3da166054788..83eadc87af26 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -9,6 +9,7 @@
> #include
>
> #include
> +#include
>
> #include "i915_reg.h"
>
> @@ -91,6 +92,9 @@ void
> intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
> u8 dp_train_pat);
> void
> +intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> + const u8 link_status[DP_LINK_STATUS_SIZE]);
> +void
> intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> u8
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2a1130dd1ad0..e8ff9e279800 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8
> link_status[DP_LINK_STATUS_SIZE])
> link_status[3], link_status[4], link_status[5]);
> }
>
> -static void
> -intel_get_adjust_train(struct intel_dp *intel_dp,
> -const u8 link_status[DP_LINK_STATUS_SIZE])
> -{
> - u8 v = 0;
> - u8 p = 0;
> - int lane;
> - u8 voltage_max;
> - u8 preemph_max;
> -
> - for (lane = 0; lane < intel_dp->lane_count; lane++) {
> - u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
> lane);
> - u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
> lane);
> -
> - if (this_v > v)
> - v = this_v;
> - if (this_p > p)
> - p = this_p;
> - }
> -
> - voltage_max = intel_dp_voltage_max(intel_dp);
> - if (v >= voltage_max)
> - v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
> -
> - preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
> - if (p >= preemph_max)
> - p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> - for (lane = 0; lane < 4; lane++)
> - intel_dp->train_set[lane] = v | p;
> -}
> -
> static bool
> intel_dp_set_link_train(struct intel_dp *intel_dp,
> u8 dp_train_pat)
> @@ -215,7 +183,7 @@ int
Re: [Intel-gfx] [PATCH v3 8/9] drm/i915/dp: Update the pattern as per request
On Mon, 30 Dec 2019, Animesh Manna wrote:
> As per request from DP phy compliance test few special
> test pattern need to set by source. Added function
> to set pattern in DP_COMP_CTL register. It will be
> called along with other test parameters like vswing,
> pre-emphasis programming in atomic_commit_tail path.
>
> Signed-off-by: Animesh Manna
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 55 +
> 1 file changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index cbefda9b6204..7c3f65e5d88b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5005,6 +5005,61 @@ static u8 intel_dp_prepare_phytest(struct intel_dp
> *intel_dp)
> return DP_TEST_ACK;
> }
>
> +static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
As a general rule, please only use the inline keyword for static inlines
in headers. Sometimes, it's useful in small helpers, but usually you
should just let the compiler decide what gets inlined.
In this case, the inline probably just hides the compiler warning about
the unused function.
BR,
Jani.
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
> + u32 temp;
> +
> + switch (data->phy_pattern) {
> + case DP_PHY_TEST_PATTERN_NONE:
> + DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port), 0x0);
> + break;
> + case DP_PHY_TEST_PATTERN_D10_2:
> + DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
> + break;
> + case DP_PHY_TEST_PATTERN_ERROR_COUNT:
> + DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +DDI_DP_COMP_CTL_ENABLE |
> +DDI_DP_COMP_CTL_SCRAMBLED_0);
> + break;
> + case DP_PHY_TEST_PATTERN_PRBS7:
> + DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
> + break;
> + case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
> + DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern\n");
> + temp = ((data->custom80[0] << 24) | (data->custom80[1] << 16) |
> + (data->custom80[2] << 8) | (data->custom80[3]));
> + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 0), temp);
> + temp = ((data->custom80[4] << 24) | (data->custom80[5] << 16) |
> + (data->custom80[6] << 8) | (data->custom80[7]));
> + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 1), temp);
> + temp = ((data->custom80[8] << 8) | data->custom80[9]);
> + I915_WRITE(DDI_DP_COMP_PAT(intel_dig_port->base.port, 2), temp);
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_CUSTOM80);
> + break;
> + case DP_PHY_TEST_PATTERN_CP2520:
> + DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
> + temp = ((data->hbr2_reset[1] << 8) | data->hbr2_reset[0]);
> + I915_WRITE(DDI_DP_COMP_CTL(intel_dig_port->base.port),
> +DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
> +temp);
> + break;
> + default:
> + WARN(1, "Invalid Phy Test PAttern\n");
> + }
> +}
> +
> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> u8 test_result = DP_TEST_NAK;
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [RFC 3/4] drm/sun4i: Reimplement plane z position setting logic
On Sun, Dec 29, 2019 at 02:02:33PM +0100, Jernej Škrabec wrote:
> Dne nedelja, 29. december 2019 ob 13:47:38 CET je Roman Stratiienko
> napisal(a):
> > On Sun, Dec 29, 2019 at 2:18 PM Jernej Škrabec
> wrote:
> > > Dne nedelja, 29. december 2019 ob 13:08:19 CET je Roman Stratiienko
> > >
> > > napisal(a):
> > > > Hello Jernej,
> > > >
> > > > Thank you for review.
> > > >
> > > > On Sun, Dec 29, 2019 at 11:40 AM Jernej Škrabec
> > > >
> > >
> > > wrote:
> > > > > Hi!
> > > > >
> > > > > Dne sobota, 28. december 2019 ob 21:28:17 CET je
> > > > >
> > > > > roman.stratiie...@globallogic.com napisal(a):
> > > > > > From: Roman Stratiienko
> > > > > >
> > > > > > To set blending channel order register software needs to know state
> > > > > > and
> > > > > > position of each channel, which impossible at plane commit stage.
> > > > > >
> > > > > > Move this procedure to atomic_flush stage, where all necessary
> > > > > > information
> > > > > > is available.
> > > > > >
> > > > > > Signed-off-by: Roman Stratiienko
> > > > > > ---
> > > > > >
> > > > > > drivers/gpu/drm/sun4i/sun8i_mixer.c| 47
> > > > > > +-
> > > > > > drivers/gpu/drm/sun4i/sun8i_mixer.h| 3 ++
> > > > > > drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 42 ---
> > > > > > drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 39 +++--
> > > > > > 4 files changed, 60 insertions(+), 71 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> > > > > > b/drivers/gpu/drm/sun4i/sun8i_mixer.c index
> > > > > > bb9a665fd053..da84fccf7784
> > > > > > 100644
> > > > > > --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> > > > > > +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> > > > > > @@ -307,8 +307,47 @@ static void sun8i_atomic_begin(struct
> > > > > > sunxi_engine
> > > > > > *engine,
> > > > > >
> > > > > > static void sun8i_mixer_commit(struct sunxi_engine *engine)
> > > > > > {
> > > > > >
> > > > > > - DRM_DEBUG_DRIVER("Committing changes\n");
> > > > > > + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
> > > > > > + u32 base = sun8i_blender_base(mixer);
> > > > > > + int i, j;
> > > > > > + int channel_by_zpos[4] = {-1, -1, -1, -1};
> > > > > > + u32 route = 0, pipe_ctl = 0;
> > > > > > +
> > > > > > + DRM_DEBUG_DRIVER("Update blender routing\n");
> > > > >
> > > > > Use drm_dbg().
> > > > >
> > > > > > + for (i = 0; i < 4; i++) {
> > > > > > + int zpos = mixer->channel_zpos[i];
> > > > >
> > > > > channel_zpos can hold 5 elements which is also theoretical maximum for
> > > > > current HW design. Why do you check only 4 elements?
> > > >
> > > > I'll use plane_cnt as it done in mixer_bind
> > > >
> > > > > It would be great to introduce a macro like SUN8I_MIXER_MAX_LAYERS so
> > > > > everyone would understand where this number comes from.
> > > >
> > > > Will do.
> > > >
> > > > > > +
> > > > > > + if (zpos >= 0 && zpos < 4)
> > > > > > + channel_by_zpos[zpos] = i;
> > > > > > + }
> > > > > > +
> > > > > > + j = 0;
> > > > > > + for (i = 0; i < 4; i++) {
> > > > > > + int ch = channel_by_zpos[i];
> > > > > > +
> > > > > > + if (ch >= 0) {
> > > > > > + pipe_ctl |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(j);
> > > > > > + route |= ch <<
> > > > >
> > > > > SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j);
> > > > >
> > > > > > + j++;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + for (i = 0; i < 4 && j < 4; i++) {
> > > > > > + int zpos = mixer->channel_zpos[i];
> > > > > >
> > > > > > + if (zpos < 0) {
> > > > > > + route |= i <<
> > > > >
> > > > > SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(j);
> > > > >
> > > > > > + j++;
> > > > > > + }
> > > > > > + }
> > > > > > +
> > > > > > + regmap_update_bits(mixer->engine.regs,
> > > > >
> > > > > SUN8I_MIXER_BLEND_PIPE_CTL(base),
> > > > >
> > > > > > +SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK,
> > > > >
> > > > > pipe_ctl);
> > > > >
> > > > > > +
> > > > > > + regmap_write(mixer->engine.regs,
> > > > > > + SUN8I_MIXER_BLEND_ROUTE(base), route);
> > > > > > +
> > > > > > + DRM_DEBUG_DRIVER("Committing changes\n");
> > > > >
> > > > > Use drm_dbg().
> > > >
> > > > According to
> > > > https://github.com/torvalds/linux/commit/99a954874e7b9f0c8058476575593b3
> > > > beb
> > > > 5731a5#diff-b0cd2d683c6afbab7bd54173cfd3d3ecR289 ,
> > > > DRM_DEBUG_DRIVER uses drm_dbg.
> > > > Also, using drm_dbg with category macro would require larger indent,
> > > > making harder to fit in 80 chars limit.
> > >
> > > From what I can see, category is already defined by macro name. Check
> > > here:
> > > https://cgit.freedesktop.org/drm/drm-misc/tree/include/drm/drm_print.h#n46
> > > 5
> > >
> > > So it should be actually shorter.
> >
[PATCH 1/6] drm/etnaviv: update hardware headers from rnndb
Update the state HI header from rnndb commit
7f1ce75 ("rnndb: document some GPU identity register")
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/state_hi.xml.h | 29 --
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h
b/drivers/gpu/drm/etnaviv/state_hi.xml.h
index 41d8da2b6f4f..004d8ddacf6a 100644
--- a/drivers/gpu/drm/etnaviv/state_hi.xml.h
+++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in
this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
-- common.xml( 35468 bytes, from 2018-01-22 13:48:54)
-- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
-- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
-- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
-- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
-- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
-
-Copyright (C) 2012-2018 by the following authors:
+- state.xml ( 2 bytes, from 2019-12-20 21:20:35)
+- common.xml( 35468 bytes, from 2018-02-10 13:09:26)
+- common_3d.xml ( 15058 bytes, from 2019-12-28 20:02:03)
+- state_hi.xml ( 30552 bytes, from 2019-12-28 20:02:48)
+- copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26)
+- state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26)
+- state_3d.xml ( 83098 bytes, from 2019-12-28 20:02:03)
+- state_blt.xml ( 14252 bytes, from 2019-10-20 19:59:15)
+- state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26)
+
+Copyright (C) 2012-2019 by the following authors:
- Wladimir J. van der Laan
- Christian Gmeiner
- Lucas Stach
@@ -48,6 +48,9 @@ DEALINGS IN THE SOFTWARE.
#define MMU_EXCEPTION_SLAVE_NOT_PRESENT
0x0001
#define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x0002
#define MMU_EXCEPTION_WRITE_VIOLATION 0x0003
+#define MMU_EXCEPTION_OUT_OF_BOUND 0x0004
+#define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x0005
+#define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x0006
#define VIVS_HI
0x
#define VIVS_HI_CLOCK_CONTROL 0x
@@ -140,6 +143,8 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_HI_CHIP_TIME 0x002c
+#define VIVS_HI_CHIP_CUSTOMER_ID 0x0030
+
#define VIVS_HI_CHIP_MINOR_FEATURE_0 0x0034
#define VIVS_HI_CACHE_CONTROL 0x0038
@@ -237,6 +242,8 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_HI_BLT_INTR 0x00d4
+#define VIVS_HI_CHIP_ECO_ID0x00e8
+
#define VIVS_HI_AUXBIT 0x00ec
#define VIVS_PM
0x
--
2.24.1
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[PATCH 5/6] drm/etnaviv: update hwdb selection logic
Take product id, customer id and eco id into account. If that
delivers no match try a search for model and revision.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index eb0f3eb87ced..d1744f1b44b1 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -44,9 +44,26 @@ bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
struct etnaviv_chip_identity *ident = &gpu->identity;
int i;
+ /* accurate match */
for (i = 0; i < ARRAY_SIZE(etnaviv_chip_identities); i++) {
if (etnaviv_chip_identities[i].model == ident->model &&
- etnaviv_chip_identities[i].revision == ident->revision) {
+ etnaviv_chip_identities[i].revision == ident->revision &&
+ etnaviv_chip_identities[i].product_id == ident->product_id
&&
+ etnaviv_chip_identities[i].customer_id ==
ident->customer_id &&
+ etnaviv_chip_identities[i].eco_id == ident->eco_id) {
+ memcpy(ident, &etnaviv_chip_identities[i],
+ sizeof(*ident));
+ return true;
+ }
+ }
+
+ /* match based only on model and revision */
+ for (i = 0; i < ARRAY_SIZE(etnaviv_chip_identities); i++) {
+ if (etnaviv_chip_identities[i].model == ident->model &&
+ etnaviv_chip_identities[i].revision == ident->revision &&
+ etnaviv_chip_identities[i].product_id == ~0U &&
+ etnaviv_chip_identities[i].customer_id == ~0U &&
+ etnaviv_chip_identities[i].eco_id == ~0U) {
memcpy(ident, &etnaviv_chip_identities[i],
sizeof(*ident));
return true;
--
2.24.1
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[PATCH 2/6] drm/etnaviv: determine product, customer and eco id
They will be used for extended HWDB support. The eco id logic was taken
from galcore kernel driver sources.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 17 +
drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 6 +++---
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index d47d1a8e0219..253301be9e95 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -321,6 +321,18 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
gpu->identity.varyings_count -= 1;
}
+static void etnaviv_hw_eco_id(struct etnaviv_gpu *gpu)
+{
+ const u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
+ gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
+
+ if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate ==
0x20120617))
+ gpu->identity.eco_id = 1;
+
+ if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate ==
0x20140511))
+ gpu->identity.eco_id = 1;
+}
+
static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
{
u32 chipIdentity;
@@ -362,6 +374,8 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
}
}
+ gpu->identity.product_id = gpu_read(gpu,
VIVS_HI_CHIP_PRODUCT_ID);
+
/*
* NXP likes to call the GPU on the i.MX6QP GC2000+, but in
* reality it's just a re-branded GC3000. We can identify this
@@ -375,6 +389,9 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
}
}
+ etnaviv_hw_eco_id(gpu);
+ gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID);
+
dev_info(gpu->dev, "model: GC%x, revision: %x\n",
gpu->identity.model, gpu->identity.revision);
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
index 8f9bd4edc96a..68bd966e3916 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
@@ -15,11 +15,11 @@ struct etnaviv_gem_submit;
struct etnaviv_vram_mapping;
struct etnaviv_chip_identity {
- /* Chip model. */
u32 model;
-
- /* Revision value.*/
u32 revision;
+ u32 product_id;
+ u32 customer_id;
+ u32 eco_id;
/* Supported feature fields. */
u32 features;
--
2.24.1
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[PATCH 0/6] update hwdw for gc400
This patch series extends the hwdb for an entry for the gc400 found in the ST STM32 SoC. With this patches we report the same limits and features for this GPU as the galcore kernel driver does. Christian Gmeiner (6): drm/etnaviv: update hardware headers from rnndb drm/etnaviv: determine product, customer and eco id drm/etnaviv: show identity information in debugfs drm/etnaviv: update gc7000 chip identity entry drm/etnaviv: update hwdb selection logic drm/etnaviv: add hwdb entry for gc400 found in STM32 drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 29 ++ drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 6 +-- drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 53 +- drivers/gpu/drm/etnaviv/state_hi.xml.h | 29 -- 4 files changed, 102 insertions(+), 15 deletions(-) -- 2.24.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 6/6] drm/etnaviv: add hwdb entry for gc400 found in STM32
The information was taken from STM32 glacore driver hw database.
The entry is named as gc7000nano_0x4652.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 31 ++
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index d1744f1b44b1..8495b041a3b7 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -6,6 +6,37 @@
#include "etnaviv_gpu.h"
static const struct etnaviv_chip_identity etnaviv_chip_identities[] = {
+ {
+ .model = 0x400,
+ .revision = 0x4652,
+ .product_id = 0x70001,
+ .customer_id = 0x100,
+ .eco_id = 0,
+ .stream_count = 4,
+ .register_max = 64,
+ .thread_count = 128,
+ .shader_core_count = 1,
+ .vertex_cache_size = 8,
+ .vertex_output_buffer_size = 1024,
+ .pixel_pipes = 1,
+ .instruction_count = 256,
+ .num_constants = 320,
+ .buffer_size = 0,
+ .varyings_count = 8,
+ .features = 0xa0e9e004,
+ .minor_features0 = 0xe1299fff,
+ .minor_features1 = 0xbe13b219,
+ .minor_features2 = 0xce110010,
+ .minor_features3 = 0x801,
+ .minor_features4 = 0x20102,
+ .minor_features5 = 0x12,
+ .minor_features6 = 0x0,
+ .minor_features7 = 0x0,
+ .minor_features8 = 0x0,
+ .minor_features9 = 0x0,
+ .minor_features10 = 0x0,
+ .minor_features11 = 0x0,
+ },
{
.model = 0x7000,
.revision = 0x6214,
--
2.24.1
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[PATCH 4/6] drm/etnaviv: update gc7000 chip identity entry
Use ~0U as marker for 'I do not care'. I am not sure what
GC7000 based devices are in the wild and I do not want to
break them. In the near future we should extend the hwdb.
Signed-off-by: Christian Gmeiner
---
drivers/gpu/drm/etnaviv/etnaviv_hwdb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
index 39b463db76c9..eb0f3eb87ced 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_hwdb.c
@@ -9,6 +9,9 @@ static const struct etnaviv_chip_identity
etnaviv_chip_identities[] = {
{
.model = 0x7000,
.revision = 0x6214,
+ .product_id = ~0U,
+ .customer_id = ~0U,
+ .eco_id = ~0U,
.stream_count = 16,
.register_max = 64,
.thread_count = 1024,
--
2.24.1
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[PATCH 3/6] drm/etnaviv: show identity information in debugfs
Signed-off-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 253301be9e95..cecef5034db1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -868,6 +868,18 @@ int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) verify_dma(gpu, &debug); + seq_puts(m, "\tidentity\n"); + seq_printf(m, "\t model: 0x%x\n", + gpu->identity.model); + seq_printf(m, "\t revision: 0x%x\n", + gpu->identity.revision); + seq_printf(m, "\t product_id: 0x%x\n", + gpu->identity.product_id); + seq_printf(m, "\t customer_id: 0x%x\n", + gpu->identity.customer_id); + seq_printf(m, "\t eco_id: 0x%x\n", + gpu->identity.eco_id); + seq_puts(m, "\tfeatures\n"); seq_printf(m, "\t major_features: 0x%08x\n", gpu->identity.features); -- 2.24.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/i915: remove boolean comparisons in conditionals.
On Thu, 02 Jan 2020, Wambui Karuga wrote:
> Remove unnecessary comparisons to true/false in if statements.
> Issues found by coccinelle.
>
> Signed-off-by: Wambui Karuga
Thanks for the patch.
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9ba794cb9b4f..c065078b3be2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1812,7 +1812,7 @@ void intel_ddi_set_vc_payload_alloc(const struct
> intel_crtc_state *crtc_state,
> u32 temp;
>
> temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
> - if (state == true)
> + if (state)
> temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> else
> temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index aa515261cb9f..93140c75386a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4958,7 +4958,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
> WARN_ON_ONCE(intel_dp->active_mst_links < 0);
> bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
> go_again:
> - if (bret == true) {
> + if (bret) {
>
> /* check link status - esi[10] = 0x200c */
> if (intel_dp->active_mst_links > 0 &&
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
> b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 47f5d87a938a..cff254c52f5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -3292,8 +3292,8 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
> if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
> goto err;
>
> - if (intel_sdvo_output_setup(intel_sdvo,
> - intel_sdvo->caps.output_flags) != true) {
> + if (!intel_sdvo_output_setup(intel_sdvo,
> + intel_sdvo->caps.output_flags)) {
> DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
> SDVO_NAME(intel_sdvo));
> /* Output_setup can leave behind connectors! */
--
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH v3 2/2] drm/sun4i: Use CRTC size instead of PRIMARY plane size as mixer frame.
Hi,
On Wed, Jan 01, 2020 at 10:47:50PM +0200, roman.stratiie...@globallogic.com
wrote:
> From: Roman Stratiienko
>
> According to DRM documentation the only difference between PRIMARY
> and OVERLAY plane is that each CRTC must have PRIMARY plane and
> OVERLAY are optional.
>
> Allow PRIMARY plane to have dimension different from full-screen.
>
> Fixes: 5bb5f5dafa1a ("drm/sun4i: Reorganize UI layer code in DE2")
> Signed-off-by: Roman Stratiienko
So it applies to all the 4 patches you've sent, but this lacks some
context.
There's a few questions that should be answered here:
- Which situation is it fixing?
- What tool / userspace stack is it fixing?
- What happens with your fix? Do you set the plane at coordinates
0,0 (meaning you'll crop the top-lef corner), do you center it? If
the plane is smaller than the CTRC size, what is set on the edges?
Thanks!
Maxime
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[PATCH v2 0/2] combine bindings for simple panels in a few files
This patchset introduces two files: panel-simple.yaml panel-simple-dsi.yaml The two files will be used for bindings for simple panels that have only a single power-supply. For now only a few bindings are migrated - the reamining bindings will be migrated when we have agreed on the format. v2: - updated binding description in panel-simple.yaml - fixed exampe in panel-simple.yaml (I was missing libyaml-dev - now the examples are checked properly here) - added panel-simple-dsi.yaml Sam Sam Ravnborg (2): dt-bindings: one binding file for all simple panels dt-bindings: one file of all simple DSI panels .../display/panel/ampire,am-480272h3tmqw-t01h.yaml | 42 -- .../display/panel/ampire,am800480r3tmqwa1h.txt | 7 --- .../display/panel/panasonic,vvx10f034n00.txt | 20 --- .../bindings/display/panel/panel-simple-dsi.yaml | 67 ++ .../bindings/display/panel/panel-simple.yaml | 59 +++ 5 files changed, 126 insertions(+), 69 deletions(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 1/2] dt-bindings: one binding file for all simple panels
There is an increasing number of new simple panels.
Common for many of these simple panels are that they have one
mandatory power-supply and some of them have backlight and / or
an enable gpio.
The binding file to describe these panels adds overhead
that really do not add value.
The binding are known and there is nothing gained from a
dedicated binding file nor for any dedicated example.
The following patch introduces a single panel-simple.yaml
and converts two ampire bindings over to the new file.
The conversion - if applied will have following effects:
- The maintainer for the individual file will change
There is no need for many different maintainers for a simple binding.
We have the same situation with the panel-simple driver in the kernel.
- The license will change to (GPL-2.0-only OR BSD-2-Clause)
There is usually only a single line copied from the original
file, a line that is often copied from a datasheet.
This license change should be acceptable considered what little
is copied.
If the license change is not OK we can use a dedicated binding
file in these cases.
This is a follow-up on Rob's big patch converting a lot of panel bindings
to individual files:
"dt-bindings: display: Convert a bunch of panels to DT schema"
https://patchwork.ozlabs.org/patch/1197683/
The objectives with one file for the relevant simple panels are:
- Make it simpler to add bindings for simple panels
- Keep the number of bindings file lower and thus easier to find a
relevant file to copy from when adding new panels.
- Keep the binding documentation for simple panels more consistent
- Make it simpler to add support for new panels
v2:
- spelling fixes (imirkin via irc, Rob)
- updated description (Rob)
- list properires in alphabetical order
- added power-supply to example (Rob)
- updated title
- reworded changelog a little
Signed-off-by: Sam Ravnborg
Cc: Thierry Reding
Cc: Rob Herring
Cc: Maxime Ripard
Cc: Yannick Fertre
Cc: Mark Rutland
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: devicet...@vger.kernel.org
---
.../panel/ampire,am-480272h3tmqw-t01h.yaml| 42 -
.../panel/ampire,am800480r3tmqwa1h.txt| 7 ---
.../bindings/display/panel/panel-simple.yaml | 59 +++
3 files changed, 59 insertions(+), 49 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml
delete mode 100644
Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/panel-simple.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml
b/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml
deleted file mode 100644
index c6e33e7f36d0..
---
a/Documentation/devicetree/bindings/display/panel/ampire,am-480272h3tmqw-t01h.yaml
+++ /dev/null
@@ -1,42 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
-$id:
http://devicetree.org/schemas/display/panel/ampire,am-480272h3tmqw-t01h.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel
-
-maintainers:
- - Yannick Fertre
- - Thierry Reding
-
-allOf:
- - $ref: panel-common.yaml#
-
-properties:
- compatible:
-const: ampire,am-480272h3tmqw-t01h
-
- power-supply: true
- enable-gpios: true
- backlight: true
- port: true
-
-required:
- - compatible
-
-additionalProperties: false
-
-examples:
- - |
-panel_rgb: panel {
- compatible = "ampire,am-480272h3tmqw-t01h";
- enable-gpios = <&gpioa 8 1>;
- port {
-panel_in_rgb: endpoint {
- remote-endpoint = <&controller_out_rgb>;
-};
- };
-};
-
-...
diff --git
a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt
b/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt
deleted file mode 100644
index 83e2cae1cc1b..
---
a/Documentation/devicetree/bindings/display/panel/ampire,am800480r3tmqwa1h.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel
-
-Required properties:
-- compatible: should be "ampire,am800480r3tmqwa1h"
-
-This binding is compatible with the simple-panel binding, which is specified
-in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
new file mode 100644
index ..51ca50201182
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-simple.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple panels with one power supply
+
+maintainers:
+ - Thierry Re
[PATCH v2 2/2] dt-bindings: one file of all simple DSI panels
To complement panel-simple.yaml, create panel-simple-dsi.yaml.
panel-simple-dsi-yaml are for all simple DSP panels with a single
power-supply and optional backlight / enable GPIO.
Migrate panasonic,vvx10f034n00 over to the new file.
The objectives with one file for all the simple DSI panels are:
- Make it simpler to add bindings for simple DSI panels
- Keep the number of bindings file lower
- Keep the binding documentation for simple DSI panels more consistent
Signed-off-by: Sam Ravnborg
Cc: Thierry Reding
Cc: Rob Herring
Cc: Maxime Ripard
Cc: Yannick Fertre
Cc: Mark Rutland
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Cc: devicet...@vger.kernel.org
---
.../display/panel/panasonic,vvx10f034n00.txt | 20 --
.../display/panel/panel-simple-dsi.yaml | 67 +++
2 files changed, 67 insertions(+), 20 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt
create mode 100644
Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
diff --git
a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt
b/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt
deleted file mode 100644
index 37dedf6a6702..
--- a/Documentation/devicetree/bindings/display/panel/panasonic,vvx10f034n00.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Panasonic 10" WUXGA TFT LCD panel
-
-Required properties:
-- compatible: should be "panasonic,vvx10f034n00"
-- reg: DSI virtual channel of the peripheral
-- power-supply: phandle of the regulator that provides the supply voltage
-
-Optional properties:
-- backlight: phandle of the backlight device attached to the panel
-
-Example:
-
- mdss_dsi@fd922800 {
- panel@0 {
- compatible = "panasonic,vvx10f034n00";
- reg = <0>;
- power-supply = <&vreg_vsp>;
- backlight = <&lp8566_wled>;
- };
- };
diff --git
a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
new file mode 100644
index ..05c52390269e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/panel-simple-dsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple DSI panels with a single power-supply
+
+maintainers:
+ - Thierry Reding
+ - Sam Ravnborg
+
+description: |
+ This binding file is a collection of the DSI panels that
+ requires only a single power-supply.
+ There are optionally a backlight and an enable GPIO.
+ The panel may use an OF graph binding for the association to the display,
+ or it may be a direct child node of the display.
+
+ If the panel is more advanced a dedicated binding file is required.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+
+ compatible:
+enum:
+# compatible must be listed in alphabetical order, ordered by compatible.
+# The description in the comment is mandatory for each compatible.
+
+# Panasonic 10" WUXGA TFT LCD panel
+- panasonic,vvx10f034n00
+
+ reg:
+maxItems: 1
+description: DSI virtual channel
+
+ backlight: true
+ enable-gpios: true
+ port: true
+ power-supply: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - power-supply
+ - reg
+
+examples:
+ - |
+mdss_dsi@fd922800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+compatible = "panasonic,vvx10f034n00";
+reg = <0>;
+power-supply = <&vcc_lcd_reg>;
+
+port {
+ panel: endpoint {
+remote-endpoint = <;
+ };
+};
+ };
+};
--
2.20.1
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Re: [PATCH v3 3/9] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation
On 02-01-2020 14:48, Jani Nikula wrote:
On Mon, 30 Dec 2019, Animesh Manna wrote:
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
I guess I'm still asking why you think this is better located in
intel_dp.c than intel_dp_link_training.c, as the function has been moved
once in the other direction already to split out stuff from intel_dp.c
and to make the file smaller. Even the file name suggests it should
really be in intel_dp_link_training.c, right?
Just a thought, can we change the name to "intel_dp_link_config.c" from
"intel_dp_link_training.c" which will provide little wider scope
and all the function playing with link configuration can be under it and also
exposed through header file.
AFAIK, processing phy compliance request always do not need link training. I
understood link training is very specific process consisting of clock recovery
+ channel eq.
So I am afraid of exposing intel_get_adjust_train() from
intel_dp_link_training.c which is not only specific to link-training. Need your
suggestion.
Regards,
Animesh
BR,
Jani.
No functional change.
v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for link_status. (Ville)
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 34 ++
drivers/gpu/drm/i915/display/intel_dp.h | 4 +++
.../drm/i915/display/intel_dp_link_training.c | 36 ++-
3 files changed, 40 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 991f343579ef..2a27ee106089 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4110,6 +4110,40 @@ ivb_cpu_edp_signal_levels(u8 train_set)
}
}
+void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ u8 v = 0;
+ u8 p = 0;
+ int lane;
+ u8 voltage_max;
+ u8 preemph_max;
+
+ for (lane = 0; lane < intel_dp->lane_count; lane++) {
+ u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
+ lane);
+ u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
+ lane);
+
+ if (this_v > v)
+ v = this_v;
+ if (this_p > p)
+ p = this_p;
+ }
+
+ voltage_max = intel_dp_voltage_max(intel_dp);
+ if (v >= voltage_max)
+ v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
+
+ preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
+ if (p >= preemph_max)
+ p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+ for (lane = 0; lane < 4; lane++)
+ intel_dp->train_set[lane] = v | p;
+}
+
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp)
{
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
b/drivers/gpu/drm/i915/display/intel_dp.h
index 3da166054788..83eadc87af26 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -9,6 +9,7 @@
#include
#include
+#include
#include "i915_reg.h"
@@ -91,6 +92,9 @@ void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
u8 dp_train_pat);
void
+intel_dp_get_adjust_train(struct intel_dp *intel_dp,
+ const u8 link_status[DP_LINK_STATUS_SIZE]);
+void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
u8
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..e8ff9e279800 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -34,38 +34,6 @@ intel_dp_dump_link_status(const u8
link_status[DP_LINK_STATUS_SIZE])
link_status[3], link_status[4], link_status[5]);
}
-static void
-intel_get_adjust_train(struct intel_dp *intel_dp,
- const u8 link_status[DP_LINK_STATUS_SIZE])
-{
- u8 v = 0;
- u8 p = 0;
- int lane;
- u8 voltage_max;
- u8 preemph_max;
-
- for (lane = 0; lane < intel_dp->lane_count; lane++) {
- u8 this_v = drm_dp_get_adjust_request_voltage(link_status,
lane);
- u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status,
lane);
-
- if (this_v > v)
- v = this_v;
- if (this_p > p)
- p = this_p;
- }
-
- voltage_max = intel_dp_voltage_m
Re: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40
On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> TCON LCD0, LCD1 in allwinner R40, are used for managing
> LCD interfaces like RGB, LVDS and DSI.
>
> Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> tcon top.
>
> Add support for it, in tcon driver.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v3:
> - none
>
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index fad72799b8df..69611d38c844 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks
> sun8i_a83t_tv_quirks = {
> .has_channel_1 = true,
> };
>
> +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = {
> + .supports_lvds = true,
> + .has_channel_0 = true,
> + /* TODO Need to support TCON output muxing via GPIO pins */
> + .set_mux= sun8i_r40_tcon_tv_set_mux,
What is this muking about? And why is it a TODO?
Maxime
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Re: [PATCH v3 3/9] ARM: dts: sun8i: r40: Use tcon top clock index macros
On Tue, Dec 31, 2019 at 06:35:22PM +0530, Jagan Teki wrote: > tcon_tv0, tcon_tv1 nodes have a clock names of tcon-ch0, > tcon-ch1 which are referring tcon_top clocks via index > numbers like 0, 1 with CLK_TCON_TV0 and CLK_TCON_TV1 > respectively. > > Use the macro in place of index numbers, for more code > readability. > > Signed-off-by: Jagan Teki > Reviewed-by: Chen-Yu Tsai Applied, thanks Maxime signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v6, 09/14] drm/mediatek: add connection from OVL_2L0 to RDMA0
this patch add add connection from OVL_2L0 to RDMA0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index bb41594..a6fed7b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -33,6 +33,12 @@
#define DISP_REG_CONFIG_DSI_SEL0x050
#define DISP_REG_CONFIG_DPI_SEL0x064
+#define MT8183_DISP_OVL0_2L_MOUT_EN0xf04
+#define MT8183_DISP_PATH0_SEL_IN 0xf24
+
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+
#define MT2701_DISP_MUTEX0_MOD00x2c
#define MT2701_DISP_MUTEX0_SOF00x30
@@ -308,6 +314,10 @@ static unsigned int mtk_ddp_mout_en(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
*addr = data->ovl0_mout_en;
value = OVL0_MOUT_EN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 &&
+ next == DDP_COMPONENT_RDMA0) {
+ *addr = MT8183_DISP_OVL0_2L_MOUT_EN;
+ value = OVL0_2L_MOUT_EN_DISP_PATH0;
} else {
value = 0;
}
@@ -373,6 +383,10 @@ static unsigned int mtk_ddp_sel_in(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DPI_SEL;
value = DPI_SEL_IN_BLS;
+ } else if (cur == DDP_COMPONENT_OVL_2L0 &&
+next == DDP_COMPONENT_RDMA0) {
+ *addr = MT8183_DISP_PATH0_SEL_IN;
+ value = DISP_PATH0_SEL_IN_OVL0_2L;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH 03/10] fbdev: s1d13xxxfb: use resource_size
Use resource_size rather than a verbose computation on
the end and start fields.
The semantic patch that makes these changes is as follows:
(http://coccinelle.lip6.fr/)
@@ struct resource ptr; @@
- (ptr.end - ptr.start + 1)
+ resource_size(&ptr)
Signed-off-by: Julia Lawall
---
drivers/video/fbdev/s1d13xxxfb.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/video/fbdev/s1d13xxxfb.c b/drivers/video/fbdev/s1d13xxxfb.c
index 8048499e398d..eaea8c373753 100644
--- a/drivers/video/fbdev/s1d13xxxfb.c
+++ b/drivers/video/fbdev/s1d13xxxfb.c
@@ -746,9 +746,9 @@ s1d13xxxfb_remove(struct platform_device *pdev)
}
release_mem_region(pdev->resource[0].start,
- pdev->resource[0].end - pdev->resource[0].start +1);
+ resource_size(&pdev->resource[0]));
release_mem_region(pdev->resource[1].start,
- pdev->resource[1].end - pdev->resource[1].start +1);
+ resource_size(&pdev->resource[1]));
return 0;
}
@@ -788,14 +788,14 @@ static int s1d13xxxfb_probe(struct platform_device *pdev)
}
if (!request_mem_region(pdev->resource[0].start,
- pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb
mem")) {
+ resource_size(&pdev->resource[0]), "s1d13xxxfb mem")) {
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
}
if (!request_mem_region(pdev->resource[1].start,
- pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb
regs")) {
+ resource_size(&pdev->resource[1]), "s1d13xxxfb regs")) {
dev_dbg(&pdev->dev, "request_mem_region failed\n");
ret = -EBUSY;
goto bail;
@@ -810,7 +810,7 @@ static int s1d13xxxfb_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, info);
default_par = info->par;
default_par->regs = ioremap(pdev->resource[1].start,
- pdev->resource[1].end - pdev->resource[1].start +1);
+ resource_size(&pdev->resource[1]));
if (!default_par->regs) {
printk(KERN_ERR PFX "unable to map registers\n");
ret = -ENOMEM;
@@ -819,7 +819,7 @@ static int s1d13xxxfb_probe(struct platform_device *pdev)
info->pseudo_palette = default_par->pseudo_palette;
info->screen_base = ioremap(pdev->resource[0].start,
- pdev->resource[0].end - pdev->resource[0].start +1);
+ resource_size(&pdev->resource[0]));
if (!info->screen_base) {
printk(KERN_ERR PFX "unable to map framebuffer\n");
@@ -857,9 +857,9 @@ static int s1d13xxxfb_probe(struct platform_device *pdev)
info->fix = s1d13xxxfb_fix;
info->fix.mmio_start = pdev->resource[1].start;
- info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +
1;
+ info->fix.mmio_len = resource_size(&pdev->resource[1]);
info->fix.smem_start = pdev->resource[0].start;
- info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +
1;
+ info->fix.smem_len = resource_size(&pdev->resource[0]);
printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
default_par->regs, info->fix.smem_len / 1024, info->screen_base);
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[PATCH v6, 12/14] drm/mediatek: add connection from RDMA0 to DSI0
This patch add connection from RDMA0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 4cc432d..68dc060 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -42,6 +42,7 @@
#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
#define DITHER0_MOUT_IN_DSI0 BIT(0)
#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
+#define DSI0_SEL_IN_RDMA0 0x1
#define MT2701_DISP_MUTEX0_MOD00x2c
#define MT2701_DISP_MUTEX0_SOF00x30
@@ -398,6 +399,9 @@ static unsigned int mtk_ddp_sel_in(const struct
mtk_mmsys_reg_data *data,
next == DDP_COMPONENT_RDMA0) {
*addr = MT8183_DISP_PATH0_SEL_IN;
value = DISP_PATH0_SEL_IN_OVL0_2L;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) {
+ *addr = data->dsi0_sel_in;
+ value = DSI0_SEL_IN_RDMA0;
} else {
value = 0;
}
--
1.8.1.1.dirty
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Re: [PATCH v2] phy: Add DisplayPort configuration options
Hi,
On Tue, Dec 24, 2019 at 12:29:40PM +, Yuti Suresh Amonkar wrote:
> > -Original Message-
> > From: Maxime Ripard
> > Sent: Monday, December 23, 2019 22:49
> > To: Yuti Suresh Amonkar
> > Cc: linux-ker...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> > prane...@ti.com; tomi.valkei...@ti.com; jsa...@ti.com; Milind Parab
> > ; Swapnil Kashinath Jakhade
> >
> > Subject: Re: [PATCH v2] phy: Add DisplayPort configuration options
> >
> > EXTERNAL MAIL
> >
> >
> > Hi,
> >
> > Please note that I don't have access to the displayPort spec, so I'll only
> > comment on the content of that patch, not whether it's complete or not.
> >
> > On Mon, Dec 23, 2019 at 02:41:13PM +0100, Yuti Amonkar wrote:
> > > Allow DisplayPort PHYs to be configured through the generic functions
> > > through a custom structure added to the generic union.
> > > The configuration structure is used for reconfiguration of DisplayPort
> > > PHYs during link training operation.
> > >
> > > The parameters added here are the ones defined in the DisplayPort spec
> > > 1.4 which include link rate, number of lanes, voltage swing and
> > > pre-emphasis.
> > >
> > > Signed-off-by: Yuti Amonkar
> > > ---
> > >
> > > This patch was a part of [1] series earlier but we think that it needs
> > > to have a separate attention of the reviewers. Also as both [1] & [2]
> > > are dependent on this patch, our sincere request to reviewers to have
> > > a faster review of this patch.
> > >
> > > [1]
> > >
> > > https://lkml.org/lkml/2019/12/11/455
> > >
> > > [2]
> > >
> > > https://patchwork.kernel.org/cover/11271191/
> > >
> > > include/linux/phy/phy-dp.h | 95
> > ++
> > > include/linux/phy/phy.h| 4 ++
> > > 2 files changed, 99 insertions(+)
> > > create mode 100644 include/linux/phy/phy-dp.h
> > >
> > > diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
> > > new file mode 100644 index 000..18cad23
> > > --- /dev/null
> > > +++ b/include/linux/phy/phy-dp.h
> > > @@ -0,0 +1,95 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * Copyright (C) 2019 Cadence Design Systems Inc.
> > > + */
> > > +
> > > +#ifndef __PHY_DP_H_
> > > +#define __PHY_DP_H_
> > > +
> > > +#include
> > > +
> > > +/**
> > > + * struct phy_configure_opts_dp - DisplayPort PHY configuration set
> > > + *
> > > + * This structure is used to represent the configuration state of a
> > > + * DisplayPort phy.
> > > + */
> > > +struct phy_configure_opts_dp {
> > > + /**
> > > + * @link_rate:
> > > + *
> > > + * Link Rate, in Mb/s, of the main link.
> > > + *
> > > + * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100
> > Mb/s
> > > + */
> > > + unsigned int link_rate;
> > > +
> > > + /**
> > > + * @lanes:
> > > + *
> > > + * Number of active, consecutive, data lanes, starting from
> > > + * lane 0, used for the transmissions on main link.
> > > + *
> > > + * Allowed values: 1, 2, 4
> > > + */
> > > + unsigned int lanes;
> > > +
> > > + /**
> > > + * @voltage:
> > > + *
> > > + * Voltage swing levels, as specified by DisplayPort specification,
> > > + * to be used by particular lanes. One value per lane.
> > > + * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
> > > + *
> > > + * Maximum value: 3
> > > + */
> > > + unsigned int voltage[4];
> > > +
> > > + /**
> > > + * @pre:
> > > + *
> > > + * Pre-emphasis levels, as specified by DisplayPort specification, to be
> > > + * used by particular lanes. One value per lane.
> > > + *
> > > + * Maximum value: 3
> > > + */
> > > + unsigned int pre[4];
> > > +
> > > + /**
> > > + * @ssc:
> > > + *
> > > + * Flag indicating, whether or not to enable spread-spectrum
> > clocking.
> > > + *
> > > + */
> > > + u8 ssc : 1;
> > > +
> > > + /**
> > > + * @set_rate:
> > > + *
> > > + * Flag indicating, whether or not reconfigure link rate and SSC to
> > > + * requested values.
> > > + *
> > > + */
> > > + u8 set_rate : 1;
> > > +
> > > + /**
> > > + * @set_lanes:
> > > + *
> > > + * Flag indicating, whether or not reconfigure lane count to
> > > + * requested value.
> > > + *
> > > + */
> > > + u8 set_lanes : 1;
> > > +
> > > + /**
> > > + * @set_voltages:
> > > + *
> > > + * Flag indicating, whether or not reconfigure voltage swing
> > > + * and pre-emphasis to requested values. Only lanes specified
> > > + * by "lanes" parameter will be affected.
> > > + *
> > > + */
> > > + u8 set_voltages : 1;
> >
> > I'm not quite sure what these flags are supposed to be doing, or what use-
> > cases they cover. The current API is using validate to make sure that we can
> > have a handshake between the caller and its PHY and must never apply the
> > configuration, and configure must always apply the configuration. These
> > flags look redundant.
> >
> > Maxime
>
> These flags are used to reconfigure the link during the link
> training procedure as described in DisplayPort spec. In this
> proced
[PATCH v6, 10/14] drm/mediatek: add connection from OVL_2L1 to RDMA1
This patch add connection from OVL_2L1 to RDMA1
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index a6fed7b..2b10d2d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -34,9 +34,11 @@
#define DISP_REG_CONFIG_DPI_SEL0x064
#define MT8183_DISP_OVL0_2L_MOUT_EN0xf04
+#define MT8183_DISP_OVL1_2L_MOUT_EN0xf08
#define MT8183_DISP_PATH0_SEL_IN 0xf24
#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
#define MT2701_DISP_MUTEX0_MOD00x2c
@@ -318,6 +320,10 @@ static unsigned int mtk_ddp_mout_en(const struct
mtk_mmsys_reg_data *data,
next == DDP_COMPONENT_RDMA0) {
*addr = MT8183_DISP_OVL0_2L_MOUT_EN;
value = OVL0_2L_MOUT_EN_DISP_PATH0;
+ } else if (cur == DDP_COMPONENT_OVL_2L1 &&
+ next == DDP_COMPONENT_RDMA1) {
+ *addr = MT8183_DISP_OVL1_2L_MOUT_EN;
+ value = OVL1_2L_MOUT_EN_RDMA1;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH v6, 08/14] drm/mediatek: add connection from RDMA1 to DSI0
This patch add connection from RDMA1 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 31a0650..bb41594 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -176,6 +176,7 @@ struct mtk_mmsys_reg_data {
u32 rdma0_sout_color0;
u32 rdma1_sout_sel_in;
u32 rdma1_sout_dpi0;
+ u32 rdma1_sout_dsi0;
u32 dpi0_sel_in;
u32 dpi0_sel_in_rdma1;
u32 dsi0_sel_in;
@@ -440,6 +441,9 @@ static unsigned int mtk_ddp_sout_sel(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
*addr = data->rdma0_sout_sel_in;
value = data->rdma0_sout_color0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = data->rdma1_sout_sel_in;
+ value = data->rdma1_sout_dsi0;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH v6, 05/14] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
rdma only has single output, but no multi output,
all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90 +-
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index ea0ce32..990021d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -300,51 +300,6 @@ static unsigned int mtk_ddp_mout_en(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = data->rdma1_sout_sel_in;
- value = data->rdma1_sout_dpi0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
@@ -430,6 +385,51 @@ static unsigned int mtk_ddp_sout_sel(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_OUT_SEL;
value = BLS_TO_DPI_RDMA1_TO_DSI;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next
[PATCH] drm/omapdrm: use BUG_ON macro for error debugging.
Since the if statement only checks for the value of the `id` variable,
it can be replaced by the more concise BUG_ON() macro for error
reporting.
Issue found using coccinelle.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 413dbdd1771e..dbb90f2d2ccd 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -393,8 +393,7 @@ static void dispc_get_reg_field(struct dispc_device *dispc,
enum dispc_feat_reg_field id,
u8 *start, u8 *end)
{
- if (id >= dispc->feat->num_reg_fields)
- BUG();
+ BUG_ON(id >= dispc->feat->num_reg_fields);
*start = dispc->feat->reg_fields[id].start;
*end = dispc->feat->reg_fields[id].end;
--
2.17.1
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Re: [PATCH v6, 02/14] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in
On Thu, 2020-01-02 at 14:40 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 14:21 +0800, Yongqiang Niu wrote:
> > On Thu, 2020-01-02 at 14:02 +0800, CK Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > On Thu, 2020-01-02 at 13:39 +0800, Yongqiang Niu wrote:
> > > > On Thu, 2020-01-02 at 13:03 +0800, CK Hu wrote:
> > > > > Hi, Yongqiang:
> > > > >
> > > > > On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > > > > > move dsi/dpi select input into mtk_ddp_sel_in
> > > > > >
> > > > > > Signed-off-by: Yongqiang Niu
> > > > > > ---
> > > > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> > > > > > 1 file changed, 6 insertions(+), 4 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > > index 39700b9..91c9b19 100644
> > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > > > @@ -376,6 +376,12 @@ static unsigned int mtk_ddp_sel_in(enum
> > > > > > mtk_ddp_comp_id cur,
> > > > > > } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > > > DDP_COMPONENT_DSI0) {
> > > > > > *addr = DISP_REG_CONFIG_DSI_SEL;
> > > > > > value = DSI_SEL_IN_BLS;
> > > > > > + } else if (cur == DDP_COMPONENT_RDMA1 && next ==
> > > > > > DDP_COMPONENT_DSI0) {
> > > > > > + *addr = DISP_REG_CONFIG_DSI_SEL;
> > > > > > + value = DSI_SEL_IN_RDMA;
> > > > >
> > > > > In original code, this is set when cur == DDP_COMPONENT_BLS and next
> > > > > ==
> > > > > DDP_COMPONENT_DPI0. Why do you change the condition?
> > > > >
> > > > > Regards,
> > > > > CK
> > > >
> > > > if bls connect with dpi0, rdma1 should connect with dsi0, the condition
> > > > is same with before.
> > >
> > > You suggest that two crtcs are both enabled. If only one crtc is
> > > enabled, just one of these two would be set.
> > >
> > > Regards,
> > > CK
> >
> > OK, i will modify like this
> > else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DPI_SEL_IN_RDMA;
> > }
> > in mtk_ddp_sel_in.
> >
> > don't set DISP_REG_CONFIG_DPI_SEL to DPI_SEL_IN_BLS anymore, because
> > DPI_SEL_IN_BLS is zero, it is same with hardware default setting.
>
> In Bibby's case, there is only the path from BLS to DPI0 and has no path
> from RDMA1 to DSI0, but it need to set these two register. Maybe its
> setting is just for some SoC, so you may use the compatible name to
> judge how to set this two register.
>
> Regards,
> CK
>
it the original use case, if bls->dpi0, it set 3 register,
DISP_REG_CONFIG_DPI_SEL set to DPI_SEL_IN_BLS ,and this is
0, so this is useless setting.
then are only 2 useful setting.
in this patch i have upload, i keep DISP_REG_CONFIG_OUT_SEL
still in mtk_ddp_sout_sel.
and only move DISP_REG_CONFIG_DSI_SEL into mtk_ddp_sel_in.
i suppose this is enough for this use case.
and no need compatible name to control this.
please double confirm.
and there will more and more SOC upstream in the future.
these function will be more complex.
there should be coding one more suitable function to
handle these connection
> > >
> > > > >
> > > > > > + } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > > > DDP_COMPONENT_DPI0) {
> > > > > > + *addr = DISP_REG_CONFIG_DPI_SEL;
> > > > > > + value = DPI_SEL_IN_BLS;
> > > > > > } else {
> > > > > > value = 0;
> > > > > > }
> > > > > > @@ -393,10 +399,6 @@ static void mtk_ddp_sout_sel(struct regmap
> > > > > > *config_regs,
> > > > > > } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > > > DDP_COMPONENT_DPI0) {
> > > > > > regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
> > > > > > BLS_TO_DPI_RDMA1_TO_DSI);
> > > > > > - regmap_write(config_regs, DISP_REG_CONFIG_DSI_SEL,
> > > > > > - DSI_SEL_IN_RDMA);
> > > > > > - regmap_write(config_regs, DISP_REG_CONFIG_DPI_SEL,
> > > > > > - DPI_SEL_IN_BLS);
> > > > > > }
> > > > > > }
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >
> >
> >
>
>
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[PATCH v6, 00/14] add drm support for MT8183
This series are based on 5.5-rc1 and provid 14 patch to support mediatek SOC MT8183 Change since v5 - fix reviewed issue in v5 Change since v4 - fix reviewed issue in v4 Change since v3 - fix reviewed issue in v3 - fix type error in v3 - fix conflict with iommu patch Change since v2 - fix reviewed issue in v2 - add mutex node into dts file Changes since v1: - fix reviewed issue in v1 - add dts for mt8183 display nodes - adjust display clock control flow in patch 22 - add vmap support for mediatek drm in patch 23 - fix page offset issue for mmap function in patch 24 - enable allow_fb_modifiers for mediatek drm in patch 25 Yongqiang Niu (14): arm64: dts: add display nodes for mt8183 drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in drm/mediatek: make sout select function format same with select input drm/mediatek: add mmsys private data for ddp path config drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel drm/mediatek: add connection from OVL0 to OVL_2L0 drm/mediatek: add connection from RDMA0 to COLOR0 drm/mediatek: add connection from RDMA1 to DSI0 drm/mediatek: add connection from OVL_2L0 to RDMA0 drm/mediatek: add connection from OVL_2L1 to RDMA1 drm/mediatek: add connection from DITHER0 to DSI0 drm/mediatek: add connection from RDMA0 to DSI0 drm/mediatek: add fifo_size into rdma private data drm/mediatek: add support for mediatek SOC MT8183 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 103 +++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 291 +++ drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 7 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 51 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 + 8 files changed, 434 insertions(+), 70 deletions(-) -- 1.8.1.1.dirty ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 00/10] use resource_size
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes these changes is as follows: (http://coccinelle.lip6.fr/) @@ struct resource ptr; @@ - ((ptr.end) - (ptr.start) + 1) + resource_size(&ptr) @@ struct resource *ptr; @@ - ((ptr->end) - (ptr->start) + 1) + resource_size(ptr) @@ struct resource ptr; @@ - ((ptr.end) + 1 - (ptr.start)) + resource_size(&ptr) @@ struct resource *ptr; @@ - ((ptr->end) + 1 - (ptr->start)) + resource_size(ptr) --- arch/mips/kernel/setup.c |6 ++ arch/powerpc/platforms/83xx/km83xx.c |2 +- arch/powerpc/platforms/powernv/pci-ioda.c |4 ++-- arch/x86/kernel/crash.c |2 +- drivers/net/ethernet/freescale/fman/mac.c |4 ++-- drivers/usb/gadget/udc/omap_udc.c |6 +++--- drivers/video/fbdev/cg14.c|3 +-- drivers/video/fbdev/s1d13xxxfb.c | 16 sound/drivers/ml403-ac97cr.c |4 +--- sound/soc/sof/imx/imx8.c |3 +-- 10 files changed, 22 insertions(+), 28 deletions(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 07/10] video: fbdev: use resource_size
Use resource_size rather than a verbose computation on the end and start fields. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) @@ struct resource ptr; @@ - (ptr.end - ptr.start + 1) + resource_size(&ptr) Signed-off-by: Julia Lawall --- drivers/video/fbdev/cg14.c |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/video/fbdev/cg14.c b/drivers/video/fbdev/cg14.c index a620b51cf7d0..6a745eb46ca1 100644 --- a/drivers/video/fbdev/cg14.c +++ b/drivers/video/fbdev/cg14.c @@ -509,8 +509,7 @@ static int cg14_probe(struct platform_device *op) if (!par->regs || !par->clut || !par->cursor || !info->screen_base) goto out_unmap_regs; - is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) == - (8 * 1024 * 1024)); + is_8mb = (resource_size(&op->resource[1]) == (8 * 1024 * 1024)); BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map)); ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 2/2] drm/sun4i: Use CRTC size instead of PRIMARY plane size as mixer frame.
Hi!
Dne sreda, 01. januar 2020 ob 21:47:50 CET je
roman.stratiie...@globallogic.com napisal(a):
> From: Roman Stratiienko
>
> According to DRM documentation the only difference between PRIMARY
> and OVERLAY plane is that each CRTC must have PRIMARY plane and
> OVERLAY are optional.
>
> Allow PRIMARY plane to have dimension different from full-screen.
>
> Fixes: 5bb5f5dafa1a ("drm/sun4i: Reorganize UI layer code in DE2")
> Signed-off-by: Roman Stratiienko
This looks great now.
Reviewed-by: Jernej Skrabec
What happened to other patches in the series? It would be nice to have a cover
letter for such cases, where you can explain reasons for dropped patches.
Best regards,
Jernej
> ---
> v2:
> - Split commit in 2 parts
> - Add Fixes line to the commit message
>
> v3:
> - Address review comments of v2 + removed 3 local varibles
> - Change 'Fixes' line
>
> Since I've put more changes from my side, please review/sign again.
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c| 28
> drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 30 --
> 2 files changed, 28 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 8b803eb903b8..658cf442c121
> 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -257,6 +257,33 @@ const struct de2_fmt_info *sun8i_mixer_format_info(u32
> format) return NULL;
> }
>
> +static void sun8i_mode_set(struct sunxi_engine *engine,
> +struct drm_display_mode *mode)
> +{
> + u32 size = SUN8I_MIXER_SIZE(mode->crtc_hdisplay, mode-
>crtc_vdisplay);
> + struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
> + u32 bld_base = sun8i_blender_base(mixer);
> + u32 val;
> +
> + DRM_DEBUG_DRIVER("Mode change, updating global size W: %u H: %u\n",
> + mode->crtc_hdisplay, mode->crtc_vdisplay);
> + regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size);
> + regmap_write(mixer->engine.regs,
> + SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
> + else
> + val = 0;
> +
> + regmap_update_bits(mixer->engine.regs,
> +SUN8I_MIXER_BLEND_OUTCTL(bld_base),
> +SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
> +val);
> + DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
> + val ? "on" : "off");
> +}
> +
> static void sun8i_mixer_commit(struct sunxi_engine *engine)
> {
> DRM_DEBUG_DRIVER("Committing changes\n");
> @@ -310,6 +337,7 @@ static struct drm_plane **sun8i_layers_init(struct
> drm_device *drm, static const struct sunxi_engine_ops sun8i_engine_ops = {
> .commit = sun8i_mixer_commit,
> .layers_init= sun8i_layers_init,
> + .mode_set = sun8i_mode_set,
> };
>
> static struct regmap_config sun8i_mixer_regmap_config = {
> diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
> b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 4343ea9f8cf8..f01ac55191f1
> 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
> @@ -120,36 +120,6 @@ static int sun8i_ui_layer_update_coord(struct
> sun8i_mixer *mixer, int channel, insize = SUN8I_MIXER_SIZE(src_w, src_h);
> outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
>
> - if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
> - bool interlaced = false;
> - u32 val;
> -
> - DRM_DEBUG_DRIVER("Primary layer, updating global size
W: %u H: %u\n",
> - dst_w, dst_h);
> - regmap_write(mixer->engine.regs,
> - SUN8I_MIXER_GLOBAL_SIZE,
> - outsize);
> - regmap_write(mixer->engine.regs,
> - SUN8I_MIXER_BLEND_OUTSIZE(bld_base),
outsize);
> -
> - if (state->crtc)
> - interlaced = state->crtc->state-
>adjusted_mode.flags
> - & DRM_MODE_FLAG_INTERLACE;
> -
> - if (interlaced)
> - val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
> - else
> - val = 0;
> -
> - regmap_update_bits(mixer->engine.regs,
> -
SUN8I_MIXER_BLEND_OUTCTL(bld_base),
> -
SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
> -val);
> -
> - DRM_DEBUG_DRIVER("Switching display mixer interlaced
mode %s\n",
> - interlaced ? "on" : "off");
> - }
> -
> /* Set height and width */
> DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
>state->src.x1 >> 16, state->src.y1 >> 16);
___
[PATCH v6, 13/14] drm/mediatek: add fifo_size into rdma private data
the fifo size of rdma in mt8183 is different.
rdma0 fifo size is 5k
rdma1 fifo size is 2k
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 405afef..691480b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -62,6 +62,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+ u32 fifo_size;
};
static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp,
unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+ u32 rdma_fifo_size;
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xf, height);
+ if (rdma->fifo_size)
+ rdma_fifo_size = rdma->fifo_size;
+ else
+ rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
+
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
@@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp,
unsigned int width,
*/
threshold = width * height * vrefresh * 4 * 7 / 100;
reg = RDMA_FIFO_UNDERFLOW_EN |
- RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
+ RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}
@@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device
*pdev)
return comp_id;
}
+ if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) {
+ ret = of_property_read_u32(dev->of_node,
+ "mediatek,rdma_fifo_size",
+ &priv->fifo_size);
+ if (ret) {
+ dev_err(dev, "Failed to get rdma fifo size\n");
+ return ret;
+ }
+
+ priv->fifo_size *= SZ_1K;
+ }
+
ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
&mtk_disp_rdma_funcs);
if (ret) {
--
1.8.1.1.dirty
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Re: [PATCH v6, 13/14] drm/mediatek: add fifo_size into rdma private data
On Thu, 2020-01-02 at 13:20 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > the fifo size of rdma in mt8183 is different.
> > rdma0 fifo size is 5k
> > rdma1 fifo size is 2k
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 21 -
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > index 405afef..691480b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > @@ -62,6 +62,7 @@ struct mtk_disp_rdma {
> > struct mtk_ddp_comp ddp_comp;
> > struct drm_crtc *crtc;
> > const struct mtk_disp_rdma_data *data;
> > + u32 fifo_size;
> > };
> >
> > static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> > @@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp
> > *comp, unsigned int width,
> > unsigned int threshold;
> > unsigned int reg;
> > struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> > + u32 rdma_fifo_size;
> >
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xf, height);
> >
> > + if (rdma->fifo_size)
> > + rdma_fifo_size = rdma->fifo_size;
> > + else
> > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
> > +
> > /*
> > * Enable FIFO underflow since DSI and DPI can't be blocked.
> > * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> > @@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp,
> > unsigned int width,
> > */
> > threshold = width * height * vrefresh * 4 * 7 / 100;
> > reg = RDMA_FIFO_UNDERFLOW_EN |
> > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
> > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> > writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> > }
> > @@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device
> > *pdev)
> > return comp_id;
> > }
> >
> > + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) {
>
> "mediatek,rdma_fifo_size" does not exists in binding document.
>
> > + ret = of_property_read_u32(dev->of_node,
> > + "mediatek,rdma_fifo_size",
> > + &priv->fifo_size);
> > + if (ret) {
> > + dev_err(dev, "Failed to get rdma fifo size\n");
> > + return ret;
> > + }
> > +
> > + priv->fifo_size *= SZ_1K;
>
> Why not define fifo_size in 'bytes' ?
>
> Regards,
> CK
this is align the definition of fifo_size in mtk_disp_rdma_data, it is
SZ_1K,
and the macro RDMA_FIFO_PSEUDO_SIZE calculated with SZ_1K
>
> > + }
> > +
> > ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
> > &mtk_disp_rdma_funcs);
> > if (ret) {
>
>
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[PATCH v3 1/2] drm/sun4i: Add mode_set callback to the engine
From: Roman Stratiienko
Create callback to update engine's registers on mode change.
Signed-off-by: Roman Stratiienko
Reviewed-by: Jernej Skrabec
---
v2:
- Split commit in 2 parts.
- Add description to mode_set callback
- Dropped 1 line from sun4i_crtc_mode_set_nofb()
- Add struct drm_display_mode declaration (fix build warning)
v3:
- Pick reviewed-by line
- Add missing 'and' word to the mode_set callback description.
---
drivers/gpu/drm/sun4i/sun4i_crtc.c | 3 +++
drivers/gpu/drm/sun4i/sunxi_engine.h | 12
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c
b/drivers/gpu/drm/sun4i/sun4i_crtc.c
index 3a153648b369..f9c627d601c3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
@@ -141,6 +141,9 @@ static void sun4i_crtc_mode_set_nofb(struct drm_crtc *crtc)
struct sun4i_crtc *scrtc = drm_crtc_to_sun4i_crtc(crtc);
sun4i_tcon_mode_set(scrtc->tcon, encoder, mode);
+
+ if (scrtc->engine->ops->mode_set)
+ scrtc->engine->ops->mode_set(scrtc->engine, mode);
}
static const struct drm_crtc_helper_funcs sun4i_crtc_helper_funcs = {
diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h
b/drivers/gpu/drm/sun4i/sunxi_engine.h
index 548710a936d5..7faa844646ff 100644
--- a/drivers/gpu/drm/sun4i/sunxi_engine.h
+++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
@@ -9,6 +9,7 @@
struct drm_plane;
struct drm_device;
struct drm_crtc_state;
+struct drm_display_mode;
struct sunxi_engine;
@@ -108,6 +109,17 @@ struct sunxi_engine_ops {
* This function is optional.
*/
void (*vblank_quirk)(struct sunxi_engine *engine);
+
+ /**
+* @mode_set:
+*
+* This callback is used to update engine registers that
+* responsible for display frame size and other mode attributes.
+*
+* This function is optional.
+*/
+ void (*mode_set)(struct sunxi_engine *engine,
+struct drm_display_mode *mode);
};
/**
--
2.17.1
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Re: [PATCH v6, 02/14] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in
On Thu, 2020-01-02 at 14:02 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 13:39 +0800, Yongqiang Niu wrote:
> > On Thu, 2020-01-02 at 13:03 +0800, CK Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > > > move dsi/dpi select input into mtk_ddp_sel_in
> > > >
> > > > Signed-off-by: Yongqiang Niu
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> > > > 1 file changed, 6 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > index 39700b9..91c9b19 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > > > @@ -376,6 +376,12 @@ static unsigned int mtk_ddp_sel_in(enum
> > > > mtk_ddp_comp_id cur,
> > > > } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > DDP_COMPONENT_DSI0) {
> > > > *addr = DISP_REG_CONFIG_DSI_SEL;
> > > > value = DSI_SEL_IN_BLS;
> > > > + } else if (cur == DDP_COMPONENT_RDMA1 && next ==
> > > > DDP_COMPONENT_DSI0) {
> > > > + *addr = DISP_REG_CONFIG_DSI_SEL;
> > > > + value = DSI_SEL_IN_RDMA;
> > >
> > > In original code, this is set when cur == DDP_COMPONENT_BLS and next ==
> > > DDP_COMPONENT_DPI0. Why do you change the condition?
> > >
> > > Regards,
> > > CK
> >
> > if bls connect with dpi0, rdma1 should connect with dsi0, the condition
> > is same with before.
>
> You suggest that two crtcs are both enabled. If only one crtc is
> enabled, just one of these two would be set.
>
> Regards,
> CK
OK, i will modify like this
else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DSI_SEL;
value = DPI_SEL_IN_RDMA;
}
in mtk_ddp_sel_in.
don't set DISP_REG_CONFIG_DPI_SEL to DPI_SEL_IN_BLS anymore, because
DPI_SEL_IN_BLS is zero, it is same with hardware default setting.
>
> > >
> > > > + } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > DDP_COMPONENT_DPI0) {
> > > > + *addr = DISP_REG_CONFIG_DPI_SEL;
> > > > + value = DPI_SEL_IN_BLS;
> > > > } else {
> > > > value = 0;
> > > > }
> > > > @@ -393,10 +399,6 @@ static void mtk_ddp_sout_sel(struct regmap
> > > > *config_regs,
> > > > } else if (cur == DDP_COMPONENT_BLS && next ==
> > > > DDP_COMPONENT_DPI0) {
> > > > regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
> > > > BLS_TO_DPI_RDMA1_TO_DSI);
> > > > - regmap_write(config_regs, DISP_REG_CONFIG_DSI_SEL,
> > > > - DSI_SEL_IN_RDMA);
> > > > - regmap_write(config_regs, DISP_REG_CONFIG_DPI_SEL,
> > > > - DPI_SEL_IN_BLS);
> > > > }
> > > > }
> > > >
> > >
> > >
> >
> >
>
>
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[PATCH v6, 03/14] drm/mediatek: make sout select function format same with select input
there will be more sout case in the future,
make the sout function format same mtk_ddp_sel_in
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 91c9b19..f99f89a1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -389,17 +389,23 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id
cur,
return value;
}
-static void mtk_ddp_sout_sel(struct regmap *config_regs,
-enum mtk_ddp_comp_id cur,
-enum mtk_ddp_comp_id next)
+static unsigned int mtk_ddp_sout_sel(enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+unsigned int *addr)
{
+ unsigned int value;
+
if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
- regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
- BLS_TO_DSI_RDMA1_TO_DPI1);
+ *addr = DISP_REG_CONFIG_OUT_SEL;
+ value = BLS_TO_DSI_RDMA1_TO_DPI1;
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
- regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
- BLS_TO_DPI_RDMA1_TO_DSI);
+ *addr = DISP_REG_CONFIG_OUT_SEL;
+ value = BLS_TO_DPI_RDMA1_TO_DSI;
+ } else {
+ value = 0;
}
+
+ return value;
}
void mtk_ddp_add_comp_to_path(struct regmap *config_regs,
@@ -412,7 +418,9 @@ void mtk_ddp_add_comp_to_path(struct regmap *config_regs,
if (value)
regmap_update_bits(config_regs, addr, value, value);
- mtk_ddp_sout_sel(config_regs, cur, next);
+ value = mtk_ddp_sout_sel(cur, next, &addr);
+ if (value)
+ regmap_update_bits(config_regs, addr, value, value);
value = mtk_ddp_sel_in(cur, next, &addr);
if (value)
--
1.8.1.1.dirty
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[PATCH v6, 04/14] drm/mediatek: add mmsys private data for ddp path config
This patch add mmsys private data for ddp path config
all these register offset and value will be different in future SOC
add these define into mmsys private data
u32 ovl0_mout_en;
u32 rdma1_sout_sel_in;
u32 rdma1_sout_dsi0;
u32 dpi0_sel_in;
u32 dpi0_sel_in_rdma1;
u32 dsi0_sel_in;
u32 dsi0_sel_in_rdma1;
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 63 -
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 6
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 ++
5 files changed, 63 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index e47cf84..9aacbcf 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -44,6 +44,7 @@ struct mtk_drm_crtc {
boolpending_planes;
struct regmap *config_regs;
+ const struct mtk_mmsys_reg_data *mmsys_reg_data;
struct mtk_disp_mutex *mutex;
unsigned intddp_comp_nr;
struct mtk_ddp_comp **ddp_comp;
@@ -283,6 +284,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
*mtk_crtc)
DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
+mtk_crtc->mmsys_reg_data,
mtk_crtc->ddp_comp[i]->id,
mtk_crtc->ddp_comp[i + 1]->id);
mtk_disp_mutex_add_comp(mtk_crtc->mutex,
@@ -340,6 +342,7 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
*mtk_crtc)
mtk_disp_mutex_disable(mtk_crtc->mutex);
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
+ mtk_crtc->mmsys_reg_data,
mtk_crtc->ddp_comp[i]->id,
mtk_crtc->ddp_comp[i + 1]->id);
mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
@@ -649,6 +652,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
return -ENOMEM;
mtk_crtc->config_regs = priv->config_regs;
+ mtk_crtc->mmsys_reg_data = priv->data->reg_data;
mtk_crtc->ddp_comp_nr = path_len;
mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
sizeof(*mtk_crtc->ddp_comp),
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index f99f89a1..ea0ce32 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -168,6 +168,16 @@ struct mtk_ddp {
const struct mtk_ddp_data *data;
};
+struct mtk_mmsys_reg_data {
+ u32 ovl0_mout_en;
+ u32 rdma1_sout_sel_in;
+ u32 rdma1_sout_dpi0;
+ u32 dpi0_sel_in;
+ u32 dpi0_sel_in_rdma1;
+ u32 dsi0_sel_in;
+ u32 dsi0_sel_in_rdma1;
+};
+
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
[DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
@@ -246,17 +256,34 @@ struct mtk_ddp {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
};
-static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
+const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = {
+ .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN,
+ .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL,
+ .dsi0_sel_in_rdma1 = DSI_SEL_IN_RDMA,
+};
+
+const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = {
+ .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
+ .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
+ .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0,
+ .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN,
+ .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1,
+ .dsi0_sel_in = DISP_REG_CONFIG_DSIE_SEL_IN,
+ .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1,
+};
+
+static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
+ enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
unsigned int *addr)
{
unsigned int value;
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
- *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+ *addr = data->ovl0_mout_en;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
- *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+ *addr = d
Re: [PATCH v6, 04/14] drm/mediatek: add mmsys private data for ddp path config
On Thu, 2020-01-02 at 13:33 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > This patch add mmsys private data for ddp path config
> > all these register offset and value will be different in future SOC
> > add these define into mmsys private data
> > u32 ovl0_mout_en;
> > u32 rdma1_sout_sel_in;
> > u32 rdma1_sout_dsi0;
> > u32 dpi0_sel_in;
> > u32 dpi0_sel_in_rdma1;
> > u32 dsi0_sel_in;
> > u32 dsi0_sel_in_rdma1;
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4 +++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 63
> > -
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 6
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 ++
> > 5 files changed, 63 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index e47cf84..9aacbcf 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -44,6 +44,7 @@ struct mtk_drm_crtc {
> > boolpending_planes;
> >
> > struct regmap *config_regs;
> > + const struct mtk_mmsys_reg_data *mmsys_reg_data;
> > struct mtk_disp_mutex *mutex;
> > unsigned intddp_comp_nr;
> > struct mtk_ddp_comp **ddp_comp;
> > @@ -283,6 +284,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc
> > *mtk_crtc)
> > DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n");
> > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> > mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> > +mtk_crtc->mmsys_reg_data,
> > mtk_crtc->ddp_comp[i]->id,
> > mtk_crtc->ddp_comp[i + 1]->id);
> > mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> > @@ -340,6 +342,7 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc
> > *mtk_crtc)
> > mtk_disp_mutex_disable(mtk_crtc->mutex);
> > for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> > mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> > + mtk_crtc->mmsys_reg_data,
> > mtk_crtc->ddp_comp[i]->id,
> > mtk_crtc->ddp_comp[i + 1]->id);
> > mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
> > @@ -649,6 +652,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > return -ENOMEM;
> >
> > mtk_crtc->config_regs = priv->config_regs;
> > + mtk_crtc->mmsys_reg_data = priv->data->reg_data;
> > mtk_crtc->ddp_comp_nr = path_len;
> > mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
> > sizeof(*mtk_crtc->ddp_comp),
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index f99f89a1..ea0ce32 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -168,6 +168,16 @@ struct mtk_ddp {
> > const struct mtk_ddp_data *data;
> > };
> >
> > +struct mtk_mmsys_reg_data {
> > + u32 ovl0_mout_en;
> > + u32 rdma1_sout_sel_in;
> > + u32 rdma1_sout_dpi0;
> > + u32 dpi0_sel_in;
> > + u32 dpi0_sel_in_rdma1;
> > + u32 dsi0_sel_in;
> > + u32 dsi0_sel_in_rdma1;
>
> This patch looks like a combination of two patches. One is a bug fix
> that dsi0_sel_in and dsi0_sel_in_rdma1 are different in MT8173 and
> MT2701. And the other is that ovl0_mout_en, rdma1_sout_sel_in,
> rdma1_sout_dpi0, dpi0_sel_in, dpi0_sel_in_rdma1 are different in MT8183.
>
> Regards,
> CK
i will split this into more patches in next version
>
> > +};
> > +
> > static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
> > [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
> > @@ -246,17 +256,34 @@ struct mtk_ddp {
> > .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> > };
> >
> > -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > +const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = {
> > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN,
> > + .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL,
> > + .dsi0_sel_in_rdma1 = DSI_SEL_IN_RDMA,
> > +};
> > +
> > +const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = {
> > + .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
> > + .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
> > + .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0,
> > + .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN,
> > + .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1,
> > + .dsi0_sel_in = DISP_REG_CONFIG_DSIE_SEL_IN,
> > + .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1,
> > +}
Re: KASAN: global-out-of-bounds Read in fbcon_get_font
syzbot has found a reproducer for the following crash on: HEAD commit:738d2902 Merge git://git.kernel.org/pub/scm/linux/kernel/g.. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=14e396c1e0 kernel config: https://syzkaller.appspot.com/x/.config?x=874bac2ff63646fa dashboard link: https://syzkaller.appspot.com/bug?extid=29d4ed7f3bdedf2aa2fd compiler: gcc (GCC) 9.0.0 20181231 (experimental) syz repro: https://syzkaller.appspot.com/x/repro.syz?x=17a0b866e0 C reproducer: https://syzkaller.appspot.com/x/repro.c?x=15fc963ee0 Bisection is inconclusive: the bug happens on the oldest tested release. bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=15b75532e0 final crash:https://syzkaller.appspot.com/x/report.txt?x=17b75532e0 console output: https://syzkaller.appspot.com/x/log.txt?x=13b75532e0 IMPORTANT: if you fix the bug, please add the following tag to the commit: Reported-by: syzbot+29d4ed7f3bdedf2aa...@syzkaller.appspotmail.com == BUG: KASAN: global-out-of-bounds in memcpy include/linux/string.h:380 [inline] BUG: KASAN: global-out-of-bounds in fbcon_get_font+0x2b2/0x5e0 drivers/video/fbdev/core/fbcon.c:2465 Read of size 32 at addr 88729e80 by task syz-executor334/10190 CPU: 0 PID: 10190 Comm: syz-executor334 Not tainted 5.5.0-rc4-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x197/0x210 lib/dump_stack.c:118 print_address_description.constprop.0.cold+0x5/0x30b mm/kasan/report.c:374 __kasan_report.cold+0x1b/0x41 mm/kasan/report.c:506 kasan_report+0x12/0x20 mm/kasan/common.c:639 check_memory_region_inline mm/kasan/generic.c:185 [inline] check_memory_region+0x134/0x1a0 mm/kasan/generic.c:192 memcpy+0x24/0x50 mm/kasan/common.c:125 memcpy include/linux/string.h:380 [inline] fbcon_get_font+0x2b2/0x5e0 drivers/video/fbdev/core/fbcon.c:2465 con_font_get drivers/tty/vt/vt.c:4446 [inline] con_font_op+0x20b/0x1270 drivers/tty/vt/vt.c:4605 vt_ioctl+0xd2e/0x26d0 drivers/tty/vt/vt_ioctl.c:913 tty_ioctl+0xa37/0x14f0 drivers/tty/tty_io.c:2660 vfs_ioctl fs/ioctl.c:47 [inline] file_ioctl fs/ioctl.c:545 [inline] do_vfs_ioctl+0x977/0x14e0 fs/ioctl.c:732 ksys_ioctl+0xab/0xd0 fs/ioctl.c:749 __do_sys_ioctl fs/ioctl.c:756 [inline] __se_sys_ioctl fs/ioctl.c:754 [inline] __x64_sys_ioctl+0x73/0xb0 fs/ioctl.c:754 do_syscall_64+0xfa/0x790 arch/x86/entry/common.c:294 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x4412d9 Code: e8 3c ad 02 00 48 83 c4 18 c3 0f 1f 80 00 00 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 0f 83 9b 09 fc ff c3 66 2e 0f 1f 84 00 00 00 00 RSP: 002b:7ffc49b97f18 EFLAGS: 0246 ORIG_RAX: 0010 RAX: ffda RBX: 004a2487 RCX: 004412d9 RDX: 2200 RSI: 4b60 RDI: 0004 RBP: 00018ac7 R08: 000d R09: 004002c8 R10: R11: 0246 R12: 00402100 R13: 00402190 R14: R15: The buggy address belongs to the variable: fontdata_8x16+0x1000/0x1120 Memory state around the buggy address: 88729d80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88729e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88729e80: fa fa fa fa 06 fa fa fa fa fa fa fa 05 fa fa fa ^ 88729f00: fa fa fa fa 06 fa fa fa fa fa fa fa 00 00 03 fa 88729f80: fa fa fa fa 00 00 00 00 00 00 00 00 00 00 00 00 == ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v6, 02/14] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in
On Thu, 2020-01-02 at 13:03 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2020-01-02 at 12:00 +0800, Yongqiang Niu wrote:
> > move dsi/dpi select input into mtk_ddp_sel_in
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> > 1 file changed, 6 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 39700b9..91c9b19 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -376,6 +376,12 @@ static unsigned int mtk_ddp_sel_in(enum
> > mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > *addr = DISP_REG_CONFIG_DSI_SEL;
> > value = DSI_SEL_IN_BLS;
> > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > + *addr = DISP_REG_CONFIG_DSI_SEL;
> > + value = DSI_SEL_IN_RDMA;
>
> In original code, this is set when cur == DDP_COMPONENT_BLS and next ==
> DDP_COMPONENT_DPI0. Why do you change the condition?
>
> Regards,
> CK
if bls connect with dpi0, rdma1 should connect with dsi0, the condition
is same with before.
>
> > + } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > + *addr = DISP_REG_CONFIG_DPI_SEL;
> > + value = DPI_SEL_IN_BLS;
> > } else {
> > value = 0;
> > }
> > @@ -393,10 +399,6 @@ static void mtk_ddp_sout_sel(struct regmap
> > *config_regs,
> > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
> > BLS_TO_DPI_RDMA1_TO_DSI);
> > - regmap_write(config_regs, DISP_REG_CONFIG_DSI_SEL,
> > - DSI_SEL_IN_RDMA);
> > - regmap_write(config_regs, DISP_REG_CONFIG_DPI_SEL,
> > - DPI_SEL_IN_BLS);
> > }
> > }
> >
>
>
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[PATCH v6, 01/14] arm64: dts: add display nodes for mt8183
This patch add display nodes for mt8183
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 103 +++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 91217e4f..de1ea00 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -30,6 +30,11 @@
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
+ ovl0 = &ovl0;
+ ovl_2l0 = &ovl_2l0;
+ ovl_2l1 = &ovl_2l1;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
};
cpus {
@@ -648,9 +653,107 @@
mmsys: syscon@1400 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
#clock-cells = <1>;
};
+ ovl0: ovl@14008000 {
+ compatible = "mediatek,mt8183-disp-ovl";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl_2l0: ovl@14009000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ mediatek,larb = <&larb0>;
+ };
+
+ ovl_2l1: ovl@1400a000 {
+ compatible = "mediatek,mt8183-disp-ovl-2l";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma@1400b000 {
+ compatible = "mediatek,mt8183-disp-rdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma_fifo_size = <5>;
+ };
+
+ rdma1: rdma@1400c000 {
+ compatible = "mediatek,mt8183-disp-rdma1";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma_fifo_size = <2>;
+ };
+
+ color0: color@1400e000 {
+ compatible = "mediatek,mt8183-disp-color",
+"mediatek,mt8173-disp-color";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ };
+
+ ccorr0: ccorr@1400f000 {
+ compatible = "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ };
+
+ aal0: aal@1401 {
+ compatible = "mediatek,mt8183-disp-aal",
+"mediatek,mt8173-disp-aal";
+ reg = <0 0x1401 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ };
+
+ gamma0: gamma@14011000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+"mediatek,mt8173-disp-gamma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = ;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ };
+
+ dither0: dither@14012000 {
+ compatible = "mediatek,mt8183-disp-dither";
+ reg = <0 0x14012000 0 0x1
[PATCH v6, 06/14] drm/mediatek: add connection from OVL0 to OVL_2L0
This patch add connection from OVL0 to OVL_2L0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 990021d..4f7182e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -137,6 +137,8 @@
#define DPI_SEL_IN_BLS 0x0
#define DSI_SEL_IN_RDMA0x1
+#define OVL0_MOUT_EN_OVL0_2L BIT(4)
+
struct mtk_disp_mutex {
int id;
bool claimed;
@@ -300,6 +302,9 @@ static unsigned int mtk_ddp_mout_en(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+ *addr = data->ovl0_mout_en;
+ value = OVL0_MOUT_EN_OVL0_2L;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH v6, 07/14] drm/mediatek: add connection from RDMA0 to COLOR0
This patch add connection from RDMA0 to COLOR0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 4f7182e..31a0650 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -172,6 +172,8 @@ struct mtk_ddp {
struct mtk_mmsys_reg_data {
u32 ovl0_mout_en;
+ u32 rdma0_sout_sel_in;
+ u32 rdma0_sout_color0;
u32 rdma1_sout_sel_in;
u32 rdma1_sout_dpi0;
u32 dpi0_sel_in;
@@ -435,6 +437,9 @@ static unsigned int mtk_ddp_sout_sel(const struct
mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
value = RDMA2_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+ *addr = data->rdma0_sout_sel_in;
+ value = data->rdma0_sout_color0;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH v6, 14/14] drm/mediatek: add support for mediatek SOC MT8183
This patch add support for mediatek SOC MT8183
1.ovl_2l share driver with ovl
2.rdma1 share drive with rdma0, but fifo size is different
3.add mt8183 mutex private data, and mmsys private data
4.add mt8183 main and external path module for crtc create
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69
drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 48 ++
5 files changed, 142 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4a55bb6..5ee175e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -423,11 +423,29 @@ static int mtk_disp_ovl_remove(struct platform_device
*pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = &mt8173_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = &mt8183_ovl_driver_data},
+ { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = &mt8183_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 691480b..a0223a5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -347,11 +347,17 @@ static int mtk_disp_rdma_remove(struct platform_device
*pdev)
.fifo_size = SZ_8K,
};
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = &mt8173_rdma_driver_data},
+ { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = &mt8183_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 68dc060..e484ef79 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -33,19 +33,31 @@
#define DISP_REG_CONFIG_DSI_SEL0x050
#define DISP_REG_CONFIG_DPI_SEL0x064
+#define MT8183_DISP_OVL0_MOUT_EN 0xf00
#define MT8183_DISP_OVL0_2L_MOUT_EN0xf04
#define MT8183_DISP_OVL1_2L_MOUT_EN0xf08
#define MT8183_DISP_DITHER0_MOUT_EN0xf0c
#define MT8183_DISP_PATH0_SEL_IN 0xf24
+#define MT8183_DISP_DSI0_SEL_IN0xf2c
+#define MT8183_DISP_DPI0_SEL_IN0xf30
+#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
#define DITHER0_MOUT_IN_DSI0 BIT(0)
#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
#define DSI0_SEL_IN_RDMA0 0x1
+#define MT8183_DSI0_SEL_IN_RDMA1 0x3
+#define MT8183_DPI0_SEL_IN_RDMA0 0x1
+#define MT8183_DPI0_SEL_IN_RDMA1 0x2
+#define MT8183_RDMA0_SOUT_COLOR0 0x1
+#define MT8183_RDMA1_SOUT_DSI0 0x1
#define MT2701_DISP_MUTEX0_MOD00x2c
#define MT2701_DISP_MUTEX0_SOF00x30
+#define MT8183_DISP_MUTEX0_MOD00x30
+#define MT8183_DISP_MUTEX0_SOF00x2c
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
@@ -56,6 +68,18 @@
#define INT_MUTEX BIT(1)
+#define MT8183_MUTEX_MOD_DISP_RDMA00
+#define MT8183_MUTEX_MOD_DISP_RDMA11
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
+#define MT8183_MUTEX_MOD_DISP_WD
[PATCH v6, 02/14] drm/mediatek: move dsi/dpi select input into mtk_ddp_sel_in
move dsi/dpi select input into mtk_ddp_sel_in
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 39700b9..91c9b19 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -376,6 +376,12 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id
cur,
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
*addr = DISP_REG_CONFIG_DSI_SEL;
value = DSI_SEL_IN_BLS;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+ *addr = DISP_REG_CONFIG_DSI_SEL;
+ value = DSI_SEL_IN_RDMA;
+ } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DPI_SEL;
+ value = DPI_SEL_IN_BLS;
} else {
value = 0;
}
@@ -393,10 +399,6 @@ static void mtk_ddp_sout_sel(struct regmap *config_regs,
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
regmap_write(config_regs, DISP_REG_CONFIG_OUT_SEL,
BLS_TO_DPI_RDMA1_TO_DSI);
- regmap_write(config_regs, DISP_REG_CONFIG_DSI_SEL,
- DSI_SEL_IN_RDMA);
- regmap_write(config_regs, DISP_REG_CONFIG_DPI_SEL,
- DPI_SEL_IN_BLS);
}
}
--
1.8.1.1.dirty
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[PATCH v3 2/2] drm/sun4i: Use CRTC size instead of PRIMARY plane size as mixer frame.
From: Roman Stratiienko
According to DRM documentation the only difference between PRIMARY
and OVERLAY plane is that each CRTC must have PRIMARY plane and
OVERLAY are optional.
Allow PRIMARY plane to have dimension different from full-screen.
Fixes: 5bb5f5dafa1a ("drm/sun4i: Reorganize UI layer code in DE2")
Signed-off-by: Roman Stratiienko
---
v2:
- Split commit in 2 parts
- Add Fixes line to the commit message
v3:
- Address review comments of v2 + removed 3 local varibles
- Change 'Fixes' line
Since I've put more changes from my side, please review/sign again.
---
drivers/gpu/drm/sun4i/sun8i_mixer.c| 28
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 30 --
2 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 8b803eb903b8..658cf442c121 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -257,6 +257,33 @@ const struct de2_fmt_info *sun8i_mixer_format_info(u32
format)
return NULL;
}
+static void sun8i_mode_set(struct sunxi_engine *engine,
+ struct drm_display_mode *mode)
+{
+ u32 size = SUN8I_MIXER_SIZE(mode->crtc_hdisplay, mode->crtc_vdisplay);
+ struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
+ u32 bld_base = sun8i_blender_base(mixer);
+ u32 val;
+
+ DRM_DEBUG_DRIVER("Mode change, updating global size W: %u H: %u\n",
+mode->crtc_hdisplay, mode->crtc_vdisplay);
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size);
+ regmap_write(mixer->engine.regs,
+SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
+ else
+ val = 0;
+
+ regmap_update_bits(mixer->engine.regs,
+ SUN8I_MIXER_BLEND_OUTCTL(bld_base),
+ SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
+ val);
+ DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
+val ? "on" : "off");
+}
+
static void sun8i_mixer_commit(struct sunxi_engine *engine)
{
DRM_DEBUG_DRIVER("Committing changes\n");
@@ -310,6 +337,7 @@ static struct drm_plane **sun8i_layers_init(struct
drm_device *drm,
static const struct sunxi_engine_ops sun8i_engine_ops = {
.commit = sun8i_mixer_commit,
.layers_init= sun8i_layers_init,
+ .mode_set = sun8i_mode_set,
};
static struct regmap_config sun8i_mixer_regmap_config = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
index 4343ea9f8cf8..f01ac55191f1 100644
--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
@@ -120,36 +120,6 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer
*mixer, int channel,
insize = SUN8I_MIXER_SIZE(src_w, src_h);
outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
- if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
- bool interlaced = false;
- u32 val;
-
- DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H:
%u\n",
-dst_w, dst_h);
- regmap_write(mixer->engine.regs,
-SUN8I_MIXER_GLOBAL_SIZE,
-outsize);
- regmap_write(mixer->engine.regs,
-SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize);
-
- if (state->crtc)
- interlaced = state->crtc->state->adjusted_mode.flags
- & DRM_MODE_FLAG_INTERLACE;
-
- if (interlaced)
- val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
- else
- val = 0;
-
- regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_BLEND_OUTCTL(bld_base),
- SUN8I_MIXER_BLEND_OUTCTL_INTERLACED,
- val);
-
- DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
-interlaced ? "on" : "off");
- }
-
/* Set height and width */
DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
state->src.x1 >> 16, state->src.y1 >> 16);
--
2.17.1
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[PATCH v6, 11/14] drm/mediatek: add connection from DITHER0 to DSI0
This patch add connection from DITHER0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 2b10d2d..4cc432d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -35,10 +35,12 @@
#define MT8183_DISP_OVL0_2L_MOUT_EN0xf04
#define MT8183_DISP_OVL1_2L_MOUT_EN0xf08
+#define MT8183_DISP_DITHER0_MOUT_EN0xf0c
#define MT8183_DISP_PATH0_SEL_IN 0xf24
#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
#define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define DITHER0_MOUT_IN_DSI0 BIT(0)
#define DISP_PATH0_SEL_IN_OVL0_2L 0x1
#define MT2701_DISP_MUTEX0_MOD00x2c
@@ -324,6 +326,9 @@ static unsigned int mtk_ddp_mout_en(const struct
mtk_mmsys_reg_data *data,
next == DDP_COMPONENT_RDMA1) {
*addr = MT8183_DISP_OVL1_2L_MOUT_EN;
value = OVL1_2L_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+ *addr = MT8183_DISP_DITHER0_MOUT_EN;
+ value = DITHER0_MOUT_IN_DSI0;
} else {
value = 0;
}
--
1.8.1.1.dirty
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[PATCH] drm/i915: remove boolean comparisons in conditionals.
Remove unnecessary comparisons to true/false in if statements.
Issues found by coccinelle.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9ba794cb9b4f..c065078b3be2 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1812,7 +1812,7 @@ void intel_ddi_set_vc_payload_alloc(const struct
intel_crtc_state *crtc_state,
u32 temp;
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
- if (state == true)
+ if (state)
temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
else
temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index aa515261cb9f..93140c75386a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4958,7 +4958,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
WARN_ON_ONCE(intel_dp->active_mst_links < 0);
bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
- if (bret == true) {
+ if (bret) {
/* check link status - esi[10] = 0x200c */
if (intel_dp->active_mst_links > 0 &&
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c
b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 47f5d87a938a..cff254c52f5e 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -3292,8 +3292,8 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv,
if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
goto err;
- if (intel_sdvo_output_setup(intel_sdvo,
- intel_sdvo->caps.output_flags) != true) {
+ if (!intel_sdvo_output_setup(intel_sdvo,
+intel_sdvo->caps.output_flags)) {
DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
SDVO_NAME(intel_sdvo));
/* Output_setup can leave behind connectors! */
--
2.17.1
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[PATCH v2 2/7] iommu/arm-smmu: Add domain attribute for QCOM system cache
From: Vivek Gautam
Add iommu domain attribute for using system cache aka last level
cache on QCOM SoCs by client drivers like GPU to set right
attributes for caching the hardware pagetables into the system cache.
Signed-off-by: Vivek Gautam
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-qcom.c | 10 ++
drivers/iommu/arm-smmu.c | 14 ++
drivers/iommu/arm-smmu.h | 1 +
include/linux/iommu.h | 1 +
4 files changed, 26 insertions(+)
diff --git a/drivers/iommu/arm-smmu-qcom.c b/drivers/iommu/arm-smmu-qcom.c
index 24c071c..d1d22df 100644
--- a/drivers/iommu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm-smmu-qcom.c
@@ -30,7 +30,17 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device
*smmu)
return ret;
}
+static int qcom_smmu_init_context(struct arm_smmu_domain *smmu_domain,
+ struct io_pgtable_cfg *pgtbl_cfg)
+{
+ if (smmu_domain->sys_cache)
+ pgtbl_cfg->coherent_walk = false;
+
+ return 0;
+}
+
static const struct arm_smmu_impl qcom_smmu_impl = {
+ .init_context = qcom_smmu_init_context,
.reset = qcom_sdm845_smmu500_reset,
};
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 4f7e0c0..055b548 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1466,6 +1466,9 @@ static int arm_smmu_domain_get_attr(struct iommu_domain
*domain,
case DOMAIN_ATTR_NESTING:
*(int *)data = (smmu_domain->stage ==
ARM_SMMU_DOMAIN_NESTED);
return 0;
+ case DOMAIN_ATTR_QCOM_SYS_CACHE:
+ *((int *)data) = smmu_domain->sys_cache;
+ return 0;
default:
return -ENODEV;
}
@@ -1506,6 +1509,17 @@ static int arm_smmu_domain_set_attr(struct iommu_domain
*domain,
else
smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
break;
+ case DOMAIN_ATTR_QCOM_SYS_CACHE:
+ if (smmu_domain->smmu) {
+ ret = -EPERM;
+ goto out_unlock;
+ }
+
+ if (*((int *)data))
+ smmu_domain->sys_cache = true;
+ else
+ smmu_domain->sys_cache = false;
+ break;
default:
ret = -ENODEV;
}
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index f57cdbe..8aeaaf0 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -322,6 +322,7 @@ struct arm_smmu_domain {
struct mutexinit_mutex; /* Protects smmu pointer */
spinlock_t cb_lock; /* Serialises ATS1* ops and
TLB syncs */
struct iommu_domain domain;
+ boolsys_cache;
};
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 0c60e75..bd61c60 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -127,6 +127,7 @@ enum iommu_attr {
DOMAIN_ATTR_FSL_PAMUV1,
DOMAIN_ATTR_NESTING,/* two stages of translation */
DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE,
+ DOMAIN_ATTR_QCOM_SYS_CACHE,
DOMAIN_ATTR_MAX,
};
--
1.9.1
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[PATCH v2 0/7] drm/msm/a6xx: System Cache Support
Some hardware variants contain a system level cache or the last level cache(llc). This cache is typically a large block which is shared by multiple clients on the SOC. GPU uses the system cache to cache both the GPU data buffers(like textures) as well the SMMU pagetables. This helps with improved render performance as well as lower power consumption by reducing the bus traffic to the system memory. The system cache architecture allows the cache to be split into slices which then be used by multiple SOC clients. This patch series is an effort to enable and use two of those slices perallocated for the GPU, one for the GPU data buffers and another for the GPU SMMU hardware pagetables. v2: Code reviews and rebased code on top of Jordan's split pagetables series To enable the system cache driver, add [1] to your stack if not already present. Please review. [1] https://lore.kernel.org/patchwork/patch/1165298/ Jordan Crouse (3): iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context drm/msm: Attach the IOMMU device during initialization drm/msm: Refactor address space initialization Sharat Masetty (3): drm: msm: a6xx: Properly free up the iommu objects drm/msm: rearrange the gpu_rmw() function drm/msm/a6xx: Add support for using system cache(LLC) Vivek Gautam (1): iommu/arm-smmu: Add domain attribute for QCOM system cache drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 16 drivers/gpu/drm/msm/adreno/a3xx_gpu.c| 1 + drivers/gpu/drm/msm/adreno/a4xx_gpu.c| 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c| 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c| 124 +++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h| 3 + drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 -- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 19 ++--- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 19 ++--- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 4 - drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 19 +++-- drivers/gpu/drm/msm/msm_drv.c| 8 ++ drivers/gpu/drm/msm/msm_drv.h| 9 +-- drivers/gpu/drm/msm/msm_gem_vma.c| 37 ++--- drivers/gpu/drm/msm/msm_gpu.c| 49 +--- drivers/gpu/drm/msm/msm_gpu.h| 9 +-- drivers/gpu/drm/msm/msm_gpummu.c | 7 -- drivers/gpu/drm/msm/msm_iommu.c | 22 +++--- drivers/gpu/drm/msm/msm_mmu.h| 5 +- drivers/iommu/arm-smmu-impl.c| 3 +- drivers/iommu/arm-smmu-qcom.c| 10 +++ drivers/iommu/arm-smmu.c | 25 +-- drivers/iommu/arm-smmu.h | 4 +- include/linux/iommu.h| 1 + 25 files changed, 269 insertions(+), 158 deletions(-) -- 1.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 1/7] iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
From: Jordan Crouse
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to
to modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu-impl.c | 3 ++-
drivers/iommu/arm-smmu.c | 11 ++-
drivers/iommu/arm-smmu.h | 3 ++-
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c
index b2fe72a..33ed682 100644
--- a/drivers/iommu/arm-smmu-impl.c
+++ b/drivers/iommu/arm-smmu-impl.c
@@ -68,7 +68,8 @@ static int cavium_cfg_probe(struct arm_smmu_device *smmu)
return 0;
}
-static int cavium_init_context(struct arm_smmu_domain *smmu_domain)
+static int cavium_init_context(struct arm_smmu_domain *smmu_domain,
+ struct io_pgtable_cfg *pgtbl_cfg)
{
struct cavium_smmu *cs = container_of(smmu_domain->smmu,
struct cavium_smmu, smmu);
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index eee48f9..4f7e0c0 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -758,11 +758,6 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
cfg->asid = cfg->cbndx;
smmu_domain->smmu = smmu;
- if (smmu->impl && smmu->impl->init_context) {
- ret = smmu->impl->init_context(smmu_domain);
- if (ret)
- goto out_unlock;
- }
smmu_domain->pgtbl_cfg = (struct io_pgtable_cfg) {
.pgsize_bitmap = smmu->pgsize_bitmap,
@@ -773,6 +768,12 @@ static int arm_smmu_init_domain_context(struct
iommu_domain *domain,
.iommu_dev = smmu->dev,
};
+ if (smmu->impl && smmu->impl->init_context) {
+ ret = smmu->impl->init_context(smmu_domain,
&smmu_domain->pgtbl_cfg);
+ if (ret)
+ goto out_unlock;
+ }
+
if (smmu_domain->non_strict)
smmu_domain->pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index b2df38c..f57cdbe 100644
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -335,7 +335,8 @@ struct arm_smmu_impl {
u64 val);
int (*cfg_probe)(struct arm_smmu_device *smmu);
int (*reset)(struct arm_smmu_device *smmu);
- int (*init_context)(struct arm_smmu_domain *smmu_domain);
+ int (*init_context)(struct arm_smmu_domain *smmu_domain,
+ struct io_pgtable_cfg *pgtbl_cfg);
};
static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
--
1.9.1
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[PATCH v2 7/7] drm/msm/a6xx: Add support for using system cache(LLC)
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for caching the GPU SMMU pagetables.
This patch talks to the core system cache driver to acquire the slice handles,
configure the SCID's to those slices and activates and deactivates the slices
upon GPU power collapse and restore.
Some support from the IOMMU driver is also needed to make use of the
system cache. IOMMU_QCOM_SYS_CACHE is a buffer protection flag which enables
caching GPU data buffers in the system cache with memory attributes such
as outer cacheable, read-allocate, write-allocate for buffers. The GPU
then has the ability to override a few cacheability parameters which it
does to override write-allocate to write-no-allocate as the GPU hardware
does not benefit much from it.
Similarly DOMAIN_ATTR_QCOM_SYS_CACHE is another domain level attribute
used by the IOMMU driver to set the right attributes to cache the hardware
pagetables into the system cache.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 100 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 3 +
drivers/gpu/drm/msm/msm_iommu.c | 3 +
drivers/gpu/drm/msm/msm_mmu.h | 4 ++
4 files changed, 110 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ab562f6..d15eb99f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -9,6 +9,8 @@
#include "a6xx_gmu.xml.h"
#include
+#include
+#include
#define GPU_PAS_ID 13
@@ -781,6 +783,81 @@ static void a6xx_bus_clear_pending_transactions(struct
adreno_gpu *adreno_gpu)
gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
}
+static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
+{
+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
+}
+
+static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
+{
+ return msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+}
+
+static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
+{
+ llcc_slice_deactivate(a6xx_gpu->llc_slice);
+ llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
+}
+
+static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
+{
+ u32 cntl1_regval = 0;
+
+ if (IS_ERR(a6xx_gpu->llc_mmio))
+ return;
+
+ if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
+ u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
+
+ gpu_scid &= 0x1f;
+ cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) |
+ (gpu_scid << 10) | (gpu_scid << 15) | (gpu_scid << 20);
+ }
+
+ if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
+ u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
+
+ gpuhtw_scid &= 0x1f;
+ cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
+ }
+
+ if (cntl1_regval) {
+ /*
+* Program the slice IDs for the various GPU blocks and GPU MMU
+* pagetables
+*/
+ a6xx_llc_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1,
+ cntl1_regval);
+
+ /*
+* Program cacheability overrides to not allocate cache lines on
+* a write miss
+*/
+ a6xx_llc_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0,
+ 0xF, 0x03);
+ }
+}
+
+static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
+{
+ llcc_slice_putd(a6xx_gpu->llc_slice);
+ llcc_slice_putd(a6xx_gpu->htw_llc_slice);
+}
+
+static void a6xx_llc_slices_init(struct platform_device *pdev,
+ struct a6xx_gpu *a6xx_gpu)
+{
+ a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");
+ if (IS_ERR(a6xx_gpu->llc_mmio))
+ return;
+
+ a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
+ a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
+
+ if (IS_ERR(a6xx_gpu->llc_slice) && IS_ERR(a6xx_gpu->htw_llc_slice))
+ a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
+}
+
static int a6xx_pm_resume(struct msm_gpu *gpu)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -795,6 +872,8 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
msm_gpu_resume_devfreq(gpu);
+ a6xx_llc_activate(a6xx_gpu);
+
return 0;
}
@@ -803,6 +882,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+ a6xx_llc_deactivate(a6xx_gpu);
+
devfreq_suspend_device(gpu->devfreq.devfreq);
/*
@@ -851,6 +932,7 @@ static void a6xx_destroy(struct msm_gpu *gpu)
drm_gem_object_put_unlocked(
[PATCH v2 3/7] drm/msm: Attach the IOMMU device during initialization
From: Jordan Crouse
Everywhere an IOMMU object is created by msm_gpu_create_address_space
the IOMMU device is attached immediately after. Instead of carrying around
the infrastructure to do the attach from the device specific code do it
directly in the msm_iommu_init() function. This gets it out of the way for
more aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 -
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 5 -
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 8
drivers/gpu/drm/msm/msm_gem_vma.c| 23 +++
drivers/gpu/drm/msm/msm_gpu.c| 11 +--
drivers/gpu/drm/msm/msm_gpummu.c | 7 ---
drivers/gpu/drm/msm/msm_iommu.c | 16 +++-
drivers/gpu/drm/msm/msm_mmu.h| 1 -
8 files changed, 27 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index ee93ba3..fdd9e2e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -736,7 +736,6 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
{
struct iommu_domain *domain;
struct msm_gem_address_space *aspace;
- int ret;
domain = iommu_domain_alloc(&platform_bus_type);
if (!domain)
@@ -752,14 +751,6 @@ static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
return PTR_ERR(aspace);
}
- ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
- ARRAY_SIZE(iommu_ports));
- if (ret) {
- DPU_ERROR("failed to attach iommu %d\n", ret);
- msm_gem_address_space_put(aspace);
- return ret;
- }
-
dpu_kms->base.aspace = aspace;
return 0;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 50711cc..c1c48df 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -523,11 +523,6 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
}
kms->aspace = aspace;
-
- ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
- ARRAY_SIZE(iommu_ports));
- if (ret)
- goto fail;
} else {
DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 91cd76a..2d66ae2 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -736,14 +736,6 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
}
kms->aspace = aspace;
-
- ret = aspace->mmu->funcs->attach(aspace->mmu, iommu_ports,
- ARRAY_SIZE(iommu_ports));
- if (ret) {
- DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu:
%d\n",
- ret);
- goto fail;
- }
} else {
DRM_DEV_INFO(&pdev->dev,
"no iommu, fallback to phys contig buffers for
scanout\n");
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c
b/drivers/gpu/drm/msm/msm_gem_vma.c
index 1af5354..91d993a 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -131,8 +131,8 @@ struct msm_gem_address_space *
const char *name)
{
struct msm_gem_address_space *aspace;
- u64 size = domain->geometry.aperture_end -
- domain->geometry.aperture_start;
+ u64 start = domain->geometry.aperture_start;
+ u64 size = domain->geometry.aperture_end - start;
aspace = kzalloc(sizeof(*aspace), GFP_KERNEL);
if (!aspace)
@@ -141,9 +141,18 @@ struct msm_gem_address_space *
spin_lock_init(&aspace->lock);
aspace->name = name;
aspace->mmu = msm_iommu_new(dev, domain);
+ if (IS_ERR(aspace->mmu)) {
+ int ret = PTR_ERR(aspace->mmu);
- drm_mm_init(&aspace->mm, (domain->geometry.aperture_start >>
PAGE_SHIFT),
- size >> PAGE_SHIFT);
+ kfree(aspace);
+ return ERR_PTR(ret);
+ }
+
+ /*
+* Attaching the IOMMU device changes the aperture values so use the
+* cached values instead
+*/
+ drm_mm_init(&aspace->mm, start >> PAGE_SHIFT, size >> PAGE_SHIFT);
kref_init(&aspace->kref);
@@ -164,6 +173,12 @@ struct msm_gem_address_space *
spin_lock_init(&aspace->lock);
aspace->name = name;
aspace->mmu = msm_gpummu_new(dev, gpu);
+ if (IS_ERR(aspace->mmu)) {
+ int ret = PTR_ERR(aspace->mmu);
+
+ kfree(aspace);
+
[PATCH v2 4/7] drm/msm: Refactor address space initialization
From: Jordan Crouse
Refactor how address space initialization works. Instead of having the
address space function create the MMU object (and thus require separate but
equal functions for gpummu and iommu) use a single function and pass the
MMU struct. Make the generic code cleaner by using target specific
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
This patch also adds support for a6xx specific mmu initialization to
allow for future extensions like supporting split pagetables.
Signed-off-by: Jordan Crouse
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 16 ++
drivers/gpu/drm/msm/adreno/a3xx_gpu.c| 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c| 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c| 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c| 24 +++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 23 ++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 8 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +++---
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 14 +
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 4 ---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 11 +--
drivers/gpu/drm/msm/msm_drv.h| 8 ++---
drivers/gpu/drm/msm/msm_gem_vma.c| 52 +---
drivers/gpu/drm/msm/msm_gpu.c| 40 ++--
drivers/gpu/drm/msm/msm_gpu.h| 4 +--
drivers/gpu/drm/msm/msm_iommu.c | 3 ++
16 files changed, 106 insertions(+), 114 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index 1f83bc1..60f6472 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -401,6 +401,21 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct
msm_gpu *gpu)
return state;
}
+static struct msm_gem_address_space *
+a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
+{
+ struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);
+ struct msm_gem_address_space *aspace;
+
+ aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
+ SZ_16M + 0xfff * SZ_64K);
+
+ if (IS_ERR(aspace) && !IS_ERR(mmu))
+ mmu->funcs->destroy(mmu);
+
+ return aspace;
+}
+
/* Register offset defines for A2XX - copy of A3XX */
static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
@@ -429,6 +444,7 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct
msm_gpu *gpu)
#endif
.gpu_state_get = a2xx_gpu_state_get,
.gpu_state_put = adreno_gpu_state_put,
+ .create_address_space = a2xx_create_address_space,
},
};
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 5f7e980..825e6f6 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -448,6 +448,7 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct
msm_gpu *gpu)
#endif
.gpu_state_get = a3xx_gpu_state_get,
.gpu_state_put = adreno_gpu_state_put,
+ .create_address_space = adreno_iommu_create_address_space,
},
};
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index ab2b752..0484e48 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -538,6 +538,7 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t
*value)
#endif
.gpu_state_get = a4xx_gpu_state_get,
.gpu_state_put = adreno_gpu_state_put,
+ .create_address_space = adreno_iommu_create_address_space,
},
.get_timestamp = a4xx_get_timestamp,
};
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 99cd6e6..b5cc407 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1394,6 +1394,7 @@ static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu)
.gpu_busy = a5xx_gpu_busy,
.gpu_state_get = a5xx_gpu_state_get,
.gpu_state_put = a5xx_gpu_state_put,
+ .create_address_space = adreno_iommu_create_address_space,
},
.get_timestamp = a5xx_get_timestamp,
};
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index daf0780..0d72e6c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -878,6 +878,29 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
return (unsigned long)busy_time;
}
+static struct msm_gem_address_space *
+a6xx_create_address
[PATCH v2 6/7] drm/msm: rearrange the gpu_rmw() function
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gpu.h | 5 +
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index f50fefb..4c4559f 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -165,6 +165,14 @@ u32 msm_readl(const void __iomem *addr)
return val;
}
+void msm_rmw(void __iomem *addr, u32 mask, u32 or)
+{
+ u32 val = msm_readl(addr);
+
+ val &= ~mask;
+ msm_writel(val | or, addr);
+}
+
struct msm_vblank_work {
struct work_struct work;
int crtc_id;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 2203729..1bc778b 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -405,6 +405,7 @@ void __iomem *msm_ioremap(struct platform_device *pdev,
const char *name,
const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);
+void msm_rmw(void __iomem *addr, u32 mask, u32 or);
struct msm_gpu_submitqueue;
int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 41d86c2..935a12f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -223,10 +223,7 @@ static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
{
- uint32_t val = gpu_read(gpu, reg);
-
- val &= ~mask;
- gpu_write(gpu, reg, val | or);
+ msm_rmw(gpu->mmio + (reg << 2), mask, or);
}
static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
--
1.9.1
___
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[PATCH v2 5/7] drm: msm: a6xx: Properly free up the iommu objects
This patch calls the right function to destroy the iommu domain as well as free the associated iommu structure there by facilitating proper clean up of resources upon failure of creating an address space. Signed-off-by: Sharat Masetty --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0d72e6c..ab562f6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -896,7 +896,7 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M, 0x); if (IS_ERR(aspace)) - iommu_domain_free(iommu); + mmu->funcs->destroy(mmu); return aspace; } -- 1.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 6/9] dt-bindings: sun6i-dsi: Add R40 DPHY compatible (w/ A31 fallback)
On Tue, Dec 31, 2019 at 06:35:25PM +0530, Jagan Teki wrote: > The MIPI DSI PHY controller on Allwinner R40 is similar > on the one on A31. > > Add R40 compatible and append A31 compatible as fallback. > > Signed-off-by: Jagan Teki > --- > Changes for v3: > - update the binding in new yaml format > > .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git > a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > index 8841938050b2..0c283fe79402 100644 > --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > @@ -18,6 +18,7 @@ properties: > oneOf: >- const: allwinner,sun6i-a31-mipi-dphy >- items: > + - const: allwinner,sun8i-r40-mipi-dphy >- const: allwinner,sun50i-a64-mipi-dphy >- const: allwinner,sun6i-a31-mipi-dphy This isn't doing what you say it does. Here you're stating that there's two valid values, one that is a single element allwinner,sun6i-a31-mipi-dphy, and another which is a list of three elements allwinner,sun8i-r40-mipi-dphy, allwinner,sun50i-a64-mipi-dphy and allwinner,sun6i-a31-mipi-dphy, in that order. Did you run make dtbs_check and dt_bindings_check? Maxime signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 7/9] dt-bindings: sun6i-dsi: Document R40 MIPI-DSI controller (w/ A64 fallback)
On Tue, Dec 31, 2019 at 06:35:26PM +0530, Jagan Teki wrote: > The MIPI DSI controller on Allwinner R40 is similar on > the one on A64 like doesn't associate any DSI_SCLK gating. > > So, add R40 compatible and append A64 compatible as fallback. > > Signed-off-by: Jagan Teki > --- > Changes for v3: > - update the binding in new yaml format > > .../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml| 8 +--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml > b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml > index d41ecb5e7f7c..138ffb6ae403 100644 > --- > a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml > +++ > b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml > @@ -15,9 +15,11 @@ properties: >"#size-cells": true > >compatible: > -enum: > - - allwinner,sun6i-a31-mipi-dsi > - - allwinner,sun50i-a64-mipi-dsi > +oneOf: > + - const: allwinner,sun6i-a31-mipi-dsi > + - const: allwinner,sun50i-a64-mipi-dsi > + - items: > + - const: allwinner,sun8i-r40-mipi-dsi Again, this isn't what you claim it does. Maxime signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] phy: Add DisplayPort configuration options
On 23/12/2019 15:41, Yuti Amonkar wrote:
> Allow DisplayPort PHYs to be configured through the generic
> functions through a custom structure added to the generic union.
> The configuration structure is used for reconfiguration of
> DisplayPort PHYs during link training operation.
>
> The parameters added here are the ones defined in the DisplayPort
> spec 1.4 which include link rate, number of lanes, voltage swing
> and pre-emphasis.
>
> Signed-off-by: Yuti Amonkar
I think we should also add phy mode for DisplayPort in this patch (or
series). e.g. something like this:
--
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index ba0aab59804f..79f25c8801f7 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -39,7 +39,8 @@ enum phy_mode {
PHY_MODE_PCIE,
PHY_MODE_ETHERNET,
PHY_MODE_MIPI_DPHY,
- PHY_MODE_SATA
+ PHY_MODE_SATA,
+ PHY_MODE_DISPLAYPORT
};
/**
--
Without it (and an associated phy_ops set_mode() call by the phy client)
the phy driver has no way to know how to interpret the "union
phy_configure_opts" in phy_ops configure() call.
Best regards,
Jyri
> ---
>
> This patch was a part of [1] series earlier but we think that it needs
> to have a separate attention of the reviewers. Also as both [1] & [2] are
> dependent on this patch, our sincere request to reviewers to have a
> faster review of this patch.
>
> [1]
>
> https://lkml.org/lkml/2019/12/11/455
>
> [2]
>
> https://patchwork.kernel.org/cover/11271191/
>
> include/linux/phy/phy-dp.h | 95
> ++
> include/linux/phy/phy.h| 4 ++
> 2 files changed, 99 insertions(+)
> create mode 100644 include/linux/phy/phy-dp.h
>
> diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
> new file mode 100644
> index 000..18cad23
> --- /dev/null
> +++ b/include/linux/phy/phy-dp.h
> @@ -0,0 +1,95 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2019 Cadence Design Systems Inc.
> + */
> +
> +#ifndef __PHY_DP_H_
> +#define __PHY_DP_H_
> +
> +#include
> +
> +/**
> + * struct phy_configure_opts_dp - DisplayPort PHY configuration set
> + *
> + * This structure is used to represent the configuration state of a
> + * DisplayPort phy.
> + */
> +struct phy_configure_opts_dp {
> + /**
> + * @link_rate:
> + *
> + * Link Rate, in Mb/s, of the main link.
> + *
> + * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
> + */
> + unsigned int link_rate;
> +
> + /**
> + * @lanes:
> + *
> + * Number of active, consecutive, data lanes, starting from
> + * lane 0, used for the transmissions on main link.
> + *
> + * Allowed values: 1, 2, 4
> + */
> + unsigned int lanes;
> +
> + /**
> + * @voltage:
> + *
> + * Voltage swing levels, as specified by DisplayPort specification,
> + * to be used by particular lanes. One value per lane.
> + * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
> + *
> + * Maximum value: 3
> + */
> + unsigned int voltage[4];
> +
> + /**
> + * @pre:
> + *
> + * Pre-emphasis levels, as specified by DisplayPort specification, to be
> + * used by particular lanes. One value per lane.
> + *
> + * Maximum value: 3
> + */
> + unsigned int pre[4];
> +
> + /**
> + * @ssc:
> + *
> + * Flag indicating, whether or not to enable spread-spectrum clocking.
> + *
> + */
> + u8 ssc : 1;
> +
> + /**
> + * @set_rate:
> + *
> + * Flag indicating, whether or not reconfigure link rate and SSC to
> + * requested values.
> + *
> + */
> + u8 set_rate : 1;
> +
> + /**
> + * @set_lanes:
> + *
> + * Flag indicating, whether or not reconfigure lane count to
> + * requested value.
> + *
> + */
> + u8 set_lanes : 1;
> +
> + /**
> + * @set_voltages:
> + *
> + * Flag indicating, whether or not reconfigure voltage swing
> + * and pre-emphasis to requested values. Only lanes specified
> + * by "lanes" parameter will be affected.
> + *
> + */
> + u8 set_voltages : 1;
> +};
> +
> +#endif /* __PHY_DP_H_ */
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index 15032f14..ba0aab5 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -16,6 +16,7 @@
> #include
> #include
>
> +#include
> #include
>
> struct phy;
> @@ -46,9 +47,12 @@ enum phy_mode {
> *
> * @mipi_dphy: Configuration set applicable for phys supporting
> * the MIPI_DPHY phy mode.
> + * @dp: Configuration set applicable for phys supporting
> + * the DisplayPort protocol.
> */
> union phy_configure_opts
[PULL] drm-misc-next
drm-misc-next-2020-01-02: drm-misc-next for v5.6: UAPI Changes: - Commandline parser: Add support for panel orientation, and per-mode options. - Fix IOCTL naming for dma-buf heaps. Cross-subsystem Changes: - Rename DMA_HEAP_IOC_ALLOC to DMA_HEAP_IOCTL_ALLOC before it becomes abi. - Change DMA-BUF system-heap's name to system. - Fix leak in error handling in dma_heap_ioctl(), and make a symbol static. - Fix udma-buf cpu access. - Fix ti devicetree bindings. Core Changes: - Add CTA-861-G modes with VIC >= 193. - Change error handling and remove bug_on in *drm_dev_init. - Export drm_panel_of_backlight() correctly once more. - Add support for lvds decoders. - Convert drm/client and drm/(gem-,)fb-helper to drm-device based logging and update logging todo. Driver Changes: - Add support for dsi/px30 to rockchip. - Add fb damage support to virtio. - Use dma_resv locking wrappers in vc4, msm, etnaviv. - Make functions in virtio static, and perform some simplifications. - Add suspend support to sun4i. - Add A64 mipi dsi support to sun4i. - Add runtime pm suspend to komeda. - Associated driver fixes. The following changes since commit 2156873f08c7893811f34177aa923ab1ea486591: drm/tilcdc: Remove obsolete bundled tilcdc tfp410 driver (2019-12-16 10:45:43 +0200) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-misc tags/drm-misc-next-2020-01-02 for you to fetch changes up to 1ce0d5162b98bf6120db1b259d0f0706e69f15fd: drm/panel: declare variable as __be16 (2020-01-01 19:53:50 +0100) drm-misc-next for v5.6: UAPI Changes: - Commandline parser: Add support for panel orientation, and per-mode options. - Fix IOCTL naming for dma-buf heaps. Cross-subsystem Changes: - Rename DMA_HEAP_IOC_ALLOC to DMA_HEAP_IOCTL_ALLOC before it becomes abi. - Change DMA-BUF system-heap's name to system. - Fix leak in error handling in dma_heap_ioctl(), and make a symbol static. - Fix udma-buf cpu access. - Fix ti devicetree bindings. Core Changes: - Add CTA-861-G modes with VIC >= 193. - Change error handling and remove bug_on in *drm_dev_init. - Export drm_panel_of_backlight() correctly once more. - Add support for lvds decoders. - Convert drm/client and drm/(gem-,)fb-helper to drm-device based logging and update logging todo. Driver Changes: - Add support for dsi/px30 to rockchip. - Add fb damage support to virtio. - Use dma_resv locking wrappers in vc4, msm, etnaviv. - Make functions in virtio static, and perform some simplifications. - Add suspend support to sun4i. - Add A64 mipi dsi support to sun4i. - Add runtime pm suspend to komeda. - Associated driver fixes. Aditya Pakki (1): drm: remove duplicate check on parent and avoid BUG_ON Andrew F. Davis (2): dma-buf: heaps: Use _IOCTL_ for userspace IOCTL identifier dma-buf: heaps: Remove redundant heap identifier from system heap name Andy Shevchenko (1): drm/drm_panel: Fix EXPORT of drm_panel_of_backlight() one more time Colin Ian King (2): dma-buf: fix resource leak on -ENOTTY error return path drm/gma500: fix null dereference of pointer fb before null check Daniel Vetter (7): drm/virtio: plane_state->fb iff plane_state->crtc drm/msm: Use dma_resv locking wrappers drm/vc4: Use dma_resv locking wrappers drm/etnaviv: Use dma_resv locking wrappers drm/malidp: plane_state->fb iff plane_state->crtc drm/mediatek: plane_state->fb iff plane_state->crtc drm/todo: Updating logging todo Fabrizio Castro (10): dt-bindings: display: bridge: Convert lvds-transmitter binding to json-schema dt-bindings: display: bridge: lvds-transmitter: Document powerdown-gpios dt-bindings: display: bridge: lvds-transmitter: Absorb ti, ds90c185.txt dt-bindings: display: bridge: lvds-transmitter: Document "ti, sn75lvds83" drm/bridge: Repurpose lvds-encoder.c drm/bridge: lvds-codec: Add "lvds-decoder" support drm/bridge: lvds-codec: Simplify panel DT node localisation dt-bindings: display: bridge: Repurpose lvds-encoder dt-bindings: display: bridge: lvds-codec: Document ti, ds90cf384a dt-bindings: display: bridge: lvds-codec: Absorb thine, thc63lvdm83d.txt Gerd Hoffmann (3): drm/virtio: skip set_scanout if framebuffer didn't change drm/virtio: batch display update commands. drm/virtio: use damage info for display updates. Gurchetan Singh (7): udmabuf: fix dma-buf cpu access drm/virtio: static-ify virtio_fence_signaled drm/virtio: static-ify virtio_gpu_framebuffer_init drm/virtio: get rid of drm_encoder_to_virtio_gpu_output drm/virtio: simplify getting fake offset drm/virtio: move to_virtio_fence inside virtgpu_fence drm/virtio: move drm_connector_to_virtio_gpu_output to virtgpu_display Hans de Goede (11): drm/modes: parse_cmdline: Fix pos
[PATCH 1/4] drm/tegra: Provide ddc symlink in output connector sysfs directory
Use the ddc pointer provided by the generic connector. Signed-off-by: Andrzej Pietrasiewicz Acked-by: Sam Ravnborg Reviewed-by: Emil Velikov --- drivers/gpu/drm/tegra/hdmi.c | 7 --- drivers/gpu/drm/tegra/sor.c | 7 --- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 50269ffbcb6b..21a629adcb51 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c @@ -1430,9 +1430,10 @@ static int tegra_hdmi_init(struct host1x_client *client) hdmi->output.dev = client->dev; - drm_connector_init(drm, &hdmi->output.connector, - &tegra_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); + drm_connector_init_with_ddc(drm, &hdmi->output.connector, + &tegra_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA, + hdmi->output.ddc); drm_connector_helper_add(&hdmi->output.connector, &tegra_hdmi_connector_helper_funcs); hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF; diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index fbbb974c1e1a..7fbcb348c7ee 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -2836,9 +2836,10 @@ static int tegra_sor_init(struct host1x_client *client) sor->output.dev = sor->dev; - drm_connector_init(drm, &sor->output.connector, - &tegra_sor_connector_funcs, - connector); + drm_connector_init_with_ddc(drm, &sor->output.connector, + &tegra_sor_connector_funcs, + connector, + sor->output.ddc); drm_connector_helper_add(&sor->output.connector, &tegra_sor_connector_helper_funcs); sor->output.connector.dpms = DRM_MODE_DPMS_OFF; -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/4] drm: zte: Provide ddc symlink in hdmi connector sysfs directory
Use the ddc pointer provided by the generic connector. Signed-off-by: Andrzej Pietrasiewicz Acked-by: Sam Ravnborg Reviewed-by: Emil Velikov --- drivers/gpu/drm/zte/zx_hdmi.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/zte/zx_hdmi.c b/drivers/gpu/drm/zte/zx_hdmi.c index a50f5a1f09b8..b98a1420dcd3 100644 --- a/drivers/gpu/drm/zte/zx_hdmi.c +++ b/drivers/gpu/drm/zte/zx_hdmi.c @@ -319,8 +319,10 @@ static int zx_hdmi_register(struct drm_device *drm, struct zx_hdmi *hdmi) hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; - drm_connector_init(drm, &hdmi->connector, &zx_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA); + drm_connector_init_with_ddc(drm, &hdmi->connector, + &zx_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA, + &hdmi->ddc->adap); drm_connector_helper_add(&hdmi->connector, &zx_hdmi_connector_helper_funcs); -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/4] drm/vc4: Provide ddc symlink in connector sysfs directory
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 1c62c6c9244b..cea18dc15f77 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -267,7 +267,8 @@ static const struct drm_connector_helper_funcs
vc4_hdmi_connector_helper_funcs =
};
static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
-struct drm_encoder
*encoder)
+struct drm_encoder
*encoder,
+struct i2c_adapter *ddc)
{
struct drm_connector *connector;
struct vc4_hdmi_connector *hdmi_connector;
@@ -281,8 +282,10 @@ static struct drm_connector
*vc4_hdmi_connector_init(struct drm_device *dev,
hdmi_connector->encoder = encoder;
- drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
- DRM_MODE_CONNECTOR_HDMIA);
+ drm_connector_init_with_ddc(dev, connector,
+ &vc4_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ ddc);
drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
/* Create and attach TV margin props to this connector. */
@@ -1395,7 +1398,8 @@ static int vc4_hdmi_bind(struct device *dev, struct
device *master, void *data)
DRM_MODE_ENCODER_TMDS, NULL);
drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
- hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
+ hdmi->connector =
+ vc4_hdmi_connector_init(drm, hdmi->encoder, hdmi->ddc);
if (IS_ERR(hdmi->connector)) {
ret = PTR_ERR(hdmi->connector);
goto err_destroy_encoder;
--
2.17.1
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[PATCH 0/4] Complete ddc symlink addition
The series completes the process of adding ddc symlink in connector's sysfs directory: of the initial submission only the below patches are still pending, hence this resend. Rebased onto drm-misc-next as of 2020-01-02. Andrzej Pietrasiewicz (4): drm/tegra: Provide ddc symlink in output connector sysfs directory drm/vc4: Provide ddc symlink in connector sysfs directory drm: zte: Provide ddc symlink in hdmi connector sysfs directory drm: zte: Provide ddc symlink in vga connector sysfs directory drivers/gpu/drm/tegra/hdmi.c | 7 --- drivers/gpu/drm/tegra/sor.c| 7 --- drivers/gpu/drm/vc4/vc4_hdmi.c | 12 drivers/gpu/drm/zte/zx_hdmi.c | 6 -- drivers/gpu/drm/zte/zx_vga.c | 6 -- 5 files changed, 24 insertions(+), 14 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4/4] drm: zte: Provide ddc symlink in vga connector sysfs directory
Use the ddc pointer provided by the generic connector.
Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Sam Ravnborg
Reviewed-by: Emil Velikov
---
drivers/gpu/drm/zte/zx_vga.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/zte/zx_vga.c b/drivers/gpu/drm/zte/zx_vga.c
index 9b67e419280c..c4fa3bbaba78 100644
--- a/drivers/gpu/drm/zte/zx_vga.c
+++ b/drivers/gpu/drm/zte/zx_vga.c
@@ -165,8 +165,10 @@ static int zx_vga_register(struct drm_device *drm, struct
zx_vga *vga)
vga->connector.polled = DRM_CONNECTOR_POLL_HPD;
- ret = drm_connector_init(drm, connector, &zx_vga_connector_funcs,
-DRM_MODE_CONNECTOR_VGA);
+ ret = drm_connector_init_with_ddc(drm, connector,
+ &zx_vga_connector_funcs,
+ DRM_MODE_CONNECTOR_VGA,
+ &vga->ddc->adap);
if (ret) {
DRM_DEV_ERROR(dev, "failed to init connector: %d\n", ret);
goto clean_encoder;
--
2.17.1
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[PATCH 3/3] drm: tiny: st7735r: Add support for Okaya RH128128T
Add support for the Okaya RH128128T display to the st7735r driver.
The RH128128T is a 128x128 1.44" TFT display driven by a Sitronix
ST7715R TFT Controller/Driver. The latter is very similar to the
ST7735R, and can be handled by the existing st7735r driver.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/tiny/st7735r.c | 65 --
1 file changed, 55 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/tiny/st7735r.c b/drivers/gpu/drm/tiny/st7735r.c
index 3f4487c716848cf8..05d162e76d8481e5 100644
--- a/drivers/gpu/drm/tiny/st7735r.c
+++ b/drivers/gpu/drm/tiny/st7735r.c
@@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * DRM driver for Sitronix ST7735R panels
+ * DRM driver for Sitronix ST7715R/ST7735R panels
*
* Copyright 2017 David Lechner
+ * Copyright (C) 2019 Glider bvba
*/
#include
@@ -10,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -37,12 +39,28 @@
#define ST7735R_MY BIT(7)
#define ST7735R_MX BIT(6)
#define ST7735R_MV BIT(5)
+#define ST7735R_RGBBIT(3)
+
+struct st7735r_cfg {
+ const struct drm_display_mode mode;
+ unsigned int left_offset;
+ unsigned int top_offset;
+ unsigned int write_only:1;
+ unsigned int rgb:1; /* RGB (vs. BGR) */
+};
+
+struct st7735r_priv {
+ struct mipi_dbi_dev dbidev; /* Must be first for .release() */
+ unsigned int rgb:1;
+};
static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe,
struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
+ struct st7735r_priv *priv = container_of(dbidev, struct st7735r_priv,
+dbidev);
struct mipi_dbi *dbi = &dbidev->dbi;
int ret, idx;
u8 addr_mode;
@@ -87,6 +105,10 @@ static void jd_t18003_t01_pipe_enable(struct
drm_simple_display_pipe *pipe,
addr_mode = ST7735R_MY | ST7735R_MV;
break;
}
+
+ if (priv->rgb)
+ addr_mode |= ST7735R_RGB;
+
mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
MIPI_DCS_PIXEL_FMT_16BIT);
@@ -116,8 +138,17 @@ static const struct drm_simple_display_pipe_funcs
jd_t18003_t01_pipe_funcs = {
.prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb,
};
-static const struct drm_display_mode jd_t18003_t01_mode = {
- DRM_SIMPLE_MODE(128, 160, 28, 35),
+static const struct st7735r_cfg jd_t18003_t01_cfg = {
+ .mode = { DRM_SIMPLE_MODE(128, 160, 28, 35) },
+ /* Cannot read from Adafruit 1.8" display via SPI */
+ .write_only = true,
+};
+
+static const struct st7735r_cfg rh128128t_cfg = {
+ .mode = { DRM_SIMPLE_MODE(128, 128, 25, 26) },
+ .left_offset= 2,
+ .top_offset = 3,
+ .rgb= true,
};
DEFINE_DRM_GEM_CMA_FOPS(st7735r_fops);
@@ -136,13 +167,14 @@ static struct drm_driver st7735r_driver = {
};
static const struct of_device_id st7735r_of_match[] = {
- { .compatible = "jianda,jd-t18003-t01" },
+ { .compatible = "jianda,jd-t18003-t01", .data = &jd_t18003_t01_cfg },
+ { .compatible = "okaya,rh128128t", .data = &rh128128t_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, st7735r_of_match);
static const struct spi_device_id st7735r_id[] = {
- { "jd-t18003-t01", 0 },
+ { "jd-t18003-t01", (uintptr_t)&jd_t18003_t01_cfg },
{ },
};
MODULE_DEVICE_TABLE(spi, st7735r_id);
@@ -150,17 +182,26 @@ MODULE_DEVICE_TABLE(spi, st7735r_id);
static int st7735r_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
+ const struct st7735r_cfg *cfg;
struct mipi_dbi_dev *dbidev;
+ struct st7735r_priv *priv;
struct drm_device *drm;
struct mipi_dbi *dbi;
struct gpio_desc *dc;
u32 rotation = 0;
int ret;
- dbidev = kzalloc(sizeof(*dbidev), GFP_KERNEL);
- if (!dbidev)
+ cfg = of_device_get_match_data(&spi->dev);
+ if (!cfg)
+ cfg = (void *)spi_get_device_id(spi)->driver_data;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
return -ENOMEM;
+ dbidev = &priv->dbidev;
+ priv->rgb = cfg->rgb;
+
dbi = &dbidev->dbi;
drm = &dbidev->drm;
ret = devm_drm_dev_init(dev, drm, &st7735r_driver);
@@ -193,10 +234,14 @@ static int st7735r_probe(struct spi_device *spi)
if (ret)
return ret;
- /* Cannot read from Adafruit 1.8" display via SPI */
- dbi->read_commands = NULL;
+ if (cfg->write_only)
+ dbi->read_commands = NULL;
+
+ dbidev->left_offset = cfg->left_o
[PATCH 2/3] drm/mipi_dbi: Add support for display offsets
If the resolution of the TFT display is smaller than the maximum
resolution supported by the display controller, the display may be
connected to the driver output arrays with a horizontal and/or vertical
offset, leading to a shifted image.
Add support for specifying these offsets.
Signed-off-by: Geert Uytterhoeven
---
drivers/gpu/drm/drm_mipi_dbi.c | 30 --
include/drm/drm_mipi_dbi.h | 12
2 files changed, 32 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/drm_mipi_dbi.c b/drivers/gpu/drm/drm_mipi_dbi.c
index 16bff1be4b8ac622..27fe81a53c88e338 100644
--- a/drivers/gpu/drm/drm_mipi_dbi.c
+++ b/drivers/gpu/drm/drm_mipi_dbi.c
@@ -238,6 +238,23 @@ int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer
*fb,
}
EXPORT_SYMBOL(mipi_dbi_buf_copy);
+static void mipi_dbi_set_window_address(struct mipi_dbi_dev *dbidev,
+ unsigned int xs, unsigned int xe,
+ unsigned int ys, unsigned int ye)
+{
+ struct mipi_dbi *dbi = &dbidev->dbi;
+
+ xs += dbidev->left_offset;
+ xe += dbidev->left_offset;
+ ys += dbidev->top_offset;
+ ye += dbidev->top_offset;
+
+ mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, (xs >> 8) & 0xff,
+xs & 0xff, (xe >> 8) & 0xff, xe & 0xff);
+ mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, (ys >> 8) & 0xff,
+ys & 0xff, (ye >> 8) & 0xff, ye & 0xff);
+}
+
static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect
*rect)
{
struct drm_gem_object *gem = drm_gem_fb_get_obj(fb, 0);
@@ -271,12 +288,8 @@ static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb,
struct drm_rect *rect)
tr = cma_obj->vaddr;
}
- mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
-(rect->x1 >> 8) & 0xff, rect->x1 & 0xff,
-((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
-(rect->y1 >> 8) & 0xff, rect->y1 & 0xff,
-((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff);
+ mipi_dbi_set_window_address(dbidev, rect->x1, rect->x2 - 1, rect->y1,
+ rect->y2 - 1);
ret = mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START, tr,
width * height * 2);
@@ -366,10 +379,7 @@ static void mipi_dbi_blank(struct mipi_dbi_dev *dbidev)
memset(dbidev->tx_buf, 0, len);
- mipi_dbi_command(dbi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
-((width - 1) >> 8) & 0xFF, (width - 1) & 0xFF);
- mipi_dbi_command(dbi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
-((height - 1) >> 8) & 0xFF, (height - 1) & 0xFF);
+ mipi_dbi_set_window_address(dbidev, 0, width - 1, 0, height - 1);
mipi_dbi_command_buf(dbi, MIPI_DCS_WRITE_MEMORY_START,
(u8 *)dbidev->tx_buf, len);
diff --git a/include/drm/drm_mipi_dbi.h b/include/drm/drm_mipi_dbi.h
index 67c66f5ee591e80f..33f325f5af2b921f 100644
--- a/include/drm/drm_mipi_dbi.h
+++ b/include/drm/drm_mipi_dbi.h
@@ -109,6 +109,18 @@ struct mipi_dbi_dev {
*/
unsigned int rotation;
+ /**
+* @left_offset: Horizontal offset of the display relative to the
+* controller's driver array
+*/
+ unsigned int left_offset;
+
+ /**
+* @top_offset: Vertical offset of the display relative to the
+* controller's driver array
+*/
+ unsigned int top_offset;
+
/**
* @backlight: backlight device (optional)
*/
--
2.17.1
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[PATCH 0/3] drm: Add support for Okaya RH128128T
Hi all,
This patch series adds support for the Okaya RH128128T LCD to the
existing ST7735R driver. This is a 128x128 1.4" TFT display driven by a
Sitronix ST7715R TFT Controller/Driver. It is used on the "lcd-pmod"
display module that is shipped with Renesas RSK+RZA1 development boards,
and with several other Renesas starter kits, for RX, Synergy, and RZ/T1
MCUs and SoCs.
I'm not 100% sure about the actual Okaya part number, but this is the
only display listed on the Okaya website that matches the
specifications.
Patch 2 depends on "[PATCH] drm/mipi_dbi: Fix off-by-one bugs in
mipi_dbi_blank()"[1], which I sent earlier this week.
This has been tested using the r7s72100-rskrza1-pmod-spi.dtso and
r7s72100-rskrza1-pmod2-lcd.dtso DT overlays[2].
Note that for using this on RSK+RZA1, there is a dependency on RSPI
cs-gpios support[3]. With DT overlays, this also depends on DT
overlays[4] and gpio-hog overlay support[5].
Thanks for your comments!
[1] https://lore.kernel.org/lkml/20191230130604.31006-1-geert+rene...@glider.be/
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/renesas-overlays
[3] "[PATCH 0/6] spi: rspi: Add support for multiple native and GPIO
chip selects"
https://lore.kernel.org/lkml/20200102133822.29346-1-geert+rene...@glider.be/
[4]
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/overlays
[5] "[PATCH/RFC 0/2] gpio: of: Add DT overlay support for GPIO hogs"
https://lore.kernel.org/lkml/20191230133852.5890-1-geert+rene...@glider.be/
Geert Uytterhoeven (3):
dt-bindings: display: sitronix,st7735r: Add Okaya rh128128t
drm/mipi_dbi: Add support for display offsets
drm: tiny: st7735r: Add support for Okaya RH128128T
.../bindings/display/sitronix,st7735r.txt | 4 +-
drivers/gpu/drm/drm_mipi_dbi.c| 30 ++---
drivers/gpu/drm/tiny/st7735r.c| 65 ---
include/drm/drm_mipi_dbi.h| 12
4 files changed, 90 insertions(+), 21 deletions(-)
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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[PATCH 1/3] dt-bindings: display: sitronix, st7735r: Add Okaya rh128128t
Document support for the Okaya RH128128T display, which is a 128x128 1.44" TFT display driven by a Sitronix ST7715R TFT Controller/Driver. ST7715R and ST7735R are very similar. Their major difference is that the former is restricted to displays of up to 132x132 pixels, while the latter supports displays up to 132x162 pixels. Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/display/sitronix,st7735r.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt index cd5c7186890a2be7..87ebdcb294e29798 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt +++ b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt @@ -4,7 +4,9 @@ This binding is for display panels using a Sitronix ST7735R controller in SPI mode. Required properties: -- compatible: "jianda,jd-t18003-t01", "sitronix,st7735r" +- compatible: Must be one of the following combinations: + - "jianda,jd-t18003-t01", "sitronix,st7735r" + - "okaya,rh128128t", "sitronix,st7715r" - dc-gpios:Display data/command selection (D/CX) - reset-gpios: Reset signal (RSTX) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/3] dt-bindings: display: sitronix, st7735r: Add Okaya rh128128t
Hi Geert. On Thu, Jan 02, 2020 at 03:12:44PM +0100, Geert Uytterhoeven wrote: > Document support for the Okaya RH128128T display, which is a 128x128 > 1.44" TFT display driven by a Sitronix ST7715R TFT Controller/Driver. > > ST7715R and ST7735R are very similar. Their major difference is that > the former is restricted to displays of up to 132x132 pixels, while the > latter supports displays up to 132x162 pixels. > > Signed-off-by: Geert Uytterhoeven > --- > .../devicetree/bindings/display/sitronix,st7735r.txt | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt > b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt > index cd5c7186890a2be7..87ebdcb294e29798 100644 > --- a/Documentation/devicetree/bindings/display/sitronix,st7735r.txt > +++ b/Documentation/devicetree/bindings/display/sitronix,st7735r.txt While touching the bindings file, can I convince you to convert it to meta-schema format (.yaml)? > @@ -4,7 +4,9 @@ This binding is for display panels using a Sitronix ST7735R > controller in SPI > mode. > > Required properties: > -- compatible:"jianda,jd-t18003-t01", "sitronix,st7735r" > +- compatible:Must be one of the following combinations: > + - "jianda,jd-t18003-t01", "sitronix,st7735r" > + - "okaya,rh128128t", "sitronix,st7715r" It would be nice if there was a "description" for each pair of compatible that identified the actual panel. In your case "Okaya RH128128T 1.44" 128x128 TFT display" It can be looked up in git history - but better to have it in the binding file. Sam ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/mipi_dbi: Fix off-by-one bugs in mipi_dbi_blank()
Den 30.12.2019 14.06, skrev Geert Uytterhoeven:
> When configuring the frame memory window, the last column and row
> numbers are written to the column resp. page address registers. These
> numbers are thus one less than the actual window width resp. height.
>
> While this is handled correctly in mipi_dbi_fb_dirty() since commit
> 03ceb1c8dfd1e293 ("drm/tinydrm: Fix setting of the column/page end
> addresses."), it is not in mipi_dbi_blank(). The latter still forgets
> to subtract one when calculating the most significant bytes of the
> column and row numbers, thus programming wrong values when the display
> width or height is a multiple of 256.
>
> Fixes: 02dd95fe31693626 ("drm/tinydrm: Add MIPI DBI support")
> Signed-off-by: Geert Uytterhoeven
> ---
Thanks, applied to drm-misc-next.
Noralf.
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Re: [PATCH v2] drm/amd/display: Reduce HDMI pixel encoding if max clock is exceeded
On 2019-12-02 4:47 p.m., Thomas Anderson wrote:
> For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
> "interesting" modes would be disabled, leaving only low-res or low
> framerate modes.
>
> This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
> clock is exceeded. Verified that 8K30 and 4K120 are now available and
> working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.
>
> Signed-off-by: Thomas Anderson
Apologies for the late response.
Thanks for getting high-res modes working on HDMI.
This change is
Reviewed-by: Harry Wentland
Harry
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 ++-
> 1 file changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 7aac9568d3be..803e59d97411 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3356,27 +3356,21 @@ get_output_color_space(const struct dc_crtc_timing
> *dc_crtc_timing)
> return color_space;
> }
>
> -static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
> -{
> - if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> - return;
> -
> - timing_out->display_color_depth--;
> -}
> -
> -static void adjust_colour_depth_from_display_info(struct dc_crtc_timing
> *timing_out,
> - const struct drm_display_info
> *info)
> +static bool adjust_colour_depth_from_display_info(
> + struct dc_crtc_timing *timing_out,
> + const struct drm_display_info *info)
> {
> + enum dc_color_depth depth = timing_out->display_color_depth;
> int normalized_clk;
> - if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> - return;
> do {
> normalized_clk = timing_out->pix_clk_100hz / 10;
> /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
> if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> normalized_clk /= 2;
> /* Adjusting pix clock following on HDMI spec based on colour
> depth */
> - switch (timing_out->display_color_depth) {
> + switch (depth) {
> + case COLOR_DEPTH_888:
> + break;
> case COLOR_DEPTH_101010:
> normalized_clk = (normalized_clk * 30) / 24;
> break;
> @@ -3387,14 +3381,15 @@ static void
> adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
> normalized_clk = (normalized_clk * 48) / 24;
> break;
> default:
> - return;
> + /* The above depths are the only ones valid for HDMI. */
> + return false;
> }
> - if (normalized_clk <= info->max_tmds_clock)
> - return;
> - reduce_mode_colour_depth(timing_out);
> -
> - } while (timing_out->display_color_depth > COLOR_DEPTH_888);
> -
> + if (normalized_clk <= info->max_tmds_clock) {
> + timing_out->display_color_depth = depth;
> + return true;
> + }
> + } while (--depth > COLOR_DEPTH_666);
> + return false;
> }
>
> static void fill_stream_properties_from_drm_display_mode(
> @@ -3474,8 +3469,14 @@ static void
> fill_stream_properties_from_drm_display_mode(
>
> stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
> stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
> - if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
> - adjust_colour_depth_from_display_info(timing_out, info);
> + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> + if (!adjust_colour_depth_from_display_info(timing_out, info) &&
> + drm_mode_is_420_also(info, mode_in) &&
> + timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
> + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
> + adjust_colour_depth_from_display_info(timing_out, info);
> + }
> + }
> }
>
> static void fill_audio_info(struct audio_info *audio_info,
>
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[Bug 205049] garbled graphics
https://bugzilla.kernel.org/show_bug.cgi?id=205049 --- Comment #16 from le...@onet.pl --- https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2836 Could somebody please provide a clear set of instructions on what can actually be done with this link? It just seems to contain a heap of forum comments, but no nothing "useful" in the conventional sense where a user can download and install a damned fix. -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40
On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
>
> On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > LCD interfaces like RGB, LVDS and DSI.
> >
> > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> > tcon top.
> >
> > Add support for it, in tcon driver.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v3:
> > - none
> >
> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > index fad72799b8df..69611d38c844 100644
> > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks
> > sun8i_a83t_tv_quirks = {
> > .has_channel_1 = true,
> > };
> >
> > +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = {
> > + .supports_lvds = true,
> > + .has_channel_0 = true,
> > + /* TODO Need to support TCON output muxing via GPIO pins */
> > + .set_mux= sun8i_r40_tcon_tv_set_mux,
>
> What is this muking about? And why is it a TODO?
Muxing similar like how TCON TOP handle TV0, TV1 I have reused the
same so-that it would configure de port selection via
sun8i_tcon_top_de_config
TCON output muxing have gpio with GPIOD and GPIOH bits, which select
which of LCD or TV TCON outputs to the LCD function pins. I have
marked these has TODO for further support as mentioned by Chen-Yu in
v1[1].
[1] https://patchwork.freedesktop.org/patch/310210/?series=62062&rev=1
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[Bug 205049] garbled graphics
https://bugzilla.kernel.org/show_bug.cgi?id=205049 --- Comment #17 from Pierre-Eric Pelloux-Prayer (pierre-eric.pelloux-pra...@amd.com) --- This bug has been fixed in Mesa, but is not part of a release yet. So the 3 possible fixes are: - compile Mesa from git - or find a package for your distribution that contains Mesa git - or define this environment variable system-wide "AMD_DEBUG=nodcc" until Mesa 20 is released and your distribution is updated. -- You are receiving this mail because: You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 6/9] dt-bindings: sun6i-dsi: Add R40 DPHY compatible (w/ A31 fallback)
On Thu, Jan 2, 2020 at 4:33 PM Maxime Ripard wrote: > > On Tue, Dec 31, 2019 at 06:35:25PM +0530, Jagan Teki wrote: > > The MIPI DSI PHY controller on Allwinner R40 is similar > > on the one on A31. > > > > Add R40 compatible and append A31 compatible as fallback. > > > > Signed-off-by: Jagan Teki > > --- > > Changes for v3: > > - update the binding in new yaml format > > > > .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git > > a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > > b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > > index 8841938050b2..0c283fe79402 100644 > > --- > > a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > > +++ > > b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml > > @@ -18,6 +18,7 @@ properties: > > oneOf: > >- const: allwinner,sun6i-a31-mipi-dphy > >- items: > > + - const: allwinner,sun8i-r40-mipi-dphy > >- const: allwinner,sun50i-a64-mipi-dphy > >- const: allwinner,sun6i-a31-mipi-dphy > > This isn't doing what you say it does. > > Here you're stating that there's two valid values, one that is a > single element allwinner,sun6i-a31-mipi-dphy, and another which is a > list of three elements allwinner,sun8i-r40-mipi-dphy, > allwinner,sun50i-a64-mipi-dphy and allwinner,sun6i-a31-mipi-dphy, in > that order. I got it Maxime, thanks for pointing this. > > Did you run make dtbs_check and dt_bindings_check? I sure I didn't, thanks for the clue. Will do this on another patch as well. Jagan. ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40
On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> >
> > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > > LCD interfaces like RGB, LVDS and DSI.
> > >
> > > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> > > tcon top.
> > >
> > > Add support for it, in tcon driver.
> > >
> > > Signed-off-by: Jagan Teki
> > > ---
> > > Changes for v3:
> > > - none
> > >
> > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 8
> > > 1 file changed, 8 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > index fad72799b8df..69611d38c844 100644
> > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks
> > > sun8i_a83t_tv_quirks = {
> > > .has_channel_1 = true,
> > > };
> > >
> > > +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = {
> > > + .supports_lvds = true,
> > > + .has_channel_0 = true,
> > > + /* TODO Need to support TCON output muxing via GPIO pins */
> > > + .set_mux= sun8i_r40_tcon_tv_set_mux,
> >
> > What is this muking about? And why is it a TODO?
>
> Muxing similar like how TCON TOP handle TV0, TV1 I have reused the
> same so-that it would configure de port selection via
> sun8i_tcon_top_de_config
>
> TCON output muxing have gpio with GPIOD and GPIOH bits, which select
> which of LCD or TV TCON outputs to the LCD function pins. I have
> marked these has TODO for further support as mentioned by Chen-Yu in
> v1[1].
It should be in the commit log.
What's the plan to support that when needed? And that means that the
LCD and TV outputs are mutually exclusive? We should at the very least
check that both aren't enabled at the same time.
Maxime
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Re: [PATCH v3] drm: Set crc->opened to false before setting crc source to NULL.
On 2019-07-26 1:37 p.m., David (Dingchen) Zhang wrote: > From: Dingchen Zhang > > to terminate the while-loop in drm_dp_aux_crc_work when > drm_dp_start/stop_crc are called in the hook to set crc source. > > v3: set crc->opened to false without checking (Nick) > v2: Move spin_lock around entire crc->opened use (Daniel) > > Cc: Daniel Vetter > Cc: Harry Wentland > Cc: Nick Kazlauskas > Signed-off-by: Dingchen Zhang Looks like we dropped the ball on this and the other CRC patch. I'll merge them now. Reviewed-by: Harry Wentland Harry > --- > drivers/gpu/drm/drm_debugfs_crc.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/drm_debugfs_crc.c > b/drivers/gpu/drm/drm_debugfs_crc.c > index dac267e840af..d2d2389d8892 100644 > --- a/drivers/gpu/drm/drm_debugfs_crc.c > +++ b/drivers/gpu/drm/drm_debugfs_crc.c > @@ -249,6 +249,11 @@ static int crtc_crc_release(struct inode *inode, struct > file *filep) > struct drm_crtc *crtc = filep->f_inode->i_private; > struct drm_crtc_crc *crc = &crtc->crc; > > + /* terminate the infinite while loop if 'drm_dp_aux_crc_work' running */ > + spin_lock_irq(&crc->lock); > + crc->opened = false; > + spin_unlock_irq(&crc->lock); > + > crtc->funcs->set_crc_source(crtc, NULL); > > spin_lock_irq(&crc->lock); > ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v3 0/6] fixes for atmel-hlcdc
On Thu, 02 Jan 2020, Sam Ravnborg wrote:
> Hi Lee.
>
> How do de handle the two mfd related patches?
>
> > I have few fixes for atmel-hlcdc driver in this series as well
> > as two reverts.
> > Revert "drm: atmel-hlcdc: enable sys_clk during initalization." is
> > due to the fix in in patch 2/5.
> >
> > Thank you,
> > Claudiu Beznea
> >
> > Changes in v3:
> > - changes dev_err() message in patch 4/6
> > - collect Acked-by tags
> >
> > Changes in v2:
> > - introduce patch 3/6
> > - use dev_err() inpatch 4/6
> > - introduce patch 5/6 instead of reverting commit f6f7ad323461
> > ("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested")
> >
> > Claudiu Beznea (5):
> > drm: atmel-hlcdc: use double rate for pixel clock only if supported
> > drm: atmel-hlcdc: enable clock before configuring timing engine
>
> > mfd: atmel-hlcdc: add struct device member to struct
> > atmel_hlcdc_regmap
> > mfd: atmel-hlcdc: return in case of error
>
> Would it be OK to apply the to drm-misc-next, or shal they go in via
> your mfd tree?
How are they related to the other patches? Do they have build-time
dependencies on any of the other patches, or vice versa?
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Re: [PATCH v3 0/6] fixes for atmel-hlcdc
Hi Lee.
> > > ("drm/atmel-hlcdc: allow selecting a higher pixel-clock than requested")
> > >
> > > Claudiu Beznea (5):
> > > drm: atmel-hlcdc: use double rate for pixel clock only if supported
> > > drm: atmel-hlcdc: enable clock before configuring timing engine
> >
> > > mfd: atmel-hlcdc: add struct device member to struct
> > > atmel_hlcdc_regmap
> > > mfd: atmel-hlcdc: return in case of error
> >
> > Would it be OK to apply the to drm-misc-next, or shal they go in via
> > your mfd tree?
>
> How are they related to the other patches? Do they have build-time
> dependencies on any of the other patches, or vice versa?
No build time dependencies.
But from the description of "atmel-hlcdc: return in case of error":
"
For HLCDC timing engine configurations bit ATMEL_HLCDC_SIP of
ATMEL_HLCDC_SR needs to be polled before applying new config.
"
I get that changing timing for the HLCDC may fail if these
patches are not applied.
So it is only to have updated hlcdc support in drm-misc-next
for further testing.
Sam
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Re: [PATCH v3 2/9] drm/sun4i: tcon: Add TCON LCD support for R40
On Thu, Jan 2, 2020 at 9:17 PM Maxime Ripard wrote:
>
> On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> > On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> > >
> > > On Tue, Dec 31, 2019 at 06:35:21PM +0530, Jagan Teki wrote:
> > > > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > > > LCD interfaces like RGB, LVDS and DSI.
> > > >
> > > > Like TCON TV0, TV1 these LCD0, LCD1 are also managed via
> > > > tcon top.
> > > >
> > > > Add support for it, in tcon driver.
> > > >
> > > > Signed-off-by: Jagan Teki
> > > > ---
> > > > Changes for v3:
> > > > - none
> > > >
> > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 8
> > > > 1 file changed, 8 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > > index fad72799b8df..69611d38c844 100644
> > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> > > > @@ -1470,6 +1470,13 @@ static const struct sun4i_tcon_quirks
> > > > sun8i_a83t_tv_quirks = {
> > > > .has_channel_1 = true,
> > > > };
> > > >
> > > > +static const struct sun4i_tcon_quirks sun8i_r40_lcd_quirks = {
> > > > + .supports_lvds = true,
> > > > + .has_channel_0 = true,
> > > > + /* TODO Need to support TCON output muxing via GPIO pins */
> > > > + .set_mux= sun8i_r40_tcon_tv_set_mux,
> > >
> > > What is this muking about? And why is it a TODO?
> >
> > Muxing similar like how TCON TOP handle TV0, TV1 I have reused the
> > same so-that it would configure de port selection via
> > sun8i_tcon_top_de_config
> >
> > TCON output muxing have gpio with GPIOD and GPIOH bits, which select
> > which of LCD or TV TCON outputs to the LCD function pins. I have
> > marked these has TODO for further support as mentioned by Chen-Yu in
> > v1[1].
>
> It should be in the commit log.
Make sense.
>
> What's the plan to support that when needed? And that means that the
> LCD and TV outputs are mutually exclusive? We should at the very least
> check that both aren't enabled at the same time.
Yes, LCD or TV within the outselect seems to be mutually exclusive.
Like LCD0 or TV0 can output to GPIOD incase of TV0_OUTSEL and LCD1 or
TV1 can output to GPIOH incase of TV1_OUTSEL. I think checking them
before configuring TCON_TOP_PORT_SEL_REG would make sense, let me know
if you have any suggestions?
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Re: [PATCH v2] dt-bindings: display: Convert Allwinner display pipeline to schemas
On Thu, Jan 2, 2020 at 8:26 AM Maxime Ripard wrote: > > The Allwinner SoCs have a display engine composed of several controllers > assembled differently depending on the SoC, the number and type of output > they have, and the additional features they provide. A number of those are > supported in Linux, with the matching bindings. > > Now that we have the DT validation in place, let's split into separate file > and convert the device tree bindings for those controllers to schemas. > > Signed-off-by: Maxime Ripard > > --- > > Changes from v1: > - Declare the ports in the bindings What about my comment on using minItems rather than maxItems? Rob ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2] drm/panel: simple: Support reset GPIOs
Hi Miquel
On Tue, Dec 24, 2019 at 03:21:34PM +0100, Miquel Raynal wrote:
> The panel common bindings provide a gpios-reset property. Let's
> support it in the simple driver.
>
> Two fields are added to the panel description structure: the time to
> assert the reset and the time to wait right after before starting to
> interact with it in any manner. In case these default values are not
> filled but the GPIO is present in the DT, default values are applied.
Wehn we discussed this the last time you wrote:
"""
my hardware is:
LVDS IP <--> LVDS to RGB bridge <> Panel
While there is a simple "RGB to LVDS" bridge driver, there is none
doing the work the other way around. In my case, the bridge has a reset
pin.
As until now there is no way to represent the "LVDS to RGB" bridge and
because the bindings already document such reset pin, I decided to add
support for it in the simple panel driver.
"""
Based on the information provided it seems that the correct way is to
add a "LVDS to RGB bridge" and then let the bridge handle the reset
functionality.
It is obviously much more code to do it this way but then
other panels using the same type of brigde have the
same functionality without adding bridge functionality to the panel.
Sam
>
> Signed-off-by: Miquel Raynal
> ---
>
> Changes since v1:
> * Add two parameters in the panel description structure.
> * Ensure the reset is asserted the right amount of time and the
> deasserted before continuing if a reset GPIO is given.
>
> drivers/gpu/drm/panel/panel-simple.c | 32 +++-
> 1 file changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c
> b/drivers/gpu/drm/panel/panel-simple.c
> index 28fa6ba7b767..ac6f6b5d200d 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -38,6 +38,9 @@
> #include
> #include
>
> +#define MIN_DEFAULT_RESET_US 10
> +#define MIN_DEFAULT_WAIT_US 10
> +
> /**
> * @modes: Pointer to array of fixed modes appropriate for this panel. If
> * only one mode then this can just be the address of this the mode.
> @@ -94,6 +97,10 @@ struct panel_desc {
>
> u32 bus_format;
> u32 bus_flags;
> +
> + /* Minimum reset duration and wait period after it in us */
> + u32 reset_time;
> + u32 reset_wait;
> };
>
> struct panel_simple {
> @@ -109,6 +116,7 @@ struct panel_simple {
> struct i2c_adapter *ddc;
>
> struct gpio_desc *enable_gpio;
> + struct gpio_desc *reset_gpio;
>
> struct drm_display_mode override_mode;
> };
> @@ -432,12 +440,34 @@ static int panel_simple_probe(struct device *dev, const
> struct panel_desc *desc)
> if (IS_ERR(panel->supply))
> return PTR_ERR(panel->supply);
>
> + panel->reset_gpio = devm_gpiod_get_optional(dev, "reset",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(panel->reset_gpio)) {
> + err = PTR_ERR(panel->reset_gpio);
> + if (err != -EPROBE_DEFER)
> + dev_err(dev, "failed to request reset pin: %d\n", err);
> + return err;
> + } else if (panel->reset_gpio) {
> + u32 reset_time = panel->desc->reset_time;
> + u32 reset_wait = panel->desc->reset_wait;
> +
> + if (!reset_time)
> + reset_time = MIN_DEFAULT_RESET_US;
> +
> + if (!reset_wait)
> + reset_wait = MIN_DEFAULT_WAIT_US;
> +
> + usleep_range(reset_time, 2 * reset_time);
> + gpiod_set_value_cansleep(panel->reset_gpio, 0);
> + usleep_range(reset_wait, 2 * reset_wait);
> + }
> +
> panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
>GPIOD_OUT_LOW);
> if (IS_ERR(panel->enable_gpio)) {
> err = PTR_ERR(panel->enable_gpio);
> if (err != -EPROBE_DEFER)
> - dev_err(dev, "failed to request GPIO: %d\n", err);
> + dev_err(dev, "failed to request enable pin: %d\n", err);
> return err;
> }
>
> --
> 2.20.1
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Re: [PATCH resend 1/2] drm/connector: Split out orientation quirk detection (v2)
On Mon, Dec 16, 2019 at 12:51:57PM +0100, Hans de Goede wrote:
> From: Derek Basehore
>
> Not every platform needs quirk detection for panel orientation, so
> split the drm_connector_init_panel_orientation_property into two
> functions. One for platforms without the need for quirks, and the
> other for platforms that need quirks.
>
> Hans de Goede (changes in v2):
>
> Rename the function from drm_connector_init_panel_orientation_property
> to drm_connector_set_panel_orientation[_with_quirk] and pass in the
> panel-orientation to set.
>
> Beside the rename, also make the function set the passed in value
> only once, if the value was set before (to a value other then
> DRM_MODE_PANEL_ORIENTATION_UNKNOWN) make any further set calls a no-op.
>
> This change is preparation for allowing the user to override the
> panel-orientation for any connector from the kernel commandline.
> When the panel-orientation is overridden this way, then we must ignore
> the panel-orientation detection done by the driver.
>
> Signed-off-by: Derek Basehore
> Signed-off-by: Hans de Goede
> ---
> drivers/gpu/drm/drm_connector.c | 74 ++---
> drivers/gpu/drm/i915/display/icl_dsi.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 9 ++-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +-
> include/drm/drm_connector.h | 9 ++-
> 5 files changed, 71 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 0965632008a9..f4fa5c59717d 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1139,7 +1139,8 @@ static const struct drm_prop_enum_list dp_colorspaces[]
> = {
> * coordinates, so if userspace rotates the picture to adjust for
> * the orientation it must also apply the same transformation to the
> * touchscreen input coordinates. This property is initialized by calling
> - * drm_connector_init_panel_orientation_property().
> + * drm_connector_set_panel_orientation() or
> + * drm_connector_set_panel_orientation_with_quirk()
do we have a better name than quirks for these dsi modes?
> *
> * scaling mode:
> * This property defines how a non-native mode is upscaled to the native
> @@ -2046,38 +2047,41 @@ void drm_connector_set_vrr_capable_property(
> EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
>
> /**
> - * drm_connector_init_panel_orientation_property -
> - * initialize the connecters panel_orientation property
> - * @connector: connector for which to init the panel-orientation property.
> - * @width: width in pixels of the panel, used for panel quirk detection
> - * @height: height in pixels of the panel, used for panel quirk detection
> + * drm_connector_set_panel_orientation - sets the connecter's
> panel_orientation
> + * @connector: connector for which to set the panel-orientation property.
> + * @panel_orientation: drm_panel_orientation value to set
> + *
> + * This function sets the connector's panel_orientation and attaches
> + * a "panel orientation" property to the connector.
> *
> - * This function should only be called for built-in panels, after setting
> - * connector->display_info.panel_orientation first (if known).
> + * Calling this function on a connector where the panel_orientation has
> + * already been set is a no-op (e.g. the orientation has been overridden with
> + * a kernel commandline option).
> *
> - * This function will check for platform specific (e.g. DMI based) quirks
> - * overriding display_info.panel_orientation first, then if panel_orientation
> - * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
> - * "panel orientation" property to the connector.
> + * It is allowed to call this function with a panel_orientation of
> + * DRM_MODE_PANEL_ORIENTATION_UNKNOWN, in which case it is a no-op.
> *
> * Returns:
> * Zero on success, negative errno on failure.
> */
> -int drm_connector_init_panel_orientation_property(
> - struct drm_connector *connector, int width, int height)
> +int drm_connector_set_panel_orientation(
> + struct drm_connector *connector,
> + enum drm_panel_orientation panel_orientation)
> {
> struct drm_device *dev = connector->dev;
> struct drm_display_info *info = &connector->display_info;
> struct drm_property *prop;
> - int orientation_quirk;
>
> - orientation_quirk = drm_get_panel_orientation_quirk(width, height);
> - if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
> - info->panel_orientation = orientation_quirk;
> + /* Already set? */
> + if (info->panel_orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
> + return 0;
What happens on the scenario of ICL DSI here?
In case we had something badly set we just respect the bad choices?
Any way to at least have some kind of warn when we tried the dsi mode but
it had already been set?
>
> - if (info->panel_orientation == DRM_M
Re: [PATCH resend 1/2] drm/connector: Split out orientation quirk detection (v2)
Hi Rodrigo,
Thank you for the review.
On 02-01-2020 19:17, Rodrigo Vivi wrote:
On Mon, Dec 16, 2019 at 12:51:57PM +0100, Hans de Goede wrote:
From: Derek Basehore
Not every platform needs quirk detection for panel orientation, so
split the drm_connector_init_panel_orientation_property into two
functions. One for platforms without the need for quirks, and the
other for platforms that need quirks.
Hans de Goede (changes in v2):
Rename the function from drm_connector_init_panel_orientation_property
to drm_connector_set_panel_orientation[_with_quirk] and pass in the
panel-orientation to set.
Beside the rename, also make the function set the passed in value
only once, if the value was set before (to a value other then
DRM_MODE_PANEL_ORIENTATION_UNKNOWN) make any further set calls a no-op.
This change is preparation for allowing the user to override the
panel-orientation for any connector from the kernel commandline.
When the panel-orientation is overridden this way, then we must ignore
the panel-orientation detection done by the driver.
Signed-off-by: Derek Basehore
Signed-off-by: Hans de Goede
---
drivers/gpu/drm/drm_connector.c | 74 ++---
drivers/gpu/drm/i915/display/icl_dsi.c | 5 +-
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++-
drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +-
include/drm/drm_connector.h | 9 ++-
5 files changed, 71 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
index 0965632008a9..f4fa5c59717d 100644
--- a/drivers/gpu/drm/drm_connector.c
+++ b/drivers/gpu/drm/drm_connector.c
@@ -1139,7 +1139,8 @@ static const struct drm_prop_enum_list dp_colorspaces[] =
{
*coordinates, so if userspace rotates the picture to adjust for
*the orientation it must also apply the same transformation to the
*touchscreen input coordinates. This property is initialized by calling
- * drm_connector_init_panel_orientation_property().
+ * drm_connector_set_panel_orientation() or
+ * drm_connector_set_panel_orientation_with_quirk()
do we have a better name than quirks for these dsi modes?
The difference between the 2 functions is that the second one calls
drm_get_panel_orientation_quirk() and that if that returns a valid
orientation it overwrites the passed orientation with the return value
from drm_get_panel_orientation_quirk(), so the name seems correct.
As for drm_get_panel_orientation_quirk() itself that currently is only
defined on x86 (it is a static inline no-op elsewhere) and it used
DMI string matching to check for a model specific quirk. So again the
name seems correct.
*
* scaling mode:
*This property defines how a non-native mode is upscaled to the native
@@ -2046,38 +2047,41 @@ void drm_connector_set_vrr_capable_property(
EXPORT_SYMBOL(drm_connector_set_vrr_capable_property);
/**
- * drm_connector_init_panel_orientation_property -
- * initialize the connecters panel_orientation property
- * @connector: connector for which to init the panel-orientation property.
- * @width: width in pixels of the panel, used for panel quirk detection
- * @height: height in pixels of the panel, used for panel quirk detection
+ * drm_connector_set_panel_orientation - sets the connecter's panel_orientation
+ * @connector: connector for which to set the panel-orientation property.
+ * @panel_orientation: drm_panel_orientation value to set
+ *
+ * This function sets the connector's panel_orientation and attaches
+ * a "panel orientation" property to the connector.
*
- * This function should only be called for built-in panels, after setting
- * connector->display_info.panel_orientation first (if known).
+ * Calling this function on a connector where the panel_orientation has
+ * already been set is a no-op (e.g. the orientation has been overridden with
+ * a kernel commandline option).
*
- * This function will check for platform specific (e.g. DMI based) quirks
- * overriding display_info.panel_orientation first, then if panel_orientation
- * is not DRM_MODE_PANEL_ORIENTATION_UNKNOWN it will attach the
- * "panel orientation" property to the connector.
+ * It is allowed to call this function with a panel_orientation of
+ * DRM_MODE_PANEL_ORIENTATION_UNKNOWN, in which case it is a no-op.
*
* Returns:
* Zero on success, negative errno on failure.
*/
-int drm_connector_init_panel_orientation_property(
- struct drm_connector *connector, int width, int height)
+int drm_connector_set_panel_orientation(
+ struct drm_connector *connector,
+ enum drm_panel_orientation panel_orientation)
{
struct drm_device *dev = connector->dev;
struct drm_display_info *info = &connector->display_info;
struct drm_property *prop;
- int orientation_quirk;
- orientation_quirk = drm_get_panel_orientation_quirk(width, height);
- if (orientation_quirk != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
[PATCH v2 0/2] drm: document logging functions
Add kernel-doc for the drm_ and DRM_ logging functions. This is the documentation that I missed when I started to use the logging functions. Version 1 of this patchset included drm_ variants of the existing logging functions - but they are left out for now. The idea is that we should try to use drm_ logging in favour of the the variants that take a device *. This patchset document the existing logging functions with no functional changes. And the documentation is properly wired up in drm-internals.rst Sam Sam Ravnborg (2): drm/print: document drm_ logging functions drm/print: document DRM_ logging functions Documentation/gpu/drm-internals.rst | 6 ++ include/drm/drm_print.h | 164 +--- 2 files changed, 159 insertions(+), 11 deletions(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 1/2] drm/print: document drm_ logging functions
This is the documentation I have missed when I looked for help
how to do proper logging. Hopefully it can help others.
v2:
- Add parameters to the logging functions in the doc
- Drop notes on other types of logging
Signed-off-by: Sam Ravnborg
Cc: Jani Nikula
Cc: Sean Paul
Cc: Daniel Vetter
---
Documentation/gpu/drm-internals.rst | 6 +++
include/drm/drm_print.h | 80 ++---
2 files changed, 79 insertions(+), 7 deletions(-)
diff --git a/Documentation/gpu/drm-internals.rst
b/Documentation/gpu/drm-internals.rst
index a73320576ca9..c2093611999c 100644
--- a/Documentation/gpu/drm-internals.rst
+++ b/Documentation/gpu/drm-internals.rst
@@ -164,6 +164,12 @@ File Operations
Misc Utilities
==
+Logging
+---
+
+.. kernel-doc:: include/drm/drm_print.h
+ :doc: logging
+
Printer
---
diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h
index 8f99d389792d..89e75eea65d2 100644
--- a/include/drm/drm_print.h
+++ b/include/drm/drm_print.h
@@ -250,22 +250,42 @@ static inline struct drm_printer drm_err_printer(const
char *prefix)
}
/**
- * enum drm_debug_category - The DRM debug categories
+ * DOC: logging
+ *
+ * There is a set of functions/macros available used for logging
+ * in the DRM subsystem.
+ * Using the drm logging function enables that the logging is consistently
+ * prefixed with *[drm]* thus the logging is easy to recognize.
+ *
+ * Example of logging with *[drm]* prefix::
*
- * Each of the DRM debug logging macros use a specific category, and the
logging
- * is filtered by the drm.debug module parameter. This enum specifies the
values
- * for the interface.
+ * [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
+ * [drm] Driver supports precise vblank timestamp query.
*
- * Each DRM_DEBUG_ macro logs to DRM_UT_ category, except
- * DRM_DEBUG() logs to DRM_UT_CORE.
+ *
+ * Each of the debug logging macros use a specific category, and the logging
+ * is filtered by the drm.debug module parameter. The &drm_debug_category enum
+ * specifies the values for the interface.
+ *
+ * Each drm_dbg_ macro logs to a DRM_UT_ category,
+ * except drm_dbg() that logs to DRM_UT_DRIVER.
*
* Enabling verbose debug messages is done through the drm.debug parameter,
each
* category being enabled by a bit:
*
* - drm.debug=0x1 will enable CORE messages
* - drm.debug=0x2 will enable DRIVER messages
+ * - drm.debug=0x4 will enable KMS messages
+ * - drm.debug=0x8 will enable PRIME messages
+ * - drm.debug=0x10 will enable ATOMIC messages
+ * - drm.debug=0x20 will enable VBL messages
+ * - drm.debug=0x40 will enable STATE messages
+ * - drm.debug=0x80 will enable LEASE messages
+ * - drm.debug=0x100 will enable DP messages
+ *
+ * To enable more than one category OR the values - examples:
+ *
* - drm.debug=0x3 will enable CORE and DRIVER messages
- * - ...
* - drm.debug=0x1ff will enable all messages
*
* An interesting feature is that it's possible to enable verbose logging at
@@ -273,6 +293,52 @@ static inline struct drm_printer drm_err_printer(const
char *prefix)
*
* # echo 0xf > /sys/module/drm/parameters/debug
*
+ *
+ * When a &drm_device * is available use one of the following logging
functions.
+ * The same prototype is shared by all the logging functions
+ * that take a &drm_device * as first argument:
+ *
+ * .. code-block:: c
+ *
+ * void drm_xxx(struct drm_device *, char * fmt, ...)
+ *
+ * DRM/Drivers can use the following functions for logging.
+ *
+ * .. code-block:: none
+ *
+ * # Plain logging
+ * drm_dbg(drm, fmt, ...)
+ * drm_info(drm, fmt, ...)
+ * drm_notice(drm, fmt, ...)
+ * drm_warn(drm, fmt, ...)
+ * drm_err(drm, fmt, ...)
+ *
+ * # Log only once
+ * drm_info_once(drm, fmt, ...)
+ * drm_notice_once(drm, fmt, ...)
+ * drm_warn_once(drm, fmt, ...)
+ * drm_err_once(drm, fmt, ...)
+ *
+ * # Ratelimited - do not flood the logs
+ * drm_err_ratelimited(drm, fmt, ...)
+ *
+ * # Logging with a specific category
+ * drm_dbg_core(drm, fmt, ...)
+ * drm_dbg(drm, fmt, ...)# Uses the DRIVER category
+ * drm_dbg_kms(drm, fmt, ...)
+ * drm_dbg_prime(drm, fmt, ...)
+ * drm_dbg_atomic(drm, fmt, ...)
+ * drm_dbg_vbl(drm, fmt, ...)
+ * drm_dbg_state(drm, fmt, ...)
+ * drm_dbg_lease(drm, fmt, ...)
+ * drm_dbg_dp(drm, fmt, ...)
+ *
+ * See enum &drm_debug_category for a description of the categories.
+ *
+ */
+
+/**
+ * enum drm_debug_category - The DRM debug categories
*/
enum drm_debug_category {
/**
--
2.20.1
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[PATCH v2 2/2] drm/print: document DRM_ logging functions
Document the remaining DRM_ logging functions. As the logging functions are now all properly listed drop the few specific kernel-doc markers so we keep the relevant parts in the documentation. Signed-off-by: Sam Ravnborg Cc: Jani Nikula Cc: Sean Paul Cc: Daniel Vetter --- include/drm/drm_print.h | 84 +++-- 1 file changed, 80 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_print.h b/include/drm/drm_print.h index 89e75eea65d2..abe247199bf7 100644 --- a/include/drm/drm_print.h +++ b/include/drm/drm_print.h @@ -335,6 +335,82 @@ static inline struct drm_printer drm_err_printer(const char *prefix) * * See enum &drm_debug_category for a description of the categories. * + * Logging when a &device * is available, but no &drm_device * + * ~ + * + * DRM/Drivers can use the following functions for logging when there is a + * struct device * available. + * The logging functions share the same prototype: + * + * .. code-block:: c + * + * void DRM_xxx(struct device *, char * fmt, ...) + * + * .. code-block:: none + * + * # Plain logging + * DRM_DEV_INFO(dev, fmt, ...) + * DRM_DEV_ERROR(dev, fmt, ...) + * + * # Log only once + * DRM_DEV_INFO_ONCE(dev, fmt, ...) + * + * # Ratelimited - do not flood the logs + * DRM_DEV_DEBUG_RATELIMITED(dev, fmt, ...) + * DRM_DEV_DEBUG_DRIVER_RATELIMITED(dev, fmt, ...) + * DRM_DEV_DEBUG_KMS_RATELIMITED(dev, fmt, ...) + * DRM_DEV_DEBUG_PRIME_RATELIMITED(dev, fmt, ...) + * DRM_DEV_ERROR_RATELIMITED(dev, fmt, ...) + * + * # Logging with a specific category + * DRM_DEV_DEBUG(dev, fmt, ...) # Logged as CORE + * DRM_DEV_DEBUG_DRIVER(dev, fmt, ...) + * DRM_DEV_DEBUG_KMS(dev, fmt, ...) + * DRM_DEV_DEBUG_PRIME(dev, fmt, ...) + * DRM_DEV_DEBUG_ATOMIC(dev, fmt, ...) + * DRM_DEV_DEBUG_VBL(dev, fmt, ...) + * DRM_DEV_DEBUG_DP(dev, fmt, ...) + * + * Logging when no &device * nor &drm_device * is available + * + * + * DRM/Drivers can use the following functions for logging when there is no + * extra info associated to the logging. + * The logging functions share the same prototype: + * + * .. code-block:: c + * + * void DRM_xxx(char * fmt, ...) + * + * .. code-block:: none + * + * # Plain logging + * DRM_INFO(fmt, ...) + * DRM_NOTE(fmt, ...) + * DRM_WARN(fmt, ...) + * DRM_ERROR(fmt, ...) + * + * # Log only once + * DRM_INFO_ONCE(fmt, ...) + * DRM_NOTE_ONCE(fmt, ...) + * DRM_WARN_ONCE(fmt, ...) + * + * # Ratelimited - do not flood the logs + * DRM_DEBUG_RATELIMITED(fmt, ...) + * DRM_DEBUG_DRIVER_RATELIMITED(fmt, ...) + * DRM_DEBUG_KMS_RATELIMITED(fmt, ...) + * DRM_DEBUG_PRIME_RATELIMITED(fmt, ...) + * DRM_ERROR_RATELIMITED(fmt, ...) + * + * # Logging with a specific category + * DRM_DEBUG(fmt, ...) # Logged as CORE + * DRM_DEBUG_DRIVER(fmt, ...) + * DRM_DEBUG_KMS(fmt, ...) + * DRM_DEBUG_PRIME(fmt, ...) + * DRM_DEBUG_ATOMIC(fmt, ...) + * DRM_DEBUG_VBL(fmt, ...) + * DRM_DEBUG_LEASE(fmt, ...) + * DRM_DEBUG_DP(fmt, ...) */ /** @@ -399,7 +475,7 @@ __printf(3, 4) void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, const char *format, ...); -/** +/* * Error output. * * @dev: device pointer @@ -408,7 +484,7 @@ void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, #define DRM_DEV_ERROR(dev, fmt, ...) \ drm_dev_printk(dev, KERN_ERR, "*ERROR* " fmt, ##__VA_ARGS__) -/** +/* * Rate limited error output. Like DRM_ERROR() but won't flood the log. * * @dev: device pointer @@ -436,7 +512,7 @@ void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, } \ }) -/** +/* * Debug output. * * @dev: device pointer @@ -466,7 +542,7 @@ void drm_dev_dbg(const struct device *dev, enum drm_debug_category category, drm_dev_dbg(dev, category, fmt, ##__VA_ARGS__); \ }) -/** +/* * Rate limited debug output. Like DRM_DEBUG() but won't flood the log. * * @dev: device pointer -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 4.9 007/171] drm: mst: Fix query_payload ack reply struct
From: Sean Paul
[ Upstream commit 268de6530aa18fe5773062367fd119f0045f6e88 ]
Spec says[1] Allocated_PBN is 16 bits
[1]- DisplayPort 1.2 Spec, Section 2.11.9.8, Table 2-98
Fixes: ad7f8a1f9ced ("drm/helper: add Displayport multi-stream helper (v0.6)")
Cc: Lyude Paul
Cc: Todd Previte
Cc: Dave Airlie
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20190829165223.129662-1-s...@poorly.run
Signed-off-by: Sasha Levin
---
include/drm/drm_dp_mst_helper.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index 003207670597..c0542de64690 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -312,7 +312,7 @@ struct drm_dp_resource_status_notify {
struct drm_dp_query_payload_ack_reply {
u8 port_number;
- u8 allocated_pbn;
+ u16 allocated_pbn;
};
struct drm_dp_sideband_msg_req_body {
--
2.20.1
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[PATCH 4.4 005/137] drm: mst: Fix query_payload ack reply struct
From: Sean Paul
[ Upstream commit 268de6530aa18fe5773062367fd119f0045f6e88 ]
Spec says[1] Allocated_PBN is 16 bits
[1]- DisplayPort 1.2 Spec, Section 2.11.9.8, Table 2-98
Fixes: ad7f8a1f9ced ("drm/helper: add Displayport multi-stream helper (v0.6)")
Cc: Lyude Paul
Cc: Todd Previte
Cc: Dave Airlie
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Lyude Paul
Signed-off-by: Sean Paul
Link:
https://patchwork.freedesktop.org/patch/msgid/20190829165223.129662-1-s...@poorly.run
Signed-off-by: Sasha Levin
---
include/drm/drm_dp_mst_helper.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h
index f356f9716474..674472ac067a 100644
--- a/include/drm/drm_dp_mst_helper.h
+++ b/include/drm/drm_dp_mst_helper.h
@@ -303,7 +303,7 @@ struct drm_dp_resource_status_notify {
struct drm_dp_query_payload_ack_reply {
u8 port_number;
- u8 allocated_pbn;
+ u16 allocated_pbn;
};
struct drm_dp_sideband_msg_req_body {
--
2.20.1
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Re: [RESEND PATCH v6 01/17] dt-bindings: mediatek: add rdma_fifo_size description for mt8183 display
Hi, Yongqiang:
On Fri, 2020-01-03 at 11:12 +0800, Yongqiang Niu wrote:
> Update device tree binding documention for rdma_fifo_size
>
> Signed-off-by: Yongqiang Niu
> ---
> .../devicetree/bindings/display/mediatek/mediatek,disp.txt | 13
> +
> 1 file changed, 13 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 681502e..34bef44 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -70,6 +70,10 @@ Required properties (DMA function blocks):
>argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
>for details.
>
> +Required properties (DMA function blocks):
> +- mediatek,rdma_fifo_size: rdma fifo size may be different even in same SOC,
> add this
> + property to the corresponding rdma
I think "mediatek,rdma_fifo_size" is not a 'required' property. In
mt8173.dtsi [1], there is no mediatek,rdma_fifo_size in rdma0, rdma1,
and rdma2. So I think you should move this to 'optional' property.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.5-rc4
Regards,
CK
> +
> Examples:
>
> mmsys: clock-controller@1400 {
> @@ -211,3 +215,12 @@ od@14023000 {
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_OD>;
> };
> +
> +rdma1: rdma@1400c000 {
> + compatible = "mediatek,mt8183-disp-rdma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = ;
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + mediatek,rdma_fifo_size = <2048>;
> +};
> \ No newline at end of file
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