[PATCH] drm/komeda: Computing layer_split internally
For layer_split no need user to enable/disable it, but compute it in
komeda internally, komeda will enable it if the scaling exceed the
acceptable range of scaler.
Signed-off-by: james qian wang (Arm Technology China)
---
drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h | 3 ++-
.../drm/arm/display/komeda/komeda_pipeline_state.c| 11 ++-
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 3 +--
.../gpu/drm/arm/display/komeda/komeda_wb_connector.c | 10 +-
4 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
index fc1b8613385e..a90bcbb3cb23 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
@@ -537,7 +537,8 @@ void komeda_pipeline_disable(struct komeda_pipeline *pipe,
void komeda_pipeline_update(struct komeda_pipeline *pipe,
struct drm_atomic_state *old_state);
-void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
+void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
+ struct komeda_data_flow_cfg *dflow,
struct drm_framebuffer *fb);
#endif /* _KOMEDA_PIPELINE_H_*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 2b415ef2b7d3..972a0f25254d 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -784,9 +784,11 @@ komeda_timing_ctrlr_validate(struct komeda_timing_ctrlr
*ctrlr,
return 0;
}
-void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
+void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
+ struct komeda_data_flow_cfg *dflow,
struct drm_framebuffer *fb)
{
+ struct komeda_scaler *scaler = layer->base.pipeline->scalers[0];
u32 w = dflow->in_w;
u32 h = dflow->in_h;
@@ -803,6 +805,13 @@ void komeda_complete_data_flow_cfg(struct
komeda_data_flow_cfg *dflow,
dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h);
dflow->is_yuv = fb->format->is_yuv;
+
+ /* try to enable split if scaling exceed the scaler's acceptable
+* input/output range.
+*/
+ if (dflow->en_scaling && scaler)
+ dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
+ !in_range(&scaler->hsize, dflow->out_w);
}
static bool merger_is_available(struct komeda_pipeline *pipe,
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
index 5bb8553cc117..b1386438357b 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
@@ -58,9 +58,8 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
}
dflow->en_img_enhancement = !!kplane_st->img_enhancement;
- dflow->en_split = !!kplane_st->layer_split;
- komeda_complete_data_flow_cfg(dflow, fb);
+ komeda_complete_data_flow_cfg(kplane->layer, dflow, fb);
return 0;
}
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
index bb8a61f6e9a4..617e1f7b8472 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
@@ -13,7 +13,6 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
struct komeda_crtc_state *kcrtc_st,
struct komeda_data_flow_cfg *dflow)
{
- struct komeda_scaler *scaler = wb_layer->base.pipeline->scalers[0];
struct drm_framebuffer *fb = conn_st->writeback_job->fb;
memset(dflow, 0, sizeof(*dflow));
@@ -28,14 +27,7 @@ komeda_wb_init_data_flow(struct komeda_layer *wb_layer,
dflow->pixel_blend_mode = DRM_MODE_BLEND_PIXEL_NONE;
dflow->rot = DRM_MODE_ROTATE_0;
- komeda_complete_data_flow_cfg(dflow, fb);
-
- /* if scaling exceed the acceptable scaler input/output range, try to
-* enable split.
-*/
- if (dflow->en_scaling && scaler)
- dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
- !in_range(&scaler->hsize, dflow->out_w);
+ komeda_complete_data_flow_cfg(wb_layer, dflow, fb);
return 0;
}
--
2.20.1
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[PATCH] drm/komeda: Computing image enhancer internally
Enable image enhancer when the input data flow is 2x+ upscaling.
Signed-off-by: james qian wang (Arm Technology China)
---
drivers/gpu/drm/arm/display/komeda/komeda_kms.h| 7 ++-
drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c | 4
drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 5 -
3 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
index 0c006576a25c..8c89fc245b83 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_kms.h
@@ -47,11 +47,8 @@ struct komeda_plane_state {
/** @zlist_node: zorder list node */
struct list_head zlist_node;
- /* @img_enhancement: on/off image enhancement
-* @layer_split: on/off layer_split
-*/
- u8 img_enhancement : 1,
- layer_split : 1;
+ /** @layer_split: on/off layer_split */
+ u8 layer_split : 1;
};
/**
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
index 972a0f25254d..950235af1e79 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
@@ -806,6 +806,10 @@ void komeda_complete_data_flow_cfg(struct komeda_layer
*layer,
dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h);
dflow->is_yuv = fb->format->is_yuv;
+ /* try to enable image enhancer if data flow is a 2x+ upscaling */
+ dflow->en_img_enhancement = dflow->out_w >= 2 * w ||
+ dflow->out_h >= 2 * h;
+
/* try to enable split if scaling exceed the scaler's acceptable
* input/output range.
*/
diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
index b1386438357b..c095af154216 100644
--- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
+++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
@@ -18,7 +18,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
struct komeda_data_flow_cfg *dflow)
{
struct komeda_plane *kplane = to_kplane(st->plane);
- struct komeda_plane_state *kplane_st = to_kplane_st(st);
struct drm_framebuffer *fb = st->fb;
const struct komeda_format_caps *caps = to_kfb(fb)->format_caps;
struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
@@ -57,8 +56,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
return -EINVAL;
}
- dflow->en_img_enhancement = !!kplane_st->img_enhancement;
-
komeda_complete_data_flow_cfg(kplane->layer, dflow, fb);
return 0;
@@ -174,8 +171,6 @@ komeda_plane_atomic_duplicate_state(struct drm_plane *plane)
old = to_kplane_st(plane->state);
- new->img_enhancement = old->img_enhancement;
-
return &new->base;
}
--
2.20.1
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Re: hmm_range_fault related fixes and legacy API removal v2
On Wed, Jul 03, 2019 at 03:02:08PM -0700, Christoph Hellwig wrote: > Hi Jérôme, Ben and Jason, > > below is a series against the hmm tree which fixes up the mmap_sem > locking in nouveau and while at it also removes leftover legacy HMM APIs > only used by nouveau. As much as I like this series, it won't make it to this merge window, sorry. Let's revisit it in a few weeks at rc1. Regards, Jason ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] Remove unused function drm_agp_bind_pages
---
drivers/gpu/drm/drm_agpsupport.c | 43
include/drm/drm_agpsupport.h | 14 -
2 files changed, 57 deletions(-)
diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c
index 117b8ee98243..8b4e7b1d82e4 100644
--- a/drivers/gpu/drm/drm_agpsupport.c
+++ b/drivers/gpu/drm/drm_agpsupport.c
@@ -465,46 +465,3 @@ void drm_legacy_agp_clear(struct drm_device *dev)
dev->agp->acquired = 0;
dev->agp->enabled = 0;
}
-
-/**
- * Binds a collection of pages into AGP memory at the given offset, returning
- * the AGP memory structure containing them.
- *
- * No reference is held on the pages during this time -- it is up to the
- * caller to handle that.
- */
-struct agp_memory *
-drm_agp_bind_pages(struct drm_device *dev,
- struct page **pages,
- unsigned long num_pages,
- uint32_t gtt_offset,
- u32 type)
-{
- struct agp_memory *mem;
- int ret, i;
-
- DRM_DEBUG("\n");
-
- mem = agp_allocate_memory(dev->agp->bridge, num_pages,
- type);
- if (mem == NULL) {
- DRM_ERROR("Failed to allocate memory for %ld pages\n",
- num_pages);
- return NULL;
- }
-
- for (i = 0; i < num_pages; i++)
- mem->pages[i] = pages[i];
- mem->page_count = num_pages;
-
- mem->is_flushed = true;
- ret = agp_bind_memory(mem, gtt_offset / PAGE_SIZE);
- if (ret != 0) {
- DRM_ERROR("Failed to bind AGP memory: %d\n", ret);
- agp_free_memory(mem);
- return NULL;
- }
-
- return mem;
-}
-EXPORT_SYMBOL(drm_agp_bind_pages);
diff --git a/include/drm/drm_agpsupport.h b/include/drm/drm_agpsupport.h
index b05e462276d5..664e120b93e6 100644
--- a/include/drm/drm_agpsupport.h
+++ b/include/drm/drm_agpsupport.h
@@ -31,11 +31,6 @@ struct drm_agp_head {
void drm_free_agp(struct agp_memory * handle, int pages);
int drm_bind_agp(struct agp_memory * handle, unsigned int start);
int drm_unbind_agp(struct agp_memory * handle);
-struct agp_memory *drm_agp_bind_pages(struct drm_device *dev,
- struct page **pages,
- unsigned long num_pages,
- uint32_t gtt_offset,
- uint32_t type);
struct drm_agp_head *drm_agp_init(struct drm_device *dev);
void drm_legacy_agp_clear(struct drm_device *dev);
@@ -80,15 +75,6 @@ static inline int drm_unbind_agp(struct agp_memory * handle)
return -ENODEV;
}
-static inline struct agp_memory *drm_agp_bind_pages(struct drm_device *dev,
- struct page **pages,
- unsigned long num_pages,
- uint32_t gtt_offset,
- uint32_t type)
-{
- return NULL;
-}
-
static inline struct drm_agp_head *drm_agp_init(struct drm_device *dev)
{
return NULL;
--
2.11.0
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[PATCH] gpu: drm: pl111: pl111_vexpress.c: Add of_node_put() before return
Each iteration of for_each_available_child_of_node puts the previous
node, but in the case of a break from the middle of the loop there is
no put, thus causing a memory leak. Hence add an of_node_put before the
break.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta
---
drivers/gpu/drm/pl111/pl111_vexpress.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/pl111/pl111_vexpress.c
b/drivers/gpu/drm/pl111/pl111_vexpress.c
index 38c938c9adda..350570fe06b5 100644
--- a/drivers/gpu/drm/pl111/pl111_vexpress.c
+++ b/drivers/gpu/drm/pl111/pl111_vexpress.c
@@ -51,6 +51,7 @@ int pl111_vexpress_clcd_init(struct device *dev,
}
if (of_device_is_compatible(child, "arm,hdlcd")) {
has_coretile_hdlcd = true;
+ of_node_put(child);
break;
}
}
--
2.19.1
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[PATCH] gpu: drm: mediatek: mtk_drm_drv.c: Add of_node_put() before goto
Each iteration of for_each_child_of_node puts the previous
node, but in the case of a goto from the middle of the loop, there is
no put, thus causing a memory leak. Hence add an of_node_put before the
goto in two places.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 95fdbd0fbcac..2dffbc8c6d73 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -524,12 +524,15 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
if (!comp) {
ret = -ENOMEM;
+ of_node_put(node);
goto err_node;
}
ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
- if (ret)
+ if (ret) {
+ of_node_put(node);
goto err_node;
+ }
private->ddp_comp[comp_id] = comp;
}
--
2.19.1
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Re: Why is Thunderbolt 3 limited to 2.5 GT/s on Linux?
On Friday, 5 July 2019, Marek Olšák wrote: > On Fri, Jul 5, 2019 at 5:27 AM Timur Kristóf > wrote: > > > On Wed, 2019-07-03 at 14:44 -0400, Marek Olšák wrote: > > > You can run: > > > AMD_DEBUG=testdmaperf glxgears > > > > > > It tests transfer sizes of up to 128 MB, and it tests ~60 slightly > > > different methods of transfering data. > > > > > > Marek > > > > > > Thanks Marek, I didn't know about that option. > > Tried it, here is the output: https://pastebin.com/raw/9SAAbbAA > > > > I'm not quite sure how to interpret the numbers, they are inconsistent > > with the results from both pcie_bw and amdgpu.benchmark, for example > > GTT->VRAM at a 128 KB is around 1400 MB/s (I assume that is megabytes / > > sec, right?). > > > > Based on the SDMA results, you have 2.4 GB/s. For 128KB, it's 2.2 GB/s for > GTT->VRAM copies. > > Marek That's interesting, AFAIU that would be 17.6 Gbit/sec. But how can that be so much faster than the 5 Gbit/sec result from amdgpu.benchmark? ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v5 05/12] drm/modes: Rewrite the command line parser
17.06.2019 17:51, Maxime Ripard пишет: > From: Maxime Ripard > > Rewrite the command line parser in order to get away from the state machine > parsing the video mode lines. > > Hopefully, this will allow to extend it more easily to support named modes > and / or properties set directly on the command line. > > Reviewed-by: Noralf Trønnes > Signed-off-by: Maxime Ripard > --- > drivers/gpu/drm/drm_modes.c | 325 +++-- > 1 file changed, 210 insertions(+), 115 deletions(-) Hello, I have a Tegra device that uses a stock android bootloader which passes "video=tegrafb" in the kernels cmdline. That wasn't a problem before this patch, but now Tegra DRM driver fails to probe because the mode is 0x0:0 and hence framebuffer allocation fails. Is it a legit regression that should be fixed in upstream? ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 2/2] drm/komeda: Computing layer_split and image_enhancer internally
On Fri, Jul 05, 2019 at 02:25:46PM +0200, Daniel Vetter wrote:
> On Fri, Jul 05, 2019 at 11:44:45AM +, james qian wang (Arm Technology
> China) wrote:
> > For layer_split:
> > Enable it if the scaling exceed the accept range of scaler.
> >
> > For image_enhancer:
> > Enable it if the scaling is a 2x+ scaling
>
> Imo should be two patches. Aside from that (and with 0 knowledge about the
> hw, just looking at this from a kms/atomic uapi pov):
>
> Acked-by: Daniel Vetter
Hi Daniel:
I split this change to two patches, please ignore this one, and please
help to review the below sparated ones:
- https://patchwork.freedesktop.org/series/63340/ for layer_split
- https://patchwork.freedesktop.org/series/63341/ for image enhancer
Thanks
James
> >
> > Signed-off-by: james qian wang (Arm Technology China)
> >
> > ---
> > .../gpu/drm/arm/display/komeda/komeda_pipeline.h | 3 ++-
> > .../arm/display/komeda/komeda_pipeline_state.c| 15 ++-
> > drivers/gpu/drm/arm/display/komeda/komeda_plane.c | 8 +---
> > .../drm/arm/display/komeda/komeda_wb_connector.c | 10 +-
> > 4 files changed, 18 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> > b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> > index fc1b8613385e..a90bcbb3cb23 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h
> > @@ -537,7 +537,8 @@ void komeda_pipeline_disable(struct komeda_pipeline
> > *pipe,
> > void komeda_pipeline_update(struct komeda_pipeline *pipe,
> > struct drm_atomic_state *old_state);
> >
> > -void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
> > +void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
> > + struct komeda_data_flow_cfg *dflow,
> > struct drm_framebuffer *fb);
> >
> > #endif /* _KOMEDA_PIPELINE_H_*/
> > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
> > b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
> > index 2b415ef2b7d3..709870bdaa4f 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c
> > @@ -784,9 +784,11 @@ komeda_timing_ctrlr_validate(struct
> > komeda_timing_ctrlr *ctrlr,
> > return 0;
> > }
> >
> > -void komeda_complete_data_flow_cfg(struct komeda_data_flow_cfg *dflow,
> > +void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
> > + struct komeda_data_flow_cfg *dflow,
> > struct drm_framebuffer *fb)
> > {
> > +struct komeda_scaler *scaler = layer->base.pipeline->scalers[0];
> > u32 w = dflow->in_w;
> > u32 h = dflow->in_h;
> >
> > @@ -803,6 +805,17 @@ void komeda_complete_data_flow_cfg(struct
> > komeda_data_flow_cfg *dflow,
> >
> > dflow->en_scaling = (w != dflow->out_w) || (h != dflow->out_h);
> > dflow->is_yuv = fb->format->is_yuv;
> > +
> > +/* try to enable image enhancer if it is a 2x+ upscaling */
> > +dflow->en_img_enhancement = dflow->out_w >= 2 * w ||
> > +dflow->out_h >= 2 * h;
> > +
> > +/* try to enable split if scaling exceed the scaler's acceptable
> > + * input/output range.
> > + */
> > +if (dflow->en_scaling && scaler)
> > +dflow->en_split = !in_range(&scaler->hsize, dflow->in_w) ||
> > + !in_range(&scaler->hsize, dflow->out_w);
> > }
> >
> > static bool merger_is_available(struct komeda_pipeline *pipe,
> > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
> > b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
> > index 5bb8553cc117..c095af154216 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_plane.c
> > @@ -18,7 +18,6 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
> > struct komeda_data_flow_cfg *dflow)
> > {
> > struct komeda_plane *kplane = to_kplane(st->plane);
> > -struct komeda_plane_state *kplane_st = to_kplane_st(st);
> > struct drm_framebuffer *fb = st->fb;
> > const struct komeda_format_caps *caps = to_kfb(fb)->format_caps;
> > struct komeda_pipeline *pipe = kplane->layer->base.pipeline;
> > @@ -57,10 +56,7 @@ komeda_plane_init_data_flow(struct drm_plane_state *st,
> > return -EINVAL;
> > }
> >
> > -dflow->en_img_enhancement = !!kplane_st->img_enhancement;
> > -dflow->en_split = !!kplane_st->layer_split;
> > -
> > -komeda_complete_data_flow_cfg(dflow, fb);
> > +komeda_complete_data_flow_cfg(kplane->layer, dflow, fb);
> >
> > return 0;
> > }
> > @@ -175,8 +171,6 @@ komeda_plane_atomic_duplicate_state(struct drm_plane
> > *plane)
> >
> > old = to_kplane_st(plane->state);
> >
> > -new->img_enhancement = old->img_enhancement;
> > -
> > return &new->base;
> > }
> >
> > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
> > b/drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c
> > index bb8a61f6e9a4..617e1f7b8472 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/komeda_wb_co
[Bug 102322] System crashes after "[drm] IP block:gmc_v8_0 is hung!" / [drm] IP block:sdma_v3_0 is hung!
https://bugs.freedesktop.org/show_bug.cgi?id=102322 --- Comment #83 from Wilko Bartels --- (In reply to Jaap Buurman from comment #81) > issue seems to be using a setup that requires higher engine clocks in idle > AFAIK. Either high refresh displays, or in my case, multiple monitors. Could > this be part of the issue that seems to trigger this bug? I might be > grasping at straws here, but I have had this problem for as long as I have > this Vega64 (bought at launch), while it is 100% stable under Windows 10 in > the same setup. This might be true. I was running i3 with xrandr set to 144hz when the freeze scenario began (somewhat last mont, did not "game" much before). Than switched to icewm to test and issue was gone. Later when i configured icewm to also have proper xrandr setting issue comes back. I didnt know that could be related. Will test this tonight. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 01/19] dt-bindings: display: renesas,cmm: Add R-Car CMM documentation
Hi Jacopo,
On Sat, Jul 6, 2019 at 4:07 PM Jacopo Mondi wrote:
> Add device tree bindings documentation for the Renesas R-Car Display
> Unit Color Management Module.
>
> CMM is the image enhancement module available on each R-Car DU video
> channel on R-Car Gen2 and Gen3 SoCs (V3H and V3M excluded).
>
> Signed-off-by: Jacopo Mondi
> Reviewed-by: Laurent Pinchart
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/renesas,cmm.txt
> @@ -0,0 +1,25 @@
> +* Renesas R-Car Color Management Module (CMM)
> +
> +Renesas R-Car image enhancement module connected to R-Car DU video channels.
> +
> +Required properties:
> + - compatible: shall be one of:
> + - "renesas,rcar-gen3-cmm"
> + - "renesas,rcar-gen2-cmm"
Why do you think you do not need SoC-specific compatible values?
What if you discover a different across the R-Car Gen3 line tomorrow?
Does the IP block have a version register?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH] Remove unused function drm_agp_bind_pages
Hi Maya. Nice catch - good to remove unused cruft. Please prefix the subject with something like "drm/agp: ". Check "git log" on the same file to pick up the usual way to identify agp specific changes. With this fixed: Reviewed-by: Sam Ravnborg You could also consider to add a few words in the body of the changelog how the unused function was identified. Sam ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110514] [CI][BAT] igt@* - skip - Test requirement: is_i915_device(fd) && has_known_intel_chipset(fd), Skip
https://bugs.freedesktop.org/show_bug.cgi?id=110514 --- Comment #25 from CI Bug Log --- The CI Bug Log issue associated to this bug has been archived. New failures matching the above filters will not be associated to this bug anymore. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [Bug 111082] Severe stutter in CS:GO surf servers, despite ~300fps
On Mon, Jul 08, 2019 at 03:20:44AM +, bugzilla-dae...@freedesktop.org wrote: > How is this not a graphics driver bug? He meant it could be a game engine bug (network or 3D, very probably). You are both right. CSGO 3D engine on based linux OSes is really bad if you use maps which are not in the competitive set. For instance, danger zone open maps, on my system, have disastrous performance... and it is CPU related, not GPU, even though I have 8 core at 4.7Ghz (something is really wrong or litteraly CPU capped somewhere). -- Sylvain ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111082] Severe stutter in CS:GO surf servers, despite ~300fps
https://bugs.freedesktop.org/show_bug.cgi?id=111082 --- Comment #3 from Sylvain BERTRAND --- On Mon, Jul 08, 2019 at 03:20:44AM +, bugzilla-dae...@freedesktop.org wrote: > How is this not a graphics driver bug? He meant it could be a game engine bug (network or 3D, very probably). You are both right. CSGO 3D engine on based linux OSes is really bad if you use maps which are not in the competitive set. For instance, danger zone open maps, on my system, have disastrous performance... and it is CPU related, not GPU, even though I have 8 core at 4.7Ghz (something is really wrong or litteraly CPU capped somewhere). -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8 1/6] drm: Add Content protection type property
On Fri, 5 Jul 2019 06:16:37 +0530
Ramalingam C wrote:
> This patch adds a DRM ENUM property to the selected connectors.
> This property is used for mentioning the protected content's type
> from userspace to kernel HDCP authentication.
>
> Type of the stream is decided by the protected content providers.
> Type 0 content can be rendered on any HDCP protected display wires.
> But Type 1 content can be rendered only on HDCP2.2 protected paths.
>
> So when a userspace sets this property to Type 1 and starts the HDCP
> enable, kernel will honour it only if HDCP2.2 authentication is through
> for type 1. Else HDCP enable will be failed.
>
> Need ACK for this new conenctor property from userspace consumer.
>
> v2:
> cp_content_type is replaced with content_protection_type [daniel]
> check at atomic_set_property is removed [Maarten]
> v3:
> %s/content_protection_type/hdcp_content_type [Pekka]
> v4:
> property is created for the first requested connector and then reused.
> [Danvet]
> v5:
> kernel doc nits addressed [Daniel]
> Rebased as part of patch reordering.
> v6:
> Kernel docs are modified [pekka]
>
> Signed-off-by: Ramalingam C
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
> drivers/gpu/drm/drm_connector.c | 22 ++
> drivers/gpu/drm/drm_hdcp.c| 36 ++-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
> include/drm/drm_connector.h | 7 +
> include/drm/drm_hdcp.h| 2 +-
> include/drm/drm_mode_config.h | 6
> include/uapi/drm/drm_mode.h | 4 +++
> 8 files changed, 82 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index abe38bdf85ae..19ae119f1a5d 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -747,6 +747,8 @@ static int drm_atomic_connector_set_property(struct
> drm_connector *connector,
> return -EINVAL;
> }
> state->content_protection = val;
> + } else if (property == config->hdcp_content_type_property) {
> + state->hdcp_content_type = val;
> } else if (property == connector->colorspace_property) {
> state->colorspace = val;
> } else if (property == config->writeback_fb_id_property) {
> @@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct drm_connector
> *connector,
> state->hdr_output_metadata->base.id : 0;
> } else if (property == config->content_protection_property) {
> *val = state->content_protection;
> + } else if (property == config->hdcp_content_type_property) {
> + *val = state->hdcp_content_type;
> } else if (property == config->writeback_fb_id_property) {
> /* Writeback framebuffer is one-shot, write and forget */
> *val = 0;
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index 068d4b05f1be..17aef88c03a6 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -951,6 +951,28 @@ static const struct drm_prop_enum_list
> hdmi_colorspaces[] = {
> * the value transitions from ENABLED to DESIRED. This signifies the link
> * is no longer protected and userspace should take appropriate action
> * (whatever that might be).
> + * HDCP Content Type:
> + * This property is used by the userspace to configure the kernel with
> + * to be displayed stream's content type. Content Type of a stream is
> + * decided by the owner of the stream, as "HDCP Type0" or "HDCP Type1".
> + *
> + * The value of the property can be one the below:
> + * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> + * HDCP Type0 streams can be transmitted on a link which is
> + * encrypted with HDCP 1.4 or higher versions of HDCP(i.e HDCP2.2
> + * and more).
> + * - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
> + * HDCP Type1 streams can be transmitted on a link which is
> + * encrypted only with HDCP 2.2. In future higher versions also
> + * might support Type1 based on their spec.
> + *
> + * Note that the HDCP Content Type property is introduced at HDCP 2.2, and
> + * defaults to type 0. It is only exposed by drivers supporting HDCP 2.2.
> + * Based on how next versions of HDCP specs are defined content Type could
> + * be used for higher versions too.
> + * If content type is changed when content_protection is not UNDESIRED,
> + * then kernel will disable the HDCP and re-enable with new type in the
> + * same atomic commit
Hi,
I think this doc covers all my previous comments on this patch now. One
more thing, the wording here reads as:
- userspace configures the content type
- the kernel transmits the content if the link satisfies the type
Re: [PATCH v8 1/6] drm: Add Content protection type property
On Mon, 8 Jul 2019 12:52:17 +0300
Pekka Paalanen wrote:
> On Fri, 5 Jul 2019 06:16:37 +0530
> Ramalingam C wrote:
>
> > This patch adds a DRM ENUM property to the selected connectors.
> > This property is used for mentioning the protected content's type
> > from userspace to kernel HDCP authentication.
> >
> > Type of the stream is decided by the protected content providers.
> > Type 0 content can be rendered on any HDCP protected display wires.
> > But Type 1 content can be rendered only on HDCP2.2 protected paths.
> >
> > So when a userspace sets this property to Type 1 and starts the HDCP
> > enable, kernel will honour it only if HDCP2.2 authentication is through
> > for type 1. Else HDCP enable will be failed.
> >
> > Need ACK for this new conenctor property from userspace consumer.
> >
> > v2:
> > cp_content_type is replaced with content_protection_type [daniel]
> > check at atomic_set_property is removed [Maarten]
> > v3:
> > %s/content_protection_type/hdcp_content_type [Pekka]
> > v4:
> > property is created for the first requested connector and then reused.
> > [Danvet]
> > v5:
> > kernel doc nits addressed [Daniel]
> > Rebased as part of patch reordering.
> > v6:
> > Kernel docs are modified [pekka]
> >
> > Signed-off-by: Ramalingam C
> > Reviewed-by: Daniel Vetter
> > ---
> > drivers/gpu/drm/drm_atomic_uapi.c | 4 +++
> > drivers/gpu/drm/drm_connector.c | 22 ++
> > drivers/gpu/drm/drm_hdcp.c| 36 ++-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++-
> > include/drm/drm_connector.h | 7 +
> > include/drm/drm_hdcp.h| 2 +-
> > include/drm/drm_mode_config.h | 6
> > include/uapi/drm/drm_mode.h | 4 +++
> > 8 files changed, 82 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_atomic_uapi.c
> > b/drivers/gpu/drm/drm_atomic_uapi.c
> > index abe38bdf85ae..19ae119f1a5d 100644
> > --- a/drivers/gpu/drm/drm_atomic_uapi.c
> > +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> > @@ -747,6 +747,8 @@ static int drm_atomic_connector_set_property(struct
> > drm_connector *connector,
> > return -EINVAL;
> > }
> > state->content_protection = val;
> > + } else if (property == config->hdcp_content_type_property) {
> > + state->hdcp_content_type = val;
> > } else if (property == connector->colorspace_property) {
> > state->colorspace = val;
> > } else if (property == config->writeback_fb_id_property) {
> > @@ -831,6 +833,8 @@ drm_atomic_connector_get_property(struct drm_connector
> > *connector,
> > state->hdr_output_metadata->base.id : 0;
> > } else if (property == config->content_protection_property) {
> > *val = state->content_protection;
> > + } else if (property == config->hdcp_content_type_property) {
> > + *val = state->hdcp_content_type;
> > } else if (property == config->writeback_fb_id_property) {
> > /* Writeback framebuffer is one-shot, write and forget */
> > *val = 0;
> > diff --git a/drivers/gpu/drm/drm_connector.c
> > b/drivers/gpu/drm/drm_connector.c
> > index 068d4b05f1be..17aef88c03a6 100644
> > --- a/drivers/gpu/drm/drm_connector.c
> > +++ b/drivers/gpu/drm/drm_connector.c
> > @@ -951,6 +951,28 @@ static const struct drm_prop_enum_list
> > hdmi_colorspaces[] = {
> > * the value transitions from ENABLED to DESIRED. This signifies the link
> > * is no longer protected and userspace should take appropriate action
> > * (whatever that might be).
> > + * HDCP Content Type:
> > + * This property is used by the userspace to configure the kernel with
> > + * to be displayed stream's content type. Content Type of a stream is
> > + * decided by the owner of the stream, as "HDCP Type0" or "HDCP Type1".
> > + *
> > + * The value of the property can be one the below:
> > + * - "HDCP Type0": DRM_MODE_HDCP_CONTENT_TYPE0 = 0
> > + * HDCP Type0 streams can be transmitted on a link which is
> > + * encrypted with HDCP 1.4 or higher versions of HDCP(i.e HDCP2.2
> > + * and more).
> > + * - "HDCP Type1": DRM_MODE_HDCP_CONTENT_TYPE1 = 1
> > + * HDCP Type1 streams can be transmitted on a link which is
> > + * encrypted only with HDCP 2.2. In future higher versions also
> > + * might support Type1 based on their spec.
> > + *
> > + * Note that the HDCP Content Type property is introduced at HDCP 2.2, and
> > + * defaults to type 0. It is only exposed by drivers supporting HDCP 2.2.
> > + * Based on how next versions of HDCP specs are defined content Type could
> > + * be used for higher versions too.
> > + * If content type is changed when content_protection is not UNDESIRED,
> > + * then kernel will disable the HDCP and re-enable with new type in the
> > + * same atomic commit
>
> Hi,
>
> I think this doc cover
Re: [PATCH v8 4/6] drm/hdcp: update content protection property with uevent
On Fri, 5 Jul 2019 06:16:40 +0530
Ramalingam C wrote:
> drm function is defined and exported to update a connector's
> content protection property state and to generate a uevent along
> with it.
>
> Need ACK for the uevent from userspace consumer.
>
> v2:
> Update only when state is different from old one.
> v3:
> KDoc is added [Daniel]
> v4:
> KDoc is extended bit more [pekka]
>
> Signed-off-by: Ramalingam C
> Reviewed-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_hdcp.c | 34 ++
> include/drm/drm_hdcp.h | 2 ++
> 2 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c
> index ce235fd1c844..77433ee3d652 100644
> --- a/drivers/gpu/drm/drm_hdcp.c
> +++ b/drivers/gpu/drm/drm_hdcp.c
> @@ -374,6 +374,10 @@ DRM_ENUM_NAME_FN(drm_get_hdcp_content_type_name,
> *
> * The content protection will be set to
> &drm_connector_state.content_protection
> *
> + * When kernel triggered content protection state change like
> DESIRED->ENABLED
> + * and ENABLED->DESIRED, will use drm_hdcp_update_content_protection() to
> update
> + * the content protection state of a connector.
> + *
> * Returns:
> * Zero on success, negative errno on failure.
> */
> @@ -414,3 +418,33 @@ int drm_connector_attach_content_protection_property(
> return 0;
> }
> EXPORT_SYMBOL(drm_connector_attach_content_protection_property);
> +
> +/**
> + * drm_hdcp_update_content_protection - Updates the content protection state
> + * of a connector
> + *
> + * @connector: drm_connector on which content protection state needs an
> update
> + * @val: New state of the content protection property
> + *
> + * This function can be used by display drivers, to update the kernel
> triggered
> + * content protection state changes of a drm_connector such as
> DESIRED->ENABLED
> + * and ENABLED->DESIRED. No uevent for DESIRED->UNDESIRED or
> ENABLED->UNDESIRED,
> + * as userspace is triggering such state change and kernel performs it
> without
> + * fail.This function update the new state of the property into the
> connector's
> + * state and generate an uevent to notify the userspace.
> + */
Hi,
this patch is not yet adding the documentation I asked for.
The uevent behaviour needs to be also documented with the Content
Protection property description. No userspace developer will know to
come to dig up these kernel-internal functions.
> +void drm_hdcp_update_content_protection(struct drm_connector *connector,
> + u64 val)
> +{
> + struct drm_device *dev = connector->dev;
> + struct drm_connector_state *state = connector->state;
> +
> + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
Still missing WARN_ON(val == UNDESIRED) to prevent other drivers from
making that mistake in the future.
Thanks,
pq
> + if (state->content_protection == val)
> + return;
> +
> + state->content_protection = val;
> + drm_sysfs_connector_status_event(connector,
> + dev->mode_config.content_protection_property);
> +}
> +EXPORT_SYMBOL(drm_hdcp_update_content_protection);
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index 2970abdfaf12..dd864ac9ce85 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -292,4 +292,6 @@ bool drm_hdcp_check_ksvs_revoked(struct drm_device *dev,
>u8 *ksvs, u32 ksv_count);
> int drm_connector_attach_content_protection_property(
> struct drm_connector *connector, bool hdcp_content_type);
> +void drm_hdcp_update_content_protection(struct drm_connector *connector,
> + u64 val);
> #endif
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Re: [PATCH v8 6/6] drm/hdcp: reference for srm file format
On Fri, 5 Jul 2019 06:16:42 +0530 Ramalingam C wrote: > In the kernel documentation, HDCP specifications links are shared as a > reference for SRM table format. > > Signed-off-by: Ramalingam C > --- > drivers/gpu/drm/drm_hdcp.c | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/drm_hdcp.c b/drivers/gpu/drm/drm_hdcp.c > index 77433ee3d652..803bf8283b83 100644 > --- a/drivers/gpu/drm/drm_hdcp.c > +++ b/drivers/gpu/drm/drm_hdcp.c > @@ -271,6 +271,13 @@ static void drm_hdcp_request_srm(struct drm_device > *drm_dev) > * > * SRM should be presented in the name of "display_hdcp_srm.bin". > * > + * Format of the SRM table that userspace needs to write into the binary file > + * is defined at > + * 1. Renewability chapter on 55th page of HDCP 1.4 specification > + * > https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secure.pdf > + * 2. Renewability chapter on 63rd page of HDCP 2.2 specification > + * > https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%20Rev2_2_Final1.pdf > + * > * Returns: > * TRUE on any of the KSV is revoked, else FALSE. > */ Hi, this look good, publicly accessible spec links even. I'm happy with this, but I repeat that the Weston work[1] does not directly prove this UAPI (perhaps not necessary either?). [1] https://gitlab.freedesktop.org/wayland/weston/merge_requests/48 Thanks, pq pgpx2UnhFwKWV.pgp Description: OpenPGP digital signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 0/4] Add a generic driver for LED-based backlight
This series aims to add a led-backlight driver, similar to pwm-backlight, but using a LED class device underneath. A few years ago (2015), Tomi Valkeinen posted a series implementing a backlight driver on top of a LED device: https://patchwork.kernel.org/patch/7293991/ https://patchwork.kernel.org/patch/7294001/ https://patchwork.kernel.org/patch/7293981/ The discussion stopped because Tomi lacked the time to work on it. The series affects the LED core and add a new backlight driver. changes in v2: - bkl: the backlight can use more than one LED. As a consequence don't make the backlight device a child of a LED controller. - bkl: make brightness-levels and default-brightness-level optional - bkl: removed the option to use a GPIO enable. - bkl: removed the option to use a regulator. It should be handled by the LED core - led: removed the mechanism to bind a child device for each LED - led: improve the way of_get_led() works and add a managed version of it Jean-Jacques Hiblot (2): leds: Add managed API to get a LED from a device driver dt-bindings: backlight: Add led-backlight binding Tomi Valkeinen (2): leds: Add of_led_get() and led_put() backlight: add led-backlight driver .../bindings/leds/backlight/led-backlight.txt | 29 +++ drivers/leds/led-class.c | 92 +++ drivers/video/backlight/Kconfig | 7 + drivers/video/backlight/Makefile | 1 + drivers/video/backlight/led_bl.c | 235 ++ include/linux/leds.h | 6 + 6 files changed, 370 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/backlight/led-backlight.txt create mode 100644 drivers/video/backlight/led_bl.c -- 2.17.1
[PATCH v2 1/4] leds: Add of_led_get() and led_put()
From: Tomi Valkeinen
This patch adds basic support for a kernel driver to get a LED device.
This will be used by the led-backlight driver.
Only OF version is implemented for now, and the behavior is similar to
PWM's of_pwm_get() and pwm_put().
Signed-off-by: Tomi Valkeinen
Signed-off-by: Jean-Jacques Hiblot
---
drivers/leds/led-class.c | 50
include/linux/leds.h | 4
2 files changed, 54 insertions(+)
diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
index e01b2d982564..0f67b13b0f1f 100644
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
#include "leds.h"
static struct class *leds_class;
@@ -214,6 +215,55 @@ static int led_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(leds_class_dev_pm_ops, led_suspend, led_resume);
+static int led_match_led_node(struct device *led_dev, const void *data)
+{
+ return led_dev->of_node == data ? 1 : 0;
+}
+
+/**
+ * of_led_get() - request a LED device via the LED framework
+ * @np: device node to get the LED device from
+ * @index: the index of the LED
+ *
+ * Returns the LED device parsed from the phandle specified in the "leds"
+ * property of a device tree node or a negative error-code on failure.
+ */
+struct led_classdev *of_led_get(struct device_node *np, int index)
+{
+ struct device *led_dev;
+ struct led_classdev *led_cdev;
+ struct device_node *led_node;
+
+ led_node = of_parse_phandle(np, "leds", index);
+ if (!led_node)
+ return ERR_PTR(-ENOENT);
+
+ led_dev = class_find_device(leds_class, NULL, led_node,
+ led_match_led_node);
+ of_node_put(led_node);
+
+ if (!led_dev)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ led_cdev = dev_get_drvdata(led_dev);
+
+ if (!try_module_get(led_cdev->dev->parent->driver->owner))
+ return ERR_PTR(-ENODEV);
+
+ return led_cdev;
+}
+EXPORT_SYMBOL_GPL(of_led_get);
+
+/**
+ * led_put() - release a LED device
+ * @led_cdev: LED device
+ */
+void led_put(struct led_classdev *led_cdev)
+{
+ module_put(led_cdev->dev->parent->driver->owner);
+}
+EXPORT_SYMBOL_GPL(led_put);
+
static int match_name(struct device *dev, const void *data)
{
if (!dev_name(dev))
diff --git a/include/linux/leds.h b/include/linux/leds.h
index bee8e3f8..0a71c7cdd191 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -19,6 +19,7 @@
struct device;
struct led_pattern;
+struct device_node;
/*
* LED Core
*/
@@ -145,6 +146,9 @@ extern void devm_led_classdev_unregister(struct device
*parent,
extern void led_classdev_suspend(struct led_classdev *led_cdev);
extern void led_classdev_resume(struct led_classdev *led_cdev);
+extern struct led_classdev *of_led_get(struct device_node *np, int index);
+extern void led_put(struct led_classdev *led_cdev);
+
/**
* led_blink_set - set blinking with software fallback
* @led_cdev: the LED to start blinking
--
2.17.1
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[PATCH v2 2/4] leds: Add managed API to get a LED from a device driver
If the LED is acquired by a consumer device with devm_led_get(), it is
automatically release when the device is detach.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/leds/led-class.c | 42
include/linux/leds.h | 2 ++
2 files changed, 44 insertions(+)
diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
index 0f67b13b0f1f..521cb76fbaf7 100644
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -264,6 +264,48 @@ void led_put(struct led_classdev *led_cdev)
}
EXPORT_SYMBOL_GPL(led_put);
+static void devm_led_release(struct device *dev, void *res)
+{
+ struct led_classdev **p = res;
+
+ led_put(*p);
+}
+
+/**
+ * devm_led_get - Resource-managed request of a LED device
+ * @dev: LED consumer
+ * @idx: index of the LED to obtain in the consumer
+ *
+ * The device node of the device is parse to find the request LED device.
+ * The LED device returned from this function is automatically released
+ * on driver detach.
+ *
+ * @return a pointer to a LED device or ERR_PTR(errno) on failure.
+ */
+struct led_classdev *__must_check devm_led_get(struct device *dev,
+ int index)
+{
+ struct led_classdev *led;
+ struct led_classdev **dr;
+
+ led = of_led_get(dev->of_node, index);
+ if (IS_ERR(led))
+ return led;
+
+ dr = devres_alloc(devm_led_release, sizeof(struct led_classdev *),
+ GFP_KERNEL);
+ if (!dr) {
+ led_put(led);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ *dr = led;
+ devres_add(dev, dr);
+
+ return led;
+}
+EXPORT_SYMBOL_GPL(devm_led_get);
+
static int match_name(struct device *dev, const void *data)
{
if (!dev_name(dev))
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 0a71c7cdd191..7fcec566d774 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -148,6 +148,8 @@ extern void led_classdev_resume(struct led_classdev
*led_cdev);
extern struct led_classdev *of_led_get(struct device_node *np, int index);
extern void led_put(struct led_classdev *led_cdev);
+struct led_classdev *__must_check devm_led_get(struct device *dev,
+ int index);
/**
* led_blink_set - set blinking with software fallback
--
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[PATCH v2 3/4] dt-bindings: backlight: Add led-backlight binding
Add DT binding for led-backlight.
Signed-off-by: Jean-Jacques Hiblot
---
.../bindings/leds/backlight/led-backlight.txt | 29 +++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
diff --git a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
new file mode 100644
index ..4f545316b288
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt
@@ -0,0 +1,29 @@
+led-backlight bindings
+
+This binding is used to describe a basic backlight device made of LEDs.
+It can also be used to describe a backlight device controlled by the output of
+a LED driver.
+
+Required properties:
+ - compatible: "led-backlight"
+ - leds: a list of LEDs
+
+Optional properties:
+ - brightness-levels: Array of distinct brightness levels. These
+ are in the range from 0 to 255. The actual brightness
+ level programmed in each LED will be adjusted based on
+ its maximum brightness:
+ led brightness = (level * maximum brightness) / 255
+
+ - default-brightness-level: The default brightness level (index into the
+ array defined by the "brightness-levels"
property).
+
+Example:
+
+ backlight {
+ compatible = "led-backlight";
+
+ leds = <&led1>, <&led2>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
--
2.17.1
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[PATCH v2 4/4] backlight: add led-backlight driver
From: Tomi Valkeinen
This patch adds a led-backlight driver (led_bl), which is similar to
pwm_bl except the driver uses a LED class driver to adjust the
brightness in the HW. Multiple LEDs can be used for a single backlight.
Signed-off-by: Tomi Valkeinen
Signed-off-by: Jean-Jacques Hiblot
---
drivers/video/backlight/Kconfig | 7 +
drivers/video/backlight/Makefile | 1 +
drivers/video/backlight/led_bl.c | 235 +++
3 files changed, 243 insertions(+)
create mode 100644 drivers/video/backlight/led_bl.c
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 8b081d61773e..585a1787618c 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -458,6 +458,13 @@ config BACKLIGHT_RAVE_SP
help
Support for backlight control on RAVE SP device.
+config BACKLIGHT_LED
+ tristate "Generic LED based Backlight Driver"
+ depends on LEDS_CLASS && OF
+ help
+ If you have a LCD backlight adjustable by LED class driver, say Y
+ to enable this driver.
+
endif # BACKLIGHT_CLASS_DEVICE
endmenu
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 63c507c07437..2a67642966a5 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -57,3 +57,4 @@ obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o
obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o
obj-$(CONFIG_BACKLIGHT_ARCXCNN)+= arcxcnn_bl.o
obj-$(CONFIG_BACKLIGHT_RAVE_SP)+= rave-sp-backlight.o
+obj-$(CONFIG_BACKLIGHT_LED)+= led_bl.o
diff --git a/drivers/video/backlight/led_bl.c b/drivers/video/backlight/led_bl.c
new file mode 100644
index ..7644277cfdbb
--- /dev/null
+++ b/drivers/video/backlight/led_bl.c
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015-2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Author: Tomi Valkeinen
+ *
+ * Based on pwm_bl.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define BKL_FULL_BRIGHTNESS 255
+
+struct led_bl_data {
+ struct device *dev;
+ struct backlight_device *bl_dev;
+ struct led_classdev **leds;
+ boolenabled;
+ int nb_leds;
+ unsigned int*levels;
+ unsigned intdefault_brightness;
+ unsigned intmax_brightness;
+};
+
+static int to_led_brightness(struct led_classdev *led, int value)
+{
+ return (value * led->max_brightness) / BKL_FULL_BRIGHTNESS;
+}
+
+static void led_bl_set_brightness(struct led_bl_data *priv, int level)
+{
+ int i;
+ int bkl_brightness;
+
+ if (priv->levels)
+ bkl_brightness = priv->levels[level];
+ else
+ bkl_brightness = level;
+
+ for (i = 0; i < priv->nb_leds; i++) {
+ int led_brightness;
+ struct led_classdev *led = priv->leds[i];
+
+ led_brightness = to_led_brightness(led, bkl_brightness);
+ led_set_brightness(led, led_brightness);
+ }
+
+ priv->enabled = true;
+}
+
+static void led_bl_power_off(struct led_bl_data *priv)
+{
+ int i;
+
+ if (!priv->enabled)
+ return;
+
+ for (i = 0; i < priv->nb_leds; i++)
+ led_set_brightness(priv->leds[i], LED_OFF);
+
+ priv->enabled = false;
+}
+
+static int led_bl_update_status(struct backlight_device *bl)
+{
+ struct led_bl_data *priv = bl_get_data(bl);
+ int brightness = bl->props.brightness;
+
+ if (bl->props.power != FB_BLANK_UNBLANK ||
+ bl->props.fb_blank != FB_BLANK_UNBLANK ||
+ bl->props.state & BL_CORE_FBBLANK)
+ brightness = 0;
+
+ if (brightness > 0)
+ led_bl_set_brightness(priv, brightness);
+ else
+ led_bl_power_off(priv);
+
+ return 0;
+}
+
+static const struct backlight_ops led_bl_ops = {
+ .update_status = led_bl_update_status,
+};
+
+static int led_bl_parse_dt(struct device *dev,
+ struct led_bl_data *priv)
+{
+ struct device_node *node = dev->of_node;
+ int num_levels;
+ u32 *levels = NULL;
+ u32 value;
+ int ret;
+ bool use_default_levels = false;
+
+ if (!node)
+ return -ENODEV;
+
+ num_levels = of_property_count_u32_elems(node, "brightness-levels");
+ if (num_levels < 0) {
+ dev_warn(dev, "can't get brightness-levels. using default
levels\n");
+ use_default_levels = true;
+ num_levels = BKL_FULL_BRIGHTNESS + 1;
+ }
+
+ if (!use_default_levels) {
+ levels = devm_kzalloc(dev, sizeof(u32) * num_levels,
+ GFP_KERNEL);
+ if (!levels)
+ return -ENOMEM;
+
+ re
[PATCH v2 1/8] drm/omap: use refcount API to track the number of users of dma_addr
This would give us a WARN_ON() if the pin/unpin calls are unbalanced.
Proposed-by: Laurent Pinchart
Signed-off-by: Jean-Jacques Hiblot
---
drivers/gpu/drm/omapdrm/omap_gem.c | 45 +++---
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 37378dbc50d0..0b6eef120cc9 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -65,7 +65,7 @@ struct omap_gem_object {
/**
* # of users of dma_addr
*/
- u32 dma_addr_cnt;
+ refcount_t dma_addr_cnt;
/**
* If the buffer has been imported from a dmabuf the OMAP_DB_DMABUF flag
@@ -771,13 +771,15 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t
*dma_addr)
mutex_lock(&omap_obj->lock);
if (!omap_gem_is_contiguous(omap_obj) && priv->has_dmm) {
- if (omap_obj->dma_addr_cnt == 0) {
+ if (refcount_read(&omap_obj->dma_addr_cnt) == 0) {
u32 npages = obj->size >> PAGE_SHIFT;
enum tiler_fmt fmt = gem2fmt(omap_obj->flags);
struct tiler_block *block;
BUG_ON(omap_obj->block);
+ refcount_set(&omap_obj->dma_addr_cnt, 1);
+
ret = omap_gem_attach_pages(obj);
if (ret)
goto fail;
@@ -811,10 +813,10 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t
*dma_addr)
omap_obj->block = block;
DBG("got dma address: %pad", &omap_obj->dma_addr);
+ } else {
+ refcount_inc(&omap_obj->dma_addr_cnt);
}
- omap_obj->dma_addr_cnt++;
-
*dma_addr = omap_obj->dma_addr;
} else if (omap_gem_is_contiguous(omap_obj)) {
*dma_addr = omap_obj->dma_addr;
@@ -844,23 +846,21 @@ void omap_gem_unpin(struct drm_gem_object *obj)
mutex_lock(&omap_obj->lock);
- if (omap_obj->dma_addr_cnt > 0) {
- omap_obj->dma_addr_cnt--;
- if (omap_obj->dma_addr_cnt == 0) {
- ret = tiler_unpin(omap_obj->block);
- if (ret) {
- dev_err(obj->dev->dev,
- "could not unpin pages: %d\n", ret);
- }
- ret = tiler_release(omap_obj->block);
- if (ret) {
- dev_err(obj->dev->dev,
- "could not release unmap: %d\n", ret);
- }
- omap_obj->dma_addr = 0;
- omap_obj->block = NULL;
+ if (refcount_dec_and_test(&omap_obj->dma_addr_cnt)) {
+ ret = tiler_unpin(omap_obj->block);
+ if (ret) {
+ dev_err(obj->dev->dev,
+ "could not unpin pages: %d\n", ret);
}
+ ret = tiler_release(omap_obj->block);
+ if (ret) {
+ dev_err(obj->dev->dev,
+ "could not release unmap: %d\n", ret);
+ }
+ omap_obj->dma_addr = 0;
+ omap_obj->block = NULL;
}
+}
mutex_unlock(&omap_obj->lock);
}
@@ -877,7 +877,7 @@ int omap_gem_rotated_dma_addr(struct drm_gem_object *obj,
u32 orient,
mutex_lock(&omap_obj->lock);
- if ((omap_obj->dma_addr_cnt > 0) && omap_obj->block &&
+ if ((refcount_read(&omap_obj->dma_addr_cnt) > 0) && omap_obj->block &&
(omap_obj->flags & OMAP_BO_TILED)) {
*dma_addr = tiler_tsptr(omap_obj->block, orient, x, y);
ret = 0;
@@ -1028,7 +1028,8 @@ void omap_gem_describe(struct drm_gem_object *obj, struct
seq_file *m)
seq_printf(m, "%08x: %2d (%2d) %08llx %pad (%2d) %p %4d",
omap_obj->flags, obj->name, kref_read(&obj->refcount),
- off, &omap_obj->dma_addr, omap_obj->dma_addr_cnt,
+ off, &omap_obj->dma_addr,
+ refcount_read(&omap_obj->dma_addr_cnt),
omap_obj->vaddr, omap_obj->roll);
if (omap_obj->flags & OMAP_BO_TILED) {
@@ -1091,7 +1092,7 @@ void omap_gem_free_object(struct drm_gem_object *obj)
mutex_lock(&omap_obj->lock);
/* The object should not be pinned. */
- WARN_ON(omap_obj->dma_addr_cnt > 0);
+ WARN_ON(refcount_read(&omap_obj->dma_addr_cnt) > 0);
if (omap_obj->pages) {
if (omap_obj->flags & OMAP_BO_MEM_DMABUF)
--
2.17.1
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[PATCH v2 6/8] drm/omap: cleanup OMAP_BO_SCANOUT use
From: Tomi Valkeinen
omap_gem_new() has a comment about OMAP_BO_SCANOUT which does not make
sense. Also, for the TILER case, we drop OMAP_BO_SCANOUT flag for some
reason.
It's not clear what the original purpose of OMAP_BO_SCANOUT is, but
presuming it means "scanout buffer, something that can be consumed by
DSS", this patch cleans up the above issues.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 07dba300ec07..5c4cdf618347 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -1153,7 +1153,6 @@ struct drm_gem_object *omap_gem_new(struct drm_device
*dev,
* Tiled buffers are always shmem paged backed. When they are
* scanned out, they are remapped into DMM/TILER.
*/
- flags &= ~OMAP_BO_SCANOUT;
flags |= OMAP_BO_MEM_SHMEM;
/*
@@ -1164,9 +1163,8 @@ struct drm_gem_object *omap_gem_new(struct drm_device
*dev,
flags |= tiler_get_cpu_cache_flags();
} else if ((flags & OMAP_BO_SCANOUT) && !priv->has_dmm) {
/*
-* OMAP_BO_SCANOUT hints that the buffer doesn't need to be
-* tiled. However, to lower the pressure on memory allocation,
-* use contiguous memory only if no TILER is available.
+* If we don't have DMM, we must allocate scanout buffers
+* from contiguous DMA memory.
*/
flags |= OMAP_BO_MEM_DMA_API;
} else if (!(flags & OMAP_BO_MEM_DMABUF)) {
--
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[PATCH v2 3/8] drm/omap: accept NULL for dma_addr in omap_gem_pin
From: Tomi Valkeinen
Allow NULL to be passed in 'dma_addr' for omap_gem_pin(), in case the
caller does not need the dma_addr.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 3071e815da73..2ac83cdbb15a 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -817,9 +817,11 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t
*dma_addr)
refcount_inc(&omap_obj->dma_addr_cnt);
}
- *dma_addr = omap_obj->dma_addr;
+ if (dma_addr)
+ *dma_addr = omap_obj->dma_addr;
} else if (omap_gem_is_contiguous(omap_obj)) {
- *dma_addr = omap_obj->dma_addr;
+ if (dma_addr)
+ *dma_addr = omap_obj->dma_addr;
} else {
ret = -EINVAL;
goto fail;
--
2.17.1
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[PATCH v2 0/8] drm/omap: OMAP_BO flags
A first version of this work had been sent by Tomi Valkeinen in may 2017 (https://www.spinics.net/lists/dri-devel/msg140663.html). This series adds a few new OMAP_BO flags to help the userspace manage situations where it needs to use lots of buffers, and would currently run out of TILER space. The TILER space is limited to mapping 128MB at any given time and some applications might need more. This seres is also the opportunity to do some cleanup in the flags and improve the comments describing them. The user-space patches for libdrm, although ready, haven't been posted yet. It will be be done when this series have been discussed and hopefully in the process of getting merged. JJ changes in v2: - fixed build error that crept in during rebase before sending (sorry about that) - rework the refcount part a bit. Jean-Jacques Hiblot (1): drm/omap: use refcount API to track the number of users of dma_addr Tomi Valkeinen (7): drm/omap: add omap_gem_unpin_locked() drm/omap: accept NULL for dma_addr in omap_gem_pin drm/omap: cleanup OMAP_BO flags drm/omap: remove OMAP_BO_TILED define drm/omap: cleanup OMAP_BO_SCANOUT use drm/omap: add omap_gem_validate_flags() drm/omap: add OMAP_BO flags to affect buffer allocation drivers/gpu/drm/omapdrm/omap_dmm_tiler.h | 2 +- drivers/gpu/drm/omapdrm/omap_fb.c | 6 +- drivers/gpu/drm/omapdrm/omap_gem.c| 162 +++--- drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 2 +- include/uapi/drm/omap_drm.h | 27 ++-- 5 files changed, 136 insertions(+), 63 deletions(-) -- 2.17.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 7/8] drm/omap: add omap_gem_validate_flags()
From: Tomi Valkeinen
Add a helper function omap_gem_validate_flags() which validates the
omap_bo flags passed from the userspace.
Also drop the dev_err() message, as the userspace can cause that at
will.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 40 ++
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 5c4cdf618347..cafa9d0bf3c1 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -1131,6 +1131,38 @@ void omap_gem_free_object(struct drm_gem_object *obj)
kfree(omap_obj);
}
+static bool omap_gem_validate_flags(struct drm_device *dev, u32 flags)
+{
+ struct omap_drm_private *priv = dev->dev_private;
+
+ switch (flags & OMAP_BO_CACHE_MASK) {
+ case OMAP_BO_CACHED:
+ case OMAP_BO_WC:
+ case OMAP_BO_CACHE_MASK:
+ break;
+
+ default:
+ return false;
+ }
+
+ if (flags & OMAP_BO_TILED_MASK) {
+ if (!priv->usergart)
+ return false;
+
+ switch (flags & OMAP_BO_TILED_MASK) {
+ case OMAP_BO_TILED_8:
+ case OMAP_BO_TILED_16:
+ case OMAP_BO_TILED_32:
+ break;
+
+ default:
+ return false;
+ }
+ }
+
+ return true;
+}
+
/* GEM buffer object constructor */
struct drm_gem_object *omap_gem_new(struct drm_device *dev,
union omap_gem_size gsize, u32 flags)
@@ -1142,13 +1174,11 @@ struct drm_gem_object *omap_gem_new(struct drm_device
*dev,
size_t size;
int ret;
+ if (!omap_gem_validate_flags(dev, flags))
+ return NULL;
+
/* Validate the flags and compute the memory and cache flags. */
if (flags & OMAP_BO_TILED_MASK) {
- if (!priv->usergart) {
- dev_err(dev->dev, "Tiled buffers require DMM\n");
- return NULL;
- }
-
/*
* Tiled buffers are always shmem paged backed. When they are
* scanned out, they are remapped into DMM/TILER.
--
2.17.1
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[PATCH v2 8/8] drm/omap: add OMAP_BO flags to affect buffer allocation
From: Tomi Valkeinen
On SoCs with DMM/TILER, we have two ways to allocate buffers: normal
dma_alloc or via DMM (which basically functions as an IOMMU). DMM can
map 128MB at a time, and we only map the DMM buffers when they are used
(i.e. not at alloc time). If DMM is present, omapdrm always uses DMM.
There are use cases that require lots of big buffers that are being used
at the same time by different IPs. At the moment the userspace has a
hard maximum of 128MB.
This patch adds three new flags that can be used by the userspace to
solve the situation:
OMAP_BO_MEM_CONTIG: The driver will use dma_alloc to get the memory.
This can be used to avoid DMM if the userspace knows it needs more than
128M of memory at the same time.
OMAP_BO_MEM_DMM: The driver will use DMM to get the memory. There's not
much use for this flag at the moment, as on platforms with DMM it is
used by default, but it's here for completeness.
OMAP_BO_MEM_PIN: The driver will pin the memory at alloc time, and keep
it pinned. This can be used to 1) get an error at alloc time if DMM
space is full, and 2) get rid of the constant pin/unpin operations which
may have some effect on performance.
If none of the flags are given, the behavior is the same as currently.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 25 -
include/uapi/drm/omap_drm.h| 9 +
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index cafa9d0bf3c1..d744d27e200a 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -1095,6 +1095,9 @@ void omap_gem_free_object(struct drm_gem_object *obj)
list_del(&omap_obj->mm_list);
mutex_unlock(&priv->list_lock);
+ if (omap_obj->flags & OMAP_BO_MEM_PIN)
+ omap_gem_unpin_locked(obj);
+
/*
* We own the sole reference to the object at this point, but to keep
* lockdep happy, we must still take the omap_obj_lock to call
@@ -1145,10 +1148,19 @@ static bool omap_gem_validate_flags(struct drm_device
*dev, u32 flags)
return false;
}
+ if ((flags & OMAP_BO_MEM_CONTIG) && (flags & OMAP_BO_MEM_DMM))
+ return false;
+
+ if ((flags & OMAP_BO_MEM_DMM) && !priv->usergart)
+ return false;
+
if (flags & OMAP_BO_TILED_MASK) {
if (!priv->usergart)
return false;
+ if (flags & OMAP_BO_MEM_CONTIG)
+ return false;
+
switch (flags & OMAP_BO_TILED_MASK) {
case OMAP_BO_TILED_8:
case OMAP_BO_TILED_16:
@@ -1191,7 +1203,8 @@ struct drm_gem_object *omap_gem_new(struct drm_device
*dev,
*/
flags &= ~(OMAP_BO_CACHED|OMAP_BO_WC|OMAP_BO_UNCACHED);
flags |= tiler_get_cpu_cache_flags();
- } else if ((flags & OMAP_BO_SCANOUT) && !priv->has_dmm) {
+ } else if ((flags & OMAP_BO_MEM_CONTIG) ||
+ ((flags & OMAP_BO_SCANOUT) && !priv->has_dmm)) {
/*
* If we don't have DMM, we must allocate scanout buffers
* from contiguous DMA memory.
@@ -1251,12 +1264,22 @@ struct drm_gem_object *omap_gem_new(struct drm_device
*dev,
goto err_release;
}
+ if (flags & OMAP_BO_MEM_PIN) {
+ ret = omap_gem_pin(obj, NULL);
+ if (ret)
+ goto err_free_dma;
+ }
+
mutex_lock(&priv->list_lock);
list_add(&omap_obj->mm_list, &priv->obj_list);
mutex_unlock(&priv->list_lock);
return obj;
+err_free_dma:
+ if (flags & OMAP_BO_MEM_DMA_API)
+ dma_free_writecombine(dev->dev, size,
+ omap_obj->vaddr, omap_obj->dma_addr);
err_release:
drm_gem_object_release(obj);
err_free:
diff --git a/include/uapi/drm/omap_drm.h b/include/uapi/drm/omap_drm.h
index 5a142fad473c..842d3180a442 100644
--- a/include/uapi/drm/omap_drm.h
+++ b/include/uapi/drm/omap_drm.h
@@ -47,6 +47,15 @@ struct drm_omap_param {
#define OMAP_BO_UNCACHED 0x0004
#define OMAP_BO_CACHE_MASK 0x0006
+/* Force allocation from contiguous DMA memory */
+#define OMAP_BO_MEM_CONTIG 0x0008
+
+/* Force allocation via DMM */
+#define OMAP_BO_MEM_DMM0x0010
+
+/* Pin the buffer when allocating and keep pinned */
+#define OMAP_BO_MEM_PIN0x0020
+
/* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits.
*/
#define OMAP_BO_TILED_80x0100
#define OMAP_BO_TILED_16 0x0200
--
2.17.1
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[PATCH v2 4/8] drm/omap: cleanup OMAP_BO flags
From: Tomi Valkeinen
Reorder OMAP_BO flags and improve the comments.
Signed-off-by: Tomi Valkeinen
---
include/uapi/drm/omap_drm.h | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/include/uapi/drm/omap_drm.h b/include/uapi/drm/omap_drm.h
index 1fccffef9e27..d8ee2f840697 100644
--- a/include/uapi/drm/omap_drm.h
+++ b/include/uapi/drm/omap_drm.h
@@ -38,19 +38,20 @@ struct drm_omap_param {
__u64 value;/* in (set_param), out (get_param) */
};
-#define OMAP_BO_SCANOUT0x0001 /* scanout capable
(phys contiguous) */
-#define OMAP_BO_CACHE_MASK 0x0006 /* cache type mask, see cache
modes */
-#define OMAP_BO_TILED_MASK 0x0f00 /* tiled mapping mask, see
tiled modes */
+/* Scanout buffer, consumable by DSS */
+#define OMAP_BO_SCANOUT0x0001
-/* cache modes */
-#define OMAP_BO_CACHED 0x /* default */
-#define OMAP_BO_WC 0x0002 /* write-combine */
-#define OMAP_BO_UNCACHED 0x0004 /* strongly-ordered (uncached)
*/
+/* Buffer CPU caching mode: cached, write-combining or uncached. */
+#define OMAP_BO_CACHED 0x
+#define OMAP_BO_WC 0x0002
+#define OMAP_BO_UNCACHED 0x0004
+#define OMAP_BO_CACHE_MASK 0x0006
-/* tiled modes */
+/* Use TILER for the buffer. The TILER container unit can be 8, 16 or 32 bits.
*/
#define OMAP_BO_TILED_80x0100
#define OMAP_BO_TILED_16 0x0200
#define OMAP_BO_TILED_32 0x0300
+#define OMAP_BO_TILED_MASK 0x0f00
#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 |
OMAP_BO_TILED_32)
union omap_gem_size {
--
2.17.1
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[PATCH v2 2/8] drm/omap: add omap_gem_unpin_locked()
From: Tomi Valkeinen
Add omap_gem_unpin_locked() which is a version of omap_gem_unpin() that
expects the caller to hold the omap_obj lock.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_gem.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 0b6eef120cc9..3071e815da73 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -832,20 +832,16 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t
*dma_addr)
}
/**
- * omap_gem_unpin() - Unpin a GEM object from memory
+ * omap_gem_unpin_locked() - Unpin a GEM object from memory
* @obj: the GEM object
*
- * Unpin the given GEM object previously pinned with omap_gem_pin(). Pins are
- * reference-counted, the actualy unpin will only be performed when the number
- * of calls to this function matches the number of calls to omap_gem_pin().
+ * omap_gem_unpin() without locking.
*/
-void omap_gem_unpin(struct drm_gem_object *obj)
+static void omap_gem_unpin_locked(struct drm_gem_object *obj)
{
struct omap_gem_object *omap_obj = to_omap_bo(obj);
int ret;
- mutex_lock(&omap_obj->lock);
-
if (refcount_dec_and_test(&omap_obj->dma_addr_cnt)) {
ret = tiler_unpin(omap_obj->block);
if (ret) {
@@ -862,6 +858,20 @@ void omap_gem_unpin(struct drm_gem_object *obj)
}
}
+/**
+ * omap_gem_unpin() - Unpin a GEM object from memory
+ * @obj: the GEM object
+ *
+ * Unpin the given GEM object previously pinned with omap_gem_pin(). Pins are
+ * reference-counted, the actual unpin will only be performed when the number
+ * of calls to this function matches the number of calls to omap_gem_pin().
+ */
+void omap_gem_unpin(struct drm_gem_object *obj)
+{
+ struct omap_gem_object *omap_obj = to_omap_bo(obj);
+
+ mutex_lock(&omap_obj->lock);
+ omap_gem_unpin_locked(obj);
mutex_unlock(&omap_obj->lock);
}
--
2.17.1
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[PATCH v2 5/8] drm/omap: remove OMAP_BO_TILED define
From: Tomi Valkeinen
OMAP_BO_TILED does not make sense, as OMAP_BO_TILED_* values are not
bitmasks but normal values. As we already have OMAP_BO_TILED_MASK for
the mask, we can remove OMAP_BO_TILED and use OMAP_BO_TILED_MASK
instead.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_dmm_tiler.h | 2 +-
drivers/gpu/drm/omapdrm/omap_fb.c | 6 +++---
drivers/gpu/drm/omapdrm/omap_gem.c| 18 +-
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 2 +-
include/uapi/drm/omap_drm.h | 1 -
5 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
index 835e6654fa82..43c1d096b021 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
@@ -113,7 +113,7 @@ extern struct platform_driver omap_dmm_driver;
/* GEM bo flags -> tiler fmt */
static inline enum tiler_fmt gem2fmt(u32 flags)
{
- switch (flags & OMAP_BO_TILED) {
+ switch (flags & OMAP_BO_TILED_MASK) {
case OMAP_BO_TILED_8:
return TILFMT_8BIT;
case OMAP_BO_TILED_16:
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/omapdrm/omap_fb.c
index 1c9048e35d90..e0e8d1cc3862 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -76,7 +76,7 @@ static u32 get_linear_addr(struct drm_framebuffer *fb,
bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb)
{
- return omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED;
+ return omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED_MASK;
}
/* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */
@@ -135,7 +135,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
x = state->src_x >> 16;
y = state->src_y >> 16;
- if (omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED) {
+ if (omap_gem_flags(fb->obj[0]) & OMAP_BO_TILED_MASK) {
u32 w = state->src_w >> 16;
u32 h = state->src_h >> 16;
@@ -193,7 +193,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
plane = &omap_fb->planes[1];
if (info->rotation_type == OMAP_DSS_ROT_TILER) {
- WARN_ON(!(omap_gem_flags(fb->obj[1]) & OMAP_BO_TILED));
+ WARN_ON(!(omap_gem_flags(fb->obj[1]) &
OMAP_BO_TILED_MASK));
omap_gem_rotated_dma_addr(fb->obj[1], orient, x/2, y/2,
&info->p_uv_addr);
} else {
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c
b/drivers/gpu/drm/omapdrm/omap_gem.c
index 2ac83cdbb15a..07dba300ec07 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -194,7 +194,7 @@ static void omap_gem_evict(struct drm_gem_object *obj)
struct omap_gem_object *omap_obj = to_omap_bo(obj);
struct omap_drm_private *priv = obj->dev->dev_private;
- if (omap_obj->flags & OMAP_BO_TILED) {
+ if (omap_obj->flags & OMAP_BO_TILED_MASK) {
enum tiler_fmt fmt = gem2fmt(omap_obj->flags);
int i;
@@ -322,7 +322,7 @@ size_t omap_gem_mmap_size(struct drm_gem_object *obj)
struct omap_gem_object *omap_obj = to_omap_bo(obj);
size_t size = obj->size;
- if (omap_obj->flags & OMAP_BO_TILED) {
+ if (omap_obj->flags & OMAP_BO_TILED_MASK) {
/* for tiled buffers, the virtual size has stride rounded up
* to 4kb.. (to hide the fact that row n+1 might start 16kb or
* 32kb later!). But we don't back the entire buffer with
@@ -511,7 +511,7 @@ vm_fault_t omap_gem_fault(struct vm_fault *vmf)
* probably trigger put_pages()?
*/
- if (omap_obj->flags & OMAP_BO_TILED)
+ if (omap_obj->flags & OMAP_BO_TILED_MASK)
ret = omap_gem_fault_2d(obj, vma, vmf);
else
ret = omap_gem_fault_1d(obj, vma, vmf);
@@ -784,7 +784,7 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t
*dma_addr)
if (ret)
goto fail;
- if (omap_obj->flags & OMAP_BO_TILED) {
+ if (omap_obj->flags & OMAP_BO_TILED_MASK) {
block = tiler_reserve_2d(fmt,
omap_obj->width,
omap_obj->height, 0);
@@ -890,7 +890,7 @@ int omap_gem_rotated_dma_addr(struct drm_gem_object *obj,
u32 orient,
mutex_lock(&omap_obj->lock);
if ((refcount_read(&omap_obj->dma_addr_cnt) > 0) && omap_obj->block &&
- (omap_obj->flags & OMAP_BO_TILED)) {
+ (omap_obj->flags & OMAP_BO_TILED_MASK)) {
*dma_addr = tiler_tsptr(omap_obj->block, orient, x, y);
ret = 0;
}
@@ -
Re: [PATCH v2 3/4] dt-bindings: backlight: Add led-backlight binding
On Mon, Jul 08, 2019 at 12:26:59PM +0200, Jean-Jacques Hiblot wrote: > Add DT binding for led-backlight. > > Signed-off-by: Jean-Jacques Hiblot > --- > .../bindings/leds/backlight/led-backlight.txt | 29 +++ > 1 file changed, 29 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/leds/backlight/led-backlight.txt > > diff --git > a/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt > b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt > new file mode 100644 > index ..4f545316b288 > --- /dev/null > +++ b/Documentation/devicetree/bindings/leds/backlight/led-backlight.txt > @@ -0,0 +1,29 @@ > +led-backlight bindings > + > +This binding is used to describe a basic backlight device made of LEDs. > +It can also be used to describe a backlight device controlled by the output > of > +a LED driver. > + > +Required properties: > + - compatible: "led-backlight" > + - leds: a list of LEDs > + > +Optional properties: > + - brightness-levels: Array of distinct brightness levels. These > + are in the range from 0 to 255. The actual brightness > + level programmed in each LED will be adjusted based on > + its maximum brightness: > + led brightness = (level * maximum brightness) / 255 8-bits is a narrow range and likely to make animated backlight effects impossible because the stepping artefacts would be too obvious. I'd rather see the brightness-levels table expressed in the native steps of the LEDs in the leds list. I know this means that the LEDs must have identical ranges but I think it is OK. A backlight design whose LEDs are connected to non-identical drivers is either badly broken or sufficiently exotic to need to special purpose driver. The driver can therefore fail to probe if the LEDs are mismatched. > + > + - default-brightness-level: The default brightness level (index into the > + array defined by the "brightness-levels" > property). The brightness-levels property is optional... this text needs to be updated. Daniel.
[PATCH] drm/bridge/megachips: Drop GPIO header
This file isn't using any interfaces from so just drop the include. Signed-off-by: Linus Walleij --- drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c index 823db80cbd19..b40ce484244a 100644 --- a/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c +++ b/drivers/gpu/drm/bridge/megachips-stdp-ge-b850v3-fw.c @@ -19,7 +19,6 @@ * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output */ -#include #include #include #include -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/bridge/nxp-ptn3460: Drop legacy GPIO headers
This driver uses exclusively the new GPIO API from so just drop the old API headers. Signed-off-by: Linus Walleij --- drivers/gpu/drm/bridge/nxp-ptn3460.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/nxp-ptn3460.c b/drivers/gpu/drm/bridge/nxp-ptn3460.c index 9fd231c5887f..19f847aa5497 100644 --- a/drivers/gpu/drm/bridge/nxp-ptn3460.c +++ b/drivers/gpu/drm/bridge/nxp-ptn3460.c @@ -6,12 +6,10 @@ */ #include -#include #include #include #include #include -#include #include #include #include -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/bridge/parade: Drop legacy GPIO header
This driver uses the new GPIO API from so drop the inclusion of the legacy header. Signed-off-by: Linus Walleij --- drivers/gpu/drm/bridge/parade-ps8622.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c index 699c8dfb0fcb..e26f475eb517 100644 --- a/drivers/gpu/drm/bridge/parade-ps8622.c +++ b/drivers/gpu/drm/bridge/parade-ps8622.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Bug ID: 111087 Summary: SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter" Product: DRI Version: XOrg git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: ludovico.denit...@collabora.com Created attachment 144719 --> https://bugs.freedesktop.org/attachment.cgi?id=144719&action=edit basic configuration details When I try to boot SteamOS I end up with just a black screen. Xorg.0.log contains this error but I'm not completely sure if it is the cause: (EE) AMDGPU(0): drmmode_do_crtc_dpms cannot get last vblank counter I also tried installing debian kernel 5.0.2-1~exp1, mesa 19.1.1 and all the relevant xserver-xorg-video-* 19.0.1 but the problem persisted. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #1 from Ludovico de Nittis --- Created attachment 144720 --> https://bugs.freedesktop.org/attachment.cgi?id=144720&action=edit Xorg.0.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #2 from Ludovico de Nittis --- Created attachment 144721 --> https://bugs.freedesktop.org/attachment.cgi?id=144721&action=edit modinfo.amdgpu.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #3 from Ludovico de Nittis --- Created attachment 144722 --> https://bugs.freedesktop.org/attachment.cgi?id=144722&action=edit lspci.vnn.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #4 from Ludovico de Nittis --- Created attachment 144723 --> https://bugs.freedesktop.org/attachment.cgi?id=144723&action=edit dmesg.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #5 from Ludovico de Nittis --- Created attachment 144724 --> https://bugs.freedesktop.org/attachment.cgi?id=144724&action=edit dkms.status.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #6 from Ludovico de Nittis --- Created attachment 144725 --> https://bugs.freedesktop.org/attachment.cgi?id=144725&action=edit lsmod.amdgpu.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #7 from Ludovico de Nittis --- Created attachment 144726 --> https://bugs.freedesktop.org/attachment.cgi?id=144726&action=edit package.log -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 110674] Crashes / Resets From AMDGPU / Radeon VII
https://bugs.freedesktop.org/show_bug.cgi?id=110674 --- Comment #46 from Tom B --- Has anyone tested 5.3 yet? I noticed there are a lot of powerplay changes. Since this bug messes up the card's power profile, how safe is testing new kernels? Is there any danger of my card being damaged due to wrong voltages if the powerplay code is as buggy or worse than it has been since 5.1? -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2] backlight: rave-sp: don't touch initial state and register with correct device
This way the backlight can be referenced through its device node and enabling/disabling can be managed through the panel driver. Signed-off-by: Lucas Stach --- drivers/video/backlight/rave-sp-backlight.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/video/backlight/rave-sp-backlight.c b/drivers/video/backlight/rave-sp-backlight.c index 462f14a1b19d..05b5f003a3d1 100644 --- a/drivers/video/backlight/rave-sp-backlight.c +++ b/drivers/video/backlight/rave-sp-backlight.c @@ -48,14 +48,20 @@ static int rave_sp_backlight_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct backlight_device *bd; - bd = devm_backlight_device_register(dev, pdev->name, dev->parent, + bd = devm_backlight_device_register(dev, pdev->name, dev, dev_get_drvdata(dev->parent), &rave_sp_backlight_ops, &rave_sp_backlight_props); if (IS_ERR(bd)) return PTR_ERR(bd); - backlight_update_status(bd); + /* +* If there is a phandle pointing to the device node we can +* assume that another device will manage the status changes. +* If not we make sure the backlight is in a consistent state. +*/ + if (!dev->of_node->phandle) + backlight_update_status(bd); return 0; } -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 00/19] drm/i915: Plane cdclk requirements and fp16 for gen4+
From: Ville Syrjälä The end of the series is just a reposting of the fp16 stuff for gen4+. The start of the series is new stuff to allow planes to dictate the minimum cdclk, which is sometimes needed for downscaling or fp16 (and sometimes even for other pixel formats). Thanks to that new code the fp16 tests should now pass on bxt/glk. Ville Syrjälä (19): drm: Add drm_modeset_lock_assert_held() drm/atomic-helper: Make crtc helper funcs optional drm/i915: Remove pointless planes_changed=true assignment drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar() drm/i915: Allow downscale factor of <3.0 on glk+ for all formats drm/i915: Extract intel_modeset_calc_cdclk() drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check() drm/i915: Stop using drm_atomic_helper_check_planes() drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update drm/i915: Make .modeset_calc_cdclk() mandatory drm/i915: Rework global state locking drm/i915: Move check_digital_port_conflicts() earier drm/i915: Allow planes to declare their minimum acceptable cdclk drm/i915: Eliminate skl_check_pipe_max_pixel_rate() drm/i915: Simplify skl_max_scale() drm/i915: Add support for half float framebuffers for skl+ drm/i915: Add support for half float framebuffers for gen4+ primary planes drm/i915: Add support for half float framebuffers for ivb+ sprites drm/i915: Add support for half float framebuffers on snb sprites drivers/gpu/drm/drm_atomic_helper.c | 2 +- drivers/gpu/drm/i915/display/intel_atomic.c | 34 +- drivers/gpu/drm/i915/display/intel_atomic.h | 3 + .../gpu/drm/i915/display/intel_atomic_plane.c | 45 +- .../gpu/drm/i915/display/intel_atomic_plane.h | 4 + drivers/gpu/drm/i915/display/intel_audio.c| 10 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 221 +++- drivers/gpu/drm/i915/display/intel_cdclk.h| 6 +- drivers/gpu/drm/i915/display/intel_display.c | 534 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 441 ++- drivers/gpu/drm/i915/display/intel_sprite.h | 8 +- drivers/gpu/drm/i915/i915_drv.h | 11 +- drivers/gpu/drm/i915/intel_drv.h | 14 +- drivers/gpu/drm/i915/intel_pm.c | 116 +--- drivers/gpu/drm/i915/intel_pm.h | 2 - include/drm/drm_modeset_lock.h| 9 + 16 files changed, 1054 insertions(+), 406 deletions(-) -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 01/19] drm: Add drm_modeset_lock_assert_held()
From: Ville Syrjälä
Add a small wrapper around lockdep_assert_held() to make
it a bit more conventinet to use with modeset locks.
Signed-off-by: Ville Syrjälä
---
include/drm/drm_modeset_lock.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/drm/drm_modeset_lock.h b/include/drm/drm_modeset_lock.h
index 7b8841065b11..4fc9a43ac45a 100644
--- a/include/drm/drm_modeset_lock.h
+++ b/include/drm/drm_modeset_lock.h
@@ -114,6 +114,15 @@ static inline bool drm_modeset_is_locked(struct
drm_modeset_lock *lock)
return ww_mutex_is_locked(&lock->mutex);
}
+/**
+ * drm_modeset_lock_assert_held - equivalent to lockdep_assert_held()
+ * @lock: lock to check
+ */
+static inline void drm_modeset_lock_assert_held(struct drm_modeset_lock *lock)
+{
+ lockdep_assert_held(&lock->mutex.base);
+}
+
int drm_modeset_lock(struct drm_modeset_lock *lock,
struct drm_modeset_acquire_ctx *ctx);
int __must_check drm_modeset_lock_single_interruptible(struct drm_modeset_lock
*lock);
--
2.21.0
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[PATCH 02/19] drm/atomic-helper: Make crtc helper funcs optional
From: Ville Syrjälä Allow drivers to call drm_atomic_helper_check_modeset() without having the crtc helper funcs specified. i915 doesn't need those anymore. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/drm_atomic_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index aa16ea17ff9b..fb2ce692ae5b 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -481,7 +481,7 @@ mode_fixup(struct drm_atomic_state *state) continue; funcs = crtc->helper_private; - if (!funcs->mode_fixup) + if (!funcs || !funcs->mode_fixup) continue; ret = funcs->mode_fixup(crtc, &new_crtc_state->mode, -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 03/19] drm/i915: Remove pointless planes_changed=true assignment
From: Ville Syrjälä i915 doesn't use the crtc_state->plane_changed flag for anything, so setting it is pointless. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 90ca11a4ae88..954d4a930864 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -378,13 +378,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, plane->base.id); return PTR_ERR(state); } - - /* -* the plane is added after plane checks are run, -* but since this plane is unchanged just do the -* minimum required validation. -*/ - crtc_state->base.planes_changed = true; } intel_plane = to_intel_plane(plane); -- 2.21.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 04/19] drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar()
From: Ville Syrjälä
There's a helper in drm_fourcc.h these days to check of we're dealing
with a two plane YUV format. Make use if it.
Also s/plane/color_plane/ in skl_plane_relative_data_rate() to reduce
the confusion.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 5 ++--
drivers/gpu/drm/i915/display/intel_display.c | 10 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 20 +++---
drivers/gpu/drm/i915/display/intel_sprite.h | 1 -
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 27 +--
6 files changed, 26 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index ab411d5e093c..7ff19b524f9d 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -143,6 +143,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_plane_state
*new_plane_state)
{
struct intel_plane *plane = to_intel_plane(new_plane_state->base.plane);
+ const struct drm_framebuffer *fb = new_plane_state->base.fb;
int ret;
new_crtc_state->active_planes &= ~BIT(plane->id);
@@ -163,11 +164,11 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->active_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
- is_planar_yuv_format(new_plane_state->base.fb->format->format))
+ drm_format_info_is_yuv_semiplanar(fb->format))
new_crtc_state->nv12_planes |= BIT(plane->id);
if (new_plane_state->base.visible &&
- new_plane_state->base.fb->format->format == DRM_FORMAT_C8)
+ fb->format->format == DRM_FORMAT_C8)
new_crtc_state->c8_planes |= BIT(plane->id);
if (new_plane_state->base.visible || old_plane_state->base.visible)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f09eda75711a..ee93577bdf95 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3540,7 +3540,7 @@ int skl_check_plane_surface(struct intel_plane_state
*plane_state)
* Handle the AUX surface first since
* the main surface setup depends on it.
*/
- if (is_planar_yuv_format(fb->format->format)) {
+ if (drm_format_info_is_yuv_semiplanar(fb->format)) {
ret = skl_check_nv12_aux_surface(plane_state);
if (ret)
return ret;
@@ -5457,7 +5457,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
bool force_detach,
return 0;
}
- if (format && is_planar_yuv_format(format->format) &&
+ if (format && drm_format_info_is_yuv_semiplanar(format) &&
(src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) {
DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n");
return -EINVAL;
@@ -5534,7 +5534,7 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
/* Pre-gen11 and SDR planes always need a scaler for planar formats. */
if (!icl_is_hdr_plane(dev_priv, intel_plane->id) &&
- fb && is_planar_yuv_format(fb->format->format))
+ fb && drm_format_info_is_yuv_semiplanar(fb->format))
need_scaler = true;
ret = skl_update_scaler(crtc_state, force_detach,
@@ -14468,7 +14468,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
int
skl_max_scale(const struct intel_crtc_state *crtc_state,
- u32 pixel_format)
+ const struct drm_format_info *format)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -14493,7 +14493,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
*or
*cdclk/crtc_clock
*/
- mult = is_planar_yuv_format(pixel_format) ? 2 : 3;
+ mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3;
tmpclk1 = (1 << 16) * mult - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 34586f29be60..e89f3f7fae05 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -47,19 +47,6 @@
#include "intel_psr.h"
#include "intel_sprite.h"
-bool is_planar_yuv_format(u32 pixelformat)
-{
- switch (pixelformat) {
- case DRM_FORMAT_NV12:
- case DRM_FORMAT_P010:
- case DRM_FORMAT_P012:
- case DRM_FORMAT_P016:
- return true;
[PATCH 05/19] drm/i915: Allow downscale factor of <3.0 on glk+ for all formats
From: Ville Syrjälä
Bspec says that glk+ max downscale factor is <3.0 for all pixel formats.
Older platforms had a max of <2.0 for NV12. Update the code to deal with
this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index ee93577bdf95..2b8a6a84605c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14472,7 +14472,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int max_scale, mult;
+ int max_scale;
int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
if (!crtc_state->base.enable)
@@ -14493,8 +14493,11 @@ skl_max_scale(const struct intel_crtc_state
*crtc_state,
*or
*cdclk/crtc_clock
*/
- mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3;
- tmpclk1 = (1 << 16) * mult - 1;
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ !drm_format_info_is_yuv_semiplanar(format))
+ tmpclk1 = 0x3 - 1;
+ else
+ tmpclk1 = 0x2 - 1;
tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
max_scale = min(tmpclk1, tmpclk2);
--
2.21.0
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[PATCH 07/19] drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check()
From: Ville Syrjälä
Clean up the mess with the drm vs. intel types in
intel_crtc_atomic_check() and rename varibles accordingly.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 54 ++--
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3efe76c2ec33..5635f2079e4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11733,25 +11733,24 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
-static int intel_crtc_atomic_check(struct drm_crtc *crtc,
- struct drm_crtc_state *crtc_state)
+static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
+ struct drm_crtc_state *_crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *pipe_config =
- to_intel_crtc_state(crtc_state);
+ struct intel_crtc *crtc = to_intel_crtc(_crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(_crtc_state);
int ret;
- bool mode_changed = needs_modeset(pipe_config);
+ bool mode_changed = needs_modeset(crtc_state);
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
- mode_changed && !crtc_state->active)
- pipe_config->update_wm_post = true;
+ mode_changed && !crtc_state->base.active)
+ crtc_state->update_wm_post = true;
- if (mode_changed && crtc_state->enable &&
+ if (mode_changed && crtc_state->base.enable &&
dev_priv->display.crtc_compute_clock &&
- !WARN_ON(pipe_config->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(intel_crtc,
- pipe_config);
+ !WARN_ON(crtc_state->shared_dpll)) {
+ ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state);
if (ret)
return ret;
}
@@ -11760,19 +11759,19 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
* May need to update pipe gamma enable bits
* when C8 planes are getting enabled/disabled.
*/
- if (c8_planes_changed(pipe_config))
- crtc_state->color_mgmt_changed = true;
+ if (c8_planes_changed(crtc_state))
+ crtc_state->base.color_mgmt_changed = true;
- if (mode_changed || pipe_config->update_pipe ||
- crtc_state->color_mgmt_changed) {
- ret = intel_color_check(pipe_config);
+ if (mode_changed || crtc_state->update_pipe ||
+ crtc_state->base.color_mgmt_changed) {
+ ret = intel_color_check(crtc_state);
if (ret)
return ret;
}
ret = 0;
if (dev_priv->display.compute_pipe_wm) {
- ret = dev_priv->display.compute_pipe_wm(pipe_config);
+ ret = dev_priv->display.compute_pipe_wm(crtc_state);
if (ret) {
DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
return ret;
@@ -11788,7 +11787,7 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
* old state and the new state. We can program these
* immediately.
*/
- ret = dev_priv->display.compute_intermediate_wm(pipe_config);
+ ret = dev_priv->display.compute_intermediate_wm(crtc_state);
if (ret) {
DRM_DEBUG_KMS("No valid intermediate pipe watermarks
are possible\n");
return ret;
@@ -11796,21 +11795,20 @@ static int intel_crtc_atomic_check(struct drm_crtc
*crtc,
}
if (INTEL_GEN(dev_priv) >= 9) {
- if (mode_changed || pipe_config->update_pipe)
- ret = skl_update_scaler_crtc(pipe_config);
+ if (mode_changed || crtc_state->update_pipe)
+ ret = skl_update_scaler_crtc(crtc_state);
if (!ret)
- ret = icl_check_nv12_planes(pipe_config);
+ ret = icl_check_nv12_planes(crtc_state);
if (!ret)
- ret = skl_check_pipe_max_pixel_rate(intel_crtc,
- pipe_config);
+ ret = skl_check_pipe_max_pixel_rate(crtc, crtc_state);
if (!ret)
- ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
-
[PATCH 06/19] drm/i915: Extract intel_modeset_calc_cdclk()
From: Ville Syrjälä
Exfiltrate the cdclk code from intel_modeset_checks() into
intel_modeset_calc_cdclk().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 135 ++-
drivers/gpu/drm/i915/display/intel_cdclk.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 119 +---
3 files changed, 135 insertions(+), 125 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0b8b8ae3b7fc..c7c46b382738 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_drv.h"
#include "intel_sideband.h"
@@ -2081,9 +2082,9 @@ bool intel_cdclk_needs_modeset(const struct
intel_cdclk_state *a,
* Returns:
* True if the CDCLK states require just a cd2x divider update, false if not.
*/
-bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_state *a,
- const struct intel_cdclk_state *b)
+static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
{
/* Older hw doesn't have the capability */
if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))
@@ -2102,8 +2103,8 @@ bool intel_cdclk_needs_cd2x_update(struct
drm_i915_private *dev_priv,
* Returns:
* True if the CDCLK states don't match, false if they do.
*/
-bool intel_cdclk_changed(const struct intel_cdclk_state *a,
-const struct intel_cdclk_state *b)
+static bool intel_cdclk_changed(const struct intel_cdclk_state *a,
+ const struct intel_cdclk_state *b)
{
return intel_cdclk_needs_modeset(a, b) ||
a->voltage_level != b->voltage_level;
@@ -2556,6 +2557,62 @@ static int cnl_modeset_calc_cdclk(struct
intel_atomic_state *state)
return 0;
}
+static int intel_lock_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /* Add all pipes to the state */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+ }
+
+ return 0;
+}
+
+static int intel_modeset_all_pipes(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ /*
+* Add all pipes to the state, and force
+* a modeset on all the active ones.
+*/
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state;
+ int ret;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (!crtc_state->base.active ||
+ drm_atomic_crtc_needs_modeset(&crtc_state->base))
+ continue;
+
+ crtc_state->base.mode_changed = true;
+
+ ret = drm_atomic_add_affected_connectors(&state->base,
+&crtc->base);
+ if (ret)
+ return ret;
+
+ ret = drm_atomic_add_affected_planes(&state->base,
+&crtc->base);
+ if (ret)
+ return ret;
+
+ crtc_state->update_planes |= crtc_state->active_planes;
+ }
+
+ return 0;
+}
+
static int icl_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -2590,6 +2647,74 @@ static int icl_modeset_calc_cdclk(struct
intel_atomic_state *state)
return 0;
}
+int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ enum pipe pipe;
+ int ret;
+
+ if (!dev_priv->display.modeset_calc_cdclk)
+ return 0;
+
+ ret = dev_priv->display.modeset_calc_cdclk(state);
+ if (ret)
+ return ret;
+
+ /*
+* Writes to dev_priv->cdclk.logical must protected by
+* holding all the crtc locks, even if we don't end up
+* touching the hardware
+*/
+ if (intel_cdclk_changed(&dev_priv->cdclk.logical,
+ &state->cdclk.logical)) {
+ ret = intel_lock_all_pipes
[PATCH 11/19] drm/i915: Rework global state locking
From: Ville Syrjälä
So far we've sort of protected the global state under dev_priv with
the connection_mutex. I wan to change that so that we can change the
cdclk even for pure plane updates. To that end let's formalize the
protection of the global state to follow what I started with the cdclk
code already (though not entirely properly) such that any crtc mutex
will suffice as a read lock, and all crtcs mutexes act as the write
lock.
We'll also pimp intel_atomic_state_clear() to clear the entire global
state, so that we don't accidentally leak stale information between
the locking retries.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_atomic.c | 27 +
drivers/gpu/drm/i915/display/intel_atomic.h | 3 +
drivers/gpu/drm/i915/display/intel_audio.c | 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 116 ++-
drivers/gpu/drm/i915/display/intel_display.c | 29 -
drivers/gpu/drm/i915/i915_drv.h | 11 +-
drivers/gpu/drm/i915/intel_drv.h | 8 ++
7 files changed, 139 insertions(+), 65 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
b/drivers/gpu/drm/i915/display/intel_atomic.c
index 954d4a930864..de4cd482dbe5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -418,6 +418,13 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
struct intel_atomic_state *state = to_intel_atomic_state(s);
drm_atomic_state_default_clear(&state->base);
state->dpll_set = state->modeset = false;
+ state->global_state_changed = false;
+ state->active_crtcs = 0;
+ memset(&state->min_cdclk, 0, sizeof(state->min_cdclk));
+ memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level));
+ memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical));
+ memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual));
+ state->cdclk.pipe = INVALID_PIPE;
}
struct intel_crtc_state *
@@ -431,3 +438,23 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
+
+int intel_atomic_lock_global_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+
+ state->global_state_changed = true;
+
+ /* Lock all crtc mutexes */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ int ret;
+
+ ret = drm_modeset_lock(&crtc->base.mutex,
+ state->base.acquire_ctx);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
b/drivers/gpu/drm/i915/display/intel_atomic.h
index 58065d3161a3..0d6cd22b7e5f 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -16,6 +16,7 @@ struct drm_crtc_state;
struct drm_device;
struct drm_i915_private;
struct drm_property;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
@@ -46,4 +47,6 @@ int intel_atomic_setup_scalers(struct drm_i915_private
*dev_priv,
struct intel_crtc *intel_crtc,
struct intel_crtc_state *crtc_state);
+int intel_atomic_lock_global_state(struct intel_atomic_state *state);
+
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index c8fd35a7ca42..22ccb824c716 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -28,6 +28,7 @@
#include
#include "i915_drv.h"
+#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_drv.h"
#include "intel_lpe_audio.h"
@@ -816,13 +817,8 @@ static void glk_force_audio_cdclk(struct drm_i915_private
*dev_priv,
to_intel_atomic_state(state)->cdclk.force_min_cdclk =
enable ? 2 * 96000 : 0;
- /*
-* Protects dev_priv->cdclk.force_min_cdclk
-* Need to lock this here in case we have no active pipes
-* and thus wouldn't lock it during the commit otherwise.
-*/
- ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
- &ctx);
+ /* Protects dev_priv->cdclk.force_min_cdclk */
+ ret = intel_atomic_lock_global_state(to_intel_atomic_state(state));
if (!ret)
ret = drm_atomic_commit(state);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4649485fee33..40583d8d259b 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -442,7 +442,7 @@ static int vlv_calc_cdclk(struct drm_i915_private
*dev_priv, int min_cdclk)
return 20;
}
-static u8 vlv_calc_voltage_level(s
[PATCH 10/19] drm/i915: Make .modeset_calc_cdclk() mandatory
From: Ville Syrjälä
While not all platforms allow us to change the cdclk frequency
we should still verify that the fixed cdclk frequency isn't
too low. To that end let's cook up a .modeset_calc_cdclk()
implementation that only does the min_cdclk vs. actual cdclk
frequency check for such platforms.
Also we mustn't forget about double wide pipe on gen2/3 when
doing this.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 31
drivers/gpu/drm/i915/display/intel_display.c | 8 ++---
2 files changed, 28 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f2910c0c3e3e..4649485fee33 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2209,9 +2209,11 @@ intel_set_cdclk_post_plane_update(struct
drm_i915_private *dev_priv,
intel_set_cdclk(dev_priv, new_state, pipe);
}
-static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv,
-int pixel_rate)
+static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ int pixel_rate = crtc_state->pixel_rate;
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
return DIV_ROUND_UP(pixel_rate, 2);
else if (IS_GEN(dev_priv, 9) ||
@@ -2219,6 +2221,8 @@ static int intel_pixel_rate_to_cdclk(struct
drm_i915_private *dev_priv,
return pixel_rate;
else if (IS_CHERRYVIEW(dev_priv))
return DIV_ROUND_UP(pixel_rate * 100, 95);
+ else if (crtc_state->double_wide)
+ return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
else
return DIV_ROUND_UP(pixel_rate * 100, 90);
}
@@ -2232,7 +2236,7 @@ int intel_crtc_compute_min_cdclk(const struct
intel_crtc_state *crtc_state)
if (!crtc_state->base.enable)
return 0;
- min_cdclk = intel_pixel_rate_to_cdclk(dev_priv, crtc_state->pixel_rate);
+ min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
@@ -2647,15 +2651,28 @@ static int icl_modeset_calc_cdclk(struct
intel_atomic_state *state)
return 0;
}
+static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
+{
+ int min_cdclk;
+
+ /*
+* We can't change the cdclk frequency, but we still want to
+* check that the required minimum frequency doesn't exceed
+* the actual cdclk frequency.
+*/
+ min_cdclk = intel_compute_min_cdclk(state);
+ if (min_cdclk < 0)
+ return min_cdclk;
+
+ return 0;
+}
+
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
enum pipe pipe;
int ret;
- if (!dev_priv->display.modeset_calc_cdclk)
- return 0;
-
ret = dev_priv->display.modeset_calc_cdclk(state);
if (ret)
return ret;
@@ -2957,6 +2974,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private
*dev_priv)
} else if (IS_VALLEYVIEW(dev_priv)) {
dev_priv->display.set_cdclk = vlv_set_cdclk;
dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+ } else {
+ dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
}
if (INTEL_GEN(dev_priv) >= 11)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5a42cbfa72c3..2d3cfdc80fd3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -16701,11 +16701,9 @@ static void intel_modeset_readout_hw_state(struct
drm_device *dev)
intel_crtc_compute_pixel_rate(crtc_state);
- if (dev_priv->display.modeset_calc_cdclk) {
- min_cdclk =
intel_crtc_compute_min_cdclk(crtc_state);
- if (WARN_ON(min_cdclk < 0))
- min_cdclk = 0;
- }
+ min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
+ if (WARN_ON(min_cdclk < 0))
+ min_cdclk = 0;
drm_calc_timestamping_constants(&crtc->base,
&crtc_state->base.adjusted_mode);
--
2.21.0
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 08/19] drm/i915: Stop using drm_atomic_helper_check_planes()
From: Ville Syrjälä
We need to insert stuff between the plane and crtc .atomic_check()
drm_atomic_helper_check_planes() doesn't allow us to do that so
stop using it and hand roll the loops instead.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 10 +---
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 57 +++
3 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 7ff19b524f9d..d7493551b28c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -194,14 +194,11 @@ get_crtc_from_states(const struct intel_plane_state
*old_plane_state,
return NULL;
}
-static int intel_plane_atomic_check(struct drm_plane *_plane,
- struct drm_plane_state *_new_plane_state)
+int intel_plane_atomic_check(struct intel_atomic_state *state,
+struct intel_plane *plane)
{
- struct intel_plane *plane = to_intel_plane(_plane);
- struct intel_atomic_state *state =
- to_intel_atomic_state(_new_plane_state->state);
struct intel_plane_state *new_plane_state =
- to_intel_plane_state(_new_plane_state);
+ intel_atomic_get_new_plane_state(state, plane);
const struct intel_plane_state *old_plane_state =
intel_atomic_get_old_plane_state(state, plane);
struct intel_crtc *crtc =
@@ -368,5 +365,4 @@ void i9xx_update_planes_on_crtc(struct intel_atomic_state
*state,
const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
.prepare_fb = intel_prepare_plane_fb,
.cleanup_fb = intel_cleanup_plane_fb,
- .atomic_check = intel_plane_atomic_check,
};
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index cb7ef4f9eafd..dc85af02e9b7 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -41,6 +41,8 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state *intel_state);
+int intel_plane_atomic_check(struct intel_atomic_state *state,
+struct intel_plane *plane);
int intel_plane_atomic_calc_changes(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*old_plane_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5635f2079e4c..5a42cbfa72c3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11733,15 +11733,14 @@ static bool c8_planes_changed(const struct
intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
-static int intel_crtc_atomic_check(struct drm_crtc *_crtc,
- struct drm_crtc_state *_crtc_state)
+static int intel_crtc_atomic_check(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(_crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(_crtc_state);
- int ret;
+ intel_atomic_get_new_crtc_state(state, crtc);
bool mode_changed = needs_modeset(crtc_state);
+ int ret;
if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv) &&
mode_changed && !crtc_state->base.active)
@@ -11813,10 +11812,6 @@ static int intel_crtc_atomic_check(struct drm_crtc
*_crtc,
return ret;
}
-static const struct drm_crtc_helper_funcs intel_helper_funcs = {
- .atomic_check = intel_crtc_atomic_check,
-};
-
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
{
struct intel_connector *connector;
@@ -13457,6 +13452,42 @@ static void intel_crtc_check_fastset(const struct
intel_crtc_state *old_crtc_sta
new_crtc_state->has_drrs = old_crtc_state->has_drrs;
}
+static int intel_atomic_check_planes(struct intel_atomic_state *state)
+{
+ struct intel_plane_state *plane_state;
+ struct intel_plane *plane;
+ int i, ret;
+
+ for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+ ret = intel_plane_atomic_check(state, plane);
+ if (ret) {
+ DRM_DEBUG_ATOMIC("[PLANE
[PATCH 13/19] drm/i915: Allow planes to declare their minimum acceptable cdclk
From: Ville Syrjälä
Various pixel formats and plane scaling impose additional constraints
on the cdclk frequency. Provide a new plane->min_cdclk() hook that
will be used to compute the minimum acceptable cdclk frequency for
each plane.
Annoyingly on some platforms the numer of active planes affects
this calculation so we must also toss in more planes into the
state when the number of active planes changes.
The sequence of state computation must also be changed:
1. check_plane() (updates plane's visibility etc.)
2. figure out if more planes now require update min_cdclk
computaion
3. calculate the new min cdclk for each plane in the state
4. if the minimum of any plane now exceeds the current
logical cdclk we recompute the cdclk
4. during cdclk computation take the planes' min_cdclk into
accoutn
5. follow the normal cdclk programming to change the
cdclk frequency. This may now require a modeset (except
on bxt/glk in some cases), which either succeeds or
fails depending on whether userspace has given
us permission to perform a modeset or not.
Signed-off-by: Ville Syrjälä
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 30 ++
.../gpu/drm/i915/display/intel_atomic_plane.h | 2 +
drivers/gpu/drm/i915/display/intel_cdclk.c| 16 +
drivers/gpu/drm/i915/display/intel_display.c | 187 --
drivers/gpu/drm/i915/display/intel_sprite.c | 342 ++
drivers/gpu/drm/i915/display/intel_sprite.h | 7 +
drivers/gpu/drm/i915/intel_drv.h | 4 +
7 files changed, 566 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d7493551b28c..91e841d38086 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -137,6 +137,35 @@ unsigned int intel_plane_data_rate(const struct
intel_crtc_state *crtc_state,
return cpp * crtc_state->pixel_rate;
}
+bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane)
+{
+ const struct intel_plane_state *plane_state =
+ intel_atomic_get_new_plane_state(state, plane);
+ struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
+ struct intel_crtc_state *crtc_state;
+
+ if (!plane_state->base.visible || !plane->min_cdclk)
+ return false;
+
+ crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ crtc_state->min_cdclk[plane->id] =
+ plane->min_cdclk(crtc_state, plane_state);
+
+ DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz (logical cdclk %d kHz)\n",
+ plane->base.base.id, plane->base.name,
+ crtc_state->min_cdclk[plane->id],
+ state->cdclk.logical.cdclk);
+
+ /* should have been populated in intel_atomic_check_planes() */
+ WARN_ON(state->cdclk.logical.cdclk == 0);
+
+ /* Does the cdclk need to be bumbed up? */
+ return crtc_state->min_cdclk[plane->id] >
+ state->cdclk.logical.cdclk;
+}
+
int intel_plane_atomic_check_with_state(const struct intel_crtc_state
*old_crtc_state,
struct intel_crtc_state *new_crtc_state,
const struct intel_plane_state
*old_plane_state,
@@ -150,6 +179,7 @@ int intel_plane_atomic_check_with_state(const struct
intel_crtc_state *old_crtc_
new_crtc_state->nv12_planes &= ~BIT(plane->id);
new_crtc_state->c8_planes &= ~BIT(plane->id);
new_crtc_state->data_rate[plane->id] = 0;
+ new_crtc_state->min_cdclk[plane->id] = 0;
new_plane_state->base.visible = false;
if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
index dc85af02e9b7..e61e9a82aadf 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h
@@ -47,5 +47,7 @@ int intel_plane_atomic_calc_changes(const struct
intel_crtc_state *old_crtc_stat
struct intel_crtc_state *crtc_state,
const struct intel_plane_state
*old_plane_state,
struct intel_plane_state *plane_state);
+bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
+ struct intel_plane *plane);
#endif /* __INTEL_ATOMIC_PLANE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 40583d8d259b..1871c56e48ea 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2227,6 +2227,19 @@ static int intel_pixel_rate_to_cdclk(const struct
intel_crtc_state *crtc_state)
return DIV_ROUND_
[PATCH 14/19] drm/i915: Eliminate skl_check_pipe_max_pixel_rate()
From: Ville Syrjälä
The normal cdclk handling now takes care of making sure the
plane's pixel rate doesn't exceed the spec appointed percentage
of the cdclk frequency. Thus we can nuke
skl_check_pipe_max_pixel_rate().
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 2 -
drivers/gpu/drm/i915/intel_pm.c | 89
drivers/gpu/drm/i915/intel_pm.h | 2 -
3 files changed, 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 68738d177fd9..1e67fbe50476 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11845,8 +11845,6 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
if (INTEL_GEN(dev_priv) >= 9) {
if (mode_changed || crtc_state->update_pipe)
ret = skl_update_scaler_crtc(crtc_state);
- if (!ret)
- ret = skl_check_pipe_max_pixel_rate(crtc, crtc_state);
if (!ret)
ret = intel_atomic_setup_scalers(dev_priv, crtc,
crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f25a605aacf9..42775db1c7e2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4101,95 +4101,6 @@ skl_plane_downscale_amount(const struct intel_crtc_state
*crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
-static uint_fixed_16_16_t
-skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
-{
- uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
-
- if (!crtc_state->base.enable)
- return pipe_downscale;
-
- if (crtc_state->pch_pfit.enabled) {
- u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
- uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
- uint_fixed_16_16_t downscale_h, downscale_w;
-
- src_w = crtc_state->pipe_src_w;
- src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0x;
-
- if (!dst_w || !dst_h)
- return pipe_downscale;
-
- fp_w_ratio = div_fixed16(src_w, dst_w);
- fp_h_ratio = div_fixed16(src_h, dst_h);
- downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
- downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
-
- pipe_downscale = mul_fixed16(downscale_w, downscale_h);
- }
-
- return pipe_downscale;
-}
-
-int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct drm_atomic_state *state = crtc_state->base.state;
- struct drm_plane *plane;
- const struct drm_plane_state *drm_plane_state;
- int crtc_clock, dotclk;
- u32 pipe_max_pixel_rate;
- uint_fixed_16_16_t pipe_downscale;
- uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
-
- if (!crtc_state->base.enable)
- return 0;
-
- drm_atomic_crtc_state_for_each_plane_state(plane, drm_plane_state,
&crtc_state->base) {
- uint_fixed_16_16_t plane_downscale;
- uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
- int bpp;
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(drm_plane_state);
-
- if (!intel_wm_plane_visible(crtc_state, plane_state))
- continue;
-
- if (WARN_ON(!plane_state->base.fb))
- return -EINVAL;
-
- plane_downscale = skl_plane_downscale_amount(crtc_state,
plane_state);
- bpp = plane_state->base.fb->format->cpp[0] * 8;
- if (bpp == 64)
- plane_downscale = mul_fixed16(plane_downscale,
- fp_9_div_8);
-
- max_downscale = max_fixed16(plane_downscale, max_downscale);
- }
- pipe_downscale = skl_pipe_downscale_amount(crtc_state);
-
- pipe_downscale = mul_fixed16(pipe_downscale, max_downscale);
-
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
-
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
- dotclk *= 2;
-
- pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
-
- if (pipe_max_pixel_rate < crtc_clock) {
- DRM_DEBUG_KMS("Max supported pixel clock with scaling
exceeded\n");
- return -EINVAL;
- }
-
- return 0;
-}
[PATCH 12/19] drm/i915: Move check_digital_port_conflicts() earier
From: Ville Syrjälä
check_digital_port_conflicts() is done needlessly late. Move it earlier.
This will be needed as later on we want to set any_ms=true a bit later
for non-modesets too and we can't call this guy without the
connection_mutex held.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5b6300b82c50..eaed4aee4ee4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13380,11 +13380,6 @@ static int intel_modeset_checks(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int ret, i;
- if (!check_digital_port_conflicts(state)) {
- DRM_DEBUG_KMS("rejecting conflicting digital port
configuration\n");
- return -EINVAL;
- }
-
/* keep the current setting */
if (!state->cdclk.force_min_cdclk_changed)
state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk;
@@ -13546,6 +13541,12 @@ static int intel_atomic_check(struct drm_device *dev,
any_ms = true;
}
+ if (any_ms && !check_digital_port_conflicts(state)) {
+ DRM_DEBUG_KMS("rejecting conflicting digital port
configuration\n");
+ ret = EINVAL;
+ goto fail;
+ }
+
ret = drm_dp_mst_atomic_check(&state->base);
if (ret)
goto fail;
--
2.21.0
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[PATCH 09/19] drm/i915: Add debugs to distingiush a cd2x update from a full cdclk pll update
From: Ville Syrjälä
To make the logs a bit less confusing let's toss in some
debug prints to indicate whether the cdclk reprogramming
is going to happen with a single pipe active or whether we
need to turn all pipes off for the duration.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c7c46b382738..f2910c0c3e3e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2696,6 +2696,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
return ret;
state->cdclk.pipe = pipe;
+
+ DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n",
+ pipe_name(pipe));
} else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual,
&state->cdclk.actual)) {
ret = intel_modeset_all_pipes(state);
@@ -2703,6 +2706,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
return ret;
state->cdclk.pipe = INVALID_PIPE;
+
+ DRM_DEBUG_KMS("Modeset required for cdclk change\n");
}
DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u
kHz\n",
--
2.21.0
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[PATCH 15/19] drm/i915: Simplify skl_max_scale()
From: Ville Syrjälä
Now that the planes declare their minimum cdclk requirements properly
we don't need to check the cdclk in skl_max_scale() anymore. Just check
against the maximum downscale ratio, and move the code next to it's
only caller.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 38
drivers/gpu/drm/i915/display/intel_sprite.c | 12 ++-
drivers/gpu/drm/i915/intel_drv.h | 2 --
3 files changed, 11 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1e67fbe50476..489620ef476b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14525,44 +14525,6 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
mutex_unlock(&dev_priv->drm.struct_mutex);
}
-int
-skl_max_scale(const struct intel_crtc_state *crtc_state,
- const struct drm_format_info *format)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- int max_scale;
- int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
-
- if (!crtc_state->base.enable)
- return DRM_PLANE_HELPER_NO_SCALING;
-
- crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- max_dotclk =
to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
-
- if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)
- max_dotclk *= 2;
-
- if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
- return DRM_PLANE_HELPER_NO_SCALING;
-
- /*
-* skl max scale is lower of:
-*close to 3 but not 3, -1 is for that purpose
-*or
-*cdclk/crtc_clock
-*/
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
- !drm_format_info_is_yuv_semiplanar(format))
- tmpclk1 = 0x3 - 1;
- else
- tmpclk1 = 0x2 - 1;
- tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
- max_scale = min(tmpclk1, tmpclk2);
-
- return max_scale;
-}
-
static void intel_begin_crtc_commit(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index a07887279e1a..0ffbec8291ee 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2089,6 +2089,16 @@ static int skl_plane_check_nv12_rotation(const struct
intel_plane_state *plane_s
return 0;
}
+static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
+ const struct drm_framebuffer *fb)
+{
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) ||
+ !drm_format_info_is_yuv_semiplanar(fb->format))
+ return 0x3 - 1;
+ else
+ return 0x2 - 1;
+}
+
static int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
@@ -2106,7 +2116,7 @@ static int skl_plane_check(struct intel_crtc_state
*crtc_state,
/* use scaler when colorkey is not required */
if (!plane_state->ckey.flags && intel_fb_scalable(fb)) {
min_scale = 1;
- max_scale = skl_max_scale(crtc_state, fb->format);
+ max_scale = skl_plane_max_scale(dev_priv, fb);
}
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 999ad3166cd1..02eeaec86997 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1620,8 +1620,6 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(const struct intel_crtc_state *crtc_state,
- const struct drm_format_info *format);
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state
*state)
{
--
2.21.0
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[PATCH 16/19] drm/i915: Add support for half float framebuffers for skl+
From: Ville Syrjälä
skl+ supports fp16 pixel formats on all universal planes. Add the
necessary bits to expose that capability. The main different to
icl is that we can't scale fp16, so need to add the relevant
checks.
v2: Rebase on top of icl fp16
Split skl+ bits into a separate patch
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++
drivers/gpu/drm/i915/display/intel_sprite.c | 11 +++
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 489620ef476b..e5ee6bc8720c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5614,10 +5614,6 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_ARGB:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
- case DRM_FORMAT_XBGR16161616F:
- case DRM_FORMAT_ABGR16161616F:
- case DRM_FORMAT_XRGB16161616F:
- case DRM_FORMAT_ARGB16161616F:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
@@ -5633,6 +5629,13 @@ static int skl_update_scaler_plane(struct
intel_crtc_state *crtc_state,
case DRM_FORMAT_XVYU12_16161616:
case DRM_FORMAT_XVYU16161616:
break;
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ if (INTEL_GEN(dev_priv) >= 11)
+ break;
+ /* fall through */
default:
DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format
0x%x\n",
intel_plane->base.base.id, intel_plane->base.name,
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 0ffbec8291ee..6e371e68c018 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1801,6 +1801,11 @@ static bool intel_fb_scalable(const struct
drm_framebuffer *fb)
switch (fb->format->format) {
case DRM_FORMAT_C8:
return false;
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_ARGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
+ case DRM_FORMAT_ABGR16161616F:
+ return INTEL_GEN(to_i915(fb->dev)) >= 11;
default:
return true;
}
@@ -2322,6 +2327,8 @@ static const u32 skl_plane_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2337,6 +2344,8 @@ static const u32 skl_planar_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
@@ -2353,6 +2362,8 @@ static const u32 glk_planar_formats[] = {
DRM_FORMAT_ABGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
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[PATCH 17/19] drm/i915: Add support for half float framebuffers for gen4+ primary planes
From: Ville Syrjälä
gen4+ supports fp16 pixel formats on the primary planes. Add the
relevant code.
On ivb fp16 scanout is slightly busted. The output from the plane will
have 1/4 the expected value. For the primary plane we would have to
use the pipe gamma or pipe csc to correct that which would affect all
the other planes as well, hence we simply choose not to expose fp16
on the ivb primary plane. On hsw the primary plane got fixed.
On gmch platforms I observed that the plane width must be below 2k
pixels with fp16 or else we get a corrupted image. This limitation
does not seem to be documented in bspec. I verified the exact limit
using the chv pipe B primary plane since it has windowing capability.
The stride limits are unaffected by fp16.
v2: Rebase on top of icl fp16
Split thea gen4+ primary plane bits into a separate patch
Deal with HAS_GMCH()
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 49 ++--
1 file changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e5ee6bc8720c..fc4af03d1113 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -88,7 +88,17 @@ static const u32 i8xx_primary_formats[] = {
DRM_FORMAT_XRGB,
};
-/* Primary plane formats for gen >= 4 */
+/* Primary plane formats for ivb (no fp16 due to hw issue) */
+static const u32 ivb_primary_formats[] = {
+ DRM_FORMAT_C8,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB2101010,
+ DRM_FORMAT_XBGR2101010,
+};
+
+/* Primary plane formats for gen >= 4, except ivb */
static const u32 i965_primary_formats[] = {
DRM_FORMAT_C8,
DRM_FORMAT_RGB565,
@@ -96,6 +106,7 @@ static const u32 i965_primary_formats[] = {
DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB2101010,
DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_XBGR16161616F,
};
static const u64 i9xx_format_modifiers[] = {
@@ -2982,6 +2993,8 @@ static int i9xx_format_to_fourcc(int format)
return DRM_FORMAT_XRGB2101010;
case DISPPLANE_RGBX101010:
return DRM_FORMAT_XBGR2101010;
+ case DISPPLANE_RGBX161616:
+ return DRM_FORMAT_XBGR16161616F;
}
}
@@ -3691,6 +3704,9 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XBGR2101010:
dspcntr |= DISPPLANE_RGBX101010;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ dspcntr |= DISPPLANE_RGBX161616;
+ break;
default:
MISSING_CASE(fb->format->format);
return 0;
@@ -3713,7 +3729,8 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- int src_x, src_y;
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ int src_x, src_y, src_w;
u32 offset;
int ret;
@@ -3724,9 +3741,14 @@ int i9xx_check_plane_surface(struct intel_plane_state
*plane_state)
if (!plane_state->base.visible)
return 0;
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
src_x = plane_state->base.src.x1 >> 16;
src_y = plane_state->base.src.y1 >> 16;
+ /* Undocumented hardware limit on i965/g4x/vlv/chv */
+ if (HAS_GMCH(dev_priv) && fb->format->cpp[0] == 8 && src_w > 2048)
+ return -EINVAL;
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -14648,6 +14670,7 @@ static bool i965_plane_format_mod_supported(struct
drm_plane *_plane,
case DRM_FORMAT_XBGR:
case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_XBGR16161616F:
return modifier == DRM_FORMAT_MOD_LINEAR ||
modifier == I915_FORMAT_MOD_X_TILED;
default:
@@ -14877,8 +14900,26 @@ intel_primary_plane_create(struct drm_i915_private
*dev_priv, enum pipe pipe)
}
if (INTEL_GEN(dev_priv) >= 4) {
- formats = i965_primary_formats;
- num_formats = ARRAY_SIZE(i965_primary_formats);
+ /*
+* WaFP16GammaEnabling:ivb
+* "Workaround : When using the 64-bit format, the plane
+* output on each color channel has one quarter amplitude.
+* It can be brought up to full amplitude by using pipe
+* gamma correction or pipe color space conversion to
+* multiply the plane output by four."
+*
+* There is no dedicated plane gamma for the primary plane,
+* and using the pipe gamma/csc could conflict with
[PATCH 18/19] drm/i915: Add support for half float framebuffers for ivb+ sprites
From: Ville Syrjälä
ivb+ supports fp16 pixel formats on the sprite planes planes. Expose
that capability.
On ivb/hsw fp16 scanout is slightly busted. The output from the plane
will have 1/4 the expected value. For the sprite plane we can fix that
up with the plane gamma unit. This was fixed on bdw.
v2: Rebase on top of icl fp16
Split the ivb+ sprite birs into a separate patch
v3: Move ivb_need_sprite_gamma() check one level up so that
we don't waste time programming garbage into he gamma registers
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 48 ++---
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index 6e371e68c018..bd8ccc2de1da 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1285,6 +1285,16 @@ static u32 ivb_sprite_ctl_crtc(const struct
intel_crtc_state *crtc_state)
return sprctl;
}
+static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+
+ return fb->format->cpp[0] == 8 &&
+ (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv));
+}
+
static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -1307,6 +1317,12 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
sprctl |= SPRITE_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX;
+ break;
+ case DRM_FORMAT_XRGB16161616F:
+ sprctl |= SPRITE_FORMAT_RGBX161616;
+ break;
case DRM_FORMAT_YUYV:
sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
break;
@@ -1324,7 +1340,8 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
return 0;
}
- sprctl |= SPRITE_INT_GAMMA_DISABLE;
+ if (!ivb_need_sprite_gamma(plane_state))
+ sprctl |= SPRITE_INT_GAMMA_DISABLE;
if (plane_state->base.color_encoding == DRM_COLOR_YCBCR_BT709)
sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709;
@@ -1346,12 +1363,26 @@ static u32 ivb_sprite_ctl(const struct intel_crtc_state
*crtc_state,
return sprctl;
}
-static void ivb_sprite_linear_gamma(u16 gamma[18])
+static void ivb_sprite_linear_gamma(const struct intel_plane_state
*plane_state,
+ u16 gamma[18])
{
- int i;
+ int scale, i;
- for (i = 0; i < 17; i++)
- gamma[i] = (i << 10) / 16;
+ /*
+* WaFP16GammaEnabling:ivb,hsw
+* "Workaround : When using the 64-bit format, the sprite output
+* on each color channel has one quarter amplitude. It can be
+* brought up to full amplitude by using sprite internal gamma
+* correction, pipe gamma correction, or pipe color space
+* conversion to multiply the sprite output by four."
+*/
+ scale = 4;
+
+ for (i = 0; i < 16; i++)
+ gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1);
+
+ gamma[i] = min((scale * i << 10) / 16, 1 << 10);
+ i++;
gamma[i] = 3 << 10;
i++;
@@ -1365,7 +1396,10 @@ static void ivb_update_gamma(const struct
intel_plane_state *plane_state)
u16 gamma[18];
int i;
- ivb_sprite_linear_gamma(gamma);
+ if (!ivb_need_sprite_gamma(plane_state))
+ return;
+
+ ivb_sprite_linear_gamma(plane_state, gamma);
/* FIXME these register are single buffered :( */
for (i = 0; i < 16; i++)
@@ -2507,6 +2541,8 @@ static bool snb_sprite_format_mod_supported(struct
drm_plane *_plane,
switch (format) {
case DRM_FORMAT_XRGB:
case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_XRGB16161616F:
+ case DRM_FORMAT_XBGR16161616F:
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
--
2.21.0
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[PATCH 19/19] drm/i915: Add support for half float framebuffers on snb sprites
From: Ville Syrjälä
snb supports fp16 pixel formats on the sprite planes. Expose that
capability. Nothing special needs to be done, it just works.
v2: Rebase on top of icl fp16
Split snb+ sprite bits into a separate patch
Reviewed-by: Maarten Lankhorst
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_sprite.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
b/drivers/gpu/drm/i915/display/intel_sprite.c
index bd8ccc2de1da..d6c499900ab5 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -1622,6 +1622,12 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state
*crtc_state,
case DRM_FORMAT_XRGB:
dvscntr |= DVS_FORMAT_RGBX888;
break;
+ case DRM_FORMAT_XBGR16161616F:
+ dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR;
+ break;
+ case DRM_FORMAT_XRGB16161616F:
+ dvscntr |= DVS_FORMAT_RGBX161616;
+ break;
case DRM_FORMAT_YUYV:
dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
break;
@@ -2330,8 +2336,10 @@ static const u64 i9xx_plane_format_modifiers[] = {
};
static const u32 snb_plane_formats[] = {
- DRM_FORMAT_XBGR,
DRM_FORMAT_XRGB,
+ DRM_FORMAT_XBGR,
+ DRM_FORMAT_XRGB16161616F,
+ DRM_FORMAT_XBGR16161616F,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_UYVY,
--
2.21.0
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Re: [PATCH 1/2] drm/vram: store dumb bo dimensions.
On Wed, 26 Jun 2019 18:27:54 +0200
Daniel Vetter wrote:
> On Wed, Jun 26, 2019 at 04:40:13PM +0200, Sam Ravnborg wrote:
> > Hi Gerd.
> >
> > On Wed, Jun 26, 2019 at 08:55:50AM +0200, Gerd Hoffmann wrote:
> > > Store width and height of the bo. Needed in case userspace
> > > sets up a framebuffer with fb->width != bo->width..
> > >
> > > Signed-off-by: Gerd Hoffmann
> > > ---
> > > include/drm/drm_gem_vram_helper.h | 1 +
> > > drivers/gpu/drm/drm_gem_vram_helper.c | 2 ++
> > > 2 files changed, 3 insertions(+)
> > >
> > > diff --git a/include/drm/drm_gem_vram_helper.h
> > > b/include/drm/drm_gem_vram_helper.h
> > > index 1a0ea18e7a74..3692dba167df 100644
> > > --- a/include/drm/drm_gem_vram_helper.h
> > > +++ b/include/drm/drm_gem_vram_helper.h
> > > @@ -39,6 +39,7 @@ struct drm_gem_vram_object {
> > > struct drm_gem_object gem;
> > > struct ttm_buffer_object bo;
> > > struct ttm_bo_kmap_obj kmap;
> > > + unsigned int width, height;
> > >
> > > /* Supported placements are %TTM_PL_VRAM and %TTM_PL_SYSTEM */
> > > struct ttm_placement placement;
> > > diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c
> > > b/drivers/gpu/drm/drm_gem_vram_helper.c
> > > index 4de782ca26b2..c02bf7694117 100644
> > > --- a/drivers/gpu/drm/drm_gem_vram_helper.c
> > > +++ b/drivers/gpu/drm/drm_gem_vram_helper.c
> > > @@ -377,6 +377,8 @@ int drm_gem_vram_fill_create_dumb(struct drm_file
> > > *file,
> > > gbo = drm_gem_vram_create(dev, bdev, size, pg_align, interruptible);
> > > if (IS_ERR(gbo))
> > > return PTR_ERR(gbo);
> > > + gbo->width = args->width;
> > > + gbo->height = args->height;
> > >
> > > ret = drm_gem_handle_create(file, &gbo->gem, &handle);
> > > if (ret)
> >
> > Be warned, I may have missed something in the bigger picture.
> >
> > Your patch will set width and height only for dumb bo's
> > But we have several users of drm_gem_vram_create() that will
> > not set the width and height.
> >
> > So only in some cases can we rely on them being set.
> > Should this be refactored so we always set width, height.
> > Or maybe say in a small comment that width,height are only
> > set for dumb bo's?
>
> Also for dumb bo allocated buffers if userspace gets the dimensions wrong
> between dumb_create and the addfb, something is wrong. Papering over that
> by remembering the right dimensions doesn't look like a good solution.
Hi,
just a note irrelevant to this particular driver:
I have deliberately allocated a too high dumb buffer in userspace and
created multiple smaller DRM FBs out of it with different offsets
(i * 128 * stride). This has been a very useful hack to see that a
GPU-less driver actually honours fences correctly, because if it
doesn't, the whole image will be off by the offset delta, which is
epileptically easy to see.
So I'm not getting the height wrong, I am deliberately overallocating
and aliasing.
Thanks,
pq
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[PATCH] drm/exynos: add CONFIG_MMU dependency
Compile-testing this driver on a NOMMU configuration shows a link failure:
drivers/gpu/drm/exynos/exynos_drm_gem.o: In function `exynos_drm_gem_fault':
exynos_drm_gem.c:(.text+0x484): undefined reference to `vmf_insert_mixed'
Add a CONFIG_MMU dependency to ensure we only enable this in configurations
that build correctly.
Many other drm drivers have the same dependency. It would be nice to
make this work in MMU-less configurations, but evidently nobody has
ever needed this so far.
Fixes: 156bdac99061 ("drm/exynos: trigger build of all modules")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/exynos/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 60ce4a8ad9e1..6f7d3b3b3628 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -2,6 +2,7 @@
config DRM_EXYNOS
tristate "DRM Support for Samsung SoC EXYNOS Series"
depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS ||
ARCH_MULTIPLATFORM || COMPILE_TEST)
+ depends on MMU
select DRM_KMS_HELPER
select VIDEOMODE_HELPERS
select SND_SOC_HDMI_CODEC if SND_SOC
--
2.20.0
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[PATCH] drm/amdgpu: fix building without CONFIG_HMM_MIRROR
'struct hmm_mirror' is not defined without the Kconfig option set,
so we cannot include it within another struct:
In file included from drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu.h:72:
drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mn.h:69:20: error: field has
incomplete type 'struct hmm_mirror'
struct hmm_mirror mirror;
^
drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgpu_mn.h:69:9: note: forward
declaration of 'struct hmm_mirror'
struct hmm_mirror mirror;
Add the #ifdef around it that is also used for all functions operating
on it.
Fixes: 7590f6d211ec ("drm/amdgpu: Prepare for hmm_range_register API change")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
index 281fd9fef662..b8ed68943625 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h
@@ -65,8 +65,10 @@ struct amdgpu_mn {
struct rw_semaphore lock;
struct rb_root_cached objects;
+#ifdef CONFIG_HMM_MIRROR
/* HMM mirror */
struct hmm_mirror mirror;
+#endif
};
#if defined(CONFIG_HMM_MIRROR)
--
2.20.0
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[PATCH] drm/amd/display: avoid 64-bit division
On 32-bit architectures, dividing a 64-bit integer in the kernel
leads to a link error:
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
Change the two recently introduced instances to a multiply+shift
operation that is also much cheaper on 32-bit architectures.
We can do that here, since both of them are really 32-bit numbers
that change a few percent.
Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to dc_link")
Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic for
NV")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c17db5c144aa..8dbf759eba45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(
* but the difference is minimal and is in a safe direction,
* which all works well around potential ambiguity of DP 1.4a
spec.
*/
- long long fec_link_bw_kbps = link_bw_kbps * 970LL;
- link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
+ link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
+ link_bw_kbps, 32);
}
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b35327bafbc5..70ac8a95d2db 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_
calculated_states[i].dram_speed_mts = uclk_states[i] * 16 /
1000;
// FCLK:UCLK ratio is 1.08
- min_fclk_required_by_uclk = ((unsigned long
long)uclk_states[i]) * 1080 / 100;
+ min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080
/ 100, uclk_states[i], 32);
calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk
< min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk;
--
2.20.0
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[PATCH] drm/amd/display: dcn20: include linux/delay.h
Without this header, we get a compiler error in some configurations:
.../dc/dcn20/dcn20_hwseq.c: In function 'dcn20_hwss_wait_for_blank_complete':
.../dc/dcn20/dcn20_hwseq.c:1493:3: error: implicit declaration of function
'udelay' [-Werror=implicit-function-declaration]
Note: the use of udelay itself may be problematic, as can occupy
the CPU for 200ms in a busy-loop here.
Fixes: 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 4b0d8b9f61da..6925d25d2457 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -22,6 +22,7 @@
* Authors: AMD
*
*/
+#include
#include "dm_services.h"
#include "dm_helpers.h"
--
2.20.0
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[PATCH] drm/amd/powerplay: work around enum conversion warnings
A couple of calls to smu_get_current_clk_freq() and smu_force_clk_levels()
pass constants of the wrong type, leading to warnings with clang-8:
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:995:39: error: implicit
conversion from enumeration type 'PPCLK_e' to different enumeration type 'enum
smu_clk_type' [-Werror,-Wenum-conversion]
ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
~~^~~
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:775:82: note: expanded
from macro 'smu_get_current_clk_freq'
((smu)->funcs->get_current_clk_freq?
(smu)->funcs->get_current_clk_freq((smu), (clk_id), (value)) : 0)
I could not figure out what the purpose is of mixing the types
like this and if it is written like this intentionally.
Assuming this is all correct, adding an explict case is an
easy way to shut up the warnings.
Fixes: bc0fcffd36ba ("drm/amd/powerplay: Unify smu handle task function (v2)")
Fixes: 096761014227 ("drm/amd/powerplay: support sysfs to get socclk, fclk,
dcefclk")
Signed-off-by: Arnd Bergmann
---
Please check carefully if the warning is just a false positive
or we need a different patch.
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 755c6c79f724..93732623b507 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1386,8 +1386,8 @@ int smu_adjust_power_state_dynamic(struct smu_context
*smu,
&soc_mask);
if (ret)
return ret;
- smu_force_clk_levels(smu, PP_SCLK, 1 << sclk_mask);
- smu_force_clk_levels(smu, PP_MCLK, 1 << mclk_mask);
+ smu_force_clk_levels(smu, (enum smu_clk_type)PP_SCLK, 1
<< sclk_mask);
+ smu_force_clk_levels(smu, (enum smu_clk_type)PP_MCLK, 1
<< mclk_mask);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index dba02fa0de01..20d477f8dc84 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -992,7 +992,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
break;
case SMU_SOCCLK:
- ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
+ ret = smu_get_current_clk_freq(smu, (enum
smu_clk_type)PPCLK_SOCCLK, &now);
if (ret) {
pr_err("Attempt to get current socclk Failed!");
return ret;
@@ -1013,7 +1013,7 @@ static int vega20_print_clk_levels(struct smu_context
*smu,
break;
case SMU_FCLK:
- ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
+ ret = smu_get_current_clk_freq(smu, (enum
smu_clk_type)PPCLK_FCLK, &now);
if (ret) {
pr_err("Attempt to get current fclk Failed!");
return ret;
@@ -1028,7 +1028,7 @@ static int vega20_print_clk_levels(struct smu_context
*smu,
break;
case SMU_DCEFCLK:
- ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
+ ret = smu_get_current_clk_freq(smu, (enum
smu_clk_type)PPCLK_DCEFCLK, &now);
if (ret) {
pr_err("Attempt to get current dcefclk Failed!");
return ret;
--
2.20.0
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[PATCH 1/2] drm/amd/powerplay: smu_v11_0: fix uninitialized variable use
A mistake in the error handling caused an uninitialized
variable to be used:
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1102:10: error: variable
'freq' is used uninitialized whenever '?:' condition is false
[-Werror,-Wsometimes-uninitialized]
ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
^
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:880:3: note: expanded
from macro 'smu_get_current_clk_freq_by_table'
((smu)->ppt_funcs->get_current_clk_freq_by_table ?
(smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
^~~
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1114:2: note: uninitialized
use occurs here
freq *= 100;
^~~~
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1102:10: note: remove the
'?:' if its condition is always true
ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
^
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:880:3: note: expanded
from macro 'smu_get_current_clk_freq_by_table'
((smu)->ppt_funcs->get_current_clk_freq_by_table ?
(smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
^
drivers/gpu/drm/amd/amdgpu/../powerplay/smu_v11_0.c:1095:15: note: initialize
the variable 'freq' to silence this warning
uint32_t freq;
^
= 0
Bail out of smu_v11_0_get_current_clk_freq() before we get there.
Fixes: e36182490dec ("drm/amd/powerplay: fix dpm freq unit error (10KHz ->
Mhz)")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index c3f9714e9047..bd89a13b6679 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1099,9 +1099,11 @@ static int smu_v11_0_get_current_clk_freq(struct
smu_context *smu,
return -EINVAL;
/* if don't has GetDpmClockFreq Message, try get current clock by
SmuMetrics_t */
- if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0)
+ if (smu_msg_get_index(smu, SMU_MSG_GetDpmClockFreq) == 0) {
ret = smu_get_current_clk_freq_by_table(smu, clk_id, &freq);
- else {
+ if (ret)
+ return ret;
+ } else {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetDpmClockFreq,
(smu_clk_get_index(smu,
clk_id) << 16));
if (ret)
--
2.20.0
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[PATCH 2/2] drm/amd/powerplay: vega20: fix uninitialized variable use
If smu_get_current_rpm() fails, we can't use the output,
as that may be uninitialized:
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3023:8: error: variable
'current_rpm' is used uninitialized whenever '?:' condition is false
[-Werror,-Wsometimes-uninitialized]
ret = smu_get_current_rpm(smu, ¤t_rpm);
^~
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:735:3: note: expanded
from macro 'smu_get_current_rpm'
((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu),
(speed)) : 0)
^
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3024:12: note:
uninitialized use occurs here
percent = current_rpm * 100 / pptable->FanMaximumRpm;
^~~
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3023:8: note: remove the
'?:' if its condition is always true
ret = smu_get_current_rpm(smu, ¤t_rpm);
^
drivers/gpu/drm/amd/amdgpu/../powerplay/inc/amdgpu_smu.h:735:3: note: expanded
from macro 'smu_get_current_rpm'
((smu)->funcs->get_current_rpm ? (smu)->funcs->get_current_rpm((smu),
(speed)) : 0)
^
drivers/gpu/drm/amd/amdgpu/../powerplay/vega20_ppt.c:3020:22: note: initialize
the variable 'current_rpm' to silence this warning
uint32_t current_rpm;
Propagate the error code in that case.
Fixes: ee0db82027ee ("drm/amd/powerplay: move PPTable_t uses into asic level")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9ce3f1c8ae0f..20d477f8dc84 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3021,10 +3021,13 @@ static int vega20_get_fan_speed_percent(struct
smu_context *smu,
PPTable_t *pptable = smu->smu_table.driver_pptable;
ret = smu_get_current_rpm(smu, ¤t_rpm);
+ if (ret)
+ return ret;
+
percent = current_rpm * 100 / pptable->FanMaximumRpm;
*speed = percent > 100 ? 100 : percent;
- return ret;
+ return 0;
}
static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)
--
2.20.0
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Re: [PATCH] drm/exynos: add CONFIG_MMU dependency
On 7/8/19 2:46 PM, Arnd Bergmann wrote:
> Compile-testing this driver on a NOMMU configuration shows a link failure:
>
> drivers/gpu/drm/exynos/exynos_drm_gem.o: In function `exynos_drm_gem_fault':
> exynos_drm_gem.c:(.text+0x484): undefined reference to `vmf_insert_mixed'
>
> Add a CONFIG_MMU dependency to ensure we only enable this in configurations
> that build correctly.
>
> Many other drm drivers have the same dependency. It would be nice to
> make this work in MMU-less configurations, but evidently nobody has
> ever needed this so far.
>
> Fixes: 156bdac99061 ("drm/exynos: trigger build of all modules")
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/exynos/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
> index 60ce4a8ad9e1..6f7d3b3b3628 100644
> --- a/drivers/gpu/drm/exynos/Kconfig
> +++ b/drivers/gpu/drm/exynos/Kconfig
> @@ -2,6 +2,7 @@
> config DRM_EXYNOS
> tristate "DRM Support for Samsung SoC EXYNOS Series"
> depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS ||
> ARCH_MULTIPLATFORM || COMPILE_TEST)
> + depends on MMU
> select DRM_KMS_HELPER
> select VIDEOMODE_HELPERS
> select SND_SOC_HDMI_CODEC if SND_SOC
>
I seen
ERROR: "vmf_insert_mixed" [drivers/gpu/drm/exynos/exynosdrm.ko] undefined!
with older kernels when driver was build as a module, so FWIW
Reviewed-by: Vladimir Murzin
Cheers
Vladimir
[PATCH] amdgpu: fix warning about misplaced initializers
The navi10_ppt code contains two instances of an incorrect struct initializer:
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:601:33: error: suggest
braces around initialization of subobject
[-Werror,-Wmissing-braces]
static SmuMetrics_t metrics = {0};
^
{}
drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c:905:26: error: suggest
braces around initialization of subobject
[-Werror,-Wmissing-braces]
SmuMetrics_t metrics = {0};
^
Setting it to {} instead of {0} is correct and more portable here.
Fixes: ab43c4bf1cc8 ("drm/amd/powerplay: fix fan speed show error (for hwmon
pwm)")
Fixes: 98e1a543c7b1 ("drm/amd/powerplay: add function get current clock freq
interface for navi10")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index fdcea2b944ab..ce1da9e6e1bf 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -606,7 +606,7 @@ static int navi10_get_current_clk_freq_by_table(struct
smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
{
- static SmuMetrics_t metrics = {0};
+ static SmuMetrics_t metrics = {};
int ret = 0, clk_id = 0;
if (!value)
@@ -957,7 +957,7 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
static int navi10_get_fan_speed(struct smu_context *smu, uint16_t *value)
{
- SmuMetrics_t metrics = {0};
+ SmuMetrics_t metrics = {};
int ret = 0;
if (!value)
--
2.20.0
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Re: [PATCH] drm/amd/display: avoid 64-bit division
On 7/8/19 9:52 AM, Arnd Bergmann wrote:
> On 32-bit architectures, dividing a 64-bit integer in the kernel
> leads to a link error:
>
> ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
> ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
>
> Change the two recently introduced instances to a multiply+shift
> operation that is also much cheaper on 32-bit architectures.
> We can do that here, since both of them are really 32-bit numbers
> that change a few percent.
>
> Fixes: bedbbe6af4be ("drm/amd/display: Move link functions from dc to
> dc_link")
> Fixes: f18bc4e53ad6 ("drm/amd/display: update calculated bounding box logic
> for NV")
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
> drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index c17db5c144aa..8dbf759eba45 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -3072,8 +3072,8 @@ uint32_t dc_link_bandwidth_kbps(
>* but the difference is minimal and is in a safe direction,
>* which all works well around potential ambiguity of DP 1.4a
> spec.
>*/
> - long long fec_link_bw_kbps = link_bw_kbps * 970LL;
> - link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
> + link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000,
> +link_bw_kbps, 32);
> }
> #endif
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index b35327bafbc5..70ac8a95d2db 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -2657,7 +2657,7 @@ static void update_bounding_box(struct dc *dc, struct
> _vcs_dpi_soc_bounding_box_
> calculated_states[i].dram_speed_mts = uclk_states[i] * 16 /
> 1000;
>
> // FCLK:UCLK ratio is 1.08
> - min_fclk_required_by_uclk = ((unsigned long
> long)uclk_states[i]) * 1080 / 100;
> + min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080
> / 100, uclk_states[i], 32);
Even though the mul + shift will be faster here, I would prefer that
this just be a div_u64 for clarity.
Nicholas Kazlauskas
>
> calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk
> < min_dcfclk) ?
> min_dcfclk : min_fclk_required_by_uclk;
>
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[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144721|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144720|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144723|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144722|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144726|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144724|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS fails to boot with "drmmode_do_crtc_dpms cannot get last vblank counter"
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Attachment #144725|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS boots to black screen
https://bugs.freedesktop.org/show_bug.cgi?id=111087 Michel Dänzer changed: What|Removed |Added Summary|SteamOS fails to boot with |SteamOS boots to black |"drmmode_do_crtc_dpms |screen |cannot get last vblank | |counter"| --- Comment #8 from Michel Dänzer --- (In reply to Ludovico de Nittis from comment #0) > When I try to boot SteamOS I end up with just a black screen. The Xorg log file indicates that Xorg starts up in 2560x1440, then an X client switches to 1920x1080 about 0.25s later (~23s after the kernel starts booting). Do you notice anything on the monitor around that time, e.g. some kind of flicker? What does the monitor say about the input signal when the black screen is shown? Does amdgpu.dc=0 on the kernel command line make any difference? > Xorg.0.log contains this error but I'm not completely sure if it is the > cause: > (EE) AMDGPU(0): drmmode_do_crtc_dpms cannot get last vblank counter It's probably not related to that. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111089] Multiple calls to ddcutil cause hard process hangs from within the DRM/i2c system
https://bugs.freedesktop.org/show_bug.cgi?id=111089 Bug ID: 111089 Summary: Multiple calls to ddcutil cause hard process hangs from within the DRM/i2c system Product: DRI Version: XOrg git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: DRM/AMDgpu Assignee: dri-devel@lists.freedesktop.org Reporter: n...@nickvahalik.com Recently found out that my monitors can be controlled via DDC and so I have been playing around with using ddcutil[1] to control the brightness. e.g. /usr/bin/ddcutil -d 1 setvcp 10 50 & /usr/bin/ddcutil -d 2 setvcp 10 50 & Everything works beautifully... until I attempt to set the brightness on both of my monitors at the same time. Doing so causes second and subsequent calls to ddcutil to fail and hangs the process such that they cannot be killed and the system has to be hard reset. Here is the dmesg dump. I've tested this on 4.16, 4.19 and 4.20 kernels. The current workaround is to add a brief sleep between calls like this: /usr/bin/ddcutil -d 1 setvcp 10 50 sleep .1 /usr/bin/ddcutil -d 2 setvcp 10 50 I'm attaching a copy of the backtrace from dmesg. I've also opened a ticket with ddcutil [2] which may or may not be of help. [1]: https://github.com/rockowitz/ddcutil [2]: https://github.com/rockowitz/ddcutil/issues/86 [ 1290.270967] WARNING: CPU: 11 PID: 13323 at drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.c:64 dal_gpio_open_ex+0x29/0x40 [amdgpu] [ 1290.270968] Modules linked in: i2c_dev uvcvideo videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common videodev media edac_mce_amd kvm_amd kvm irqbypass snd_hda_codec_realtek nls_iso8859_1 amdgpu snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel crct10dif_pclmul snd_hda_codec snd_usb_audio snd_hda_core snd_usbmidi_lib crc32_pclmul snd_hwdep chash ghash_clmulni_intel amd_iommu_v2 snd_pcm gpu_sched snd_seq_dummy ttm snd_seq_oss snd_seq_midi drm_kms_helper snd_seq_midi_event snd_rawmidi drm snd_seq drm_panel_orientation_quirks cfbfillrect cfbimgblt snd_seq_device aesni_intel snd_timer cfbcopyarea eeepc_wmi fb_sys_fops syscopyarea asus_wmi aes_x86_64 snd sysfillrect crypto_simd sparse_keymap input_leds joydev sysimgblt cryptd glue_helper mxm_wmi video wmi_bmof soundcore ccp k10temp fb fbdev mac_hid sch_fq_codel parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic usbhid hid igb i2c_algo_bit i2c_piix4 dca nvme i2c_core ahci nvme_core libahci gpio_amdpt wmi [ 1290.271002] gpio_generic [ 1290.271005] CPU: 11 PID: 13323 Comm: ddcutil Not tainted 4.20.17-042017-generic #201903190933 [ 1290.271006] Hardware name: System manufacturer System Product Name/PRIME X470-PRO, BIOS 4207 12/07/2018 [ 1290.271075] RIP: 0010:dal_gpio_open_ex+0x29/0x40 [amdgpu] [ 1290.271076] Code: 00 0f 1f 44 00 00 55 48 83 7f 08 00 48 89 e5 75 19 89 77 18 8b 57 14 4c 8d 47 08 89 f1 8b 77 10 48 8b 3f e8 f9 04 00 00 5d c3 <0f> 0b e8 e0 1a 87 c3 b8 05 00 00 00 5d c3 66 0f 1f 84 00 00 00 00 [ 1290.271077] RSP: 0018:b2af4fe83b70 EFLAGS: 00010286 [ 1290.271079] RAX: RBX: 920037f87380 RCX: [ 1290.271080] RDX: RSI: 0003 RDI: 920037f87ca0 [ 1290.271080] RBP: b2af4fe83b70 R08: R09: 0001 [ 1290.271081] R10: R11: R12: 0003 [ 1290.271082] R13: R14: 0001 R15: 0030 [ 1290.271083] FS: 7fd33ac28b80() GS:92003ecc() knlGS: [ 1290.271084] CS: 0010 DS: ES: CR0: 80050033 [ 1290.271085] CR2: 7f762abaa040 CR3: 00063cfe CR4: 003406e0 [ 1290.271085] Call Trace: [ 1290.271155] dal_ddc_open+0x32/0xe0 [amdgpu] [ 1290.271224] acquire+0x3b/0x80 [amdgpu] [ 1290.271286] dc_link_aux_transfer+0x98/0x150 [amdgpu] [ 1290.271355] dm_dp_aux_transfer+0x9f/0x130 [amdgpu] [ 1290.271361] drm_dp_i2c_do_msg+0x8b/0x290 [drm_kms_helper] [ 1290.271367] drm_dp_i2c_xfer+0xc4/0x250 [drm_kms_helper] [ 1290.271372] __i2c_transfer+0x14a/0x450 [i2c_core] [ 1290.271376] ? _cond_resched+0x19/0x30 [ 1290.271379] i2c_transfer+0x5a/0xd0 [i2c_core] [ 1290.271383] i2c_transfer_buffer_flags+0x4d/0x70 [i2c_core] [ 1290.271386] i2cdev_write+0x56/0xa0 [i2c_dev] [ 1290.271389] __vfs_write+0x3a/0x190 [ 1290.271391] ? apparmor_file_permission+0x1a/0x20 [ 1290.271394] ? security_file_permission+0x31/0xc0 [ 1290.271396] vfs_write+0xab/0x1b0 [ 1290.271397] ksys_write+0x55/0xc0 [ 1290.271399] __x64_sys_write+0x1a/0x20 [ 1290.271402] do_syscall_64+0x5a/0x110 [ 1290.271404] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 1290.271405] RIP: 0033:0x7fd3398a7154 [ 1290.271407] Code: 89 02 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 66 90 48 8d 05 b1 07 2e 00 8b 00 85 c0 75 13 b8 01 00 00 00 0f 05 <
[PATCH 1/2] amdgpu: make pmu support optional
When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu
portion of the amdgpu driver:
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in
'struct perf_event'
struct hw_perf_event *hwc = &event->hw;
~ ^
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in
'struct perf_event'
if (event->attr.type != event->pmu->type)
~ ^
...
Use conditional compilation for this file.
Fixes: 9c7c85f7ea1f ("drm/amdgpu: add pmu counters")
Signed-off-by: Arnd Bergmann
---
drivers/gpu/drm/amd/amdgpu/Makefile| 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 --
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 3a15a46b4ecb..3f5329906fce 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -54,7 +54,9 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
amdgpu_gmc.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \
- amdgpu_vm_sdma.o amdgpu_pmu.o amdgpu_discovery.o
+ amdgpu_vm_sdma.o amdgpu_discovery.o
+
+amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o
# add asic specific block
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 30989b455047..a02ccce7bf53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2816,7 +2816,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
return r;
}
- r = amdgpu_pmu_init(adev);
+ if (IS_ENABLED(CONFIG_PERF_EVENTS))
+ r = amdgpu_pmu_init(adev);
if (r)
dev_err(adev->dev, "amdgpu_pmu_init failed\n");
@@ -2888,7 +2889,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, &dev_attr_pcie_replay_count);
amdgpu_ucode_sysfs_fini(adev);
- amdgpu_pmu_fini(adev);
+ if (IS_ENABLED(CONFIG_PERF_EVENTS))
+ amdgpu_pmu_fini(adev);
amdgpu_debugfs_preempt_cleanup(adev);
if (amdgpu_discovery)
amdgpu_discovery_fini(adev);
--
2.20.0
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[PATCH 2/2] amdgpu: make SOC15/navi support conditional
Enabling amdgpu but not CONFIG_DRM_AMD_DC leads to a warning: drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_set_ip_blocks': drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: #warning "Enable CONFIG_DRM_AMD_DC for display support on navi." [-Werror=cpp] # warning "Enable CONFIG_DRM_AMD_DC for display support on navi." ^~~ drivers/gpu/drm/amd/amdgpu/soc15.c: In function 'soc15_set_ip_blocks': drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: #warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." [-Werror=cpp] However, CONFIG_DRM_AMD_DC can only be enabled on x86, so we cannot do that when building for other architectures. Add another Kconfig symbol to handle the SOC15 and navi, making sure that we implicitly enable DC. Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/amd/amdgpu/Kconfig | 7 + drivers/gpu/drm/amd/amdgpu/Makefile| 32 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 4 files changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index a04f2fc7bf37..d7186dd88dbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -24,6 +24,13 @@ config DRM_AMDGPU_CIK radeon.cik_support=0 amdgpu.cik_support=1 +config DRM_AMDGPU_SOC15 + bool "Enable amdgpu support for SOC15 parts" + depends on DRM_AMDGPU + select DRM_AMD_DC + help + Choose this option if you want to enable support for SOC15 asics. + config DRM_AMDGPU_USERPTR bool "Always enable userptr write support" depends on DRM_AMDGPU diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 3f5329906fce..e95ae468eaa1 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -64,9 +64,10 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o -amdgpu-y += \ - vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ - vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o +amdgpu-y += vi.o mxgpu_vi.o emu_soc.o nbio_v7_4.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += gmc_v9_0.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o \ + vega10_reg_init.o vega20_reg_init.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o # add DF block amdgpu-y += \ @@ -77,7 +78,10 @@ amdgpu-y += \ amdgpu-y += \ gmc_v7_0.o \ gmc_v8_0.o \ - gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \ + gfxhub_v1_0.o mmhub_v1_0.o gfxhub_v1_1.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ + gmc_v9_0.o \ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o # add IH block @@ -86,7 +90,9 @@ amdgpu-y += \ amdgpu_ih.o \ iceland_ih.o \ tonga_ih.o \ - cz_ih.o \ + cz_ih.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ vega10_ih.o \ navi10_ih.o @@ -111,7 +117,9 @@ amdgpu-y += \ amdgpu-y += \ amdgpu_gfx.o \ amdgpu_rlc.o \ - gfx_v8_0.o \ + gfx_v8_0.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ gfx_v9_0.o \ gfx_v10_0.o @@ -119,12 +127,14 @@ amdgpu-y += \ amdgpu-y += \ amdgpu_sdma.o \ sdma_v2_4.o \ - sdma_v3_0.o \ + sdma_v3_0.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ sdma_v4_0.o \ sdma_v5_0.o # add MES block -amdgpu-y += \ +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ mes_v10_1.o # add UVD block @@ -161,8 +171,10 @@ amdgpu-y += \ amdgpu_amdkfd_fence.o \ amdgpu_amdkfd_gpuvm.o \ amdgpu_amdkfd_gfx_v8.o \ -amdgpu_amdkfd_gfx_v9.o \ -amdgpu_amdkfd_gfx_v10.o + +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ + amdgpu_amdkfd_gfx_v9.o \ + amdgpu_amdkfd_gfx_v10.o ifneq ($(CONFIG_DRM_AMDGPU_CIK),) amdgpu-y += amdgpu_amdkfd_gfx_v7.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 9fa4f25a3745..101d806ff996 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -81,6 +81,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) case CHIP_VEGAM: kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); break; +#ifdef CONFIG_DRM_AMDGPU_SOC15 case CHIP_VEGA10: case CHIP_VEGA12: case CHIP_VEGA20: @@ -90,6 +91,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) case CHIP_NAVI10: kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions(); break; +#endif default: dev_info(adev->dev, "kfd not supported on this ASIC\n"); return; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
Re: [PATCH 2/2] amdgpu: make SOC15/navi support conditional
On Mon, Jul 8, 2019 at 10:42 AM Arnd Bergmann wrote: > > Enabling amdgpu but not CONFIG_DRM_AMD_DC leads to a warning: > > drivers/gpu/drm/amd/amdgpu/nv.c: In function 'nv_set_ip_blocks': > drivers/gpu/drm/amd/amdgpu/nv.c:400:3: error: #warning "Enable > CONFIG_DRM_AMD_DC for display support on navi." [-Werror=cpp] > # warning "Enable CONFIG_DRM_AMD_DC for display support on navi." >^~~ > drivers/gpu/drm/amd/amdgpu/soc15.c: In function 'soc15_set_ip_blocks': > drivers/gpu/drm/amd/amdgpu/soc15.c:653:3: error: #warning "Enable > CONFIG_DRM_AMD_DC for display support on SOC15." [-Werror=cpp] > > However, CONFIG_DRM_AMD_DC can only be enabled on x86, so we > cannot do that when building for other architectures. DC is not limited to x86. I can drop the warning if that is the concern. Alex > > Add another Kconfig symbol to handle the SOC15 and navi, making > sure that we implicitly enable DC. > > Signed-off-by: Arnd Bergmann > --- > drivers/gpu/drm/amd/amdgpu/Kconfig | 7 + > drivers/gpu/drm/amd/amdgpu/Makefile| 32 +++--- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ > 4 files changed, 33 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig > b/drivers/gpu/drm/amd/amdgpu/Kconfig > index a04f2fc7bf37..d7186dd88dbc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Kconfig > +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig > @@ -24,6 +24,13 @@ config DRM_AMDGPU_CIK > > radeon.cik_support=0 amdgpu.cik_support=1 > > +config DRM_AMDGPU_SOC15 > + bool "Enable amdgpu support for SOC15 parts" > + depends on DRM_AMDGPU > + select DRM_AMD_DC > + help > + Choose this option if you want to enable support for SOC15 asics. > + > config DRM_AMDGPU_USERPTR > bool "Always enable userptr write support" > depends on DRM_AMDGPU > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile > b/drivers/gpu/drm/amd/amdgpu/Makefile > index 3f5329906fce..e95ae468eaa1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -64,9 +64,10 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o > kv_dpm.o \ > > amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o > dce_v6_0.o si_dpm.o si_smc.o > > -amdgpu-y += \ > - vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o > vega10_reg_init.o \ > - vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o > navi14_reg_init.o > +amdgpu-y += vi.o mxgpu_vi.o emu_soc.o nbio_v7_4.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += gmc_v9_0.o nbio_v6_1.o soc15.o > mxgpu_ai.o nbio_v7_0.o \ > + vega10_reg_init.o vega20_reg_init.o nbio_v2_3.o nv.o > navi10_reg_init.o navi14_reg_init.o > > # add DF block > amdgpu-y += \ > @@ -77,7 +78,10 @@ amdgpu-y += \ > amdgpu-y += \ > gmc_v7_0.o \ > gmc_v8_0.o \ > - gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o \ > + gfxhub_v1_0.o mmhub_v1_0.o gfxhub_v1_1.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > + gmc_v9_0.o \ > gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o > > # add IH block > @@ -86,7 +90,9 @@ amdgpu-y += \ > amdgpu_ih.o \ > iceland_ih.o \ > tonga_ih.o \ > - cz_ih.o \ > + cz_ih.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > vega10_ih.o \ > navi10_ih.o > > @@ -111,7 +117,9 @@ amdgpu-y += \ > amdgpu-y += \ > amdgpu_gfx.o \ > amdgpu_rlc.o \ > - gfx_v8_0.o \ > + gfx_v8_0.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > gfx_v9_0.o \ > gfx_v10_0.o > > @@ -119,12 +127,14 @@ amdgpu-y += \ > amdgpu-y += \ > amdgpu_sdma.o \ > sdma_v2_4.o \ > - sdma_v3_0.o \ > + sdma_v3_0.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > sdma_v4_0.o \ > sdma_v5_0.o > > # add MES block > -amdgpu-y += \ > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > mes_v10_1.o > > # add UVD block > @@ -161,8 +171,10 @@ amdgpu-y += \ > amdgpu_amdkfd_fence.o \ > amdgpu_amdkfd_gpuvm.o \ > amdgpu_amdkfd_gfx_v8.o \ > -amdgpu_amdkfd_gfx_v9.o \ > -amdgpu_amdkfd_gfx_v10.o > + > +amdgpu-$(CONFIG_DRM_AMDGPU_SOC15) += \ > + amdgpu_amdkfd_gfx_v9.o \ > + amdgpu_amdkfd_gfx_v10.o > > ifneq ($(CONFIG_DRM_AMDGPU_CIK),) > amdgpu-y += amdgpu_amdkfd_gfx_v7.o > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c > index 9fa4f25a3745..101d806ff996 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c > @@ -81,6 +81,7 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) > case CHIP_VEGAM: > kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); > break; > +#ifdef CONFIG_DRM_AMDGPU_SOC15 > case CHIP_VEGA10: > case CHIP_VEG
[PATCH v2 0/2] Add DRM ILI9341 parallel RGB panel driver
Hi, This is the v2 of the patch-set which adds support for Ilitek ILI9341 parallel RGB panels. The ILI9341 chip supports both parallel RGB input mode and SPI input mode. This driver adds support for the parallel RGB input mode. Changes since v1: * Device-tree bindings in one file * D/C GPIO pin is optional * mipi_dbi_* functions used to initialize the display * entry in MAINTAINERS sorted alphabetically * Makefile, Kconfig: DRM_PANEL_ILITEK_IL9341 renamed to DRM_PANEL_ILITEK_ILI9341 * Kconfig: depend on BACKLIGHT_CLASS_DEVICE * Kconfig: select TINYDRM_MIPI_DBI * order of include files changed * drm_mode_duplicate checked for failure Thank you Rob Herring and Sam Ravnborg for comments. Josef Lusticky (2): dt-bindings: panel: Add parallel RGB mode for Ilitek ILI9341 panels drm/panel: Add Ilitek ILI9341 parallel RGB panel driver .../bindings/display/ilitek,ili9341.txt | 67 +++- MAINTAINERS | 6 + drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile| 1 + drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 291 ++ 5 files changed, 363 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9341.c -- 2.20.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v2 2/2] drm/panel: Add Ilitek ILI9341 parallel RGB panel driver
Add driver for Ilitek ILI9341 panels in parallel RGB mode
Signed-off-by: Josef Lusticky
---
MAINTAINERS | 6 +
drivers/gpu/drm/panel/Kconfig| 9 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 291 +++
4 files changed, 307 insertions(+)
create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9341.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a76716874bd..a35bf56cc018 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5028,6 +5028,12 @@ S: Maintained
F: drivers/gpu/drm/tinydrm/hx8357d.c
F: Documentation/devicetree/bindings/display/himax,hx8357d.txt
+DRM DRIVER FOR ILITEK ILI9341 PANELS
+M: Josef Lusticky
+S: Maintained
+F: drivers/gpu/drm/panel/panel-ilitek-ili9341.c
+F: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.txt
+
DRM DRIVER FOR INTEL I810 VIDEO CARDS
S: Orphan / Obsolete
F: drivers/gpu/drm/i810/
diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index eaecd40cc32e..34a5b262f924 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -56,6 +56,15 @@ config DRM_PANEL_ILITEK_IL9322
Say Y here if you want to enable support for Ilitek IL9322
QVGA (320x240) RGB, YUV and ITU-T BT.656 panels.
+config DRM_PANEL_ILITEK_ILI9341
+ tristate "Ilitek ILI9341 240x320 panels"
+ depends on OF && SPI
+ depends on BACKLIGHT_CLASS_DEVICE
+ select TINYDRM_MIPI_DBI
+ help
+ Say Y here if you want to enable support for Ilitek ILI9341
+ QVGA (240x320) RGB panel.
+
config DRM_PANEL_ILITEK_ILI9881C
tristate "Ilitek ILI9881C-based panels"
depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 62dae45f8f74..ba4a303c1a66 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) +=
panel-feiyang-fy07024di26a30d.o
obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o
+obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o
obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o
obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o
obj-$(CONFIG_DRM_PANEL_JDI_LT070ME05000) += panel-jdi-lt070me05000.o
diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
new file mode 100644
index ..0c700b171025
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-ilitek-ili9341.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Ilitek ILI9341 drm_panel driver
+ * 240RGBx320 dots resolution TFT LCD display
+ *
+ * This driver supports the following panel configurations:
+ * - Command interface:
+ * - MIPI-DBI Type 3 Option 1
+ * (9-bit SPI with Data/Command bit - IM[3:0] = 1101)
+ * - MIPI-DBI Type 3 Option 3
+ * (8-bit SPI with Data/Command GPIO - IM[3:0] = 1110)
+ * - Graphical data interface:
+ * - MIPI-DPI 18-bit parallel RGB interface
+ *
+ * Copyright (C) 2019 Josef Lusticky
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+/* ILI9341 extended register set (Vendor Command Set) */
+#define ILI9341_IFMODE 0xB0 // clock polarity
+#define ILI9341_IFCTL 0xF6 // interface conrol
+#define ILI9341_PGAMCTRL 0xE0 // positive gamma control
+#define ILI9341_NGAMCTRL 0xE1 // negative gamma control
+
+#define ILI9341_MADCTL_MV BIT(5)
+#define ILI9341_MADCTL_MX BIT(6)
+#define ILI9341_MADCTL_MY BIT(7)
+
+/**
+ * struct ili9341_config - the display specific configuration
+ * @width_mm: physical panel width [mm]
+ * @height_mm: physical panel height [mm]
+ */
+struct ili9341_config {
+ u32 width_mm;
+ u32 height_mm;
+};
+
+struct ili9341 {
+ struct drm_panel panel;
+ struct mipi_dbi *mipi;
+ const struct ili9341_config *conf;
+};
+
+static inline struct ili9341 *panel_to_ili9341(struct drm_panel *panel)
+{
+ return container_of(panel, struct ili9341, panel);
+}
+
+static int ili9341_deinit(struct drm_panel *panel, struct ili9341 *ili)
+{
+ mipi_dbi_command(ili->mipi, MIPI_DCS_SET_DISPLAY_OFF);
+ mipi_dbi_command(ili->mipi, MIPI_DCS_ENTER_SLEEP_MODE);
+ msleep(5);
+ return 0;
+}
+
+static int ili9341_init(struct drm_panel *panel, struct ili9341 *ili)
+{
+ /* HW / SW Reset display and wait */
+ if (ili->mipi->reset)
+ mipi_dbi_hw_reset(ili->mipi);
+
+ mipi_dbi_command(ili->mipi, MIPI_DCS_SOFT_RESET);
+ msleep(120);
+
+ /* Polarity */
+ mipi_dbi_command(ili->mipi, ILI9341_IFMODE, 0xC0);
+
+ /* Interface control */
+ mipi_dbi_co
[PATCH v2 1/2] dt-bindings: panel: Add parallel RGB mode for Ilitek ILI9341 panels
ILI9341 supports both SPI input mode and parallel RGB input mode.
This commit adds parallel RGB input mode bindings.
Signed-off-by: Josef Lusticky
---
.../bindings/display/ilitek,ili9341.txt | 67 ---
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
index 169b32e4ee4e..629f38a1d0cd 100644
--- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
+++ b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt
@@ -1,27 +1,72 @@
Ilitek ILI9341 display panels
-This binding is for display panels using an Ilitek ILI9341 controller in SPI
-mode.
+This binding is for display panels using an Ilitek ILI9341 controller.
+The display panels are supported in the following graphical input modes:
+- SPI input mode
+ MIPI-DBI Type 3 Option 1 or Option 3 is used to transfer
+ commands and graphical data
+- parallel RGB input mode
+ MIPI-DBI Type 3 Option 1 or Option 3 is used for commands
+ MIPI-DPI 18-bit parallel RGB connection is used to transfer
+ graphical data
-Required properties:
-- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
-- dc-gpios:D/C pin
-- reset-gpios: Reset pin
+
+SPI input mode:
The node for this driver must be a child node of a SPI controller, hence
-all mandatory properties described in ../spi/spi-bus.txt must be specified.
+all mandatory properties described in spi/spi-bus.txt must be specified.
+
+Required properties in SPI input mode:
+- compatible: "adafruit,yx240qv29", "ilitek,ili9341"
+- backlight:phandle of the backlight device attached to the panel
+
+Optional properties in SPI input mode:
+- rotation: panel rotation in degrees counter clockwise (0,90,180,270)
+- dc-gpios: GPIO spec for the D/C pin, see gpio/gpio.txt
+- reset-gpios: GPIO spec for the reset pin, see gpio/gpio.txt
+
+
+Parallel RGB input mode:
+
+The node for this driver must be a child node of a SPI controller, hence
+all mandatory properties described in spi/spi-bus.txt must be specified.
+
+Required properties in parallel RGB input mode:
+- compatible: "displaytech,dt024ctft", "ilitek,ili9341"
+- backlight:phandle of the backlight device attached to the panel
+
+Optional properties in parallel RGB input mode:
+- dc-gpios: GPIO spec for the D/C pin, see gpio/gpio.txt
+- reset-gpios: GPIO spec for the reset pin, see gpio/gpio.txt
-Optional properties:
-- rotation:panel rotation in degrees counter clockwise (0,90,180,270)
-- backlight: phandle of the backlight device attached to the panel
+In parallel RGB input mode,
+the device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in
+media/video-interfaces.txt. This node should describe panel's video bus.
-Example:
+
+Example in SPI input mode:
display@0{
compatible = "adafruit,yx240qv29", "ilitek,ili9341";
reg = <0>;
spi-max-frequency = <3200>;
dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+ backlight = <&backlight>;
rotation = <270>;
+ };
+
+Example in parallel RGB input mode:
+ panel@{
+ compatible = "displaytech,dt024ctft", "ilitek,ili9341";
+ reg = <0>;
+ spi-max-frequency = <3200>;
+ dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
};
--
2.20.1
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[PATCH v2] drm/msm/mdp5: Find correct node for creating gem address space
Creating the msm gem address space requires a reference to the dev where
the iommu is located. The driver currently assumes this is the same as
the platform device, which breaks when the iommu is outside of the
platform device (ie in the parent). Default to using the platform device,
but check to see if that has an iommu reference, and if not, use the parent
device instead. This should handle all the various iommu designs for
mdp5 supported systems.
Signed-off-by: Jeffrey Hugo
---
v2: It turns out there isn't a universal way to get the iommu device, so
check to see if its in the current node or parent
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index 4a60f5fca6b0..02dc7d426cb0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -663,6 +663,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
struct msm_kms *kms;
struct msm_gem_address_space *aspace;
int irq, i, ret;
+ struct device *iommu_dev;
/* priv->kms would have been populated by the MDP5 driver */
kms = priv->kms;
@@ -702,7 +703,11 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
mdelay(16);
if (config->platform.iommu) {
- aspace = msm_gem_address_space_create(&pdev->dev,
+ iommu_dev = &pdev->dev;
+ if (!iommu_dev->iommu_fwspec)
+ iommu_dev = iommu_dev->parent;
+
+ aspace = msm_gem_address_space_create(iommu_dev,
config->platform.iommu, "mdp5");
if (IS_ERR(aspace)) {
ret = PTR_ERR(aspace);
--
2.17.1
[Bug 111087] SteamOS boots to black screen
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #9 from Ludovico de Nittis --- (In reply to Michel Dänzer from comment #8) > The Xorg log file indicates that Xorg starts up in 2560x1440, then an X > client switches to 1920x1080 about 0.25s later (~23s after the kernel starts > booting). Do you notice anything on the monitor around that time, e.g. some > kind of flicker? What does the monitor say about the input signal when the > black screen is shown? After trying one more time I realized that the timing reported by the Xorg log was really too high. So I tried to leave the PC in this black screen for a couple of minutes and I saw that the Xorg log entries were all starting at 140s+ Apparently it is not a static black screen but instead an endless loop? And the Xorg log is only about the last boot attempt. With a video it will be easier to show exactly what happens: https://youtu.be/YipyPIcP0lA Moreover as you can see if I move the mouse I'm able to see the SteamOS cursor for a fraction of a second before the monitor turns completely black again. > Does amdgpu.dc=0 on the kernel command line make any difference? No difference. I'll upload the Xorg log and the dmesg of it anyway, just in case it could be of any help. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/msm/a6xx: add missing MODULE_FIRMWARE()
On Wed, Jul 03, 2019 at 07:00:35AM -0700, Rob Clark wrote:
> From: Rob Clark
>
> For platforms that require the "zap shader" to take the GPU out of
> secure mode at boot, we also need the zap fw to end up in the initrd.
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
> b/drivers/gpu/drm/msm/adreno/adreno_device.c
> index d9ac8c4cd866..aa64514afd5c 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_device.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
> @@ -174,6 +174,10 @@ MODULE_FIRMWARE("qcom/a530_zap.b01");
> MODULE_FIRMWARE("qcom/a530_zap.b02");
> MODULE_FIRMWARE("qcom/a630_sqe.fw");
> MODULE_FIRMWARE("qcom/a630_gmu.bin");
> +MODULE_FIRMWARE("qcom/a630_zap.mdt");
> +MODULE_FIRMWARE("qcom/a630_zap.b00");
> +MODULE_FIRMWARE("qcom/a630_zap.b01");
> +MODULE_FIRMWARE("qcom/a630_zap.b02");
Hopefully we are in the very last days of the split PIL so we can leave this
ugliness behind us once and for all.
Reviewed-by: Jordan Crouse
> static inline bool _rev_match(uint8_t entry, uint8_t id)
> {
> --
> 2.20.1
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
___
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dri-devel@lists.freedesktop.org
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Re: [PATCH 1/1] drm/amdgpu: adopt to hmm_range_register API change
On 2019-07-07 7:30 p.m., Stephen Rothwell wrote: > Hi all, > > On Wed, 3 Jul 2019 17:09:16 -0400 Alex Deucher wrote: >> On Wed, Jul 3, 2019 at 5:03 PM Kuehling, Felix >> wrote: >>> On 2019-07-03 10:10 a.m., Jason Gunthorpe wrote: On Wed, Jul 03, 2019 at 01:55:08AM +, Kuehling, Felix wrote: > From: Philip Yang > > In order to pass mirror instead of mm to hmm_range_register, we need > pass bo instead of ttm to amdgpu_ttm_tt_get_user_pages because mirror > is part of amdgpu_mn structure, which is accessible from bo. > > Signed-off-by: Philip Yang > Reviewed-by: Felix Kuehling > Signed-off-by: Felix Kuehling > CC: Stephen Rothwell > CC: Jason Gunthorpe > CC: Dave Airlie > CC: Alex Deucher > --- >drivers/gpu/drm/Kconfig | 1 - >drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++--- >drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- >drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 +-- >drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c | 8 >drivers/gpu/drm/amd/amdgpu/amdgpu_mn.h | 5 + >drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 ++-- >drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 5 +++-- >8 files changed, 30 insertions(+), 11 deletions(-) This is too big to use as a conflict resolution, what you could do is apply the majority of the patch on top of your tree as-is (ie keep using the old hmm_range_register), then the conflict resolution for the updated AMD GPU tree can be a simple one line change: - hmm_range_register(range, mm, start, + hmm_range_register(range, mirror, start, start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT); Which is trivial for everone to deal with, and solves the problem. >>> Good idea. > With the changes added to the amdgpu tree over the weekend, I will > apply the following merge fix patch to the hmm merge today: > > From: Philip Yang > Sibject: drm/amdgpu: adopt to hmm_range_register API change > > Signed-off-by: Stephen Rothwell > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c > @@ -783,7 +783,7 @@ int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, > struct page **pages) > 0 : range->flags[HMM_PFN_WRITE]; > range->pfn_flags_mask = 0; > range->pfns = pfns; > - hmm_range_register(range, mm, start, > + hmm_range_register(range, mirror, start, > start + ttm->num_pages * PAGE_SIZE, PAGE_SHIFT); > > retry: > > And someone just needs to make sure Linus is aware of this needed merge fix. Thank you! Who will be that someone? It should probably be one of the maintainers of the trees Linux pulls from ... Regards, Felix ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/1] drm/amdgpu: adopt to hmm_range_register API change
Hi Felix, On Mon, 8 Jul 2019 15:26:22 + "Kuehling, Felix" wrote: > > Thank you! Who will be that someone? It should probably be one of the > maintainers of the trees Linux pulls from ... That would be Dave (pushing drm) or Jason (pushing hmm), or both. -- Cheers, Stephen Rothwell pgpsVn47weqyK.pgp Description: OpenPGP digital signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS boots to black screen
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #10 from Ludovico de Nittis --- Created attachment 144727 --> https://bugs.freedesktop.org/attachment.cgi?id=144727&action=edit dmesg with kernel option amdgpu.dc=0 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 111087] SteamOS boots to black screen
https://bugs.freedesktop.org/show_bug.cgi?id=111087 --- Comment #11 from Ludovico de Nittis --- Created attachment 144728 --> https://bugs.freedesktop.org/attachment.cgi?id=144728&action=edit Xorg log with kernel option amdgpu.dc=0 -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
