Re: [PATCH 1/2] drm: replace drm_[cm]alloc* by kvmalloc alternatives
On Wed, May 17, 2017 at 08:55:08AM +0200, Michal Hocko wrote: > From: Michal Hocko > > drm_[cm]alloc* has grown their own kvmalloc with vmalloc fallback > implementations. MM has grown kvmalloc* helpers in the meantime. Let's > use those because it a) reduces the code and b) MM has a better idea > how to implement fallbacks (e.g. do not vmalloc before kmalloc is tried > with __GFP_NORETRY). > > drm_calloc_large needs to get __GFP_ZERO explicitly but it is the same > thing as kvmalloc_array in principle. > > Signed-off-by: Michal Hocko Just a little surprised that calloc_large users still exist. Reviewed-by: Chris Wilson One more feature request from mm, can we have the if (size != 0 && n > SIZE_MAX / size) check exported by itself. It is used by both kvmalloc_array and kmalloc_array, and in my ioctls I have it open-coded as well to differentiate between the -EINVAL (for bogus user values) and genuine -ENOMEM. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 13/21] drm/sun4i: tcon: Change vertical total size computation inconsistency
Both TCON channels need to have the resolution doubled, since the size the hardware is going to use is whatever we put in the register divided by two. However, we handle it differently for the two channels: in the channel 0, our register access macro does the multiplication of the value passed as paremeter, while in the channel 1, the macro doesn't do this, and we need to do it before calling it. Make this consistent by aligning the channel 0 with the channel 1 behaviour. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +- drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 931dd374552e..62e254aedb57 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -194,7 +194,7 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, /* Set vertical display timings */ regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, -SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal) | +SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); /* Set Hsync and Vsync length */ diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h index f60e0b4c6db8..e3c50ecdcd04 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h @@ -52,7 +52,7 @@ #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) #define SUN4I_TCON0_BASIC2_REG 0x50 -#define SUN4I_TCON0_BASIC2_V_TOTAL(total) total) * 2) & 0x1fff) << 16) +#define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16) #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) #define SUN4I_TCON0_BASIC3_REG 0x54 -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 01/21] clk: divider: Make divider_round_rate take the parent clock
So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.
This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.
Clocks in that case cannot use divider_round_rate, so would have to come up
with a very similar logic to work around it. Instead of having to do
something like this, and duplicate that logic everywhere, create a
divider_round_rate parent to allow caller to give an additional parameter
for the parent clock to consider.
Reviewed-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/clk/clk-divider.c| 19 ++-
include/linux/clk-provider.h | 16 +---
2 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 96386ffc8483..9bb472a6 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -275,7 +275,8 @@ static int _next_div(const struct clk_div_table *table, int
div,
return div;
}
-static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
+ unsigned long rate,
unsigned long *best_parent_rate,
const struct clk_div_table *table, u8 width,
unsigned long flags)
@@ -314,8 +315,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned
long rate,
*best_parent_rate = parent_rate_saved;
return i;
}
- parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
- rate * i);
+ parent_rate = clk_hw_round_rate(parent, rate * i);
now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
if (_is_best_div(rate, now, best, flags)) {
bestdiv = i;
@@ -326,23 +326,24 @@ static int clk_divider_bestdiv(struct clk_hw *hw,
unsigned long rate,
if (!bestdiv) {
bestdiv = _get_maxdiv(table, width, flags);
- *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+ *best_parent_rate = clk_hw_round_rate(parent, 1);
}
return bestdiv;
}
-long divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate, const struct clk_div_table *table,
- u8 width, unsigned long flags)
+long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+ unsigned long rate, unsigned long *prate,
+ const struct clk_div_table *table,
+ u8 width, unsigned long flags)
{
int div;
- div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
+ div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
return DIV_ROUND_UP_ULL((u64)*prate, div);
}
-EXPORT_SYMBOL_GPL(divider_round_rate);
+EXPORT_SYMBOL_GPL(divider_round_rate_parent);
static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a428aec36ace..c59c62571e4f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -412,9 +412,10 @@ extern const struct clk_ops clk_divider_ro_ops;
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
unsigned int val, const struct clk_div_table *table,
unsigned long flags);
-long divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate, const struct clk_div_table *table,
- u8 width, unsigned long flags);
+long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
+ unsigned long rate, unsigned long *prate,
+ const struct clk_div_table *table,
+ u8 width, unsigned long flags);
int divider_get_val(unsigned long rate, unsigned long parent_rate,
const struct clk_div_table *table, u8 width,
unsigned long flags);
@@ -757,6 +758,15 @@ static inline void __clk_hw_set_clk(struct clk_hw *dst,
struct clk_hw *src)
dst->core = src->core;
}
+static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate,
+ const struct clk_div_table *table,
+ u8 width, unsigned long flags)
+{
+ return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
+rate, prate, table, width, flags);
+}
+
/*
*
[PATCH v3 00/21] drm: sun4i: Add support for the HDMI controller
Hi, Here is an attempt at getting the HDMI controller running. This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s, A20, A31). This driver only supports for now the A10s because it was an easy target, being very close to the A13 that is already supported by our DRM driver. There's nothing out of the extraordinary there, except maybe the clock setup. All the internal clocks (TMDS, DDC) have been modeled using the common clock framework, the TMDS clock being the parent of the DDC one. While this might sound overkill, other SoC have a different, external source for the DDC clock, which will be easier to support through the clock framework. The IP also supports audio (through an already supported i2s controller, and some missing configuration in the HDMI controller) and CEC. Both will come eventually. Let me know what you think! Maxime Changes from v2: - Fixed the PLL control macros definitions - Called clk_enable / disable on the DDC clock - Added the flags to enable the connection polling - Fixed the vtotal computation in TCON's code, and added a comment - Added and documented the A10s display engine compatible - Reworked the component parsing code to bail out when a standard connector is found - Fixed a inconsistent comment in the predivider unapplication - Fixed a commit log - Added Chen-Yu's and Rob's Acked-By - Changed divider_round_rate to a static, inline function in the header - Added and document the A10s display pipeline compatible - Rebased on top of 4.12 Changes from v1: - Fixed typos in the CCU header and the HDMI code - Reintroduced the comment for the backporch timings - Renamed the hdmi node to hdmi, instead of hdmi0 - Added support for hdmi-connector - Added a separate Kconfig option for the HDMI support - Changed the TCON muxing configuration for an explicit call in the TCON's "clients" - Fixed the initialisation sequence that was clearing the clocks bits - Constified the HDMI's structures and removed whitespaces errors - Fixed an issue in the sunxi-ng code that was not reporting the proper parent clock rate if it was modified - Removed unused headers - Removed CLK_SET_RATE_PARENT for the DDC clock - Used the DDC address defines - Removed the interlace flag that wasn't supported at the moment - Moved most of the HDMI encoder init to the bind function like we do for the other encoders - Switched to drm_of_find_possible_crtcs - Removed the extra printk that were still in my code - Rebased on top of linux-next - Removed the patch changing the divider_round_rate prototype to introduce a new function instead that takes the parent clock to evaluate - Added a clk_set_rate for the hdmi module clock - Fixed the V_TOTAL TCON ch0 calculation to be consistent with ch1's - Defined all registers, and remove the TODOs - Fixed the EDID issues by increasing the timeout. - Added an atomic_check to prevent the DBLCLK modes to be used, as it is not supported yet - Updated the binding to add the interrupts and DMA channels Maxime Ripard (21): clk: divider: Make divider_round_rate take the parent clock clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate clk: sunxi-ng: div: Switch to divider_round_rate clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT clk: sunxi-ng: mux: split out the pre-divider computation code clk: sunxi-ng: mux: Change pre-divider application function prototype clk: sunxi-ng: mux: Re-adjust parent rate clk: sunxi-ng: sun5i: Export video PLLs drm/sun4i: tcon: Add channel debug drm/sun4i: tcon: Move the muxing out of the mode set function drm/sun4i: tcon: Switch mux on only for composite drm/sun4i: tcon: Fix tcon channel 1 backporch calculation drm/sun4i: tcon: Change vertical total size computation inconsistency drm/sun4i: tcon: multiply the vtotal when not in interlace drm/sun4i: Ignore the generic connectors for components dt-bindings: display: sun4i: Add HDMI display bindings dt-bindings: display: sun4i: Add allwinner,tcon-channel property drm/sun4i: Add HDMI support drm/sun4i: Add compatible for the A10s pipeline ARM: sun5i: a10s: Add the HDMI controller node ARM: sun5i: a10s-olinuxino: Enable HDMI Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 91 +- arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 +- arch/arm/boot/dts/sun5i-a10s.dtsi | 47 +- arch/arm/boot/dts/sun5i.dtsi | 1 +- drivers/clk/clk-divider.c | 19 +- drivers/clk/sunxi-ng/ccu-sun5i.h | 6 +- drivers/clk/sunxi-ng/ccu_div.c| 38 +- drivers/clk/sunxi-ng/ccu_mp.c | 15 +- drivers/clk/sunxi-ng/ccu_mult.c | 19 +- drivers/clk/sunxi-ng/ccu_mux.c
[PATCH v3 06/21] clk: sunxi-ng: mux: Change pre-divider application function prototype
The current function name is a bit confusing, and doesn't really allow to create an explicit function to reverse the operation. We also for now change the parent rate through a pointer, while we don't return anything. In order to be less confusing, and easier to use for downstream users, change the function name to something hopefully clearer, and return the adjusted rate instead of changing the pointer. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu_div.c | 8 drivers/clk/sunxi-ng/ccu_mp.c | 8 drivers/clk/sunxi-ng/ccu_mult.c | 8 drivers/clk/sunxi-ng/ccu_mux.c | 29 - drivers/clk/sunxi-ng/ccu_mux.h | 8 5 files changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c index 419463375bc1..c0e5c10d0091 100644 --- a/drivers/clk/sunxi-ng/ccu_div.c +++ b/drivers/clk/sunxi-ng/ccu_div.c @@ -59,8 +59,8 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw, val = reg >> cd->div.shift; val &= (1 << cd->div.width) - 1; - ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1, - &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, + parent_rate); return divider_recalc_rate(hw, parent_rate, val, cd->div.table, cd->div.flags); @@ -83,8 +83,8 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long val; u32 reg; - ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1, - &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1, + parent_rate); val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width, cd->div.flags); diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c index de02e6c386d8..b917ad7a386c 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.c +++ b/drivers/clk/sunxi-ng/ccu_mp.c @@ -87,8 +87,8 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw, u32 reg; /* Adjust parent_rate according to pre-dividers */ - ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux, - -1, &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, + parent_rate); reg = readl(cmp->common.base + cmp->common.reg); @@ -123,8 +123,8 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate, u32 reg; /* Adjust parent_rate according to pre-dividers */ - ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux, - -1, &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1, + parent_rate); max_m = cmp->m.max ?: 1 << cmp->m.width; max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c index 6ee7ba0738fb..20d0300867f2 100644 --- a/drivers/clk/sunxi-ng/ccu_mult.c +++ b/drivers/clk/sunxi-ng/ccu_mult.c @@ -88,8 +88,8 @@ static unsigned long ccu_mult_recalc_rate(struct clk_hw *hw, val = reg >> cm->mult.shift; val &= (1 << cm->mult.width) - 1; - ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1, - &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1, + parent_rate); return parent_rate * (val + cm->mult.offset); } @@ -116,8 +116,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate, else ccu_frac_helper_disable(&cm->common, &cm->frac); - ccu_mux_helper_adjust_parent_for_prediv(&cm->common, &cm->mux, -1, - &parent_rate); + parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1, + parent_rate); _cm.min = cm->mult.min; diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c index 3eb23d4e6534..c33210972581 100644 --- a/drivers/clk/sunxi-ng/ccu_mux.c +++ b/drivers/clk/sunxi-ng/ccu_mux.c @@ -56,13 +56,12 @@ static u16 ccu_mux_get_prediv(struct ccu_common *common, return prediv; } -void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common, -struct ccu_mux_internal *cm, -int parent_index, -
[PATCH v3 02/21] clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_div.c | 7 ---
drivers/clk/sunxi-ng/ccu_mp.c | 7 ---
drivers/clk/sunxi-ng/ccu_mult.c | 11 ++-
drivers/clk/sunxi-ng/ccu_mux.c | 8 +---
drivers/clk/sunxi-ng/ccu_mux.h | 3 ++-
drivers/clk/sunxi-ng/ccu_nkm.c | 7 ---
6 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 4057e6021aa9..a489f18a3c01 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -14,7 +14,8 @@
#include "ccu_div.h"
static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
- unsigned long parent_rate,
+ struct clk_hw *parent,
+ unsigned long *parent_rate,
unsigned long rate,
void *data)
{
@@ -26,10 +27,10 @@ static unsigned long ccu_div_round_rate(struct
ccu_mux_internal *mux,
* several parents, while we might be called to evaluate
* several different parents.
*/
- val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
+ val = divider_get_val(rate, *parent_rate, cd->div.table, cd->div.width,
cd->div.flags);
- return divider_recalc_rate(&cd->common.hw, parent_rate, val,
+ return divider_recalc_rate(&cd->common.hw, *parent_rate, val,
cd->div.table, cd->div.flags);
}
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index b583f186a804..de02e6c386d8 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -41,7 +41,8 @@ static void ccu_mp_find_best(unsigned long parent, unsigned
long rate,
}
static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
- unsigned long parent_rate,
+ struct clk_hw *hw,
+ unsigned long *parent_rate,
unsigned long rate,
void *data)
{
@@ -52,9 +53,9 @@ static unsigned long ccu_mp_round_rate(struct
ccu_mux_internal *mux,
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
- ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
+ ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
- return parent_rate / p / m;
+ return *parent_rate / p / m;
}
static void ccu_mp_disable(struct clk_hw *hw)
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 671141359895..6ee7ba0738fb 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -33,9 +33,10 @@ static void ccu_mult_find_best(unsigned long parent,
unsigned long rate,
}
static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
- unsigned long parent_rate,
- unsigned long rate,
- void *data)
+struct clk_hw *parent,
+unsigned long *parent_rate,
+unsigned long rate,
+void *data)
{
struct ccu_mult *cm = data;
struct _ccu_mult _cm;
@@ -47,9 +48,9 @@ static unsigned long ccu_mult_round_rate(struct
ccu_mux_internal *mux,
else
_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
- ccu_mult_find_best(parent_rate, rate, &_cm);
+ ccu_mult_find_best(*parent_rate, rate, &_cm);
- return parent_rate * _cm.mult;
+ return *parent_rate * _cm.mult;
}
static void ccu_mult_disable(struct clk_hw *hw)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index c6bb1f523232..bae735e252b6 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -61,7 +61,8 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
struct ccu_mux_internal *cm,
struct clk_rate_request *req,
unsigned long (*round)(struct
ccu_mux_internal *,
-unsigned long,
+struct clk_hw *,
+unsigned long *,
u
[PATCH v3 04/21] clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.
However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that might be achieved for a given rate.
round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the
functions already do that if they modify the parent, or don't modify the
praents at all.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_mux.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index bae735e252b6..58b6e349a0ed 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -95,19 +95,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
if (!parent)
continue;
- if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
- struct clk_rate_request parent_req = *req;
- int ret = __clk_determine_rate(parent, &parent_req);
-
- if (ret)
- continue;
-
- parent_rate = parent_req.rate;
- } else {
- parent_rate = clk_hw_get_rate(parent);
- }
-
- adj_parent_rate = parent_rate;
+ adj_parent_rate = parent_rate = clk_hw_get_rate(parent);
ccu_mux_helper_adjust_parent_for_prediv(common, cm, i,
&adj_parent_rate);
--
git-series 0.9.1
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[PATCH v3 03/21] clk: sunxi-ng: div: Switch to divider_round_rate
divider_round_rate_parent already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_div.c | 27 ---
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index a489f18a3c01..419463375bc1 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -20,18 +20,11 @@ static unsigned long ccu_div_round_rate(struct
ccu_mux_internal *mux,
void *data)
{
struct ccu_div *cd = data;
- unsigned long val;
-
- /*
-* We can't use divider_round_rate that assumes that there's
-* several parents, while we might be called to evaluate
-* several different parents.
-*/
- val = divider_get_val(rate, *parent_rate, cd->div.table, cd->div.width,
- cd->div.flags);
- return divider_recalc_rate(&cd->common.hw, *parent_rate, val,
- cd->div.table, cd->div.flags);
+ return divider_round_rate_parent(&cd->common.hw, parent,
+rate, parent_rate,
+cd->div.table, cd->div.width,
+cd->div.flags);
}
static void ccu_div_disable(struct clk_hw *hw)
@@ -78,18 +71,6 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
{
struct ccu_div *cd = hw_to_ccu_div(hw);
- if (clk_hw_get_num_parents(hw) == 1) {
- req->rate = divider_round_rate(hw, req->rate,
- &req->best_parent_rate,
- cd->div.table,
- cd->div.width,
- cd->div.flags);
-
- req->best_parent_hw = clk_hw_get_parent(hw);
-
- return 0;
- }
-
return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
req, ccu_div_round_rate, cd);
}
--
git-series 0.9.1
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[PATCH v3 12/21] drm/sun4i: tcon: Fix tcon channel 1 backporch calculation
It seems like what's called a backporch in the datasheet is actually the
backporch plus the sync period. Fix that in our driver.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 74aa01e75e32..931dd374552e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -269,7 +269,7 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
/* Set horizontal display timings */
- bp = mode->crtc_htotal - mode->crtc_hsync_end;
+ bp = mode->crtc_htotal - mode->crtc_hsync_start;
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
mode->htotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
@@ -277,7 +277,7 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
/* Set vertical display timings */
- bp = mode->crtc_vtotal - mode->crtc_vsync_end;
+ bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
mode->vtotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
--
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[PATCH v3 05/21] clk: sunxi-ng: mux: split out the pre-divider computation code
The pre-divider retrieval code was merged into the function to apply the
current pre-divider onto the parent clock rate so that we can use that
adjusted value to do our factors computation.
However, since we'll need to do the reverse operation, we need to split out
that code into a function that will be shared.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_mux.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 58b6e349a0ed..3eb23d4e6534 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -15,24 +15,20 @@
#include "ccu_gate.h"
#include "ccu_mux.h"
-void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
-struct ccu_mux_internal *cm,
-int parent_index,
-unsigned long *parent_rate)
+static u16 ccu_mux_get_prediv(struct ccu_common *common,
+ struct ccu_mux_internal *cm,
+ int parent_index)
{
u16 prediv = 1;
u32 reg;
- int i;
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
(common->features & CCU_FEATURE_VARIABLE_PREDIV) ||
(common->features & CCU_FEATURE_ALL_PREDIV)))
- return;
+ return 1;
- if (common->features & CCU_FEATURE_ALL_PREDIV) {
- *parent_rate = *parent_rate / common->prediv;
- return;
- }
+ if (common->features & CCU_FEATURE_ALL_PREDIV)
+ return common->prediv;
reg = readl(common->base + common->reg);
if (parent_index < 0) {
@@ -40,10 +36,13 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct
ccu_common *common,
parent_index &= (1 << cm->width) - 1;
}
- if (common->features & CCU_FEATURE_FIXED_PREDIV)
+ if (common->features & CCU_FEATURE_FIXED_PREDIV) {
+ int i;
+
for (i = 0; i < cm->n_predivs; i++)
if (parent_index == cm->fixed_predivs[i].index)
prediv = cm->fixed_predivs[i].div;
+ }
if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
if (parent_index == cm->variable_prediv.index) {
@@ -54,7 +53,16 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct
ccu_common *common,
prediv = div + 1;
}
- *parent_rate = *parent_rate / prediv;
+ return prediv;
+}
+
+void ccu_mux_helper_adjust_parent_for_prediv(struct ccu_common *common,
+struct ccu_mux_internal *cm,
+int parent_index,
+unsigned long *parent_rate)
+{
+ *parent_rate = *parent_rate / ccu_mux_get_prediv(common, cm,
+parent_index);
}
int ccu_mux_helper_determine_rate(struct ccu_common *common,
--
git-series 0.9.1
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[PATCH v3 11/21] drm/sun4i: tcon: Switch mux on only for composite
Even though that mux is undocumented, it seems like it needs to be set to 1
when using composite, and 0 when using HDMI.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index a3fc6ab3c14b..74aa01e75e32 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -112,16 +112,23 @@ EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
struct drm_encoder *encoder)
{
+ u32 val;
+
if (!tcon->quirks->has_unknown_mux)
return;
if (channel != 1)
return;
+ if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
+ val = 1;
+ else
+ val = 0;
+
/*
* FIXME: Undocumented bits
*/
- regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
+ regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
}
EXPORT_SYMBOL(sun4i_tcon_set_mux);
--
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[PATCH v3 08/21] clk: sunxi-ng: sun5i: Export video PLLs
The video PLLs are used directly by the HDMI controller. Export them so that we can use them in our DT node. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- drivers/clk/sunxi-ng/ccu-sun5i.h | 6 -- include/dt-bindings/clock/sun5i-ccu.h | 3 +++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h index 8144487eb7ca..93a275fbd9a9 100644 --- a/drivers/clk/sunxi-ng/ccu-sun5i.h +++ b/drivers/clk/sunxi-ng/ccu-sun5i.h @@ -28,15 +28,17 @@ #define CLK_PLL_AUDIO_4X 6 #define CLK_PLL_AUDIO_8X 7 #define CLK_PLL_VIDEO0 8 -#define CLK_PLL_VIDEO0_2X 9 + +/* The PLL_VIDEO0_2X is exported for HDMI */ + #define CLK_PLL_VE 10 #define CLK_PLL_DDR_BASE 11 #define CLK_PLL_DDR12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL_PERIPH 14 #define CLK_PLL_VIDEO1 15 -#define CLK_PLL_VIDEO1_2X 16 +/* The PLL_VIDEO1_2X is exported for HDMI */ /* The CPU clock is exported */ #define CLK_AXI18 diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h index aeb2e2f781fb..81f34d477aeb 100644 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ b/include/dt-bindings/clock/sun5i-ccu.h @@ -19,6 +19,9 @@ #define CLK_HOSC 1 +#define CLK_PLL_VIDEO0_2X 9 + +#define CLK_PLL_VIDEO1_2X 16 #define CLK_CPU17 #define CLK_AHB_OTG23 -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v3 07/21] clk: sunxi-ng: mux: Re-adjust parent rate
Currently, the parent rate given back to the clock framework in our
request is the original parent rate we calculated before trying to round
the rate of our clock.
This works fine unless our clock also changes its parent rate, in which
case we will simply ignore that change and still use the previous parent
rate.
Create a new function to re-adjust the parent rate to take the pre-dividers
into account, and give that back to the clock framework.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_mux.c | 33 -
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index c33210972581..748b172f9193 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -64,6 +64,14 @@ unsigned long ccu_mux_helper_apply_prediv(struct ccu_common
*common,
return parent_rate / ccu_mux_get_prediv(common, cm, parent_index);
}
+unsigned long ccu_mux_helper_unapply_prediv(struct ccu_common *common,
+ struct ccu_mux_internal *cm,
+ int parent_index,
+ unsigned long parent_rate)
+{
+ return parent_rate * ccu_mux_get_prediv(common, cm, parent_index);
+}
+
int ccu_mux_helper_determine_rate(struct ccu_common *common,
struct ccu_mux_internal *cm,
struct clk_rate_request *req,
@@ -89,22 +97,37 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
best_rate = round(cm, best_parent, &adj_parent_rate,
req->rate, data);
+ /*
+* adj_parent_rate might have been modified by our clock.
+* Unapply the pre-divider if there's one, and give
+* the actual frequency the parent needs to run at.
+*/
+ best_parent_rate = ccu_mux_helper_unapply_prediv(common, cm, -1,
+
adj_parent_rate);
+
goto out;
}
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
- unsigned long tmp_rate, parent_rate, adj_parent_rate;
+ unsigned long tmp_rate, parent_rate;
struct clk_hw *parent;
parent = clk_hw_get_parent_by_index(hw, i);
if (!parent)
continue;
- parent_rate = clk_hw_get_rate(parent);
- adj_parent_rate = ccu_mux_helper_apply_prediv(common, cm, i,
- parent_rate);
+ parent_rate = ccu_mux_helper_apply_prediv(common, cm, i,
+
clk_hw_get_rate(parent));
+
+ tmp_rate = round(cm, parent, &parent_rate, req->rate, data);
- tmp_rate = round(cm, parent, &adj_parent_rate, req->rate, data);
+ /*
+* parent_rate might have been modified by our clock.
+* Unapply the pre-divider if there's one, and give
+* the actual frequency the parent needs to run at.
+*/
+ parent_rate = ccu_mux_helper_unapply_prediv(common, cm, i,
+ parent_rate);
if (tmp_rate == req->rate) {
best_parent = parent;
best_parent_rate = parent_rate;
--
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[PATCH v3 16/21] dt-bindings: display: sun4i: Add HDMI display bindings
One of the possible output of the display pipeline, on the SoCs that have
it, is the HDMI controller.
Add a binding for it.
Acked-by: Chen-Yu Tsai
Acked-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 79 +++-
1 file changed, 79 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7acdbf14ae1c..e74794f20ec5 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -14,6 +14,34 @@ Conversely, for the output ports of the same group, the
remote endpoint
ID must be the index of the local hardware block. If the local backend
is backend 1, then the remote endpoint ID must be 1.
+HDMI Encoder
+
+
+The HDMI Encoder supports the HDMI video and audio outputs, and does
+CEC. It is one end of the pipeline.
+
+Required properties:
+ - compatible: value must be one of:
+* allwinner,sun5i-a10s-hdmi
+ - reg: base address and size of memory-mapped region
+ - interrupts: interrupt associated to this IP
+ - clocks: phandles to the clocks feeding the HDMI encoder
+* ahb: the HDMI interface clock
+* mod: the HDMI module clock
+* pll-0: the first video PLL
+* pll-1: the second video PLL
+ - clock-names: the clock names mentioned above
+ - dmas: phandles to the DMA channels used by the HDMI encoder
+* ddc-tx: The channel for DDC transmission
+* ddc-rx: The channel for DDC reception
+* audio-tx: The channel used for audio transmission
+ - dma-names: the channel names mentioned above
+
+ - ports: A ports node with endpoint definitions as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The
+first port should be the input endpoint. The second should be the
+output, usually to an HDMI connector.
+
TV Encoder
--
@@ -183,6 +211,57 @@ panel: panel {
};
};
+connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+};
+
+hdmi: hdmi@01c16000 {
+ compatible = "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+<&ccu CLK_PLL_VIDEO0_2X>,
+<&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_hdmi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
+
tve0: tv-encoder@01c0a000 {
compatible = "allwinner,sun4i-a10-tv-encoder";
reg = <0x01c0a000 0x1000>;
--
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[PATCH v3 18/21] drm/sun4i: Add HDMI support
The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI controller. That HDMI controller is able to do audio and CEC, but those have been left out for now. Reviewed-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- drivers/gpu/drm/sun4i/Kconfig | 9 +- drivers/gpu/drm/sun4i/Makefile | 6 +- drivers/gpu/drm/sun4i/sun4i_hdmi.h | 157 +++- drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 127 +- drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 501 +- drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 225 +- 6 files changed, 1025 insertions(+) create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi.h create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig index a4b357db8856..35299c4e2594 100644 --- a/drivers/gpu/drm/sun4i/Kconfig +++ b/drivers/gpu/drm/sun4i/Kconfig @@ -12,3 +12,12 @@ config DRM_SUN4I Choose this option if you have an Allwinner SoC with a Display Engine. If M is selected the module will be called sun4i-drm. + +if DRM_SUN4I +config DRM_SUN4I_HDMI + tristate "Allwinner A10 HDMI Controller Support" + help + Choose this option if you have an Allwinner SoC with an HDMI + controller. + +endif diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile index 59b757350a1f..c09bf8093710 100644 --- a/drivers/gpu/drm/sun4i/Makefile +++ b/drivers/gpu/drm/sun4i/Makefile @@ -11,3 +11,9 @@ obj-$(CONFIG_DRM_SUN4I) += sun4i-drm.o sun4i-tcon.o obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o + +sun4i-drm-hdmi-y += sun4i_hdmi_enc.o +sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o +sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o + +obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h new file mode 100644 index ..2f2f2ff1ea63 --- /dev/null +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2016 Maxime Ripard + * + * Maxime Ripard + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef _SUN4I_HDMI_H_ +#define _SUN4I_HDMI_H_ + +#include +#include + +#define SUN4I_HDMI_CTRL_REG0x004 +#define SUN4I_HDMI_CTRL_ENABLE BIT(31) + +#define SUN4I_HDMI_IRQ_REG 0x008 +#define SUN4I_HDMI_IRQ_STA_MASK0x73 +#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) +#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) + +#define SUN4I_HDMI_HPD_REG 0x00c +#define SUN4I_HDMI_HPD_HIGHBIT(0) + +#define SUN4I_HDMI_VID_CTRL_REG0x010 +#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) +#define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) + +#define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 +#define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 +#define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c +#define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 + +#define SUN4I_HDMI_VID_TIMING_X(x) x) - 1) & GENMASK(11, 0))) +#define SUN4I_HDMI_VID_TIMING_Y(y) y) - 1) & GENMASK(11, 0)) << 16) + +#define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 +#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK(0x3e0 << 16) +#define SUN4I_HDMI_VID_TIMING_POL_VSYNCBIT(1) +#define SUN4I_HDMI_VID_TIMING_POL_HSYNCBIT(0) + +#define SUN4I_HDMI_AVI_INFOFRAME_REG(n)(0x080 + (n)) + +#define SUN4I_HDMI_PAD_CTRL0_REG 0x200 +#define SUN4I_HDMI_PAD_CTRL0_BIASENBIT(31) +#define SUN4I_HDMI_PAD_CTRL0_LDOCENBIT(30) +#define SUN4I_HDMI_PAD_CTRL0_LDODENBIT(29) +#define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) +#define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) +#define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) +#define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) +#define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) + +#define SUN4I_HDMI_PAD_CTRL1_REG 0x204 +#define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) +#define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) +#define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) +#define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) +#define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) +#define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) +#define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n)(((n) & 7) << 10) +#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) +#define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n
[PATCH v3 15/21] drm/sun4i: Ignore the generic connectors for components
The generic connectors such as hdmi-connector doesn't have any driver in,
so if they are added to the component list, we will be waiting forever for
a non-existing driver to probe.
Add a list of the connectors we want to ignore when building our component
list.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index c52f7a9eb045..9b3e8c8d7c75 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -166,6 +166,11 @@ static const struct component_master_ops
sun4i_drv_master_ops = {
.unbind = sun4i_drv_unbind,
};
+static bool sun4i_drv_node_is_connector(struct device_node *node)
+{
+ return of_device_is_compatible(node, "hdmi-connector");
+}
+
static bool sun4i_drv_node_is_frontend(struct device_node *node)
{
return of_device_is_compatible(node,
"allwinner,sun5i-a13-display-frontend") ||
@@ -206,6 +211,13 @@ static int sun4i_drv_add_endpoints(struct device *dev,
!of_device_is_available(node))
return 0;
+ /*
+* The connectors will be the last nodes in our pipeline, we
+* can just bail out.
+*/
+ if (sun4i_drv_node_is_connector(node))
+ return 0;
+
if (!sun4i_drv_node_is_frontend(node)) {
/* Add current component */
DRM_DEBUG_DRIVER("Adding component %s\n",
--
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[PATCH v3 10/21] drm/sun4i: tcon: Move the muxing out of the mode set function
The muxing can actually happen on both channels on some SoCs, so it makes
more sense to just move it out of the sun4i_tcon1_mode_set function and
create a separate function that needs to be called by the encoders.
Let's do that and convert the existing drivers.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_rgb.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 22 --
drivers/gpu/drm/sun4i/sun4i_tcon.h | 2 ++
drivers/gpu/drm/sun4i/sun4i_tv.c | 1 +
4 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index c9bbb3b560a5..422b191faa77 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -175,6 +175,7 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder
*encoder,
struct sun4i_tcon *tcon = rgb->tcon;
sun4i_tcon0_mode_set(tcon, mode);
+ sun4i_tcon_set_mux(tcon, 0, encoder);
/* FIXME: This seems to be board specific */
clk_set_phase(tcon->dclk, 120);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 48fadd188d65..a3fc6ab3c14b 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -109,6 +109,22 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon,
bool enable)
}
EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
+void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
+ struct drm_encoder *encoder)
+{
+ if (!tcon->quirks->has_unknown_mux)
+ return;
+
+ if (channel != 1)
+ return;
+
+ /*
+* FIXME: Undocumented bits
+*/
+ regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
+}
+EXPORT_SYMBOL(sun4i_tcon_set_mux);
+
static int sun4i_tcon_get_clk_delay(struct drm_display_mode *mode,
int channel)
{
@@ -273,12 +289,6 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
SUN4I_TCON_GCTL_IOMAP_MASK,
SUN4I_TCON_GCTL_IOMAP_TCON1);
-
- /*
-* FIXME: Undocumented bits
-*/
- if (tcon->quirks->has_unknown_mux)
- regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
}
EXPORT_SYMBOL(sun4i_tcon1_mode_set);
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index d37e1e2ed60e..f60e0b4c6db8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -196,6 +196,8 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool
enable);
/* Mode Related Controls */
void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon,
bool enable);
+void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
+ struct drm_encoder *encoder);
void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
struct drm_display_mode *mode);
void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 542da220818b..1177edaa8094 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -393,6 +393,7 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
sun4i_tcon1_mode_set(tcon, mode);
+ sun4i_tcon_set_mux(tcon, 1, encoder);
/* Enable and map the DAC to the output */
regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
--
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[PATCH v3 20/21] ARM: sun5i: a10s: Add the HDMI controller node
The A10s has an HDMI controller connected to the second TCON channel. Add
it to our DT.
Since the TV Encoder was the only channel 1 user so far, also add the
property now that we have several users.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 47 -
arch/arm/boot/dts/sun5i.dtsi | 1 +-
2 files changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 1e38ff80366c..567cce46486b 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -71,7 +71,46 @@
};
};
+ display-engine {
+ compatible = "allwinner,sun5i-a10s-display-engine";
+ allwinner,pipelines = <&fe0>;
+ };
+
soc@01c0 {
+ hdmi: hdmi@01c16000 {
+ compatible = "allwinner,sun5i-a10s-hdmi";
+ reg = <0x01c16000 0x1000>;
+ interrupts = <58>;
+ clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+<&ccu CLK_PLL_VIDEO0_2X>,
+<&ccu CLK_PLL_VIDEO1_2X>;
+ clock-names = "ahb", "mod", "pll-0", "pll-1";
+ dmas = <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_NORMAL 16>,
+ <&dma SUN4I_DMA_DEDICATED 24>;
+ dma-names = "ddc-tx", "ddc-rx", "audio-tx";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon0: endpoint {
+ remote-endpoint =
<&tcon0_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -128,3 +167,11 @@
&sram_a {
};
+
+&tcon0_out {
+ tcon0_out_hdmi: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&hdmi_in_tcon0>;
+ allwinner,tcon-channel = <1>;
+ };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 5175f9cc9bed..0e29f1d98a9e 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -272,6 +272,7 @@
tcon0_out_tve0: endpoint@1 {
reg = <1>;
remote-endpoint =
<&tve0_in_tcon0>;
+ allwinner,tcon-channel = <1>;
};
};
};
--
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[PATCH v3 21/21] ARM: sun5i: a10s-olinuxino: Enable HDMI
The A10s Olinuxino has an HDMI connector. Make sure we can use it.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 29 +-
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 894f874a5beb..1d13b6407222 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -63,6 +63,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -76,6 +87,10 @@
};
};
+&be0 {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -91,6 +106,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -248,6 +273,10 @@
status = "okay";
};
+&tcon0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
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[PATCH v3 19/21] drm/sun4i: Add compatible for the A10s pipeline
The A10s has a slightly different display pipeline than the A13, with an
HDMI controller.
Add a compatible for it.
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 0832c8491895..1b74a412aec2 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -189,6 +189,7 @@ extra node.
Required properties:
- compatible: value must be one of:
+* allwinner,sun5i-a10s-display-engine
* allwinner,sun5i-a13-display-engine
* allwinner,sun6i-a31-display-engine
* allwinner,sun6i-a31s-display-engine
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 9b3e8c8d7c75..4e0e7bd542ee 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -304,6 +304,7 @@ static int sun4i_drv_remove(struct platform_device *pdev)
}
static const struct of_device_id sun4i_drv_of_table[] = {
+ { .compatible = "allwinner,sun5i-a10s-display-engine" },
{ .compatible = "allwinner,sun5i-a13-display-engine" },
{ .compatible = "allwinner,sun6i-a31-display-engine" },
{ .compatible = "allwinner,sun6i-a31s-display-engine" },
--
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[PATCH v3 09/21] drm/sun4i: tcon: Add channel debug
While all functions have debug logs, the channel enable and disable are not
logged. Make sure this is the case.
Acked-by: Chen-Yu Tsai
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 8b6aaa60037d..48fadd188d65 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -55,6 +55,8 @@ EXPORT_SYMBOL(sun4i_tcon_enable);
void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
{
+ DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
+
/* Disable the TCON's channel */
if (channel == 0) {
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
@@ -72,6 +74,8 @@ EXPORT_SYMBOL(sun4i_tcon_channel_disable);
void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
{
+ DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
+
/* Enable the TCON's channel */
if (channel == 0) {
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
--
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[PATCH v3 14/21] drm/sun4i: tcon: multiply the vtotal when not in interlace
It appears that the total vertical resolution needs to be doubled when
we're not in interlaced. Make sure that is the case.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 62e254aedb57..a0f9a8a516c7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -153,7 +153,7 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode
*mode,
void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
struct drm_display_mode *mode)
{
- unsigned int bp, hsync, vsync;
+ unsigned int bp, hsync, vsync, vtotal;
u8 clk_delay;
u32 val = 0;
@@ -192,9 +192,26 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
mode->crtc_vtotal, bp);
+ /*
+* The vertical resolution needs to be doubled in all
+* cases. We could use crtc_vtotal and always multiply by two,
+* but that leads to a rounding error in interlace when vtotal
+* is odd.
+*
+* This happens with TV's PAL for example, where vtotal will
+* be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
+* 624, which apparently confuses the hardware.
+*
+* To work around this, we will always use vtotal, and
+* multiply by two only if we're not in interlace.
+*/
+ vtotal = mode->vtotal;
+ if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
+ vtotal = vtotal * 2;
+
/* Set vertical display timings */
regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
-SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
+SUN4I_TCON0_BASIC2_V_TOTAL(vtotal) |
SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
/* Set Hsync and Vsync length */
@@ -279,9 +296,9 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
/* Set vertical display timings */
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
-mode->vtotal, bp);
+mode->crtc_vtotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
-SUN4I_TCON1_BASIC4_V_TOTAL(mode->vtotal) |
+SUN4I_TCON1_BASIC4_V_TOTAL(mode->crtc_vtotal * 2) |
SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
/* Set Hsync and Vsync length */
--
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[PATCH v3 17/21] dt-bindings: display: sun4i: Add allwinner, tcon-channel property
The Allwinner Timings Controller has two, mutually exclusive, channels. When the binding has been introduced, it was assumed that there would be only a single user per channel in the system. While this is likely for the channel 0 which only connects to LCD displays, it turns out that the channel 1 can be connected to multiple controllers in the SoC (HDMI and TV encoders for example). And while the simultaneous use of HDMI and TV outputs cannot be achieved, switching from one to the other at runtime definitely sounds plausible. Add an extra property, allwinner,tcon-channel, to specify for a given endpoint which TCON channel it is connected to, while falling back to the previous mechanism if that property is missing. Acked-by: Chen-Yu Tsai Acked-by: Rob Herring Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 11 --- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index e74794f20ec5..0832c8491895 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -85,10 +85,13 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoint, the second one the output - The output should have two endpoints. The first is the block - connected to the TCON channel 0 (usually a panel or a bridge), the - second the block connected to the TCON channel 1 (usually the TV - encoder) + The output may have multiple endpoints. The TCON has two channels, + usually with the first channel being used for the panels interfaces + (RGB, LVDS, etc.), and the second being used for the outputs that + require another controller (TV Encoder, HDMI, etc.). The endpoints + will take an extra property, allwinner,tcon-channel, to specify the + channel the endpoint is associated to. If that property is not + present, the endpoint number will be used as the channel number. On SoCs other than the A33, there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 -- git-series 0.9.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/7] drm/omap: remove omap_drm_win
struct omap_drm_window is only used to pass plane setup data to
omap_framebuffer_update_scanout(). This can as well be accomplished by
just passing the DRM state.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_drv.h | 11 +--
drivers/gpu/drm/omapdrm/omap_fb.c| 35 ++-
drivers/gpu/drm/omapdrm/omap_plane.c | 25 +
3 files changed, 20 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h
b/drivers/gpu/drm/omapdrm/omap_drv.h
index ca087a993909..4bd1e9070b31 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -38,15 +38,6 @@
struct omap_drm_usergart;
-/* parameters which describe (unrotated) coordinates of scanout within a fb: */
-struct omap_drm_window {
- uint32_t rotation;
- int32_t crtc_x, crtc_y;/* signed because can be
offscreen */
- uint32_t crtc_w, crtc_h;
- uint32_t src_x, src_y;
- uint32_t src_w, src_h;
-};
-
/* For KMS code that needs to wait for a certain # of IRQs:
*/
struct omap_irq_wait;
@@ -157,7 +148,7 @@ struct drm_framebuffer *omap_framebuffer_init(struct
drm_device *dev,
int omap_framebuffer_pin(struct drm_framebuffer *fb);
void omap_framebuffer_unpin(struct drm_framebuffer *fb);
void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
- struct omap_drm_window *win, struct omap_overlay_info *info);
+ struct drm_plane_state *state, struct omap_overlay_info *info);
struct drm_connector *omap_framebuffer_get_next_connector(
struct drm_framebuffer *fb, struct drm_connector *from);
bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/omapdrm/omap_fb.c
index 4fc5db5d2d29..b7e7038cd2ce 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -155,7 +155,7 @@ static uint32_t drm_rotation_to_tiler(unsigned int drm_rot)
/* update ovl info for scanout, handles cases of multi-planar fb's, etc.
*/
void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
- struct omap_drm_window *win, struct omap_overlay_info *info)
+ struct drm_plane_state *state, struct omap_overlay_info *info)
{
struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
const struct drm_format_info *format = omap_fb->format;
@@ -164,25 +164,27 @@ void omap_framebuffer_update_scanout(struct
drm_framebuffer *fb,
info->fourcc = fb->format->format;
- info->pos_x = win->crtc_x;
- info->pos_y = win->crtc_y;
- info->out_width = win->crtc_w;
- info->out_height = win->crtc_h;
- info->width = win->src_w;
- info->height = win->src_h;
+ info->pos_x = state->crtc_x;
+ info->pos_y = state->crtc_y;
+ info->out_width = state->crtc_w;
+ info->out_height = state->crtc_h;
+ info->width = state->src_w >> 16;
+ info->height = state->src_h >> 16;
- x = win->src_x;
- y = win->src_y;
+ /* DSS driver wants the w & h in rotated orientation */
+ if (drm_rotation_90_or_270(state->rotation))
+ swap(info->width, info->height);
+
+ x = state->src_x >> 16;
+ y = state->src_y >> 16;
if (omap_gem_flags(plane->bo) & OMAP_BO_TILED) {
- uint32_t w = win->src_w;
- uint32_t h = win->src_h;
+ uint32_t w = state->src_w >> 16;
+ uint32_t h = state->src_h >> 16;
- orient = drm_rotation_to_tiler(win->rotation);
+ orient = drm_rotation_to_tiler(state->rotation);
/* adjust x,y offset for flip/invert: */
- if (orient & MASK_XY_FLIP)
- swap(w, h);
if (orient & MASK_Y_INVERT)
y += h - 1;
if (orient & MASK_X_INVERT)
@@ -193,7 +195,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
info->rotation_type = OMAP_DSS_ROT_TILER;
info->screen_width = omap_gem_tiled_stride(plane->bo, orient);
} else {
- switch (win->rotation & DRM_ROTATE_MASK) {
+ switch (state->rotation & DRM_ROTATE_MASK) {
case 0:
case DRM_ROTATE_0:
/* OK */
@@ -202,8 +204,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
default:
dev_warn(fb->dev->dev,
"rotation '%d' ignored for non-tiled fb\n",
- win->rotation);
- win->rotation = 0;
+ state->rotation);
break;
}
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c
b/drivers/gpu/drm/omapdrm/omap_plane.c
index 7
[PATCH 4/7] drm/omap: DRM_REFLECT_* instead of mirror boolean
Change dispc driver to use the DRM_REFLECT flags instead of a mirror
boolean.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 24 ++--
drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 --
drivers/gpu/drm/omapdrm/omap_plane.c | 1 -
3 files changed, 10 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 612170a96bdd..a25db6e25165 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -1804,15 +1804,14 @@ static void dispc_ovl_set_scaling(enum omap_plane_id
plane,
}
static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation,
- enum omap_dss_rotation_type rotation_type,
- bool mirroring, u32 fourcc)
+ enum omap_dss_rotation_type rotation_type, u32 fourcc)
{
bool row_repeat = false;
int vidrot = 0;
if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
- if (mirroring) {
+ if (rotation & DRM_REFLECT_X) {
switch (rotation & DRM_ROTATE_MASK) {
case DRM_ROTATE_0:
vidrot = 2;
@@ -2367,7 +2366,7 @@ static int dispc_ovl_setup_common(enum omap_plane_id
plane,
enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
u16 out_width, u16 out_height, u32 fourcc,
- u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
+ u8 rotation, u8 zorder, u8 pre_mult_alpha,
u8 global_alpha, enum omap_dss_rotation_type rotation_type,
bool replication, const struct videomode *vm,
bool mem_to_mem)
@@ -2515,8 +2514,7 @@ static int dispc_ovl_setup_common(enum omap_plane_id
plane,
dispc_ovl_set_vid_color_conv(plane, cconv);
}
- dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
- fourcc);
+ dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc);
dispc_ovl_set_zorder(plane, caps, zorder);
dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
@@ -2537,17 +2535,17 @@ static int dispc_ovl_setup(enum omap_plane_id plane,
const bool replication = true;
DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
- " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
+ " %dx%d, cmode %x, rot %d, chan %d repl %d\n",
plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
- oi->fourcc, oi->rotation, oi->mirror, channel, replication);
+ oi->fourcc, oi->rotation, channel, replication);
dispc_ovl_set_channel_out(plane, channel);
r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
- oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
+ oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
oi->rotation_type, replication, vm, mem_to_mem);
return r;
@@ -2569,13 +2567,12 @@ int dispc_wb_setup(const struct omap_dss_writeback_info
*wi,
OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
- "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
- in_height, wi->width, wi->height, wi->fourcc, wi->rotation,
- wi->mirror);
+ "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
+ in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
- wi->height, wi->fourcc, wi->rotation, wi->mirror, zorder,
+ wi->height, wi->fourcc, wi->rotation, zorder,
wi->pre_mult_alpha, global_alpha, wi->rotation_type,
replication, vm, mem_to_mem);
@@ -3916,7 +3913,6 @@ static const struct dispc_errata_i734_data {
.fourcc = DRM_FORMAT_XRGB,
.rotation = DRM_ROTATE_0,
.rotation_type = OMAP_DSS_ROT_NONE,
- .mirror = 0,
.pos_x = 0, .pos_y = 0,
.out_width = 0, .out_height = 0,
.global_alpha = 0xff,
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h
b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index daf792496882..e9d6b72eb69e 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
[PATCH 0/7] drm/omap: rotation fixes and cleanups
Hi, This series cleans up rotation related code and fixes the major bugs with rotation with YUV422 pixelformats. This series is based on the earlier "drm/omap: misc cleanups and pixel format change" series. There are still some smaller bugs with the rotation when used with scaling, which I will continue on debugging. Tomi Tomi Valkeinen (7): drm/omap: add drm_rotation_to_tiler helper() drm/omap: remove omap_drm_win drm/omap: use DRM_ROTATE_* instead of OMAP_DSS_ROT_* drm/omap: DRM_REFLECT_* instead of mirror boolean drm/omap: pass rotation to dispc drm/omap: fix YUV422 rotation with TILER drm/omap: fix YUV422 90/270 rotation with mirroring drivers/gpu/drm/omapdrm/dss/dispc.c | 94 -- drivers/gpu/drm/omapdrm/dss/omapdss.h | 10 drivers/gpu/drm/omapdrm/omap_drv.h| 11 +--- drivers/gpu/drm/omapdrm/omap_fb.c | 105 +- drivers/gpu/drm/omapdrm/omap_plane.c | 28 + 5 files changed, 119 insertions(+), 129 deletions(-) -- 2.7.4 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/7] drm/omap: use DRM_ROTATE_* instead of OMAP_DSS_ROT_*
At the moment the dispc driver uses a custom enum for rotation. Change
it to use the DRM's DRM_ROTATE_*.
Note that mirroring is at the moment handled as a separate boolean in
the dispc driver, so we only use the DRM_ROTATE_* values.
Note, DSS HW uses clockwise rotation, DRM counter-clockwise.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 46 +--
drivers/gpu/drm/omapdrm/dss/omapdss.h | 8 --
drivers/gpu/drm/omapdrm/omap_plane.c | 2 +-
3 files changed, 23 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 7ccbcfc1d011..612170a96bdd 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -41,6 +41,7 @@
#include
#include
#include
+#include
#include "omapdss.h"
#include "dss.h"
@@ -1600,22 +1601,20 @@ static void dispc_ovl_set_accu_uv(enum omap_plane_id
plane,
{ 0, 1, 0, 1, -1, 1, 0, 1 },
};
- switch (rotation) {
- case OMAP_DSS_ROT_0:
+ switch (rotation & DRM_ROTATE_MASK) {
+ default:
+ case DRM_ROTATE_0:
idx = 0;
break;
- case OMAP_DSS_ROT_90:
+ case DRM_ROTATE_270:
idx = 1;
break;
- case OMAP_DSS_ROT_180:
+ case DRM_ROTATE_180:
idx = 2;
break;
- case OMAP_DSS_ROT_270:
+ case DRM_ROTATE_90:
idx = 3;
break;
- default:
- BUG();
- return;
}
switch (fourcc) {
@@ -1742,8 +1741,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id
plane,
case DRM_FORMAT_YUYV:
case DRM_FORMAT_UYVY:
/* For YUV422 with 90/270 rotation, we don't upsample chroma */
- if (rotation == OMAP_DSS_ROT_0 ||
- rotation == OMAP_DSS_ROT_180) {
+ if (!drm_rotation_90_or_270(rotation)) {
if (chroma_upscale)
/* UV is subsampled by 2 horizontally */
orig_width >>= 1;
@@ -1753,7 +1751,7 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id
plane,
}
/* must use FIR for YUV422 if rotated */
- if (rotation != OMAP_DSS_ROT_0)
+ if (rotation != DRM_ROTATE_0)
scale_x = scale_y = true;
break;
@@ -1815,38 +1813,38 @@ static void dispc_ovl_set_rotation_attrs(enum
omap_plane_id plane, u8 rotation,
if (fourcc == DRM_FORMAT_YUYV || fourcc == DRM_FORMAT_UYVY) {
if (mirroring) {
- switch (rotation) {
- case OMAP_DSS_ROT_0:
+ switch (rotation & DRM_ROTATE_MASK) {
+ case DRM_ROTATE_0:
vidrot = 2;
break;
- case OMAP_DSS_ROT_90:
+ case DRM_ROTATE_270:
vidrot = 1;
break;
- case OMAP_DSS_ROT_180:
+ case DRM_ROTATE_180:
vidrot = 0;
break;
- case OMAP_DSS_ROT_270:
+ case DRM_ROTATE_90:
vidrot = 3;
break;
}
} else {
- switch (rotation) {
- case OMAP_DSS_ROT_0:
+ switch (rotation & DRM_ROTATE_MASK) {
+ case DRM_ROTATE_0:
vidrot = 0;
break;
- case OMAP_DSS_ROT_90:
+ case DRM_ROTATE_270:
vidrot = 1;
break;
- case OMAP_DSS_ROT_180:
+ case DRM_ROTATE_180:
vidrot = 2;
break;
- case OMAP_DSS_ROT_270:
+ case DRM_ROTATE_90:
vidrot = 3;
break;
}
}
- if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
+ if (drm_rotation_90_or_270(rotation))
row_repeat = true;
else
row_repeat = false;
@@ -1869,7 +1867,7 @@ static void dispc_ovl_set_rotation_attrs(enum
omap_plane_id plane, u8 rotation,
bool doublestride =
fourcc == DRM_FORMAT_NV12 &&
rotation_type == OMAP_DSS_ROT_TILER &&
- (rotation == OMAP_DSS_ROT_0 || r
[PATCH 5/7] drm/omap: pass rotation to dispc
The omapdrm driver has not passed the rotation value to the dispc
driver. This doesn't affect RGB formats, but YUV formats don't work
without dispc knowing the orientation.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_fb.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/omapdrm/omap_fb.c
index b7e7038cd2ce..bd05976fc20b 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -193,6 +193,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
omap_gem_rotated_dma_addr(plane->bo, orient, x, y,
&info->paddr);
info->rotation_type = OMAP_DSS_ROT_TILER;
+ info->rotation = state->rotation ?: DRM_ROTATE_0;
info->screen_width = omap_gem_tiled_stride(plane->bo, orient);
} else {
switch (state->rotation & DRM_ROTATE_MASK) {
@@ -210,6 +211,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer
*fb,
info->paddr = get_linear_addr(plane, format, 0, x, y);
info->rotation_type = OMAP_DSS_ROT_NONE;
+ info->rotation = DRM_ROTATE_0;
info->screen_width = plane->pitch;
}
--
2.7.4
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[PATCH 7/7] drm/omap: fix YUV422 90/270 rotation with mirroring
When rotating 90/270 + mirroring with YUV422, the end result will have
adjacent pixels swapped. The problem is that
dispc_ovl_set_rotation_attrs() has wrong rotation values for these
cases.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 80c75e5913cb..7261f87b2a5b 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -1817,13 +1817,13 @@ static void dispc_ovl_set_rotation_attrs(enum
omap_plane_id plane, u8 rotation,
vidrot = 2;
break;
case DRM_ROTATE_270:
- vidrot = 1;
+ vidrot = 3;
break;
case DRM_ROTATE_180:
vidrot = 0;
break;
case DRM_ROTATE_90:
- vidrot = 3;
+ vidrot = 1;
break;
}
} else {
--
2.7.4
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[PATCH 1/7] drm/omap: add drm_rotation_to_tiler helper()
Add a helper function to convert DRM rotation to TILER rotation.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/omap_fb.c | 56 ++-
1 file changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/omapdrm/omap_fb.c
index c565f5734a53..4fc5db5d2d29 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -122,6 +122,36 @@ bool omap_framebuffer_supports_rotation(struct
drm_framebuffer *fb)
return omap_gem_flags(plane->bo) & OMAP_BO_TILED;
}
+/* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */
+static uint32_t drm_rotation_to_tiler(unsigned int drm_rot)
+{
+ uint32_t orient;
+
+ switch (drm_rot & DRM_ROTATE_MASK) {
+ default:
+ case DRM_ROTATE_0:
+ orient = 0;
+ break;
+ case DRM_ROTATE_90:
+ orient = MASK_XY_FLIP | MASK_X_INVERT;
+ break;
+ case DRM_ROTATE_180:
+ orient = MASK_X_INVERT | MASK_Y_INVERT;
+ break;
+ case DRM_ROTATE_270:
+ orient = MASK_XY_FLIP | MASK_Y_INVERT;
+ break;
+ }
+
+ if (drm_rot & DRM_REFLECT_X)
+ orient ^= MASK_X_INVERT;
+
+ if (drm_rot & DRM_REFLECT_Y)
+ orient ^= MASK_Y_INVERT;
+
+ return orient;
+}
+
/* update ovl info for scanout, handles cases of multi-planar fb's, etc.
*/
void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
@@ -148,31 +178,7 @@ void omap_framebuffer_update_scanout(struct
drm_framebuffer *fb,
uint32_t w = win->src_w;
uint32_t h = win->src_h;
- switch (win->rotation & DRM_ROTATE_MASK) {
- default:
- dev_err(fb->dev->dev, "invalid rotation: %02x",
- (uint32_t)win->rotation);
- /* fallthru to default to no rotation */
- case 0:
- case DRM_ROTATE_0:
- orient = 0;
- break;
- case DRM_ROTATE_90:
- orient = MASK_XY_FLIP | MASK_X_INVERT;
- break;
- case DRM_ROTATE_180:
- orient = MASK_X_INVERT | MASK_Y_INVERT;
- break;
- case DRM_ROTATE_270:
- orient = MASK_XY_FLIP | MASK_Y_INVERT;
- break;
- }
-
- if (win->rotation & DRM_REFLECT_X)
- orient ^= MASK_X_INVERT;
-
- if (win->rotation & DRM_REFLECT_Y)
- orient ^= MASK_Y_INVERT;
+ orient = drm_rotation_to_tiler(win->rotation);
/* adjust x,y offset for flip/invert: */
if (orient & MASK_XY_FLIP)
--
2.7.4
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[PATCH 6/7] drm/omap: fix YUV422 rotation with TILER
TILER rotation with YUV422 pixelformats does not work at the moment. All
other pixel formats work, because the pixelformat's pixel size is equal
to tiler unit size (e.g. XR24's pixel size is 32 bits, and the TILER
unit size that has to be used is 32 bits).
For YUV422 formats this is not the case, as the TILER unit size has to
be 32 bits, but the pixel size is 16 bits. The end result is OCP errors
and sync losts.
This patch adds the code to adjust the variables for YUV422 formats.
We could make the code more generic by passing around the pixel format,
rotation type, angle and the tiler unit size, which would allow us to do
calculations without special case for YUV422. However, this would make
the code more complex, and at least for now this is much more easier to
handle with these two special cases for YUV422.
Signed-off-by: Tomi Valkeinen
---
drivers/gpu/drm/omapdrm/dss/dispc.c | 20 ++--
drivers/gpu/drm/omapdrm/omap_fb.c | 14 ++
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c
b/drivers/gpu/drm/omapdrm/dss/dispc.c
index a25db6e25165..80c75e5913cb 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -1917,7 +1917,8 @@ static s32 pixinc(int pixels, u8 ps)
static void calc_offset(u16 screen_width, u16 width,
u32 fourcc, bool fieldmode,
unsigned int field_offset, unsigned *offset0, unsigned *offset1,
- s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
+ s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
+ enum omap_dss_rotation_type rotation_type, u8 rotation)
{
u8 ps;
@@ -1925,6 +1926,20 @@ static void calc_offset(u16 screen_width, u16 width,
DSSDBG("scrw %d, width %d\n", screen_width, width);
+ if (rotation_type == OMAP_DSS_ROT_TILER &&
+ (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) &&
+ drm_rotation_90_or_270(rotation)) {
+ /*
+* HACK: ROW_INC needs to be calculated with TILER units.
+* We get such 'screen_width' that multiplying it with the
+* YUV422 pixel size gives the correct TILER container width.
+* However, 'width' is in pixels and multiplying it with YUV422
+* pixel size gives incorrect result. We thus multiply it here
+* with 2 to match the 32 bit TILER unit size.
+*/
+ width *= 2;
+ }
+
/*
* field 0 = even field = bottom field
* field 1 = odd field = top field
@@ -2473,7 +2488,8 @@ static int dispc_ovl_setup_common(enum omap_plane_id
plane,
calc_offset(screen_width, frame_width,
fourcc, fieldmode, field_offset,
&offset0, &offset1, &row_inc, &pix_inc,
- x_predecim, y_predecim);
+ x_predecim, y_predecim,
+ rotation_type, rotation);
DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
offset0, offset1, row_inc, pix_inc);
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c
b/drivers/gpu/drm/omapdrm/omap_fb.c
index bd05976fc20b..e5cc13799e73 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -184,16 +184,30 @@ void omap_framebuffer_update_scanout(struct
drm_framebuffer *fb,
orient = drm_rotation_to_tiler(state->rotation);
+ /*
+* omap_gem_rotated_paddr() wants the x & y in tiler units.
+* Usually tiler unit size is the same as the pixel size, except
+* for YUV422 formats, for which the tiler unit size is 32 bits
+* and pixel size is 16 bits.
+*/
+ if (fb->format->format == DRM_FORMAT_UYVY ||
+ fb->format->format == DRM_FORMAT_YUYV) {
+ x /= 2;
+ w /= 2;
+ }
+
/* adjust x,y offset for flip/invert: */
if (orient & MASK_Y_INVERT)
y += h - 1;
if (orient & MASK_X_INVERT)
x += w - 1;
+ /* Note: x and y are in TILER units, not pixels */
omap_gem_rotated_dma_addr(plane->bo, orient, x, y,
&info->paddr);
info->rotation_type = OMAP_DSS_ROT_TILER;
info->rotation = state->rotation ?: DRM_ROTATE_0;
+ /* Note: stride in TILER units, not pixels */
info->screen_width = omap_gem_tiled_stride(plane->bo, orient);
} else {
switch (state->rotation & DRM_ROTATE_MASK) {
--
2.7.4
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Re: [PATCH] drm: use kvmalloc_array for drm_malloc*
On Wed, May 17, 2017 at 09:44:53AM +0200, Michal Hocko wrote: > On Tue 16-05-17 12:09:08, Chris Wilson wrote: > > On Tue, May 16, 2017 at 12:53:52PM +0200, Michal Hocko wrote: > > > On Tue 16-05-17 10:31:19, Chris Wilson wrote: > > > > On Tue, May 16, 2017 at 11:06:06AM +0200, Michal Hocko wrote: > > > > > From: Michal Hocko > > > > > > > > > > drm_malloc* has grown their own kmalloc with vmalloc fallback > > > > > implementations. MM has grown kvmalloc* helpers in the meantime. Let's > > > > > use those because it a) reduces the code and b) MM has a better idea > > > > > how to implement fallbacks (e.g. do not vmalloc before kmalloc is > > > > > tried > > > > > with __GFP_NORETRY). > > > > > > > > Better? The same idea. The only difference I was reluctant to hand out > > > > large pages for long lived objects. If that's the wisdom of the core mm, > > > > so be it. > > > > > > vmalloc tends to fragment physical memory more os it is preferable to > > > try the physically contiguous request first and only fall back to > > > vmalloc if the first attempt would be too costly or it fails. > > > > Not relevant for the changelog in this patch, but it would be nice to > > have that written in kvmalloc() as to why the scatterring of 4k vmapped > > pages prevents defragmentation when compared to allocating large pages. > > Well, it is not as much about defragmentation because both vmapped and > kmalloc allocations are very likely to be unmovable (at least > currently). Theoretically there shouldn't be a problem to make vmapped > pages movable as the ptes can be modified but this is not implemented... > The problem is that vmapped pages are more likely to break up more > larger order blocks. kmalloc will naturally break a single larger block. > > > I have vague recollections of seeing the conversation, but a summary as > > to the reason why kvmalloc prefers large pages will be good for future > > reference. > > Does the following sound better to you? > > diff --git a/mm/util.c b/mm/util.c > index 464df3489903..87499f8119f2 100644 > --- a/mm/util.c > +++ b/mm/util.c > @@ -357,7 +357,10 @@ void *kvmalloc_node(size_t size, gfp_t flags, int node) > WARN_ON_ONCE((flags & GFP_KERNEL) != GFP_KERNEL); > > /* > - * Make sure that larger requests are not too disruptive - no OOM > + * We want to attempt a large physically contiguous block first because > + * it is less likely to fragment multiple larger blocks and therefore > + * contribute to a long term fragmentation less than vmalloc fallback. > + * However make sure that larger requests are not too disruptive - no > OOM >* killer and no allocation failure warnings as we have a fallback >*/ Hmm, shouldn't we also teach vmalloc to allocate large chunks where possible - even mixing huge and normal pages? As well as avoiding pinning the pages and allowing migration. That comment is helping me to understand why the decison is made to favour kmalloc over vmalloc, thanks. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 3/3] staging: android: ion: Avoid calling free_duped_table() twice
Currently, the duplicated sg table is freed in the detach() and
the error path of map_dma_buf() ion's dma_buf_ops.
If a call to dma_buf_map_attachment() fails, the importer is
expected to call dma_buf_detach() to remove the attachment. This
will result in us trying to free the duped sg table twice.
Don't call free_duped_table() in ion_map_dma_buf() to avoid this.
Signed-off-by: Archit Taneja
---
drivers/staging/android/ion/ion.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/staging/android/ion/ion.c
index 90ae6ce466ed..b483e1081309 100644
--- a/drivers/staging/android/ion/ion.c
+++ b/drivers/staging/android/ion/ion.c
@@ -268,20 +268,14 @@ static struct sg_table *ion_map_dma_buf(struct
dma_buf_attachment *attachment,
{
struct ion_dma_buf_attachment *a = attachment->priv;
struct sg_table *table;
- int ret;
table = a->table;
if (!dma_map_sg(attachment->dev, table->sgl, table->nents,
- direction)){
- ret = -ENOMEM;
- goto err;
- }
- return table;
+ direction))
+ return ERR_PTR(-ENOMEM);
-err:
- free_duped_table(table);
- return ERR_PTR(ret);
+ return table;
}
static void ion_unmap_dma_buf(struct dma_buf_attachment *attachment,
--
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[PATCH 1/3] staging: android: ion: Remove unused members from ion_buffer
A few members in ion_buffer struct are unused after features
like page faulting, ion_handle and ion_client were removed.
Remove these members and the leftover references to them.
Signed-off-by: Archit Taneja
---
drivers/staging/android/ion/ion.c | 2 --
drivers/staging/android/ion/ion.h | 14 --
2 files changed, 16 deletions(-)
diff --git a/drivers/staging/android/ion/ion.c
b/drivers/staging/android/ion/ion.c
index 03d3a4fce0e2..90ae6ce466ed 100644
--- a/drivers/staging/android/ion/ion.c
+++ b/drivers/staging/android/ion/ion.c
@@ -115,7 +115,6 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap
*heap,
buffer->dev = dev;
buffer->size = len;
- INIT_LIST_HEAD(&buffer->vmas);
INIT_LIST_HEAD(&buffer->attachments);
mutex_init(&buffer->lock);
mutex_lock(&dev->buffer_lock);
@@ -135,7 +134,6 @@ void ion_buffer_destroy(struct ion_buffer *buffer)
if (WARN_ON(buffer->kmap_cnt > 0))
buffer->heap->ops->unmap_kernel(buffer->heap, buffer);
buffer->heap->ops->free(buffer);
- vfree(buffer->pages);
kfree(buffer);
}
diff --git a/drivers/staging/android/ion/ion.h
b/drivers/staging/android/ion/ion.h
index ace8416bd509..fa9ed81ab972 100644
--- a/drivers/staging/android/ion/ion.h
+++ b/drivers/staging/android/ion/ion.h
@@ -68,14 +68,6 @@ struct ion_platform_heap {
* @kmap_cnt: number of times the buffer is mapped to the kernel
* @vaddr: the kernel mapping if kmap_cnt is not zero
* @sg_table: the sg table for the buffer if dmap_cnt is not zero
- * @pages: flat array of pages in the buffer -- used by fault
- * handler and only valid for buffers that are faulted in
- * @vmas: list of vma's mapping this buffer
- * @handle_count: count of handles referencing this buffer
- * @task_comm: taskcomm of last client to reference this buffer in a
- * handle, used for debugging
- * @pid: pid of last client to reference this buffer in a
- * handle, used for debugging
*/
struct ion_buffer {
union {
@@ -92,13 +84,7 @@ struct ion_buffer {
int kmap_cnt;
void *vaddr;
struct sg_table *sg_table;
- struct page **pages;
- struct list_head vmas;
struct list_head attachments;
- /* used to track orphaned buffers */
- int handle_count;
- char task_comm[TASK_COMM_LEN];
- pid_t pid;
};
void ion_buffer_destroy(struct ion_buffer *buffer);
--
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[PATCH 0/3] staging: android: ion: Minor clean ups and fixes
The recent ION clean ups introduced some leftover code that can be removed, and a bug that comes up if the call to dma_buf_map_attachment() from an importer fails. Fix these. Archit Taneja (3): staging: android: ion: Remove unused members from ion_buffer staging: android: ion: Remove ION_FLAG_CACHED_NEEDS_SYNC staging: android: ion: Avoid calling free_duped_table() twice drivers/staging/android/ion/ion.c | 14 +++--- drivers/staging/android/ion/ion.h | 14 -- drivers/staging/android/uapi/ion.h | 6 -- 3 files changed, 3 insertions(+), 31 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/3] staging: android: ion: Remove ION_FLAG_CACHED_NEEDS_SYNC
The flag ION_FLAG_CACHED_NEEDS_SYNC isn't used anymore. Remove it.
Signed-off-by: Archit Taneja
---
drivers/staging/android/uapi/ion.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/staging/android/uapi/ion.h
b/drivers/staging/android/uapi/ion.h
index b76db1b2e197..d415589757e7 100644
--- a/drivers/staging/android/uapi/ion.h
+++ b/drivers/staging/android/uapi/ion.h
@@ -57,12 +57,6 @@ enum ion_heap_type {
*/
#define ION_FLAG_CACHED 1
-/*
- * mappings of this buffer will created at mmap time, if this is set
- * caches must be managed manually
- */
-#define ION_FLAG_CACHED_NEEDS_SYNC 2
-
/**
* DOC: Ion Userspace API
*
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Re: [PATCH] gpu: drm: radeon: refactor code
Am 17.05.2017 um 04:20 schrieb Gustavo A. R. Silva: Local variable _color_ is assigned to a constant value and it is never updated again. Remove this variable and refactor the code it affects. Addresses-Coverity-ID: 1226745 Signed-off-by: Gustavo A. R. Silva Mhm, on the one hand it looks like a valid cleanup. On the other that is legacy code we haven't touched in a while. Feel free to put my Reviewed-by: Christian König on it, but I'm not sure if Alex will pick it up. Regards, Christian. --- drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 222a1fa..7235d0c 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -640,7 +640,6 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc uint32_t vclk_ecp_cntl, crtc_ext_cntl; uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; enum drm_connector_status found = connector_status_disconnected; - bool color = true; /* just don't bother on RN50 those chip are often connected to remoting * console hw and often we get failure to load detect those. So to make @@ -665,12 +664,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc WREG32(RADEON_CRTC_EXT_CNTL, tmp); tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | - RADEON_DAC_FORCE_DATA_EN; - - if (color) - tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; - else - tmp |= RADEON_DAC_FORCE_DATA_SEL_G; + RADEON_DAC_FORCE_DATA_EN | RADEON_DAC_FORCE_DATA_SEL_RGB; if (ASIC_IS_R300(rdev)) tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 0/3] Cleanup evergreen/si IRQ handling code
Am 16.05.2017 um 23:11 schrieb Lyude:
This is the first part of me going through and cleaning up the IRQ handling
code for radeon, since after taking a look at it the other day while trying to
debug something I realized basically all of the code was copy pasted
everywhere, and quite difficult to actually read through.
Will come up with something for r600 and cik once I've got the chipsets on hand
to test with.
Oh, yes please. This always annoyed me as well, but never had the time
to clean it up globally.
Just two general comments:
1. Don't modify the register headers.
They are more or less from a database and we don't want manual code like
this in there:
+#define DISP_INTERRUPT_STATUS(i) \
+ ((i < 4) ? 0x60f4 + (0x4 * i) : 0x614c + (0x4 * (i - 4)))
Instead use a static constant array, e.g. like this:
static const uint32_t disp_interrupt_status[4] {
DISP_INTERRUPT_STATUS,
DISP_INTERRUPT_STATUS_CONTINUE,
...
};
2. Keep the order in which stuff is written to the regs exactly the same.
In other words, don't replace this:
- rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC0_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC1_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC2_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC3_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC4_REGISTER_OFFSET);
- rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS +
EVERGREEN_CRTC5_REGISTER_OFFSET);
With:
for (i = 0; i < EVERGREEN_MAX_DISP_REGISTERS; i++) {
disp_int[i] = RREG32(DISP_INTERRUPT_STATUS(i));
+ afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
if (disp_int[i] & DC_HPDx_INTERRUPT)
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
if (disp_int[i] & DC_HPDx_RX_INTERRUPT)
WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);
+ if (afmt_status[i] & AFMT_AZ_FORMAT_WTRIG)
+ WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
+ AFMT_AZ_FORMAT_WTRIG_ACK);
Regards,
Christian.
Lyude (3):
drm/radeon: Cleanup display interrupt handling for evergreen, si
drm/radeon: Cleanup HDMI audio interrupt handling for evergreen
drm/radeon: Cleanup pageflipping IRQ handling for evergreen, si
drivers/gpu/drm/radeon/evergreen.c | 915 +---
drivers/gpu/drm/radeon/evergreend.h | 74 +--
drivers/gpu/drm/radeon/radeon.h | 27 +-
drivers/gpu/drm/radeon/radeon_irq_kms.c | 35 ++
drivers/gpu/drm/radeon/si.c | 627 --
drivers/gpu/drm/radeon/sid.h| 72 +--
6 files changed, 328 insertions(+), 1422 deletions(-)
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[Bug 101029] notebook does not work when not booted using nomodeset AMD APU
https://bugs.freedesktop.org/show_bug.cgi?id=101029 --- Comment #14 from Michel Dänzer --- Looks like https://patchwork.freedesktop.org/patch/146519/ might help, or passing iommu=soft on the kernel command line might serve as a workaround. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/2] drm: replace drm_[cm]alloc* by kvmalloc alternatives
On Wed, May 17, 2017 at 11:03:50AM +0200, Michal Hocko wrote:
> On Wed 17-05-17 08:38:09, Chris Wilson wrote:
> > On Wed, May 17, 2017 at 08:55:08AM +0200, Michal Hocko wrote:
> > > From: Michal Hocko
> > >
> > > drm_[cm]alloc* has grown their own kvmalloc with vmalloc fallback
> > > implementations. MM has grown kvmalloc* helpers in the meantime. Let's
> > > use those because it a) reduces the code and b) MM has a better idea
> > > how to implement fallbacks (e.g. do not vmalloc before kmalloc is tried
> > > with __GFP_NORETRY).
> > >
> > > drm_calloc_large needs to get __GFP_ZERO explicitly but it is the same
> > > thing as kvmalloc_array in principle.
> > >
> > > Signed-off-by: Michal Hocko
> >
> > Just a little surprised that calloc_large users still exist.
> >
> > Reviewed-by: Chris Wilson
>
> Thanks!
>
> > One more feature request from mm, can we have the
> > if (size != 0 && n > SIZE_MAX / size)
> > check exported by itself.
>
> What do you exactly mean by exporting?
Just make available to others so that little things like choice between
SIZE_MAX and ULONG_MAX are consistent and actually reflect the right
limit (as dictated by kmalloc/kvmalloc/vmalloc...).
> Something like the following?
> I haven't compile tested it outside of mm with different config options.
> Sticking alloc_array_check into mm_types.h is kind of gross but I do not
> have a great idea where to put it. A new header doesn't seem nice.
> ---
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 7cb17c6b97de..f908b14ffc4c 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -534,7 +534,7 @@ static inline void *kvzalloc(size_t size, gfp_t flags)
>
> static inline void *kvmalloc_array(size_t n, size_t size, gfp_t flags)
> {
> - if (size != 0 && n > SIZE_MAX / size)
> + if (!alloc_array_check(n, size))
> return NULL;
>
> return kvmalloc(n * size, flags);
> diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
> index 45cdb27791a3..d7154b43a0d1 100644
> --- a/include/linux/mm_types.h
> +++ b/include/linux/mm_types.h
> @@ -601,4 +601,10 @@ typedef struct {
> unsigned long val;
> } swp_entry_t;
>
> +static inline bool alloc_array_check(size_t n, size_t size)
> +{
> + if (size != 0 && n > SIZE_MAX / size)
> + return false;
> + return true;
Just return size == 0 || n <= SIZE_MAX /size ?
Whether or not size being 0 makes for a sane user is another question.
The guideline is that size is the known constant from sizeof() or
whatever and n is the variable number to allocate.
But yes, that inline is what I want :)
-Chris
--
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[Bug 100510] [radeon] Heavy artifacts during hw accelerated playback of wmv files
https://bugs.freedesktop.org/show_bug.cgi?id=100510 Arthur Marsh changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|FIXED |--- --- Comment #10 from Arthur Marsh --- commit 8f12bbe6d94a51f3ae314c27cc7b9b315adfe383 Author: Christian König Date: Tue Apr 11 19:20:20 2017 +0200 drm/radeon: force the UVD DPB into VRAM as well Seems to be mandatory for WMV playback. Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=100510 breaks video playback for me with a VERDE card (DVD and some other formats), with the error: [75728.141010] [drm:radeon_uvd_cs_parse [radeon]] *ERROR* msg/fb buffer 14674000-1686F000 out of 256MB segment! [75728.141030] [drm:radeon_cs_ioctl [radeon]] *ERROR* Invalid command stream ! I'm happy to supply more specifics of my configuration. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[GIT PULL] etnaviv-fixes for 4.12-rc2
Hi Dave, just a single fix for a refcounting issue, introduced with the new explicit fencing support in 4.12. Regards, Lucas The following changes since commit 8b03d1ed2c43a2ba5ef3381322ee4515b97381bf: Merge branch 'linux-4.12' of git://github.com/skeggsb/linux into drm-next (2017-05-02 04:46:01 +1000) are available in the git repository at: https://git.pengutronix.de/git/lst/linux etnaviv/fixes for you to fetch changes up to 657314b7a5d16961e7e0ecdae4a59d28123e74c0: drm/etnaviv: don't put fence in case of submit failure (2017-05-05 17:12:34 +0200) Lucas Stach (1): drm/etnaviv: don't put fence in case of submit failure drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 1/6] drm: Deduplicate driver initialization message
On Fri, 30 Dec 2016, Daniel Vetter wrote:
> On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
>> Several DRM drivers print the same initialization message right after
>> drm_dev_register, so move that to common code. The exception is i915,
>> which uses its own register handle, so let it keep its own message.
>>
>> Notice that this was tested only with Exynos, but looks simple enough
>> for the other drivers.
>>
>> Signed-off-by: Gabriel Krisman Bertazi
>
> Makes sense, applied to drm-misc.
Makes sense for everything except i915:
https://bugs.freedesktop.org/show_bug.cgi?id=101025
BR,
Jani.
>
> Thanks, Daniel
>
>> ---
>> drivers/gpu/drm/armada/armada_drv.c | 6 --
>> drivers/gpu/drm/drm_drv.c | 7 +++
>> drivers/gpu/drm/drm_pci.c | 4
>> drivers/gpu/drm/drm_platform.c | 4
>> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 4
>> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 4
>> drivers/gpu/drm/tegra/drm.c | 4
>> drivers/gpu/drm/virtio/virtgpu_drm_bus.c| 4
>> 8 files changed, 7 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/armada/armada_drv.c
>> b/drivers/gpu/drm/armada/armada_drv.c
>> index 07086b427c22..63f42d001f33 100644
>> --- a/drivers/gpu/drm/armada/armada_drv.c
>> +++ b/drivers/gpu/drm/armada/armada_drv.c
>> @@ -203,12 +203,6 @@ static int armada_drm_bind(struct device *dev)
>> armada_drm_debugfs_init(priv->drm.primary);
>> #endif
>>
>> -DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> - armada_drm_driver.name, armada_drm_driver.major,
>> - armada_drm_driver.minor, armada_drm_driver.patchlevel,
>> - armada_drm_driver.date, dev_name(dev),
>> - priv->drm.primary->index);
>> -
>> return 0;
>>
>> err_poll:
>> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
>> index 4a7b3e98d586..d5aeba58c2ac 100644
>> --- a/drivers/gpu/drm/drm_drv.c
>> +++ b/drivers/gpu/drm/drm_drv.c
>> @@ -728,6 +728,7 @@ static void remove_compat_control_link(struct drm_device
>> *dev)
>> */
>> int drm_dev_register(struct drm_device *dev, unsigned long flags)
>> {
>> +struct drm_driver *driver = dev->driver;
>> int ret;
>>
>> mutex_lock(&drm_global_mutex);
>> @@ -758,6 +759,12 @@ int drm_dev_register(struct drm_device *dev, unsigned
>> long flags)
>> drm_modeset_register_all(dev);
>>
>> ret = 0;
>> +
>> +DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> + driver->name, driver->major, driver->minor,
>> + driver->patchlevel, driver->date, dev_name(dev->dev),
>> + dev->primary->index);
>> +
>> goto out_unlock;
>>
>> err_minors:
>> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
>> index 3ceea9cb9d3e..dc358f860aea 100644
>> --- a/drivers/gpu/drm/drm_pci.c
>> +++ b/drivers/gpu/drm/drm_pci.c
>> @@ -257,10 +257,6 @@ int drm_get_pci_dev(struct pci_dev *pdev, const struct
>> pci_device_id *ent,
>> if (ret)
>> goto err_agp;
>>
>> -DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> - driver->name, driver->major, driver->minor, driver->patchlevel,
>> - driver->date, pci_name(pdev), dev->primary->index);
>> -
>> /* No locking needed since shadow-attach is single-threaded since it may
>> * only be called from the per-driver module init hook. */
>> if (drm_core_check_feature(dev, DRIVER_LEGACY))
>> diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c
>> index 026269851ce9..7af3005a030c 100644
>> --- a/drivers/gpu/drm/drm_platform.c
>> +++ b/drivers/gpu/drm/drm_platform.c
>> @@ -57,10 +57,6 @@ static int drm_get_platform_dev(struct platform_device
>> *platdev,
>> if (ret)
>> goto err_free;
>>
>> -DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
>> - driver->name, driver->major, driver->minor, driver->patchlevel,
>> - driver->date, dev->primary->index);
>> -
>> return 0;
>>
>> err_free:
>> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> index 0b35da73c2b0..9a31711d5158 100644
>> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> @@ -415,10 +415,6 @@ static int fsl_dcu_drm_probe(struct platform_device
>> *pdev)
>> if (ret < 0)
>> goto unref;
>>
>> -DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
>> - driver->major, driver->minor, driver->patchlevel,
>> - driver->date, drm->primary->index);
>> -
>> return 0;
>>
>> unref:
>> diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
>> b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
>> index fa228b7b022c..7df0e8535e41 100644
>> --- a/driv
Re: [PATCH v3 1/3] drm: Plumb modifiers through plane init
On Tue, May 16, 2017 at 02:31:24PM -0700, Ben Widawsky wrote:
> This is the plumbing for supporting fb modifiers on planes. Modifiers
> have already been introduced to some extent, but this series will extend
> this to allow querying modifiers per plane. Based on this, the client to
> enable optimal modifications for framebuffers.
>
> This patch simply allows the DRM drivers to initialize their list of
> supported modifiers upon initializing the plane.
>
> v2: A minor addition from Daniel
>
> v3: Updated commit message
> s/INVALID/DRM_FORMAT_MOD_INVALID (Liviu)
> Remove some excess newlines (Liviu)
> Update comment for > 64 modifiers (Liviu)
>
> Cc: Liviu Dudau
> Reviewed-by: Daniel Stone (v2)
> Signed-off-by: Ben Widawsky
Minor nits, see below, but otherwise:
Reviewed-by: Liviu Dudau
Thanks,
Liviu
> ---
> drivers/gpu/drm/arc/arcpgu_crtc.c | 1 +
> drivers/gpu/drm/arm/hdlcd_crtc.c| 1 +
> drivers/gpu/drm/arm/malidp_planes.c | 2 +-
> drivers/gpu/drm/armada/armada_crtc.c| 1 +
> drivers/gpu/drm/armada/armada_overlay.c | 1 +
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 ++-
> drivers/gpu/drm/drm_modeset_helper.c| 1 +
> drivers/gpu/drm/drm_plane.c | 35
> -
> drivers/gpu/drm/drm_simple_kms_helper.c | 3 +++
> drivers/gpu/drm/exynos/exynos_drm_plane.c | 2 +-
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 2 +-
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 1 +
> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c| 5 +++-
> drivers/gpu/drm/i915/intel_sprite.c | 4 +--
> drivers/gpu/drm/imx/ipuv3-plane.c | 4 +--
> drivers/gpu/drm/mediatek/mtk_drm_plane.c| 2 +-
> drivers/gpu/drm/meson/meson_plane.c | 1 +
> drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c | 2 +-
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 4 +--
> drivers/gpu/drm/mxsfb/mxsfb_drv.c | 2 +-
> drivers/gpu/drm/nouveau/nv50_display.c | 5 ++--
> drivers/gpu/drm/omapdrm/omap_plane.c| 3 ++-
> drivers/gpu/drm/qxl/qxl_display.c | 2 +-
> drivers/gpu/drm/rcar-du/rcar_du_plane.c | 4 +--
> drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 4 +--
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 +--
> drivers/gpu/drm/sti/sti_cursor.c| 2 +-
> drivers/gpu/drm/sti/sti_gdp.c | 2 +-
> drivers/gpu/drm/sti/sti_hqvdp.c | 2 +-
> drivers/gpu/drm/sun4i/sun4i_layer.c | 2 +-
> drivers/gpu/drm/tegra/dc.c | 12 -
> drivers/gpu/drm/vc4/vc4_plane.c | 2 +-
> drivers/gpu/drm/virtio/virtgpu_plane.c | 2 +-
> drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 4 +--
> drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c| 4 +--
> drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c| 4 +--
> drivers/gpu/drm/zte/zx_plane.c | 2 +-
> include/drm/drm_plane.h | 20 +-
> include/drm/drm_simple_kms_helper.h | 1 +
> include/uapi/drm/drm_fourcc.h | 11
> 41 files changed, 126 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c
> b/drivers/gpu/drm/arc/arcpgu_crtc.c
> index ad9a95916f1f..cd8a24c7c67d 100644
> --- a/drivers/gpu/drm/arc/arcpgu_crtc.c
> +++ b/drivers/gpu/drm/arc/arcpgu_crtc.c
> @@ -218,6 +218,7 @@ static struct drm_plane *arc_pgu_plane_init(struct
> drm_device *drm)
>
> ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
> formats, ARRAY_SIZE(formats),
> +NULL,
> DRM_PLANE_TYPE_PRIMARY, NULL);
> if (ret)
> return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c
> b/drivers/gpu/drm/arm/hdlcd_crtc.c
> index 798a3cc480a2..0caa03ae8708 100644
> --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> @@ -303,6 +303,7 @@ static struct drm_plane *hdlcd_plane_init(struct
> drm_device *drm)
>
> ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
> formats, ARRAY_SIZE(formats),
> +NULL,
> DRM_PLANE_TYPE_PRIMARY, NULL);
> if (ret) {
> devm_kfree(drm->dev, plane);
> diff --git a/drivers/gpu/drm/arm/malidp_planes.c
> b/drivers/gpu/drm/arm/malidp_planes.c
> index 814fda23cead..b156610c68a5 100644
> --- a/drivers/gpu/drm/arm/malidp_planes.c
> +++ b/drivers/gpu/drm/arm/malidp_planes.c
> @@ -400,7 +400,7 @@ int malidp_de_planes_init(struct drm_device *drm)
> DRM_PLANE_TYPE_OVERLAY;
> re
[PATCH libdrm] xf86drm: fix compile error for declare i in for loop
error log:
xf86drm.c: In function 'parse_separate_sysfs_files':
xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed in
C99 mode
for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
^
xf86drm.c:3104:5: note: use option -std=c99 or -std=gnu99 to compile your code
make[4]: *** [libdrm_la-xf86drm.lo] Error 1
Signed-off-by: Qiang Yu
---
xf86drm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/xf86drm.c b/xf86drm.c
index 728ac78..dc028cc 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -3100,8 +3100,9 @@ static int parse_separate_sysfs_files(int maj, int min,
unsigned int data[ARRAY_SIZE(attrs)];
FILE *fp;
int ret;
+unsigned i;
-for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
+for (i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
snprintf(path, PATH_MAX, "/sys/dev/char/%d:%d/device/%s", maj, min,
attrs[i]);
fp = fopen(path, "r");
--
1.9.1
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Re: [PATCH 2/2] drm: drop drm_[cm]alloc* helpers
Hi Michal,
[auto build test ERROR on drm/drm-next]
[also build test ERROR on v4.12-rc1 next-20170517]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Michal-Hocko/drm-replace-drm_-cm-alloc-by-kvmalloc-alternatives/20170517-150333
base: git://people.freedesktop.org/~airlied/linux.git drm-next
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
drivers/gpu//drm/etnaviv/etnaviv_gem.c: In function
'etnaviv_gem_userptr_do_get_pages':
>> drivers/gpu//drm/etnaviv/etnaviv_gem.c:751:9: error: implicit declaration of
>> function 'kvmallo_array' [-Werror=implicit-function-declaration]
pvec = kvmallo_array(npages, sizeof(struct page *), GFP_KERNEL);
^
>> drivers/gpu//drm/etnaviv/etnaviv_gem.c:751:7: warning: assignment makes
>> pointer from integer without a cast [-Wint-conversion]
pvec = kvmallo_array(npages, sizeof(struct page *), GFP_KERNEL);
^
cc1: some warnings being treated as errors
vim +/kvmallo_array +751 drivers/gpu//drm/etnaviv/etnaviv_gem.c
745 {
746 int ret = 0, pinned, npages = etnaviv_obj->base.size >>
PAGE_SHIFT;
747 struct page **pvec;
748 uintptr_t ptr;
749 unsigned int flags = 0;
750
> 751 pvec = kvmallo_array(npages, sizeof(struct page *), GFP_KERNEL);
752 if (!pvec)
753 return ERR_PTR(-ENOMEM);
754
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
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Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob
On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
> On 17-05-03 17:08:27, Daniel Vetter wrote:
> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
> > > +struct drm_format_modifier_blob {
> > > +#define FORMAT_BLOB_CURRENT 1
> > > + /* Version of this blob format */
> > > + u32 version;
> > > +
> > > + /* Flags */
> > > + u32 flags;
> > > +
> > > + /* Number of fourcc formats supported */
> > > + u32 count_formats;
> > > +
> > > + /* Where in this blob the formats exist (in bytes) */
> > > + u32 formats_offset;
> > > +
> > > + /* Number of drm_format_modifiers */
> > > + u32 count_modifiers;
> > > +
> > > + /* Where in this blob the modifiers exist (in bytes) */
> > > + u32 modifiers_offset;
> > > +
> > > + /* u32 formats[] */
> > > + /* struct drm_format_modifier modifiers[] */
> > > +} __packed;
> >
> > The struct should be in the uapi header. Otherwise it won't show up in
> > libdrm headers when following the proper process.
> > -Daniel
> >
>
> I don't agree that blobs are ever really part of the API, but it doesn't hurt
> to
> move it... in other words, done.
Userspace writes them, the kernel reads them (or maybe even the other way
round). How exactly is a specific blob and its layout not part of uapi?
Can you explain your reasoning here pls?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [RFC v3 5/8] drm/msm: update cursors asynchronously through atomic
On Wed, May 17, 2017 at 10:56:25AM +0530, Archit Taneja wrote:
> Hi,
>
> On 05/16/2017 08:14 PM, Archit Taneja wrote:
> >
> >
> > On 5/13/2017 12:40 AM, Gustavo Padovan wrote:
> > > From: Gustavo Padovan
> > >
> > > Add support to async updates of cursors by using the new atomic
> > > interface for that. Basically what this commit does is do what
> > > mdp5_update_cursor_plane_legacy() did but through atomic.
> >
> > Works well on DB820c (which has a APQ8096 SoC).
> >
> > Tested-by: Archit Taneja
>
> Actually, after some more thorough testing, I found one issue, mentioned
> below.
>
> >
> > >
> > > v3: move size checks back to drivers (Ville Syrjälä)
> > >
> > > v2: move fb setting to core and use new state (Eric Anholt)
> > >
> > > Cc: Rob Clark
> > > Signed-off-by: Gustavo Padovan
> > > ---
> > > drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 151
> > > +-
> > > 1 file changed, 63 insertions(+), 88 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
> > > b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
> > > index a38c5fe..07106c1 100644
> > > --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
> > > +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
> > > @@ -33,15 +33,6 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
> > > struct drm_crtc *crtc, struct drm_framebuffer *fb,
> > > struct drm_rect *src, struct drm_rect *dest);
> > > -static int mdp5_update_cursor_plane_legacy(struct drm_plane *plane,
> > > -struct drm_crtc *crtc,
> > > -struct drm_framebuffer *fb,
> > > -int crtc_x, int crtc_y,
> > > -unsigned int crtc_w, unsigned int crtc_h,
> > > -uint32_t src_x, uint32_t src_y,
> > > -uint32_t src_w, uint32_t src_h,
> > > -struct drm_modeset_acquire_ctx *ctx);
> > > -
> > > static struct mdp5_kms *get_kms(struct drm_plane *plane)
> > > {
> > > struct msm_drm_private *priv = plane->dev->dev_private;
> > > @@ -257,7 +248,7 @@ static const struct drm_plane_funcs mdp5_plane_funcs
> > > = {
> > > };
> > > static const struct drm_plane_funcs mdp5_cursor_plane_funcs = {
> > > -.update_plane = mdp5_update_cursor_plane_legacy,
> > > +.update_plane = drm_atomic_helper_update_plane,
> > > .disable_plane = drm_atomic_helper_disable_plane,
> > > .destroy = mdp5_plane_destroy,
> > > .set_property = drm_atomic_helper_plane_set_property,
> > > @@ -484,11 +475,73 @@ static void mdp5_plane_atomic_update(struct
> > > drm_plane *plane,
> > > }
> > > }
> > > +static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
> > > + struct drm_plane_state *state)
> > > +{
> > > +struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
> > > +struct drm_crtc_state *crtc_state;
> > > +
> > > +crtc_state = drm_atomic_get_existing_crtc_state(state->state,
> > > +state->crtc);
>
> I see a kernel splat here (a NULL pointer dereference). The async_check
> function assumes that there is always going to be a plane_state->crtc
> available. This doesn't seem to be the case at least in the
> drm_atomic_helper_disable_plane() path. Moving the check to set
> legacy_cursor_update after calling __drm_atomic_helper_disable_plane()
> seems to fix the issue. Do you think it's a legit fix?
Yes, plane_state->crtc == NULL is what happens when disabling a plane. I
guess simplest would be to just not handle this for the async cursor
helpers.
I thought we've had tons of igts to test this ...
> One more point w.r.t msm driver is that we don't use the default
> drm_atomic_helper_commit() for our atomic_commit op. So I had to
> call drm_atomic_helper_async_commit() from our atomic_commit
> implementation
> (i.e, in msm_atomic_commit in drivers/gpu/drm/msm/msm_atomic.c)
Would be great to fix that - msm predates the nonblocking support in the
commit helper, but since this is fixed there's no reason anymore for
driver-private commit functions. Or at least there shouldn't be, for
almost all drivers. You can stuff all your hw commit logic into
atomic_commit_tail.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 1/6] drm: Deduplicate driver initialization message
On Wed, May 17, 2017 at 01:06:46PM +0300, Jani Nikula wrote:
> On Fri, 30 Dec 2016, Daniel Vetter wrote:
> > On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
> >> Several DRM drivers print the same initialization message right after
> >> drm_dev_register, so move that to common code. The exception is i915,
> >> which uses its own register handle, so let it keep its own message.
> >>
> >> Notice that this was tested only with Exynos, but looks simple enough
> >> for the other drivers.
> >>
> >> Signed-off-by: Gabriel Krisman Bertazi
> >
> > Makes sense, applied to drm-misc.
>
> Makes sense for everything except i915:
>
> https://bugs.freedesktop.org/show_bug.cgi?id=101025
Not sure how this happened, the i915 patch landed a few months earlier:
commit bc5ca47c0af4f949ba889e666b7da65569e36093
Author: Chris Wilson
Date: Thu Aug 25 08:23:14 2016 +0100
drm/i915: Restore lost "Initialized i915" welcome message
Gabriel, can you pls follow up with a patch to address this?
Thanks, Daniel
>
> BR,
> Jani.
>
>
> >
> > Thanks, Daniel
> >
> >> ---
> >> drivers/gpu/drm/armada/armada_drv.c | 6 --
> >> drivers/gpu/drm/drm_drv.c | 7 +++
> >> drivers/gpu/drm/drm_pci.c | 4
> >> drivers/gpu/drm/drm_platform.c | 4
> >> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 4
> >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 4
> >> drivers/gpu/drm/tegra/drm.c | 4
> >> drivers/gpu/drm/virtio/virtgpu_drm_bus.c| 4
> >> 8 files changed, 7 insertions(+), 30 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/armada/armada_drv.c
> >> b/drivers/gpu/drm/armada/armada_drv.c
> >> index 07086b427c22..63f42d001f33 100644
> >> --- a/drivers/gpu/drm/armada/armada_drv.c
> >> +++ b/drivers/gpu/drm/armada/armada_drv.c
> >> @@ -203,12 +203,6 @@ static int armada_drm_bind(struct device *dev)
> >>armada_drm_debugfs_init(priv->drm.primary);
> >> #endif
> >>
> >> - DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
> >> - armada_drm_driver.name, armada_drm_driver.major,
> >> - armada_drm_driver.minor, armada_drm_driver.patchlevel,
> >> - armada_drm_driver.date, dev_name(dev),
> >> - priv->drm.primary->index);
> >> -
> >>return 0;
> >>
> >> err_poll:
> >> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
> >> index 4a7b3e98d586..d5aeba58c2ac 100644
> >> --- a/drivers/gpu/drm/drm_drv.c
> >> +++ b/drivers/gpu/drm/drm_drv.c
> >> @@ -728,6 +728,7 @@ static void remove_compat_control_link(struct
> >> drm_device *dev)
> >> */
> >> int drm_dev_register(struct drm_device *dev, unsigned long flags)
> >> {
> >> + struct drm_driver *driver = dev->driver;
> >>int ret;
> >>
> >>mutex_lock(&drm_global_mutex);
> >> @@ -758,6 +759,12 @@ int drm_dev_register(struct drm_device *dev, unsigned
> >> long flags)
> >>drm_modeset_register_all(dev);
> >>
> >>ret = 0;
> >> +
> >> + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
> >> + driver->name, driver->major, driver->minor,
> >> + driver->patchlevel, driver->date, dev_name(dev->dev),
> >> + dev->primary->index);
> >> +
> >>goto out_unlock;
> >>
> >> err_minors:
> >> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
> >> index 3ceea9cb9d3e..dc358f860aea 100644
> >> --- a/drivers/gpu/drm/drm_pci.c
> >> +++ b/drivers/gpu/drm/drm_pci.c
> >> @@ -257,10 +257,6 @@ int drm_get_pci_dev(struct pci_dev *pdev, const
> >> struct pci_device_id *ent,
> >>if (ret)
> >>goto err_agp;
> >>
> >> - DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
> >> - driver->name, driver->major, driver->minor, driver->patchlevel,
> >> - driver->date, pci_name(pdev), dev->primary->index);
> >> -
> >>/* No locking needed since shadow-attach is single-threaded since it may
> >> * only be called from the per-driver module init hook. */
> >>if (drm_core_check_feature(dev, DRIVER_LEGACY))
> >> diff --git a/drivers/gpu/drm/drm_platform.c
> >> b/drivers/gpu/drm/drm_platform.c
> >> index 026269851ce9..7af3005a030c 100644
> >> --- a/drivers/gpu/drm/drm_platform.c
> >> +++ b/drivers/gpu/drm/drm_platform.c
> >> @@ -57,10 +57,6 @@ static int drm_get_platform_dev(struct platform_device
> >> *platdev,
> >>if (ret)
> >>goto err_free;
> >>
> >> - DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
> >> - driver->name, driver->major, driver->minor, driver->patchlevel,
> >> - driver->date, dev->primary->index);
> >> -
> >>return 0;
> >>
> >> err_free:
> >> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> >> b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> >> index 0b35da73c2b0..9a31711d5158 100644
> >> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> >> +++ b/drivers/gpu/drm/fsl-dcu/fsl
Re: [PATCH 1/6] drm: Deduplicate driver initialization message
On Wed, 17 May 2017, Daniel Vetter wrote:
> On Wed, May 17, 2017 at 01:06:46PM +0300, Jani Nikula wrote:
>> On Fri, 30 Dec 2016, Daniel Vetter wrote:
>> > On Wed, Dec 28, 2016 at 12:32:11PM -0200, Gabriel Krisman Bertazi wrote:
>> >> Several DRM drivers print the same initialization message right after
>> >> drm_dev_register, so move that to common code. The exception is i915,
>> >> which uses its own register handle, so let it keep its own message.
>> >>
>> >> Notice that this was tested only with Exynos, but looks simple enough
>> >> for the other drivers.
>> >>
>> >> Signed-off-by: Gabriel Krisman Bertazi
>> >
>> > Makes sense, applied to drm-misc.
>>
>> Makes sense for everything except i915:
>>
>> https://bugs.freedesktop.org/show_bug.cgi?id=101025
>
> Not sure how this happened, the i915 patch landed a few months earlier:
>
> commit bc5ca47c0af4f949ba889e666b7da65569e36093
> Author: Chris Wilson
> Date: Thu Aug 25 08:23:14 2016 +0100
>
> drm/i915: Restore lost "Initialized i915" welcome message
>
> Gabriel, can you pls follow up with a patch to address this?
Isn't the fix then to revert that? Since the message now comes from
core?
BR,
Jani.
>
> Thanks, Daniel
>
>>
>> BR,
>> Jani.
>>
>>
>> >
>> > Thanks, Daniel
>> >
>> >> ---
>> >> drivers/gpu/drm/armada/armada_drv.c | 6 --
>> >> drivers/gpu/drm/drm_drv.c | 7 +++
>> >> drivers/gpu/drm/drm_pci.c | 4
>> >> drivers/gpu/drm/drm_platform.c | 4
>> >> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 4
>> >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 4
>> >> drivers/gpu/drm/tegra/drm.c | 4
>> >> drivers/gpu/drm/virtio/virtgpu_drm_bus.c| 4
>> >> 8 files changed, 7 insertions(+), 30 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/armada/armada_drv.c
>> >> b/drivers/gpu/drm/armada/armada_drv.c
>> >> index 07086b427c22..63f42d001f33 100644
>> >> --- a/drivers/gpu/drm/armada/armada_drv.c
>> >> +++ b/drivers/gpu/drm/armada/armada_drv.c
>> >> @@ -203,12 +203,6 @@ static int armada_drm_bind(struct device *dev)
>> >> armada_drm_debugfs_init(priv->drm.primary);
>> >> #endif
>> >>
>> >> - DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> >> - armada_drm_driver.name, armada_drm_driver.major,
>> >> - armada_drm_driver.minor, armada_drm_driver.patchlevel,
>> >> - armada_drm_driver.date, dev_name(dev),
>> >> - priv->drm.primary->index);
>> >> -
>> >> return 0;
>> >>
>> >> err_poll:
>> >> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
>> >> index 4a7b3e98d586..d5aeba58c2ac 100644
>> >> --- a/drivers/gpu/drm/drm_drv.c
>> >> +++ b/drivers/gpu/drm/drm_drv.c
>> >> @@ -728,6 +728,7 @@ static void remove_compat_control_link(struct
>> >> drm_device *dev)
>> >> */
>> >> int drm_dev_register(struct drm_device *dev, unsigned long flags)
>> >> {
>> >> + struct drm_driver *driver = dev->driver;
>> >> int ret;
>> >>
>> >> mutex_lock(&drm_global_mutex);
>> >> @@ -758,6 +759,12 @@ int drm_dev_register(struct drm_device *dev,
>> >> unsigned long flags)
>> >> drm_modeset_register_all(dev);
>> >>
>> >> ret = 0;
>> >> +
>> >> + DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> >> + driver->name, driver->major, driver->minor,
>> >> + driver->patchlevel, driver->date, dev_name(dev->dev),
>> >> + dev->primary->index);
>> >> +
>> >> goto out_unlock;
>> >>
>> >> err_minors:
>> >> diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
>> >> index 3ceea9cb9d3e..dc358f860aea 100644
>> >> --- a/drivers/gpu/drm/drm_pci.c
>> >> +++ b/drivers/gpu/drm/drm_pci.c
>> >> @@ -257,10 +257,6 @@ int drm_get_pci_dev(struct pci_dev *pdev, const
>> >> struct pci_device_id *ent,
>> >> if (ret)
>> >> goto err_agp;
>> >>
>> >> - DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
>> >> - driver->name, driver->major, driver->minor, driver->patchlevel,
>> >> - driver->date, pci_name(pdev), dev->primary->index);
>> >> -
>> >> /* No locking needed since shadow-attach is single-threaded since it may
>> >>* only be called from the per-driver module init hook. */
>> >> if (drm_core_check_feature(dev, DRIVER_LEGACY))
>> >> diff --git a/drivers/gpu/drm/drm_platform.c
>> >> b/drivers/gpu/drm/drm_platform.c
>> >> index 026269851ce9..7af3005a030c 100644
>> >> --- a/drivers/gpu/drm/drm_platform.c
>> >> +++ b/drivers/gpu/drm/drm_platform.c
>> >> @@ -57,10 +57,6 @@ static int drm_get_platform_dev(struct platform_device
>> >> *platdev,
>> >> if (ret)
>> >> goto err_free;
>> >>
>> >> - DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
>> >> - driver->name, driver->major, driver->minor, driver->patchlevel,
>> >> - driver->date, dev->primary->index);
>> >> -
>> >> return 0;
>> >>
>> >> err_free:
>> >> diff -
Re: [PATCH v2 15/29] drm/vc4: fix include notation and remove -Iinclude/drm flag
On Mon, Apr 24, 2017 at 01:50:33PM +0900, Masahiro Yamada wrote:
> Include instead of relative path from include/drm, then
> remove the -Iinclude/drm compiler flag.
>
> While we are here, use <...> instead of "..." for include/linux/*.h
> headers too.
>
> Signed-off-by: Masahiro Yamada
This one doesn't apply anymore cleanly. Can you pls rebase onto latest
linux-next? I'm going through the remaining patches, up to this all merged
to drm-misc-next.
Thanks, Daniel
> ---
>
> Changes in v2: None
>
> drivers/gpu/drm/vc4/Makefile| 2 --
> drivers/gpu/drm/vc4/vc4_crtc.c | 14 +++---
> drivers/gpu/drm/vc4/vc4_dpi.c | 16
> drivers/gpu/drm/vc4/vc4_drv.c | 2 +-
> drivers/gpu/drm/vc4/vc4_drv.h | 5 ++---
> drivers/gpu/drm/vc4/vc4_dsi.c | 28 ++--
> drivers/gpu/drm/vc4/vc4_hdmi.c | 20 ++--
> drivers/gpu/drm/vc4/vc4_hvs.c | 2 +-
> drivers/gpu/drm/vc4/vc4_kms.c | 12 ++--
> drivers/gpu/drm/vc4/vc4_plane.c | 9 +
> drivers/gpu/drm/vc4/vc4_v3d.c | 4 ++--
> 11 files changed, 56 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile
> index 61f45d1..f0efc7eb 100644
> --- a/drivers/gpu/drm/vc4/Makefile
> +++ b/drivers/gpu/drm/vc4/Makefile
> @@ -1,5 +1,3 @@
> -ccflags-y := -Iinclude/drm
> -
> # Please keep these build lists sorted!
>
> # core driver code
> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
> index d86c8cc..34d2e8a 100644
> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
> @@ -32,13 +32,13 @@
> * ones that set the clock.
> */
>
> -#include "drm_atomic.h"
> -#include "drm_atomic_helper.h"
> -#include "drm_crtc_helper.h"
> -#include "linux/clk.h"
> -#include "drm_fb_cma_helper.h"
> -#include "linux/component.h"
> -#include "linux/of_device.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> #include "vc4_drv.h"
> #include "vc4_regs.h"
>
> diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c
> index c6d7039..39d6808 100644
> --- a/drivers/gpu/drm/vc4/vc4_dpi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dpi.c
> @@ -22,14 +22,14 @@
> * ALT2 function.
> */
>
> -#include "drm_atomic_helper.h"
> -#include "drm_crtc_helper.h"
> -#include "drm_edid.h"
> -#include "drm_panel.h"
> -#include "linux/clk.h"
> -#include "linux/component.h"
> -#include "linux/of_graph.h"
> -#include "linux/of_platform.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> #include "vc4_drv.h"
> #include "vc4_regs.h"
>
> diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c
> index 61e674b..2037a5f 100644
> --- a/drivers/gpu/drm/vc4/vc4_drv.c
> +++ b/drivers/gpu/drm/vc4/vc4_drv.c
> @@ -31,7 +31,7 @@
> #include
> #include
> #include
> -#include "drm_fb_cma_helper.h"
> +#include
> #include
>
> #include "uapi/drm/vc4_drm.h"
> diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
> index dffce629..ebfef52 100644
> --- a/drivers/gpu/drm/vc4/vc4_drv.h
> +++ b/drivers/gpu/drm/vc4/vc4_drv.h
> @@ -6,10 +6,9 @@
> * published by the Free Software Foundation.
> */
>
> -#include "drmP.h"
> -#include "drm_gem_cma_helper.h"
> -
> +#include
> #include
> +#include
>
> struct vc4_dev {
> struct drm_device *dev;
> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
> index 160f981..d18c9b1 100644
> --- a/drivers/gpu/drm/vc4/vc4_dsi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
> @@ -29,20 +29,20 @@
> * hopefully present.
> */
>
> -#include "drm_atomic_helper.h"
> -#include "drm_crtc_helper.h"
> -#include "drm_edid.h"
> -#include "drm_mipi_dsi.h"
> -#include "drm_panel.h"
> -#include "linux/clk.h"
> -#include "linux/clk-provider.h"
> -#include "linux/completion.h"
> -#include "linux/component.h"
> -#include "linux/dmaengine.h"
> -#include "linux/i2c.h"
> -#include "linux/of_address.h"
> -#include "linux/of_platform.h"
> -#include "linux/pm_runtime.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> #include "vc4_drv.h"
> #include "vc4_regs.h"
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index e9cbe26..c91591c 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -42,16 +42,16 @@
> * encoder block has CEC support.
> */
>
> -#include "drm_atomic_helper.h"
> -#include "drm_crtc_helper.h"
> -#include "drm_edid.h"
> -#include "linux/clk.h"
> -#include "linux/component.h"
> -#include "linux/i2c.h"
> -#include "linux/of_address.h"
> -#include "linux/of_gpio.h"
> -#include "linux/of_platform.h"
> -#include "linux/rational.h"
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#incl
[Bug 101029] notebook does not work when not booted using nomodeset AMD APU
https://bugs.freedesktop.org/show_bug.cgi?id=101029 --- Comment #15 from Craig --- where do i find the amd_iommu.c in ubuntu 17.04 so that I can patch it? or is there a different method? I was considering using this syntax: patch -p[num] < patchfile patch [options] originalfile patchfile thanks very much -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 101029] notebook does not work when not booted using nomodeset AMD APU
https://bugs.freedesktop.org/show_bug.cgi?id=101029 --- Comment #16 from Craig --- (In reply to Craig from comment #15) > where do i find the amd_iommu.c in ubuntu 17.04 so that I can patch it? or > is there a different method? I was considering using this syntax: patch > -p[num] < patchfile > patch [options] originalfile patchfile > thanks very much please disregard this i believe i found a solution. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 100577] DC + TearFree display lock
https://bugs.freedesktop.org/show_bug.cgi?id=100577 --- Comment #7 from Harry Wentland --- This might've been fixed by Mario's patches plus Andrey's scanline change d58f8724e636 Mario Kleiner drm/amd/display: Prevent premature pageflip when comitting in vblank. (v3) 8494f61e14ff Mario Kleiner drm/amd/display: Fix race between vblank irq and pageflip irq. (v2) -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
Hi Qiang Yu,
On 17 May 2017 at 10:26, Qiang Yu wrote:
> error log:
> xf86drm.c: In function 'parse_separate_sysfs_files':
> xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed in
> C99 mode
> for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
> ^
> xf86drm.c:3104:5: note: use option -std=c99 or -std=gnu99 to compile your code
> make[4]: *** [libdrm_la-xf86drm.lo] Error 1
>
configure should error out if the compiler does not support C99. Are
you explicitly patching that out?
Why can't we use a C99 in 2017 - gcc and clang has supported it for 10+ years.
Thanks
Emil
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
Hi Emil,
I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure pass
but
fail when compile.
I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
configure
script add it into CC variable. When just use "make", it's OK, but my build
script uses
"make CC=gcc".
If you think current state is OK, I can change my build script for that.
Regards,
Qiang
From: Emil Velikov
Sent: Wednesday, May 17, 2017 9:17:53 PM
To: Yu, Qiang
Cc: ML dri-devel
Subject: Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
Hi Qiang Yu,
On 17 May 2017 at 10:26, Qiang Yu wrote:
> error log:
> xf86drm.c: In function 'parse_separate_sysfs_files':
> xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed in
> C99 mode
> for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++) {
> ^
> xf86drm.c:3104:5: note: use option -std=c99 or -std=gnu99 to compile your code
> make[4]: *** [libdrm_la-xf86drm.lo] Error 1
>
configure should error out if the compiler does not support C99. Are
you explicitly patching that out?
Why can't we use a C99 in 2017 - gcc and clang has supported it for 10+ years.
Thanks
Emil
___
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 100437] IO_PAGE_FAULT is spammed in dmesg
https://bugs.freedesktop.org/show_bug.cgi?id=100437 --- Comment #7 from Corbin --- Same error as well. System Specs : Gentoo Linux x86_64, Kernel 4.9.x AMDGPU v1.2 Driver AMD 990FX Chipset AMD FX-9590 CPU AMD RX480 Video Card AMDGPU Firmware blobs compiled into the kernel. GART IOMMU support not included in the kernel / modules. errors copied from '/var/log/dmesg' : [0.987710] pci :01:00.0: Video device with shadowed ROM at [mem 0x000c-0x000d] [0.988027] PCI: CLS 64 bytes, default 64 [0.988362] iommu: Adding device :00:00.0 to group 0 [0.988530] iommu: Adding device :00:02.0 to group 1 [0.988689] iommu: Adding device :00:0a.0 to group 2 [0.988872] iommu: Adding device :00:0d.0 to group 3 [0.989029] iommu: Adding device :00:11.0 to group 4 [0.989194] iommu: Adding device :00:12.0 to group 5 [0.989318] iommu: Adding device :00:12.2 to group 5 [0.989484] iommu: Adding device :00:13.0 to group 6 [0.989615] iommu: Adding device :00:13.2 to group 6 [0.989780] iommu: Adding device :00:14.0 to group 7 [0.989943] iommu: Adding device :00:14.1 to group 8 [0.990128] iommu: Adding device :00:14.3 to group 9 [0.990292] iommu: Adding device :00:14.4 to group 10 [0.990458] iommu: Adding device :00:14.5 to group 11 [0.990637] iommu: Adding device :00:15.0 to group 12 [0.990763] iommu: Adding device :00:15.1 to group 12 [0.990935] iommu: Adding device :00:16.0 to group 13 [0.991058] iommu: Adding device :00:16.2 to group 13 [0.991252] iommu: Adding device :01:00.0 to group 14 [0.991387] iommu: Adding device :01:00.1 to group 14 [0.991560] iommu: Adding device :02:00.0 to group 15 [0.991742] iommu: Adding device :03:00.0 to group 16 [0.991863] iommu: Adding device :06:00.0 to group 12 [0.991982] iommu: Adding device :07:04.0 to group 12 [1.063849] AMD-Vi: Found IOMMU at :00:00.2 cap 0x40 [1.063962] AMD-Vi: Interrupt remapping enabled [1.064145] AMD-Vi: Lazy IO/TLB flushing enabled [1.065331] perf: AMD NB counters detected [1.065622] LVT offset 0 assigned for vector 0x400 [1.065836] perf: AMD IBS detected (0x00ff) [7.337130] [drm] amdgpu kernel modesetting enabled. [7.337326] [drm] initializing kernel modesetting (POLARIS10 0x1002:0x67DF 0x1682:0x9480 0xC7). [7.337334] [drm] register mmio base: 0xFEA0 [7.337334] [drm] register mmio size: 262144 [7.337336] [drm] doorbell mmio base: 0xD000 [7.337336] [drm] doorbell mmio size: 2097152 [7.337341] [drm] probing gen 2 caps for device 1002:5a16 = 31cd02/0 [7.337342] [drm] probing mlw for device 1002:5a16 = 31cd02 [7.337348] [drm] UVD is enabled in VM mode [7.337348] [drm] VCE enabled in VM mode [7.350857] ATOM BIOS: D00901 [7.350863] [drm] GPU post is not needed [7.351266] [TTM] Zone kernel: Available graphics memory: 16464010 kiB [7.351266] [TTM] Zone dma32: Available graphics memory: 2097152 kiB [7.351266] [TTM] Initializing pool allocator [7.351270] [TTM] Initializing DMA pool allocator [7.351281] amdgpu :01:00.0: VRAM: 8192M 0x - 0x0001 (8192M used) [7.351283] amdgpu :01:00.0: GTT: 16078M 0x0002 - 0x0005ECE227FF [7.351285] [drm] Detected VRAM RAM=8192M, BAR=256M [7.351285] [drm] RAM width 256bits GDDR5 [7.351292] [drm] amdgpu: 8192M of VRAM memory ready [7.351293] [drm] amdgpu: 16078M of GTT memory ready. [7.351297] [drm] GART: num cpu pages 4116002, num gpu pages 4116002 [7.352437] AMD-Vi: Event logged [ [7.352438] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f40010 flags=0x0010] [7.352438] AMD-Vi: Event logged [ [7.352439] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f400101400 flags=0x0010] [7.352440] AMD-Vi: Event logged [ [7.352440] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f400100040 flags=0x0010] [7.352440] AMD-Vi: Event logged [ [7.352441] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f400100080 flags=0x0010] [7.352441] AMD-Vi: Event logged [ [7.352442] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f400100240 flags=0x0010] [7.352442] AMD-Vi: Event logged [ [7.352443] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f400100280 flags=0x0010] [7.352443] AMD-Vi: Event logged [ [7.352444] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f4001000c0 flags=0x0010] ( the errors just continue, skipped in this posting ) [7.352866] AMD-Vi: Event logged [ [7.352867] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f40010ddc0 flags=0x0010] [7.352867] AMD-Vi: Event logged [ [7.352868] IO_PAGE_FAULT device=01:00.0 domain=0x000f address=0x00f40010df80 flags=0x0010] [7.352868] AMD-Vi: Event
[PATCH 0/4] drm/dp: device identification and quirks
New version of [1] with DPCD OUI etc. reading moved from i915 to DP helpers, and the quirks based on that. Helps improve the documentation that Daniel longed for. BR, Jani. [1] 20170511095721.7392-1-jani.nikula@intel.com">http://mid.mail-archive.com/20170511095721.7392-1-jani.nikula@intel.com Jani Nikula (4): drm/dp: add helper for reading DP sink/branch device desc from DPCD drm/i915: use drm DP helper to read DPCD desc drm/dp: start a DPCD based DP sink/branch device quirk database drm/i915: Detect USB-C specific dongles before reducing M and N drivers/gpu/drm/drm_dp_helper.c | 83 drivers/gpu/drm/i915/i915_drv.h | 3 +- drivers/gpu/drm/i915/intel_display.c | 22 ++ drivers/gpu/drm/i915/intel_dp.c | 45 +-- drivers/gpu/drm/i915/intel_dp_mst.c | 5 ++- drivers/gpu/drm/i915/intel_drv.h | 5 +-- drivers/gpu/drm/i915/intel_lspcon.c | 2 +- include/drm/drm_dp_helper.h | 51 ++ 8 files changed, 166 insertions(+), 50 deletions(-) -- 2.11.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/4] drm/dp: add helper for reading DP sink/branch device desc from DPCD
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 35 +++
include/drm/drm_dp_helper.h | 19 +++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 3e5f52110ea1..52e0ca9a5bb1 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1208,3 +1208,38 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux)
return 0;
}
EXPORT_SYMBOL(drm_dp_stop_crc);
+
+/**
+ * drm_dp_read_desc - read sink/branch descriptor from DPCD
+ * @aux: DisplayPort AUX channel
+ * @desc: Device decriptor to fill from DPCD
+ * @is_branch: true for branch devices, false for sink devices
+ *
+ * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
+ * identification.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
+bool is_branch)
+{
+ struct drm_dp_dpcd_ident *ident = &desc->ident;
+ unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
+ int ret, dev_id_len;
+
+ ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
+ if (ret < 0)
+ return ret;
+
+ dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
+
+ DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
+ is_branch ? "branch" : "sink",
+ (int)sizeof(ident->oui), ident->oui,
+ dev_id_len, ident->device_id,
+ ident->hw_rev >> 4, ident->hw_rev & 0xf,
+ ident->sw_major_rev, ident->sw_minor_rev);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_desc);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index f7007e544f29..aee5b96b51d7 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1079,4 +1079,23 @@ void drm_dp_aux_unregister(struct drm_dp_aux *aux);
int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
int drm_dp_stop_crc(struct drm_dp_aux *aux);
+struct drm_dp_dpcd_ident {
+ u8 oui[3];
+ u8 device_id[6];
+ u8 hw_rev;
+ u8 sw_major_rev;
+ u8 sw_minor_rev;
+} __packed;
+
+/**
+ * struct drm_dp_desc - DP branch/sink device descriptor
+ * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
+ */
+struct drm_dp_desc {
+ struct drm_dp_dpcd_ident ident;
+};
+
+int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
+bool is_branch);
+
#endif /* _DRM_DP_HELPER_H_ */
--
2.11.0
___
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/4] drm/i915: use drm DP helper to read DPCD desc
Switch to using the common DP helpers instead of using our own.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dp.c | 37 -
drivers/gpu/drm/i915/intel_drv.h| 5 +
drivers/gpu/drm/i915/intel_lspcon.c | 2 +-
3 files changed, 6 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4a6feb6a69bd..2a5f385e8f44 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1548,37 +1548,6 @@ static void intel_dp_print_rates(struct intel_dp
*intel_dp)
DRM_DEBUG_KMS("common rates: %s\n", str);
}
-bool
-__intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc)
-{
- u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI :
- DP_SINK_OUI;
-
- return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) ==
- sizeof(*desc);
-}
-
-bool intel_dp_read_desc(struct intel_dp *intel_dp)
-{
- struct intel_dp_desc *desc = &intel_dp->desc;
- bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] &
- DP_OUI_SUPPORT;
- int dev_id_len;
-
- if (!__intel_dp_read_desc(intel_dp, desc))
- return false;
-
- dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id));
- DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
- drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink",
- (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)",
- dev_id_len, desc->device_id,
- desc->hw_rev >> 4, desc->hw_rev & 0xf,
- desc->sw_major_rev, desc->sw_minor_rev);
-
- return true;
-}
-
int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
@@ -3662,7 +3631,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
if (!intel_dp_read_dpcd(intel_dp))
return false;
- intel_dp_read_desc(intel_dp);
+ drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+drm_dp_is_branch(intel_dp->dpcd));
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
@@ -4677,7 +4647,8 @@ intel_dp_long_pulse(struct intel_connector
*intel_connector)
intel_dp_print_rates(intel_dp);
- intel_dp_read_desc(intel_dp);
+ drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
+drm_dp_is_branch(intel_dp->dpcd));
intel_dp_configure_mst(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bd500977b3fc..61a9981343d5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -996,7 +996,7 @@ struct intel_dp {
/* Max rate for the current link */
int max_link_rate;
/* sink or branch descriptor */
- struct intel_dp_desc desc;
+ struct drm_dp_desc desc;
struct drm_dp_aux aux;
enum intel_display_power_domain aux_power_domain;
uint8_t train_set[4];
@@ -1571,9 +1571,6 @@ static inline unsigned int intel_dp_unused_lane_mask(int
lane_count)
}
bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
-bool __intel_dp_read_desc(struct intel_dp *intel_dp,
- struct intel_dp_desc *desc);
-bool intel_dp_read_desc(struct intel_dp *intel_dp);
int intel_dp_link_required(int pixel_clock, int bpp);
int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_lspcon.c
b/drivers/gpu/drm/i915/intel_lspcon.c
index 71cbe9c08932..5abef482eacf 100644
--- a/drivers/gpu/drm/i915/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/intel_lspcon.c
@@ -240,7 +240,7 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port)
return false;
}
- intel_dp_read_desc(dp);
+ drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd));
DRM_DEBUG_KMS("Success: LSPCON init\n");
return true;
--
2.11.0
___
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[PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on the DP device
identification. At least for now, we leave the workarounds for the
drivers to implement as they see fit.
For starters, add a branch device that can't handle full 24-bit main
link M and N attributes properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 52 +++--
include/drm/drm_dp_helper.h | 32 +
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 52e0ca9a5bb1..8c3797283c3b 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1209,6 +1209,51 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux)
}
EXPORT_SYMBOL(drm_dp_stop_crc);
+struct dpcd_quirk {
+ u8 oui[3];
+ bool is_branch;
+ u32 quirks;
+};
+
+#define OUI(first, second, third) { (first), (second), (third) }
+
+static const struct dpcd_quirk dpcd_quirk_list[] = {
+ /* Analogix 7737 needs reduced M and N at HBR2 link rates */
+ { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+};
+
+#undef OUI
+
+/*
+ * Get a bit mask of DPCD quirks for the sink/branch device identified by
+ * ident. The quirk data is shared but it's up to the drivers to act on the
+ * data.
+ *
+ * For now, only the OUI (first three bytes) is used, but this may be extended
+ * to device identification string and hardware/firmware revisions later.
+ */
+static u32
+drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
+{
+ const struct dpcd_quirk *quirk;
+ u32 quirks = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
+ quirk = &dpcd_quirk_list[i];
+
+ if (quirk->is_branch != is_branch)
+ continue;
+
+ if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui) != 0))
+ continue;
+
+ quirks |= quirk->quirks;
+ }
+
+ return quirks;
+}
+
/**
* drm_dp_read_desc - read sink/branch descriptor from DPCD
* @aux: DisplayPort AUX channel
@@ -1231,14 +1276,17 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
if (ret < 0)
return ret;
+ desc->quirks = drm_dp_get_quirks(ident, is_branch);
+
dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
- DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev
%d.%d\n",
+ DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d
quirks 0x%04x\n",
is_branch ? "branch" : "sink",
(int)sizeof(ident->oui), ident->oui,
dev_id_len, ident->device_id,
ident->hw_rev >> 4, ident->hw_rev & 0xf,
- ident->sw_major_rev, ident->sw_minor_rev);
+ ident->sw_major_rev, ident->sw_minor_rev,
+ desc->quirks);
return 0;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index aee5b96b51d7..717cb8496725 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1090,12 +1090,44 @@ struct drm_dp_dpcd_ident {
/**
* struct drm_dp_desc - DP branch/sink device descriptor
* @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
+ * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
*/
struct drm_dp_desc {
struct drm_dp_dpcd_ident ident;
+ u32 quirks;
};
int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
bool is_branch);
+/**
+ * enum drm_dp_quirk - Display Port sink/branch device specific quirks
+ *
+ * Display Port sink and branch devices in the wild have a variety of bugs, try
+ * to collect them here. The quirks are shared, but it's up to the drivers to
+ * implement workarounds for them.
+ */
+enum drm_dp_quirk {
+ /**
+* @DP_DPCD_QUIRK_LIMITED_M_N:
+*
+* The device requires main link attributes Mdiv and Ndiv to be limited
+* to 16 bits.
+*/
+ DP_DPCD_QUIRK_LIMITED_M_N,
+};
+
+/**
+ * drm_dp_has_quirk() - does the DP device have a specific quirk
+ * @desc: Device decriptor filled by drm_dp_read_desc()
+ * @quirk: Quirk to query for
+ *
+ * Return true if DP device identified by @desc has @quirk.
+ */
+static inline bool
+drm_dp_has_quirk(const struct drm_dp_desc *desc, enum
[PATCH 4/4] drm/i915: Detect USB-C specific dongles before reducing M and N
The Analogix 7737 DP to HDMI converter requires reduced M and N values
when to operate correctly at HBR2. Detect this IC by its OUI value of
0x0022B9 via the DPCD quirk list.
v2 by Jani: Rebased on the DP quirk database
v3 by Jani: Rebased on the reworked DP quirk database
Fixes: 9a86cda07af2 ("drm/i915/dp: reduce link M/N parameters")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93578
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100755
Cc: Jani Nikula
Cc: Dhinakaran Pandiyan
Cc: Ville Syrjälä
Signed-off-by: Clint Taylor
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_display.c | 22 ++
drivers/gpu/drm/i915/intel_dp.c | 8 ++--
drivers/gpu/drm/i915/intel_dp_mst.c | 5 -
4 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a6f20471b4cd..699e07362044 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -563,7 +563,8 @@ struct intel_link_m_n {
void intel_link_compute_m_n(int bpp, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n);
+ struct intel_link_m_n *m_n,
+ bool reduce_m_n);
/* Interface history:
*
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8217ed0e7132..ea4f116bd410 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6116,7 +6116,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc,
pipe_config->fdi_lanes = lane;
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
- link_bw, &pipe_config->fdi_m_n);
+ link_bw, &pipe_config->fdi_m_n, false);
ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
@@ -6292,7 +6292,8 @@ intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
}
static void compute_m_n(unsigned int m, unsigned int n,
- uint32_t *ret_m, uint32_t *ret_n)
+ uint32_t *ret_m, uint32_t *ret_n,
+ bool reduce_m_n)
{
/*
* Reduce M/N as much as possible without loss in precision. Several DP
@@ -6300,9 +6301,11 @@ static void compute_m_n(unsigned int m, unsigned int n,
* values. The passed in values are more likely to have the least
* significant bits zero than M after rounding below, so do this first.
*/
- while ((m & 1) == 0 && (n & 1) == 0) {
- m >>= 1;
- n >>= 1;
+ if (reduce_m_n) {
+ while ((m & 1) == 0 && (n & 1) == 0) {
+ m >>= 1;
+ n >>= 1;
+ }
}
*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
@@ -6313,16 +6316,19 @@ static void compute_m_n(unsigned int m, unsigned int n,
void
intel_link_compute_m_n(int bits_per_pixel, int nlanes,
int pixel_clock, int link_clock,
- struct intel_link_m_n *m_n)
+ struct intel_link_m_n *m_n,
+ bool reduce_m_n)
{
m_n->tu = 64;
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
- &m_n->gmch_m, &m_n->gmch_n);
+ &m_n->gmch_m, &m_n->gmch_n,
+ reduce_m_n);
compute_m_n(pixel_clock, link_clock,
- &m_n->link_m, &m_n->link_n);
+ &m_n->link_m, &m_n->link_n,
+ reduce_m_n);
}
static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 2a5f385e8f44..1ae9de5cf39c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1627,6 +1627,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int link_avail, link_clock;
int common_len;
uint8_t link_bw, rate_select;
+ bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
+ DP_DPCD_QUIRK_LIMITED_M_N);
common_len = intel_dp_common_len_rate_limit(intel_dp,
intel_dp->max_link_rate);
@@ -1759,7 +1761,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_link_compute_m_n(bpp, lane_count,
adjusted_mode->crtc_clock,
pipe_config->port_clock,
- &pipe_config->dp_m_n);
+ &pipe_config->dp_m_n,
+ reduce_m_n);
if (intel_connector->panel.down
Re: [PATCH v2] drm: Add DRM_ROTATE_ and DRM_REFLECT_ defines to UAPI
Hey Ville,
On 2017-05-16 12:20 PM, Ville Syrjälä wrote:
On Tue, May 16, 2017 at 11:55:00AM -0400, Robert Foss wrote:
Add DRM_ROTATE_ and DRM_REFLECT_ defines to the UAPI as a convenience.
I just noticed this line using the wrong define names.
Will fix in v3.
Ideally the DRM_ROTATE_ and DRM_REFLECT_ property ids are looked up
through the atomic API, but realizing that userspace is likely to take
shortcuts and assume that the enum values are what is sent over the
wire.
As a result these defines are provided purely as a convenience to
userspace applications.
Signed-off-by: Robert Foss
---
Changes since v1:
- Moved defines from drm.h to drm_mode.h
- Changed define prefix from DRM_ to DRM_MODE_PROP_
DRM_MODE_PROP_ would potentially cause confusion with the prop types.
DRM_MODE_ROTATE_ etc. could be acceptable I suppose.
- Updated uses of the defines to the new prefix
- Removed include from drm_rect.c
- Stopped using the BIT() macro
drivers/gpu/drm/drm_atomic.c | 2 +-
drivers/gpu/drm/drm_atomic_helper.c| 2 +-
drivers/gpu/drm/drm_blend.c| 43 +--
drivers/gpu/drm/drm_fb_helper.c| 4 +-
drivers/gpu/drm/drm_plane_helper.c | 2 +-
drivers/gpu/drm/drm_rect.c | 36
drivers/gpu/drm/nouveau/nv50_display.c | 2 +-
include/drm/drm_blend.h| 21 +-
include/uapi/drm/drm_mode.h| 76 ++
I'm pretty sure this won't even compile properly since it's missing all
but one driver.
I did check it using an arbitrary Kconfig, but I also missed a ton of uses.
Will fix in v3.
9 files changed, 124 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index f32506a7c1d6..ec1839b01d2a 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -769,7 +769,7 @@ int drm_atomic_plane_set_property(struct drm_plane *plane,
} else if (property == config->prop_src_h) {
state->src_h = val;
} else if (property == plane->rotation_property) {
- if (!is_power_of_2(val & DRM_ROTATE_MASK))
+ if (!is_power_of_2(val & DRM_MODE_PROP_ROTATE_MASK))
return -EINVAL;
state->rotation = val;
} else if (property == plane->zpos_property) {
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 8be9719284b0..37f461aa5e66 100644
--- a/drivers/gpu/drm/drm_atomic_helper.c
+++ b/drivers/gpu/drm/drm_atomic_helper.c
@@ -3220,7 +3220,7 @@ void drm_atomic_helper_plane_reset(struct drm_plane
*plane)
if (plane->state) {
plane->state->plane = plane;
- plane->state->rotation = DRM_ROTATE_0;
+ plane->state->rotation = DRM_MODE_PROP_ROTATE_0;
}
}
EXPORT_SYMBOL(drm_atomic_helper_plane_reset);
diff --git a/drivers/gpu/drm/drm_blend.c b/drivers/gpu/drm/drm_blend.c
index a0d0d6843288..044640a04d51 100644
--- a/drivers/gpu/drm/drm_blend.c
+++ b/drivers/gpu/drm/drm_blend.c
@@ -119,15 +119,15 @@
* drm_property_create_bitmask()) called "rotation" and has the following
* bitmask enumaration values:
*
- * DRM_ROTATE_0:
+ * DRM_MODE_PROP_ROTATE_0:
* "rotate-0"
- * DRM_ROTATE_90:
+ * DRM_MODE_PROP_ROTATE_90:
* "rotate-90"
- * DRM_ROTATE_180:
+ * DRM_MODE_PROP_ROTATE_180:
* "rotate-180"
- * DRM_ROTATE_270:
+ * DRM_MODE_PROP_ROTATE_270:
* "rotate-270"
- * DRM_REFLECT_X:
+ * DRM_MODE_PROP_REFLECT_X:
* "reflect-x"
* DRM_REFELCT_Y:
* "reflect-y"
@@ -142,17 +142,17 @@ int drm_plane_create_rotation_property(struct drm_plane
*plane,
unsigned int supported_rotations)
{
static const struct drm_prop_enum_list props[] = {
- { __builtin_ffs(DRM_ROTATE_0) - 1, "rotate-0" },
- { __builtin_ffs(DRM_ROTATE_90) - 1, "rotate-90" },
- { __builtin_ffs(DRM_ROTATE_180) - 1, "rotate-180" },
- { __builtin_ffs(DRM_ROTATE_270) - 1, "rotate-270" },
- { __builtin_ffs(DRM_REFLECT_X) - 1, "reflect-x" },
- { __builtin_ffs(DRM_REFLECT_Y) - 1, "reflect-y" },
+ { __builtin_ffs(DRM_MODE_PROP_ROTATE_0) - 1, "rotate-0" },
+ { __builtin_ffs(DRM_MODE_PROP_ROTATE_90) - 1, "rotate-90" },
+ { __builtin_ffs(DRM_MODE_PROP_ROTATE_180) - 1, "rotate-180" },
+ { __builtin_ffs(DRM_MODE_PROP_ROTATE_270) - 1, "rotate-270" },
+ { __builtin_ffs(DRM_MODE_PROP_REFLECT_X) - 1, "reflect-x" },
+ { __builtin_ffs(DRM_MODE_PROP_REFLECT_Y) - 1, "reflect-y" },
};
struct drm_property *prop;
- WARN_ON((supported_rotations & DRM_ROTATE_MASK) == 0);
- WARN_ON(!is_power_of_2(rotation & DRM_ROTATE_MASK));
+ WARN_ON((supported_rotations & DRM_MODE_PROP_ROTATE_MASK) == 0);
+ WARN_ON(!is_power_of_2(r
[Bug 100510] [radeon] Heavy artifacts during hw accelerated playback of wmv files
https://bugs.freedesktop.org/show_bug.cgi?id=100510 Michel Dänzer changed: What|Removed |Added Resolution|--- |FIXED Status|REOPENED|RESOLVED --- Comment #11 from Michel Dänzer --- Arthur, please file your own report. The commit in question did fix the problem reported here, so this is the correct status. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v5] drm/msm: gpu: Enable zap shader for A5XX
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can
only render to buffers that are marked as secure and inaccessible
to the kernel and user through a series of hardware protections. In
practice secure mode is used to draw things like a UI on a secure
video frame.
In order to switch out of secure mode the GPU executes a special
shader that clears out the GMEM and other sensitve registers and
then writes a register. Because the kernel can't be trusted the
shader binary is signed and verified and programmed by the
secure world. To do this we need to read the MDT header and the
segments from the firmware location and put them in memory and
present them for approval.
For targets without secure support there is an out: if the
secure world doesn't support secure then there are no hardware
protections and we can freely write the SECVID_TRUST register from
the CPU. We don't have 100% confidence that we can query the
secure capabilities at run time but we have enough calls that
need to go right to give us some confidence that we're at least doing
something useful.
Of course if we guess wrong you trigger a permissions violation
which usually ends up in a system crash but thats a problem
that shows up immediately.
[v2: use child device per Bjorn]
[v3: use generic MDT loader per Bjorn]
[v4: use managed dma functions and ifdefs for the MDT loader]
[v5: Add depends for QCOM_MDT_LOADER]
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig| 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 180 -
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 2 +
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.h| 1 +
5 files changed, 183 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 5b8e23d..b29bd30 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -5,6 +5,7 @@ config DRM_MSM
depends on ARCH_QCOM || (ARM && COMPILE_TEST)
depends on OF && COMMON_CLK
depends on MMU
+ depends on QCOM_MDT_LOADER || QCOM_MDT_LOADER=n
select REGULATOR
select DRM_KMS_HELPER
select DRM_PANEL
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 31a9bce..058cb80 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -11,6 +11,12 @@
*
*/
+#include
+#include
+#include
+#include
+#include
+#include
#include "msm_gem.h"
#include "msm_mmu.h"
#include "a5xx_gpu.h"
@@ -18,6 +24,62 @@
extern bool hang_debug;
static void a5xx_dump(struct msm_gpu *gpu);
+#define GPU_PAS_ID 13
+
+#ifdef CONFIG_QCOM_MDT_LOADER
+
+static int zap_shader_load_mdt(struct device *dev, const char *fwname)
+{
+ const struct firmware *fw;
+ phys_addr_t mem_phys;
+ ssize_t mem_size;
+ void *mem_region = NULL;
+ int ret;
+
+ /* Request the MDT file for the firmware */
+ ret = request_firmware(&fw, fwname, dev);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname);
+ return ret;
+ }
+
+ /* Figure out how much memory we need */
+ mem_size = qcom_mdt_get_size(fw);
+ if (mem_size < 0) {
+ ret = mem_size;
+ goto out;
+ }
+
+ /* Allocate memory for the firmware image */
+ mem_region = dmam_alloc_coherent(dev, mem_size, &mem_phys, GFP_KERNEL);
+ if (!mem_region) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* Load the rest of the MDT */
+ ret = qcom_mdt_load(dev, fw, fwname, GPU_PAS_ID, mem_region, mem_phys,
+ mem_size);
+ if (ret)
+ goto out;
+
+ /* Send the image to the secure world */
+ ret = qcom_scm_pas_auth_and_reset(GPU_PAS_ID);
+ if (ret)
+ DRM_DEV_ERROR(dev, "Unable to authorize the image\n");
+
+out:
+ release_firmware(fw);
+
+ return ret;
+}
+#else
+static int zap_shader_load_mdt(struct device *dev, const char *fwname)
+{
+ return -ENODEV;
+}
+#endif
+
static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx)
{
@@ -304,6 +366,98 @@ static int a5xx_ucode_init(struct msm_gpu *gpu)
return 0;
}
+#define SCM_GPU_ZAP_SHADER_RESUME 0
+
+static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
+{
+ int ret;
+
+ ret = qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID);
+ if (ret)
+ DRM_ERROR("%s: zap-shader resume failed: %d\n",
+ gpu->name, ret);
+
+ return ret;
+}
+
+/* Set up a child device to "own" the zap shader */
+static int a5xx_zap_shader_dev_init(struct device *parent, struct device *dev)
+{
+ struct device_node *node;
+ int ret;
+
+ if (dev->parent)
+ return 0;
+
+ /*
Re: [Intel-gfx] [PATCH 2/3] drm: Create a format/modifier blob
On Wed, May 17, 2017 at 1:31 PM, Daniel Vetter wrote:
> On Tue, May 16, 2017 at 02:19:12PM -0700, Ben Widawsky wrote:
>> On 17-05-03 17:08:27, Daniel Vetter wrote:
>> > On Tue, May 02, 2017 at 10:14:27PM -0700, Ben Widawsky wrote:
>> > > +struct drm_format_modifier_blob {
>> > > +#define FORMAT_BLOB_CURRENT 1
>> > > + /* Version of this blob format */
>> > > + u32 version;
>> > > +
>> > > + /* Flags */
>> > > + u32 flags;
>> > > +
>> > > + /* Number of fourcc formats supported */
>> > > + u32 count_formats;
>> > > +
>> > > + /* Where in this blob the formats exist (in bytes) */
>> > > + u32 formats_offset;
>> > > +
>> > > + /* Number of drm_format_modifiers */
>> > > + u32 count_modifiers;
>> > > +
>> > > + /* Where in this blob the modifiers exist (in bytes) */
>> > > + u32 modifiers_offset;
>> > > +
>> > > + /* u32 formats[] */
>> > > + /* struct drm_format_modifier modifiers[] */
>> > > +} __packed;
>> >
>> > The struct should be in the uapi header. Otherwise it won't show up in
>> > libdrm headers when following the proper process.
>> > -Daniel
>> >
>>
>> I don't agree that blobs are ever really part of the API, but it doesn't
>> hurt to
>> move it... in other words, done.
>
> Userspace writes them, the kernel reads them (or maybe even the other way
> round). How exactly is a specific blob and its layout not part of uapi?
> Can you explain your reasoning here pls?
Ok, this is the other way round, kernel writes this, userspace reads
it. Question still stands.
-Daniel
--
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
On 17 May 2017 at 14:58, Yu, Qiang wrote: > Hi Emil, > > I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure > pass but > fail when compile. > > I think my gcc support c99 but needs adding "-std=c99" to enable it, and the > configure > script add it into CC variable. When just use "make", it's OK, but my build > script uses > "make CC=gcc". > > If you think current state is OK, I can change my build script for that. > Overrides shouldn't be used normally. If needed, one has to be very careful what they set them to. So the question is: why do you set CC - is there something broken on our end? Add "-std=c99" is fine, but I'd suggest dropping the override all together. Thanks Emil ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 0/3] staging: android: ion: Minor clean ups and fixes
On 05/17/2017 01:15 AM, Archit Taneja wrote: > The recent ION clean ups introduced some leftover code that can be > removed, and a bug that comes up if the call to dma_buf_map_attachment() > from an importer fails. Fix these. > > Archit Taneja (3): > staging: android: ion: Remove unused members from ion_buffer > staging: android: ion: Remove ION_FLAG_CACHED_NEEDS_SYNC > staging: android: ion: Avoid calling free_duped_table() twice > > drivers/staging/android/ion/ion.c | 14 +++--- > drivers/staging/android/ion/ion.h | 14 -- > drivers/staging/android/uapi/ion.h | 6 -- > 3 files changed, 3 insertions(+), 31 deletions(-) > Acked-by: Laura Abbott ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support
On Wed, May 17, 2017 at 10:47:16PM +0800, Icenowy Zheng wrote: > This patchset is the initial patchset for Allwinner DE2 support. > > As the DE2 CCU support is already applied, this patchset now contains > only DRM changes and device tree changes. > > The SoC used to develop this patchset is V3s, as V3s is the simplest > one of the SoCs that have DE2. > > (Allwinner V3s features only one mixer, and its only video output is > RGB LCD, which is already supported in our TCON driver) > > The last patch is only a testing patch, it shouldn't be merged; and > for the patch to be really usable, the RFC fix of the TCON driver [1] > is needed. > > No HDMI, TV encoder or other internal bridges' support is included > in this patchset, which makes it currently not usable on H3. > > Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts > to discover the internal of DE2! > > [1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html > > Icenowy Zheng (9): > drm/sun4i: abstract a engine type > drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer > drm/sun4i: add a Kconfig option for sun4i-backend > drm/sun4i: add support for Allwinner DE2 mixers > drm/sun4i: Add compatible string for V3s display engine > drm/sun4i: tcon: add support for V3s TCON Applied all those patches... > ARM: sun8i: v3s: add device nodes for DE2 display pipeline But this one doesn't apply. Please rebase and resend. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
2017-05-18 0:10 GMT+08:00 Emil Velikov : > On 17 May 2017 at 14:58, Yu, Qiang wrote: >> Hi Emil, >> >> I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure >> pass but >> fail when compile. >> >> I think my gcc support c99 but needs adding "-std=c99" to enable it, and the >> configure >> script add it into CC variable. When just use "make", it's OK, but my build >> script uses >> "make CC=gcc". >> >> If you think current state is OK, I can change my build script for that. >> > Overrides shouldn't be used normally. If needed, one has to be very > careful what they set them to. > > So the question is: why do you set CC - is there something broken on our end? > Add "-std=c99" is fine, but I'd suggest dropping the override all together. Indeed it also causes building error on Android before and include 6.0. Adding "-std=c99" will result in more strange errors that I can't understand. So I have to make a similar change to avoid it. -- Chih-Wei Android-x86 project http://www.android-x86.org ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/amd/powerplay: ensure loop does not wraparound on decrement
From: Colin Ian King
The current for loop decrements i when it is zero and this causes
a wrap-around back to ~0 because i is unsigned. In the unlikely event
that mask is 0, the loop will run forever. Fix this so we can't loop
forever.
Detected by CoverityScan, CID#1435469 ("Unsigned compared against 0")
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index ad30f5d3a10d..d92c9b9b15be 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4199,7 +4199,7 @@ static int vega10_force_clock_level(struct pp_hwmgr
*hwmgr,
}
data->smc_state_table.gfx_boot_level = i;
- for (i = 31; i >= 0; i--) {
+ for (i = 32; --i; ) {
if (mask & (1 << i))
break;
}
--
2.11.0
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Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for loop
On Wednesday, 2017-05-17 13:58:42 +, Yu, Qiang wrote:
> Hi Emil,
>
> I didn't modify the code. I'm using Ubuntu 14.04 gcc 4.8.4, the configure
> pass but
> fail when compile.
>
> I think my gcc support c99 but needs adding "-std=c99" to enable it, and the
> configure
> script add it into CC variable.
From the AC_PROG_CC_C99 docs:
> If the C compiler is not in C99 mode by default, try to add an option
> to output variable `CC` to make it so.
G... Add that to the pile of reasons to move away from autotools,
I suppose.
> When just use "make", it's OK, but my build script uses
> "make CC=gcc".
>
> If you think current state is OK, I can change my build script for that.
Yes, I think you should change your build command. It's a shame that
autotools has this bug, but we'd like to avoid changing our codebase to
work around these, and in this case, it would mean dropping the C99
requirement and having to downgrade the whole codebase to something
older.
>
> Regards,
> Qiang
>
> From: Emil Velikov
> Sent: Wednesday, May 17, 2017 9:17:53 PM
> To: Yu, Qiang
> Cc: ML dri-devel
> Subject: Re: [PATCH libdrm] xf86drm: fix compile error for declare i in for
> loop
>
> Hi Qiang Yu,
>
> On 17 May 2017 at 10:26, Qiang Yu wrote:
> > error log:
> > xf86drm.c: In function 'parse_separate_sysfs_files':
> > xf86drm.c:3104:5: error: 'for' loop initial declarations are only allowed
> > in C99 mode
> > for (unsigned i = ignore_revision ? 1 : 0; i < ARRAY_SIZE(attrs); i++)
> > {
> > ^
> > xf86drm.c:3104:5: note: use option -std=c99 or -std=gnu99 to compile your
> > code
> > make[4]: *** [libdrm_la-xf86drm.lo] Error 1
> >
> configure should error out if the compiler does not support C99. Are
> you explicitly patching that out?
> Why can't we use a C99 in 2017 - gcc and clang has supported it for 10+ years.
>
> Thanks
> Emil
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Re: [PATCH] drm: trivial documentation fix to drm_for_each_connector_iter
Daniel Vetter writes:
> On Thu, Apr 20, 2017 at 09:38:19PM -0300, Gabriel Krisman Bertazi wrote:
>> While reading drm_for_each_connector_iter, I noticed a mention to
>> drm_connector_begin which doesn't exist. It should be
>> drm_connector_get.
>>
>> Signed-off-by: Gabriel Krisman Bertazi
>
> Fixes: b982dab1e66d ("drm: Rename connector list iterator API")
> Reviewed-by: Daniel Vetter
Hi Daniel,
Can you apply this one? I couldn't find it in drm-misc yet.
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[Bug 97942] [IGT] [BYT] /gem_mmap_gtt subtest basic-wc fails due to Test assertion failure
https://bugs.freedesktop.org/show_bug.cgi?id=97942 --- Comment #6 from Humberto Israel Perez Rodriguez --- The following test cases failure on BXT with latest configuration igt@gem_mmap@swap-bo igt@gem_mmap_gtt@coherency igt@gem_mmap_gtt@swap-copy igt@gem_mmap_gtt@swap-copy-odd igt@gem_mmap_gtt@swap-copy-xy == Software == kernel version : 4.12.0-rc1-drm-tip-ww20-commit-713f8ec+ architecture: x86_64 os version : Ubuntu 16.10 os codename : yakkety kernel driver : i915 bios revision : 5.6 bios release date : 03/10/2017 ksc : 16.0 == Graphic drivers == Component: drm tag: libdrm-2.4.80-11-ga2fa2e0 commit: a2fa2e08692483cf9f4d06caa6e0f0add59e3343 Component: cairo tag: 1.15.4-21-g9d44136 commit: 9d44136ef8e2a1ad2c6631beb4bbdaeed7a2dad8 Component: intel-gpu-tools tag: intel-gpu-tools-1.18-173-g93215b0 commit: 93215b00db06ba568c34a6cad194f4749bbfbc9d Component: piglit tag: piglit-v1 commit: 7352f4a98a23eae1201bfc4a0121d9c3a969d23f == Hardware == motherboard model : NUC6CAYS motherboard id : NUC6CAYB form factor: Desktop manufacturer : Intelcorporation cpu family : Celeron cpu family id : 6 cpu information: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz gpu card : Intel Corporation Device 5a85 (rev 0b) (prog-if 00 [VGA controller]) memory ram : 15.54 GB cpu thread : 4 cpu core : 4 cpu model : 92 cpu stepping : 9 signature : Type 0, Family 6, Model 92, Stepping 9 current cd clock frequency : 384000 kHz maximum cd clock frequency : 624000 kHz displays connected : DP-1 DP-2 == Firmware == dmc fw loaded : yes dmc version : 1.7 guc fw loaded : NONE guc version wanted: 0.0 guc version found : 0.0 Add Comment -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 97942] [IGT] [BYT] [BXT] /gem_mmap_gtt subtest basic-wc fails due to Test assertion failure
https://bugs.freedesktop.org/show_bug.cgi?id=97942 Humberto Israel Perez Rodriguez changed: What|Removed |Added Summary|[IGT] [BYT] /gem_mmap_gtt |[IGT] [BYT] [BXT] |subtest basic-wc fails due |/gem_mmap_gtt subtest |to Test assertion failure |basic-wc fails due to Test ||assertion failure -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/amd/powerplay: ensure loop does not wraparound on decrement
I sent a patch for this bug earlier. There is a second bug later in the function which my patch fixes as well. regards, dan carpenter ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/4] drm/dp: start a DPCD based DP sink/branch device quirk database
On 05/17/2017 07:25 AM, Jani Nikula wrote:
Face the fact, there are Display Port sink and branch devices out there
in the wild that don't follow the Display Port specifications, or they
have bugs, or just otherwise require special treatment. Start a common
quirk database the drivers can query based on the DP device
identification. At least for now, we leave the workarounds for the
drivers to implement as they see fit.
For starters, add a branch device that can't handle full 24-bit main
link M and N attributes properly. Naturally, the workaround of reducing
main link attributes for all devices ended up in regressions for other
devices. So here we are.
v2: Rebase on DRM DP desc read helpers
Cc: Ville Syrjälä
Cc: Dhinakaran Pandiyan
Cc: Clint Taylor
Cc: Adam Jackson
Cc: Harry Wentland
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 52 +++--
include/drm/drm_dp_helper.h | 32 +
2 files changed, 82 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 52e0ca9a5bb1..8c3797283c3b 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -1209,6 +1209,51 @@ int drm_dp_stop_crc(struct drm_dp_aux *aux)
}
EXPORT_SYMBOL(drm_dp_stop_crc);
+struct dpcd_quirk {
+ u8 oui[3];
+ bool is_branch;
+ u32 quirks;
+};
+
+#define OUI(first, second, third) { (first), (second), (third) }
+
+static const struct dpcd_quirk dpcd_quirk_list[] = {
+ /* Analogix 7737 needs reduced M and N at HBR2 link rates */
+ { OUI(0x00, 0x22, 0xb9), true, BIT(DP_DPCD_QUIRK_LIMITED_M_N) },
+};
+
+#undef OUI
+
+/*
+ * Get a bit mask of DPCD quirks for the sink/branch device identified by
+ * ident. The quirk data is shared but it's up to the drivers to act on the
+ * data.
+ *
+ * For now, only the OUI (first three bytes) is used, but this may be extended
+ * to device identification string and hardware/firmware revisions later.
+ */
+static u32
+drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
+{
+ const struct dpcd_quirk *quirk;
+ u32 quirks = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
+ quirk = &dpcd_quirk_list[i];
+
+ if (quirk->is_branch != is_branch)
+ continue;
+
+ if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui) != 0))
+ continue;
Oops, All branch devices appear to have the quirk applied. The memcmp
should be closed before the !=0
if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
[ 659.496861] [drm:drm_dp_read_desc] DP branch: OUI 00-1c-f8 dev-ID
175IB0 HW-rev 1.0 SW-rev 7.32 quirks 0x0001
[ 659.549017] [drm:drm_dp_read_desc] DP branch: OUI 00-22-b9 dev-ID
7737 HW-rev 10.12 SW-rev 6.4 quirks 0x0001
[ 659.630449] [drm:drm_dp_read_desc] DP sink: OUI ee-ff-c0 dev-ID \001
HW-rev 0.0 SW-rev 0.0 quirks 0x
This was actually good to find out that LSPCON didn't like the reduced M
and N from the quirk at HBR2.
-Clint
+
+ quirks |= quirk->quirks;
+ }
+
+ return quirks;
+}
+
/**
* drm_dp_read_desc - read sink/branch descriptor from DPCD
* @aux: DisplayPort AUX channel
@@ -1231,14 +1276,17 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct
drm_dp_desc *desc,
if (ret < 0)
return ret;
+ desc->quirks = drm_dp_get_quirks(ident, is_branch);
+
dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
- DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n",
+ DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks
0x%04x\n",
is_branch ? "branch" : "sink",
(int)sizeof(ident->oui), ident->oui,
dev_id_len, ident->device_id,
ident->hw_rev >> 4, ident->hw_rev & 0xf,
- ident->sw_major_rev, ident->sw_minor_rev);
+ ident->sw_major_rev, ident->sw_minor_rev,
+ desc->quirks);
return 0;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index aee5b96b51d7..717cb8496725 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1090,12 +1090,44 @@ struct drm_dp_dpcd_ident {
/**
* struct drm_dp_desc - DP branch/sink device descriptor
* @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
+ * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
*/
struct drm_dp_desc {
struct drm_dp_dpcd_ident ident;
+ u32 quirks;
};
int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
bool is_branch);
+/**
+ * enum drm_dp_quirk - Display Port sink/branch device specific quirks
+ *
+ * Display Port sink and branch devices in the wild have a var
Re: [REGRESSION] drm/i915: Wait for all engines to be idle as part of i915_gem_wait_for_idle()
On Wed, May 17, 2017 at 11:29:13PM +0200, Nicolai Stange wrote:
> Hi,
>
> my system (always) locks up when booting a next-20170515 kernel.
>
> No oops. Sending magic sysrqs over serial doesn't cause any reaction.
>
> Last few console messages before death are:
>
> [7.089221] Console: switching to colour frame buffer device 128x48
> [7.101470] radeon :01:00.0: fb0: radeondrmfb frame buffer device
> [7.111292] [drm] Initialized radeon 2.50.0 20080528 for :01:00.0 on
> minor 1
> [7.113056] [drm] Initialized i915 1.6.0 20170403 for :00:02.0 on
> minor 0
> [7.113446] [Firmware Bug]: ACPI(PEGP) defines _DOD but not _DOS
> [7.114227] ACPI: Video Device [PEGP] (multi-head: yes rom: no post:
> no)
> [7.114798] input: Video Bus as
> /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:4f/LNXVIDEO:00/input/input12
> [7.116253] ACPI: Video Device [GFX0] (multi-head: yes rom: no post:
> no)
> [7.130432] input: Video Bus as
> /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:01/input/input13
> [7.130481] [drm] Initialized i915 1.6.0 20170403 for :00:02.0 on
> minor 0
>
>
> Bisection lead to commit 25112b64b3d2 ("drm/i915: Wait for all engines
> to be idle as part of i915_gem_wait_for_idle()"). Reverting this commit
> on top of next-20170515 fixes the issue for me.
That's really odd as it adds a loop around a previous used function with
a timeout. If the timeout is hit, we get a loud bang, but nothing that
should take the machine out, just one portion of the driver.
drm.debug=0xff would be one step to see more breadcrumbs prior to
death. Did you enable the i915 debugging? I hope not, we tried walling
it off to prevent it being accidentally enabled... Otherwise, it looks
like we need a bit of printk debugging to work out just what it doesn't
like.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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[Bug 100577] DC + TearFree display lock
https://bugs.freedesktop.org/show_bug.cgi?id=100577 --- Comment #8 from Andy Furniss --- I can still reproduce this. Seems I may just get lucky runs - one 90 mins no issue, stopped and started again later and it locked after 20. -- You are receiving this mail because: You are the assignee for the bug.___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/2] dt/bindings: display: move rotation into a common place
Commit b60c1be74741 (dt-bindings: display/panel: Add common rotation property) added the rotation property description in a new file. We have a place for common display panel properties already. Move there the rotation property. Cc: Noralf Trønnes Cc: Rob Herring Signed-off-by: Baruch Siach --- Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++ Documentation/devicetree/bindings/display/panel/panel.txt| 4 2 files changed, 6 insertions(+), 4 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/panel.txt diff --git a/Documentation/devicetree/bindings/display/panel/panel-common.txt b/Documentation/devicetree/bindings/display/panel/panel-common.txt index 0603af877155..c92dcfd8c32f 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-common.txt +++ b/Documentation/devicetree/bindings/display/panel/panel-common.txt @@ -89,3 +89,9 @@ backlight controller. - backlight: For panels whose backlight is controlled by an external backlight controller, this property contains a phandle that references the controller. + + +Rotation + + +- rotation: Display rotation in degrees counter clockwise (0,90,180,270) diff --git a/Documentation/devicetree/bindings/display/panel/panel.txt b/Documentation/devicetree/bindings/display/panel/panel.txt deleted file mode 100644 index e2e6867852b8.. --- a/Documentation/devicetree/bindings/display/panel/panel.txt +++ /dev/null @@ -1,4 +0,0 @@ -Common display properties -- - -- rotation:Display rotation in degrees counter clockwise (0,90,180,270) -- 2.11.0 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/tegra: Check offsets of a submitted command buffer and of relocations
On 16.05.2017 11:10, Mikko Perttunen wrote:
>
>
> On 16.05.2017 10:32, Erik Faye-Lund wrote:
>> On Tue, May 16, 2017 at 8:56 AM, Mikko Perttunen wrote:
>>> On 14.05.2017 23:47, Dmitry Osipenko wrote:
If commands buffer claims a number of words that is higher than its BO can
fit, a kernel OOPS will be fired on the out-of-bounds BO access. This was
triggered by an opentegra Xorg driver that erroneously pushed too many
commands to the pushbuf. The CMDA commands buffer address is 4 bytes
aligned, so check the alignment as well.
Add a sanity check for the relocations in a same way.
[ 46.829393] Unable to handle kernel paging request at virtual address
f09b2000
...
[] (host1x_job_pin) from []
(tegra_drm_submit+0x474/0x510)
[] (tegra_drm_submit) from [] (tegra_submit+0x50/0x6c)
[] (tegra_submit) from [] (drm_ioctl+0x1e4/0x3ec)
[] (drm_ioctl) from [] (do_vfs_ioctl+0x9c/0x8e4)
[] (do_vfs_ioctl) from [] (SyS_ioctl+0x34/0x5c)
[] (SyS_ioctl) from [] (ret_fast_syscall+0x0/0x3c)
Signed-off-by: Dmitry Osipenko
Reviewed-by: Erik Faye-Lund
---
drivers/gpu/drm/tegra/drm.c | 30 ++
drivers/gpu/drm/tegra/gem.c | 5 -
drivers/gpu/drm/tegra/gem.h | 5 +
3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 768750226452..c5844a065681 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -362,6 +362,8 @@ int tegra_drm_submit(struct tegra_drm_context
*context,
while (num_cmdbufs) {
struct drm_tegra_cmdbuf cmdbuf;
struct host1x_bo *bo;
+ struct tegra_bo *obj;
+ u64 offset;
if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
err = -EFAULT;
@@ -374,6 +376,14 @@ int tegra_drm_submit(struct tegra_drm_context
*context,
goto fail;
}
+ offset = (u64)cmdbuf.offset + (u64)cmdbuf.words *
sizeof(u32);
+ obj = host1x_to_tegra_bo(bo);
+
+ if (offset & 3 || offset > obj->gem.size) {
+ err = -EINVAL;
+ goto fail;
+ }
+
host1x_job_add_gather(job, bo, cmdbuf.words,
cmdbuf.offset);
num_cmdbufs--;
cmdbufs++;
@@ -381,11 +391,31 @@ int tegra_drm_submit(struct tegra_drm_context
*context,
/* copy and resolve relocations from submit */
while (num_relocs--) {
+ struct host1x_reloc *reloc;
+ struct tegra_bo *obj;
+
err =
host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
&relocs[num_relocs],
drm,
file);
if (err < 0)
goto fail;
+
+ reloc = &job->relocarray[num_relocs];
+ obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
+
+ if (reloc->cmdbuf.offset & 3 ||
+ reloc->cmdbuf.offset > obj->gem.size) {
>>>
>>>
>>> This could still fail if the bo's size is not divisible by 4, even with >=
>>> comparison (we would overwrite the buffer by 1 to 3 bytes). I would do the
>>> same as in the gather case, i.e. find out the address immediately after the
>>> write and compare using >. Perhaps add a helper function if it makes sense.
>>> I also don't think the "& 3" checks are needed.
>>
>> The bo-size is always a multiple of PAGE_SIZE, due to the rounding in
>> tegra_bo_alloc_object(), so I don't think this actually can fail. But
>> maybe we want to future-proof this code for a potential future where
>> this is not the case?
>>
>
> Yeah, I think whether or not this might change in the future, the code would
> be
> easier to understand with the change.
It's very unlikely to me that BO size round-upping may go away. I'll add a
comment for that alignment check to make it clear in the code.
--
Dmitry
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Re: [PATCH] drm: use kvmalloc_array for drm_malloc*
On Tue 16-05-17 15:08:56, Daniel Vetter wrote: > On Tue, May 16, 2017 at 11:52:55AM +0200, Michal Hocko wrote: > > On Tue 16-05-17 11:22:30, Daniel Vetter wrote: > > > On Tue, May 16, 2017 at 11:06:06AM +0200, Michal Hocko wrote: > > > > From: Michal Hocko > > > > > > > > drm_malloc* has grown their own kmalloc with vmalloc fallback > > > > implementations. MM has grown kvmalloc* helpers in the meantime. Let's > > > > use those because it a) reduces the code and b) MM has a better idea > > > > how to implement fallbacks (e.g. do not vmalloc before kmalloc is tried > > > > with __GFP_NORETRY). > > > > > > > > Signed-off-by: Michal Hocko > > > > > > Shouldn't we go one step further and just remove these wrappers, maybe > > > with cocci? > > > > my cocci sucks... > > > > > Especially drm_malloc_gfp is surpremely pointless after this > > > patch (and drm_malloc_ab probably not that useful either). > > > > So what about the following instead? It passes allyesconfig compilation. > > Yeah, looks good, but perhaps rebased onto your first patch. That way we > split the functional change from the refactor (not the first time innocent > looking changes in i915 gem code resulted in surprises). OK, I will split it. > Your patch also seems to need some stuff from -rc1, and atm drm-misc is > still pre-rc1, so I'll pull both patches in once that's sorted (I can do > the rebase myself, since it's rather trivial). But pls remind me in case > it falls through the cracks and isn't in linux-next by end of this week > :-) I have based it on top of the current linux next (next-20170516). Let me know if other tree is more appropriate. -- Michal Hocko SUSE Labs ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v8 5/5] drm/i915: Set PWM divider to match desired frequency in vbt
Read desired PWM frequency from panel vbt and calculate the
value for divider in DPCD address 0x724 and 0x728 to have
as many bits as possible for PWM duty cyle for granularity of
brightness adjustment while the frequency divisor is still
within 25% of the desired value.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 82 +++
1 file changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index c0eeb8fc2013..a01cbf3db1c2 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -116,12 +116,87 @@ intel_dp_aux_set_dynamic_backlight_percent(struct
intel_dp *intel_dp,
}
}
+/*
+ * Set PWM Frequency divider to match desired frequency in vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+static void intel_dp_aux_set_pwm_freq(struct intel_connector *connector)
+{
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
+ int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ u8 pn, pn_min, pn_max;
+
+ /* Find desired value of (F x P)
+* Note that, if F x P is out of supported range, the maximum value or
+* minimum value will applied automatically. So no need to check that.
+*/
+ freq = dev_priv->vbt.backlight.pwm_freq_hz;
+ DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq);
+ if (!freq) {
+ DRM_DEBUG_KMS("Use panel default backlight frequency\n");
+ return;
+ }
+
+ fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
+
+ /* Use highest possible value of Pn for more granularity of brightness
+* adjustment while satifying the conditions below.
+* - Pn is in the range of Pn_min and Pn_max
+* - F is in the range of 1 and 255
+* - FxP is within 25% of desired value.
+* Note: 25% is arbitrary value and may need some tweak.
+*/
+ if (drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
+ DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n");
+ return;
+ }
+ if (drm_dp_dpcd_readb(&intel_dp->aux,
+ DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
+ DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n");
+ return;
+ }
+ pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+ fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+ if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+ DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n");
+ return;
+ }
+
+ for (pn = pn_max; pn >= pn_min; pn--) {
+ f = clamp(DIV_ROUND_CLOSEST(fxp , 1 << pn), 1, 255);
+ fxp_actual = f << pn;
+ if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+ break;
+ }
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+ DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n");
+ return;
+ }
+ if (drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
+ DRM_DEBUG_KMS("Failed to write aux backlight freq\n");
+ return;
+ }
+}
+
static void intel_dp_aux_enable_backlight(struct intel_connector *connector)
{
struct intel_dp *intel_dp = enc_to_intel_dp(&connector->encoder->base);
uint8_t dpcd_buf = 0;
uint8_t new_dpcd_buf = 0;
uint8_t edp_backlight_mode = 0;
+ bool freq_cap;
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
@@ -154,6 +229,10 @@ static void intel_dp_aux_enable_backlight(struct
intel_connector *connector)
DRM_DEBUG_KMS("Enable dynamic brightness.\n");
}
+ freq_cap = intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP;
+ if (freq_cap)
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
@@ -161,6 +240,9 @@ static void intel_dp_aux_
Re: [PATCH 1/2] drm: replace drm_[cm]alloc* by kvmalloc alternatives
On Wed 17-05-17 10:12:41, Chris Wilson wrote:
> On Wed, May 17, 2017 at 11:03:50AM +0200, Michal Hocko wrote:
[...]
> > +static inline bool alloc_array_check(size_t n, size_t size)
> > +{
> > + if (size != 0 && n > SIZE_MAX / size)
> > + return false;
> > + return true;
>
> Just return size == 0 || n <= SIZE_MAX /size ?
>
> Whether or not size being 0 makes for a sane user is another question.
> The guideline is that size is the known constant from sizeof() or
> whatever and n is the variable number to allocate.
>
> But yes, that inline is what I want :)
I will think about this. Maybe it will help to simplify/unify some other
users. Do you have any pointers to save me some grepping...?
--
Michal Hocko
SUSE Labs
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Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt
On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat wrote: > > > > > > On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran > > wrote: > > On Tue, 2017-05-16 at 11:07 -0700, Puthikorn Voravootivat > > wrote: > > > > > > > > > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran > > > wrote: > > > On Mon, 2017-05-15 at 17:43 -0700, Puthikorn > > Voravootivat > > > wrote: > > > > > > > > > > > > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, > > Dhinakaran > > > > wrote: > > > > On Fri, 2017-05-12 at 17:31 -0700, > > Puthikorn > > > Voravootivat > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Fri, May 12, 2017 at 5:12 PM, > > Pandiyan, > > > Dhinakaran > > > > > wrote: > > > > > On Thu, 2017-05-11 at 16:02 > > -0700, > > > Puthikorn > > > > Voravootivat > > > > > wrote: > > > > > > Read desired PWM frequency > > from panel > > > vbt and > > > > calculate the > > > > > > value for divider in DPCD > > address 0x724 > > > and 0x728 > > > > to have > > > > > > as many bits as possible for > > PWM duty > > > cyle for > > > > granularity > > > > > of > > > > > > brightness adjustment while > > the > > > frequency is still > > > > within > > > > > 25% > > > > > > of the desired frequency. > > > > > > > > > > I read a few eDP panel data > > sheets, the > > > PWM > > > > frequencies all > > > > > start from > > > > > ~200Hz. If the VBT chooses this > > lowest > > > value to > > > > allow for more > > > > > brightness control, and then > > this patch > > > lowers the > > > > value by > > > > > another 25%, > > > > > we'll end up below the panel > > allowed PWM > > > frequency. > > > > > > > > > > In fact, one of the systems I > > checked had > > > PWM > > > > frequency as > > > > > 200Hz in VBT > > > > > and the panel datasheet also had > > PWM > > > frequency range > > > > starting > > > > > from > > > > > 200Hz. Have you considered this > > case? > > > > > > > > > > The spec said "A given LCD panel > > typically has a > > > limited > > > > range of > > > > > backlight frequency capability. > > > > > To limit the programmable frequency > > range, > > > limitations are > > > > placed on > > > > > the allowable total divider ratio with > > the Sink > > > device" > > > > > So I think it should be auto cap to > > 200Hz in this > > > case. > > > > > > > > > > -DK > > > > > > > > > > > > Signed-off-by: Puthikorn > > Voravootivat > > > > > > > > > > --- > > > > > > > > > drivers/gpu/drm/i915/intel_dp_aux_backlight.c | > > > > 81 > > > > > +++ > > > > > > 1 file changed, 81 > > insertions(+) > > > > > > > > > > > > diff --git > > > > > > a/drivers/
Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt
On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran < dhinakaran.pandi...@intel.com> wrote: > On Tue, 2017-05-16 at 11:07 -0700, Puthikorn Voravootivat wrote: > > > > > > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran > > wrote: > > On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat > > wrote: > > > > > > > > > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, Dhinakaran > > > wrote: > > > On Fri, 2017-05-12 at 17:31 -0700, Puthikorn > > Voravootivat > > > wrote: > > > > > > > > > > > > > > > > On Fri, May 12, 2017 at 5:12 PM, Pandiyan, > > Dhinakaran > > > > wrote: > > > > On Thu, 2017-05-11 at 16:02 -0700, > > Puthikorn > > > Voravootivat > > > > wrote: > > > > > Read desired PWM frequency from panel > > vbt and > > > calculate the > > > > > value for divider in DPCD address 0x724 > > and 0x728 > > > to have > > > > > as many bits as possible for PWM duty > > cyle for > > > granularity > > > > of > > > > > brightness adjustment while the > > frequency is still > > > within > > > > 25% > > > > > of the desired frequency. > > > > > > > > I read a few eDP panel data sheets, the > > PWM > > > frequencies all > > > > start from > > > > ~200Hz. If the VBT chooses this lowest > > value to > > > allow for more > > > > brightness control, and then this patch > > lowers the > > > value by > > > > another 25%, > > > > we'll end up below the panel allowed PWM > > frequency. > > > > > > > > In fact, one of the systems I checked had > > PWM > > > frequency as > > > > 200Hz in VBT > > > > and the panel datasheet also had PWM > > frequency range > > > starting > > > > from > > > > 200Hz. Have you considered this case? > > > > > > > > The spec said "A given LCD panel typically has a > > limited > > > range of > > > > backlight frequency capability. > > > > To limit the programmable frequency range, > > limitations are > > > placed on > > > > the allowable total divider ratio with the Sink > > device" > > > > So I think it should be auto cap to 200Hz in this > > case. > > > > > > > > -DK > > > > > > > > > > Signed-off-by: Puthikorn Voravootivat > > > > > > > > --- > > > > > > > drivers/gpu/drm/i915/intel_dp_aux_backlight.c | > > > 81 > > > > +++ > > > > > 1 file changed, 81 insertions(+) > > > > > > > > > > diff --git > > > a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c > > > > > > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c > > > > > index 0b48851013cc..6f10a2f1ab76 100644 > > > > > --- > > > a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c > > > > > +++ > > > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c > > > > > @@ -113,12 +113,86 @@ > > > > > > intel_dp_aux_set_dynamic_backlight_percent(struct > > > intel_dp > > > > *intel_dp, > > > > > } > > > > > } > > > > > > > > > > +/* > > > > > + * Set PWM Frequency divider to match > > desired > > > frequency in > > > > vbt. > > > > > + * The PWM Frequency is calculated as > > 27Mhz / (F > > > x P). > > > > > + * - Where F = PWM Frequency > > Pre-Divider value > > > programmed > > > > by field 7:0 of the > > > > > + * EDP_BACKLIGHT_FRE
[RFC PATCH 01/11] dt-bindings: update the binding for Allwinner H3 TVE support
Allwinner H3 features a "DE2.0" and a TV Encoder. Add device tree bindings for the following parts: - H3 TCONs - H3 Mixers - The connection between H3 TCONs and H3 Mixers - H3 TV Encoder - H3 Display engine Signed-off-by: Icenowy Zheng --- .../bindings/display/sunxi/sun4i-drm.txt | 47 -- 1 file changed, 43 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 66b85a195ef2..52781943713b 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -21,7 +21,9 @@ The TV Encoder supports the composite and VGA output. It is one end of the pipeline. Required properties: - - compatible: value should be "allwinner,sun4i-a10-tv-encoder". + - compatible: value must be either: +* allwinner,sun4i-a10-tv-encoder +* allwinner,sun8i-h3-tv-encoder - reg: base address and size of memory-mapped region - clocks: the clocks driving the TV encoder - resets: phandle to the reset controller driving the encoder @@ -30,6 +32,13 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoint. +For "allwinner,sun4i-a10-tv-encoder", there is only one clock required, +and it's not named. + +For "allwinner,sun8i-h3-tv-encoder", these clocks are needed: +- 'bus': the AHB bus clock of TVE +- 'mod': the mod clock of TVE + TCON @@ -41,29 +50,51 @@ Required properties: * allwinner,sun6i-a31-tcon * allwinner,sun6i-a31s-tcon * allwinner,sun8i-a33-tcon + * allwinner,sun8i-h3-tcon0 + * allwinner,sun8i-h3-tcon1 * allwinner,sun8i-v3s-tcon - reg: base address and size of memory-mapped region - interrupts: interrupt associated to this IP - clocks: phandles to the clocks feeding the TCON. Three are needed: - 'ahb': the interface clocks - - 'tcon-ch0': The clock driving the TCON channel 0 - resets: phandles to the reset controllers driving the encoder - "lcd": the reset line for the TCON channel 0 - clock-names: the clock names mentioned above - reset-names: the reset names mentioned above - - clock-output-names: Name of the pixel clock created - ports: A ports node with endpoint definitions as defined in Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoint, the second one the output + In the situation of Display Engine 2.0 that the connection between + the mixer and the TCON can be swapped, the input should have two + endpoints. The first is the default mixer connected to the TCON, + the second the mixer which will be connected to the TCON if the + swap bit is set. + The output should have two endpoints. The first is the block connected to the TCON channel 0 (usually a panel or a bridge), the second the block connected to the TCON channel 1 (usually the TV encoder) -On SoCs other than the A33 and V3s, there is one more clock required: +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-a33-tcon + * allwinner,sun8i-v3s-tcon +there is one more clock and one more property required: + - clocks: + - 'tcon-ch0': The clock driving the TCON channel 0 + - clock-output-names: Name of the pixel clock created + +For the following compatibles: + * allwinner,sun5i-a13-tcon + * allwinner,sun6i-a31-tcon + * allwinner,sun6i-a31s-tcon + * allwinner,sun8i-h3-tcon0 +there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 DRC @@ -158,6 +189,8 @@ supported. Required properties: - compatible: value must be one of: * allwinner,sun8i-v3s-de2-mixer +* allwinner,sun8i-h3-de2-mixer0 +* allwinner,sun8i-h3-de2-mixer1 - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the mixer * bus: the mixer interface clock @@ -169,6 +202,11 @@ Required properties: Documentation/devicetree/bindings/media/video-interfaces.txt. The first port should be the input endpoints, the second one the output + In the situation of Display Engine 2.0 that the connection between + the mixer and the TCON can be swapped, the output should have two + endpoints. The first is the default TCON connected to the mixer, + the second the TCON which will be connected to the mixer if the + swap bit is set. Display Engine Pipeline --- @@ -183,6 +221,7 @@ Required properties: * allwinner,sun6i-a31-display-engine * allwinner,sun6i-a31s-display-engine * allwinner,sun8i-a33-display-engine +* allwinner,sun8i-h3-display-engine * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine -- 2.12.2 _
Re: [PATCH v3 19/21] drm/sun4i: Add compatible for the A10s pipeline
On Wed, May 17, 2017 at 3:40 PM, Maxime Ripard wrote: > The A10s has a slightly different display pipeline than the A13, with an > HDMI controller. > > Add a compatible for it. > > Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH v8 0/9] Initial Allwinner Display Engine 2.0 Support
This patchset is the initial patchset for Allwinner DE2 support. As the DE2 CCU support is already applied, this patchset now contains only DRM changes and device tree changes. The SoC used to develop this patchset is V3s, as V3s is the simplest one of the SoCs that have DE2. (Allwinner V3s features only one mixer, and its only video output is RGB LCD, which is already supported in our TCON driver) The last patch is only a testing patch, it shouldn't be merged; and for the patch to be really usable, the RFC fix of the TCON driver [1] is needed. No HDMI, TV encoder or other internal bridges' support is included in this patchset, which makes it currently not usable on H3. Thanks to Jean-Francois Moine and Jernej Skrabec for their efforts to discover the internal of DE2! [1] https://lists.freedesktop.org/archives/dri-devel/2016-December/126264.html Icenowy Zheng (9): drm/sun4i: abstract a engine type drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer drm/sun4i: add a Kconfig option for sun4i-backend drm/sun4i: add support for Allwinner DE2 mixers drm/sun4i: Add compatible string for V3s display engine drm/sun4i: tcon: add support for V3s TCON ARM: sun8i: v3s: add device nodes for DE2 display pipeline ARM: sun8i: v3s: add pinmux for LCD pins of V3s SoC [DO NOT MERGE] ARM: sun8i: v3s: enable LCD panel of Lichee Pi Zero arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 36 +++ arch/arm/boot/dts/sun8i-v3s.dtsi | 96 ++ drivers/gpu/drm/sun4i/Kconfig | 20 ++ drivers/gpu/drm/sun4i/Makefile| 9 +- drivers/gpu/drm/sun4i/sun4i_backend.c | 78 ++--- drivers/gpu/drm/sun4i/sun4i_backend.h | 19 +- drivers/gpu/drm/sun4i/sun4i_crtc.c| 11 +- drivers/gpu/drm/sun4i/sun4i_crtc.h| 4 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 6 +- drivers/gpu/drm/sun4i/sun4i_drv.h | 2 +- drivers/gpu/drm/sun4i/sun4i_layer.c | 9 +- drivers/gpu/drm/sun4i/sun4i_layer.h | 4 +- drivers/gpu/drm/sun4i/sun4i_tcon.c| 43 +-- drivers/gpu/drm/sun4i/sun4i_tv.c | 9 +- drivers/gpu/drm/sun4i/sun8i_layer.c | 134 + drivers/gpu/drm/sun4i/sun8i_layer.h | 36 +++ drivers/gpu/drm/sun4i/sun8i_mixer.c | 414 ++ drivers/gpu/drm/sun4i/sun8i_mixer.h | 137 + drivers/gpu/drm/sun4i/sunxi_engine.h | 98 ++ 19 files changed, 1077 insertions(+), 88 deletions(-) create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c create mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.c create mode 100644 drivers/gpu/drm/sun4i/sun8i_mixer.h create mode 100644 drivers/gpu/drm/sun4i/sunxi_engine.h -- 2.12.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[RFC PATCH 02/11] drm: sun4i: add support for H3 mixers
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI.
Add support for these two variants.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c
b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..d658a3a8159a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -390,11 +390,29 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg =
{
.ui_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ .vi_num = 1,
+ .ui_num = 3,
+};
+
+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ .vi_num = 1,
+ .ui_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer0",
+ .data = &sun8i_h3_mixer0_cfg
+ },
+ {
+ .compatible = "allwinner,sun8i-h3-de2-mixer1",
+ .data = &sun8i_h3_mixer1_cfg
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.12.2
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Re: [PATCH v3 14/21] drm/sun4i: tcon: multiply the vtotal when not in interlace
On Wed, May 17, 2017 at 3:40 PM, Maxime Ripard
wrote:
> It appears that the total vertical resolution needs to be doubled when
> we're not in interlaced. Make sure that is the case.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +
> 1 file changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> index 62e254aedb57..a0f9a8a516c7 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
> @@ -153,7 +153,7 @@ static int sun4i_tcon_get_clk_delay(struct
> drm_display_mode *mode,
> void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> struct drm_display_mode *mode)
> {
> - unsigned int bp, hsync, vsync;
> + unsigned int bp, hsync, vsync, vtotal;
> u8 clk_delay;
> u32 val = 0;
>
> @@ -192,9 +192,26 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
> DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
> mode->crtc_vtotal, bp);
>
> + /*
> +* The vertical resolution needs to be doubled in all
> +* cases. We could use crtc_vtotal and always multiply by two,
> +* but that leads to a rounding error in interlace when vtotal
> +* is odd.
> +*
> +* This happens with TV's PAL for example, where vtotal will
> +* be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
> +* 624, which apparently confuses the hardware.
> +*
> +* To work around this, we will always use vtotal, and
> +* multiply by two only if we're not in interlace.
> +*/
> + vtotal = mode->vtotal;
> + if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
> + vtotal = vtotal * 2;
> +
> /* Set vertical display timings */
> regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
> -SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
> +SUN4I_TCON0_BASIC2_V_TOTAL(vtotal) |
> SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
>
> /* Set Hsync and Vsync length */
> @@ -279,9 +296,9 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
> /* Set vertical display timings */
> bp = mode->crtc_vtotal - mode->crtc_vsync_start;
> DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
> -mode->vtotal, bp);
> +mode->crtc_vtotal, bp);
You should duplicate the logic from channel 0 to channel 1.
In fact, interlaced modes happen predominantly on channel 1,
for composite and HDMI modes.
ChenYu
> regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
> -SUN4I_TCON1_BASIC4_V_TOTAL(mode->vtotal) |
> +SUN4I_TCON1_BASIC4_V_TOTAL(mode->crtc_vtotal * 2) |
> SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
>
> /* Set Hsync and Vsync length */
> --
> git-series 0.9.1
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[PATCH v8 6/9] drm/sun4i: tcon: add support for V3s TCON
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v7:
- Added Chen-Yu's Reviewed-by.
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 4a979d17ddaa..1dd1948025d2 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -178,7 +178,8 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return of_device_is_compatible(node, "allwinner,sun5i-a13-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
- of_device_is_compatible(node, "allwinner,sun8i-a33-tcon");
+ of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+ of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
}
static int compare_of(struct device *dev, void *data)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 990c973c0334..f44a37a5993d 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -601,11 +601,16 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
/* nothing is supported */
};
+static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
+ /* nothing is supported */
+};
+
static const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks
},
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
+ { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
--
2.12.2
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[RFC PATCH 00/11] Support for H3 Composite Output support
This patchset depends on the DE2 patchset, version 8 of that patchset is available at [1]. Allwinner H3 SoC features a TV Encoder like the one in Allwinner A13, which can only output TV Composite signal. The display pipeline of H3 is also special -- it has two mixers and two TCONs, of which the connection can be swapped. The TCONs do not have channel 0 (as they are all connected to internal bridges, TVE and HDMI TX). Add support for the display pipeline and the TVE in H3, in order to make it possible to display something with mainline kernel with H3. The image quality of TVE is bad, so HDMI is a better output -- this patchset also prepared the mixers and TCONs for HDMI output, and the HDMI controller driver is already done by Jernej Skrabec. Currently the jack detection feature of the TVE is still not so clear -- so it's not implemented in this version. Thus the TV output shouldn't be defaultly enabled now. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2017-May/506806.html Icenowy Zheng (11): dt-bindings: update the binding for Allwinner H3 TVE support drm: sun4i: add support for H3 mixers drm: sun4i: ignore swapped mixer<->tcon connection for DE2 drm: sun4i: add support for H3's TCON0/1 drm: sun4i: add compatible for H3 display engine drm: sun4i: add color space correction support for DE2 mixer drm: sun4i: add support for the TV encoder in H3 SoC clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 clk: sunxi-ng: export CLK_PLL_DE for H3 ARM: sun8i: h3: add display engine pipeline for TVE [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC .../bindings/display/sunxi/sun4i-drm.txt | 47 - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 12 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 189 + drivers/clk/sunxi-ng/ccu-sun8i-h3.c| 2 +- drivers/clk/sunxi-ng/ccu-sun8i-h3.h| 3 +- drivers/gpu/drm/sun4i/sun4i_drv.c | 28 +++ drivers/gpu/drm/sun4i/sun4i_tcon.c | 117 + drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 + drivers/gpu/drm/sun4i/sun4i_tv.c | 65 ++- drivers/gpu/drm/sun4i/sun8i_mixer.c| 53 ++ drivers/gpu/drm/sun4i/sun8i_mixer.h| 6 +- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 + 12 files changed, 488 insertions(+), 41 deletions(-) -- 2.12.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 2/2 -v2] drm: drop drm_[cm]alloc* helpers
As it turned out my allyesconfig on x86_64 wasn't sufficient and 0day build machinery found a failure on arm architecture. It was clearly a typo. Now I have pushed this to my build battery with cross arch compilers and it passes so there shouldn't more surprises hopefully. Here is the v2. --- From 4a00b3ade5ca4514f7affd8de6f7119c8d5c5a86 Mon Sep 17 00:00:00 2001 From: Michal Hocko Date: Tue, 16 May 2017 11:00:47 +0200 Subject: [PATCH -v2] drm: drop drm_[cm]alloc* helpers Now that drm_[cm]alloc* helpers are simple one line wrappers around kvmalloc_array and drm_free_large is just kvfree alias we can drop them and replace by their native forms. This shouldn't introduce any functional change. Changes since v1 - fix typo in drivers/gpu//drm/etnaviv/etnaviv_gem.c - noticed by 0day build robot Suggested-by: Daniel Vetter Signed-off-by: Michal Hocko --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c| 16 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 19 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 7 +-- drivers/gpu/drm/drm_gem.c | 6 +-- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 12 ++--- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c| 4 +- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 12 ++--- drivers/gpu/drm/exynos/exynos_drm_gem.c| 11 +++-- drivers/gpu/drm/i915/i915_debugfs.c| 4 +- drivers/gpu/drm/i915/i915_gem.c| 4 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 34 +++--- drivers/gpu/drm/i915/i915_gem_gtt.c| 6 +-- drivers/gpu/drm/i915/i915_gem_userptr.c| 8 ++-- drivers/gpu/drm/i915/selftests/intel_breadcrumbs.c | 12 ++--- drivers/gpu/drm/msm/msm_gem.c | 10 ++-- drivers/gpu/drm/radeon/radeon_cs.c | 11 +++-- drivers/gpu/drm/radeon/radeon_gem.c| 2 +- drivers/gpu/drm/radeon/radeon_ring.c | 4 +- drivers/gpu/drm/radeon/radeon_vm.c | 4 +- drivers/gpu/drm/ttm/ttm_tt.c | 13 +++--- drivers/gpu/drm/udl/udl_dmabuf.c | 2 +- drivers/gpu/drm/udl/udl_gem.c | 2 +- drivers/gpu/drm/vc4/vc4_gem.c | 15 +++--- drivers/gpu/drm/virtio/virtgpu_ioctl.c | 27 +-- include/drm/drmP.h | 1 - include/drm/drm_mem_util.h | 53 -- 26 files changed, 126 insertions(+), 173 deletions(-) delete mode 100644 include/drm/drm_mem_util.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index a6649874e6ce..9f0247cdda5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -96,7 +96,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, int r; unsigned long total_size = 0; - array = drm_malloc_ab(num_entries, sizeof(struct amdgpu_bo_list_entry)); + array = kvmalloc_array(num_entries, sizeof(struct amdgpu_bo_list_entry), GFP_KERNEL); if (!array) return -ENOMEM; memset(array, 0, num_entries * sizeof(struct amdgpu_bo_list_entry)); @@ -148,7 +148,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, for (i = 0; i < list->num_entries; ++i) amdgpu_bo_unref(&list->array[i].robj); - drm_free_large(list->array); + kvfree(list->array); list->gds_obj = gds_obj; list->gws_obj = gws_obj; @@ -163,7 +163,7 @@ static int amdgpu_bo_list_set(struct amdgpu_device *adev, error_free: while (i--) amdgpu_bo_unref(&array[i].robj); - drm_free_large(array); + kvfree(array); return r; } @@ -224,7 +224,7 @@ void amdgpu_bo_list_free(struct amdgpu_bo_list *list) amdgpu_bo_unref(&list->array[i].robj); mutex_destroy(&list->lock); - drm_free_large(list->array); + kvfree(list->array); kfree(list); } @@ -244,8 +244,8 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, int r; - info = drm_malloc_ab(args->in.bo_number, -sizeof(struct drm_amdgpu_bo_list_entry)); + info = kvmalloc_array(args->in.bo_number, +sizeof(struct drm_amdgpu_bo_list_entry), GFP_KERNEL); if (!info) return -ENOMEM; @@ -311,11 +311,11 @@ int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, memset(args, 0, sizeof(*args)); args->out.list_handle = handle; - drm_free_large(info); + kvfree(info); return 0; error_free: - drm_free_large(info); + kvfree(info); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4e6b9501ab0a..5b3e0f63a115 100644 --- a/drivers/gpu/drm/amd/a
[RFC PATCH 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
Allwinner H3 features a PLL named CLK_PLL_DE, and a mod clock for the
"Display Engine 2.0" named CLK_DE. As the name indicated, the CLK_PLL_DE
is a PLL for CLK_DE.
Only CLK_DE and CLK_TVE have a parent of CLK_PLL_DE, and CLK_TVE is also
one part of the display clocks.
So allow CLK_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..6e39ba7cb173 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -439,7 +439,7 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
-0x104, 0, 4, 24, 3, BIT(31), 0);
+0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
--
2.12.2
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[PATCH v8 1/5] drm/i915: Drop AUX backlight enable check for backlight control
There are some panel that
(1) does not support display backlight enable via AUX
(2) support display backlight adjustment via AUX
(3) support display backlight enable via eDP BL_ENABLE pin
The current driver required that (1) must be support to enable (2).
This patch drops that requirement.
Signed-off-by: Puthikorn Voravootivat
---
drivers/gpu/drm/i915/intel_dp_aux_backlight.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
index b87c5a381d6a..d32c06583e0b 100644
--- a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
@@ -165,7 +165,6 @@ intel_dp_aux_display_control_capable(struct intel_connector
*connector)
* the panel can support backlight control over the aux channel
*/
if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) &&
!((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_PIN_ENABLE_CAP) ||
(intel_dp->edp_dpcd[2] &
DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP))) {
--
2.13.0.303.g4ebf302169-goog
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[PATCH v8 7/9] ARM: sun8i: v3s: add device nodes for DE2 display pipeline
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.
Add device nodes for this display pipeline.
Signed-off-by: Icenowy Zheng
---
Changes in v8:
- Changed some label names.
Changes in v7:
- Change DE2 clock compatible to V3s one.
- Mention only one TCON in commit message.
- Changed commit brief.
arch/arm/boot/dts/sun8i-v3s.dtsi | 87
1 file changed, 87 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 71075969e5e6..e47a9b29f55c 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -41,6 +41,10 @@
*/
#include
+#include
+#include
+#include
+#include
/ {
#address-cells = <1>;
@@ -59,6 +63,12 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun8i-v3s-display-engine";
+ allwinner,pipelines = <&mixer0>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -93,6 +103,83 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock@100 {
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_DE>,
+<&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@110 {
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <&display_clocks CLK_MIXER0>,
+<&display_clocks CLK_BUS_MIXER0>;
+ clock-names = "mod",
+ "bus";
+ resets = <&display_clocks RST_MIXER0>;
+ assigned-clocks = <&display_clocks CLK_MIXER0>;
+ assigned-clock-rates = <15000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
--
2.12.2
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Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt
On Tue, 2017-05-16 at 17:39 -0700, Puthikorn Voravootivat wrote: > > > On Tue, May 16, 2017 at 2:21 PM, Pandiyan, Dhinakaran > wrote: > On Tue, 2017-05-16 at 13:56 -0700, Puthikorn Voravootivat > wrote: > > > > > > On Tue, May 16, 2017 at 1:29 PM, Pandiyan, Dhinakaran > > wrote: > > On Tue, 2017-05-16 at 11:07 -0700, Puthikorn > Voravootivat > > wrote: > > > > > > > > > On Mon, May 15, 2017 at 11:21 PM, Pandiyan, > Dhinakaran > > > wrote: > > > On Mon, 2017-05-15 at 17:43 -0700, > Puthikorn > > Voravootivat > > > wrote: > > > > > > > > > > > > On Mon, May 15, 2017 at 4:07 PM, > Pandiyan, > > Dhinakaran > > > > wrote: > > > > On Fri, 2017-05-12 at 17:31 > -0700, > > Puthikorn > > > Voravootivat > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Fri, May 12, 2017 at 5:12 > PM, > > Pandiyan, > > > Dhinakaran > > > > > > wrote: > > > > > On Thu, 2017-05-11 at > 16:02 > > -0700, > > > Puthikorn > > > > Voravootivat > > > > > wrote: > > > > > > Read desired PWM > frequency > > from panel > > > vbt and > > > > calculate the > > > > > > value for divider in > DPCD > > address 0x724 > > > and 0x728 > > > > to have > > > > > > as many bits as > possible for > > PWM duty > > > cyle for > > > > granularity > > > > > of > > > > > > brightness > adjustment while > > the > > > frequency is still > > > > within > > > > > 25% > > > > > > of the desired > frequency. > > > > > > > > > > I read a few eDP panel > data > > sheets, the > > > PWM > > > > frequencies all > > > > > start from > > > > > ~200Hz. If the VBT > chooses this > > lowest > > > value to > > > > allow for more > > > > > brightness control, > and then > > this patch > > > lowers the > > > > value by > > > > > another 25%, > > > > > we'll end up below the > panel > > allowed PWM > > > frequency. > > > > > > > > > > In fact, one of the > systems I > > checked had > > > PWM > > > > frequency as > > > > > 200Hz in VBT > > > > > and the panel > datasheet also had > > PWM > > > frequency range > > > > starting > > > > > from > > > > > 200Hz. Have you > considered this > > case? > > > > > > > > > > The spec said "A given LCD > panel > > typically has a > > > limited > > > > range of > > > > > backlight frequency > capability. > > > > > To limit the programmable > frequency > > range, > > > limitations are > >
Re: [Intel-gfx] [PATCH v7 9/9] drm/i915: Set PWM divider to match desired frequency in vbt
On Mon, May 15, 2017 at 11:21 PM, Pandiyan, Dhinakaran <
dhinakaran.pandi...@intel.com> wrote:
> On Mon, 2017-05-15 at 17:43 -0700, Puthikorn Voravootivat wrote:
> >
> >
> > On Mon, May 15, 2017 at 4:07 PM, Pandiyan, Dhinakaran
> > wrote:
> > On Fri, 2017-05-12 at 17:31 -0700, Puthikorn Voravootivat
> > wrote:
> > >
> > >
> > >
> > > On Fri, May 12, 2017 at 5:12 PM, Pandiyan, Dhinakaran
> > > wrote:
> > > On Thu, 2017-05-11 at 16:02 -0700, Puthikorn
> > Voravootivat
> > > wrote:
> > > > Read desired PWM frequency from panel vbt and
> > calculate the
> > > > value for divider in DPCD address 0x724 and 0x728
> > to have
> > > > as many bits as possible for PWM duty cyle for
> > granularity
> > > of
> > > > brightness adjustment while the frequency is still
> > within
> > > 25%
> > > > of the desired frequency.
> > >
> > > I read a few eDP panel data sheets, the PWM
> > frequencies all
> > > start from
> > > ~200Hz. If the VBT chooses this lowest value to
> > allow for more
> > > brightness control, and then this patch lowers the
> > value by
> > > another 25%,
> > > we'll end up below the panel allowed PWM frequency.
> > >
> > > In fact, one of the systems I checked had PWM
> > frequency as
> > > 200Hz in VBT
> > > and the panel datasheet also had PWM frequency range
> > starting
> > > from
> > > 200Hz. Have you considered this case?
> > >
> > > The spec said "A given LCD panel typically has a limited
> > range of
> > > backlight frequency capability.
> > > To limit the programmable frequency range, limitations are
> > placed on
> > > the allowable total divider ratio with the Sink device"
> > > So I think it should be auto cap to 200Hz in this case.
> > >
> > > -DK
> > > >
> > > > Signed-off-by: Puthikorn Voravootivat
> >
> > > > ---
> > > > drivers/gpu/drm/i915/intel_dp_aux_backlight.c |
> > 81
> > > +++
> > > > 1 file changed, 81 insertions(+)
> > > >
> > > > diff --git
> > a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > > index 0b48851013cc..6f10a2f1ab76 100644
> > > > ---
> > a/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > > +++
> > b/drivers/gpu/drm/i915/intel_dp_aux_backlight.c
> > > > @@ -113,12 +113,86 @@
> > > intel_dp_aux_set_dynamic_backlight_percent(struct
> > intel_dp
> > > *intel_dp,
> > > > }
> > > > }
> > > >
> > > > +/*
> > > > + * Set PWM Frequency divider to match desired
> > frequency in
> > > vbt.
> > > > + * The PWM Frequency is calculated as 27Mhz / (F
> > x P).
> > > > + * - Where F = PWM Frequency Pre-Divider value
> > programmed
> > > by field 7:0 of the
> > > > + * EDP_BACKLIGHT_FREQ_SET register
> > (DPCD
> > > Address 00728h)
> > > > + * - Where P = 2^Pn, where Pn is the value
> > programmed by
> > > field 4:0 of the
> > > > + * EDP_PWMGEN_BIT_COUNT register
> > (DPCD Address
> > > 00724h)
> > > > + */
> > > > +static void intel_dp_aux_set_pwm_freq(struct
> > > intel_connector *connector)
> > > > +{
> > > > + struct drm_i915_private *dev_priv =
> > > to_i915(connector->base.dev);
> > > > + struct intel_dp *intel_dp =
> > > enc_to_intel_dp(&connector->encoder->base);
> > > > + int freq, fxp, fxp_min, fxp_max, fxp_actual,
> > f = 1;
> > > > + u8 pn, pn_min, pn_max;
> > > > +
> > > > + /* Find desired value of (F x P)
> > > > + * Note that, if F x P is out of supported
> > range, the
> > > maximum value or
> > > > + * minimum value will applied automatically.
> > So no
> > > need to check that.
> > > > + */
> >
Re: [PATCH v7 11/13] ARM: sun8i: v3s: add device nodes for DE2 display pipeline
在 2017-05-15 17:24，Maxime Ripard 写道：
On Mon, May 15, 2017 at 12:30:43AM +0800, Icenowy Zheng wrote:
+ de2_clocks: clock@100 {
display_clocks would be better there, we don't have to dissociate de1
with de2
How about de_clocks ? (See A80 DTSI)
+ compatible = "allwinner,sun8i-v3s-de2-clk";
+ reg = <0x0100 0x10>;
+ clocks = <&ccu CLK_DE>,
+<&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ de2_mixer0: mixer@110 {
and mixer0 here is enough too.
Is there several of them? Why not just use mixer if there's only one?
Nope, here it's tagged 0 only for consistency with other SoCs.
+ compatible = "allwinner,sun8i-v3s-de2-mixer";
+ reg = <0x0110 0x10>;
+ clocks = <&de2_clocks CLK_MIXER0>,
+<&de2_clocks CLK_BUS_MIXER0>;
+ clock-names = "mod",
+ "bus";
+ resets = <&de2_clocks RST_MIXER0>;
+ assigned-clocks = <&de2_clocks CLK_MIXER0>;
+ assigned-clock-rates = <15000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun8i-v3s-tcon";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = <&ccu CLK_BUS_TCON0>,
+<&ccu CLK_TCON0>;
+ clock-names = "ahb",
+ "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>;
+ reset-names = "lcd";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint =
<&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+
You have an extra new line here.
Maxime
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