[Bug 194731] drm general protection fault in drm_atomic_init

[bugzilla-daemon]

https://bugzilla.kernel.org/show_bug.cgi?id=194731

--- Comment #7 from Janpieter Sollie (janpieter.sol...@dommel.be) ---
hello, I have some other news about this bug (if anyone is still interested):
I rewrote the amdgpu-pro driver, as the amdgpu driver seems more complex, and I
took one step forward! this is my solution:
- unload the Cape Verde card with echo 1 > /proc/sys/pci/:41:00.0/remove
- load the driver, the driver loading finishes successfully
- rescan the pci bus: echo 1 > /sys/bus/pci/rescan
then the behaviour of amdgpu and amdgpu-pro are the same: the system reboots
after initialisation, even if I order it not to restart on panic.
can somebody tell me where I should look for Cape Verde initialization code in
the in-tree driver? I may be able to fix the initialization bug.

Thank you

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[PATCH 7/15] dt-bindings: display: sun4i: Add allwinner, tcon-channel property

[Maxime Ripard]

The Allwinner Timings Controller has two, mutually exclusive, channels.
When the binding has been introduced, it was assumed that there would be
only a single user per channel in the system.

While this is likely for the channel 0 which only connects to LCD displays,
it turns out that the channel 1 can be connected to multiple controllers in
the SoC (HDMI and TV encoders for example). And while the simultaneous use
of HDMI and TV outputs cannot be achieved, switching from one to the other
at runtime definitely sounds plausible.

Add an extra property, allwinner,tcon-channel, to specify for a given
endpoint which TCON channel it is connected to, while falling back to the
previous mechanism if that property is missing.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 11 ---
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 4b280672658e..18d445723c3e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -68,10 +68,13 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoint, the second one the output
 
-  The output should have two endpoints. The first is the block
-  connected to the TCON channel 0 (usually a panel or a bridge), the
-  second the block connected to the TCON channel 1 (usually the TV
-  encoder)
+  The output may have multiple endpoints. The TCON has two channels,
+  usually with the first channel being used for the panels interfaces
+  (RGB, LVDS, etc.), and the second being used for the outputs that
+  require another controller (TV Encoder, HDMI, etc.). The endpoints
+  will take an extra property, allwinner,tcon-channel, to specify the
+  channel the endpoint is associated to. If that property is not
+  present, the endpoint number will be used as the channel number.
 
 On SoCs other than the A33, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-- 
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[PATCH 5/15] clk: sunxi-ng: sun5i: Export video PLLs

[Maxime Ripard]

The video PLLs are used directly by the HDMI controller. Export them so
that we can use them in our DT node.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/sunxi-ng/ccu-sun5i.h  | 6 --
 include/dt-bindings/clock/sun5i-ccu.h | 3 +++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.h b/drivers/clk/sunxi-ng/ccu-sun5i.h
index 8144487eb7ca..16f7aa92957e 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.h
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.h
@@ -28,15 +28,17 @@
 #define CLK_PLL_AUDIO_4X   6
 #define CLK_PLL_AUDIO_8X   7
 #define CLK_PLL_VIDEO0 8
-#define CLK_PLL_VIDEO0_2X  9
+
+/* The PLL_VIDEO0_2X is exported for HDMI */
+
 #define CLK_PLL_VE 10
 #define CLK_PLL_DDR_BASE   11
 #define CLK_PLL_DDR12
 #define CLK_PLL_DDR_OTHER  13
 #define CLK_PLL_PERIPH 14
 #define CLK_PLL_VIDEO1 15
-#define CLK_PLL_VIDEO1_2X  16
 
+/* The PLL_VIDEO0_2X is exported for HDMI */
 /* The CPU clock is exported */
 
 #define CLK_AXI18
diff --git a/include/dt-bindings/clock/sun5i-ccu.h 
b/include/dt-bindings/clock/sun5i-ccu.h
index aeb2e2f781fb..81f34d477aeb 100644
--- a/include/dt-bindings/clock/sun5i-ccu.h
+++ b/include/dt-bindings/clock/sun5i-ccu.h
@@ -19,6 +19,9 @@
 
 #define CLK_HOSC   1
 
+#define CLK_PLL_VIDEO0_2X  9
+
+#define CLK_PLL_VIDEO1_2X  16
 #define CLK_CPU17
 
 #define CLK_AHB_OTG23
-- 
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[PATCH 1/15] clk: divider: Make divider_round_rate take the parent clock

[Maxime Ripard]

So far, divider_round_rate only considers the parent clock returned by
clk_hw_get_parent.

This works fine on clocks that have a single parents, this doesn't work on
muxes, since we will only consider the first parent, while other parents
may totally be able to provide a better combination.

Clocks in that case cannot use divider_round_rate, so would have to come up
with a very similar logic to work around it. Instead of having to do
something like this, and duplicate that logic everywhere, give an
additional parameter for the parent clock to consider.

Current users have been converted using the following coccinelle script

@@
identifier hw, rate, prate, table, width, flags;
@@

-long divider_round_rate(struct clk_hw *hw,
+long divider_round_rate(struct clk_hw *hw, struct clk_hw *parent,
unsigned long rate,
unsigned long *prate,
const struct clk_div_table *table,
u8 width,
unsigned long flags) { ... }

@@
identifier fn, hw;
expression E2, E3, E4, E5, E6;
@@
 fn (struct clk_hw *hw, ...) {
 <...
-divider_round_rate(hw, E2, E3, E4, E5, E6)
+divider_round_rate(hw, clk_hw_get_parent(hw), E2, E3, E4, E5, E6)
 ...>
}

Signed-off-by: Maxime Ripard 
Cc: Carlo Caione 
Cc: Kevin Hilman 
Cc: Vladimir Zapolskiy 
Cc: Sylvain Lemieux 
Cc: Andy Gross 
Cc: David Brown 
Cc: Alessandro Zummo 
Cc: Alexandre Belloni 
Cc: linux-amlo...@lists.infradead.org
Cc: linux-arm-...@vger.kernel.org
Cc: linux-...@vger.kernel.org
Cc: rtc-li...@googlegroups.com
---
 drivers/clk/clk-divider.c | 18 ++
 drivers/clk/hisilicon/clkdivider-hi6220.c |  5 +++--
 drivers/clk/meson/clk-cpu.c   |  5 +++--
 drivers/clk/nxp/clk-lpc32xx.c |  5 +++--
 drivers/clk/qcom/clk-alpha-pll.c  |  5 +++--
 drivers/clk/qcom/clk-regmap-divider.c |  3 ++-
 drivers/clk/sunxi-ng/ccu_div.c|  6 +++---
 drivers/rtc/rtc-ac100.c   |  6 --
 include/linux/clk-provider.h  |  5 +++--
 9 files changed, 34 insertions(+), 24 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 96386ffc8483..d8d7dc84956a 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -275,7 +275,8 @@ static int _next_div(const struct clk_div_table *table, int 
div,
return div;
 }
 
-static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
+static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
+  unsigned long rate,
   unsigned long *best_parent_rate,
   const struct clk_div_table *table, u8 width,
   unsigned long flags)
@@ -314,8 +315,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned 
long rate,
*best_parent_rate = parent_rate_saved;
return i;
}
-   parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-  rate * i);
+   parent_rate = clk_hw_round_rate(parent, rate * i);
now = DIV_ROUND_UP_ULL((u64)parent_rate, i);
if (_is_best_div(rate, now, best, flags)) {
bestdiv = i;
@@ -326,19 +326,20 @@ static int clk_divider_bestdiv(struct clk_hw *hw, 
unsigned long rate,
 
if (!bestdiv) {
bestdiv = _get_maxdiv(table, width, flags);
-   *best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), 1);
+   *best_parent_rate = clk_hw_round_rate(parent, 1);
}
 
return bestdiv;
 }
 
-long divider_round_rate(struct clk_hw *hw, unsigned long rate,
+long divider_round_rate(struct clk_hw *hw, struct clk_hw *parent,
+   unsigned long rate,
unsigned long *prate, const struct clk_div_table *table,
u8 width, unsigned long flags)
 {
int div;
 
-   div = clk_divider_bestdiv(hw, rate, prate, table, width, flags);
+   div = clk_divider_bestdiv(hw, parent, rate, prate, table, width, flags);
 
return DIV_ROUND_UP_ULL((u64)*prate, div);
 }
@@ -359,8 +360,9 @@ static long clk_divider_round_rate(struct clk_hw *hw, 
unsigned long rate,
return DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
}
 
-   return divider_round_rate(hw, rate, prate, divider->table,
- divider->width, divider->flags);
+   return divider_round_rate(hw, clk_hw_get_parent(hw), rate, prate,
+ divider->table, divider->width,
+ divider->flags);
 }
 
 int divider_get_val(unsigned long rate, unsigned long parent_rate,
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c 
b/drivers/clk/hisilicon/clkdivider-hi6220.c
index a1c1f684ad58..deaa72902555 100644
--- a/drivers/clk/hisil

[PATCH 4/15] clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT

[Maxime Ripard]

The current code only rely on the parent to change its rate in the case
where CLK_SET_RATE_PARENT is set.

However, some clock rates might be obtained only through a modification of
the parent and the clock divider. Just rely on the round rate of the clocks
to give us the best computation that might be achieved for a given rate.

round_rate functions now need to honor CLK_SET_RATE_PARENT, but either the
functions already do that if they modify the parent, or don't modify the
praents at all.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/sunxi-ng/ccu_mux.c | 14 +-
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index bae735e252b6..58b6e349a0ed 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -95,19 +95,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
if (!parent)
continue;
 
-   if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
-   struct clk_rate_request parent_req = *req;
-   int ret = __clk_determine_rate(parent, &parent_req);
-
-   if (ret)
-   continue;
-
-   parent_rate = parent_req.rate;
-   } else {
-   parent_rate = clk_hw_get_rate(parent);
-   }
-
-   adj_parent_rate = parent_rate;
+   adj_parent_rate = parent_rate = clk_hw_get_rate(parent);
ccu_mux_helper_adjust_parent_for_prediv(common, cm, i,
&adj_parent_rate);
 
-- 
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[PATCH 3/15] clk: sunxi-ng: div: Switch to divider_round_rate

[Maxime Ripard]

divider_round_rate already evaluates changing the parent rate if
CLK_SET_RATE_PARENT is set. Now that we can do that on muxes too, let's
just use it.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/sunxi-ng/ccu_div.c | 25 ++---
 1 file changed, 2 insertions(+), 23 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 7f8b06e38636..0ccdd3dcc20c 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -20,18 +20,9 @@ static unsigned long ccu_div_round_rate(struct 
ccu_mux_internal *mux,
void *data)
 {
struct ccu_div *cd = data;
-   unsigned long val;
-
-   /*
-* We can't use divider_round_rate that assumes that there's
-* several parents, while we might be called to evaluate
-* several different parents.
-*/
-   val = divider_get_val(rate, *parent_rate, cd->div.table, cd->div.width,
- cd->div.flags);
 
-   return divider_recalc_rate(&cd->common.hw, *parent_rate, val,
-  cd->div.table, cd->div.flags);
+   return divider_round_rate(&cd->common.hw, parent, rate, parent_rate,
+ cd->div.table, cd->div.width, cd->div.flags);
 }
 
 static void ccu_div_disable(struct clk_hw *hw)
@@ -78,18 +69,6 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
 {
struct ccu_div *cd = hw_to_ccu_div(hw);
 
-   if (clk_hw_get_num_parents(hw) == 1) {
-   req->rate = divider_round_rate(hw, clk_hw_get_parent(hw),
-  req->rate,
-  &req->best_parent_rate,
-  cd->div.table, cd->div.width,
-  cd->div.flags);
-
-   req->best_parent_hw = clk_hw_get_parent(hw);
-
-   return 0;
-   }
-
return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
 req, ccu_div_round_rate, cd);
 }
-- 
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[PATCH 6/15] dt-bindings: display: sun4i: Add HDMI display bindings

[Maxime Ripard]

One of the possible output of the display pipeline, on the SoCs that have
it, is the HDMI controller.

Add a binding for it.

Signed-off-by: Maxime Ripard 
---
 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 21 +++-
 1 file changed, 21 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index b82c00449468..4b280672658e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -4,6 +4,27 @@ Allwinner A10 Display Pipeline
 The Allwinner A10 Display pipeline is composed of several components
 that are going to be documented below:
 
+HDMI Encoder
+
+
+The HDMI Encoder supports the HDMI video and audio outputs, and does
+CEC. It is one end of the pipeline.
+
+Required properties:
+  - compatible: value must be one of:
+* allwinner,sun5i-a10s-hdmi
+  - reg: base address and size of memory-mapped region
+  - clocks: phandles to the clocks feeding the HDMI encoder
+* ahb: the HDMI interface clock
+* mod: the HDMI module clock
+* pll-0: the first video PLL
+* pll-1: the second video PLL
+  - clock-names: the clock names mentioned above
+
+  - ports: A ports node with endpoint definitions as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt. The
+first port should be the input endpoint.
+
 TV Encoder
 --
 
-- 
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[PATCH 0/15] drm: sun4i: Add support for the HDMI controller

[Maxime Ripard]

Hi,

Here is an attempt at getting the HDMI controller running.

This HDMI controller is found on a number of old Allwinner SoCs (A10, A10s,
A20, A31).

This driver only supports for now the A10s because it was an easy target,
being very close to the A13 that is already supported by our DRM driver.

There's nothing out of the extraordinary there, except maybe the clock
setup. All the internal clocks (TMDS, DDC) have been modeled using the
common clock framework, the TMDS clock being the parent of the DDC one.

While this might sound overkill, other SoC have a different, external
source for the DDC clock, which will be easier to support through the clock
framework.

It's still a bit rough around the edges, as it doesn't work for all the
modes. This will need to be fixed before being merged obviously.

The IP also supports audio (through an already supported i2s controller,
and some missing configuration in the HDMI controller) and CEC. Both will
come eventually.

Let me know what you think!
Maxime

Maxime Ripard (15):
  clk: divider: Make divider_round_rate take the parent clock
  clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate
  clk: sunxi-ng: div: Switch to divider_round_rate
  clk: sunxi-ng: mux: Don't just rely on the parent for CLK_SET_RATE_PARENT
  clk: sunxi-ng: sun5i: Export video PLLs
  dt-bindings: display: sun4i: Add HDMI display bindings
  dt-bindings: display: sun4i: Add allwinner,tcon-channel property
  drm/sun4i: tcon: Add channel debug
  drm/sun4i: tcon: Pass the encoder to the mode set functions
  drm/sun4i: tcon: Switch mux on only for composite
  drm/sun4i: tcon: Fix tcon channel 1 backporch calculation
  drm/sun4i: tcon: multiply the vtotal when not in interlace
  drm/sun4i: Add HDMI support
  ARM: sun5i: a10s: Add the HDMI controller node
  ARM: sun5i: a10s-olinuxino: Enable HDMI

 Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt |  32 +-
 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts  |  12 +-
 arch/arm/boot/dts/sun5i-a10s.dtsi |  34 +-
 arch/arm/boot/dts/sun5i.dtsi  |   1 +-
 drivers/clk/clk-divider.c |  18 +-
 drivers/clk/hisilicon/clkdivider-hi6220.c |   5 +-
 drivers/clk/meson/clk-cpu.c   |   5 +-
 drivers/clk/nxp/clk-lpc32xx.c |   5 +-
 drivers/clk/qcom/clk-alpha-pll.c  |   5 +-
 drivers/clk/qcom/clk-regmap-divider.c |   3 +-
 drivers/clk/sunxi-ng/ccu-sun5i.h  |   6 +-
 drivers/clk/sunxi-ng/ccu_div.c|  28 +-
 drivers/clk/sunxi-ng/ccu_mp.c |   7 +-
 drivers/clk/sunxi-ng/ccu_mult.c   |  11 +-
 drivers/clk/sunxi-ng/ccu_mux.c|  22 +-
 drivers/clk/sunxi-ng/ccu_mux.h|   3 +-
 drivers/clk/sunxi-ng/ccu_nkm.c|   7 +-
 drivers/gpu/drm/sun4i/Makefile|   5 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h| 124 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c| 128 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c| 449 +++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c   | 236 -
 drivers/gpu/drm/sun4i/sun4i_rgb.c |   2 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c|  25 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.h|   4 +-
 drivers/gpu/drm/sun4i/sun4i_tv.c  |   2 +-
 drivers/rtc/rtc-ac100.c   |   6 +-
 include/dt-bindings/clock/sun5i-ccu.h |   3 +-
 include/linux/clk-provider.h  |   5 +-
 29 files changed, 1103 insertions(+), 90 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c

base-commit: d1bee31b9da7222c6be3248d1f3b087e8cc9004c
-- 
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[PATCH 11/15] drm/sun4i: tcon: Fix tcon channel 1 backporch calculation

[Maxime Ripard]

It seems like what's called a backporch in the datasheet is actually the
backporch plus the sync period. Fix that in our driver.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 93249c5ab1e4..e44217fb4f6f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -240,15 +240,14 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, struct 
drm_encoder *encoder,
 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
 
/* Set horizontal display timings */
-   bp = mode->crtc_htotal - mode->crtc_hsync_end;
+   bp = mode->crtc_htotal - mode->crtc_hsync_start;
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
 mode->htotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 
-   /* Set vertical display timings */
-   bp = mode->crtc_vtotal - mode->crtc_vsync_end;
+   bp = mode->crtc_vtotal - mode->crtc_vsync_start;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 mode->vtotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
-- 
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[PATCH 10/15] drm/sun4i: tcon: Switch mux on only for composite

[Maxime Ripard]

Even though that mux is undocumented, it seems like it needs to be set to 1
when using composite, and 0 when using HDMI.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d2335f109601..93249c5ab1e4 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -268,11 +268,16 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, struct 
drm_encoder *encoder,
   SUN4I_TCON_GCTL_IOMAP_MASK,
   SUN4I_TCON_GCTL_IOMAP_TCON1);
 
+   if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
+   val = 1;
+   else
+   val = 0;
+
/*
 * FIXME: Undocumented bits
 */
if (tcon->quirks->has_unknown_mux)
-   regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, 1);
+   regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
 }
 EXPORT_SYMBOL(sun4i_tcon1_mode_set);
 
-- 
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[PATCH 8/15] drm/sun4i: tcon: Add channel debug

[Maxime Ripard]

While all functions have debug logs, the channel enable and disable are not
logged. Make sure this is the case.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 
 1 file changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 505520baa585..7461ae107e54 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -55,6 +55,8 @@ EXPORT_SYMBOL(sun4i_tcon_enable);
 
 void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
 {
+   DRM_DEBUG_DRIVER("Disabling TCON channel %d\n", channel);
+
/* Disable the TCON's channel */
if (channel == 0) {
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
@@ -72,6 +74,8 @@ EXPORT_SYMBOL(sun4i_tcon_channel_disable);
 
 void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
 {
+   DRM_DEBUG_DRIVER("Enabling TCON channel %d\n", channel);
+
/* Enable the TCON's channel */
if (channel == 0) {
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
-- 
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[PATCH 12/15] drm/sun4i: tcon: multiply the vtotal when not in interlace

[Maxime Ripard]

It appears that the total vertical resolution needs to be doubled when
we're not in interlaced. Make sure that is the case.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index e44217fb4f6f..515fa56c1e6a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -248,10 +248,13 @@ void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, struct 
drm_encoder *encoder,
 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
 
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
+   val = mode->crtc_vtotal;
+   if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
+   val = val * 2;
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
 mode->vtotal, bp);
regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
-SUN4I_TCON1_BASIC4_V_TOTAL(mode->vtotal) |
+SUN4I_TCON1_BASIC4_V_TOTAL(val) |
 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
 
/* Set Hsync and Vsync length */
-- 
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[PATCH 14/15] ARM: sun5i: a10s: Add the HDMI controller node

[Maxime Ripard]

The A10s has an HDMI controller connected to the second TCON channel. Add
it to our DT.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 34 -
 arch/arm/boot/dts/sun5i.dtsi  |  1 +-
 2 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi 
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 074485782a4a..3482c9d2b120 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -72,7 +72,33 @@
};
};
 
+   display-engine {
+   compatible = "allwinner,sun5i-a10s-display-engine",
+"allwinner,sun5i-a13-display-engine";
+   allwinner,pipelines = <&fe0>;
+   };
+
soc@01c0 {
+   hdmi0: hdmi@01c16000 {
+   compatible = "allwinner,sun5i-a10s-hdmi";
+   reg = <0x01c16000 0x1000>;
+   clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
+<&ccu CLK_PLL_VIDEO0_2X>,
+<&ccu CLK_PLL_VIDEO1_2X>;
+   clock-names = "ahb", "mod", "pll-0", "pll-1";
+   status = "disabled";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   hdmi0_in_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&tcon0_out_hdmi0>;
+   };
+   };
+   };
+
pwm: pwm@01c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -129,3 +155,11 @@
 
 &sram_a {
 };
+
+&tcon0_out {
+   tcon0_out_hdmi0: endpoint@2 {
+   reg = <2>;
+   remote-endpoint = <&hdmi0_in_tcon0>;
+   allwinner,tcon-channel = <1>;
+   };
+};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index f3b6e19244f9..3d009b2aa42a 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -273,6 +273,7 @@
tcon0_out_tve0: endpoint@1 {
reg = <1>;
remote-endpoint = 
<&tve0_in_tcon0>;
+   allwinner,tcon-channel = <1>;
};
};
};
-- 
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[PATCH 13/15] drm/sun4i: Add HDMI support

[Maxime Ripard]

The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
controller.

That HDMI controller is able to do audio and CEC, but those have been left
out for now.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/Makefile  |   5 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi.h  | 124 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c  | 128 ++-
 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c  | 449 +-
 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 236 +++-
 5 files changed, 942 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi.h
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
 create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c

diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 59b757350a1f..68a0f6244a59 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -7,7 +7,12 @@ sun4i-tcon-y += sun4i_dotclock.o
 sun4i-tcon-y += sun4i_crtc.o
 sun4i-tcon-y += sun4i_layer.o
 
+sun4i-drm-hdmi-y += sun4i_hdmi_enc.o
+sun4i-drm-hdmi-y += sun4i_hdmi_ddc_clk.o
+sun4i-drm-hdmi-y += sun4i_hdmi_tmds_clk.o
+
 obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm.o sun4i-tcon.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_backend.o
 obj-$(CONFIG_DRM_SUN4I)+= sun6i_drc.o
+obj-$(CONFIG_DRM_SUN4I)+= sun4i-drm-hdmi.o
 obj-$(CONFIG_DRM_SUN4I)+= sun4i_tv.o
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h 
b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
new file mode 100644
index ..2ad25b8fd3cd
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard
+ *
+ * Maxime Ripard 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef _SUN4I_HDMI_H_
+#define _SUN4I_HDMI_H_
+
+#include 
+#include 
+
+#define SUN4I_HDMI_CTRL_REG0x004
+#define SUN4I_HDMI_CTRL_ENABLE BIT(31)
+
+#define SUN4I_HDMI_IRQ_REG 0x008
+#define SUN4I_HDMI_IRQ_STA_MASK0x73
+#define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1)
+#define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
+
+#define SUN4I_HDMI_HPD_REG 0x00c
+#define SUN4I_HDMI_HPD_HIGHBIT(0)
+
+#define SUN4I_HDMI_VID_CTRL_REG0x010
+#define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31)
+#define SUN4I_HDMI_VID_CTRL_HDMI_MODE  BIT(30)
+
+#define SUN4I_HDMI_VID_TIMING_ACT_REG  0x014
+#define SUN4I_HDMI_VID_TIMING_BP_REG   0x018
+#define SUN4I_HDMI_VID_TIMING_FP_REG   0x01c
+#define SUN4I_HDMI_VID_TIMING_SPW_REG  0x020
+
+#define SUN4I_HDMI_VID_TIMING_X(x) x) - 1) & GENMASK(11, 0)))
+#define SUN4I_HDMI_VID_TIMING_Y(y) y) - 1) & GENMASK(11, 0)) 
<< 16)
+
+#define SUN4I_HDMI_VID_TIMING_POL_REG  0x024
+#define SUN4I_HDMI_VID_TIMING_POL_TX_CLK(0x3e0 << 16)
+#define SUN4I_HDMI_VID_TIMING_POL_VSYNCBIT(1)
+#define SUN4I_HDMI_VID_TIMING_POL_HSYNCBIT(0)
+
+#define SUN4I_HDMI_AVI_INFOFRAME_REG(n)(0x080 + (n))
+
+#define SUN4I_HDMI_PAD_CTRL0_REG   0x200
+
+#define SUN4I_HDMI_PAD_CTRL1_REG   0x204
+#define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6)
+
+#define SUN4I_HDMI_PLL_CTRL_REG0x208
+#define SUN4I_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
+#define SUN4I_HDMI_PLL_CTRL_DIV_MASK   GENMASK(7, 4)
+
+#define SUN4I_HDMI_PLL_DBG0_REG0x20c
+#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21)
+#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK   BIT(21)
+#define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT  21
+
+#define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
+#define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4))
+
+#define SUN4I_HDMI_UNKNOWN_REG 0x300
+#define SUN4I_HDMI_UNKNOWN_INPUT_SYNC  BIT(27)
+
+#define SUN4I_HDMI_DDC_CTRL_REG0x500
+#define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31)
+#define SUN4I_HDMI_DDC_CTRL_START_CMD  BIT(30)
+#define SUN4I_HDMI_DDC_CTRL_RESET  BIT(0)
+
+#define SUN4I_HDMI_DDC_ADDR_REG0x504
+#define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg)   (((seg) & 0xff) << 24)
+#define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
+#define SUN4I_HDMI_DDC_ADDR_OFFSET(off)(((off) & 0xff) << 8)
+#define SUN4I_HDMI_DDC_ADDR_SLAVE(addr)((addr) & 0xff)
+
+#define SUN4I_HDMI_DDC_FIFO_CTRL_REG   0x510
+#define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31)
+   
+#define SUN4I_HDMI_DDC_FIFO_DATA_REG   0x518
+#define SUN4I_HDMI_DDC_BYTE_COUNT_REG  0x51c
+
+#define SUN4I_HDMI_DDC_

[PATCH 15/15] ARM: sun5i: a10s-olinuxino: Enable HDMI

[Maxime Ripard]

The A10s Olinuxino has an HDMI connector. Make sure we can use it.

Signed-off-by: Maxime Ripard 
---
 arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 12 
 1 file changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts 
b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index baee64d61f6d..3102c27b04df 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -77,6 +77,10 @@
};
 };
 
+&be0 {
+   status = "okay";
+};
+
 &ehci0 {
status = "okay";
 };
@@ -92,6 +96,10 @@
status = "okay";
 };
 
+&hdmi0 {
+   status = "okay";
+};
+
 &i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
@@ -249,6 +257,10 @@
status = "okay";
 };
 
+&tcon0 {
+   status = "okay";
+};
+
 &uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
-- 
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[PATCH 2/15] clk: sunxi-ng: Pass the parent and a pointer to the clocks round rate

[Maxime Ripard]

The clocks might need to modify their parent clocks. In order to make that
possible, give them access to the parent clock being evaluated, and to a
pointer to the parent rate so that they can modify it if needed.

Signed-off-by: Maxime Ripard 
---
 drivers/clk/sunxi-ng/ccu_div.c  |  7 ---
 drivers/clk/sunxi-ng/ccu_mp.c   |  7 ---
 drivers/clk/sunxi-ng/ccu_mult.c | 11 ++-
 drivers/clk/sunxi-ng/ccu_mux.c  |  8 +---
 drivers/clk/sunxi-ng/ccu_mux.h  |  3 ++-
 drivers/clk/sunxi-ng/ccu_nkm.c  |  7 ---
 6 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index 92855c2b30bb..7f8b06e38636 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -14,7 +14,8 @@
 #include "ccu_div.h"
 
 static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
-   unsigned long parent_rate,
+   struct clk_hw *parent,
+   unsigned long *parent_rate,
unsigned long rate,
void *data)
 {
@@ -26,10 +27,10 @@ static unsigned long ccu_div_round_rate(struct 
ccu_mux_internal *mux,
 * several parents, while we might be called to evaluate
 * several different parents.
 */
-   val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
+   val = divider_get_val(rate, *parent_rate, cd->div.table, cd->div.width,
  cd->div.flags);
 
-   return divider_recalc_rate(&cd->common.hw, parent_rate, val,
+   return divider_recalc_rate(&cd->common.hw, *parent_rate, val,
   cd->div.table, cd->div.flags);
 }
 
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index b583f186a804..de02e6c386d8 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -41,7 +41,8 @@ static void ccu_mp_find_best(unsigned long parent, unsigned 
long rate,
 }
 
 static unsigned long ccu_mp_round_rate(struct ccu_mux_internal *mux,
-  unsigned long parent_rate,
+  struct clk_hw *hw,
+  unsigned long *parent_rate,
   unsigned long rate,
   void *data)
 {
@@ -52,9 +53,9 @@ static unsigned long ccu_mp_round_rate(struct 
ccu_mux_internal *mux,
max_m = cmp->m.max ?: 1 << cmp->m.width;
max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
 
-   ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);
+   ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
 
-   return parent_rate / p / m;
+   return *parent_rate / p / m;
 }
 
 static void ccu_mp_disable(struct clk_hw *hw)
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 8724c01171b1..76d17162366f 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -33,9 +33,10 @@ static void ccu_mult_find_best(unsigned long parent, 
unsigned long rate,
 }
 
 static unsigned long ccu_mult_round_rate(struct ccu_mux_internal *mux,
-   unsigned long parent_rate,
-   unsigned long rate,
-   void *data)
+struct clk_hw *parent,
+unsigned long *parent_rate,
+unsigned long rate,
+void *data)
 {
struct ccu_mult *cm = data;
struct _ccu_mult _cm;
@@ -47,9 +48,9 @@ static unsigned long ccu_mult_round_rate(struct 
ccu_mux_internal *mux,
else
_cm.max = (1 << cm->mult.width) + cm->mult.offset - 1;
 
-   ccu_mult_find_best(parent_rate, rate, &_cm);
+   ccu_mult_find_best(*parent_rate, rate, &_cm);
 
-   return parent_rate * _cm.mult;
+   return *parent_rate * _cm.mult;
 }
 
 static void ccu_mult_disable(struct clk_hw *hw)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index c6bb1f523232..bae735e252b6 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -61,7 +61,8 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
  struct ccu_mux_internal *cm,
  struct clk_rate_request *req,
  unsigned long (*round)(struct 
ccu_mux_internal *,
-unsigned long,
+struct clk_hw *,
+unsigned long *,
 unsigned long,
  

[PATCH 9/15] drm/sun4i: tcon: Pass the encoder to the mode set functions

[Maxime Ripard]

The mode set function need some changes based on which encoder is being
used. Make sure we can differentiate between our encoders by passing the
encoder structure asking for the mode set.

Signed-off-by: Maxime Ripard 
---
 drivers/gpu/drm/sun4i/sun4i_rgb.c  | 2 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++--
 drivers/gpu/drm/sun4i/sun4i_tcon.h | 4 ++--
 drivers/gpu/drm/sun4i/sun4i_tv.c   | 2 +-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_rgb.c 
b/drivers/gpu/drm/sun4i/sun4i_rgb.c
index 1147451eb993..1d4a59a44d04 100644
--- a/drivers/gpu/drm/sun4i/sun4i_rgb.c
+++ b/drivers/gpu/drm/sun4i/sun4i_rgb.c
@@ -173,7 +173,7 @@ static void sun4i_rgb_encoder_mode_set(struct drm_encoder 
*encoder,
struct sun4i_rgb *rgb = drm_encoder_to_sun4i_rgb(encoder);
struct sun4i_tcon *tcon = rgb->tcon;
 
-   sun4i_tcon0_mode_set(tcon, mode);
+   sun4i_tcon0_mode_set(tcon, encoder, mode);
 
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c 
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 7461ae107e54..d2335f109601 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -127,7 +127,7 @@ static int sun4i_tcon_get_clk_delay(struct drm_display_mode 
*mode,
return delay;
 }
 
-void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
+void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
  struct drm_display_mode *mode)
 {
unsigned int bp, hsync, vsync;
@@ -200,7 +200,7 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
 }
 EXPORT_SYMBOL(sun4i_tcon0_mode_set);
 
-void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
  struct drm_display_mode *mode)
 {
unsigned int bp, hsync, vsync;
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h 
b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index f636343a935d..95b7e76eb1f8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -190,9 +190,9 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool 
enable);
 /* Mode Related Controls */
 void sun4i_tcon_switch_interlace(struct sun4i_tcon *tcon,
 bool enable);
-void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
+void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
  struct drm_display_mode *mode);
-void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, struct drm_encoder *encoder,
  struct drm_display_mode *mode);
 
 #endif /* __SUN4I_TCON_H__ */
diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
index 32ed5fdf0c4d..2d36df092a6a 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
@@ -389,7 +389,7 @@ static void sun4i_tv_mode_set(struct drm_encoder *encoder,
struct sun4i_tcon *tcon = drv->tcon;
const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
 
-   sun4i_tcon1_mode_set(tcon, mode);
+   sun4i_tcon1_mode_set(tcon, encoder, mode);
 
/* Enable and map the DAC to the output */
regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
-- 
git-series 0.8.11
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Re: [PATCH 3/4] drm/exynos/decon5433: fix vblank event handling

[Inki Dae]

Thanks for fixing it.

Andrzej,
DECON_CRFMID register is new to me. Where did you refer this register 
description from? I couldn't find this register in datasheet I have for 
Exynos5433.

Below are a little bit trivial comments.

2017년 02월 23일 01:05에 Andrzej Hajda 이(가) 쓴 글:
> Current implementation of event handling assumes that vblank interrupt is
> always called at the right time. It is not true, it can be delayed due to
> various reasons. As a result different races can happen. The patch fixes
> the issue by using hardware frame counter present in DECON to serialize
> vblank and commit completion events.
> 
> Signed-off-by: Andrzej Hajda 
> ---
>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 62 
> +--
>  include/video/exynos5433_decon.h  |  9 
>  2 files changed, 67 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 147911e..bfa9396 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -68,6 +68,8 @@ struct decon_context {
>   unsigned long   flags;
>   unsigned long   out_type;
>   int first_win;
> + spinlock_t  vblank_lock;
> + u32 frame_id;
>  };
>  
>  static const uint32_t decon_formats[] = {
> @@ -365,25 +367,32 @@ static void decon_disable_plane(struct exynos_drm_crtc 
> *crtc,
>  static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
>  {
>   struct decon_context *ctx = crtc->ctx;
> + unsigned long flags;
>   int i;
>  
>   if (test_bit(BIT_SUSPENDED, &ctx->flags))
>   return;
>  
> + spin_lock_irqsave(&ctx->vblank_lock, flags);
> +
>   for (i = ctx->first_win; i < WINDOWS_NR; i++)
>   decon_shadow_protect_win(ctx, i, false);
>  
> + if (ctx->out_type & IFTYPE_I80)
> + set_bit(BIT_WIN_UPDATED, &ctx->flags);
> +
>   if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
>   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
>  
> - if (ctx->out_type & IFTYPE_I80)
> - set_bit(BIT_WIN_UPDATED, &ctx->flags);
> - exynos_crtc_handle_event(crtc);
> + exynos_crtc_handle_event(ctx->crtc);

You don't have to change 'crtc' to 'ctx->crtc'. Keep 'crtc'.

> +
> + spin_unlock_irqrestore(&ctx->vblank_lock, flags);
>  }
>  
>  static void decon_swreset(struct decon_context *ctx)
>  {
>   unsigned int tries;
> + unsigned long flags;
>  
>   writel(0, ctx->addr + DECON_VIDCON0);
>   for (tries = 2000; tries; --tries) {
> @@ -401,6 +410,10 @@ static void decon_swreset(struct decon_context *ctx)
>  
>   WARN(tries == 0, "failed to software reset DECON\n");
>  
> + spin_lock_irqsave(&ctx->vblank_lock, flags);
> + ctx->frame_id = 0;
> + spin_unlock_irqrestore(&ctx->vblank_lock, flags);
> +
>   if (!(ctx->out_type & IFTYPE_HDMI))
>   return;
>  
> @@ -579,6 +592,46 @@ static const struct component_ops decon_component_ops = {
>   .unbind = decon_unbind,
>  };
>  
> +static void decon_handle_vblank(struct decon_context *ctx)
> +{
> + u32 frm, pfrm, status, cnt;
> +
> + spin_lock(&ctx->vblank_lock);
> +
> + /* To get consistent result repeat read until frame id is stable. */
> + frm = readl(ctx->addr + DECON_CRFMID);
> + cnt = 3;

Is there some guide that initial value of cnt should be 3?

> + do {
> + status = readl(ctx->addr + DECON_VIDCON1);
> + pfrm = frm;
> + frm = readl(ctx->addr + DECON_CRFMID);
> + } while (frm != pfrm && --cnt);
> +
> + status &= VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE;

I couldn't find I80_ACTIVE field on DECON_VIDCON1 register descrption. Do you 
have other datasheet, new one?

> +
> + /* In case of delayed vblank CRFMID could be already incremented,
> +  * it should be taken into account.
> +  */
> + if (frm > 0)
> + switch (status) {
> + case VIDCON1_VSTATUS_VS:
> + if (ctx->out_type & IFTYPE_I80)
> + break;
> + case VIDCON1_I80_ACTIVE:
> + case VIDCON1_VSTATUS_BP:
> + case VIDCON1_VSTATUS_AC:
> + --frm;

Let's add 'break;' and 'default: break;' explicitly.

> + }
> +
> + if (frm != ctx->frame_id) {
> + if (frm > ctx->frame_id)
> + drm_crtc_handle_vblank(&ctx->crtc->base);
> + ctx->frame_id = frm;
> + }
> +
> + spin_unlock(&ctx->vblank_lock);
> +}
> +
>  static irqreturn_t decon_irq_handler(int irq, void *dev_id)
>  {
>   struct decon_context *ctx = dev_id;
> @@ -599,7 +652,7 @@ static irqreturn_t decon_irq_handler(int irq, void 
> *dev_id)
>   (VIDOUT_INTERLACE_EN_F | VIDOUT_INTE

Re: [PATCH] drm/exynos/decon5433: implement frame counter

[Inki Dae]

2017년 03월 02일 17:35에 Andrzej Hajda 이(가) 쓴 글:
> Decon in Exynos5433 has frame counter, it can be used to implement
> get_vblank_counter callback.
> 
> Signed-off-by: Andrzej Hajda 
> ---
> Hi Inki,
> 
> The patch is based on my last patches, maybe to make it clear I will resend 
> all
> these patches in one patchset, what do you think?

One patch set it better. :)

Thanks.

> 
> Regards
> Andrzej
> 
>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 76 
> ++-
>  drivers/gpu/drm/exynos/exynos_drm_crtc.c  | 11 
>  drivers/gpu/drm/exynos/exynos_drm_drv.h   |  1 +
>  3 files changed, 63 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index 4b596dc..4b5af67 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -123,6 +123,53 @@ static void decon_disable_vblank(struct exynos_drm_crtc 
> *crtc)
>   writel(0, ctx->addr + DECON_VIDINTCON0);
>  }
>  
> +/* return number of starts/ends of frame transmissions since reset */
> +static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
> +{
> + u32 frm, pfrm, status, cnt;
> +
> + /* To get consistent result repeat read until frame id is stable. */
> + frm = readl(ctx->addr + DECON_CRFMID);
> + cnt = 3;
> + do {
> + status = readl(ctx->addr + DECON_VIDCON1);
> + pfrm = frm;
> + frm = readl(ctx->addr + DECON_CRFMID);
> + } while (frm != pfrm && --cnt);
> +
> + /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
> +  * of RGB, it should be taken into account.
> +  */
> + if (!frm)
> + return 0;
> +
> + switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
> + case VIDCON1_VSTATUS_VS:
> + if (!(ctx->out_type & IFTYPE_I80))
> + --frm;
> + break;
> + case VIDCON1_VSTATUS_BP:
> + --frm;
> + break;
> + case VIDCON1_I80_ACTIVE:
> + case VIDCON1_VSTATUS_AC:
> + if (end)
> + --frm;
> + }
> +
> + return frm;
> +}
> +
> +static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
> +{
> + struct decon_context *ctx = crtc->ctx;
> +
> + if (test_bit(BIT_SUSPENDED, &ctx->flags))
> + return 0;
> +
> + return decon_get_frame_count(ctx, false);
> +}
> +
>  static void decon_setup_trigger(struct decon_context *ctx)
>  {
>   if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
> @@ -518,6 +565,7 @@ static const struct exynos_drm_crtc_ops decon_crtc_ops = {
>   .enable = decon_enable,
>   .disable= decon_disable,
>   .enable_vblank  = decon_enable_vblank,
> + .get_vblank_counter = decon_get_vblank_counter,
>   .disable_vblank = decon_disable_vblank,
>   .atomic_begin   = decon_atomic_begin,
>   .update_plane   = decon_update_plane,
> @@ -536,6 +584,7 @@ static int decon_bind(struct device *dev, struct device 
> *master, void *data)
>   int ret;
>  
>   ctx->drm_dev = drm_dev;
> + drm_dev->max_vblank_count = 0x;
>  
>   for (win = ctx->first_win; win < WINDOWS_NR; win++) {
>   int tmp = (win == ctx->first_win) ? 0 : win;
> @@ -581,34 +630,11 @@ static const struct component_ops decon_component_ops = 
> {
>  
>  static void decon_handle_vblank(struct decon_context *ctx)
>  {
> - u32 frm, pfrm, status, cnt;
> + u32 frm;
>  
>   spin_lock(&ctx->vblank_lock);
>  
> - /* To get consistent result repeat read until frame id is stable. */
> - frm = readl(ctx->addr + DECON_CRFMID);
> - cnt = 3;
> - do {
> - status = readl(ctx->addr + DECON_VIDCON1);
> - pfrm = frm;
> - frm = readl(ctx->addr + DECON_CRFMID);
> - } while (frm != pfrm && --cnt);
> -
> - status &= VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE;
> -
> - /* In case of delayed vblank CRFMID could be already incremented,
> -  * it should be taken into account.
> -  */
> - if (frm > 0)
> - switch (status) {
> - case VIDCON1_VSTATUS_VS:
> - if (ctx->out_type & IFTYPE_I80)
> - break;
> - case VIDCON1_I80_ACTIVE:
> - case VIDCON1_VSTATUS_BP:
> - case VIDCON1_VSTATUS_AC:
> - --frm;
> - }
> + frm = decon_get_frame_count(ctx, true);
>  
>   if (frm != ctx->frame_id) {
>   if (frm > ctx->frame_id)
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c 
> b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> index 0c9a775..d72777f 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
> @@ -132,6 +132,16 @@ static void exynos_drm_crtc_disable_vblank

Re: [PATCH 4/4] drm/exynos/decon5433: signal frame done interrupt at VSYNC

[Inki Dae]

2017년 02월 23일 01:05에 Andrzej Hajda 이(가) 쓴 글:
> DECON in case of video mode generates interrupt by default at start
> of vertical back porch. As this interrupt is used to generate VBLANK
> events more optimal point is start of vertical front porch.
> 
> Signed-off-by: Andrzej Hajda 
> ---
>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 2 +-
>  include/video/exynos5433_decon.h  | 4 
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> index bfa9396..2694b32 100644
> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> @@ -105,7 +105,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc 
> *crtc)
>   if (ctx->out_type & IFTYPE_I80)
>   val |= VIDINTCON0_FRAMEDONE;
>   else
> - val |= VIDINTCON0_INTFRMEN;
> + val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
>  
>   writel(val, ctx->addr + DECON_VIDINTCON0);
>   }
> diff --git a/include/video/exynos5433_decon.h 
> b/include/video/exynos5433_decon.h
> index beefc62..2391b03 100644
> --- a/include/video/exynos5433_decon.h
> +++ b/include/video/exynos5433_decon.h
> @@ -128,6 +128,10 @@
>  
>  /* VIDINTCON0 */
>  #define VIDINTCON0_FRAMEDONE (1 << 17)
> +#define VIDINTCON0_FRAMESEL_BP   (0 << 15)
> +#define VIDINTCON0_FRAMESEL_VS   (1 << 15)
> +#define VIDINTCON0_FRAMESEL_AC   (2 << 15)

Above definitions are not used.

Thanks.

> +#define VIDINTCON0_FRAMESEL_FP   (3 << 15)
>  #define VIDINTCON0_INTFRMEN  (1 << 12)
>  #define VIDINTCON0_INTEN (1 << 0)
>  
> 
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Re: [PATCH 3/4] drm/exynos/decon5433: fix vblank event handling

[Andrzej Hajda]

On 07.03.2017 10:12, Inki Dae wrote:
> Thanks for fixing it.
>
> Andrzej,
> DECON_CRFMID register is new to me. Where did you refer this register 
> description from? I couldn't find this register in datasheet I have for 
> Exynos5433.

I have found it in android sources.

>
> Below are a little bit trivial comments.
>
> 2017년 02월 23일 01:05에 Andrzej Hajda 이(가) 쓴 글:
>> Current implementation of event handling assumes that vblank interrupt is
>> always called at the right time. It is not true, it can be delayed due to
>> various reasons. As a result different races can happen. The patch fixes
>> the issue by using hardware frame counter present in DECON to serialize
>> vblank and commit completion events.
>>
>> Signed-off-by: Andrzej Hajda 
>> ---
>>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 62 
>> +--
>>  include/video/exynos5433_decon.h  |  9 
>>  2 files changed, 67 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
>> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> index 147911e..bfa9396 100644
>> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> @@ -68,6 +68,8 @@ struct decon_context {
>>  unsigned long   flags;
>>  unsigned long   out_type;
>>  int first_win;
>> +spinlock_t  vblank_lock;
>> +u32 frame_id;
>>  };
>>  
>>  static const uint32_t decon_formats[] = {
>> @@ -365,25 +367,32 @@ static void decon_disable_plane(struct exynos_drm_crtc 
>> *crtc,
>>  static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
>>  {
>>  struct decon_context *ctx = crtc->ctx;
>> +unsigned long flags;
>>  int i;
>>  
>>  if (test_bit(BIT_SUSPENDED, &ctx->flags))
>>  return;
>>  
>> +spin_lock_irqsave(&ctx->vblank_lock, flags);
>> +
>>  for (i = ctx->first_win; i < WINDOWS_NR; i++)
>>  decon_shadow_protect_win(ctx, i, false);
>>  
>> +if (ctx->out_type & IFTYPE_I80)
>> +set_bit(BIT_WIN_UPDATED, &ctx->flags);
>> +
>>  if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
>>  decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
>>  
>> -if (ctx->out_type & IFTYPE_I80)
>> -set_bit(BIT_WIN_UPDATED, &ctx->flags);
>> -exynos_crtc_handle_event(crtc);
>> +exynos_crtc_handle_event(ctx->crtc);
> You don't have to change 'crtc' to 'ctx->crtc'. Keep 'crtc'.

OK

>
>> +
>> +spin_unlock_irqrestore(&ctx->vblank_lock, flags);
>>  }
>>  
>>  static void decon_swreset(struct decon_context *ctx)
>>  {
>>  unsigned int tries;
>> +unsigned long flags;
>>  
>>  writel(0, ctx->addr + DECON_VIDCON0);
>>  for (tries = 2000; tries; --tries) {
>> @@ -401,6 +410,10 @@ static void decon_swreset(struct decon_context *ctx)
>>  
>>  WARN(tries == 0, "failed to software reset DECON\n");
>>  
>> +spin_lock_irqsave(&ctx->vblank_lock, flags);
>> +ctx->frame_id = 0;
>> +spin_unlock_irqrestore(&ctx->vblank_lock, flags);
>> +
>>  if (!(ctx->out_type & IFTYPE_HDMI))
>>  return;
>>  
>> @@ -579,6 +592,46 @@ static const struct component_ops decon_component_ops = 
>> {
>>  .unbind = decon_unbind,
>>  };
>>  
>> +static void decon_handle_vblank(struct decon_context *ctx)
>> +{
>> +u32 frm, pfrm, status, cnt;
>> +
>> +spin_lock(&ctx->vblank_lock);
>> +
>> +/* To get consistent result repeat read until frame id is stable. */
>> +frm = readl(ctx->addr + DECON_CRFMID);
>> +cnt = 3;
> Is there some guide that initial value of cnt should be 3?

No, this is my arbitrary choice. In general the loop will be passed only
once. In rare case when code runs at frame change time it will be run
twice. It never should run more than two times - it would be sign of HW
error, incorrect DECON programming or serious bottleneck.
I initially left cnt=3 to detect such case, but after all I did not
report such situation, so I can either change cnt to 2, or add error log
if after loop cnt is 0, what do you prefer?

>
>> +do {
>> +status = readl(ctx->addr + DECON_VIDCON1);
>> +pfrm = frm;
>> +frm = readl(ctx->addr + DECON_CRFMID);
>> +} while (frm != pfrm && --cnt);
>> +
>> +status &= VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE;
> I couldn't find I80_ACTIVE field on DECON_VIDCON1 register descrption. Do you 
> have other datasheet, new one?

No, this is just result of my hardware analysis/debugging.

>
>> +
>> +/* In case of delayed vblank CRFMID could be already incremented,
>> + * it should be taken into account.
>> + */
>> +if (frm > 0)
>> +switch (status) {
>> +case VIDCON1_VSTATUS_VS:
>> +if (ctx->out_type & IFTYPE_I80)
>> +break;
>> +case VIDCON1_I80_ACTIVE:
>> +   

Re: [PATCH v7 5/6] drm/i915: enable scrambling

[Ander Conselvan De Oliveira]

On Fri, 2017-03-03 at 21:58 +0530, Shashank Sharma wrote:
> Geminilake platform sports a native HDMI 2.0 controller, and is
> capable of driving pixel-clocks upto 594Mhz. HDMI 2.0 spec
> mendates scrambling for these higher clocks, for reduced RF footprint.
> 
> This patch checks if the monitor supports scrambling, and if required,
> enables it during the modeset.
> 
> V2: Addressed review comments from Ville:
> - Do not track scrambling status in DRM layer, track somewhere in
>   driver like in intel_crtc_state.
> - Don't talk to monitor at such a low layer, set monitor scrambling
>   in intel_enable_ddi() before enabling the port.
> 
> V3: Addressed review comments from Jani
>  - In comments, function names, use "sink" instead of "monitor",
>so that the implementation could be close to the language of
>HDMI spec.
> 
> V4: Addressed review comment from Maarten
>  - scrambling -> hdmi_scrambling
>high_tmds_clock_ratio -> hdmi_high_tmds_clock_ratio
> 
> V5: Addressed review comments from Ville and Ander
>  - Do not modifiy the crtc_state after compute_config. Move all
>scrambling and tmds_clock_ratio calcutations to compute_config.
>  - While setting scrambling for source/sink, do not check the
>conditions again, just go by the crtc_state flags. This will
>simplyfy the condition checks.
> 
> V6: Addressed review comments from Ville
>  - Do not add IS_GLK check in disable/enable function, instead add it
>in compute_config, while setting state flags.
>  - Remove unnecessary paranthesis.
>  - Simplyfy handle_sink_scrambling function as suggested.
>  - Add readout code for scrambling status in get_ddi_config and add a
>check for the same in pipe_config_compare.
> 
> V7: Addressed review comments from Ander/Ville
>  - No separate function for source scrambling, make it inline
>  - Align the last line of the macro TRANS_DDI_HDMI_SCRAMBLING_MASK
>  - Do not add platform check while setting source scrambling
>  - Use pipe_config instead of crtc->config to set sink scrambling
>  - To readout scrambling status, Compare with SCRAMBLING_MASK
>not any of its bits
>  - Remove platform check in intel_pipe_config_compare while checking
>scrambling status
> 
> Signed-off-by: Shashank Sharma 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  7 +
>  drivers/gpu/drm/i915/intel_ddi.c | 33 +++
>  drivers/gpu/drm/i915/intel_display.c |  3 +++
>  drivers/gpu/drm/i915/intel_drv.h | 10 +++
>  drivers/gpu/drm/i915/intel_hdmi.c| 52 
> 
>  5 files changed, 105 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4906ce4d..bfd988b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7824,7 +7824,14 @@ enum {
>  #define  TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
>  #define  TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
>  #define  TRANS_DDI_DP_VC_PAYLOAD_ALLOC   (1<<8)
> +#define  TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1<<7)
> +#define  TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1<<6)
>  #define  TRANS_DDI_BFI_ENABLE(1<<4)
> +#define  TRANS_DDI_HIGH_TMDS_CHAR_RATE   (1<<4)
> +#define  TRANS_DDI_HDMI_SCRAMBLING   (1<<0)
> +#define  TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE 
> \
> + | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
> + | TRANS_DDI_HDMI_SCRAMBLING)
>  
>  /* DisplayPort Transport Control */
>  #define _DP_TP_CTL_A 0x64040
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index a7c08d7..2159b2b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1311,6 +1311,11 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc 
> *crtc)
>   temp |= TRANS_DDI_MODE_SELECT_HDMI;
>   else
>   temp |= TRANS_DDI_MODE_SELECT_DVI;
> +
> + if (intel_crtc->config->hdmi_scrambling)
> + temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
> + if (intel_crtc->config->hdmi_high_tmds_clock_ratio)
> + temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
>   } else if (type == INTEL_OUTPUT_ANALOG) {
>   temp |= TRANS_DDI_MODE_SELECT_FDI;
>   temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
> @@ -1885,6 +1890,20 @@ static void intel_enable_ddi(struct intel_encoder 
> *intel_encoder,
>   struct intel_digital_port *intel_dig_port =
>   enc_to_dig_port(encoder);
>  
> + if (IS_GEMINILAKE(dev_priv)) {
> + /*
> +  * GLK sports a native HDMI 2.0 controller. If required
> +  * clock rate is > 340 Mhz && scrambling is supported
> +  * by sink, enable scrambling before enabling the
> +  * HDMI 2.0 port. The sink can ch

[Bug 93687] ppc64el:Gallium / clover fails to compile

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93687

Andreas Boll  changed:

   What|Removed |Added

 Resolution|NOTOURBUG   |DUPLICATE

--- Comment #6 from Andreas Boll  ---


*** This bug has been marked as a duplicate of bug 68504 ***

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Re: [Intel-gfx] [PATCH v1] drm/i915/bxt: use NULL for GPIO connection ID

[Daniel Vetter]

On Tue, Mar 07, 2017 at 12:48:26PM +0200, Andy Shevchenko wrote:
> On Sun, 2017-02-26 at 22:45 +0100, Daniel Vetter wrote:
> > On Tue, Feb 21, 2017 at 06:52:24PM +0200, Andy Shevchenko wrote:
> > > On Tue, 2017-02-21 at 18:26 +0200, Jani Nikula wrote:
> > > > On Tue, 21 Feb 2017, Andy Shevchenko  > > > l.co
> > > > m> wrote:
> > > > > The commit 213e08ad60ba ("drm/i915/bxt: add bxt dsi gpio element
> > > > > support") enables GPIO support for Broxton based platforms.
> > > > > 
> > > > > While using that API we might get into troubles in the future,
> > > > > because
> > > > > we can't rely on label "panel" in the driver since vendor
> > > > > firmware
> > > > > might
> > > > > provide any GPIO pin there, e.g. "reset", and even mark it in
> > > > > _DSD
> > > > > (in
> > > > > which case the request will fail).
> > > > > 
> > > > > To avoid inconsistency and potential issues we have two options:
> > > > > a) generate GPIO ACPI mapping table and supply it via
> > > > > acpi_dev_add_driver_gpios(), or
> > > > > b) just pass NULL as connection ID.
> > > > > 
> > > > > The b) approach is much simplier and would work since the driver
> > > > > relies
> > > > > on GPIO indeces only. Moreover, the _CRS fallback mechanism,
> > > > > when
> > > > > requesting GPIO, is going to be stricter, and supplying non-NULL
> > > > > connection ID when neither _DSD, nor GPIO ACPI mapping is
> > > > > present,
> > > > > will
> > > > > make request fail.
> > > > 
> > > > The patch version log in the commit suggests otherwise; we'd tried
> > > > and
> > > > failed with NULL,
> > > 
> > > Can I see DSDT excerpts of the platform that fails?
> > > 
> > > >  until Mika realized passing "panel" works:
> > > > 
> > > > v2 by Mika: switch *NULL* to *"panel"* when requesting gpio
> > > > for
> > > > MIPI/DSI
> > > > panel.
> > > > 
> > > > See also [1]. What has changed since then that should make this
> > > > work
> > > > now? We shouldn't apply until we get Tested-by's.
> > > 
> > > Not changed yet, but *going to be*. See my repository here [2].
> > > To fix the mess with GPIO ACPI stuff we are going to make request
> > > stricter as I pointed in commit message above, i.e. asking for a
> > > GPIO by
> > > connection ID without _DSD present will guarantee -ENOENT since it
> > > will
> > > be no fallback to _CRS. You may follow discussion in our internal
> > > mailing list for drivers.
> > 
> > Why exactly is this being discussed on an internal mailing list?
> > Upstream
> > happens in public ...
> 
> It was a prelininary discussion and it's sad you didn't notice it.

The problem isn't that I didn't notice (I don't think I can provide
anything of value here), but that technical discussion should happen in
the open, on public mailing lists, because otherwise we just have a big
coordination chaos. GFX is huge, and just the automatic public archiving
mailing lists provides is super important to get people up to speed when
suddenly you realize you need them.
-Daniel
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[Bug 100058] amdgpu/dpm: NULL pointer dereference

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100058

--- Comment #7 from Adam Wolk  ---
Regarding the display flicking on/off (the effect feels like changing
resolution - the way it goes out and back). This is completely mitigated by
running DRI_PRIME=1 glxgears hence why I thought it might be AMD driver
related.

Regardless, the main thing reported here is a null pointer dereference in the
kernel and a system unable to boot completely.

I can live with the flicker - I just workaround it by running DRI_PRIME=1
glxgears all day...

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Re: [Intel-gfx] Implementing Miracast

[Martin Peres]

On 07/03/17 05:00, Daniel Kasak wrote:

Any news on this? I'm also interested :)

Dan


Hmm, good question! I will ping internally and see if we are ready to 
release something as an RFC.


Martin
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Re: [PATCH 1/15] clk: divider: Make divider_round_rate take the parent clock

[Stephen Boyd]

On 03/07, Maxime Ripard wrote:
> So far, divider_round_rate only considers the parent clock returned by
> clk_hw_get_parent.
> 
> This works fine on clocks that have a single parents, this doesn't work on
> muxes, since we will only consider the first parent, while other parents
> may totally be able to provide a better combination.
> 
> Clocks in that case cannot use divider_round_rate, so would have to come up
> with a very similar logic to work around it. Instead of having to do
> something like this, and duplicate that logic everywhere, give an
> additional parameter for the parent clock to consider.
> 
> Current users have been converted using the following coccinelle script
> 
> @@
> identifier hw, rate, prate, table, width, flags;
> @@
> 
> -long divider_round_rate(struct clk_hw *hw,
> +long divider_round_rate(struct clk_hw *hw, struct clk_hw *parent,
> unsigned long rate,
> unsigned long *prate,
> const struct clk_div_table *table,
> u8 width,
> unsigned long flags) { ... }
> 
> @@
> identifier fn, hw;
> expression E2, E3, E4, E5, E6;
> @@
>  fn (struct clk_hw *hw, ...) {
>  <...
> -divider_round_rate(hw, E2, E3, E4, E5, E6)
> +divider_round_rate(hw, clk_hw_get_parent(hw), E2, E3, E4, E5, E6)
>  ...>
> }

Why not introduce another function like 

divider_round_rate_parent()
divider_round_rate_mux()

that takes the extra parent argument? Technically, a divider is
considered to only have one parent, and if it has more than one
parent, then it is a mux and a divider.

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Re: RFC: late drm pull requests and other topics

[Sean Paul]

On Tue, Mar 07, 2017 at 01:11:43AM +0100, Daniel Vetter wrote:
> Hi all,
> 
> In the 4.11 drm pull request Linus raised a few things that we need to 
> discuss:
> 
> Late driver/enabling pull requests
> --
> 
> Imo this isn't as one-sided as Linus made it sound, we've had the policy of
> pulling new drivers and enabling for new hw very late in the merge window
> forever. And I think there's some good benefits, both for users as for 
> companies
> trying to do early enabling. It's just that in the past few years it's been
> mostly arm drivers (where Linus doesn't see the inevitable Kconfig fail) or 
> new
> code in existing big drivers (where Kconfig fail tends to not happen if you
> leave backlight code alone ...).
> 
> Anyway, Linus has been pretty clear here, not really wiggle room left and
> personally I think this doesn't hurt us that much, it's more on the 
> unfortunate
> side. I discussed this a bit with Dave on irc, and the proposal would be that
> every feature patch must be in linux-next by -rc6 and in drm-next by -rc7. 
> This
> is how drm-intel has run since years, and also what we started doing with
> drm-misc (except new platform enabling, which I guess now can't happen any 
> more,
> amdgpu with Vega will probably be hurt first). So works, just means everyone
> needs to queue stuff early and also have their tree in linux-next (or get into
> drm-misc if that's too much pain).
> 
> Linus shitting on dri-devel
> ---
> 
> I'm not happy with that, and asked Linus to at least drop dri-devel when he
> shits on Dave and maintainers. Dave also brought up the idea of bcc'ing
> dri-devel, which should prevent shouting from Linus reliably. Note I'm not
> suggesting we ignore Linus' input, just that we keep the 90% insults that it's
> wrapped in out of our community as much as we can. Better ideas than bcc would
> be good.

Pretty much copypasta from irc:

I'm not sure bcc really solves the problem, you'll notice that Linus directly 
cc'd
the contributor in his rant. Aside from that, his rants usually create a bit of
"omg look at what Linus said" buzz that is sure to get back to contributors. 
IMO,
the best approach is to do exactly what danvet did last time: praise the 
contributor
for their work and reiterate the list rule that one must be respectful on 
dri-devel.
I think everyone agrees that beyond the legitimate concerns about late pulls, 
the
rest is a non-event and we'll all move on.


> 
> Splitting the drm pull
> --
> 
> I don't think this would be a good idea at all:
> 
> - Personally I don't want to send pull requests to Linus. Dave seems ok with
>   taking the heat for us, and I'm very happy he's willing to do that. I'd
>   certainly not do that.
> 
> - There's the small problem that more trees means we need to spent more time
>   with the burocratics. From my experience with drm-misc and drm-intel alone
>   there's lots of coordination needed, and we resync every 1-3 weeks in 
> drm-next
>   with pull requests to Dave. I don't see anyone volunteering to spend more 
> time
>   on burocratics, there's already enough to do.
> 

Yeah, I feel like if we split things up, Linus would likely be even more
unhappy. Even with very careful planning, the drm core changes so frequently
that things are bound to drift. drm-misc does a good job of mostly solving that
issue, and having Dave between the subtree chaos and Linus is very valuable.

Sean

> - We've done some really impressive refactorings in drm the past 1-2 years, 
> very
>   often cleanups that new driver contributors have done. Looking at drm-misc 
> we
>   need to resync about once per month to be able to move forward, since new
>   drivers depend upon new refactorings and new refactorings later then need to
>   have a tree with all the drivers. So really no way to split things up I 
> think
>   without slowing down a lot. And ime if you want to ship upstream as product 
> in
>   the embedded space, we're still not fast enough.
> 
>   For Intel that'd mean we'd have to pull out a lot of our efforts spent in
>   improving the core and helpers, and I think the same holds for a lot of 
> other
>   drivers. Many might even entirely drop upstream because bikeshedding a 
> helper
>   for 3 months first and then the driver for another 3 months for something
>   trivial is silly.
> 
> So overall I think overall this would hurt way too much, and we don't have the
> people with free time to implement it anyway. Well, without slowing down and
> making upstream gfx irrevelant again now that it's finally being taken more
> serious. I also discussed this with Dave and others on irc a bit, and Dave
> thinks that there shouldn't be any problem for us if we keept he one single
> overall subsystem tree.
> 
> Those 3 items where the ones I noted, anything I missed?
> 
> Thanks, Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> __

[Bug 99387] Kernel 4.9: Kaveri + Hainan choked on boot using amdgpu

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99387

Alex Deucher  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

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[Bug 100058] amdgpu/dpm: NULL pointer dereference

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100058

--- Comment #8 from Alex Deucher  ---
Do the patches in bug 99387 help?

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Re: RFC: late drm pull requests and other topics

[Alex Deucher]

On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter  wrote:
> Hi all,
>
> In the 4.11 drm pull request Linus raised a few things that we need to 
> discuss:
>
> Late driver/enabling pull requests
> --
>
> Imo this isn't as one-sided as Linus made it sound, we've had the policy of
> pulling new drivers and enabling for new hw very late in the merge window
> forever. And I think there's some good benefits, both for users as for 
> companies
> trying to do early enabling. It's just that in the past few years it's been
> mostly arm drivers (where Linus doesn't see the inevitable Kconfig fail) or 
> new
> code in existing big drivers (where Kconfig fail tends to not happen if you
> leave backlight code alone ...).
>
> Anyway, Linus has been pretty clear here, not really wiggle room left and
> personally I think this doesn't hurt us that much, it's more on the 
> unfortunate
> side. I discussed this a bit with Dave on irc, and the proposal would be that
> every feature patch must be in linux-next by -rc6 and in drm-next by -rc7. 
> This
> is how drm-intel has run since years, and also what we started doing with
> drm-misc (except new platform enabling, which I guess now can't happen any 
> more,
> amdgpu with Vega will probably be hurt first). So works, just means everyone
> needs to queue stuff early and also have their tree in linux-next (or get into
> drm-misc if that's too much pain).

I've always tried to have all major new features sent to Dave by rc5,
so no problems with the timelines.  Dave and Linus have generally been
ok with new asic support at strange times assuming it has minimal
impact on existing support.  Our code release dates rarely line up
well with kernel cycles, but we can manage.


>
> Linus shitting on dri-devel
> ---
>
> I'm not happy with that, and asked Linus to at least drop dri-devel when he
> shits on Dave and maintainers. Dave also brought up the idea of bcc'ing
> dri-devel, which should prevent shouting from Linus reliably. Note I'm not
> suggesting we ignore Linus' input, just that we keep the 90% insults that it's
> wrapped in out of our community as much as we can. Better ideas than bcc would
> be good.

It sucks, but I guess my skin has hardened over the years.  We've had
a fair share of heated arguments even on dri-devel.

>
> Splitting the drm pull
> --
>
> I don't think this would be a good idea at all:
>
> - Personally I don't want to send pull requests to Linus. Dave seems ok with
>   taking the heat for us, and I'm very happy he's willing to do that. I'd
>   certainly not do that.
>
> - There's the small problem that more trees means we need to spent more time
>   with the burocratics. From my experience with drm-misc and drm-intel alone
>   there's lots of coordination needed, and we resync every 1-3 weeks in 
> drm-next
>   with pull requests to Dave. I don't see anyone volunteering to spend more 
> time
>   on burocratics, there's already enough to do.
>
> - We've done some really impressive refactorings in drm the past 1-2 years, 
> very
>   often cleanups that new driver contributors have done. Looking at drm-misc 
> we
>   need to resync about once per month to be able to move forward, since new
>   drivers depend upon new refactorings and new refactorings later then need to
>   have a tree with all the drivers. So really no way to split things up I 
> think
>   without slowing down a lot. And ime if you want to ship upstream as product 
> in
>   the embedded space, we're still not fast enough.
>
>   For Intel that'd mean we'd have to pull out a lot of our efforts spent in
>   improving the core and helpers, and I think the same holds for a lot of 
> other
>   drivers. Many might even entirely drop upstream because bikeshedding a 
> helper
>   for 3 months first and then the driver for another 3 months for something
>   trivial is silly.
>
> So overall I think overall this would hurt way too much, and we don't have the
> people with free time to implement it anyway. Well, without slowing down and
> making upstream gfx irrevelant again now that it's finally being taken more
> serious. I also discussed this with Dave and others on irc a bit, and Dave
> thinks that there shouldn't be any problem for us if we keept he one single
> overall subsystem tree.
>
> Those 3 items where the ones I noted, anything I missed?

I agree.  I don't see the need to split up the pulls.  I think we do
pretty well overall.

Alex


>
> Thanks, Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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[PATCH] gpu: host1x: Fix syncpt array index check

[Mikko Perttunen]

The index overflow check in host1x_syncpt_get was incorrect,
and would return a pointer past the syncpt array if the
syncpt index given was the total number of syncpts. Fix
this.

Signed-off-by: Mikko Perttunen 
---
 drivers/gpu/host1x/syncpt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/host1x/syncpt.c b/drivers/gpu/host1x/syncpt.c
index 25c11a85050b..3236c3d21a15 100644
--- a/drivers/gpu/host1x/syncpt.c
+++ b/drivers/gpu/host1x/syncpt.c
@@ -484,10 +484,10 @@ unsigned int host1x_syncpt_nb_mlocks(struct host1x *host)
 
 struct host1x_syncpt *host1x_syncpt_get(struct host1x *host, unsigned int id)
 {
-   if (host->info->nb_pts < id)
+   if (id < host->info->nb_pts)
+   return host->syncpt + id;
+   else
return NULL;
-
-   return host->syncpt + id;
 }
 EXPORT_SYMBOL(host1x_syncpt_get);
 
-- 
2.11.1

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Re: [PATCH 0/2] Documentation/EDID fixes

[Jani Nikula]

On Mon, 06 Mar 2017, Javi Merino  wrote:
> I found these two minor issues while building an EDID.  I'm not sure
> whether the second patch (Add O= to support) is upstream material, but
> I'm sending it just in case.

I'm not opposed to fixing existing issues like this, but really I think
there should be an userspace tool for this. Definitely outside of the
Documentation directory, perhaps even outside the kernel tree
altogether.

BR,
Jani.


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Re: [PATCH 1/6] doc: Explain light-handed markup preference a bit better

[Daniel Vetter]

On Thu, Mar 02, 2017 at 04:16:33PM +0100, Daniel Vetter wrote:
> We already had a super-short blurb, but worth extending it I think:
> We're still pretty far away from anything like a consensus, but
> there's clearly a lot of people who prefer an as-light as possible
> approach to converting existing .txt files to .rst. Make sure this is
> properly taken into account and clear.
> 
> Motivated by discussions with Peter and Christoph and others.
> 
> v2:
> - Mention that existing headings should be kept when converting
>   existing .txt files (Mauro).
> - Explain that we prefer :: for quoting code, it's easier on the
>   eyes (Mauro).
> - Explain that blindly converting outdated docs is harmful. Motived
>   by comments Peter did in our discussion.
> 
> v3: Make the explanations around fixed-width quoting more concise
> (Jani).
> 
> v4:
> - Rebase onto docs-4.10.
> - Go with the more terse recommendation from Jani, defer to the much
>   more detailed conversion guide Mauro is working on for details.
> 
> Cc: Jonathan Corbet 
> Cc: linux-...@vger.kernel.org
> Cc: Christoph Hellwig 
> Cc: Peter Zijlstra 
> Cc: Jani Nikula 
> Cc: Mauro Carvalho Chehab 
> Signed-off-by: Daniel Vetter 

Jon, can you pls pick this one up, or want me to resend stand-alone?

Thanks, Daniel
> ---
>  Documentation/doc-guide/sphinx.rst | 17 -
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/doc-guide/sphinx.rst 
> b/Documentation/doc-guide/sphinx.rst
> index 96fe7ccb2c67..532d65b70500 100644
> --- a/Documentation/doc-guide/sphinx.rst
> +++ b/Documentation/doc-guide/sphinx.rst
> @@ -73,7 +73,16 @@ Specific guidelines for the kernel documentation
>  
>  Here are some specific guidelines for the kernel documentation:
>  
> -* Please don't go overboard with reStructuredText markup. Keep it simple.
> +* Please don't go overboard with reStructuredText markup. Keep it
> +  simple. For the most part the documentation should be plain text with
> +  just enough consistency in formatting that it can be converted to
> +  other formats.
> +
> +* Please keep the formatting changes minimal when converting existing
> +  documentation to reStructuredText.
> +
> +* Also update the content, not just the formatting, when converting
> +  documentation.
>  
>  * Please stick to this order of heading adornments:
>  
> @@ -103,6 +112,12 @@ Here are some specific guidelines for the kernel 
> documentation:
>the order as encountered."), having the higher levels the same overall 
> makes
>it easier to follow the documents.
>  
> +* For inserting fixed width text blocks (for code examples, use case
> +  examples, etc.), use ``::`` for anything that doesn't really benefit
> +  from syntax highlighting, especially short snippets. Use
> +  ``.. code-block:: `` for longer code blocks that benefit
> +  from highlighting.
> +
>  
>  the C domain
>  
> -- 
> 2.11.0
> 

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Re: RFC: late drm pull requests and other topics

[Jani Nikula]

On Tue, 07 Mar 2017, Daniel Vetter  wrote:
> Hi all,
>
> In the 4.11 drm pull request Linus raised a few things that we need to 
> discuss:
>
> Late driver/enabling pull requests
> --
>
> Imo this isn't as one-sided as Linus made it sound, we've had the policy of
> pulling new drivers and enabling for new hw very late in the merge window
> forever. And I think there's some good benefits, both for users as for 
> companies
> trying to do early enabling. It's just that in the past few years it's been
> mostly arm drivers (where Linus doesn't see the inevitable Kconfig fail) or 
> new
> code in existing big drivers (where Kconfig fail tends to not happen if you
> leave backlight code alone ...).
>
> Anyway, Linus has been pretty clear here, not really wiggle room left and
> personally I think this doesn't hurt us that much, it's more on the 
> unfortunate
> side. I discussed this a bit with Dave on irc, and the proposal would be that
> every feature patch must be in linux-next by -rc6 and in drm-next by -rc7. 
> This
> is how drm-intel has run since years, and also what we started doing with
> drm-misc (except new platform enabling, which I guess now can't happen any 
> more,
> amdgpu with Vega will probably be hurt first). So works, just means everyone
> needs to queue stuff early and also have their tree in linux-next (or get into
> drm-misc if that's too much pain).

The sad part is when the shit hits the fan as a result of us being kind
and accepting stuff near the merge window, with the idea that new
drivers and enabling won't regress anything. For everything else the
rule has been -rc5-ish for some time and should remain that way. We'll
just have to document and be transparent about the reasons why we're
being strict.

Spelling out the obvious, the penalty for missing the deadline is a
delay of one kernel release, or about 10 weeks. Folks, please let's keep
that in mind when we're contemplating the bikeshedding review near that
critical time frame. Let's be considerate.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Technology Center
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[PATCH v3 1/6] drm: bridge: dw-hdmi: Extract PHY interrupt setup to a function

[Neil Armstrong]

From: Laurent Pinchart 

In preparation for adding PHY operations to handle RX SENSE and HPD,
group all the PHY interrupt setup code in a single location and extract
it to a separate function.

Signed-off-by: Laurent Pinchart 
Signed-off-by: Neil Armstrong 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 50 ++-
 1 file changed, 23 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 026a0dc..1ed8bc1 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1496,7 +1496,7 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct 
drm_display_mode *mode)
 }
 
 /* Wait until we are registered to enable interrupts */
-static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
+static void dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
 {
hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
HDMI_PHY_I2CM_INT_ADDR);
@@ -1504,15 +1504,6 @@ static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
HDMI_PHY_I2CM_CTLINT_ADDR);
-
-   /* enable cable hot plug irq */
-   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
-
-   /* Clear Hotplug interrupts */
-   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
-   HDMI_IH_PHY_STAT0);
-
-   return 0;
 }
 
 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
@@ -1630,6 +1621,26 @@ static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
 }
 
+static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi)
+{
+   /*
+* Configure the PHY RX SENSE and HPD interrupts polarities and clear
+* any pending interrupt.
+*/
+   hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
+   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
+   HDMI_IH_PHY_STAT0);
+
+   /* Enable cable hot plug irq. */
+   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
+
+   /* Clear and unmute interrupts. */
+   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
+   HDMI_IH_PHY_STAT0);
+   hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
+   HDMI_IH_MUTE_PHY_STAT0);
+}
+
 static enum drm_connector_status
 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
 {
@@ -2141,29 +2152,14 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
hdmi->ddc = NULL;
}
 
-   /*
-* Configure registers related to HDMI interrupt
-* generation before registering IRQ.
-*/
-   hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
-
-   /* Clear Hotplug interrupts */
-   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
-   HDMI_IH_PHY_STAT0);
-
hdmi->bridge.driver_private = hdmi;
hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
 #ifdef CONFIG_OF
hdmi->bridge.of_node = pdev->dev.of_node;
 #endif
 
-   ret = dw_hdmi_fb_registered(hdmi);
-   if (ret)
-   goto err_iahb;
-
-   /* Unmute interrupts */
-   hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
-   HDMI_IH_MUTE_PHY_STAT0);
+   dw_hdmi_fb_registered(hdmi);
+   dw_hdmi_phy_setup_hpd(hdmi);
 
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.parent = dev;
-- 
1.9.1

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[PATCH v3 2/6] media: uapi: Add RGB and YUV bus formats for Synopsys HDMI TX Controller

[Neil Armstrong]

In order to describe the RGB and YUB bus formats used to feed the
Synopsys DesignWare HDMI TX Controller, add missing formats to the
list of Bus Formats.

Documentation for these formats is added in a separate patch.

Signed-off-by: Neil Armstrong 
---
 include/uapi/linux/media-bus-format.h | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/include/uapi/linux/media-bus-format.h 
b/include/uapi/linux/media-bus-format.h
index 2168759..7cc820b 100644
--- a/include/uapi/linux/media-bus-format.h
+++ b/include/uapi/linux/media-bus-format.h
@@ -33,7 +33,7 @@
 
 #define MEDIA_BUS_FMT_FIXED0x0001
 
-/* RGB - next is   0x1018 */
+/* RGB - next is   0x101b */
 #define MEDIA_BUS_FMT_RGB444_1X12  0x1016
 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE  0x1001
 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE  0x1002
@@ -57,8 +57,11 @@
 #define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA   0x1012
 #define MEDIA_BUS_FMT_ARGB_1X320x100d
 #define MEDIA_BUS_FMT_RGB888_1X32_PADHI0x100f
+#define MEDIA_BUS_FMT_RGB101010_1X30   0x1018
+#define MEDIA_BUS_FMT_RGB121212_1X36   0x1019
+#define MEDIA_BUS_FMT_RGB161616_1X48   0x101a
 
-/* YUV (including grey) - next is  0x2026 */
+/* YUV (including grey) - next is  0x202c */
 #define MEDIA_BUS_FMT_Y8_1X8   0x2001
 #define MEDIA_BUS_FMT_UV8_1X8  0x2015
 #define MEDIA_BUS_FMT_UYVY8_1_5X8  0x2002
@@ -90,12 +93,18 @@
 #define MEDIA_BUS_FMT_YVYU10_1X20  0x200e
 #define MEDIA_BUS_FMT_VUY8_1X240x2024
 #define MEDIA_BUS_FMT_YUV8_1X240x2025
+#define MEDIA_BUS_FMT_UYVY8_1_1X24 0x2026
 #define MEDIA_BUS_FMT_UYVY12_1X24  0x2020
 #define MEDIA_BUS_FMT_VYUY12_1X24  0x2021
 #define MEDIA_BUS_FMT_YUYV12_1X24  0x2022
 #define MEDIA_BUS_FMT_YVYU12_1X24  0x2023
 #define MEDIA_BUS_FMT_YUV10_1X30   0x2016
+#define MEDIA_BUS_FMT_UYVY10_1_1X300x2027
 #define MEDIA_BUS_FMT_AYUV8_1X32   0x2017
+#define MEDIA_BUS_FMT_UYVY12_1_1X360x2028
+#define MEDIA_BUS_FMT_YUV12_1X36   0x2029
+#define MEDIA_BUS_FMT_YUV16_1X48   0x202a
+#define MEDIA_BUS_FMT_UYVY16_1_1X480x202b
 
 /* Bayer - next is 0x3021 */
 #define MEDIA_BUS_FMT_SBGGR8_1X8   0x3001
-- 
1.9.1

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[PATCH v3 5/6] drm: bridge: dw-hdmi: Add Documentation on supported input formats

[Neil Armstrong]

This patch adds a new DRM documentation entry and links to the input
format table added in the dw_hdmi header.

Signed-off-by: Neil Armstrong 
---
 Documentation/gpu/dw-hdmi.rst | 15 +++
 Documentation/gpu/index.rst   |  1 +
 2 files changed, 16 insertions(+)
 create mode 100644 Documentation/gpu/dw-hdmi.rst

diff --git a/Documentation/gpu/dw-hdmi.rst b/Documentation/gpu/dw-hdmi.rst
new file mode 100644
index 000..486faad
--- /dev/null
+++ b/Documentation/gpu/dw-hdmi.rst
@@ -0,0 +1,15 @@
+===
+ drm/bridge/dw-hdmi Synopsys DesignWare HDMI Controller
+===
+
+Synopsys DesignWare HDMI Controller
+===
+
+This section covers everything related to the Synopsys DesignWare HDMI
+Controller implemented as a DRM bridge.
+
+Supported Input Formats and Encodings
+-
+
+.. kernel-doc:: include/drm/bridge/dw_hdmi.h
+   :doc: Supported input formats and encodings
diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst
index e998ee0..0725449 100644
--- a/Documentation/gpu/index.rst
+++ b/Documentation/gpu/index.rst
@@ -10,6 +10,7 @@ Linux GPU Driver Developer's Guide
drm-kms
drm-kms-helpers
drm-uapi
+   dw-hdmi
i915
tinydrm
vc4
-- 
1.9.1

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[PATCH v3 3/6] documentation: media: Add documentation for new RGB and YUV bus formats

[Neil Armstrong]

Add documentation for added Bus Formats to describe RGB and YUS formats used
as input to the Synopsys DesignWare HDMI TX Controller.

Signed-off-by: Neil Armstrong 
---
 Documentation/media/uapi/v4l/subdev-formats.rst | 4992 ++-
 1 file changed, 3963 insertions(+), 1029 deletions(-)

diff --git a/Documentation/media/uapi/v4l/subdev-formats.rst 
b/Documentation/media/uapi/v4l/subdev-formats.rst
index d6152c9..feb55b5 100644
--- a/Documentation/media/uapi/v4l/subdev-formats.rst
+++ b/Documentation/media/uapi/v4l/subdev-formats.rst
@@ -114,7 +114,7 @@ The following tables list existing packed RGB formats.
 .. it switches to long table, and there's no way to override it.
 
 
-.. tabularcolumns:: 
|p{4.0cm}|p{0.7cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|
+.. tabularcolumns:: 
|p{4.0cm}|p{0.7cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|
 
 .. _v4l2-mbus-pixelcode-rgb:
 
@@ -127,7 +127,7 @@ The following tables list existing packed RGB formats.
 .. flat-table:: RGB formats
 :header-rows:  2
 :stub-columns: 0
-:widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 
2 2 2
+:widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
 
 * - Identifier
   - Code
@@ -136,6 +136,22 @@ The following tables list existing packed RGB formats.
 * -
   -
   - Bit
+  - 47
+  - 46
+  - 45
+  - 44
+  - 43
+  - 42
+  - 41
+  - 40
+  - 39
+  - 38
+  - 37
+  - 36
+  - 35
+  - 34
+  - 33
+  - 32
   - 31
   - 30
   - 29
@@ -193,6 +209,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - r\ :sub:`3`
   - r\ :sub:`2`
   - r\ :sub:`1`
@@ -234,6 +266,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - 0
   - 0
   - 0
@@ -269,6 +317,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - g\ :sub:`3`
   - g\ :sub:`2`
   - g\ :sub:`1`
@@ -306,6 +370,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - g\ :sub:`3`
   - g\ :sub:`2`
   - g\ :sub:`1`
@@ -341,6 +421,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - 0
   - 0
   - 0
@@ -378,6 +474,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - 0
   - r\ :sub:`4`
   - r\ :sub:`3`
@@ -413,6 +525,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - g\ :sub:`2`
   - g\ :sub:`1`
   - g\ :sub:`0`
@@ -450,6 +578,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
   - g\ :sub:`2`
   - g\ :sub:`1`
   - g\ :sub:`0`
@@ -485,6 +629,22 @@ The following tables list existing packed RGB formats.
   -
   -
   -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -
+  -

[PATCH v3 0/6] drm: bridge: dw-hdmi: Add support for Custom PHYs

[Neil Armstrong]

The Amlogic GX SoCs implements a Synopsys DesignWare HDMI TX Controller
in combination with a very custom PHY.

Thanks to Laurent Pinchart's changes, the HW report the following :
 Detected HDMI TX controller v2.01a with HDCP (Vendor PHY)

The following differs from common PHY integration as managed in the current
driver :
 - Amlogic PHY is not configured through the internal I2C link
 - Amlogic PHY do not use the ENTMDS, SVSRET, PDDQ, ... signals from the 
controller
 - Amlogic PHY do not export HPD ands RxSense signals to the controller

And finally, concerning the controller integration :
 - the Controller registers are not flat memory-mapped, and uses an
addr+read/write register pair to write all registers.
 - Inputs only YUV444 pixel data

Most of these uses case are implemented in Laurent Pinchart v5.1 patchset at 
[3] :
 - Conversion to regmap for register access
 - Add more callbacks ops to handle Custom PHYs
 - Fixes a bug that considers the input to be always RBG and sends bad pixel
   format to a DVI sink by disabling CSC

This is why the following patchset implements :
 - Configure the Input format from the plat_data
 - Add PHY callback to handle HPD and RxSense out of the dw-hdmi driver

To implement the input format handling, the Synopsys HDMIT TX Controller input
V4L bus formats are used and missing formats + documentation are added.

This patchset makes the Amlogic GX SoCs HDMI output successfully work, and is
also tested on the RK3288 ACT8846 EVB Board.

Changes since v2 at [4] :
 - Rebase on laurent patch "Extract PHY interrupt setup to a function"
 - Reduce phy operations
 - Switch the V4L bus formats and encodings instead of custom enum

Changes since v1 at [2] :
 - Drop patches submitted by laurent

Changes since RFC at [1] :
 - Regmap fixup for 4bytes register access, tested on RK3288 SoC
 - Move phy callbacks to phy_ops and move Synopsys PHY calls into default ops
 - Move HDMI link data into shared header
 - Move Pixel Encoding enum to shared header

[1] 
http://lkml.kernel.org/r/1484656294-6140-1-git-send-email-narmstr...@baylibre.com
[2] 
http://lkml.kernel.org/r/1485774318-21916-1-git-send-email-narmstr...@baylibre.com
[3] 
http://lkml.kernel.org/r/20170303172007.26541-1-laurent.pinchart+rene...@ideasonboard.com
[4] 
http://lkml.kernel.org/r/1488468572-31971-1-git-send-email-narmstr...@baylibre.com

Laurent Pinchart (1):
  drm: bridge: dw-hdmi: Extract PHY interrupt setup to a function

Neil Armstrong (5):
  media: uapi: Add RGB and YUV bus formats for Synopsys HDMI TX
Controller
  documentation: media: Add documentation for new RGB and YUV bus
formats
  drm: bridge: dw-hdmi: Switch to V4L bus format and encodings
  drm: bridge: dw-hdmi: Add Documentation on supported input formats
  drm: bridge: dw-hdmi: Move HPD handling to PHY operations

 Documentation/gpu/dw-hdmi.rst   |   15 +
 Documentation/gpu/index.rst |1 +
 Documentation/media/uapi/v4l/subdev-formats.rst | 4992 ++-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c   |  465 ++-
 include/drm/bridge/dw_hdmi.h|   68 +
 include/uapi/linux/media-bus-format.h   |   13 +-
 6 files changed, 4368 insertions(+), 1186 deletions(-)
 create mode 100644 Documentation/gpu/dw-hdmi.rst

-- 
1.9.1

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[PATCH v3 6/6] drm: bridge: dw-hdmi: Move HPD handling to PHY operations

[Neil Armstrong]

The HDMI TX controller support HPD and RXSENSE signaling from the PHY
via it's STAT0 PHY interface, but some vendor PHYs can manage these
signals independently from the controller, thus these STAT0 handling
should be moved to PHY specific operations and become optional.

The existing STAT0 HPD and RXSENSE handling code is refactored into
a supplementaty set of default PHY operations that are used automatically
when the platform glue doesn't provide its own operations.

Signed-off-by: Neil Armstrong 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 135 ++
 include/drm/bridge/dw_hdmi.h  |   5 ++
 2 files changed, 86 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 348311c..1c6cb46 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -1215,10 +1215,46 @@ static enum drm_connector_status 
dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
connector_status_connected : connector_status_disconnected;
 }
 
+static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+  bool force, bool disabled, bool rxsense)
+{
+   u8 old_mask = hdmi->phy_mask;
+
+   if (force || disabled || !rxsense)
+   hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
+   else
+   hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
+
+   if (old_mask != hdmi->phy_mask)
+   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
+}
+
+static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
+{
+   /*
+* Configure the PHY RX SENSE and HPD interrupts polarities and clear
+* any pending interrupt.
+*/
+   hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
+   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
+   HDMI_IH_PHY_STAT0);
+
+   /* Enable cable hot plug irq. */
+   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
+
+   /* Clear and unmute interrupts. */
+   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
+   HDMI_IH_PHY_STAT0);
+   hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
+   HDMI_IH_MUTE_PHY_STAT0);
+}
+
 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
.init = dw_hdmi_phy_init,
.disable = dw_hdmi_phy_disable,
.read_hpd = dw_hdmi_phy_read_hpd,
+   .update_hpd = dw_hdmi_phy_update_hpd,
+   .setup_hpd = dw_hdmi_phy_setup_hpd,
 };
 
 /* 
-
@@ -1742,35 +1778,10 @@ static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
  */
 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
 {
-   u8 old_mask = hdmi->phy_mask;
-
-   if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
-   hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
-   else
-   hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
-
-   if (old_mask != hdmi->phy_mask)
-   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
-}
-
-static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi)
-{
-   /*
-* Configure the PHY RX SENSE and HPD interrupts polarities and clear
-* any pending interrupt.
-*/
-   hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
-   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
-   HDMI_IH_PHY_STAT0);
-
-   /* Enable cable hot plug irq. */
-   hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
-
-   /* Clear and unmute interrupts. */
-   hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
-   HDMI_IH_PHY_STAT0);
-   hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
-   HDMI_IH_MUTE_PHY_STAT0);
+   if (hdmi->phy.ops->update_hpd)
+   hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
+ hdmi->force, hdmi->disabled,
+ hdmi->rxsense);
 }
 
 static enum drm_connector_status
@@ -1962,6 +1973,41 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
return ret;
 }
 
+void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
+{
+   mutex_lock(&hdmi->mutex);
+
+   if (!hdmi->disabled && !hdmi->force) {
+   /*
+* If the RX sense status indicates we're disconnected,
+* clear the software rxsense status.
+*/
+   if (!rx_sense)
+   hdmi->rxsense = false;
+
+   /*
+* Only set the software rxsense status when both
+* rxsense and hpd indicates we're connected.
+* This avoids what seems to be bad behaviour in
+ 

[PATCH v3 4/6] drm: bridge: dw-hdmi: Switch to V4L bus format and encodings

[Neil Armstrong]

Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.

Signed-off-by: Neil Armstrong 
---
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 322 +-
 include/drm/bridge/dw_hdmi.h  |  63 ++
 2 files changed, 290 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 1ed8bc1..348311c 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -30,17 +30,14 @@
 #include 
 #include 
 
+#include 
+#include 
+
 #include "dw-hdmi.h"
 #include "dw-hdmi-audio.h"
 
 #define HDMI_EDID_LEN  512
 
-#define RGB0
-#define YCBCR444   1
-#define YCBCR422_16BITS2
-#define YCBCR422_8BITS 3
-#define XVYCC444   4
-
 enum hdmi_datamap {
RGB444_8B = 0x01,
RGB444_10B = 0x03,
@@ -94,10 +91,10 @@ struct hdmi_vmode {
 };
 
 struct hdmi_data_info {
-   unsigned int enc_in_format;
-   unsigned int enc_out_format;
-   unsigned int enc_color_depth;
-   unsigned int colorimetry;
+   unsigned int enc_in_bus_format;
+   unsigned int enc_out_bus_format;
+   unsigned int enc_in_encoding;
+   unsigned int enc_out_encoding;
unsigned int pix_repet_factor;
unsigned int hdcp_enable;
struct hdmi_vmode video_mode;
@@ -557,6 +554,92 @@ void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 }
 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 
+static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
+{
+   switch (bus_format) {
+   case MEDIA_BUS_FMT_RGB888_1X24:
+   case MEDIA_BUS_FMT_RGB101010_1X30:
+   case MEDIA_BUS_FMT_RGB121212_1X36:
+   case MEDIA_BUS_FMT_RGB161616_1X48:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
+static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
+{
+   switch (bus_format) {
+   case MEDIA_BUS_FMT_YUV8_1X24:
+   case MEDIA_BUS_FMT_YUV10_1X30:
+   case MEDIA_BUS_FMT_YUV12_1X36:
+   case MEDIA_BUS_FMT_YUV16_1X48:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
+static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
+{
+   switch (bus_format) {
+   case MEDIA_BUS_FMT_UYVY8_1X16:
+   case MEDIA_BUS_FMT_UYVY10_1X20:
+   case MEDIA_BUS_FMT_UYVY12_1X24:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
+static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
+{
+   switch (bus_format) {
+   case MEDIA_BUS_FMT_UYVY8_1_1X24:
+   case MEDIA_BUS_FMT_UYVY10_1_1X30:
+   case MEDIA_BUS_FMT_UYVY12_1_1X36:
+   case MEDIA_BUS_FMT_UYVY16_1_1X48:
+   return true;
+
+   default:
+   return false;
+   }
+}
+
+static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
+{
+   switch (bus_format) {
+   case MEDIA_BUS_FMT_RGB888_1X24:
+   case MEDIA_BUS_FMT_YUV8_1X24:
+   case MEDIA_BUS_FMT_UYVY8_1X16:
+   case MEDIA_BUS_FMT_UYVY8_1_1X24:
+   return 8;
+
+   case MEDIA_BUS_FMT_RGB101010_1X30:
+   case MEDIA_BUS_FMT_YUV10_1X30:
+   case MEDIA_BUS_FMT_UYVY10_1X20:
+   case MEDIA_BUS_FMT_UYVY10_1_1X30:
+   return 10;
+
+   case MEDIA_BUS_FMT_RGB121212_1X36:
+   case MEDIA_BUS_FMT_YUV12_1X36:
+   case MEDIA_BUS_FMT_UYVY12_1X24:
+   case MEDIA_BUS_FMT_UYVY12_1_1X36:
+   return 12;
+
+   case MEDIA_BUS_FMT_RGB161616_1X48:
+   case MEDIA_BUS_FMT_YUV16_1X48:
+   case MEDIA_BUS_FMT_UYVY16_1_1X48:
+   return 16;
+
+   default:
+   return 0;
+   }
+}
+
 /*
  * this submodule is responsible for the video data synchronization.
  * for example, for RGB 4:4:4 input, the data map is defined as
@@ -569,37 +652,45 @@ static void hdmi_video_sample(struct dw_hdmi *hdmi)
int color_format = 0;
u8 val;
 
-   if (hdmi->hdmi_data.enc_in_format == RGB) {
-   if (hdmi->hdmi_data.enc_color_depth == 8)
-   color_format = 0x01;
-   else if (hdmi->hdmi_data.enc_color_depth == 10)
-   color_format = 0x03;
-   else if (hdmi->hdmi_data.enc_color_depth == 12)
-   color_format = 0x05;
-   else if (hdmi->hdmi_data.enc_color_depth == 16)
-   color_format = 0x07;
-   else
-   return;
-   } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
-   if (hdmi->hdmi_data.enc_color_depth == 8)
-   color_format = 0x09;
-   else if (hdmi->hdmi_data.enc_color_depth == 10)
-   color_format = 0x0B;
-   else if (hdmi->hdmi_data.enc_color_depth == 12)
-

[PATCH 1/4] drm/msm: Fix wrong pointer check in a5xx_destroy

[Jordan Crouse]

Instead of checking for a5xx_gpu->gpmu_iova during destroy we
accidently check a5xx_gpu->gpmu_bo.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 71b30dd..cd30088 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -768,7 +768,7 @@ static void a5xx_destroy(struct msm_gpu *gpu)
}
 
if (a5xx_gpu->gpmu_bo) {
-   if (a5xx_gpu->gpmu_bo)
+   if (a5xx_gpu->gpmu_iova)
msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
}
-- 
1.9.1

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[PATCH 0/4] drm/msm: Fixes for 4.11

[Jordan Crouse]

Hey Rob, here are a handful of things that might be fixable for 4.11 but if not
consider them for -next.

Jordan

Jordan Crouse (4):
  drm/msm: Fix wrong pointer check in a5xx_destroy
  drm/msm: Don't increase priv->num_aspaces until we know that it fits
  drm/msm: Pass interrupt status to a5xx_rbbm_err_irq()
  drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 22 +++---
 drivers/gpu/drm/msm/msm_drv.c |  7 +++
 drivers/gpu/drm/msm/msm_rd.c  |  4 ++--
 3 files changed, 20 insertions(+), 13 deletions(-)

-- 
1.9.1

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[PATCH 3/4] drm/msm: Pass interrupt status to a5xx_rbbm_err_irq()

[Jordan Crouse]

The interrupt status was being cleared before processing the handlers.
a5xx_rbbm_err_irq() was checking the interrupt status again, which would
likely turn out bad because the interrupt status would be 0 (or at least
different). Pass the original status to the function instead.

Also, skip clearing RBBM_AHB_ERROR from the interrupt status. The interrupt
will keep firing until the error source is cleared.  Skip the clear to
avoid a storm until the error is cleared in a5xx_rbbm_err_irq().

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index cd30088..dfc9734 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -872,10 +872,8 @@ static void a5xx_cp_err_irq(struct msm_gpu *gpu)
}
 }
 
-static void a5xx_rbbm_err_irq(struct msm_gpu *gpu)
+static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)
 {
-   u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
-
if (status & A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR) {
u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);
 
@@ -887,6 +885,10 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu)
 
/* Clear the error */
gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4));
+
+   /* Clear the interrupt */
+   gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
+   A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
}
 
if (status & A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT)
@@ -938,10 +940,16 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
 {
u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
 
-   gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, status);
+   /*
+* Clear all the interrupts except RBBM_AHB_ERROR - if we clear it
+* before the source is cleared the interrupt will storm.
+*/
+   gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
+   status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
 
+   /* Pass status to a5xx_rbbm_err_irq because we've already cleared it */
if (status & RBBM_ERROR_MASK)
-   a5xx_rbbm_err_irq(gpu);
+   a5xx_rbbm_err_irq(gpu, status);
 
if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR)
a5xx_cp_err_irq(gpu);
-- 
1.9.1

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[PATCH 4/4] drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

[Jordan Crouse]

Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR
section while maintaining backwards compatibility for tools that
only understand 32 bit iovas.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_rd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index 6607456..1e23132 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -348,7 +348,7 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
}
 
for (i = 0; i < submit->nr_cmds; i++) {
-   uint32_t iova = submit->cmd[i].iova;
+   uint64_t iova = submit->cmd[i].iova;
uint32_t szd  = submit->cmd[i].size; /* in dwords */
 
/* snapshot cmdstream bo's (if we haven't already): */
@@ -367,7 +367,7 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
case MSM_SUBMIT_CMD_BUF:
rd_write_section(rd, RD_CMDSTREAM_ADDR,
-   (uint32_t[2]){ iova, szd }, 8);
+   (uint32_t[3]){ iova, szd, iova >> 32 }, 12);
break;
}
}
-- 
1.9.1

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[PATCH 2/4] drm/msm: Don't increase priv->num_aspaces until we know that it fits

[Jordan Crouse]

priv->num_aspaces is increased and then checked to see if it still fits
in the priv->aspace array.  If it doesn't, we warn and exit but
priv->num_aspaces remains incremented.

Don't incremement the count until we know that it fits in the array.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_drv.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 70226ea..a9a520f 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -55,14 +55,13 @@ int msm_register_address_space(struct drm_device *dev,
struct msm_gem_address_space *aspace)
 {
struct msm_drm_private *priv = dev->dev_private;
-   int idx = priv->num_aspaces++;
 
-   if (WARN_ON(idx >= ARRAY_SIZE(priv->aspace)))
+   if (WARN_ON(priv->num_aspaces >= ARRAY_SIZE(priv->aspace)))
return -EINVAL;
 
-   priv->aspace[idx] = aspace;
+   priv->aspace[priv->num_aspaces] = aspace;
 
-   return idx;
+   return priv->num_aspaces++;
 }
 
 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
-- 
1.9.1

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Re: RFC: late drm pull requests and other topics

[Jani Nikula]

On Tue, 07 Mar 2017, Sean Paul  wrote:
> On Tue, Mar 07, 2017 at 01:11:43AM +0100, Daniel Vetter wrote:
>> Linus shitting on dri-devel
>> ---
>> 
> IMO, the best approach is to do exactly what danvet did last time:
> praise the contributor for their work and reiterate the list rule that
> one must be respectful on dri-devel.

Agreed, I prefer this over Bcc.

>> Splitting the drm pull
>> --
>> 
> Yeah, I feel like if we split things up, Linus would likely be even more
> unhappy. Even with very careful planning, the drm core changes so frequently
> that things are bound to drift. drm-misc does a good job of mostly solving 
> that
> issue, and having Dave between the subtree chaos and Linus is very valuable.

Agreed.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [PATCH 1/6] doc: Explain light-handed markup preference a bit better

[Jonathan Corbet]

On Tue, 7 Mar 2017 17:40:35 +0100
Daniel Vetter  wrote:

> Jon, can you pls pick this one up, or want me to resend stand-alone?

I got it; I should get both applied before too long.

jon
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[PATCH 02/11] drm/msm: Improve the zap shader

[Jordan Crouse]

Simply the code, use snprintf correct and make sure that we memset
the rest of the segment if the memory size in the ELF file is larger
than the file size.

Signed-off-by: Jordan Crouse 
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  4 +-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 70 +--
 2 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index b004275..2903020 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -915,8 +915,8 @@
};
};
 
-   qcom,zap-shader {
-   compatible = "qcom,zap-shader";
+   zap-shader {
+   compatible = "zap-shader";
memory-region = <&peripheral_reserved>;
 
qcom,firmware = "a530_zap";
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index dfc9734..9d754a7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -31,11 +31,11 @@ static inline bool _check_segment(const struct elf32_phdr 
*phdr)
phdr->p_memsz);
 }
 
-static int __pil_tz_load_image(struct platform_device *pdev,
+static int zap_load_segments(struct platform_device *pdev,
const struct firmware *mdt, const char *fwname,
void *fwptr, size_t fw_size, unsigned long fw_min_addr)
 {
-   char str[64] = { 0 };
+   char filename[64];
const struct elf32_hdr *ehdr = (struct elf32_hdr *) mdt->data;
const struct elf32_phdr *phdrs = (struct elf32_phdr *) (ehdr + 1);
const struct firmware *fw;
@@ -53,16 +53,18 @@ static int __pil_tz_load_image(struct platform_device *pdev,
offset = (phdr->p_paddr - fw_min_addr);
 
/* Request the file containing the segment */
-   snprintf(str, sizeof(str) - 1, "%s.b%02d", fwname, i);
+   snprintf(filename, sizeof(filename), "%s.b%02d", fwname, i);
 
-   ret = request_firmware(&fw, str, &pdev->dev);
+   ret = request_firmware(&fw, filename, &pdev->dev);
if (ret) {
-   dev_err(&pdev->dev, "Failed to load segment %s\n", str);
+   DRM_DEV_ERROR(&pdev->dev, "Failed to load segment %s\n",
+   filename);
break;
}
 
if (offset + fw->size > fw_size) {
-   dev_err(&pdev->dev, "Segment %s is too big\n", str);
+   DRM_DEV_ERROR(&pdev->dev, "Segment %s is too big\n",
+   filename);
ret = -EINVAL;
release_firmware(fw);
break;
@@ -70,15 +72,19 @@ static int __pil_tz_load_image(struct platform_device *pdev,
 
/* Copy the segment into place */
memcpy(fwptr + offset, fw->data, fw->size);
+
+   if (phdr->p_memsz > phdr->p_filesz)
+   memset(fwptr + fw->size, 0,
+   phdr->p_memsz - phdr->p_filesz);
release_firmware(fw);
}
 
return ret;
 }
 
-static int _pil_tz_load_image(struct platform_device *pdev)
+static int zap_load_mdt(struct platform_device *pdev)
 {
-   char str[64] = { 0 };
+   char filename[64];
const char *fwname;
const struct elf32_hdr *ehdr;
const struct elf32_phdr *phdrs;
@@ -86,7 +92,6 @@ static int _pil_tz_load_image(struct platform_device *pdev)
phys_addr_t fw_min_addr, fw_max_addr;
dma_addr_t fw_phys;
size_t fw_size;
-   u32 pas_id;
void *ptr;
int i, ret;
 
@@ -94,35 +99,29 @@ static int _pil_tz_load_image(struct platform_device *pdev)
return -ENODEV;
 
if (!qcom_scm_is_available()) {
-   dev_err(&pdev->dev, "SCM is not available\n");
-   return -EINVAL;
+   DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n");
+   return -EPROBE_DEFER;
}
 
ret = of_reserved_mem_device_init(&pdev->dev);
-
if (ret) {
-   dev_err(&pdev->dev, "Unable to set up the reserved memory\n");
+   DRM_DEV_ERROR(&pdev->dev, "Unable to set up the reserved 
memory\n");
return ret;
}
 
/* Get the firmware and PAS id from the device node */
if (of_property_read_string(pdev->dev.of_node, "qcom,firmware",
&fwname)) {
-   dev_err(&pdev->dev, "Could not read a firmware name\n");
-   return -EINVAL;
-   }
-
-   if (of_property_read_u32(pdev->dev.of_node, "qcom,pas-id", &pas_id)) {
-   dev_err(&pdev->dev, "Could not read the pas ID\n");
+

[PATCH 04/11] drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA

[Jordan Crouse]

Modify the 'pad' member of struct drm_msm_gem_info to 'hint'. If the
user sets 'hint' to non-zero it means that they want a IOVA for the
GEM object instead of a mmap() offset. Return the iova in the 'offset'
member.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_drv.c | 23 +--
 include/uapi/drm/msm_drm.h|  8 ++--
 2 files changed, 27 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index a9a520f..92375ac 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -695,6 +695,17 @@ static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, 
void *data,
return ret;
 }
 
+static int msm_ioctl_gem_info_iova(struct drm_device *dev,
+   struct drm_gem_object *obj, uint64_t *iova)
+{
+   struct msm_drm_private *priv = dev->dev_private;
+
+   if (!priv->gpu)
+   return -EINVAL;
+
+   return msm_gem_get_iova(obj, priv->gpu->id, iova);
+}
+
 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
struct drm_file *file)
 {
@@ -702,14 +713,22 @@ static int msm_ioctl_gem_info(struct drm_device *dev, 
void *data,
struct drm_gem_object *obj;
int ret = 0;
 
-   if (args->pad)
+   if (args->flags & ~MSM_INFO_FLAGS)
return -EINVAL;
 
obj = drm_gem_object_lookup(file, args->handle);
if (!obj)
return -ENOENT;
 
-   args->offset = msm_gem_mmap_offset(obj);
+   if (args->flags & MSM_INFO_IOVA) {
+   uint64_t iova;
+
+   ret = msm_ioctl_gem_info_iova(dev, obj, &iova);
+   if (!ret)
+   args->offset = iova;
+   } else {
+   args->offset = msm_gem_mmap_offset(obj);
+   }
 
drm_gem_object_unreference_unlocked(obj);
 
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 4d5d6a2..05dc5b3 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -103,10 +103,14 @@ struct drm_msm_gem_new {
__u32 handle; /* out */
 };
 
+#define MSM_INFO_IOVA  0x01
+
+#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
+
 struct drm_msm_gem_info {
__u32 handle; /* in */
-   __u32 pad;
-   __u64 offset; /* out, offset to pass to mmap() */
+   __u32 flags;  /* in - combination of MSM_INFO_* flags */
+   __u64 offset; /* out, mmap() offset or iova */
 };
 
 #define MSM_PREP_READ0x01
-- 
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[v2] [PATCH 00/11] drm/msm: A5XX preemption

[Jordan Crouse]

Here is v2 of the preemption series - Changes:

 * Refactored API in DRM_IOCTL_MSM_GEM_INFO (Thanks Emil Velikov)
 * Removed preemption worker and fixed atomics (Thanks Stephen Boyd)
 * Various fixes and improvements based on testing

Thanks!
Jordan

Jordan Crouse (11):
  drm/msm: Make sure to detach the MMU during GPU cleanup
  drm/msm: Improve the zap shader
  drm/msm: Remove idle function hook
  drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVA
  drm/msm: get an iova from the address space instead of an id
  drm/msm: Add a struct to pass configuration to msm_gpu_init()
  drm/msm: Remove memptrs->wptr
  drm/msm: Support multiple ringbuffers
  drm/msm: Shadow current pointer in the ring until command is complete
  drm/msm: Make the value of RB_CNTL (almost) generic
  drm/msm: Implement preemption for A5XX targets

 arch/arm64/boot/dts/qcom/msm8996.dtsi |   4 +-
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c |  13 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c |  13 +-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 292 +++--
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 103 -
 drivers/gpu/drm/msm/adreno/a5xx_power.c   |  11 +-
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 345 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   | 220 ---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  44 ++--
 drivers/gpu/drm/msm/dsi/dsi_host.c|  15 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c  |   8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  18 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c |  13 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c  |   5 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  11 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  13 +-
 drivers/gpu/drm/msm/msm_drv.c |  36 ++--
 drivers/gpu/drm/msm/msm_drv.h |  27 ++-
 drivers/gpu/drm/msm/msm_fb.c  |  15 +-
 drivers/gpu/drm/msm/msm_fbdev.c   |  10 +-
 drivers/gpu/drm/msm/msm_fence.c   |  85 ++--
 drivers/gpu/drm/msm/msm_fence.h   |  13 +-
 drivers/gpu/drm/msm/msm_gem.c | 134 
 drivers/gpu/drm/msm/msm_gem.h |   5 +-
 drivers/gpu/drm/msm/msm_gem_submit.c  |  14 +-
 drivers/gpu/drm/msm/msm_gpu.c | 141 +++-
 drivers/gpu/drm/msm/msm_gpu.h |  54 -
 drivers/gpu/drm/msm/msm_kms.h |   3 +
 drivers/gpu/drm/msm/msm_ringbuffer.c  |  14 +-
 drivers/gpu/drm/msm/msm_ringbuffer.h  |  21 +-
 include/uapi/drm/msm_drm.h|  13 +-
 34 files changed, 1322 insertions(+), 400 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c

-- 
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[PATCH 06/11] drm/msm: Add a struct to pass configuration to msm_gpu_init()

[Jordan Crouse]

The amount of information that we need to pass into msm_gpu_init()
is steadily increasing, so add a new struct to stabilize the function
call and make it easier to add new configuration down the line.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 ++--
 drivers/gpu/drm/msm/msm_gpu.c   | 13 ++---
 drivers/gpu/drm/msm/msm_gpu.h   | 11 ++-
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 959876d..cda4156 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -344,6 +344,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs 
*funcs)
 {
struct adreno_platform_config *config = pdev->dev.platform_data;
+   struct msm_gpu_config adreno_gpu_config  = { 0 };
struct msm_gpu *gpu = &adreno_gpu->base;
int ret;
 
@@ -363,9 +364,16 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
 
+   adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
+   adreno_gpu_config.irqname = "kgsl_3d0_irq";
+
+   adreno_gpu_config.va_start = SZ_16M;
+   adreno_gpu_config.va_end = 0x;
+
+   adreno_gpu_config.ringsz = RB_SIZE;
+
ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
-   adreno_gpu->info->name, "kgsl_3d0_reg_memory", 
"kgsl_3d0_irq",
-   RB_SIZE);
+   adreno_gpu->info->name, &adreno_gpu_config);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 16610ef..050d994 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -569,7 +569,7 @@ static irqreturn_t irq_handler(int irq, void *data)
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-   const char *name, const char *ioname, const char *irqname, int 
ringsz)
+   const char *name, struct msm_gpu_config *config)
 {
struct iommu_domain *iommu;
int i, ret;
@@ -605,14 +605,14 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
 
/* Map registers: */
-   gpu->mmio = msm_ioremap(pdev, ioname, name);
+   gpu->mmio = msm_ioremap(pdev, config->ioname, name);
if (IS_ERR(gpu->mmio)) {
ret = PTR_ERR(gpu->mmio);
goto fail;
}
 
/* Get Interrupt: */
-   gpu->irq = platform_get_irq_byname(pdev, irqname);
+   gpu->irq = platform_get_irq_byname(pdev, config->irqname);
if (gpu->irq < 0) {
ret = gpu->irq;
dev_err(drm->dev, "failed to get irq: %d\n", ret);
@@ -656,9 +656,8 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 */
iommu = iommu_domain_alloc(&platform_bus_type);
if (iommu) {
-   /* TODO 32b vs 64b address space.. */
-   iommu->geometry.aperture_start = SZ_16M;
-   iommu->geometry.aperture_end = 0x;
+   iommu->geometry.aperture_start = config->va_start;
+   iommu->geometry.aperture_end = config->va_end;
 
dev_info(drm->dev, "%s: using IOMMU\n", name);
gpu->aspace = msm_gem_address_space_create(&pdev->dev,
@@ -677,7 +676,7 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 
/* Create ringbuffer: */
mutex_lock(&drm->struct_mutex);
-   gpu->rb = msm_ringbuffer_new(gpu, ringsz);
+   gpu->rb = msm_ringbuffer_new(gpu, config->ringsz);
mutex_unlock(&drm->struct_mutex);
if (IS_ERR(gpu->rb)) {
ret = PTR_ERR(gpu->rb);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index ad6d13a..cc6530f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -28,6 +28,14 @@
 struct msm_gem_submit;
 struct msm_gpu_perfcntr;
 
+struct msm_gpu_config {
+   const char *ioname;
+   const char *irqname;
+   uint64_t va_start;
+   uint64_t va_end;
+   unsigned int ringsz;
+};
+
 /* So far, with hardware that I've seen to date, we can have:
  *  + zero, one, or two z180 2d cores
  *  + a3xx or a2xx 3d core, which share a common CP (the firmware
@@ -205,7 +213,8 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
-   

[PATCH 07/11] drm/msm: Remove memptrs->wptr

[Jordan Crouse]

memptrs->wptr seems to be unused. Remove it to avoid
confusing the upcoming preemption code.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 -
 2 files changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index cda4156..59b8930 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -123,7 +123,6 @@ void adreno_recover(struct msm_gpu *gpu)
/* reset completed fence seqno: */
adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
adreno_gpu->memptrs->rptr  = 0;
-   adreno_gpu->memptrs->wptr  = 0;
 
gpu->funcs->pm_resume(gpu);
 
@@ -256,7 +255,6 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
seq_printf(m, "fence:%d/%d\n", adreno_gpu->memptrs->fence,
gpu->fctx->last_fence);
seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
-   seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
 
gpu->funcs->pm_resume(gpu);
@@ -296,7 +294,6 @@ void adreno_dump_info(struct msm_gpu *gpu)
printk("fence:%d/%d\n", adreno_gpu->memptrs->fence,
gpu->fctx->last_fence);
printk("rptr: %d\n", get_rptr(adreno_gpu));
-   printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
printk("rb wptr:  %d\n", get_wptr(gpu->rb));
 }
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 42e444a..da47468 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -86,7 +86,6 @@ struct adreno_info {
 
 struct adreno_rbmemptrs {
volatile uint32_t rptr;
-   volatile uint32_t wptr;
volatile uint32_t fence;
 };
 
-- 
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[PATCH 08/11] drm/msm: Support multiple ringbuffers

[Jordan Crouse]

Add the infrastructure to support the idea of multiple ringbuffers.
Assign each ringbuffer an id and use that as an index for the various
ring specific operations.

The biggest delta is to support legacy fences. Each fence gets its own
sequence number but the legacy functions expect to use a unique integer.
To handle this we return a unique identifer for each submission but
map it to a specific ring/sequence under the covers. Newer users use
a dma_fence pointer anyway so they don't care about the actual sequence
ID or ring.

The actual mechanics for multiple ringbuffers are very target specific
so this code just allows for the possibility but still only defines
one ringbuffer for each target family.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |   9 +-
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c   |   9 +-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c   |  45 -
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h   |   2 +-
 drivers/gpu/drm/msm/adreno/a5xx_power.c |   6 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 156 +---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  36 +---
 drivers/gpu/drm/msm/msm_drv.h   |   2 +
 drivers/gpu/drm/msm/msm_fence.c |  85 -
 drivers/gpu/drm/msm/msm_fence.h |  13 ++-
 drivers/gpu/drm/msm/msm_gem.h   |   1 +
 drivers/gpu/drm/msm/msm_gem_submit.c|  10 +-
 drivers/gpu/drm/msm/msm_gpu.c   | 123 -
 drivers/gpu/drm/msm/msm_gpu.h   |  38 ++--
 drivers/gpu/drm/msm/msm_ringbuffer.c|  13 ++-
 drivers/gpu/drm/msm/msm_ringbuffer.h|   8 +-
 include/uapi/drm/msm_drm.h  |   5 +
 17 files changed, 375 insertions(+), 186 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index fc4fd2d..2f72848 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -44,7 +44,7 @@
 
 static bool a3xx_me_init(struct msm_gpu *gpu)
 {
-   struct msm_ringbuffer *ring = gpu->rb;
+   struct msm_ringbuffer *ring = gpu->rb[0];
 
OUT_PKT3(ring, CP_ME_INIT, 17);
OUT_RING(ring, 0x03f7);
@@ -65,7 +65,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
OUT_RING(ring, 0x);
 
-   gpu->funcs->flush(gpu);
+   gpu->funcs->flush(gpu, ring);
return a3xx_idle(gpu);
 }
 
@@ -339,7 +339,7 @@ static void a3xx_destroy(struct msm_gpu *gpu)
 static bool a3xx_idle(struct msm_gpu *gpu)
 {
/* wait for ringbuffer to drain: */
-   if (!adreno_idle(gpu))
+   if (!adreno_idle(gpu, gpu->rb[0]))
return false;
 
/* then wait for GPU to finish: */
@@ -449,6 +449,7 @@ static void a3xx_dump(struct msm_gpu *gpu)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
+   .active_ring = adreno_active_ring,
.irq = a3xx_irq,
.destroy = a3xx_destroy,
 #ifdef CONFIG_DEBUG_FS
@@ -496,7 +497,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
adreno_gpu->registers = a3xx_registers;
adreno_gpu->reg_offsets = a3xx_register_offsets;
 
-   ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
+   ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
if (ret)
goto fail;
 
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 6bc948b..bdd2a24 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -116,7 +116,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu)
 
 static bool a4xx_me_init(struct msm_gpu *gpu)
 {
-   struct msm_ringbuffer *ring = gpu->rb;
+   struct msm_ringbuffer *ring = gpu->rb[0];
 
OUT_PKT3(ring, CP_ME_INIT, 17);
OUT_RING(ring, 0x03f7);
@@ -137,7 +137,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
OUT_RING(ring, 0x);
 
-   gpu->funcs->flush(gpu);
+   gpu->funcs->flush(gpu, ring);
return a4xx_idle(gpu);
 }
 
@@ -337,7 +337,7 @@ static void a4xx_destroy(struct msm_gpu *gpu)
 static bool a4xx_idle(struct msm_gpu *gpu)
 {
/* wait for ringbuffer to drain: */
-   if (!adreno_idle(gpu))
+   if (!adreno_idle(gpu, gpu->rb[0]))
return false;
 
/* then wait for GPU to finish: */
@@ -539,6 +539,7 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t 
*value)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
+   .active_ring = adreno_active_ring,
.irq = a4xx_irq,
.destroy = a4xx_destroy,
 #ifdef CONFIG_DEBUG_FS
@@ -580,7 +581,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
adreno_gpu->registers = a4xx_registers;
adreno_

[PATCH 01/11] drm/msm: Make sure to detach the MMU during GPU cleanup

[Jordan Crouse]

We should be detaching the MMU before destroying the address
space. To do this cleanly, the detach has to happen in
adreno_gpu_cleanup() because it needs access to structs
in adreno_gpu.c.  Plus it is better symmetry to have
the attach and detach at the same code level.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 31 ---
 drivers/gpu/drm/msm/msm_gpu.c   |  3 ---
 2 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index f67e6f8..35a6849 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark 
  *
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as published by
@@ -420,18 +420,27 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
return 0;
 }
 
-void adreno_gpu_cleanup(struct adreno_gpu *gpu)
+void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
 {
-   if (gpu->memptrs_bo) {
-   if (gpu->memptrs)
-   msm_gem_put_vaddr(gpu->memptrs_bo);
+   struct msm_gpu *gpu = &adreno_gpu->base;
+
+   if (adreno_gpu->memptrs_bo) {
+   if (adreno_gpu->memptrs)
+   msm_gem_put_vaddr(adreno_gpu->memptrs_bo);
+
+   if (adreno_gpu->memptrs_iova)
+   msm_gem_put_iova(adreno_gpu->memptrs_bo, gpu->id);
+
+   drm_gem_object_unreference_unlocked(adreno_gpu->memptrs_bo);
+   }
+   release_firmware(adreno_gpu->pm4);
+   release_firmware(adreno_gpu->pfp);
 
-   if (gpu->memptrs_iova)
-   msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
+   msm_gpu_cleanup(gpu);
 
-   drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
+   if (gpu->aspace) {
+   gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
+   iommu_ports, ARRAY_SIZE(iommu_ports));
+   msm_gem_address_space_destroy(gpu->aspace);
}
-   release_firmware(gpu->pm4);
-   release_firmware(gpu->pfp);
-   msm_gpu_cleanup(&gpu->base);
 }
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 7b29843..e89093c 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -710,9 +710,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
msm_ringbuffer_destroy(gpu->rb);
}
 
-   if (gpu->aspace)
-   msm_gem_address_space_destroy(gpu->aspace);
-
if (gpu->fctx)
msm_fence_context_free(gpu->fctx);
 }
-- 
1.9.1

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[PATCH 10/11] drm/msm: Make the value of RB_CNTL (almost) generic

[Jordan Crouse]

We use a global ringbuffer size and block size for all targets and
at least for 5XX preemption we need to know the value the RB_CNTL
in several locations so it makes sense to caculate it once and use
it everywhere.

The only monkey wrench is that we need to disable the RPTR shadow
for A430 targets but that only needs to be done once and doesn't
affect A5XX so we can or in the value at init time.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 12 +++-
 drivers/gpu/drm/msm/msm_gpu.h   |  5 +
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index b8c11a0..8c23d92 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -21,7 +21,6 @@
 #include "msm_gem.h"
 #include "msm_mmu.h"
 
-#define RB_BLKSIZE 32
 
 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
 {
@@ -71,11 +70,14 @@ int adreno_hw_init(struct msm_gpu *gpu)
}
}
 
-   /* Setup REG_CP_RB_CNTL: */
+   /*
+* Setup REG_CP_RB_CNTL.  The same value is used across targets (with
+* the excpetion of A430 that disables the RPTR shadow) - the cacluation
+* for the ringbuffer size and block size is moved to msm_gpu.h for the
+* pre-processor to deal with and the A430 variant is ORed in here
+*/
adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
-   /* size is log2(quad-words): */
-   AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) |
-   AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
+   MSM_GPU_RB_CNTL_DEFAULT |
(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
 
/* Setup ringbuffer address - use ringbuffer[0] for GPU init */
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 38d826a..50fef27 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -135,6 +135,11 @@ struct msm_gpu {
 
 /* It turns out that all targets use the same ringbuffer size */
 #define MSM_GPU_RINGBUFFER_SZ SZ_32K
+#define MSM_GPU_RINGBUFFER_BLKSIZE 32
+
+#define MSM_GPU_RB_CNTL_DEFAULT \
+   (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \
+   AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8)))
 
 static inline struct msm_ringbuffer *__get_ring(struct msm_gpu *gpu, int index)
 {
-- 
1.9.1

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[PATCH 11/11] drm/msm: Implement preemption for A5XX targets

[Jordan Crouse]

Implement preemption for A5XX targets - this allows multiple
ringbuffers for different priorities with automatic preemption
of a lower priority ringbuffer if a higher one is ready.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 176 ++-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 102 -
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 345 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |  15 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   7 +-
 drivers/gpu/drm/msm/msm_drv.h |   2 +-
 drivers/gpu/drm/msm/msm_ringbuffer.c  |   2 +
 drivers/gpu/drm/msm/msm_ringbuffer.h  |   1 +
 9 files changed, 634 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/adreno/a5xx_preempt.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 3905536..a1d808b 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -8,6 +8,7 @@ msm-y := \
adreno/a4xx_gpu.o \
adreno/a5xx_gpu.o \
adreno/a5xx_power.o \
+   adreno/a5xx_preempt.o \
hdmi/hdmi.o \
hdmi/hdmi_audio.o \
hdmi/hdmi_bridge.o \
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 4ad98b9..fef1541 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -184,14 +184,66 @@ static int zap_load_mdt(struct platform_device *pdev)
return ret;
 }
 
+static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
+{
+   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
+   uint32_t wptr;
+   unsigned long flags;
+
+   spin_lock_irqsave(&ring->lock, flags);
+
+   /* Copy the shadow to the actual register */
+   ring->cur = ring->next;
+
+   /* Make sure to wrap wptr if we need to */
+   wptr = get_wptr(ring);
+
+   spin_unlock_irqrestore(&ring->lock, flags);
+
+   /* Make sure everything is posted before making a decision */
+   mb();
+
+   /* Update HW if this is the current ring and we are not in preempt */
+   if (a5xx_gpu->cur_ring == ring && !a5xx_in_preempt(a5xx_gpu))
+   gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
+}
+
 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
+
struct msm_drm_private *priv = gpu->dev->dev_private;
struct msm_ringbuffer *ring = submit->ring;
unsigned int i, ibs = 0;
 
+   OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Turn off protected mode to write to special registers */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 0);
+
+   /* Set the save preemption record for the ring/command */
+   OUT_PKT4(ring, REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 2);
+   OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
+   OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));
+
+   /* Turn back on protected mode */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 1);
+
+   /* Enable local preemption for finegrain preemption */
+   OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Allow CP_CONTEXT_SWITCH_YIELD packets in the IB2 */
+   OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
+   OUT_RING(ring, 0x02);
+
+   /* Submit the commands */
for (i = 0; i < submit->nr_cmds; i++) {
switch (submit->cmd[i].type) {
case MSM_SUBMIT_CMD_IB_TARGET_BUF:
@@ -209,16 +261,54 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
}
}
 
+   /*
+* Write the render mode to NULL (0) to indicate to the CP that the IBs
+* are done rendering - otherwise a lucky preemption would start
+* replaying from the last checkpoint
+*/
+   OUT_PKT7(ring, CP_SET_RENDER_MODE, 5);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+   OUT_RING(ring, 0);
+
+   /* Turn off IB level preemptions */
+   OUT_PKT7(ring, CP_YIELD_ENABLE, 1);
+   OUT_RING(ring, 0x01);
+
+   /* Write the fence to the scratch register */
OUT_PKT4(ring, REG_A5XX_CP_SCRATCH_REG(2), 1);
OUT_RING(ring, submit->fence->seqno);
 
+   /*
+* Execute a CACHE_FLUSH_TS event. This will ensure that the
+* timestamp is written to the memory and then triggers the interrupt
+*/
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));
OUT_RING(ring, lower_32_bits(

[PATCH 09/11] drm/msm: Shadow current pointer in the ring until command is complete

[Jordan Crouse]

Add a shadow pointer to track the current command being written into
the ring. Don't commit it as 'cur' until the command is submitted.
Because 'cur' is used to construct the software copy of the wptr this
ensures that somebody peeking in on the ring doesn't assume that a
command is inflight while it is being written. This isn't a huge deal
with a single ring (though technically the hangcheck could assume
the system is prematurely busy when it isn't) but it will be rather
important for preemption where the decision to preempt is based
on a non-empty ringbuffer. Without a shadow an aggressive preemption
scheme could assume that the ringbuffer is non empty and switch to it
before the CPU is done writing the command and boom.

Even though preemption won't be supported for all targets because of
the way the code is organized it is simpler to make this generic for
all targets. The extra load for non-preemption targets should be
minimal.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  9 +++--
 drivers/gpu/drm/msm/msm_ringbuffer.c|  1 +
 drivers/gpu/drm/msm/msm_ringbuffer.h| 12 
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 21c839f..b8c11a0 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -144,6 +144,7 @@ void adreno_recover(struct msm_gpu *gpu)
continue;
 
ring->cur = ring->start;
+   ring->next = ring->start;
 
/* reset completed fence seqno, discard anything pending: */
adreno_gpu->memptrs->fence[ring->id] = ring->completed_fence;
@@ -240,12 +241,15 @@ void adreno_flush(struct msm_gpu *gpu, struct 
msm_ringbuffer *ring)
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
uint32_t wptr;
 
+   /* Copy the shadow to the actual register */
+   ring->cur = ring->next;
+
/*
 * Mask wptr value that we calculate to fit in the HW range. This is
 * to account for the possibility that the last command fit exactly into
 * the ringbuffer and rb->next hasn't wrapped to zero yet
 */
-   wptr = get_wptr(ring) % (MSM_GPU_RINGBUFFER_SZ >> 2);
+   wptr = (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
 
/* ensure writes to ringbuffer have hit system memory: */
mb();
@@ -366,7 +370,8 @@ static uint32_t ring_freewords(struct msm_ringbuffer *ring)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2;
-   uint32_t wptr = get_wptr(ring);
+   /* Use ring->next to calculate free size */
+   uint32_t wptr = ring->next - ring->start;
uint32_t rptr = get_rptr(adreno_gpu, ring);
return (rptr + (size - 1) - wptr) % size;
 }
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c 
b/drivers/gpu/drm/msm/msm_ringbuffer.c
index 2ab31c7..b885979 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -47,6 +47,7 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu 
*gpu, int id)
goto fail;
}
ring->end   = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2);
+   ring->next  = ring->start;
ring->cur   = ring->start;
 
return ring;
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h 
b/drivers/gpu/drm/msm/msm_ringbuffer.h
index 4eb05fe..865b21a 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.h
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.h
@@ -24,7 +24,7 @@ struct msm_ringbuffer {
struct msm_gpu *gpu;
int id;
struct drm_gem_object *bo;
-   uint32_t *start, *end, *cur;
+   uint32_t *start, *end, *cur, *next;
uint64_t iova;
/* last_fence == completed_fence --> no pending work */
uint32_t last_fence;
@@ -39,9 +39,13 @@ struct msm_ringbuffer {
 static inline void
 OUT_RING(struct msm_ringbuffer *ring, uint32_t data)
 {
-   if (ring->cur == ring->end)
-   ring->cur = ring->start;
-   *(ring->cur++) = data;
+   /*
+* ring->next points to the current command being written - it won't be
+* committed as ring->cur until the flush
+*/
+   if (ring->next == ring->end)
+   ring->next = ring->start;
+   *(ring->next++) = data;
 }
 
 #endif /* __MSM_RINGBUFFER_H__ */
-- 
1.9.1

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[PATCH 05/11] drm/msm: get an iova from the address space instead of an id

[Jordan Crouse]

In the future we won't have a fixed set of addresses spaces.
Instead of going through the effort of assigning a ID for each
address space just use the address space itself as a token for
getting / putting an iova.

This forces a few changes in the gem object however: instead
of using a simple index into a list of domains, we need to
maintain a list of them. Luckily the list will be pretty small;
even with dynamic address spaces we wouldn't ever see more than
two or three.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c |   8 +-
 drivers/gpu/drm/msm/adreno/a5xx_power.c   |   5 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |   6 +-
 drivers/gpu/drm/msm/dsi/dsi_host.c|  15 +++-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c  |   8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  18 ++--
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c |  13 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c  |   5 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c   |  11 +--
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h   |   4 -
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c |  13 +--
 drivers/gpu/drm/msm/msm_drv.c |  15 +---
 drivers/gpu/drm/msm/msm_drv.h |  25 +++---
 drivers/gpu/drm/msm/msm_fb.c  |  15 ++--
 drivers/gpu/drm/msm/msm_fbdev.c   |  10 ++-
 drivers/gpu/drm/msm/msm_gem.c | 134 +-
 drivers/gpu/drm/msm/msm_gem.h |   4 +-
 drivers/gpu/drm/msm/msm_gem_submit.c  |   4 +-
 drivers/gpu/drm/msm/msm_gpu.c |   8 +-
 drivers/gpu/drm/msm/msm_gpu.h |   1 -
 drivers/gpu/drm/msm/msm_kms.h |   3 +
 22 files changed, 194 insertions(+), 135 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 5d3c4ff..25ab1f4 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -415,7 +415,7 @@ static struct drm_gem_object *a5xx_ucode_load_bo(struct 
msm_gpu *gpu,
}
 
if (iova) {
-   int ret = msm_gem_get_iova(bo, gpu->id, iova);
+   int ret = msm_gem_get_iova(bo, gpu->aspace, iova);
 
if (ret) {
drm_gem_object_unreference_unlocked(bo);
@@ -757,19 +757,19 @@ static void a5xx_destroy(struct msm_gpu *gpu)
 
if (a5xx_gpu->pm4_bo) {
if (a5xx_gpu->pm4_iova)
-   msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->pm4_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->pm4_bo);
}
 
if (a5xx_gpu->pfp_bo) {
if (a5xx_gpu->pfp_iova)
-   msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->pfp_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->pfp_bo);
}
 
if (a5xx_gpu->gpmu_bo) {
if (a5xx_gpu->gpmu_iova)
-   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
}
 
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c 
b/drivers/gpu/drm/msm/adreno/a5xx_power.c
index ed0802e..2fdee44 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
@@ -301,7 +301,8 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
if (IS_ERR(a5xx_gpu->gpmu_bo))
goto err;
 
-   if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->id, &a5xx_gpu->gpmu_iova))
+   if (msm_gem_get_iova(a5xx_gpu->gpmu_bo, gpu->aspace,
+   &a5xx_gpu->gpmu_iova))
goto err;
 
ptr = msm_gem_get_vaddr(a5xx_gpu->gpmu_bo);
@@ -330,7 +331,7 @@ void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
 
 err:
if (a5xx_gpu->gpmu_iova)
-   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
+   msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
if (a5xx_gpu->gpmu_bo)
drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
 
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 35a6849..959876d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -61,7 +61,7 @@ int adreno_hw_init(struct msm_gpu *gpu)
 
DBG("%s", gpu->name);
 
-   ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
+   ret = msm_gem_get_iova(gpu->rb->bo, gpu->aspace, &gpu->rb_iova);
if (ret) {
gpu->rb_iova = 0;
dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
@@ -410,7 +410,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
return -ENOMEM;
}
 
-   ret = msm_gem_get_iova(adreno_gpu->mempt

[PATCH 03/11] drm/msm: Remove idle function hook

[Jordan Crouse]

There isn't any generic code that uses ->idle so remove it.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 4 ++--
 drivers/gpu/drm/msm/adreno/a4xx_gpu.c   | 4 ++--
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c   | 9 -
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h   | 1 +
 drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +-
 drivers/gpu/drm/msm/msm_gpu.h   | 1 -
 6 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index b999349..fc4fd2d 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -40,6 +40,7 @@
 extern bool hang_debug;
 
 static void a3xx_dump(struct msm_gpu *gpu);
+static bool a3xx_idle(struct msm_gpu *gpu);
 
 static bool a3xx_me_init(struct msm_gpu *gpu)
 {
@@ -65,7 +66,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
 
gpu->funcs->flush(gpu);
-   return gpu->funcs->idle(gpu);
+   return a3xx_idle(gpu);
 }
 
 static int a3xx_hw_init(struct msm_gpu *gpu)
@@ -448,7 +449,6 @@ static void a3xx_dump(struct msm_gpu *gpu)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
-   .idle = a3xx_idle,
.irq = a3xx_irq,
.destroy = a3xx_destroy,
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 511bc85..6bc948b 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -31,6 +31,7 @@
 
 extern bool hang_debug;
 static void a4xx_dump(struct msm_gpu *gpu);
+static bool a4xx_idle(struct msm_gpu *gpu);
 
 /*
  * a4xx_enable_hwcg() - Program the clock control registers
@@ -137,7 +138,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x);
 
gpu->funcs->flush(gpu);
-   return gpu->funcs->idle(gpu);
+   return a4xx_idle(gpu);
 }
 
 static int a4xx_hw_init(struct msm_gpu *gpu)
@@ -538,7 +539,6 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t 
*value)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
-   .idle = a4xx_idle,
.irq = a4xx_irq,
.destroy = a4xx_destroy,
 #ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 9d754a7..5d3c4ff 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -391,7 +391,7 @@ static int a5xx_me_init(struct msm_gpu *gpu)
 
gpu->funcs->flush(gpu);
 
-   return gpu->funcs->idle(gpu) ? 0 : -EINVAL;
+   return a5xx_idle(gpu) ? 0 : -EINVAL;
 }
 
 static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
@@ -699,7 +699,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x0F);
 
gpu->funcs->flush(gpu);
-   if (!gpu->funcs->idle(gpu))
+   if (!a5xx_idle(gpu))
return -EINVAL;
}
 
@@ -716,7 +716,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x);
 
gpu->funcs->flush(gpu);
-   if (!gpu->funcs->idle(gpu))
+   if (!a5xx_idle(gpu))
return -EINVAL;
} else {
/* Print a warning so if we die, we know why */
@@ -790,7 +790,7 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
 }
 
-static bool a5xx_idle(struct msm_gpu *gpu)
+bool a5xx_idle(struct msm_gpu *gpu)
 {
/* wait for CP to drain ringbuffer: */
if (!adreno_idle(gpu))
@@ -1099,7 +1099,6 @@ static void a5xx_show(struct msm_gpu *gpu, struct 
seq_file *m)
.last_fence = adreno_last_fence,
.submit = a5xx_submit,
.flush = adreno_flush,
-   .idle = a5xx_idle,
.irq = a5xx_irq,
.destroy = a5xx_destroy,
.show = a5xx_show,
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index 1590f84..6b20f28 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -56,5 +56,6 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t 
usecs,
return -ETIMEDOUT;
 }
 
+bool a5xx_idle(struct msm_gpu *gpu);
 
 #endif /* __A5XX_GPU_H__ */
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c 
b/drivers/gpu/drm/msm/adreno/a5xx_power.c
index 72d52c7..ed0802e 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_power.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c
@@ -194,7 +194,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
 
gpu->funcs->flush(gpu);
 
-   if (!gpu->funcs->idle(gpu)) {
+   if (!a5xx_idle(gpu

[PATCH 0/6] drm/msm: New features for 4.12

[Jordan Crouse]

Hey Rob - here are a handful of new features and more extensive bug fixes that
might be suitable for 4.12.

Of note is the reference count for address spaces which is a pre-requisite for
per-instance pagetables and the move to OPP tables which is a stepping stone for
all sorts of clock related shenanigans.

Thanks!
Jordan

Jordan Crouse (6):
  drm/msm: Don't allow zero sized buffer objects
  drm/msm: Reference count address spaces
  drm/msm: Add MSM_PARAM_GMEM_BASE
  drm/msm: Hard code the GPU "slow frequency"
  drm/msm: gpu: Use OPP tables if we can
  msm/drm: gpu: Dynamically locate the clocks from the device tree

 drivers/gpu/drm/msm/adreno/adreno_device.c | 90 ++
 drivers/gpu/drm/msm/adreno/adreno_gpu.c| 10 ++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|  2 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c|  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c|  2 +-
 drivers/gpu/drm/msm/msm_drv.h  |  3 +-
 drivers/gpu/drm/msm/msm_gem.c  |  6 ++
 drivers/gpu/drm/msm/msm_gem.h  |  2 +
 drivers/gpu/drm/msm/msm_gem_vma.c  | 35 +---
 drivers/gpu/drm/msm/msm_gpu.c  | 82 +++
 drivers/gpu/drm/msm/msm_gpu.h  |  6 +-
 include/uapi/drm/msm_drm.h |  1 +
 12 files changed, 176 insertions(+), 65 deletions(-)

-- 
1.9.1

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[PATCH 1/6] drm/msm: Don't allow zero sized buffer objects

[Jordan Crouse]

Zero sized buffer objects tend to make various bits of the GEM
infrastructure complain:

 WARNING: CPU: 1 PID: 2323 at drivers/gpu/drm/drm_mm.c:389 
drm_mm_insert_node_generic+0x258/0x2f0
 Modules linked in:

 CPU: 1 PID: 2323 Comm: drm-api-test Tainted: GW 
4.9.0-rc4-00906-g693af44 #213
 Hardware name: Qualcomm Technologies, Inc. DB820c (DT)
 task: 8000d7353400 task.stack: 8000d772
 PC is at drm_mm_insert_node_generic+0x258/0x2f0
 LR is at drm_vma_offset_add+0x4c/0x70

Zero sized buffers serve no appreciable value to the user so disallow
them at create time.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_gem.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 4c3e6ef..e819b83 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -874,6 +874,12 @@ struct drm_gem_object *msm_gem_new(struct drm_device *dev,
 
size = PAGE_ALIGN(size);
 
+   /* Disallow zero sized objects as they make the underlying
+* infrastructure grumpy
+*/
+   if (size == 0)
+   return ERR_PTR(-EINVAL);
+
ret = msm_gem_new_impl(dev, size, flags, NULL, &obj);
if (ret)
goto fail;
-- 
1.9.1

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[PATCH 5/6] drm/msm: gpu: Use OPP tables if we can

[Jordan Crouse]

If a OPP table is defined for the GPU device in the device tree use
that in lieu of the downstream style GPU frequency table. If we do
use the downstream table convert it to a OPP table so that we can
take advantage of the OPP lookup facilities later.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 85 +++---
 1 file changed, 66 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 8374e9a..24da7f6 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -17,6 +17,7 @@
  * this program.  If not, see .
  */
 
+#include 
 #include "adreno_gpu.h"
 
 #define ANY_ID 0xff
@@ -220,10 +221,71 @@ static int find_chipid(struct device *dev, u32 *chipid)
return 0;
 }
 
+/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */
+static int adreno_get_legacy_pwrlevels(struct device *dev)
+{
+   struct device_node *child, *node;
+   int ret;
+
+   node = of_find_compatible_node(dev->of_node, NULL,
+   "qcom,gpu-pwrlevels");
+   if (!node) {
+   dev_err(dev, "Could not find the GPU powerlevels\n");
+   return -ENXIO;
+   }
+
+   for_each_child_of_node(node, child) {
+   unsigned int val;
+
+   ret = of_property_read_u32(child, "qcom,gpu-freq", &val);
+   if (ret)
+   continue;
+
+   /*
+* Skip the intentionally bogus clock value found at the bottom
+* of most legacy frequency tables
+*/
+   if (val != 2700)
+   dev_pm_opp_add(dev, val, 0);
+   }
+
+   return 0;
+}
+
+static int adreno_get_pwrlevels(struct device *dev,
+   struct adreno_platform_config *config)
+{
+   unsigned long freq = ULONG_MAX;
+   struct dev_pm_opp *opp;
+   int ret;
+
+   /* You down with OPP? */
+   if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
+   ret = adreno_get_legacy_pwrlevels(dev);
+   else
+   ret = dev_pm_opp_of_add_table(dev);
+
+   if (ret)
+   return ret;
+
+   /* Find the fastest defined rate */
+   opp = dev_pm_opp_find_freq_floor(dev, &freq);
+   if (!IS_ERR(opp))
+   config->fast_rate = dev_pm_opp_get_freq(opp);
+
+   if (!config->fast_rate) {
+   DRM_DEV_INFO(dev,
+   "Could not find clock rate. Using default\n");
+   /* Pick a suitably safe clock speed for any target */
+   config->fast_rate = 2;
+   }
+
+   return 0;
+}
+
 static int adreno_bind(struct device *dev, struct device *master, void *data)
 {
static struct adreno_platform_config config = {};
-   struct device_node *child, *node = dev->of_node;
u32 val;
int ret;
 
@@ -238,25 +300,10 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
 
/* find clock rates: */
config.fast_rate = 0;
-   for_each_child_of_node(node, child) {
-   if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
-   struct device_node *pwrlvl;
-   for_each_child_of_node(child, pwrlvl) {
-   ret = of_property_read_u32(pwrlvl, 
"qcom,gpu-freq", &val);
-   if (ret) {
-   dev_err(dev, "could not find gpu-freq: 
%d\n", ret);
-   return ret;
-   }
-   config.fast_rate = max(config.fast_rate, val);
-   }
-   }
-   }
 
-   if (!config.fast_rate) {
-   dev_warn(dev, "could not find clk rates\n");
-   /* This is a safe low speed for all devices: */
-   config.fast_rate = 2;
-   }
+   ret = adreno_get_pwrlevels(dev, &config);
+   if (ret)
+   return ret;
 
dev->platform_data = &config;
set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
-- 
1.9.1

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[PATCH 6/6] msm/drm: gpu: Dynamically locate the clocks from the device tree

[Jordan Crouse]

Instead of using a fixed list of clock names use the clock-names
list in the device tree to discover and get the list of clocks
that we need.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_gpu.c | 76 ++-
 drivers/gpu/drm/msm/msm_gpu.h |  4 ++-
 2 files changed, 57 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 2b731e7..25de46f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -93,18 +93,18 @@ static int enable_clk(struct msm_gpu *gpu)
 {
int i;
 
-   if (gpu->grp_clks[0] && gpu->fast_rate)
-   clk_set_rate(gpu->grp_clks[0], gpu->fast_rate);
+   if (gpu->core_clk && gpu->fast_rate)
+   clk_set_rate(gpu->core_clk, gpu->fast_rate);
 
/* Set the RBBM timer rate to 19.2Mhz */
-   if (gpu->grp_clks[2])
-   clk_set_rate(gpu->grp_clks[2], 1920);
+   if (gpu->rbbmtimer_clk)
+   clk_set_rate(gpu->rbbmtimer_clk, 1920);
 
-   for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
+   for (i = gpu->nr_clocks - 1; i >= 0; i--)
if (gpu->grp_clks[i])
clk_prepare(gpu->grp_clks[i]);
 
-   for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
+   for (i = gpu->nr_clocks - 1; i >= 0; i--)
if (gpu->grp_clks[i])
clk_enable(gpu->grp_clks[i]);
 
@@ -115,11 +115,11 @@ static int disable_clk(struct msm_gpu *gpu)
 {
int i;
 
-   for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
+   for (i = gpu->nr_clocks - 1; i >= 0; i--)
if (gpu->grp_clks[i])
clk_disable(gpu->grp_clks[i]);
 
-   for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i >= 0; i--)
+   for (i = gpu->nr_clocks - 1; i >= 0; i--)
if (gpu->grp_clks[i])
clk_unprepare(gpu->grp_clks[i]);
 
@@ -128,10 +128,11 @@ static int disable_clk(struct msm_gpu *gpu)
 * speed had to be non zero to avoid problems. On newer targets this
 * will be rounded down to zero anyway so it all works out.
 */
-   clk_set_rate(gpu->grp_clks[0], 2700);
+   if (gpu->core_clk)
+   clk_set_rate(gpu->core_clk, 2700);
 
-   if (gpu->grp_clks[2])
-   clk_set_rate(gpu->grp_clks[2], 0);
+   if (gpu->rbbmtimer_clk)
+   clk_set_rate(gpu->rbbmtimer_clk, 0);
 
return 0;
 }
@@ -586,9 +587,45 @@ static irqreturn_t irq_handler(int irq, void *data)
return gpu->funcs->irq(gpu);
 }
 
-static const char *clk_names[] = {
-   "core", "iface", "rbbmtimer", "mem", "mem_iface", "alt_mem_iface",
-};
+static struct clk *get_clock(struct device *dev, const char *name)
+{
+   struct clk *clk = devm_clk_get(dev, name);
+
+   return IS_ERR(clk) ? NULL : clk;
+}
+
+static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
+{
+   struct device *dev = &pdev->dev;
+   struct property *prop;
+   const char *name;
+   int i = 0;
+
+   gpu->nr_clocks = of_property_count_strings(dev->of_node, "clock-names");
+   if (gpu->nr_clocks < 1) {
+   gpu->nr_clocks = 0;
+   return 0;
+   }
+
+   gpu->grp_clks = devm_kcalloc(dev, sizeof(struct clk *), gpu->nr_clocks,
+   GFP_KERNEL);
+   if (!gpu->grp_clks)
+   return -ENOMEM;
+
+   of_property_for_each_string(dev->of_node, "clock-names", prop, name) {
+   gpu->grp_clks[i] = get_clock(dev, name);
+
+   /* Remember the key clocks that we need to control later */
+   if (!strcmp(name, "core"))
+   gpu->core_clk = gpu->grp_clks[i];
+   else if (!strcmp(name, "rbbmtimer"))
+   gpu->rbbmtimer_clk = gpu->grp_clks[i];
+
+   ++i;
+   }
+
+   return 0;
+}
 
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
@@ -625,7 +662,6 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
 
spin_lock_init(&gpu->perf_lock);
 
-   BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
 
/* Map registers: */
gpu->mmio = msm_ioremap(pdev, config->ioname, name);
@@ -649,13 +685,9 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
goto fail;
}
 
-   /* Acquire clocks: */
-   for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
-   gpu->grp_clks[i] = msm_clk_get(pdev, clk_names[i]);
-   DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
-   if (IS_ERR(gpu->grp_clks[i]))
-   gpu->grp_clks[i] = NULL;
-   }
+   ret = get_clocks(pdev, gpu);
+   if (ret)
+   goto fail;
 
gpu->ebi1_clk = msm_clk_get(pdev, "bus");

[PATCH 2/6] drm/msm: Reference count address spaces

[Jordan Crouse]

There are reasons for a memory object to outlive the file descriptor
that created it and so the address space that a buffer object is
attached to must also outlive the file descriptor. Reference count
the address space so that it can remain viable until all the objects
have released their addresses.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  2 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c |  2 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  2 +-
 drivers/gpu/drm/msm/msm_drv.h   |  3 ++-
 drivers/gpu/drm/msm/msm_gem.h   |  2 ++
 drivers/gpu/drm/msm/msm_gem_vma.c   | 35 -
 6 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 2debc76..18a4f74 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -498,6 +498,6 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu)
if (gpu->aspace) {
gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
iommu_ports, ARRAY_SIZE(iommu_ports));
-   msm_gem_address_space_destroy(gpu->aspace);
+   msm_gem_address_space_put(gpu->aspace);
}
 }
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
index 239a202..ea1dab7 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
@@ -168,7 +168,7 @@ static void mdp4_destroy(struct msm_kms *kms)
if (aspace) {
aspace->mmu->funcs->detach(aspace->mmu,
iommu_ports, ARRAY_SIZE(iommu_ports));
-   msm_gem_address_space_destroy(aspace);
+   msm_gem_address_space_put(aspace);
}
 
drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 889dd5d..fa4096a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -168,7 +168,7 @@ static void mdp5_kms_destroy(struct msm_kms *kms)
if (aspace) {
aspace->mmu->funcs->detach(aspace->mmu,
iommu_ports, ARRAY_SIZE(iommu_ports));
-   msm_gem_address_space_destroy(aspace);
+   msm_gem_address_space_put(aspace);
}
 
/*
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 08ad9e4..e740fa5 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -190,7 +190,8 @@ void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
 int msm_gem_map_vma(struct msm_gem_address_space *aspace,
struct msm_gem_vma *vma, struct sg_table *sgt, int npages);
 
-void msm_gem_address_space_destroy(struct msm_gem_address_space *aspace);
+void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
+
 struct msm_gem_address_space *
 msm_gem_address_space_create(struct device *dev, struct iommu_domain *domain,
const char *name);
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index 633b5c1..c57b54e 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -18,6 +18,7 @@
 #ifndef __MSM_GEM_H__
 #define __MSM_GEM_H__
 
+#include 
 #include 
 #include "msm_drv.h"
 
@@ -31,6 +32,7 @@ struct msm_gem_address_space {
 */
struct drm_mm mm;
struct msm_mmu *mmu;
+   struct kref kref;
 };
 
 struct msm_gem_vma {
diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c 
b/drivers/gpu/drm/msm/msm_gem_vma.c
index a311d26..2b1d2cb 100644
--- a/drivers/gpu/drm/msm/msm_gem_vma.c
+++ b/drivers/gpu/drm/msm/msm_gem_vma.c
@@ -19,6 +19,25 @@
 #include "msm_gem.h"
 #include "msm_mmu.h"
 
+static void
+msm_gem_address_space_destroy(struct kref *kref)
+{
+   struct msm_gem_address_space *aspace = container_of(kref,
+   struct msm_gem_address_space, kref);
+
+   drm_mm_takedown(&aspace->mm);
+   if (aspace->mmu)
+   aspace->mmu->funcs->destroy(aspace->mmu);
+   kfree(aspace);
+}
+
+
+void msm_gem_address_space_put(struct msm_gem_address_space *aspace)
+{
+   if (aspace)
+   kref_put(&aspace->kref, msm_gem_address_space_destroy);
+}
+
 void
 msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
struct msm_gem_vma *vma, struct sg_table *sgt)
@@ -34,6 +53,8 @@
drm_mm_remove_node(&vma->node);
 
vma->iova = 0;
+
+   msm_gem_address_space_put(aspace);
 }
 
 int
@@ -58,16 +79,10 @@
size, IOMMU_READ | IOMMU_WRITE);
}
 
-   return ret;
-}
+   /* Get a reference to the aspace to keep it around */
+   kref_get(&aspace->kref);
 
-void
-msm_gem_address_space_destroy(struct msm_gem_address_space *aspace)
-{
-   drm_mm_takedown(&aspace->mm

[PATCH 4/6] drm/msm: Hard code the GPU "slow frequency"

[Jordan Crouse]

Some A3XX and A4XX GPU targets required that the GPU clock be
programmed to a non zero value when it was disabled so
27Mhz was chosen as the "invalid" frequency.

Even though newer targets do not have the same clock restrictions
we still write 27Mhz on clock disable and expect the clock subsystem
to round down to zero.

For unknown reasons even though the slow clock speed is always
27Mhz and it isn't actually a functional level the legacy device tree
frequency tables always defined it and then did gymnastics to work
around it.

Instead of playing the same silly games just hard code the "slow" clock
speed in the code as 27MHz and save ourselves a bit of infrastructure.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c| 5 ++---
 drivers/gpu/drm/msm/adreno/adreno_gpu.h| 2 +-
 drivers/gpu/drm/msm/msm_gpu.c  | 8 ++--
 drivers/gpu/drm/msm/msm_gpu.h  | 2 +-
 5 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c 
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 6e060e7..8374e9a 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -2,7 +2,7 @@
  * Copyright (C) 2013-2014 Red Hat
  * Author: Rob Clark 
  *
- * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 as published by
@@ -238,7 +238,6 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
 
/* find clock rates: */
config.fast_rate = 0;
-   config.slow_rate = ~0;
for_each_child_of_node(node, child) {
if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
struct device_node *pwrlvl;
@@ -249,7 +248,6 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
return ret;
}
config.fast_rate = max(config.fast_rate, val);
-   config.slow_rate = min(config.slow_rate, val);
}
}
}
@@ -258,7 +256,6 @@ static int adreno_bind(struct device *dev, struct device 
*master, void *data)
dev_warn(dev, "could not find clk rates\n");
/* This is a safe low speed for all devices: */
config.fast_rate = 2;
-   config.slow_rate = 2700;
}
 
dev->platform_data = &config;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index dcbf3ea..b41bd88 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -407,14 +407,13 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
adreno_gpu->rev = config->rev;
 
gpu->fast_rate = config->fast_rate;
-   gpu->slow_rate = config->slow_rate;
gpu->bus_freq  = config->bus_freq;
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
gpu->bus_scale_table = config->bus_scale_table;
 #endif
 
-   DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
-   gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
+   DBG("fast_rate=%u, slow_rate=2700, bus_freq=%u",
+   gpu->fast_rate, gpu->bus_freq);
 
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
adreno_gpu_config.irqname = "kgsl_3d0_irq";
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 4a3630f..841ec30 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -128,7 +128,7 @@ struct adreno_gpu {
 /* platform config data (ie. from DT, or pdata) */
 struct adreno_platform_config {
struct adreno_rev rev;
-   uint32_t fast_rate, slow_rate, bus_freq;
+   uint32_t fast_rate, bus_freq;
 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
struct msm_bus_scale_pdata *bus_scale_table;
 #endif
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index c7969f5..2b731e7 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -123,8 +123,12 @@ static int disable_clk(struct msm_gpu *gpu)
if (gpu->grp_clks[i])
clk_unprepare(gpu->grp_clks[i]);
 
-   if (gpu->grp_clks[0] && gpu->slow_rate)
-   clk_set_rate(gpu->grp_clks[0], gpu->slow_rate);
+   /*
+* Set the clock to a deliberately low rate. On older targets the clock
+* speed had to be non zero to avoid problems. On newer targets this
+* will be rounded down to zero anyway so it all works out.
+*/
+   clk_set_r

[PATCH 3/6] drm/msm: Add MSM_PARAM_GMEM_BASE

[Jordan Crouse]

User space needs to know where the GMEM whole starts so that they
can set up the addressing correctly.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
 include/uapi/drm/msm_drm.h  | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 18a4f74..dcbf3ea 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -33,6 +33,9 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, 
uint64_t *value)
case MSM_PARAM_GMEM_SIZE:
*value = adreno_gpu->gmem;
return 0;
+   case MSM_PARAM_GMEM_BASE:
+   *value = 0x10;
+   return 0;
case MSM_PARAM_CHIP_ID:
*value = adreno_gpu->rev.patchid |
(adreno_gpu->rev.minor << 8) |
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 915634b..c8244f4 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -72,6 +72,7 @@ struct drm_msm_timespec {
 #define MSM_PARAM_CHIP_ID0x03
 #define MSM_PARAM_MAX_FREQ   0x04
 #define MSM_PARAM_TIMESTAMP  0x05
+#define MSM_PARAM_GMEM_BASE  0x06
 
 struct drm_msm_param {
__u32 pipe;   /* in, MSM_PIPE_x */
-- 
1.9.1

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[PATCH 2/6] drm/msm: Pass the MMU domain index in struct msm_file_private

[Jordan Crouse]

Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_drv.c|  2 ++
 drivers/gpu/drm/msm/msm_drv.h|  6 +-
 drivers/gpu/drm/msm/msm_gem.h|  1 +
 drivers/gpu/drm/msm/msm_gem_submit.c | 12 
 drivers/gpu/drm/msm/msm_gpu.c|  3 +--
 5 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index b03e785..7b7a2e7 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -507,6 +507,7 @@ static void load_gpu(struct drm_device *dev)
 
 static int msm_open(struct drm_device *dev, struct drm_file *file)
 {
+   struct msm_drm_private *priv = dev->dev_private;
struct msm_file_private *ctx;
 
/* For now, load gpu on open.. to avoid the requirement of having
@@ -518,6 +519,7 @@ static int msm_open(struct drm_device *dev, struct drm_file 
*file)
if (!ctx)
return -ENOMEM;
 
+   ctx->aspace = priv->gpu->aspace;
file->driver_priv = ctx;
 
return 0;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index e740fa5..bbad6c7 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -58,11 +58,7 @@
 #define NUM_DOMAINS 2/* one for KMS, then one per gpu core (?) */
 
 struct msm_file_private {
-   /* currently we don't do anything useful with this.. but when
-* per-context address spaces are supported we'd keep track of
-* the context's page-tables here.
-*/
-   int dummy;
+   struct msm_gem_address_space *aspace;
 };
 
 enum msm_mdp_plane_property {
diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h
index c57b54e..74a2e67 100644
--- a/drivers/gpu/drm/msm/msm_gem.h
+++ b/drivers/gpu/drm/msm/msm_gem.h
@@ -116,6 +116,7 @@ static inline bool is_vunmapable(struct msm_gem_object 
*msm_obj)
 struct msm_gem_submit {
struct drm_device *dev;
struct msm_gpu *gpu;
+   struct msm_gem_address_space *aspace;
struct list_head node;   /* node in gpu submit_list */
struct list_head bo_list;
struct ww_acquire_ctx ticket;
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c 
b/drivers/gpu/drm/msm/msm_gem_submit.c
index d8021a0..214e6d9 100644
--- a/drivers/gpu/drm/msm/msm_gem_submit.c
+++ b/drivers/gpu/drm/msm/msm_gem_submit.c
@@ -31,17 +31,20 @@
 #define BO_PINNED   0x2000
 
 static struct msm_gem_submit *submit_create(struct drm_device *dev,
-   struct msm_gpu *gpu, int nr_bos, int nr_cmds)
+   struct msm_gpu *gpu, struct msm_gem_address_space *aspace,
+   int nr_bos, int nr_cmds)
 {
struct msm_gem_submit *submit;
int sz = sizeof(*submit) + (nr_bos * sizeof(submit->bos[0])) +
(nr_cmds * sizeof(*submit->cmd));
 
submit = kmalloc(sz, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
+
if (!submit)
return NULL;
 
submit->dev = dev;
+   submit->aspace = aspace;
submit->gpu = gpu;
submit->fence = NULL;
submit->pid = get_pid(task_pid(current));
@@ -158,7 +161,7 @@ static void submit_unlock_unpin_bo(struct msm_gem_submit 
*submit, int i)
struct msm_gem_object *msm_obj = submit->bos[i].obj;
 
if (submit->bos[i].flags & BO_PINNED)
-   msm_gem_put_iova(&msm_obj->base, submit->gpu->aspace);
+   msm_gem_put_iova(&msm_obj->base, submit->aspace);
 
if (submit->bos[i].flags & BO_LOCKED)
ww_mutex_unlock(&msm_obj->resv->lock);
@@ -246,7 +249,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit)
 
/* if locking succeeded, pin bo: */
ret = msm_gem_get_iova_locked(&msm_obj->base,
-   submit->gpu->aspace, &iova);
+   submit->aspace, &iova);
 
if (ret)
break;
@@ -417,7 +420,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
}
priv->struct_mutex_task = current;
 
-   submit = submit_create(dev, gpu, args->nr_bos, args->nr_cmds);
+   submit = submit_create(dev, gpu, ctx->aspace, args->nr_bos,
+   args->nr_cmds);
if (!submit) {
ret = -ENOMEM;
goto out_unlock;
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 25de46f..f7f85bd 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -562,8 +562,7 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
 
/* submit takes a reference to the bo and iova until retired: */
drm_gem_object_reference(&msm_obj->base);
-   msm_gem_get_iova_locked(&msm_obj->base,
-   submit->gpu->aspace, &iova

[PATCH 1/6] drm/msm: Enable 64 bit mode by default

[Jordan Crouse]

A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers
and the microcode use 64 bit virtual addressing in either case but the
upper 32 bits are ignored if the GPU is in 32 bit mode. There is no
performance disadvantage to remaining in 64 bit mode even if we are
only generating 32 bit addresses so switch over now to prepare for
using addresses above 4G for targets that support them.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
 drivers/gpu/drm/msm/msm_iommu.c   |  7 +++
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index fef1541..06238b7 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -800,6 +800,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x);
gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x);
 
+   /* Put the GPU into 64 bit by default */
+   gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
+   gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
+
/* Load the GPMU firmware before starting the HW init */
a5xx_gpmu_ucode_init(gpu);
 
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 7521582..d520db2 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -34,10 +34,9 @@ static int msm_fault_handler(struct iommu_domain *domain, 
struct device *dev,
if (iommu->base.handler)
ret = iommu->base.handler(iommu->base.arg, iova, flags);
else
-   pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, 
flags);
+   pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, 
flags);
 
iommu_domain_resume(domain, false);
-
return 0;
 }
 
@@ -104,7 +103,7 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
dma_addr_t pa = sg_phys(sg) - sg->offset;
size_t bytes = sg->length + sg->offset;
 
-   VERB("map[%d]: %08lx %08lx(%zx)", i, da, (unsigned long)pa, 
bytes);
+   VERB("map[%d]: %16lx %16lx(%zx)", i, da, (unsigned long)pa, 
bytes);
 
ret = iommu_map(domain, da, pa, bytes, prot);
if (ret)
@@ -143,7 +142,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t 
iova,
if (unmapped < bytes)
return unmapped;
 
-   VERB("unmap[%d]: %08lx(%zx)", i, da, bytes);
+   VERB("unmap[%d]: %16lx(%zx)", i, da, bytes);
 
BUG_ON(!PAGE_ALIGNED(bytes));
 
-- 
1.9.1

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[PATCH 4/6] drm/msm: Use TTBR1 for kernel side GPU buffer objects

[Jordan Crouse]

Use a TTBR1 pagetable for the GPU IOMMU domain and map all
the GPU kernel side buffer objects into that range.  This
will make it easier to switch out TTBR0 for per-process
pagetables.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 --
 drivers/gpu/drm/msm/msm_iommu.c |  7 +++
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index b41bd88..d7864ac 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -418,8 +418,22 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
adreno_gpu_config.ioname = "kgsl_3d0_reg_memory";
adreno_gpu_config.irqname = "kgsl_3d0_irq";
 
-   adreno_gpu_config.va_start = SZ_16M;
-   adreno_gpu_config.va_end = 0x;
+   if (adreno_gpu->revn >= 500) {
+   /*
+* By default map all A5XX buffers into the TTBR1 va space.
+* If per-instance pagetables are used then they will
+* use their own address space and the default domain will only
+* be used for kernel buffers. If per-instance pagetables aren't
+* enabled then we'll end up using the TTBR1 range as the
+* default global pagetable but that's okay because we have
+* plenty of room.
+*/
+   adreno_gpu_config.va_start = 0xfff8ULL;
+   adreno_gpu_config.va_end =   0xfff8ULL;
+   } else {
+   adreno_gpu_config.va_start = SZ_16M;
+   adreno_gpu_config.va_end = 0x;
+   }
 
adreno_gpu_config.nr_rings = nr_rings;
 
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index c1bfc92..cc82410 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -83,6 +83,13 @@ static int msm_iommu_v2_attach(struct msm_mmu *mmu, const 
char * const *names,
   int cnt)
 {
struct msm_iommu *iommu = to_msm_iommu(mmu);
+   int val = 1;
+
+   /* Use TTBR1 if it exists */
+   /* FIXME: This should only be for GPU and in theory only for A5XX */
+
+   iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_ENABLE_TTBR1,
+   &val);
 
return iommu_attach_device(iommu->domain, mmu->dev);
 }
-- 
1.9.1

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[PATCH 3/6] drm/msm: Make separate iommu function tables for v1 and v2 MMUs

[Jordan Crouse]

Since we have the infrastructure for IOMMU function tables it makes
sense to use it to differentiate between v1 and v2 targets. It adds
a bit more infrastructure but it also gives us the freedom to expand
on each flavor (especially v2) for things like dynamic domains.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_iommu.c | 60 -
 1 file changed, 41 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index d520db2..c1bfc92 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -21,7 +21,6 @@
 struct msm_iommu {
struct msm_mmu base;
struct iommu_domain *domain;
-   bool has_ctx;
 };
 #define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
 
@@ -40,15 +39,12 @@ static int msm_fault_handler(struct iommu_domain *domain, 
struct device *dev,
return 0;
 }
 
-static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names,
-   int cnt)
+static int msm_iommu_v1_attach(struct msm_mmu *mmu, const char *const *names,
+  int cnt)
 {
struct msm_iommu *iommu = to_msm_iommu(mmu);
int i, ret;
 
-   if (!iommu->has_ctx)
-   return iommu_attach_device(iommu->domain, mmu->dev);
-
for (i = 0; i < cnt; i++) {
struct device *ctx = msm_iommu_get_ctx(names[i]);
 
@@ -67,15 +63,12 @@ static int msm_iommu_attach(struct msm_mmu *mmu, const char 
* const *names,
return 0;
 }
 
-static void msm_iommu_detach(struct msm_mmu *mmu, const char * const *names,
-int cnt)
+static void msm_iommu_v1_detach(struct msm_mmu *mmu, const char * const *names,
+   int cnt)
 {
struct msm_iommu *iommu = to_msm_iommu(mmu);
int i;
 
-   if (!iommu->has_ctx)
-   iommu_detach_device(iommu->domain, mmu->dev);
-
for (i = 0; i < cnt; i++) {
struct device *ctx = msm_iommu_get_ctx(names[i]);
 
@@ -86,6 +79,22 @@ static void msm_iommu_detach(struct msm_mmu *mmu, const char 
* const *names,
}
 }
 
+static int msm_iommu_v2_attach(struct msm_mmu *mmu, const char * const *names,
+  int cnt)
+{
+   struct msm_iommu *iommu = to_msm_iommu(mmu);
+
+   return iommu_attach_device(iommu->domain, mmu->dev);
+}
+
+static void msm_iommu_v2_detach(struct msm_mmu *mmu, const char * const *names,
+   int cnt)
+{
+   struct msm_iommu *iommu = to_msm_iommu(mmu);
+
+   iommu_detach_device(iommu->domain, mmu->dev);
+}
+
 static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
struct sg_table *sgt, unsigned len, int prot)
 {
@@ -159,9 +168,19 @@ static void msm_iommu_destroy(struct msm_mmu *mmu)
kfree(iommu);
 }
 
-static const struct msm_mmu_funcs funcs = {
-   .attach = msm_iommu_attach,
-   .detach = msm_iommu_detach,
+/* These are for qcom,msm-smmu-v2 and qcom,msm-mmu-500 based targets */
+static const struct msm_mmu_funcs funcs_v1 = {
+   .attach = msm_iommu_v1_attach,
+   .detach = msm_iommu_v1_detach,
+   .map = msm_iommu_map,
+   .unmap = msm_iommu_unmap,
+   .destroy = msm_iommu_destroy,
+};
+
+/* These are for the arm-smmu based targets */
+static const struct msm_mmu_funcs funcs_v2 = {
+   .attach = msm_iommu_v2_attach,
+   .detach = msm_iommu_v2_detach,
.map = msm_iommu_map,
.unmap = msm_iommu_unmap,
.destroy = msm_iommu_destroy,
@@ -170,18 +189,21 @@ static void msm_iommu_destroy(struct msm_mmu *mmu)
 struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
 {
struct msm_iommu *iommu;
+   const struct msm_mmu_funcs *funcs;
 
iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
if (!iommu)
return ERR_PTR(-ENOMEM);
 
-   iommu->domain = domain;
-   msm_mmu_init(&iommu->base, dev, &funcs);
-   iommu_set_fault_handler(domain, msm_fault_handler, iommu, true);
-
if (of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v2") ||
of_find_compatible_node(NULL, NULL, "qcom,msm-mmu-500"))
-   iommu->has_ctx = true;
+   funcs = &funcs_v1;
+   else
+   funcs = &funcs_v2;
+
+   iommu->domain = domain;
+   msm_mmu_init(&iommu->base, dev, funcs);
+   iommu_set_fault_handler(domain, msm_fault_handler, iommu, true);
 
return &iommu->base;
 }
-- 
1.9.1

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[PATCH 0/6] drm/msm: Add per-instance pagetables

[Jordan Crouse]

Using the framework described here

https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html

This implements per-instance pagetables for the GPU driver creating an
individual pagetable for each file descriptor (so not strictly per-process
but in practice we can't share buffers between file descriptors anyway without
importing them).

This is the brief workflow for the process:

 - At init, the driver attaches an UNMANGED domain to the IOMMU (context bank 0)

 - All "global" buffers (kernel side GPU buffers such as ringbuffers, etc) are
   mapped into the TTBR1 space which is defined as any address with bit 48 set.
   In pratice we have discovered that for reasons yet uknown, bit 47 also has
   to be set for the GPU to sign extend correctly, so the TTBR1 region is
   defined as starting at 0x8___.

 - When a new file descriptor is opened, a dynamic domain is cloned from the
   real domain - this does not program the hardware but it creates a pagetable
   and returns a pointer that we can use to map memory to - this is wrapped in a
   new addresss space and used for all allocations created with the file
   descriptor.

 - At command submission time, a SMMU_TABLE_UPDATE packet is set before every
   command which contains the physical address of the TTBR0 register for the
   pagetable associated with the process - the GPU will automatically switch
   the pagetable for the process.

Because no kernel side allocations are in the TTBR0 space there is no setup
required to switch the TTBR0 pagetable and we do not need to reprogram it
after the command is over since the next command will rewrite the register.
This makes the code significantly more simple than it could be (*cough*
downstream *cough*).

I'm sure there will be questions, and I'm sure that what we have won't be what
is finally decided upon in the arm-smmu driver (in particular there are some
nice parts of the arm-v3 SVM solution that we can borrow) but I think it is
important to get eyeballs on this for posterity.

Thanks!
Jordan

Jordan Crouse (6):
  drm/msm: Enable 64 bit mode by default
  drm/msm: Pass the MMU domain index in struct msm_file_private
  drm/msm: Make separate iommu function tables for v1 and v2 MMUs
  drm/msm: Use TTBR1 for kernel side GPU buffer objects
  drm/msm: Support dynamic IOMMU domains
  drm/msm: a5xx: Support per-instance pagetables

 arch/arm64/boot/dts/qcom/msm8996.dtsi |   2 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c |  78 ++-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h |  17 
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c |  61 +---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c   |  18 +++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   2 +
 drivers/gpu/drm/msm/msm_drv.c |  60 +---
 drivers/gpu/drm/msm/msm_drv.h |   9 +-
 drivers/gpu/drm/msm/msm_gem.h |   1 +
 drivers/gpu/drm/msm/msm_gem_submit.c  |  12 ++-
 drivers/gpu/drm/msm/msm_gem_vma.c |  38 ++--
 drivers/gpu/drm/msm/msm_gpu.c |   3 +-
 drivers/gpu/drm/msm/msm_iommu.c   | 151 --
 drivers/gpu/drm/msm/msm_iommu.h   |  34 +++
 drivers/gpu/drm/msm/msm_mmu.h |   2 +-
 15 files changed, 415 insertions(+), 73 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/msm_iommu.h

-- 
1.9.1

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[PATCH 6/6] drm/msm: a5xx: Support per-instance pagetables

[Jordan Crouse]

Support per-instance pagetables for 5XX targets. Per-instance
pagetables allow each open DRM instance to have its own VM memory
space to prevent accidently or maliciously copying or overwriting
buffers from other instances. It also opens the door for SVM since
any given CPU side address can be more reliably mapped into the
instance's GPU VM space without conflict.

To support this create a new dynamic domain (pagetable) for each open
DRM file and map buffer objects for each instance into that pagetable.
Use the GPU to switch to the pagetable for the instance while doing a
submit.

Signed-off-by: Jordan Crouse 
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  2 +
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 64 ++-
 drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 17 
 drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 61 +++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.h   |  2 +
 drivers/gpu/drm/msm/msm_drv.c | 60 ++---
 drivers/gpu/drm/msm/msm_drv.h |  3 ++
 drivers/gpu/drm/msm/msm_gem_vma.c | 38 +++---
 8 files changed, 216 insertions(+), 31 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 2903020..6372f3a 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -867,7 +867,9 @@
 
qcom,skip-init;
qcom,register-save;
+
arm,smmu-enable-stall;
+   qcom,dynamic;
 
status = "okay";
};
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 06238b7..65cd3ef 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -18,7 +18,7 @@
 #include 
 #include 
 #include "msm_gem.h"
-#include "msm_mmu.h"
+#include "msm_iommu.h"
 #include "a5xx_gpu.h"
 
 extern bool hang_debug;
@@ -209,6 +209,66 @@ static void a5xx_flush(struct msm_gpu *gpu, struct 
msm_ringbuffer *ring)
gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
 }
 
+static void a5xx_set_pagetable(struct msm_gpu *gpu, struct msm_ringbuffer 
*ring,
+   struct msm_file_private *ctx)
+{
+   struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct msm_mmu *mmu = ctx->aspace->mmu;
+   struct msm_iommu *iommu = to_msm_iommu(mmu);
+
+   if (!iommu->ttbr0)
+   return;
+
+   /* Turn off protected mode */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 0);
+
+   /* Turn on APIV mode to access critical regions */
+   OUT_PKT4(ring, REG_A5XX_CP_CNTL, 1);
+   OUT_RING(ring, 1);
+
+   /* Make sure the ME is syncronized before staring the update */
+   OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
+
+   /* Execute the table update */
+   OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 3);
+   OUT_RING(ring, lower_32_bits(iommu->ttbr0));
+   OUT_RING(ring, upper_32_bits(iommu->ttbr0));
+   OUT_RING(ring, iommu->contextidr);
+
+   /*
+* Write the new TTBR0 to the preemption records - this will be used to
+* reload the pagetable if the current ring gets preempted out.
+*/
+   OUT_PKT7(ring, CP_MEM_WRITE, 4);
+   OUT_RING(ring, lower_32_bits(rbmemptr(adreno_gpu, ring->id, ttbr0)));
+   OUT_RING(ring, upper_32_bits(rbmemptr(adreno_gpu, ring->id, ttbr0)));
+   OUT_RING(ring, lower_32_bits(iommu->ttbr0));
+   OUT_RING(ring, upper_32_bits(iommu->ttbr0));
+
+   /* Also write the current contextidr (ASID) */
+   OUT_PKT7(ring, CP_MEM_WRITE, 3);
+   OUT_RING(ring, lower_32_bits(rbmemptr(adreno_gpu, ring->id,
+   contextidr)));
+   OUT_RING(ring, upper_32_bits(rbmemptr(adreno_gpu, ring->id,
+   contextidr)));
+   OUT_RING(ring, iommu->contextidr);
+
+   /* Invalidate the draw state so we start off fresh */
+   OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
+   OUT_RING(ring, 0x4);
+   OUT_RING(ring, 1);
+   OUT_RING(ring, 0);
+
+   /* Turn off APRIV */
+   OUT_PKT4(ring, REG_A5XX_CP_CNTL, 1);
+   OUT_RING(ring, 0);
+
+   /* Turn off protected mode */
+   OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
+   OUT_RING(ring, 1);
+}
+
 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx)
 {
@@ -219,6 +279,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
struct msm_ringbuffer *ring = submit->ring;
unsigned int i, ibs = 0;
 
+   a5xx_set_pagetable(gpu, ring, ctx);
+
OUT_PKT7(ring, CP_PREEMPT_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x02);
 
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index f042a78..19deea0 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5x

[PATCH 5/6] drm/msm: Support dynamic IOMMU domains

[Jordan Crouse]

Dynamic IOMMU domains allow multiple pagetables to be attached to the
same IOMMU device. These can be used by smart devices like the GPU
that can switch the pagetable dynamically between DRM instances.

Add support for dynamic IOMMU domains if they are enabled and
supported by your friendly neighborhood IOMMU driver.

Signed-off-by: Jordan Crouse 
---
 drivers/gpu/drm/msm/msm_iommu.c | 99 ++---
 drivers/gpu/drm/msm/msm_iommu.h | 34 ++
 drivers/gpu/drm/msm/msm_mmu.h   |  2 +-
 3 files changed, 117 insertions(+), 18 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/msm_iommu.h

diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index cc82410..38ec5e8 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -16,13 +16,7 @@
  */
 
 #include "msm_drv.h"
-#include "msm_mmu.h"
-
-struct msm_iommu {
-   struct msm_mmu base;
-   struct iommu_domain *domain;
-};
-#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
+#include "msm_iommu.h"
 
 static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
unsigned long iova, int flags, void *arg)
@@ -83,14 +77,19 @@ static int msm_iommu_v2_attach(struct msm_mmu *mmu, const 
char * const *names,
   int cnt)
 {
struct msm_iommu *iommu = to_msm_iommu(mmu);
-   int val = 1;
+   int val = 1, ret;
 
/* Use TTBR1 if it exists */
-   /* FIXME: This should only be for GPU and in theory only for A5XX */
-
-   iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_ENABLE_TTBR1,
+   ret = iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_ENABLE_TTBR1,
&val);
 
+   /*
+* We will only allow per-instance pagetables if TTBR1 is available
+* because the alternative is too labor intensive
+*/
+   iommu->allow_dynamic = !ret ? true : false;
+
+   /* Attach the device to the domain */
return iommu_attach_device(iommu->domain, mmu->dev);
 }
 
@@ -102,6 +101,18 @@ static void msm_iommu_v2_detach(struct msm_mmu *mmu, const 
char * const *names,
iommu_detach_device(iommu->domain, mmu->dev);
 }
 
+/* Dynamic domains do not have attach/detach steps */
+static int msm_iommu_attach_dynamic(struct msm_mmu *mmu,
+   const char * const *names, int cnt)
+{
+   return 0;
+}
+
+static void msm_iommu_detach_dynamic(struct msm_mmu *mmu,
+const char * const *names, int cnt)
+{
+}
+
 static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
struct sg_table *sgt, unsigned len, int prot)
 {
@@ -193,24 +204,78 @@ static void msm_iommu_destroy(struct msm_mmu *mmu)
.destroy = msm_iommu_destroy,
 };
 
-struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
+/* These are for dynamic per-instance domains */
+static const struct msm_mmu_funcs dynamic_funcs = {
+   .attach = msm_iommu_attach_dynamic,
+   .detach = msm_iommu_detach_dynamic,
+   .map = msm_iommu_map,
+   .unmap = msm_iommu_unmap,
+   .destroy = msm_iommu_destroy,
+};
+
+struct msm_mmu *_msm_iommu_new(struct device *dev, struct iommu_domain *domain,
+   const struct msm_mmu_funcs *funcs)
 {
struct msm_iommu *iommu;
-   const struct msm_mmu_funcs *funcs;
 
iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
if (!iommu)
return ERR_PTR(-ENOMEM);
 
+   iommu->domain = domain;
+   msm_mmu_init(&iommu->base, dev, funcs);
+   iommu_set_fault_handler(domain, msm_fault_handler, iommu, true);
+
+   return &iommu->base;
+}
+
+struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
+{
+   const struct msm_mmu_funcs *funcs;
+
if (of_find_compatible_node(NULL, NULL, "qcom,msm-smmu-v2") ||
of_find_compatible_node(NULL, NULL, "qcom,msm-mmu-500"))
funcs = &funcs_v1;
else
funcs = &funcs_v2;
 
-   iommu->domain = domain;
-   msm_mmu_init(&iommu->base, dev, funcs);
-   iommu_set_fault_handler(domain, msm_fault_handler, iommu, true);
+   return _msm_iommu_new(dev, domain, funcs);
+}
 
-   return &iommu->base;
+/*
+ * Given a base domain that is attached to a IOMMU device try to create a
+ * dynamic domain that is also attached to the same device but allocates a new
+ * pagetable. This is used to allow multiple pagetables to be attached to the
+ * same device.
+ */
+struct msm_mmu *msm_iommu_new_dynamic(struct msm_mmu *base)
+{
+   static unsigned int procid;
+   struct msm_iommu *base_iommu = to_msm_iommu(base);
+   struct msm_iommu *iommu;
+   struct iommu_domain *domain;
+   struct msm_mmu *mmu;
+
+   /* Don't continue if the base domain didn't have the support we need */
+   if (!base || base_iommu->allow_dynamic ==

[Bug 100104] Gallium-9 hitting LLVM assert when trying to start EVE-Online

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100104

Bug ID: 100104
   Summary: Gallium-9 hitting LLVM assert when trying to start
EVE-Online
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel@lists.freedesktop.org
  Reporter: b74...@gmail.com
QA Contact: dri-devel@lists.freedesktop.org

Hi,
EVE-Online don't start anymore since I upgraded to last Mesa GIT and LLVM git
two days ago. The game start, Like you see the black screen and the login
loading bar and then it crash with that error.

void llvm::LiveRangeEdit::eliminateDeadDef(llvm::MachineInstr*,
llvm::LiveRangeEdit::ToShrinkSet&, llvm::AliasAnalysis*): Assertion
`MI->allDefsAreDead() && "Def isn't really dead"' failed.

>From the LLVM bugs, It got reported last years but nothing append because "this
path is not used by default"

https://bugs.llvm.org//show_bug.cgi?id=31015

I don't know if it's the same and/or if I have to post that on the llvm bugs
(waiting for a login as they allow people to register on there bugzilla).

Note : It do work (but unplayable in 4K) without Gallium-9.

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Re: [PATCH v3 3/4] drm/imx: don't wait for vblank and stop calling cleanup_planes in commit_tail

[Lucas Stach]

Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel:
> drm_atomic_helper_cleanup_planes only calls the cleanup_fb plane
> helpers, which we don't implement as a CMA framebuffer based driver.
> There is no reason to wait for vblanks in commit_tail only to do nothing
> afterwards.
> 
> Signed-off-by: Philipp Zabel 

Reviewed-by: Lucas Stach 

> ---
> Changes since v2:
>  - New patch that removes wait_for_vblanks and cleanup_planes instead
>of reordering commit_hw_done and wait_for_vblanks.
> ---
>  drivers/gpu/drm/imx/imx-drm-core.c | 4 
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/imx-drm-core.c 
> b/drivers/gpu/drm/imx/imx-drm-core.c
> index f562cb7964b08..0a5e4fbb906bf 100644
> --- a/drivers/gpu/drm/imx/imx-drm-core.c
> +++ b/drivers/gpu/drm/imx/imx-drm-core.c
> @@ -170,10 +170,6 @@ static void imx_drm_atomic_commit_tail(struct 
> drm_atomic_state *state)
>   drm_atomic_helper_commit_modeset_enables(dev, state);
>  
>   drm_atomic_helper_commit_hw_done(state);
> -
> - drm_atomic_helper_wait_for_vblanks(dev, state);
> -
> - drm_atomic_helper_cleanup_planes(dev, state);
>  }
>  
>  static struct drm_mode_config_helper_funcs imx_drm_mode_config_helpers = {


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Re: [PATCH v3 4/4] drm/imx: add deferred plane disabling

[Lucas Stach]

Am Dienstag, den 28.02.2017, 15:18 +0100 schrieb Philipp Zabel:
> The DP (display processor) channel disable code tried to busy wait for
> the DP sync flow end interrupt status bit when disabling the partial
> plane without a full modeset. That never worked reliably, and it was
> disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC
> channel disable" patch, causing ipu_wait_interrupt to always time out
> after 50 ms, which in turn would trigger a timeout in
> drm_atomic_helper_wait_for_vblanks.
> 
> This patch changes ipu_plane_atomic_disable to only queue a DP channel
> register update at the next frame boundary and set a flag, which can be
> done without any waiting whatsoever. The imx_drm_atomic_commit_tail then
> calls a new ipu_plane_disable_deferred function that does the actual
> IDMAC teardown of the planes that are flagged for deferred disabling,
> after waiting for the vblank.
> 
> Signed-off-by: Philipp Zabel 

Reviewed-by: Lucas Stach 

> ---
> Changes since v2:
>  - Add missing export for ipu_plane_disable_deferred
>  - Check if there are any planes to be disabled and only then wait for
>vblanks and call the deferred disable function
> ---
>  drivers/gpu/drm/imx/imx-drm-core.c | 18 ++
>  drivers/gpu/drm/imx/ipuv3-crtc.c   | 22 +-
>  drivers/gpu/drm/imx/ipuv3-plane.c  | 25 ++---
>  drivers/gpu/drm/imx/ipuv3-plane.h  |  5 +
>  drivers/gpu/ipu-v3/ipu-dp.c|  3 ---
>  5 files changed, 62 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/imx/imx-drm-core.c 
> b/drivers/gpu/drm/imx/imx-drm-core.c
> index 0a5e4fbb906bf..94f9c25e1c67b 100644
> --- a/drivers/gpu/drm/imx/imx-drm-core.c
> +++ b/drivers/gpu/drm/imx/imx-drm-core.c
> @@ -30,6 +30,7 @@
>  #include 
>  
>  #include "imx-drm.h"
> +#include "ipuv3-plane.h"
>  
>  #define MAX_CRTC 4
>  
> @@ -160,6 +161,10 @@ static const struct drm_mode_config_funcs 
> imx_drm_mode_config_funcs = {
>  static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
>  {
>   struct drm_device *dev = state->dev;
> + struct drm_plane *plane;
> + struct drm_plane_state *plane_state;
> + bool plane_disabling = false;
> + int i;
>  
>   drm_atomic_helper_commit_modeset_disables(dev, state);
>  
> @@ -169,6 +174,19 @@ static void imx_drm_atomic_commit_tail(struct 
> drm_atomic_state *state)
>  
>   drm_atomic_helper_commit_modeset_enables(dev, state);
>  
> + for_each_plane_in_state(state, plane, plane_state, i) {
> + if (drm_atomic_plane_disabling(plane, plane_state))
> + plane_disabling = true;
> + }
> +
> + if (plane_disabling) {
> + drm_atomic_helper_wait_for_vblanks(dev, state);
> +
> + for_each_plane_in_state(state, plane, plane_state, i)
> + ipu_plane_disable_deferred(plane);
> +
> + }
> +
>   drm_atomic_helper_commit_hw_done(state);
>  }
>  
> diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c 
> b/drivers/gpu/drm/imx/ipuv3-crtc.c
> index 6be515a9fb694..0f15f11f26e0c 100644
> --- a/drivers/gpu/drm/imx/ipuv3-crtc.c
> +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
> @@ -60,6 +60,26 @@ static void ipu_crtc_enable(struct drm_crtc *crtc)
>   ipu_di_enable(ipu_crtc->di);
>  }
>  
> +static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc,
> + struct drm_crtc_state *old_crtc_state)
> +{
> + bool disable_partial = false;
> + bool disable_full = false;
> + struct drm_plane *plane;
> +
> + drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) {
> + if (plane == &ipu_crtc->plane[0]->base)
> + disable_full = true;
> + if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base)
> + disable_partial = true;
> + }
> +
> + if (disable_partial)
> + ipu_plane_disable(ipu_crtc->plane[1], true);
> + if (disable_full)
> + ipu_plane_disable(ipu_crtc->plane[0], false);
> +}
> +
>  static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
>   struct drm_crtc_state *old_crtc_state)
>  {
> @@ -73,7 +93,7 @@ static void ipu_crtc_atomic_disable(struct drm_crtc *crtc,
>* attached IDMACs will be left in undefined state, possibly hanging
>* the IPU or even system.
>*/
> - drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
> + ipu_crtc_disable_planes(ipu_crtc, old_crtc_state);
>   ipu_dc_disable(ipu);
>  
>   spin_lock_irq(&crtc->dev->event_lock);
> diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c 
> b/drivers/gpu/drm/imx/ipuv3-plane.c
> index 55991d46ced50..a37735298615e 100644
> --- a/drivers/gpu/drm/imx/ipuv3-plane.c
> +++ b/drivers/gpu/drm/imx/ipuv3-plane.c
> @@ -172,23 +172,30 @@ static void ipu_plane_enable(struct ipu_plane 
> *ipu_plane)
>   ipu_dp_enable_channel(ipu_plane->dp);
>  }
>  
> -static int ipu_

Re: [PATCH v6 2/4] drm/dp: add helpers for capture of frame CRCs

[Gabriel Krisman Bertazi]

Tomeu Vizoso  writes:

> +
> +/**
> + * drm_dp_start_crc() - start capture of frame CRCs
> + * @aux: DisplayPort AUX channel
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
> +{
> + u8 buf;
> + int ret;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
> + if (ret < 0)
> + return ret;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
> + if (ret < 0)
> + return ret;
> +
> + aux->crc_count = 0;
> + aux->crtc = crtc;
> + schedule_work(&aux->crc_work);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_start_crc);
> +

Hi Tomeu,

This triggers a new warning when building documentation:

./drivers/gpu/drm/drm_dp_helper.c:1165: warning: No description found
for parameter 'crtc'
./drivers/gpu/drm/drm_dp_helper.c:1166: warning: No description found
for parameter 'crtc'

-- 
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[Bug 100105] Make Theano OpenCL support work on Clover and RadeonSI

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100105

Bug ID: 100105
   Summary: Make Theano OpenCL support work on Clover and RadeonSI
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: major
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel@lists.freedesktop.org
  Reporter: ved...@miletic.net
QA Contact: dri-devel@lists.freedesktop.org

$ DEVICE="opencl0:0" python -c "import pygpu;pygpu.test()"
pygpu is installed in
/usr/lib64/python2.7/site-packages/pygpu-0.6.2-py2.7-linux-x86_64.egg/pygpu
NumPy version 1.11.2
NumPy relaxed strides checking option: False
NumPy is installed in /usr/lib64/python2.7/site-packages/numpy
Python version 2.7.13 (default, Jan 12 2017, 17:59:37) [GCC 6.3.1 20161221 (Red
Hat 6.3.1-1)]
nose version 1.3.7
*** Testing for AMD FIJI (DRM 3.8.0 / 4.9.13-200.fc25.x86_64, LLVM 5.0.0)



AN INTERNAL KERNEL BUILD ERROR OCCURRED!
device name = AMD FIJI (DRM 3.8.0 / 4.9.13-200.fc25.x86_64, LLVM 5.0.0)
error = -43
memory pattern = Register accumulation based swap, computing kernel generator
Subproblem dimensions: dims[0].itemY = 32, dims[0].itemX = 32, dims[0].y = 32,
dims[0].x = 32, dims[0].bwidth = 64; ; dims[1].itemY = 4, dims[1].itemX = 4,
dims[1].y = 4, dims[1].x = 4, dims[1].bwidth = 8; ; 
Parallelism granularity: pgran->wgDim = 1, pgran->wgSize[0] = 64,
pgran->wgSize[1] = 1, pgran->wfSize = 64
Kernel extra flags: 369130144
Source:

#ifdef DOUBLE_PRECISION
#ifdef cl_khr_fp64
#pragma OPENCL EXTENSION cl_khr_fp64 : enable
#else
#pragma OPENCL EXTENSION cl_amd_fp64 : enable
#endif
#endif

__kernel void Sdot_kernel( __global float *_X, __global float *_Y, __global
float *scratchBuff,
uint N, uint offx, int incx, uint offy,
int incy, int doConj )
{
__global float *X = _X + offx;
__global float *Y = _Y + offy;
float dotP = (float) 0.0;

if ( incx < 0 ) {
X = X + (N - 1) * abs(incx);
}
if ( incy < 0 ) {
Y = Y + (N - 1) * abs(incy);
}

int gOffset;
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[Bug 100105] Make Theano OpenCL support work on Clover and RadeonSI

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100105

Vedran Miletić  changed:

   What|Removed |Added

 Blocks||99553
URL||http://deeplearning.net/sof
   ||tware/libgpuarray/installat
   ||ion.html


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=99553
[Bug 99553] Tracker bug for runnning OpenCL applications on Clover
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[Bug 99553] Tracker bug for runnning OpenCL applications on Clover

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99553

Vedran Miletić  changed:

   What|Removed |Added

 Depends on||100105


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=100105
[Bug 100105] Make Theano OpenCL support work on Clover and RadeonSI
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Re: RFC: late drm pull requests and other topics

[Lukas Wunner]

On Tue, Mar 07, 2017 at 10:56:49AM -0500, Alex Deucher wrote:
> On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter  wrote:
> I've always tried to have all major new features sent to Dave by rc5,
> so no problems with the timelines.  Dave and Linus have generally been
> ok with new asic support at strange times assuming it has minimal
> impact on existing support.  Our code release dates rarely line up
> well with kernel cycles, but we can manage.

Well, you were also once the target of a rant because of too recent
commit dates that turned out to have an entirely innocuous explanation:

https://www.spinics.net/lists/dri-devel/msg87996.html

In a follow-up, Linus said "I want to at least be able to fool myself
into thinking that downstream has really worked hard at validating what
they send me".

https://www.spinics.net/lists/dri-devel/msg87999.html

So since he was asking for it, maybe use something like:

GIT_AUTHOR_DATE=`date --date="8 weeks ago"` \
GIT_COMMITTER_DATE=`date --date="4 weeks ago"` \
  git commit --amend --date

Best regards ;-)

Lukas
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Re: [PATCH 4/5] drm/radeon: Don't register Thunderbolt eGPU with vga_switcheroo

[Alex Deucher]

On Fri, Feb 24, 2017 at 2:19 PM, Lukas Wunner  wrote:
> An external Thunderbolt GPU can neither drive the laptop's panel nor be
> powered off by the platform, so there's no point in registering it with
> vga_switcheroo.  In fact, when the external GPU is runtime suspended,
> vga_switcheroo will cut power to the internal discrete GPU, resulting in
> a lockup.

I'm not necessarily opposed to this, but I'd prefer something more
generic.  E.g., what happens if someone uses another dGPU in a docking
station or some other sort of PCIe bridge?  I think on AMD platforms
at least we should be able to determine what devices are the
switcheroo devices based on information in the ATIF and ATPX ACPI
methods.  In that case, we can be explicit in which devices we
register with vga_switcheroo.

Alex

>
> Cc: Alex Deucher 
> Signed-off-by: Lukas Wunner 
> ---
>  drivers/gpu/drm/radeon/radeon_device.c | 7 +--
>  drivers/gpu/drm/radeon/radeon_kms.c| 3 ++-
>  2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
> b/drivers/gpu/drm/radeon/radeon_device.c
> index 4b0c388be3f5..27be17f0b227 100644
> --- a/drivers/gpu/drm/radeon/radeon_device.c
> +++ b/drivers/gpu/drm/radeon/radeon_device.c
> @@ -1471,7 +1471,9 @@ int radeon_device_init(struct radeon_device *rdev,
>
> if (rdev->flags & RADEON_IS_PX)
> runtime = true;
> -   vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, 
> runtime);
> +   if (!pci_is_thunderbolt_attached(rdev->pdev))
> +   vga_switcheroo_register_client(rdev->pdev,
> +  &radeon_switcheroo_ops, 
> runtime);
> if (runtime)
> vga_switcheroo_init_domain_pm_ops(rdev->dev, 
> &rdev->vga_pm_domain);
>
> @@ -1564,7 +1566,8 @@ void radeon_device_fini(struct radeon_device *rdev)
> /* evict vram memory */
> radeon_bo_evict_vram(rdev);
> radeon_fini(rdev);
> -   vga_switcheroo_unregister_client(rdev->pdev);
> +   if (!pci_is_thunderbolt_attached(rdev->pdev))
> +   vga_switcheroo_unregister_client(rdev->pdev);
> if (rdev->flags & RADEON_IS_PX)
> vga_switcheroo_fini_domain_pm_ops(rdev->dev);
> vga_client_register(rdev->pdev, NULL, NULL, NULL);
> diff --git a/drivers/gpu/drm/radeon/radeon_kms.c 
> b/drivers/gpu/drm/radeon/radeon_kms.c
> index 56f35c06742c..e95ceec1c97a 100644
> --- a/drivers/gpu/drm/radeon/radeon_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -115,7 +115,8 @@ int radeon_driver_load_kms(struct drm_device *dev, 
> unsigned long flags)
>
> if ((radeon_runtime_pm != 0) &&
> radeon_has_atpx() &&
> -   ((flags & RADEON_IS_IGP) == 0))
> +   ((flags & RADEON_IS_IGP) == 0) &&
> +   !pci_is_thunderbolt_attached(rdev->pdev))
> flags |= RADEON_IS_PX;
>
> /* radeon_device_init should report only fatal error
> --
> 2.11.0
>
> ___
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: RFC: late drm pull requests and other topics

[Alex Deucher]

On Tue, Mar 7, 2017 at 10:56 AM, Alex Deucher  wrote:
> On Mon, Mar 6, 2017 at 7:11 PM, Daniel Vetter  wrote:
>> Hi all,
>>
>> In the 4.11 drm pull request Linus raised a few things that we need to 
>> discuss:
>>
>> Late driver/enabling pull requests
>> --
>>
>> Imo this isn't as one-sided as Linus made it sound, we've had the policy of
>> pulling new drivers and enabling for new hw very late in the merge window
>> forever. And I think there's some good benefits, both for users as for 
>> companies
>> trying to do early enabling. It's just that in the past few years it's been
>> mostly arm drivers (where Linus doesn't see the inevitable Kconfig fail) or 
>> new
>> code in existing big drivers (where Kconfig fail tends to not happen if you
>> leave backlight code alone ...).
>>
>> Anyway, Linus has been pretty clear here, not really wiggle room left and
>> personally I think this doesn't hurt us that much, it's more on the 
>> unfortunate
>> side. I discussed this a bit with Dave on irc, and the proposal would be that
>> every feature patch must be in linux-next by -rc6 and in drm-next by -rc7. 
>> This
>> is how drm-intel has run since years, and also what we started doing with
>> drm-misc (except new platform enabling, which I guess now can't happen any 
>> more,
>> amdgpu with Vega will probably be hurt first). So works, just means everyone
>> needs to queue stuff early and also have their tree in linux-next (or get 
>> into
>> drm-misc if that's too much pain).
>
> I've always tried to have all major new features sent to Dave by rc5,
> so no problems with the timelines.  Dave and Linus have generally been
> ok with new asic support at strange times assuming it has minimal
> impact on existing support.  Our code release dates rarely line up
> well with kernel cycles, but we can manage.
>
>
>>
>> Linus shitting on dri-devel
>> ---
>>
>> I'm not happy with that, and asked Linus to at least drop dri-devel when he
>> shits on Dave and maintainers. Dave also brought up the idea of bcc'ing
>> dri-devel, which should prevent shouting from Linus reliably. Note I'm not
>> suggesting we ignore Linus' input, just that we keep the 90% insults that 
>> it's
>> wrapped in out of our community as much as we can. Better ideas than bcc 
>> would
>> be good.
>
> It sucks, but I guess my skin has hardened over the years.  We've had
> a fair share of heated arguments even on dri-devel.

I discussed this a bit with Daniel on IRC and I realized I may not
have made myself clear.  My main point was that I think it's important
not to shield our developers too much.  They need to have some
knowledge or linux-kernel and other subsystems just to get a taste of
different development styles or things that might not have occurred to
them so seeing feedback from outside developers is important.  I'm not
condoning threats or insults.

Alex

>
>>
>> Splitting the drm pull
>> --
>>
>> I don't think this would be a good idea at all:
>>
>> - Personally I don't want to send pull requests to Linus. Dave seems ok with
>>   taking the heat for us, and I'm very happy he's willing to do that. I'd
>>   certainly not do that.
>>
>> - There's the small problem that more trees means we need to spent more time
>>   with the burocratics. From my experience with drm-misc and drm-intel alone
>>   there's lots of coordination needed, and we resync every 1-3 weeks in 
>> drm-next
>>   with pull requests to Dave. I don't see anyone volunteering to spend more 
>> time
>>   on burocratics, there's already enough to do.
>>
>> - We've done some really impressive refactorings in drm the past 1-2 years, 
>> very
>>   often cleanups that new driver contributors have done. Looking at drm-misc 
>> we
>>   need to resync about once per month to be able to move forward, since new
>>   drivers depend upon new refactorings and new refactorings later then need 
>> to
>>   have a tree with all the drivers. So really no way to split things up I 
>> think
>>   without slowing down a lot. And ime if you want to ship upstream as 
>> product in
>>   the embedded space, we're still not fast enough.
>>
>>   For Intel that'd mean we'd have to pull out a lot of our efforts spent in
>>   improving the core and helpers, and I think the same holds for a lot of 
>> other
>>   drivers. Many might even entirely drop upstream because bikeshedding a 
>> helper
>>   for 3 months first and then the driver for another 3 months for something
>>   trivial is silly.
>>
>> So overall I think overall this would hurt way too much, and we don't have 
>> the
>> people with free time to implement it anyway. Well, without slowing down and
>> making upstream gfx irrevelant again now that it's finally being taken more
>> serious. I also discussed this with Dave and others on irc a bit, and Dave
>> thinks that there shouldn't be any problem for us if we keept he one single
>> overall subsystem tree.
>>
>> Those 3 items where the

[PATCH 1/3] drm/msm: Remove msm_debugfs_cleanup()

[Noralf Trønnes]

Move the contents of msm_debugfs_cleanup() to msm_drm_uninit() to free
up the drm_driver->debugfs_cleanup callback. Also remove the
mdp_kms_funcs->debugfs_cleanup callback which has no users.

Cc: robdcl...@gmail.com
Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/msm/msm_debugfs.c | 15 ---
 drivers/gpu/drm/msm/msm_debugfs.h |  1 -
 drivers/gpu/drm/msm/msm_drv.c |  4 +++-
 drivers/gpu/drm/msm/msm_drv.h |  4 ++--
 drivers/gpu/drm/msm/msm_kms.h |  1 -
 drivers/gpu/drm/msm/msm_perf.c|  5 ++---
 drivers/gpu/drm/msm/msm_rd.c  |  5 ++---
 7 files changed, 9 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/msm/msm_debugfs.c 
b/drivers/gpu/drm/msm/msm_debugfs.c
index e754429..1855182 100644
--- a/drivers/gpu/drm/msm/msm_debugfs.c
+++ b/drivers/gpu/drm/msm/msm_debugfs.c
@@ -166,20 +166,5 @@ int msm_debugfs_init(struct drm_minor *minor)
 
return ret;
 }
-
-void msm_debugfs_cleanup(struct drm_minor *minor)
-{
-   struct drm_device *dev = minor->dev;
-   struct msm_drm_private *priv = dev->dev_private;
-
-   if (!priv)
-   return;
-
-   if (priv->kms->funcs->debugfs_cleanup)
-   priv->kms->funcs->debugfs_cleanup(priv->kms, minor);
-
-   msm_rd_debugfs_cleanup(minor);
-   msm_perf_debugfs_cleanup(minor);
-}
 #endif
 
diff --git a/drivers/gpu/drm/msm/msm_debugfs.h 
b/drivers/gpu/drm/msm/msm_debugfs.h
index 6110c97..f4077e3 100644
--- a/drivers/gpu/drm/msm/msm_debugfs.h
+++ b/drivers/gpu/drm/msm/msm_debugfs.h
@@ -20,7 +20,6 @@
 
 #ifdef CONFIG_DEBUG_FS
 int msm_debugfs_init(struct drm_minor *minor);
-void msm_debugfs_cleanup(struct drm_minor *minor);
 #endif
 
 #endif /* __MSM_DEBUGFS_H__ */
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 6c1a499..500ad18 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -241,6 +241,9 @@ static int msm_drm_uninit(struct device *dev)
 
drm_dev_unregister(ddev);
 
+   msm_perf_debugfs_cleanup(priv);
+   msm_rd_debugfs_cleanup(priv);
+
 #ifdef CONFIG_DRM_FBDEV_EMULATION
if (fbdev && priv->fbdev)
msm_fbdev_free(ddev);
@@ -838,7 +841,6 @@ static struct drm_driver msm_driver = {
.gem_prime_mmap = msm_gem_prime_mmap,
 #ifdef CONFIG_DEBUG_FS
.debugfs_init   = msm_debugfs_init,
-   .debugfs_cleanup= msm_debugfs_cleanup,
 #endif
.ioctls = msm_ioctls,
.num_ioctls = DRM_MSM_NUM_IOCTLS,
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index c3b1487..b51fb0d 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -304,10 +304,10 @@ void msm_gem_describe_objects(struct list_head *list, 
struct seq_file *m);
 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
 int msm_debugfs_late_init(struct drm_device *dev);
 int msm_rd_debugfs_init(struct drm_minor *minor);
-void msm_rd_debugfs_cleanup(struct drm_minor *minor);
+void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
 void msm_rd_dump_submit(struct msm_gem_submit *submit);
 int msm_perf_debugfs_init(struct drm_minor *minor);
-void msm_perf_debugfs_cleanup(struct drm_minor *minor);
+void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
 #else
 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
 static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 117635d2..faa22c7 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -64,7 +64,6 @@ struct msm_kms_funcs {
 #ifdef CONFIG_DEBUG_FS
/* debugfs: */
int (*debugfs_init)(struct msm_kms *kms, struct drm_minor *minor);
-   void (*debugfs_cleanup)(struct msm_kms *kms, struct drm_minor *minor);
 #endif
 };
 
diff --git a/drivers/gpu/drm/msm/msm_perf.c b/drivers/gpu/drm/msm/msm_perf.c
index fc5a948..5ab21bd 100644
--- a/drivers/gpu/drm/msm/msm_perf.c
+++ b/drivers/gpu/drm/msm/msm_perf.c
@@ -231,13 +231,12 @@ int msm_perf_debugfs_init(struct drm_minor *minor)
return 0;
 
 fail:
-   msm_perf_debugfs_cleanup(minor);
+   msm_perf_debugfs_cleanup(priv);
return -1;
 }
 
-void msm_perf_debugfs_cleanup(struct drm_minor *minor)
+void msm_perf_debugfs_cleanup(struct msm_drm_private *priv)
 {
-   struct msm_drm_private *priv = minor->dev->dev_private;
struct msm_perf_state *perf = priv->perf;
 
if (!perf)
diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c
index ab0b39f..3df7322 100644
--- a/drivers/gpu/drm/msm/msm_rd.c
+++ b/drivers/gpu/drm/msm/msm_rd.c
@@ -245,13 +245,12 @@ int msm_rd_debugfs_init(struct drm_minor *minor)
return 0;
 
 fail:
-   msm_rd_debugfs_cleanup(minor);
+   msm_rd_debugfs_cleanup(priv);
return -1;
 }
 
-void msm_rd_debugfs_cleanup(struct drm_minor *minor)
+void msm_rd_debugfs_cleanup

[PATCH 2/3] drm/debugfs: Remove the drm_driver.debugfs_cleanup callback

[Noralf Trønnes]

Remove the .debugfs_cleanup() callback now that all the users are gone.

Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/drm_debugfs.c | 5 -
 include/drm/drm_drv.h | 1 -
 2 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index 8b2c61a..1d2d18d 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -242,14 +242,9 @@ static void drm_debugfs_remove_all_files(struct drm_minor 
*minor)
  */
 int drm_debugfs_cleanup(struct drm_minor *minor)
 {
-   struct drm_device *dev = minor->dev;
-
if (!minor->debugfs_root)
return 0;
 
-   if (dev->driver->debugfs_cleanup)
-   dev->driver->debugfs_cleanup(minor);
-
drm_debugfs_remove_all_files(minor);
 
debugfs_remove_recursive(minor->debugfs_root);
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index 661ca24..8ed1ef5 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -302,7 +302,6 @@ struct drm_driver {
void (*master_drop)(struct drm_device *dev, struct drm_file *file_priv);
 
int (*debugfs_init)(struct drm_minor *minor);
-   void (*debugfs_cleanup)(struct drm_minor *minor);
 
/**
 * @gem_free_object: deconstructor for drm_gem_objects
-- 
2.10.2

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[PATCH 3/3] drm/qxl: Remove qxl_debugfs_remove_files()

[Noralf Trønnes]

drm_debugfs_cleanup() now removes all minor->debugfs_list entries
automatically, so it's not necessary to call drm_debugfs_remove_files().

Cc: airl...@linux.ie
Cc: kra...@redhat.com
Signed-off-by: Noralf Trønnes 
---
 drivers/gpu/drm/qxl/qxl_debugfs.c | 13 -
 drivers/gpu/drm/qxl/qxl_drv.h |  1 -
 drivers/gpu/drm/qxl/qxl_kms.c |  1 -
 3 files changed, 15 deletions(-)

diff --git a/drivers/gpu/drm/qxl/qxl_debugfs.c 
b/drivers/gpu/drm/qxl/qxl_debugfs.c
index 8e6c780..ffe821b 100644
--- a/drivers/gpu/drm/qxl/qxl_debugfs.c
+++ b/drivers/gpu/drm/qxl/qxl_debugfs.c
@@ -129,16 +129,3 @@ int qxl_debugfs_add_files(struct qxl_device *qdev,
 #endif
return 0;
 }
-
-void qxl_debugfs_remove_files(struct qxl_device *qdev)
-{
-#if defined(CONFIG_DEBUG_FS)
-   unsigned i;
-
-   for (i = 0; i < qdev->debugfs_count; i++) {
-   drm_debugfs_remove_files(qdev->debugfs[i].files,
-qdev->debugfs[i].num_files,
-qdev->ddev.primary);
-   }
-#endif
-}
diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h
index c048170..ed50a5b 100644
--- a/drivers/gpu/drm/qxl/qxl_drv.h
+++ b/drivers/gpu/drm/qxl/qxl_drv.h
@@ -232,7 +232,6 @@ int qxl_debugfs_add_files(struct qxl_device *rdev,
 struct drm_info_list *files,
 unsigned nfiles);
 int qxl_debugfs_fence_init(struct qxl_device *rdev);
-void qxl_debugfs_remove_files(struct qxl_device *qdev);
 
 struct qxl_device;
 
diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c
index 2b1e1f3..1c46532 100644
--- a/drivers/gpu/drm/qxl/qxl_kms.c
+++ b/drivers/gpu/drm/qxl/qxl_kms.c
@@ -284,5 +284,4 @@ void qxl_device_fini(struct qxl_device *qdev)
qdev->rom = NULL;
qdev->mode_info.modes = NULL;
qdev->mode_info.num_modes = 0;
-   qxl_debugfs_remove_files(qdev);
 }
-- 
2.10.2

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[PATCH 0/3] drm: debugfs: Remove all files automatically on cleanup part 2

[Noralf Trønnes]

This is a follow up that removes the drm_driver.debugfs_cleanup callback.

Tegra is the only remaining user of drm_debugfs_remove_files().

Note:
Patches are only compile tested.

Noralf.


Noralf Trønnes (3):
  drm/msm: Remove msm_debugfs_cleanup()
  drm/debugfs: Remove the drm_driver.debugfs_cleanup callback
  drm/qxl: Remove qxl_debugfs_remove_files()

 drivers/gpu/drm/drm_debugfs.c |  5 -
 drivers/gpu/drm/msm/msm_debugfs.c | 15 ---
 drivers/gpu/drm/msm/msm_debugfs.h |  1 -
 drivers/gpu/drm/msm/msm_drv.c |  4 +++-
 drivers/gpu/drm/msm/msm_drv.h |  4 ++--
 drivers/gpu/drm/msm/msm_kms.h |  1 -
 drivers/gpu/drm/msm/msm_perf.c|  5 ++---
 drivers/gpu/drm/msm/msm_rd.c  |  5 ++---
 drivers/gpu/drm/qxl/qxl_debugfs.c | 13 -
 drivers/gpu/drm/qxl/qxl_drv.h |  1 -
 drivers/gpu/drm/qxl/qxl_kms.c |  1 -
 include/drm/drm_drv.h |  1 -
 12 files changed, 9 insertions(+), 47 deletions(-)

--
2.10.2

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[Bug 99974] Pinned memory is extremely slow on Dolphin

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99974

--- Comment #1 from Marek Olšák  ---
Has it ever been fast? Even with a different GPU?

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Re: linux-next: build failure after merge of the sunxi tree

[Maxime Ripard]

Hi Stephen, Daniel,

On Tue, Mar 07, 2017 at 11:10:19AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> After merging the sunxi tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
> 
> drivers/gpu/drm/sun4i/sun4i_crtc.c: In function 'sun4i_crtc_enable_vblank':
> drivers/gpu/drm/sun4i/sun4i_crtc.c:109:31: error: 'struct sun4i_crtc' has no 
> member named 'drv'
>   struct sun4i_drv *drv = scrtc->drv;
>^
> drivers/gpu/drm/sun4i/sun4i_crtc.c: In function 'sun4i_crtc_disable_vblank':
> drivers/gpu/drm/sun4i/sun4i_crtc.c:121:31: error: 'struct sun4i_crtc' has no 
> member named 'drv'
>   struct sun4i_drv *drv = scrtc->drv;
>^
> 
> Caused by commit
> 
>   50480a78e282 ("drm: sun4i: use vblank hooks in struct drm_crtc_funcs")
> 
> from the drm-misc tree interacting with commit
> 
>   1b8d109585df ("drm/sun4i: Add backend and tcon pointers to sun4i_crtc")
> 
> from the sunxi tree.

I just rebased my tree on top of the latest drm-misc tag
(drm-misc-next-2017-03-06). It should compile, and not have merge
conflicts anymore.

Thanks!
Maxime

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Re: [PATCH 0/6] drm/msm: Add per-instance pagetables

[Daniel Vetter]

On Tue, Mar 07, 2017 at 10:14:14AM -0700, Jordan Crouse wrote:
> Using the framework described here
> 
> https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020716.html
> 
> This implements per-instance pagetables for the GPU driver creating an
> individual pagetable for each file descriptor (so not strictly per-process
> but in practice we can't share buffers between file descriptors anyway without
> importing them).

This is pretty much how it's done everywhere else. Or well, maybe at a
context level, if your driver allos creation of additional contexts.

Might be good to document that somewhere in drm-mm.rst as best practices
for gem drivers ... Volunteered?
-Daniel

> 
> This is the brief workflow for the process:
> 
>  - At init, the driver attaches an UNMANGED domain to the IOMMU (context bank 
> 0)
> 
>  - All "global" buffers (kernel side GPU buffers such as ringbuffers, etc) are
>mapped into the TTBR1 space which is defined as any address with bit 48 
> set.
>In pratice we have discovered that for reasons yet uknown, bit 47 also has
>to be set for the GPU to sign extend correctly, so the TTBR1 region is
>defined as starting at 0x8___.
> 
>  - When a new file descriptor is opened, a dynamic domain is cloned from the
>real domain - this does not program the hardware but it creates a pagetable
>and returns a pointer that we can use to map memory to - this is wrapped 
> in a
>new addresss space and used for all allocations created with the file
>descriptor.
> 
>  - At command submission time, a SMMU_TABLE_UPDATE packet is set before every
>command which contains the physical address of the TTBR0 register for the
>pagetable associated with the process - the GPU will automatically switch
>the pagetable for the process.
> 
> Because no kernel side allocations are in the TTBR0 space there is no setup
> required to switch the TTBR0 pagetable and we do not need to reprogram it
> after the command is over since the next command will rewrite the register.
> This makes the code significantly more simple than it could be (*cough*
> downstream *cough*).
> 
> I'm sure there will be questions, and I'm sure that what we have won't be what
> is finally decided upon in the arm-smmu driver (in particular there are some
> nice parts of the arm-v3 SVM solution that we can borrow) but I think it is
> important to get eyeballs on this for posterity.
> 
> Thanks!
> Jordan
> 
> Jordan Crouse (6):
>   drm/msm: Enable 64 bit mode by default
>   drm/msm: Pass the MMU domain index in struct msm_file_private
>   drm/msm: Make separate iommu function tables for v1 and v2 MMUs
>   drm/msm: Use TTBR1 for kernel side GPU buffer objects
>   drm/msm: Support dynamic IOMMU domains
>   drm/msm: a5xx: Support per-instance pagetables
> 
>  arch/arm64/boot/dts/qcom/msm8996.dtsi |   2 +
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c |  78 ++-
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.h |  17 
>  drivers/gpu/drm/msm/adreno/a5xx_preempt.c |  61 +---
>  drivers/gpu/drm/msm/adreno/adreno_gpu.c   |  18 +++-
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h   |   2 +
>  drivers/gpu/drm/msm/msm_drv.c |  60 +---
>  drivers/gpu/drm/msm/msm_drv.h |   9 +-
>  drivers/gpu/drm/msm/msm_gem.h |   1 +
>  drivers/gpu/drm/msm/msm_gem_submit.c  |  12 ++-
>  drivers/gpu/drm/msm/msm_gem_vma.c |  38 ++--
>  drivers/gpu/drm/msm/msm_gpu.c |   3 +-
>  drivers/gpu/drm/msm/msm_iommu.c   | 151 
> --
>  drivers/gpu/drm/msm/msm_iommu.h   |  34 +++
>  drivers/gpu/drm/msm/msm_mmu.h |   2 +-
>  15 files changed, 415 insertions(+), 73 deletions(-)
>  create mode 100644 drivers/gpu/drm/msm/msm_iommu.h
> 
> -- 
> 1.9.1
> 
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Re: [PATCH] drm/dp: Add missing description to parameter

[Sean Paul]

On Tue, Mar 07, 2017 at 09:35:11PM +0100, Tomeu Vizoso wrote:
> Gabriel Krisman reported these warnings when building the documentation:
> 
>  ./drivers/gpu/drm/drm_dp_helper.c:1165: warning: No description found
> for parameter 'crtc'
> ./drivers/gpu/drm/drm_dp_helper.c:1166: warning: No description found
> for parameter 'crtc'
> 

I've now added htmldocs build to my pre-merge build testing so I'll hopefully
catch this earlier (no promises).

In the meantime, this has been applied to -misc

Thanks,

Sean

> Signed-off-by: Tomeu Vizoso 
> ---
>  drivers/gpu/drm/drm_dp_helper.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index c40cfe2e63ab..3e5f52110ea1 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -1158,6 +1158,7 @@ EXPORT_SYMBOL(drm_dp_psr_setup_time);
>  /**
>   * drm_dp_start_crc() - start capture of frame CRCs
>   * @aux: DisplayPort AUX channel
> + * @crtc: CRTC displaying the frames whose CRCs are to be captured
>   *
>   * Returns 0 on success or a negative error code on failure.
>   */
> -- 
> 2.9.3
> 
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[Bug 100071] [Regression] Tomb Raider: TressFX broken with recent LLVM

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100071

--- Comment #2 from Marek Olšák  ---
Not sure but this might help: https://reviews.llvm.org/D30717

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[Bug 100095] [Regression] Volumetric lighting result in white surface

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100095

--- Comment #1 from Marek Olšák  ---
Not sure but this might help: https://reviews.llvm.org/D30717

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Re: [PATCH v4 1/7] drm: Add DRM support for tiny LCD displays

[Daniel Vetter]

On Sat, Feb 11, 2017 at 07:48:52PM +0100, Noralf Trønnes wrote:
> +const struct file_operations tinydrm_fops = {
> + .owner  = THIS_MODULE,
> + .open   = drm_open,
> + .release= drm_release,
> + .unlocked_ioctl = drm_ioctl,
> +#ifdef CONFIG_COMPAT
> + .compat_ioctl   = drm_compat_ioctl,
> +#endif
> + .poll   = drm_poll,
> + .read   = drm_read,
> + .llseek = no_llseek,
> + .mmap   = drm_gem_cma_mmap,
> +};
> +EXPORT_SYMBOL(tinydrm_fops);

Just spotted this while doing a drive-by refactoring, this doesn't really
work. The THIS_MODULE must be in the source code for your driver, and
can't be in some helper library module like tinydrm.ko.

I'm working on a macro to make this easier, and I guess you could try to
integrate that into your driver macro somehow (probably simplest to
generate the entire structure and just pass name+desc to that macro,
everything else is boilerplate anyway).

I'll cc you on that patch.
-Daniel
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[Bug 100089] Space Run rendering prolems

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100089

LunarG  changed:

   What|Removed |Added

 QA Contact|intel-3d-bugs@lists.freedes |dri-devel@lists.freedesktop
   |ktop.org|.org
   Assignee|intel-3d-bugs@lists.freedes |dri-devel@lists.freedesktop
   |ktop.org|.org
  Component|Drivers/DRI/i965|Drivers/Gallium/radeonsi

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Re: [PATCH 00/19] drm: debugfs: Remove all files automatically on cleanup

[Daniel Vetter]

On Mon, Jan 30, 2017 at 10:10:15AM +0100, Thierry Reding wrote:
> On Mon, Jan 30, 2017 at 10:03:44AM +0100, Daniel Vetter wrote:
> > On Mon, Jan 30, 2017 at 09:58:48AM +0100, Thierry Reding wrote:
> > > On Fri, Jan 27, 2017 at 03:05:46PM +0100, Daniel Vetter wrote:
> > > > On Fri, Jan 27, 2017 at 10:36:16AM +0100, Thierry Reding wrote:
> > > > > On Fri, Jan 27, 2017 at 08:49:34AM +0100, Daniel Vetter wrote:
> > > > > > On Thu, Jan 26, 2017 at 11:56:02PM +0100, Noralf Trønnes wrote:
> > > > > > > This patchset removes the need for drivers to clean up their 
> > > > > > > debugfs
> > > > > > > files on exit. It is done automatically in drm_debugfs_cleanup().
> > > > > > > This funtion is also called should the driver error out in it's
> > > > > > > drm_driver.debugfs_init callback.
> > > > > > > 
> > > > > > > Two drivers still use drm_debugfs_remove_files():
> > > > > > > - tegra in it's connectors, not sure if I can remove it.
> > > > > > 
> > > > > > I read through them, and they're removed on the component device 
> > > > > > nodes
> > > > > > stuff. That looks somewhat fishy from a lifetime point of view, and 
> > > > > > I
> > > > > > think removing all that code would be better, too.
> > > > > 
> > > > > What makes you think that's problematic from a lifetime point of view?
> > > > > The component device is tied to the DRM device, so these callbacks are
> > > > > called at the right time.
> > > > 
> > > > debugfs is a userspace interface, which should disappear when
> > > > drm_dev_unregister gets called. I'm not sure at all whether that lines 
> > > > up
> > > > with the cleanup of all your component nodes, but otoh it's rather
> > > > academic since you can't hotplug a tegra.
> > > > 
> > > > > That said, I think it's safe to remove the other debugfs files from
> > > > > Tegra. It might not be possible to remove the cleanup functions
> > > > > altogether, though, because they have to do a special dance involving
> > > > > kmemdup() drm_debugfs_create_files() and kfree() in order to support
> > > > > debugfs files for multiple instances of subdevices.
> > > > 
> > > > Hm, that entire "do debugfs on the minor" thing makes almost never 
> > > > sense.
> > > > All the things we have left in modern drivers are either per-fd, or
> > > > per-device. Nothing of interest is per-minor. Or do you mean something
> > > > else?
> > > 
> > > I'm not sure I understand what you're saying. We have plenty of code
> > > that adds debugfs files to the connector's debugfs entry. And that's
> > > within the minor's debugfs root.
> > > 
> > > Am I missing something?
> > 
> > Per-connector entries are fine, per-minor imo not.
> 
> Most, if not all, debugfs files in Tegra a per-connector. We have a
> couple that are per-CRTC. And then we have two files that are on the
> minor, which is something I had copied from i915, if I remember
> correctly, though I can't seem to find the original anymore. Maybe
> that was moved somewhere else in the meantime?

All the code I've found in tegra about debugfs is per drm_minor. Some of
it create subdirectories within that, but nothing uses the crtc and
connector ->debugfs_root stuff (which is only in the primary drm_minor
debugfs directory).

> > This is a historical accident, but it also doesn't really hurt anyone.
> > I think it'd make much more sense to move everything into a
> > per-devices entry (with maybe backwards compat links from minor to
> > devices).
> 
> With per-device entries you mean rooted at the device backing the CRTC,
> encoder, connector, ...?

I didn't see any drm support for encoders, no idea what you mean.

> > But really, this is 100% orthogonal to the cleanup here.
> 
> If we want to get rid of the remainder of the cleanup, then it's not
> entirely orthogonal anymore. =)
> 
> Not to say that this cleanup isn't useful in its own right.

Well, looking at this a bit more we might go even further by using
debugfs_remove_recursive(), then we could remove even the tegra stuff. Atm
I think that's not doable because tegra creates its own subdirectories in
drm_minor->debugfs_root. I guess that's a mess for a different day though.
-Daniel
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Re: [PATCH v10 3/3] arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board

[Krzysztof Kozlowski]

On Wed, Feb 22, 2017 at 10:09:54AM +0900, Hoegeun Kwon wrote:
> From: Hyungwon Hwang 
> 
> This patch add the panel device tree node for S6E3HA2 display
> controller to TM2 dts.
> 
> Signed-off-by: Hyungwon Hwang 
> Signed-off-by: Andrzej Hajda 
> Signed-off-by: Chanwoo Choi 
> Signed-off-by: Hoegeun Kwon 
> Tested-by: Chanwoo Choi 
> ---
>  arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 12 
>  1 file changed, 12 insertions(+)

I tried to apply but:
fatal: corrupt patch at line 37
Patch failed at 0001 arm64: dts: exynos: Add support for S6E3HA2 panel
device on TM2 board

Please fix, rebase, add blank link as suggested by Javier and send a
v11.

Best regards,
Krzysztof
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Re: [Intel-gfx] [PATCH v1] drm/i915/bxt: use NULL for GPIO connection ID

[Andy Shevchenko]

On Sun, 2017-02-26 at 22:45 +0100, Daniel Vetter wrote:
> On Tue, Feb 21, 2017 at 06:52:24PM +0200, Andy Shevchenko wrote:
> > On Tue, 2017-02-21 at 18:26 +0200, Jani Nikula wrote:
> > > On Tue, 21 Feb 2017, Andy Shevchenko  > > l.co
> > > m> wrote:
> > > > The commit 213e08ad60ba ("drm/i915/bxt: add bxt dsi gpio element
> > > > support") enables GPIO support for Broxton based platforms.
> > > > 
> > > > While using that API we might get into troubles in the future,
> > > > because
> > > > we can't rely on label "panel" in the driver since vendor
> > > > firmware
> > > > might
> > > > provide any GPIO pin there, e.g. "reset", and even mark it in
> > > > _DSD
> > > > (in
> > > > which case the request will fail).
> > > > 
> > > > To avoid inconsistency and potential issues we have two options:
> > > > a) generate GPIO ACPI mapping table and supply it via
> > > > acpi_dev_add_driver_gpios(), or
> > > > b) just pass NULL as connection ID.
> > > > 
> > > > The b) approach is much simplier and would work since the driver
> > > > relies
> > > > on GPIO indeces only. Moreover, the _CRS fallback mechanism,
> > > > when
> > > > requesting GPIO, is going to be stricter, and supplying non-NULL
> > > > connection ID when neither _DSD, nor GPIO ACPI mapping is
> > > > present,
> > > > will
> > > > make request fail.
> > > 
> > > The patch version log in the commit suggests otherwise; we'd tried
> > > and
> > > failed with NULL,
> > 
> > Can I see DSDT excerpts of the platform that fails?
> > 
> > >  until Mika realized passing "panel" works:
> > > 
> > > v2 by Mika: switch *NULL* to *"panel"* when requesting gpio
> > > for
> > > MIPI/DSI
> > > panel.
> > > 
> > > See also [1]. What has changed since then that should make this
> > > work
> > > now? We shouldn't apply until we get Tested-by's.
> > 
> > Not changed yet, but *going to be*. See my repository here [2].
> > To fix the mess with GPIO ACPI stuff we are going to make request
> > stricter as I pointed in commit message above, i.e. asking for a
> > GPIO by
> > connection ID without _DSD present will guarantee -ENOENT since it
> > will
> > be no fallback to _CRS. You may follow discussion in our internal
> > mailing list for drivers.
> 
> Why exactly is this being discussed on an internal mailing list?
> Upstream
> happens in public ...

It was a prelininary discussion and it's sad you didn't notice it.

Nevertheless, Hans started it in public mailing list here [1].

I would include you in Cc list for my further replies there.

Mika K., my branch is here [2] with above patch included. Can you,
please, test your use case? Because it sounds too strange to me that
connection ID in there affects somehow the PM flow. It very likely
unveils a bug somewhere else.

[1] https://www.spinics.net/lists/linux-input/msg49127.html
[2] http://bitbucket.org/andy-shev/linux/branch/topic%2Fuart%2frpm

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