[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hello Andrzej,
>
>
> Andrzej Hajda wrote:
>> On 27.09.2016 13:22, Tobias Jakobi wrote:
>>> Hello Inki,
>>>
>>>
>>> Inki Dae wrote:
2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
> in mixer_cfg_layer().
> Trigger this via atomic flush.
>
> Changes in v2:
> - issue mixer_cfg_layer() in mixer_disable()
> - rename fields as suggested by Andrzej
> - added docu to mixer context struct
> - simplify mixer_win_reset() as well
>
> Changes in v3:
> - simplify some conditions as suggested by Inki
> - add docu to mixer_cfg_layer()
> - fold switch statements into a single one
>
> Signed-off-by: Tobias Jakobi
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 135
> ++
> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
> 2 files changed, 92 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 1e78d57..4f06f4d 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
> DRM_FORMAT_NV21,
> };
>
> +/*
> + * Mixer context structure.
> + *
> + * @crtc: The HDMI CRTC attached to the mixer.
> + * @planes: Array of plane objects for each of the mixer windows.
> + * @active_windows: Cache of the mixer's hardware state.
> + * Tracks which mixer windows are active/inactive.
> + * @pipe: The CRTC index.
> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
> + * @mixer_resources: A struct containing registers, clocks, etc.
> + * @mxr_ver: The hardware revision/version of the mixer.
> + */
> struct mixer_context {
> struct platform_device *pdev;
> struct device *dev;
> struct drm_device *drm_dev;
> struct exynos_drm_crtc *crtc;
> struct exynos_drm_plane planes[MIXER_WIN_NR];
> + unsigned long active_windows;
> int pipe;
> unsigned long flags;
>
> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context
> *ctx, unsigned int height)
> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
> }
>
> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
> - unsigned int priority, bool enable)
> +/**
> + * mixer_cfg_layer - apply layer configuration to hardware
> + * @ctx: mixer context
> + *
> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
> + * using the 'active_windows' field of the the mixer content, and
> + * the pixel format of the framebuffers associated with the enabled
> + * windows.
> + *
> + * Has to be called under mixer lock.
> + */
> +static void mixer_cfg_layer(struct mixer_context *ctx)
> {
> struct mixer_resources *res = &ctx->mixer_res;
> - u32 val = enable ? ~0 : 0;
> -
> - switch (win) {
> - case 0:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP0_VAL(priority),
> - MXR_LAYER_CFG_GRP0_MASK);
> - break;
> - case 1:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP1_VAL(priority),
> - MXR_LAYER_CFG_GRP1_MASK);
> + unsigned int win;
>
> - break;
> - case VP_DEFAULT_WIN:
> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
> - vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
> - mixer_reg_writemask(res, MXR_CFG, val,
> - MXR_CFG_VP_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_VP_VAL(priority),
> - MXR_LAYER_CFG_VP_MASK);
> + struct exynos_drm_plane_state *state;
> + struct drm_framebuffer *fb;
> + unsigned int priority;
> + u32 mxr_cfg = 0, mxr_layer_cfg = 0, vp_enable = 0;
> + bool enable;
> +
> + for (win = 0; win < MIXER_WIN_NR; ++win) {
> + state = to_exynos_plane_state(ctx->planes[win].base.state);
> + fb = state->fb;
> +
> + priority = state->base.normalized_zpos + 1;
> + enable = test_bit(win, &ctx->active_windows);
> +
> + if (!enable)
> + continue;
> +
> +
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 27ì¼ 20:22ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hey Inki,
>
>
> Inki Dae wrote:
>> 2016ë
09ì 27ì¼ 14:40ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Inki Dae wrote:
2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
> in mixer_cfg_layer().
> Trigger this via atomic flush.
>
> Changes in v2:
> - issue mixer_cfg_layer() in mixer_disable()
> - rename fields as suggested by Andrzej
> - added docu to mixer context struct
> - simplify mixer_win_reset() as well
>
> Changes in v3:
> - simplify some conditions as suggested by Inki
> - add docu to mixer_cfg_layer()
> - fold switch statements into a single one
>
> Signed-off-by: Tobias Jakobi
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 135
> ++
> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
> 2 files changed, 92 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 1e78d57..4f06f4d 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
> DRM_FORMAT_NV21,
> };
>
> +/*
> + * Mixer context structure.
> + *
> + * @crtc: The HDMI CRTC attached to the mixer.
> + * @planes: Array of plane objects for each of the mixer windows.
> + * @active_windows: Cache of the mixer's hardware state.
> + * Tracks which mixer windows are active/inactive.
> + * @pipe: The CRTC index.
> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
> + * @mixer_resources: A struct containing registers, clocks, etc.
> + * @mxr_ver: The hardware revision/version of the mixer.
> + */
> struct mixer_context {
> struct platform_device *pdev;
> struct device *dev;
> struct drm_device *drm_dev;
> struct exynos_drm_crtc *crtc;
> struct exynos_drm_plane planes[MIXER_WIN_NR];
> + unsigned long active_windows;
> int pipe;
> unsigned long flags;
>
> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context
> *ctx, unsigned int height)
> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
> }
>
> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
> - unsigned int priority, bool enable)
> +/**
> + * mixer_cfg_layer - apply layer configuration to hardware
> + * @ctx: mixer context
> + *
> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
> + * using the 'active_windows' field of the the mixer content, and
> + * the pixel format of the framebuffers associated with the enabled
> + * windows.
> + *
> + * Has to be called under mixer lock.
> + */
> +static void mixer_cfg_layer(struct mixer_context *ctx)
> {
> struct mixer_resources *res = &ctx->mixer_res;
> - u32 val = enable ? ~0 : 0;
> -
> - switch (win) {
> - case 0:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP0_VAL(priority),
> - MXR_LAYER_CFG_GRP0_MASK);
> - break;
> - case 1:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP1_VAL(priority),
> - MXR_LAYER_CFG_GRP1_MASK);
> + unsigned int win;
>
> - break;
> - case VP_DEFAULT_WIN:
> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
> - vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
> - mixer_reg_writemask(res, MXR_CFG, val,
> - MXR_CFG_VP_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_VP_VAL(priority),
> - MXR_LAYER_CFG_VP_MASK);
> + struct exynos_drm_plane_state *state;
> + struct drm_framebuffer *fb;
> + unsigned int priority;
> + u32 mxr_cfg = 0, mxr_layer_cfg = 0, vp_enable = 0;
> + bool enable;
> +
> + for (win = 0; win < MIXER_WIN_NR; ++win) {
> + state = to_exynos_plane_state(ctx->planes[win].base.state);
> + fb = state->fb;
> +
> + priority = state->base.normalized_zpos + 1;
> + enable = test_bit(win, &ctx->active_windows);
> +
> + if (!enable)
> + continue;
> +
> + BUG_
[PATCH 0/6] drm/exynos: g2d: rework sleep and runtime PM
We would need to review this patch series for -next in a hurry.
I have to request git-pull soon.
2016ë
09ì 28ì¼ 00:50ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hello everyone,
>
> as discussed with Marek I have broken down my initial patch into smaller
> piecer.
>
> Anyway, this series fixes a regression introduced by commit
> b05984e21a7e000bf5074ace00d7a574944b2c16.
>
> With best wishes,
> Tobias
>
> Tobias Jakobi (6):
> Revert "drm/exynos: g2d: fix system and runtime pm integration"
> drm/exynos: g2d: move PM management to runqueue worker
> drm/exynos: g2d: remove runqueue nodes in g2d_{close,remove}()
> drm/exynos: g2d: wait for engine to finish
> drm/exynos: g2d: use autosuspend mode for PM runtime
> drm/exynos: g2d: simplify g2d_free_runqueue_node()
>
> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 237
> +---
> 1 file changed, 188 insertions(+), 49 deletions(-)
>
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 28ì¼ 08:31ì Inki Dae ì´(ê°) ì´ ê¸:
>
>
> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hello Andrzej,
>>
>>
>> Andrzej Hajda wrote:
>>> On 27.09.2016 13:22, Tobias Jakobi wrote:
Hello Inki,
Inki Dae wrote:
> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>> in mixer_cfg_layer().
>> Trigger this via atomic flush.
>>
>> Changes in v2:
>> - issue mixer_cfg_layer() in mixer_disable()
>> - rename fields as suggested by Andrzej
>> - added docu to mixer context struct
>> - simplify mixer_win_reset() as well
>>
>> Changes in v3:
>> - simplify some conditions as suggested by Inki
>> - add docu to mixer_cfg_layer()
>> - fold switch statements into a single one
>>
>> Signed-off-by: Tobias Jakobi
>> ---
>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>> ++
>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 1e78d57..4f06f4d 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>> DRM_FORMAT_NV21,
>> };
>>
>> +/*
>> + * Mixer context structure.
>> + *
>> + * @crtc: The HDMI CRTC attached to the mixer.
>> + * @planes: Array of plane objects for each of the mixer windows.
>> + * @active_windows: Cache of the mixer's hardware state.
>> + * Tracks which mixer windows are active/inactive.
>> + * @pipe: The CRTC index.
>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>> + * @mixer_resources: A struct containing registers, clocks, etc.
>> + * @mxr_ver: The hardware revision/version of the mixer.
>> + */
>> struct mixer_context {
>> struct platform_device *pdev;
>> struct device *dev;
>> struct drm_device *drm_dev;
>> struct exynos_drm_crtc *crtc;
>> struct exynos_drm_plane planes[MIXER_WIN_NR];
>> +unsigned long active_windows;
>> int pipe;
>> unsigned long flags;
>>
>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context
>> *ctx, unsigned int height)
>> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>> }
>>
>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
>> -unsigned int priority, bool enable)
>> +/**
>> + * mixer_cfg_layer - apply layer configuration to hardware
>> + * @ctx: mixer context
>> + *
>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>> + * using the 'active_windows' field of the the mixer content, and
>> + * the pixel format of the framebuffers associated with the enabled
>> + * windows.
>> + *
>> + * Has to be called under mixer lock.
>> + */
>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>> {
>> struct mixer_resources *res = &ctx->mixer_res;
>> -u32 val = enable ? ~0 : 0;
>> -
>> -switch (win) {
>> -case 0:
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP0_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -MXR_LAYER_CFG_GRP0_VAL(priority),
>> -MXR_LAYER_CFG_GRP0_MASK);
>> -break;
>> -case 1:
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP1_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -MXR_LAYER_CFG_GRP1_VAL(priority),
>> -MXR_LAYER_CFG_GRP1_MASK);
>> +unsigned int win;
>>
>> -break;
>> -case VP_DEFAULT_WIN:
>> -if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>> -vp_reg_writemask(res, VP_ENABLE, val,
>> VP_ENABLE_ON);
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> -MXR_CFG_VP_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -
>> MXR_LAYER_CFG_VP_VAL(priority),
>> -MXR_LAYER_CFG_VP_MASK);
>> +struct exynos_drm_plane_state *state;
>> +struct drm_framebuffer *fb;
>> +unsigned int priority;
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Hey Inki,
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hello Andrzej,
>>
>>
>> Andrzej Hajda wrote:
>>> On 27.09.2016 13:22, Tobias Jakobi wrote:
Hello Inki,
Inki Dae wrote:
> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>> in mixer_cfg_layer().
>> Trigger this via atomic flush.
>>
>> Changes in v2:
>> - issue mixer_cfg_layer() in mixer_disable()
>> - rename fields as suggested by Andrzej
>> - added docu to mixer context struct
>> - simplify mixer_win_reset() as well
>>
>> Changes in v3:
>> - simplify some conditions as suggested by Inki
>> - add docu to mixer_cfg_layer()
>> - fold switch statements into a single one
>>
>> Signed-off-by: Tobias Jakobi
>> ---
>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>> ++
>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 1e78d57..4f06f4d 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>> DRM_FORMAT_NV21,
>> };
>>
>> +/*
>> + * Mixer context structure.
>> + *
>> + * @crtc: The HDMI CRTC attached to the mixer.
>> + * @planes: Array of plane objects for each of the mixer windows.
>> + * @active_windows: Cache of the mixer's hardware state.
>> + * Tracks which mixer windows are active/inactive.
>> + * @pipe: The CRTC index.
>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>> + * @mixer_resources: A struct containing registers, clocks, etc.
>> + * @mxr_ver: The hardware revision/version of the mixer.
>> + */
>> struct mixer_context {
>> struct platform_device *pdev;
>> struct device *dev;
>> struct drm_device *drm_dev;
>> struct exynos_drm_crtc *crtc;
>> struct exynos_drm_plane planes[MIXER_WIN_NR];
>> +unsigned long active_windows;
>> int pipe;
>> unsigned long flags;
>>
>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context
>> *ctx, unsigned int height)
>> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>> }
>>
>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
>> -unsigned int priority, bool enable)
>> +/**
>> + * mixer_cfg_layer - apply layer configuration to hardware
>> + * @ctx: mixer context
>> + *
>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>> + * using the 'active_windows' field of the the mixer content, and
>> + * the pixel format of the framebuffers associated with the enabled
>> + * windows.
>> + *
>> + * Has to be called under mixer lock.
>> + */
>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>> {
>> struct mixer_resources *res = &ctx->mixer_res;
>> -u32 val = enable ? ~0 : 0;
>> -
>> -switch (win) {
>> -case 0:
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP0_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -MXR_LAYER_CFG_GRP0_VAL(priority),
>> -MXR_LAYER_CFG_GRP0_MASK);
>> -break;
>> -case 1:
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP1_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -MXR_LAYER_CFG_GRP1_VAL(priority),
>> -MXR_LAYER_CFG_GRP1_MASK);
>> +unsigned int win;
>>
>> -break;
>> -case VP_DEFAULT_WIN:
>> -if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>> -vp_reg_writemask(res, VP_ENABLE, val,
>> VP_ENABLE_ON);
>> -mixer_reg_writemask(res, MXR_CFG, val,
>> -MXR_CFG_VP_ENABLE);
>> -mixer_reg_writemask(res, MXR_LAYER_CFG,
>> -
>> MXR_LAYER_CFG_VP_VAL(priority),
>> -MXR_LAYER_CFG_VP_MASK);
>> +struct exynos_drm_plane_state *state;
>> +struct drm_framebuffer *fb;
>> +unsigned int priority;
>> +u32 mxr_cfg =
[PATCH 0/6] drm/exynos: g2d: rework sleep and runtime PM
Hello,
Inki Dae wrote:
> We would need to review this patch series for -next in a hurry.
> I have to request git-pull soon.
I just want to point out that I have yet to test the split series.
Currently it's only compile-tested.
But I have done a stress test with both sync and async execution mode
with the first version of the patch (the big one, before the split), and
there everything seemed to work.
So this should apply for this series as well... hopefully :)
With best wishes,
Tobias
> 2016ë
09ì 28ì¼ 00:50ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hello everyone,
>>
>> as discussed with Marek I have broken down my initial patch into smaller
>> piecer.
>>
>> Anyway, this series fixes a regression introduced by commit
>> b05984e21a7e000bf5074ace00d7a574944b2c16.
>>
>> With best wishes,
>> Tobias
>>
>> Tobias Jakobi (6):
>> Revert "drm/exynos: g2d: fix system and runtime pm integration"
>> drm/exynos: g2d: move PM management to runqueue worker
>> drm/exynos: g2d: remove runqueue nodes in g2d_{close,remove}()
>> drm/exynos: g2d: wait for engine to finish
>> drm/exynos: g2d: use autosuspend mode for PM runtime
>> drm/exynos: g2d: simplify g2d_free_runqueue_node()
>>
>> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 237
>> +---
>> 1 file changed, 188 insertions(+), 49 deletions(-)
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc"
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>
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Hello Inki,
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 08:31ì Inki Dae ì´(ê°) ì´ ê¸:
>>
>>
>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Hello Andrzej,
>>>
>>>
>>> Andrzej Hajda wrote:
On 27.09.2016 13:22, Tobias Jakobi wrote:
> Hello Inki,
>
>
> Inki Dae wrote:
>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>>> in mixer_cfg_layer().
>>> Trigger this via atomic flush.
>>>
>>> Changes in v2:
>>> - issue mixer_cfg_layer() in mixer_disable()
>>> - rename fields as suggested by Andrzej
>>> - added docu to mixer context struct
>>> - simplify mixer_win_reset() as well
>>>
>>> Changes in v3:
>>> - simplify some conditions as suggested by Inki
>>> - add docu to mixer_cfg_layer()
>>> - fold switch statements into a single one
>>>
>>> Signed-off-by: Tobias Jakobi
>>> ---
>>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>>> ++
>>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> index 1e78d57..4f06f4d 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>>> DRM_FORMAT_NV21,
>>> };
>>>
>>> +/*
>>> + * Mixer context structure.
>>> + *
>>> + * @crtc: The HDMI CRTC attached to the mixer.
>>> + * @planes: Array of plane objects for each of the mixer windows.
>>> + * @active_windows: Cache of the mixer's hardware state.
>>> + * Tracks which mixer windows are active/inactive.
>>> + * @pipe: The CRTC index.
>>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>>> + * @mixer_resources: A struct containing registers, clocks, etc.
>>> + * @mxr_ver: The hardware revision/version of the mixer.
>>> + */
>>> struct mixer_context {
>>> struct platform_device *pdev;
>>> struct device *dev;
>>> struct drm_device *drm_dev;
>>> struct exynos_drm_crtc *crtc;
>>> struct exynos_drm_plane planes[MIXER_WIN_NR];
>>> + unsigned long active_windows;
>>> int pipe;
>>> unsigned long flags;
>>>
>>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
>>> mixer_context *ctx, unsigned int height)
>>> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>>> }
>>>
>>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
>>> win,
>>> - unsigned int priority, bool enable)
>>> +/**
>>> + * mixer_cfg_layer - apply layer configuration to hardware
>>> + * @ctx: mixer context
>>> + *
>>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>>> + * using the 'active_windows' field of the the mixer content, and
>>> + * the pixel format of the framebuffers associated with the enabled
>>> + * windows.
>>> + *
>>> + * Has to be called under mixer lock.
>>> + */
>>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>>> {
>>> struct mixer_resources *res = &ctx->mixer_res;
>>> - u32 val = enable ? ~0 : 0;
>>> -
>>> - switch (win) {
>>> - case 0:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP0_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP0_VAL(priority),
>>> - MXR_LAYER_CFG_GRP0_MASK);
>>> - break;
>>> - case 1:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP1_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP1_VAL(priority),
>>> - MXR_LAYER_CFG_GRP1_MASK);
>>> + unsigned int win;
>>>
>>> - break;
>>> - case VP_DEFAULT_WIN:
>>> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>>> - vp_reg_writemask(res, VP_ENABLE, val,
>>> VP_ENABLE_ON);
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> - MXR_CFG_VP_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> -
>>> MXR_LAYER_CFG_VP_VAL(priority),
>>> - MXR_LAYER_CFG_VP_MASK);
>>> +
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 28ì¼ 09:03ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hey Inki,
>
>
> Inki Dae wrote:
>>
>>
>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Hello Andrzej,
>>>
>>>
>>> Andrzej Hajda wrote:
On 27.09.2016 13:22, Tobias Jakobi wrote:
> Hello Inki,
>
>
> Inki Dae wrote:
>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>>> in mixer_cfg_layer().
>>> Trigger this via atomic flush.
>>>
>>> Changes in v2:
>>> - issue mixer_cfg_layer() in mixer_disable()
>>> - rename fields as suggested by Andrzej
>>> - added docu to mixer context struct
>>> - simplify mixer_win_reset() as well
>>>
>>> Changes in v3:
>>> - simplify some conditions as suggested by Inki
>>> - add docu to mixer_cfg_layer()
>>> - fold switch statements into a single one
>>>
>>> Signed-off-by: Tobias Jakobi
>>> ---
>>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>>> ++
>>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> index 1e78d57..4f06f4d 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>>> DRM_FORMAT_NV21,
>>> };
>>>
>>> +/*
>>> + * Mixer context structure.
>>> + *
>>> + * @crtc: The HDMI CRTC attached to the mixer.
>>> + * @planes: Array of plane objects for each of the mixer windows.
>>> + * @active_windows: Cache of the mixer's hardware state.
>>> + * Tracks which mixer windows are active/inactive.
>>> + * @pipe: The CRTC index.
>>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>>> + * @mixer_resources: A struct containing registers, clocks, etc.
>>> + * @mxr_ver: The hardware revision/version of the mixer.
>>> + */
>>> struct mixer_context {
>>> struct platform_device *pdev;
>>> struct device *dev;
>>> struct drm_device *drm_dev;
>>> struct exynos_drm_crtc *crtc;
>>> struct exynos_drm_plane planes[MIXER_WIN_NR];
>>> + unsigned long active_windows;
>>> int pipe;
>>> unsigned long flags;
>>>
>>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
>>> mixer_context *ctx, unsigned int height)
>>> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>>> }
>>>
>>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
>>> win,
>>> - unsigned int priority, bool enable)
>>> +/**
>>> + * mixer_cfg_layer - apply layer configuration to hardware
>>> + * @ctx: mixer context
>>> + *
>>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>>> + * using the 'active_windows' field of the the mixer content, and
>>> + * the pixel format of the framebuffers associated with the enabled
>>> + * windows.
>>> + *
>>> + * Has to be called under mixer lock.
>>> + */
>>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>>> {
>>> struct mixer_resources *res = &ctx->mixer_res;
>>> - u32 val = enable ? ~0 : 0;
>>> -
>>> - switch (win) {
>>> - case 0:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP0_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP0_VAL(priority),
>>> - MXR_LAYER_CFG_GRP0_MASK);
>>> - break;
>>> - case 1:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP1_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP1_VAL(priority),
>>> - MXR_LAYER_CFG_GRP1_MASK);
>>> + unsigned int win;
>>>
>>> - break;
>>> - case VP_DEFAULT_WIN:
>>> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>>> - vp_reg_writemask(res, VP_ENABLE, val,
>>> VP_ENABLE_ON);
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> - MXR_CFG_VP_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> -
>>> MXR_LAYER_CFG_VP_VAL(priority),
>>> - MXR_LAYER_CFG_VP_MASK);
>>>
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 28ì¼ 09:12ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hello Inki,
>
>
> Inki Dae wrote:
>>
>>
>> 2016ë
09ì 28ì¼ 08:31ì Inki Dae ì´(ê°) ì´ ê¸:
>>>
>>>
>>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Hello Andrzej,
Andrzej Hajda wrote:
> On 27.09.2016 13:22, Tobias Jakobi wrote:
>> Hello Inki,
>>
>>
>> Inki Dae wrote:
>>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
in mixer_cfg_layer().
Trigger this via atomic flush.
Changes in v2:
- issue mixer_cfg_layer() in mixer_disable()
- rename fields as suggested by Andrzej
- added docu to mixer context struct
- simplify mixer_win_reset() as well
Changes in v3:
- simplify some conditions as suggested by Inki
- add docu to mixer_cfg_layer()
- fold switch statements into a single one
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 135
++
drivers/gpu/drm/exynos/regs-mixer.h | 2 +
2 files changed, 92 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 1e78d57..4f06f4d 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
DRM_FORMAT_NV21,
};
+/*
+ * Mixer context structure.
+ *
+ * @crtc: The HDMI CRTC attached to the mixer.
+ * @planes: Array of plane objects for each of the mixer windows.
+ * @active_windows: Cache of the mixer's hardware state.
+ * Tracks which mixer windows are active/inactive.
+ * @pipe: The CRTC index.
+ * @flags: Bitfield build from the mixer_flag_bits enumerator.
+ * @mixer_resources: A struct containing registers, clocks, etc.
+ * @mxr_ver: The hardware revision/version of the mixer.
+ */
struct mixer_context {
struct platform_device *pdev;
struct device *dev;
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[MIXER_WIN_NR];
+ unsigned long active_windows;
int pipe;
unsigned long flags;
@@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
mixer_context *ctx, unsigned int height)
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}
-static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
win,
- unsigned int priority, bool enable)
+/**
+ * mixer_cfg_layer - apply layer configuration to hardware
+ * @ctx: mixer context
+ *
+ * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
+ * using the 'active_windows' field of the the mixer content, and
+ * the pixel format of the framebuffers associated with the enabled
+ * windows.
+ *
+ * Has to be called under mixer lock.
+ */
+static void mixer_cfg_layer(struct mixer_context *ctx)
{
struct mixer_resources *res = &ctx->mixer_res;
- u32 val = enable ? ~0 : 0;
-
- switch (win) {
- case 0:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP0_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP0_VAL(priority),
- MXR_LAYER_CFG_GRP0_MASK);
- break;
- case 1:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP1_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP1_VAL(priority),
- MXR_LAYER_CFG_GRP1_MASK);
+ unsigned int win;
- break;
- case VP_DEFAULT_WIN:
- if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
- vp_reg_writemask(res, VP_ENABLE, val,
VP_ENABLE_ON);
- mixer_reg_writemask(res, MXR_CFG, val,
- MXR_CFG_VP_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
-
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
> in mixer_cfg_layer().
> Trigger this via atomic flush.
>
> Changes in v2:
> - issue mixer_cfg_layer() in mixer_disable()
> - rename fields as suggested by Andrzej
> - added docu to mixer context struct
> - simplify mixer_win_reset() as well
>
> Changes in v3:
> - simplify some conditions as suggested by Inki
> - add docu to mixer_cfg_layer()
> - fold switch statements into a single one
>
> Signed-off-by: Tobias Jakobi
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 135
> ++
> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
> 2 files changed, 92 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 1e78d57..4f06f4d 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
> DRM_FORMAT_NV21,
> };
>
> +/*
> + * Mixer context structure.
> + *
> + * @crtc: The HDMI CRTC attached to the mixer.
> + * @planes: Array of plane objects for each of the mixer windows.
> + * @active_windows: Cache of the mixer's hardware state.
> + * Tracks which mixer windows are active/inactive.
> + * @pipe: The CRTC index.
> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
> + * @mixer_resources: A struct containing registers, clocks, etc.
> + * @mxr_ver: The hardware revision/version of the mixer.
> + */
> struct mixer_context {
> struct platform_device *pdev;
> struct device *dev;
> struct drm_device *drm_dev;
> struct exynos_drm_crtc *crtc;
> struct exynos_drm_plane planes[MIXER_WIN_NR];
> + unsigned long active_windows;
> int pipe;
> unsigned long flags;
>
> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context
> *ctx, unsigned int height)
> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
> }
>
> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
> - unsigned int priority, bool enable)
> +/**
> + * mixer_cfg_layer - apply layer configuration to hardware
> + * @ctx: mixer context
> + *
> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
> + * using the 'active_windows' field of the the mixer content, and
> + * the pixel format of the framebuffers associated with the enabled
> + * windows.
> + *
> + * Has to be called under mixer lock.
> + */
> +static void mixer_cfg_layer(struct mixer_context *ctx)
> {
> struct mixer_resources *res = &ctx->mixer_res;
> - u32 val = enable ? ~0 : 0;
> -
> - switch (win) {
> - case 0:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP0_VAL(priority),
> - MXR_LAYER_CFG_GRP0_MASK);
> - break;
> - case 1:
> - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP1_VAL(priority),
> - MXR_LAYER_CFG_GRP1_MASK);
> + unsigned int win;
>
> - break;
> - case VP_DEFAULT_WIN:
> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
> - vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
> - mixer_reg_writemask(res, MXR_CFG, val,
> - MXR_CFG_VP_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_VP_VAL(priority),
> - MXR_LAYER_CFG_VP_MASK);
> + struct exynos_drm_plane_state *state;
> + struct drm_framebuffer *fb;
> + unsigned int priority;
> + u32 mxr_cfg = 0, mxr_layer_cfg = 0, vp_enable = 0;
> + bool enable;
> +
> + for (win = 0; win < MIXER_WIN_NR; ++win) {
> + state = to_exynos_plane_state(ctx->planes[win].base.state);
> + fb = state->fb;
> +
> + priority = state->base.normalized_zpos + 1;
> + enable = test_bit(win, &ctx->active_windows);
> +
> + if (!enable)
> + continue;
> +
> + BUG_ON(!fb);
> +
> + /*
> + * TODO: Don't enable alpha blending for the bottom window.
> + */
> + switch (win) {
> + case 0:
> + mxr_cfg |= MXR_CFG_GRP0_ENABLE;
> + mxr_layer_cfg |= MXR_LAYER_CFG_GRP0_VAL(priority);
> + mixer_cfg_gfx_blend(ctx, win,
> is_alpha_format(fb->pixel_format));
> + break;
> +
> + case
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
2016ë
09ì 28ì¼ 09:03ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hey Inki,
>
>
> Inki Dae wrote:
>>
>>
>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Hello Andrzej,
>>>
>>>
>>> Andrzej Hajda wrote:
On 27.09.2016 13:22, Tobias Jakobi wrote:
> Hello Inki,
>
>
> Inki Dae wrote:
>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>>> in mixer_cfg_layer().
>>> Trigger this via atomic flush.
>>>
>>> Changes in v2:
>>> - issue mixer_cfg_layer() in mixer_disable()
>>> - rename fields as suggested by Andrzej
>>> - added docu to mixer context struct
>>> - simplify mixer_win_reset() as well
>>>
>>> Changes in v3:
>>> - simplify some conditions as suggested by Inki
>>> - add docu to mixer_cfg_layer()
>>> - fold switch statements into a single one
>>>
>>> Signed-off-by: Tobias Jakobi
>>> ---
>>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>>> ++
>>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> index 1e78d57..4f06f4d 100644
>>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>>> DRM_FORMAT_NV21,
>>> };
>>>
>>> +/*
>>> + * Mixer context structure.
>>> + *
>>> + * @crtc: The HDMI CRTC attached to the mixer.
>>> + * @planes: Array of plane objects for each of the mixer windows.
>>> + * @active_windows: Cache of the mixer's hardware state.
>>> + * Tracks which mixer windows are active/inactive.
>>> + * @pipe: The CRTC index.
>>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>>> + * @mixer_resources: A struct containing registers, clocks, etc.
>>> + * @mxr_ver: The hardware revision/version of the mixer.
>>> + */
>>> struct mixer_context {
>>> struct platform_device *pdev;
>>> struct device *dev;
>>> struct drm_device *drm_dev;
>>> struct exynos_drm_crtc *crtc;
>>> struct exynos_drm_plane planes[MIXER_WIN_NR];
>>> + unsigned long active_windows;
>>> int pipe;
>>> unsigned long flags;
>>>
>>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
>>> mixer_context *ctx, unsigned int height)
>>> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>>> }
>>>
>>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
>>> win,
>>> - unsigned int priority, bool enable)
>>> +/**
>>> + * mixer_cfg_layer - apply layer configuration to hardware
>>> + * @ctx: mixer context
>>> + *
>>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>>> + * using the 'active_windows' field of the the mixer content, and
>>> + * the pixel format of the framebuffers associated with the enabled
>>> + * windows.
>>> + *
>>> + * Has to be called under mixer lock.
>>> + */
>>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>>> {
>>> struct mixer_resources *res = &ctx->mixer_res;
>>> - u32 val = enable ? ~0 : 0;
>>> -
>>> - switch (win) {
>>> - case 0:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP0_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP0_VAL(priority),
>>> - MXR_LAYER_CFG_GRP0_MASK);
>>> - break;
>>> - case 1:
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> MXR_CFG_GRP1_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> - MXR_LAYER_CFG_GRP1_VAL(priority),
>>> - MXR_LAYER_CFG_GRP1_MASK);
>>> + unsigned int win;
>>>
>>> - break;
>>> - case VP_DEFAULT_WIN:
>>> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>>> - vp_reg_writemask(res, VP_ENABLE, val,
>>> VP_ENABLE_ON);
>>> - mixer_reg_writemask(res, MXR_CFG, val,
>>> - MXR_CFG_VP_ENABLE);
>>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>>> -
>>> MXR_LAYER_CFG_VP_VAL(priority),
>>> - MXR_LAYER_CFG_VP_MASK);
>>>
linux-next: manual merge of the drm-misc tree with the drm tree
Hi all,
Today's linux-next merge of the drm-misc tree got conflicts in:
drivers/gpu/drm/sti/sti_dvo.c
drivers/gpu/drm/sti/sti_hqvdp.c
drivers/gpu/drm/sti/sti_mixer.c
between commits:
bdfd36ef8e64 ("drm/sti: Fix sparse warnings")
b4bba92dfbe2 ("drm/sti: remove stih415-416 platform support")
from the drm tree and commit:
bd233af436ba ("drm/sti: mark symbols static where possible")
from the drm-misc tree.
I fixed it up (I just used the drm-misc tree versions and removed the
comflicting function in the sti_mixer.c case) and can carry the fix as
necessary. This is now fixed as far as linux-next is concerned, but any
non trivial conflicts should be mentioned to your upstream maintainer
when your tree is submitted for merging. You may also want to consider
cooperating with the maintainer of the conflicting tree to minimise any
particularly complex conflicts.
--
Cheers,
Stephen Rothwell
[Bug 97879] [amdgpu] Rocket League: long hangs (several seconds) when loading assets (models/textures/shaders?)
https://bugs.freedesktop.org/show_bug.cgi?id=97879 --- Comment #30 from Michel Dänzer --- (In reply to Eero Tamminen from comment #20) > Apitrace's own CPU overhead is so high that it's not very good for > identifying CPU bottlenecks. That may be true in general, but taking a CPU profile while replaying the referenced apitrace clearly shows that most of the CPU cycles during the startup phase are spent in the GLSL compiler frontend code for me. Can't you reproduce that? Anyway, it looks like there may be at least one other, not shader compilation related, issue at play here. But that doesn't mean nothing can be done about the shader compilation issue. -- You are receiving this mail because: You are on the CC list for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/b12f50f7/attachment.html>
[Bug 97857] card detects non-existent monitor on display port
https://bugs.freedesktop.org/show_bug.cgi?id=97857 --- Comment #10 from Michel Dänzer --- (In reply to Alex Deucher from comment #9) > Maybe some core drm/dp change? Any chance you could bisect? I can try, but probably not before next week. FWIW, according to the attached dmesg outputs, the regression happened between upstream versions 4.5.1 and 4.5.5. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/12c9ff64/attachment.html>
-next trees
Hey all, Back from a week off, I've hoovered up everything and backmerged -rc8 on top. If I've missed anything please let me know, I haven't seen next trees for exynos or nouveau, as possibly a few others, but those are the main two I noticed. Dave.
[PATCH v4] drm/fsl-dcu: Implement gamma_lut atomic crtc properties
Gamma correction is optional and can be used to adjust the color
output values to match the gamut of a particular TFT LCD panel
Errata:
Gamma_R, Gamma_G and Gamma_B registers are little-endian registers
while the rest of the address-space in 2D-ACE is big-endian.
Workaround:
Split the DCU regs into "regs", "palette", "gamma" and "cursor".
Create a second regmap for gamma memory space using little endian.
Suggested-by: Stefan Agner
Signed-off-by: Meng Yi
---
Changes since V1:
-created a second regmap for gamma
-updated the DCU DT binding
-removed Kconfig for gamma and enable gamma when valid data filled.
---
.../devicetree/bindings/display/fsl,dcu.txt| 15 +-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 32
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 35 +-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 7 +
4 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt
b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index 63ec2a6..e3cf2de 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -6,6 +6,15 @@ Required properties:
* "fsl,vf610-dcu".
- reg: Address and length of the register set for dcu.
+ ParameterAddress Range
+
+ Register address space 0x â 0x1FFF
+ Palette/Tile address space 0x2000 â 0x3FFF
+ Gamma_R address space0x4000 â 0x43FF
+ Gamma_G address space0x4400 â 0x47FF
+ Gamma_B address space0x4800 â 0x4BFF
+ Cursor address space 0x4C00 â 0x4FFF
+
- clocks: Handle to "dcu" and "pix" clock (in the order below)
This can be the same clock (e.g. LS1021a)
See ../clocks/clock-bindings.txt for details.
@@ -20,7 +29,11 @@ Optional properties:
Examples:
dcu: dcu at 2ce {
compatible = "fsl,ls1021a-dcu";
- reg = <0x0 0x2ce 0x0 0x1>;
+ reg = <0x0 0x2ce 0x0 0x2000>,
+ <0x0 0x2ce2000 0x0 0x2000>,
+ <0x0 0x2ce4000 0x0 0xc00>,
+ <0x0 0x2ce4c00 0x0 0x400>;
+ reg-names = "regs", "palette", "gamma", "cursor";
clocks = <&platform_clk 0>, <&platform_clk 0>;
clock-names = "dcu", "pix";
big-endian;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..4ff969b 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -22,6 +22,30 @@
#include "fsl_dcu_drm_drv.h"
#include "fsl_dcu_drm_plane.h"
+static void fsl_crtc_gamma_set(struct drm_crtc *crtc, struct drm_color_lut
*lut,
+ uint32_t size)
+{
+ struct fsl_dcu_drm_device *fsl_dev = crtc->dev->dev_private;
+ unsigned int i;
+
+ if (crtc->state->gamma_lut->data) {
+ for (i = 0; i < size; i++) {
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_R + 4 * i,
+lut[i].red);
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_G + 4 * i,
+lut[i].green);
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_B + 4 * i,
+lut[i].blue);
+ }
+
+ regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+ DCU_MODE_EN_GAMMA_MASK,
+ DCU_MODE_GAMMA_ENABLE);
+ } else
+ regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+ DCU_MODE_EN_GAMMA_MASK, 0);
+}
+
static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -37,6 +61,10 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc
*crtc,
drm_crtc_send_vblank_event(crtc, event);
spin_unlock_irq(&crtc->dev->event_lock);
}
+
+ if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut)
+ fsl_crtc_gamma_set(crtc, (struct drm_color_lut *)
+ crtc->state->gamma_lut->data, 256);
}
static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
@@ -135,6 +163,7 @@ static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs =
{
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.set_config = drm_atomic_helper_set_config,
+ .gamma_set = drm_atomic_helper_legacy_gamma_set,
};
int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
@@ -158,5 +187,8 @@ i
[PATCH] drm/sti: mark symbols static where possible
Yes true, patch from Ville
https://lists.freedesktop.org/archives/dri-devel/2016-September/118631.html";
already fix patches sent by Baoyou.
Vincent
On 09/27/2016 09:07 PM, Benjamin Gaignard wrote:
> I think that create conflicts with what is already in Vincent pull
> request where we have fix the problem reported by coccicheck and
> sparse.
>
> https://lists.freedesktop.org/archives/dri-devel/2016-September/118892.html
>
> Benjamin
>
> 2016-09-27 18:35 GMT+02:00 Sean Paul :
>> On Sun, Sep 25, 2016 at 3:57 AM, Baoyou Xie wrote:
>>> We get 6 warnings when building kernel with W=1:
>>> drivers/gpu/drm/sti/sti_mixer.c:361:6: warning: no previous prototype for
>>> 'sti_mixer_set_matrix' [-Wmissing-prototypes]
>>> drivers/gpu/drm/sti/sti_dvo.c:109:5: warning: no previous prototype for
>>> 'dvo_awg_generate_code' [-Wmissing-prototypes]
>>> drivers/gpu/drm/sti/sti_gdp.c:476:5: warning: no previous prototype for
>>> 'sti_gdp_field_cb' [-Wmissing-prototypes]
>>> drivers/gpu/drm/sti/sti_hqvdp.c:786:5: warning: no previous prototype for
>>> 'sti_hqvdp_vtg_cb' [-Wmissing-prototypes]
>>> drivers/gpu/drm/sti/sti_hqvdp.c:1292:5: warning: no previous prototype for
>>> 'sti_hqvdp_bind' [-Wmissing-prototypes]
>>> drivers/gpu/drm/sti/sti_drv.c:143:6: warning: no previous prototype for
>>> 'sti_drm_dbg_cleanup' [-Wmissing-prototypes]
>>>
>>> In fact, these functions are only used in the file in which they are
>>> declared and don't need a declaration, but can be made static.
>>> So this patch marks these functions with 'static'.
>>>
>>> Signed-off-by: Baoyou Xie
>>
>> Applied to -misc, thanks.
>>
>> Sean
>>
>>> ---
>>> drivers/gpu/drm/sti/sti_drv.c | 2 +-
>>> drivers/gpu/drm/sti/sti_dvo.c | 3 ++-
>>> drivers/gpu/drm/sti/sti_gdp.c | 2 +-
>>> drivers/gpu/drm/sti/sti_hqvdp.c | 5 +++--
>>> drivers/gpu/drm/sti/sti_mixer.c | 2 +-
>>> 5 files changed, 8 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/drm/sti/sti_drv.c
>>> index 7cd3804..e6f0706 100644
>>> --- a/drivers/gpu/drm/sti/sti_drv.c
>>> +++ b/drivers/gpu/drm/sti/sti_drv.c
>>> @@ -140,7 +140,7 @@ static int sti_drm_dbg_init(struct drm_minor *minor)
>>> return ret;
>>> }
>>>
>>> -void sti_drm_dbg_cleanup(struct drm_minor *minor)
>>> +static void sti_drm_dbg_cleanup(struct drm_minor *minor)
>>> {
>>> drm_debugfs_remove_files(sti_drm_dbg_list,
>>> ARRAY_SIZE(sti_drm_dbg_list), minor);
>>> diff --git a/drivers/gpu/drm/sti/sti_dvo.c b/drivers/gpu/drm/sti/sti_dvo.c
>>> index 00881eb..4545ad0 100644
>>> --- a/drivers/gpu/drm/sti/sti_dvo.c
>>> +++ b/drivers/gpu/drm/sti/sti_dvo.c
>>> @@ -106,7 +106,8 @@ struct sti_dvo_connector {
>>> container_of(x, struct sti_dvo_connector, drm_connector)
>>>
>>> #define BLANKING_LEVEL 16
>>> -int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
>>> +static int
>>> +dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
>>> {
>>> struct drm_display_mode *mode = &dvo->mode;
>>> struct dvo_config *config = dvo->config;
>>> diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c
>>> index b8d942c..4648d1b 100644
>>> --- a/drivers/gpu/drm/sti/sti_gdp.c
>>> +++ b/drivers/gpu/drm/sti/sti_gdp.c
>>> @@ -473,7 +473,7 @@ static void sti_gdp_disable(struct sti_gdp *gdp)
>>> * RETURNS:
>>> * 0 on success.
>>> */
>>> -int sti_gdp_field_cb(struct notifier_block *nb,
>>> +static int sti_gdp_field_cb(struct notifier_block *nb,
>>> unsigned long event, void *data)
>>> {
>>> struct sti_gdp *gdp = container_of(nb, struct sti_gdp,
>>> vtg_field_nb);
>>> diff --git a/drivers/gpu/drm/sti/sti_hqvdp.c
>>> b/drivers/gpu/drm/sti/sti_hqvdp.c
>>> index b5ee783..7f0dea8 100644
>>> --- a/drivers/gpu/drm/sti/sti_hqvdp.c
>>> +++ b/drivers/gpu/drm/sti/sti_hqvdp.c
>>> @@ -783,7 +783,8 @@ static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
>>> * RETURNS:
>>> * 0 on success.
>>> */
>>> -int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void
>>> *data)
>>> +static int
>>> +sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
>>> {
>>> struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp,
>>> vtg_nb);
>>> int btm_cmd_offset, top_cmd_offest;
>>> @@ -1289,7 +1290,7 @@ static struct drm_plane *sti_hqvdp_create(struct
>>> drm_device *drm_dev,
>>> return &hqvdp->plane.drm_plane;
>>> }
>>>
>>> -int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
>>> +static int sti_hqvdp_bind(struct device *dev, struct device *master, void
>>> *data)
>>> {
>>> struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
>>> struct drm_device *drm_dev = data;
>>> diff --git a/drivers/gpu/drm/sti/sti_mixer.c
>>> b/drivers/gpu/drm/sti/sti_mixer.c
>>> index 7d9aea8..b78cec5 100644
>>> --- a/drivers/gpu/drm/sti/sti_mixer.c
>>> +++ b/drivers/gpu/drm/sti/sti_mixer.c
>>> @@
[PATCH 2/7] drm/doc: Polish for drm_plane.[hc]
On Wed, 28 Sep 2016, Rafael Antognolli wrote:
> Hi Daniel,
>
> On Wed, Sep 21, 2016 at 10:59:25AM +0200, Daniel Vetter wrote:
>> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
>> index 1407715736a5..256219bfd07b 100644
>> --- a/include/drm/drm_plane.h
>> +++ b/include/drm/drm_plane.h
>> @@ -319,10 +319,48 @@ struct drm_plane_funcs {
>> void (*early_unregister)(struct drm_plane *plane);
>> };
>>
>> +/**
>> + * enum drm_plane_type - uapi plane type enumeration
>> + *
>> + * For historical reasons not all planes are made the same. This
>> enumeration is
>> + * used to tell the different types of planes apart to implement the
>> different
>> + * uapi semantics for them. For userspace which is universal plane aware and
>> + * which is using that atomic IOCTL there's no difference between these
>> planes
>> + * (beyong what the driver and hardware can support of course).
>> + *
>> + * For compatibility with legacy userspace, only overlay planes are made
>> + * available to userspace by default. Userspace clients may set the
>> + * DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate that
>> they
>> + * wish to receive a universal plane list containing all plane types. See
>> also
>> + * drm_for_each_legacy_plane().
>> + */
>> enum drm_plane_type {
>> -DRM_PLANE_TYPE_OVERLAY,
>> +/**
>> + * @DRM_PLANE_TYPE_PRIMARY:
>> + *
>> + * Primary planes represent a "main" plane for a CRTC. Primary planes
>> + * are the planes operated upon by CRTC modesetting and flipping
>> + * operations described in the page_flip and set_config hooks in struct
>> + * &drm_crtc_funcs.
>> + */
>> DRM_PLANE_TYPE_PRIMARY,
>> +
>> +/**
>> + * @DRM_PLANE_TYPE_CURSOR:
>> + *
>> + * Cursor planes represent a "cursor" plane for a CRTC. Cursor planes
>> + * are the planes operated upon by the DRM_IOCTL_MODE_CURSOR and
>> + * DRM_IOCTL_MODE_CURSOR2 IOCTLs.
>> + */
>> DRM_PLANE_TYPE_CURSOR,
>> +
>> +/**
>> + * @DRM_PLANE_TYPE_OVERLAY:
>> + *
>> + * Overlay planes represent all non-primary, non-cursor planes. Some
>> + * drivers refer to these types of planes as "sprites" internally.
>> + */
>> +DRM_PLANE_TYPE_OVERLAY,
>> };
>
> This is changing the order (and consequently the values) of these enums.
> But it is not updated in libdrm. I noticed this is causing an issue when
> playing with robclark's version of kmscube (branch atomic):
>
> https://github.com/robclark/kmscube/tree/atomic
>
> It looks like IGT also uses this macro from libdrm:
>
> $ git grep -n DRM_PLANE_TYPE_PRIMARY
> lib/igt_kms.c:1398: case DRM_PLANE_TYPE_PRIMARY:
> tests/kms_frontbuffer_tracking.c:2302: drm.plane_types[i] ==
> DRM_PLANE_TYPE_PRIMARY)
> tests/kms_frontbuffer_tracking.c:2602: drm.plane_types[i] ==
> DRM_PLANE_TYPE_PRIMARY) {
> tests/kms_frontbuffer_tracking.c:2741: drm.plane_types[i] ==
> DRM_PLANE_TYPE_PRIMARY)
>
> Anyway, should we update it on libdrm, bring the order back to its
> original values, or something else? Or am I missing something?
You're absolutely right. But you're missing the fix has already landed
in drm-misc tree:
commit 226714dc7c6af6d0acee449eb2afce08d128edad
Author: Daniel Vetter
Date: Fri Sep 23 08:35:25 2016 +0200
drm: Fix plane type uabi breakage
BR,
Jani.
>
> Thanks,
> Rafael
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Jani Nikula, Intel Open Source Technology Center
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 09:03ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hey Inki,
>>
>>
>> Inki Dae wrote:
>>>
>>>
>>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Hello Andrzej,
Andrzej Hajda wrote:
> On 27.09.2016 13:22, Tobias Jakobi wrote:
>> Hello Inki,
>>
>>
>> Inki Dae wrote:
>>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
in mixer_cfg_layer().
Trigger this via atomic flush.
Changes in v2:
- issue mixer_cfg_layer() in mixer_disable()
- rename fields as suggested by Andrzej
- added docu to mixer context struct
- simplify mixer_win_reset() as well
Changes in v3:
- simplify some conditions as suggested by Inki
- add docu to mixer_cfg_layer()
- fold switch statements into a single one
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 135
++
drivers/gpu/drm/exynos/regs-mixer.h | 2 +
2 files changed, 92 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 1e78d57..4f06f4d 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
DRM_FORMAT_NV21,
};
+/*
+ * Mixer context structure.
+ *
+ * @crtc: The HDMI CRTC attached to the mixer.
+ * @planes: Array of plane objects for each of the mixer windows.
+ * @active_windows: Cache of the mixer's hardware state.
+ * Tracks which mixer windows are active/inactive.
+ * @pipe: The CRTC index.
+ * @flags: Bitfield build from the mixer_flag_bits enumerator.
+ * @mixer_resources: A struct containing registers, clocks, etc.
+ * @mxr_ver: The hardware revision/version of the mixer.
+ */
struct mixer_context {
struct platform_device *pdev;
struct device *dev;
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[MIXER_WIN_NR];
+ unsigned long active_windows;
int pipe;
unsigned long flags;
@@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
mixer_context *ctx, unsigned int height)
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}
-static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
win,
- unsigned int priority, bool enable)
+/**
+ * mixer_cfg_layer - apply layer configuration to hardware
+ * @ctx: mixer context
+ *
+ * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
+ * using the 'active_windows' field of the the mixer content, and
+ * the pixel format of the framebuffers associated with the enabled
+ * windows.
+ *
+ * Has to be called under mixer lock.
+ */
+static void mixer_cfg_layer(struct mixer_context *ctx)
{
struct mixer_resources *res = &ctx->mixer_res;
- u32 val = enable ? ~0 : 0;
-
- switch (win) {
- case 0:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP0_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP0_VAL(priority),
- MXR_LAYER_CFG_GRP0_MASK);
- break;
- case 1:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP1_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP1_VAL(priority),
- MXR_LAYER_CFG_GRP1_MASK);
+ unsigned int win;
- break;
- case VP_DEFAULT_WIN:
- if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
- vp_reg_writemask(res, VP_ENABLE, val,
VP_ENABLE_ON);
- mixer_reg_writemask(res, MXR_CFG, val,
- MXR_CFG_VP_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
-
MXR_LAYER
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Hello Inki,
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 09:03ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hey Inki,
>>
>>
>> Inki Dae wrote:
>>>
>>>
>>> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Hello Andrzej,
Andrzej Hajda wrote:
> On 27.09.2016 13:22, Tobias Jakobi wrote:
>> Hello Inki,
>>
>>
>> Inki Dae wrote:
>>> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
in mixer_cfg_layer().
Trigger this via atomic flush.
Changes in v2:
- issue mixer_cfg_layer() in mixer_disable()
- rename fields as suggested by Andrzej
- added docu to mixer context struct
- simplify mixer_win_reset() as well
Changes in v3:
- simplify some conditions as suggested by Inki
- add docu to mixer_cfg_layer()
- fold switch statements into a single one
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 135
++
drivers/gpu/drm/exynos/regs-mixer.h | 2 +
2 files changed, 92 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 1e78d57..4f06f4d 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
DRM_FORMAT_NV21,
};
+/*
+ * Mixer context structure.
+ *
+ * @crtc: The HDMI CRTC attached to the mixer.
+ * @planes: Array of plane objects for each of the mixer windows.
+ * @active_windows: Cache of the mixer's hardware state.
+ * Tracks which mixer windows are active/inactive.
+ * @pipe: The CRTC index.
+ * @flags: Bitfield build from the mixer_flag_bits enumerator.
+ * @mixer_resources: A struct containing registers, clocks, etc.
+ * @mxr_ver: The hardware revision/version of the mixer.
+ */
struct mixer_context {
struct platform_device *pdev;
struct device *dev;
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[MIXER_WIN_NR];
+ unsigned long active_windows;
int pipe;
unsigned long flags;
@@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
mixer_context *ctx, unsigned int height)
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}
-static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
win,
- unsigned int priority, bool enable)
+/**
+ * mixer_cfg_layer - apply layer configuration to hardware
+ * @ctx: mixer context
+ *
+ * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
+ * using the 'active_windows' field of the the mixer content, and
+ * the pixel format of the framebuffers associated with the enabled
+ * windows.
+ *
+ * Has to be called under mixer lock.
+ */
+static void mixer_cfg_layer(struct mixer_context *ctx)
{
struct mixer_resources *res = &ctx->mixer_res;
- u32 val = enable ? ~0 : 0;
-
- switch (win) {
- case 0:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP0_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP0_VAL(priority),
- MXR_LAYER_CFG_GRP0_MASK);
- break;
- case 1:
- mixer_reg_writemask(res, MXR_CFG, val,
MXR_CFG_GRP1_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP1_VAL(priority),
- MXR_LAYER_CFG_GRP1_MASK);
+ unsigned int win;
- break;
- case VP_DEFAULT_WIN:
- if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
- vp_reg_writemask(res, VP_ENABLE, val,
VP_ENABLE_ON);
- mixer_reg_writemask(res, MXR_CFG, val,
- MXR_CFG_VP_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
-
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Hello Inki,
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 09:12ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hello Inki,
>>
>>
>> Inki Dae wrote:
>>>
>>>
>>> 2016ë
09ì 28ì¼ 08:31ì Inki Dae ì´(ê°) ì´ ê¸:
2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Hello Andrzej,
>
>
> Andrzej Hajda wrote:
>> On 27.09.2016 13:22, Tobias Jakobi wrote:
>>> Hello Inki,
>>>
>>>
>>> Inki Dae wrote:
2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
> in mixer_cfg_layer().
> Trigger this via atomic flush.
>
> Changes in v2:
> - issue mixer_cfg_layer() in mixer_disable()
> - rename fields as suggested by Andrzej
> - added docu to mixer context struct
> - simplify mixer_win_reset() as well
>
> Changes in v3:
> - simplify some conditions as suggested by Inki
> - add docu to mixer_cfg_layer()
> - fold switch statements into a single one
>
> Signed-off-by: Tobias Jakobi
> ---
> drivers/gpu/drm/exynos/exynos_mixer.c | 135
> ++
> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
> 2 files changed, 92 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
> b/drivers/gpu/drm/exynos/exynos_mixer.c
> index 1e78d57..4f06f4d 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
> DRM_FORMAT_NV21,
> };
>
> +/*
> + * Mixer context structure.
> + *
> + * @crtc: The HDMI CRTC attached to the mixer.
> + * @planes: Array of plane objects for each of the mixer windows.
> + * @active_windows: Cache of the mixer's hardware state.
> + * Tracks which mixer windows are active/inactive.
> + * @pipe: The CRTC index.
> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
> + * @mixer_resources: A struct containing registers, clocks, etc.
> + * @mxr_ver: The hardware revision/version of the mixer.
> + */
> struct mixer_context {
> struct platform_device *pdev;
> struct device *dev;
> struct drm_device *drm_dev;
> struct exynos_drm_crtc *crtc;
> struct exynos_drm_plane planes[MIXER_WIN_NR];
> + unsigned long active_windows;
> int pipe;
> unsigned long flags;
>
> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
> mixer_context *ctx, unsigned int height)
> mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
> }
>
> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
> win,
> - unsigned int priority, bool enable)
> +/**
> + * mixer_cfg_layer - apply layer configuration to hardware
> + * @ctx: mixer context
> + *
> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
> + * using the 'active_windows' field of the the mixer content, and
> + * the pixel format of the framebuffers associated with the enabled
> + * windows.
> + *
> + * Has to be called under mixer lock.
> + */
> +static void mixer_cfg_layer(struct mixer_context *ctx)
> {
> struct mixer_resources *res = &ctx->mixer_res;
> - u32 val = enable ? ~0 : 0;
> -
> - switch (win) {
> - case 0:
> - mixer_reg_writemask(res, MXR_CFG, val,
> MXR_CFG_GRP0_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP0_VAL(priority),
> - MXR_LAYER_CFG_GRP0_MASK);
> - break;
> - case 1:
> - mixer_reg_writemask(res, MXR_CFG, val,
> MXR_CFG_GRP1_ENABLE);
> - mixer_reg_writemask(res, MXR_LAYER_CFG,
> - MXR_LAYER_CFG_GRP1_VAL(priority),
> - MXR_LAYER_CFG_GRP1_MASK);
> + unsigned int win;
>
> - break;
> - case VP_DEFAULT_WIN:
> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
> - vp_reg_writemask(res, VP_ENABLE, val,
> VP_ENABLE_ON);
> - mixer_reg_writemask(res, MXR_CFG, val,
> -
[PATCH v5] drm/fsl-dcu: Implement gamma_lut atomic crtc properties
Gamma correction is optional and can be used to adjust the color
output values to match the gamut of a particular TFT LCD panel
Split the DCU regs into "regs", "palette", "gamma" and "cursor".
Create a second regmap for gamma memory space using little endian.
The registers after the first address space are not accessed yet,
hence new device trees would even work with old kernels. Just new
kernel need the new format so we can access the separate gamma
reg space.
Suggested-by: Stefan Agner
Signed-off-by: Meng Yi
---
Changes since V1:
-created a second regmap for gamma
-updated the DCU DT binding
-removed Kconfig for gamma and enable gamma when valid data filled.
-extended and simplified comment lines.
---
.../devicetree/bindings/display/fsl,dcu.txt| 12 +++-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 33
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 35 +-
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 7 +
4 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt
b/Documentation/devicetree/bindings/display/fsl,dcu.txt
index 63ec2a6..8140b5d 100644
--- a/Documentation/devicetree/bindings/display/fsl,dcu.txt
+++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt
@@ -6,6 +6,12 @@ Required properties:
* "fsl,vf610-dcu".
- reg: Address and length of the register set for dcu.
+ Must contain four address/length tuples:
+ 1. Register address space
+ 2. Palette/Tile address space
+ 3. Gamma address space
+ 4. Cursor address space
+- reg-names: Should be "regs", "palette", "gamma" and "cursor"
- clocks: Handle to "dcu" and "pix" clock (in the order below)
This can be the same clock (e.g. LS1021a)
See ../clocks/clock-bindings.txt for details.
@@ -20,7 +26,11 @@ Optional properties:
Examples:
dcu: dcu at 2ce {
compatible = "fsl,ls1021a-dcu";
- reg = <0x0 0x2ce 0x0 0x1>;
+ reg = <0x0 0x2ce 0x0 0x2000>,
+ <0x0 0x2ce2000 0x0 0x2000>,
+ <0x0 0x2ce4000 0x0 0xc00>,
+ <0x0 0x2ce4c00 0x0 0x400>;
+ reg-names = "regs", "palette", "gamma", "cursor";
clocks = <&platform_clk 0>, <&platform_clk 0>;
clock-names = "dcu", "pix";
big-endian;
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
index 3371635..6371e4d 100644
--- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
@@ -22,6 +22,31 @@
#include "fsl_dcu_drm_drv.h"
#include "fsl_dcu_drm_plane.h"
+static void fsl_crtc_gamma_set(struct drm_crtc *crtc, struct drm_color_lut
*lut,
+ uint32_t size)
+{
+ struct fsl_dcu_drm_device *fsl_dev = crtc->dev->dev_private;
+ unsigned int i;
+
+ if (crtc->state->gamma_lut->data) {
+ for (i = 0; i < size; i++) {
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_R + 4 * i,
+lut[i].red);
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_G + 4 * i,
+lut[i].green);
+ regmap_write(fsl_dev->regmap_gamma, FSL_GAMMA_B + 4 * i,
+lut[i].blue);
+ }
+
+ regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+ DCU_MODE_EN_GAMMA_MASK,
+ DCU_MODE_GAMMA_ENABLE);
+ } else {
+ regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
+ DCU_MODE_EN_GAMMA_MASK, 0);
+ }
+}
+
static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -37,6 +62,10 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc
*crtc,
drm_crtc_send_vblank_event(crtc, event);
spin_unlock_irq(&crtc->dev->event_lock);
}
+
+ if (crtc->state->color_mgmt_changed && crtc->state->gamma_lut)
+ fsl_crtc_gamma_set(crtc, (struct drm_color_lut *)
+ crtc->state->gamma_lut->data, 256);
}
static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
@@ -135,6 +164,7 @@ static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs =
{
.page_flip = drm_atomic_helper_page_flip,
.reset = drm_atomic_helper_crtc_reset,
.set_config = drm_atomic_helper_set_config,
+ .gamma_set = drm_atomic_helper_legacy_gamma_set,
};
int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
@@ -158,5 +188,8 @@ int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device
*fsl_dev)
drm_c
[Bug 97917] Enabling sisched gives Assertion `!NodePtr->isKnownSentinel()' failed
https://bugs.freedesktop.org/show_bug.cgi?id=97917 --- Comment #5 from Nicolai Hähnle --- I suspect sisched needs to be updated for recent changes in LLVM to the control flow lowering. Trying to ping Axel Davy... -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/83f97e9c/attachment.html>
[PATCH] drm: tilcdc: add a workaround for failed clk_set_rate()
On 09/27/16 18:29, Bartosz Golaszewski wrote:
> Some architectures don't use the common clock framework and don't
> implement all the clk interfaces for every clock. This is the case
> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
>
> Trying to set the clock rate for the LCDC clock results in -EINVAL
> being returned.
>
> As a workaround for that: if the call to clk_set_rate() fails, fall
> back to adjusting the clock divider instead. Proper divider value is
> calculated by dividing the current clock rate by the required pixel
> clock rate in HZ.
>
> This code is based on a hack initially developed internally for
> baylibre by Karl Beldan .
>
> Tested with a da850-lcdk with an LCD display connected over VGA.
>
Could you rebase the fix on top of latest drm-next[1] (or my latest pull
request tag[2])?
The conflict is so big that it is better the check that the fix still
works after rebasing.
Best regards,
Jyri
[1] git://people.freedesktop.org/~airlied/linux drm-next
[2] https://github.com/jsarha/linux tags/tilcdc-4.9-3.1
> Signed-off-by: Bartosz Golaszewski
> ---
> drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ---
> 1 file changed, 24 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> index 2087689..f2ff3b1 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> @@ -636,22 +636,40 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
> struct drm_device *dev = crtc->dev;
> struct tilcdc_drm_private *priv = dev->dev_private;
> unsigned long lcd_clk;
> - const unsigned clkdiv = 2; /* using a fixed divider of 2 */
> + unsigned int clkdiv;
> int ret;
>
> pm_runtime_get_sync(dev->dev);
>
> tilcdc_crtc_disable(crtc);
>
> + clkdiv = 2; /* first try using a standard divider of 2 */
> +
> /* mode.clock is in KHz, set_rate wants parameter in Hz */
> ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
> + lcd_clk = clk_get_rate(priv->clk);
> if (ret < 0) {
> - dev_err(dev->dev, "failed to set display clock rate to: %d\n",
> - crtc->mode.clock);
> - goto out;
> - }
> + /*
> + * If we fail to set the clock rate (some architectures don't
> + * use the common clock framework yet and may not implement
> + * all the clk API calls for every clock), try the next best
> + * thing: adjusting the clock divider, unless clk_get_rate()
> + * failed as well.
> + */
> + dev_err(dev->dev,
> + "failed to set display clock rate to: %d\n",
> + crtc->mode.clock);
> + if (!lcd_clk) {
> + /* Nothing more we can do. Just bail out. */
> + dev_err(dev->dev,
> + "failed to read the display clock rate\n");
> + goto out;
> + }
>
> - lcd_clk = clk_get_rate(priv->clk);
> + dev_info(dev->dev,
> + "falling back to adjusting the clock divisor\n");
> + clkdiv = DIV_ROUND_CLOSEST(lcd_clk, (crtc->mode.clock * 1000));
> + }
>
> DBG("lcd_clk=%lu, mode clock=%d, div=%u",
> lcd_clk, crtc->mode.clock, clkdiv);
> @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
> tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
> LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
> LCDC_V2_CORE_CLK_EN);
> -
> if (tilcdc_crtc_is_on(crtc))
> tilcdc_crtc_enable(crtc);
>
>
[PATCH] drm: tilcdc: add a workaround for failed clk_set_rate()
Hi,
On 27/09/16 18:29, Bartosz Golaszewski wrote:
> Some architectures don't use the common clock framework and don't
> implement all the clk interfaces for every clock. This is the case
> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
>
> Trying to set the clock rate for the LCDC clock results in -EINVAL
> being returned.
>
> As a workaround for that: if the call to clk_set_rate() fails, fall
> back to adjusting the clock divider instead. Proper divider value is
> calculated by dividing the current clock rate by the required pixel
> clock rate in HZ.
>
> This code is based on a hack initially developed internally for
> baylibre by Karl Beldan .
>
> Tested with a da850-lcdk with an LCD display connected over VGA.
>
> Signed-off-by: Bartosz Golaszewski
> ---
> drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ---
> 1 file changed, 24 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> index 2087689..f2ff3b1 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> @@ -636,22 +636,40 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
> struct drm_device *dev = crtc->dev;
> struct tilcdc_drm_private *priv = dev->dev_private;
> unsigned long lcd_clk;
> - const unsigned clkdiv = 2; /* using a fixed divider of 2 */
> + unsigned int clkdiv;
> int ret;
>
> pm_runtime_get_sync(dev->dev);
>
> tilcdc_crtc_disable(crtc);
>
> + clkdiv = 2; /* first try using a standard divider of 2 */
> +
> /* mode.clock is in KHz, set_rate wants parameter in Hz */
> ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
> + lcd_clk = clk_get_rate(priv->clk);
> if (ret < 0) {
> - dev_err(dev->dev, "failed to set display clock rate to: %d\n",
> - crtc->mode.clock);
> - goto out;
> - }
> + /*
> + * If we fail to set the clock rate (some architectures don't
> + * use the common clock framework yet and may not implement
> + * all the clk API calls for every clock), try the next best
> + * thing: adjusting the clock divider, unless clk_get_rate()
> + * failed as well.
> + */
> + dev_err(dev->dev,
> + "failed to set display clock rate to: %d\n",
> + crtc->mode.clock);
This code path is not an error, is it? No reason to print anything here.
> + if (!lcd_clk) {
> + /* Nothing more we can do. Just bail out. */
> + dev_err(dev->dev,
> + "failed to read the display clock rate\n");
This is an error, but maybe the error message should say something else.
I mean, "failed to _read_ display clk rate", when the user tries to set
pixel clock, doesn't quite make sense =).
> + goto out;
> + }
>
> - lcd_clk = clk_get_rate(priv->clk);
> + dev_info(dev->dev,
> + "falling back to adjusting the clock divisor\n");
I don't see a reason for this print either. This is normal if the
platform doesn't support changing the lcdc's input clock.
> + clkdiv = DIV_ROUND_CLOSEST(lcd_clk, (crtc->mode.clock * 1000));
> + }
If the clock divider path easily creates pixel clocks that are quite far
from the requested ones (which I think it does), I think it would make
sense to have a print here if the final pixel clock is far enough from
the requested one. And that's a valid print for the current code path
too, as it's not clear whether lcdc's input clock can be set to an exact
value.
> DBG("lcd_clk=%lu, mode clock=%d, div=%u",
> lcd_clk, crtc->mode.clock, clkdiv);
> @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
> tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
> LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
> LCDC_V2_CORE_CLK_EN);
> -
Extra change here.
Tomi
-- next part --
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[Bug 173041] New: Nouveau random hangs in g84_gr_tlb_flush (NVIDIA GT240)
https://bugzilla.kernel.org/show_bug.cgi?id=173041 Bug ID: 173041 Summary: Nouveau random hangs in g84_gr_tlb_flush (NVIDIA GT240) Product: Drivers Version: 2.5 Kernel Version: 4.7.4 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: high Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri at kernel-bugs.osdl.org Reporter: nikolay.romanovich at yandex.com Regression: No Created attachment 239941 --> https://bugzilla.kernel.org/attachment.cgi?id=239941&action=edit Kernel log before hang System random hangs if nouveau driver in use lspci: 02:00.0 VGA compatible controller: NVIDIA Corporation GT215 [GeForce GT 240] (rev a2) (prog-if 00 [VGA controller]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- Kernel driver in use: nvidia Kernel modules: nouveau, nvidia -- You are receiving this mail because: You are watching the assignee of the bug.
[PATCH] drm: tilcdc: add a workaround for failed clk_set_rate()
+ Sekhar
2016-09-28 13:19 GMT+02:00 Tomi Valkeinen :
> Hi,
>
> On 27/09/16 18:29, Bartosz Golaszewski wrote:
>> Some architectures don't use the common clock framework and don't
>> implement all the clk interfaces for every clock. This is the case
>> for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
>>
>> Trying to set the clock rate for the LCDC clock results in -EINVAL
>> being returned.
>>
>> As a workaround for that: if the call to clk_set_rate() fails, fall
>> back to adjusting the clock divider instead. Proper divider value is
>> calculated by dividing the current clock rate by the required pixel
>> clock rate in HZ.
>>
>> This code is based on a hack initially developed internally for
>> baylibre by Karl Beldan .
>>
>> Tested with a da850-lcdk with an LCD display connected over VGA.
>>
>> Signed-off-by: Bartosz Golaszewski
[snip]
>
> If the clock divider path easily creates pixel clocks that are quite far
> from the requested ones (which I think it does), I think it would make
> sense to have a print here if the final pixel clock is far enough from
> the requested one. And that's a valid print for the current code path
> too, as it's not clear whether lcdc's input clock can be set to an exact
> value.
>
>> DBG("lcd_clk=%lu, mode clock=%d, div=%u",
>> lcd_clk, crtc->mode.clock, clkdiv);
>> @@ -664,7 +682,6 @@ void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
>> tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
>> LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
>> LCDC_V2_CORE_CLK_EN);
>> -
Hi Tomi,
how far is far enough to emit a warning? On da850 the requested rate
is 22800 Hz, while the calculated divider is 6, which results in
the real rate of 22500 Hz. This is less than 1% difference -
should we take this value as reference?
I'll apply all other requested changes.
Best regards,
Bartosz Golaszewski
[PATCH] drm: tilcdc: add a workaround for failed clk_set_rate()
On 28/09/16 14:43, Bartosz Golaszewski wrote: > how far is far enough to emit a warning? On da850 the requested rate > is 22800 Hz, while the calculated divider is 6, which results in > the real rate of 22500 Hz. This is less than 1% difference - > should we take this value as reference? Good question, and I don't have a clear answer. But I think the point is just to inform the user that it's likely that his LCD won't work properly, and often LCDs are quite tolerant about the pclk. So diff less than 1% is just fine. Even 5% sounds still fine to me, perhaps even 10%. I think we just have to try something out, and adjust it if people get the message too often. Tomi -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: OpenPGP digital signature URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/5377aea6/attachment-0001.sig>
[Bug 97852] Unreal Engine corrupted preview viewport
https://bugs.freedesktop.org/show_bug.cgi?id=97852 --- Comment #1 from Nicolai Hähnle --- Hi Markus, can you provide an apitrace that can reproduce the corruption? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/4c4e4355/attachment.html>
[Bug 97887] llvm segfault in janusvr -render vive
https://bugs.freedesktop.org/show_bug.cgi?id=97887 --- Comment #2 from Nicolai Hähnle --- I can reproduce this running plain JanusVR, and I'm going to investigate. Looks like there are actually two bugs - the one you originally reported, and another that prevents proper dumping of the affected shader. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/06291fca/attachment.html>
[PATCH v2] drm: tilcdc: add a workaround for failed clk_set_rate()
Some architectures don't use the common clock framework and don't
implement all the clk interfaces for every clock. This is the case
for da850-lcdk where clk_set_rate() only works for PLL0 and PLL1.
Trying to set the clock rate for the LCDC clock results in -EINVAL
being returned.
As a workaround for that: if the call to clk_set_rate() fails, fall
back to adjusting the clock divider instead. Proper divider value is
calculated by dividing the current clock rate by the required pixel
clock rate in HZ.
This code is based on a hack initially developed internally for
baylibre by Karl Beldan .
Tested with a da850-lcdk with an LCD display connected over VGA.
Signed-off-by: Bartosz Golaszewski
---
v1 -> v2:
- rebased on top of current drm-next
- removed unnecessary error messages
- removed an extra newline
- added a warning if the effective pixel clock rate differs much from
the requested rate
Retested with modetest -M tilcdc -s 26:800x600 at RG16 using some
additional work-in-progress changes on top of this patch.
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 50
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 52ebe8f..7346f300b 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -320,23 +320,63 @@ static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
return true;
}
+/*
+ * Calculate the percentage difference between the requested pixel clock rate
+ * and the effective rate resulting from calculating the clock divider value.
+ */
+static unsigned int tilcdc_pclk_diff(unsigned long rate,
+unsigned long real_rate)
+{
+ int r = rate / 100, rr = real_rate / 100;
+
+ return (unsigned int)(abs(((rr - r) * 100) / r));
+}
+
static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
- const unsigned clkdiv = 2; /* using a fixed divider of 2 */
+ unsigned long rate, real_rate;
+ unsigned int clkdiv;
int ret;
+ clkdiv = 2; /* first try using a standard divider of 2 */
+
/* mode.clock is in KHz, set_rate wants parameter in Hz */
ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
+ rate = clk_get_rate(priv->clk);
if (ret < 0) {
- dev_err(dev->dev, "failed to set display clock rate to: %d\n",
- crtc->mode.clock);
- return;
+ /*
+* If we fail to set the clock rate (some architectures don't
+* use the common clock framework yet and may not implement
+* all the clk API calls for every clock), try the next best
+* thing: adjusting the clock divider, unless clk_get_rate()
+* failed as well.
+*/
+ if (!rate) {
+ /* Nothing more we can do. Just bail out. */
+ dev_err(dev->dev,
+ "failed to set the pixel clock - unable to read
current lcdc clock rate\n");
+ return;
+ }
+
+ clkdiv = DIV_ROUND_CLOSEST(rate, (crtc->mode.clock * 1000));
+
+ /*
+* Emit a warning if the real clock rate resulting from the
+* calculated divider differs much from the requested rate.
+*
+* 5% is an arbitrary value - LCDs are usually quite tolerant
+* about pixel clock rates.
+*/
+ real_rate = clkdiv * crtc->mode.clock * 1000;
+
+ WARN_ONCE(tilcdc_pclk_diff(rate, real_rate) > 5,
+ "real pixel clock rate diverged from the requested
rate more than 5%%\n");
}
- tilcdc_crtc->lcd_fck_rate = clk_get_rate(priv->clk);
+ tilcdc_crtc->lcd_fck_rate = rate;
DBG("lcd_clk=%u, mode clock=%d, div=%u",
tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
--
2.7.4
[PATCH v2 00/10] drm/edid: Clean up display_info stuff
From: Ville Syrjälä Rebased the series (previous version [1]) mostly due to code shuffling. i915 specific bits still need to be eyeballed by someone. Series available here: git://github.com/vsyrjala/linux.git hdmi_sink_tmds_limit_4 [1] https://lists.freedesktop.org/archives/dri-devel/2016-August/114634.html Ville Syrjälä (10): drm/edid: Clear old audio latency values before parsing the new EDID drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new EDID drm/edid: Make max_tmds_clock kHz instead of MHz drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info drm/edid: Don't pass around drm_display_info needlessly drm/edid: Reduce the number of times we parse the CEA extension block drm/edid: Clear the old cea_rev when there's no CEA extension in the new EDID drm/edid: Move dvi_dual/max_tmds_clock parsing out from drm_edid_to_eld() drm/i915: Replace a bunch of connector->base.display_info with a local variable drm/i915: Account for sink max TMDS clock when checking the port clock drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 +- drivers/gpu/drm/drm_edid.c | 248 + drivers/gpu/drm/i915/intel_display.c | 14 +- drivers/gpu/drm/i915/intel_hdmi.c | 9 +- drivers/gpu/drm/radeon/radeon_connectors.c | 4 +- include/drm/drm_connector.h| 15 +- 6 files changed, 159 insertions(+), 135 deletions(-) -- 2.7.4
[PATCH 01/10] drm/edid: Clear old audio latency values before parsing the new EDID
From: Ville Syrjälä
Clear out stale audio latency information (potentially from a previous
EDID) before constructing the ELD from the EDID.
Signed-off-by: Ville Syrjälä
Acked-by: Christian König
---
drivers/gpu/drm/drm_edid.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 50541324a4ab..065896add86e 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3358,6 +3358,13 @@ void drm_edid_to_eld(struct drm_connector *connector,
struct edid *edid)
memset(eld, 0, sizeof(connector->eld));
+ connector->latency_present[0] = false;
+ connector->latency_present[1] = false;
+ connector->video_latency[0] = 0;
+ connector->audio_latency[0] = 0;
+ connector->video_latency[1] = 0;
+ connector->audio_latency[1] = 0;
+
cea = drm_find_cea_extension(edid);
if (!cea) {
DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
--
2.7.4
[PATCH v2 03/10] drm/edid: Make max_tmds_clock kHz instead of MHz
From: Ville Syrjälä
We generally store clocks in kHz, so let's do that for the
HDMI max TMDS clock value as well. Less surpising.
v2: Deal with superfluous code shuffling
Cc: Alex Deucher
Cc: "Christian König"
Signed-off-by: Ville Syrjälä
Reviewed-by: Christian König (v1)
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +-
drivers/gpu/drm/drm_edid.c | 2 +-
drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
include/drm/drm_connector.h| 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 319a5e1d9389..ef63ab944fec 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -173,7 +173,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector
*connector)
mode_clock = amdgpu_connector->pixelclock_for_modeset;
/* Maximum allowable input clock in kHz */
- max_tmds_clock = connector->max_tmds_clock * 1000;
+ max_tmds_clock = connector->max_tmds_clock;
DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds
input clock %d kHz.\n",
connector->name, mode_clock, max_tmds_clock);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index d0166cc990cb..b144d5ee66ea 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3262,7 +3262,7 @@ parse_hdmi_vsdb(struct drm_connector *connector, const u8
*db)
connector->dvi_dual = db[6] & 1;
}
if (len >= 7)
- connector->max_tmds_clock = db[7] * 5;
+ connector->max_tmds_clock = db[7] * 5000;
if (len >= 8) {
connector->latency_present[0] = db[8] >> 7;
connector->latency_present[1] = (db[8] >> 6) & 1;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index b79f3b002471..db5488732e31 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -203,7 +203,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector)
mode_clock = radeon_connector->pixelclock_for_modeset;
/* Maximum allowable input clock in kHz */
- max_tmds_clock = connector->max_tmds_clock * 1000;
+ max_tmds_clock = connector->max_tmds_clock;
DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds
input clock %d kHz.\n",
connector->name, mode_clock,
max_tmds_clock);
diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
index 51a15deda161..5928cb74a06d 100644
--- a/include/drm/drm_connector.h
+++ b/include/drm/drm_connector.h
@@ -651,7 +651,7 @@ struct drm_connector {
/* EDID bits */
uint8_t eld[MAX_ELD_BYTES];
bool dvi_dual;
- int max_tmds_clock; /* in MHz */
+ int max_tmds_clock; /* in kHz */
bool latency_present[2];
int video_latency[2]; /* [0]: progressive, [1]: interlaced */
int audio_latency[2];
--
2.7.4
[PATCH 05/10] drm/edid: Don't pass around drm_display_info needlessly
From: Ville Syrjälä
We already pass the connector to drm_add_display_info() and
drm_assign_hdmi_deep_color_info(), so passing the
connector->display_info also is pointless.
Signed-off-by: Ville Syrjälä
Acked-by: Christian König
---
drivers/gpu/drm/drm_edid.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 81b9ef82af73..caa84a056779 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3738,9 +3738,9 @@ EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
* Return true if HDMI deep color supported, false if not or unknown.
*/
static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
-struct drm_display_info *info,
struct drm_connector *connector)
{
+ struct drm_display_info *info = &connector->display_info;
u8 *edid_ext, *hdmi;
int i;
int start_offset, end_offset;
@@ -3828,9 +3828,9 @@ static bool drm_assign_hdmi_deep_color_info(struct edid
*edid,
}
static void drm_add_display_info(struct edid *edid,
- struct drm_display_info *info,
struct drm_connector *connector)
{
+ struct drm_display_info *info = &connector->display_info;
u8 *edid_ext;
info->width_mm = edid->width_cm * 10;
@@ -3860,7 +3860,7 @@ static void drm_add_display_info(struct edid *edid,
}
/* HDMI deep color modes supported? Assign to info, if so */
- drm_assign_hdmi_deep_color_info(edid, info, connector);
+ drm_assign_hdmi_deep_color_info(edid, connector);
/*
* Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
@@ -4096,7 +4096,7 @@ int drm_add_edid_modes(struct drm_connector *connector,
struct edid *edid)
if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
edid_fixup_preferred(connector, quirks);
- drm_add_display_info(edid, &connector->display_info, connector);
+ drm_add_display_info(edid, connector);
if (quirks & EDID_QUIRK_FORCE_6BPC)
connector->display_info.bpc = 6;
--
2.7.4
[PATCH 02/10] drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new EDID
From: Ville Syrjälä
Clear out old max_tmds_clock and dvi_dual information (possibly from a
previous EDID) before parsing the current EDID. Tne current EDID might
not even have these in its HDMI VSDB, which would mean that we'd leave
the old stale values in place.
Signed-off-by: Ville Syrjälä
Acked-by: Christian König
---
drivers/gpu/drm/drm_edid.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 065896add86e..d0166cc990cb 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3365,6 +3365,9 @@ void drm_edid_to_eld(struct drm_connector *connector,
struct edid *edid)
connector->video_latency[1] = 0;
connector->audio_latency[1] = 0;
+ connector->max_tmds_clock = 0;
+ connector->dvi_dual = false;
+
cea = drm_find_cea_extension(edid);
if (!cea) {
DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
--
2.7.4
[PATCH v2 04/10] drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info
From: Ville Syrjälä
We have the drm_display_info for storing information about the sink, so
let's move dvi_dual and max_tmds_clock in there.
v2: Deal with superfluous code shuffling
Document dvi_dual and max_tmds_clock too
Cc: Alex Deucher
Cc: "Christian König"
Signed-off-by: Ville Syrjälä
Reviewed-by: Christian König (v1)
---
drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 ++--
drivers/gpu/drm/drm_edid.c | 14 --
drivers/gpu/drm/radeon/radeon_connectors.c | 4 ++--
include/drm/drm_connector.h| 15 +++
4 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index ef63ab944fec..31dbf6c5445e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -168,12 +168,12 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector
*connector)
}
/* Any defined maximum tmds clock limit we must not exceed? */
- if (connector->max_tmds_clock > 0) {
+ if (connector->display_info.max_tmds_clock > 0) {
/* mode_clock is clock in kHz for mode to be modeset on
this connector */
mode_clock = amdgpu_connector->pixelclock_for_modeset;
/* Maximum allowable input clock in kHz */
- max_tmds_clock = connector->max_tmds_clock;
+ max_tmds_clock = connector->display_info.max_tmds_clock;
DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds
input clock %d kHz.\n",
connector->name, mode_clock, max_tmds_clock);
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index b144d5ee66ea..81b9ef82af73 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3255,14 +3255,15 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
static void
parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
{
+ struct drm_display_info *info = &connector->display_info;
u8 len = cea_db_payload_len(db);
if (len >= 6) {
connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
- connector->dvi_dual = db[6] & 1;
+ info->dvi_dual = db[6] & 1;
}
if (len >= 7)
- connector->max_tmds_clock = db[7] * 5000;
+ info->max_tmds_clock = db[7] * 5000;
if (len >= 8) {
connector->latency_present[0] = db[8] >> 7;
connector->latency_present[1] = (db[8] >> 6) & 1;
@@ -3281,8 +3282,8 @@ parse_hdmi_vsdb(struct drm_connector *connector, const u8
*db)
"latency present %d %d, "
"video latency %d %d, "
"audio latency %d %d\n",
- connector->dvi_dual,
- connector->max_tmds_clock,
+ info->dvi_dual,
+ info->max_tmds_clock,
(int) connector->latency_present[0],
(int) connector->latency_present[1],
connector->video_latency[0],
@@ -3349,6 +3350,7 @@ EXPORT_SYMBOL(drm_edid_get_monitor_name);
*/
void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
{
+ struct drm_display_info *info = &connector->display_info;
uint8_t *eld = connector->eld;
u8 *cea;
u8 *db;
@@ -3365,8 +3367,8 @@ void drm_edid_to_eld(struct drm_connector *connector,
struct edid *edid)
connector->video_latency[1] = 0;
connector->audio_latency[1] = 0;
- connector->max_tmds_clock = 0;
- connector->dvi_dual = false;
+ info->max_tmds_clock = 0;
+ info->dvi_dual = false;
cea = drm_find_cea_extension(edid);
if (!cea) {
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index db5488732e31..50e96d2c593d 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -198,12 +198,12 @@ int radeon_get_monitor_bpc(struct drm_connector
*connector)
}
/* Any defined maximum tmds clock limit we must not exceed? */
- if (connector->max_tmds_clock > 0) {
+ if (connector->display_info.max_tmds_clock > 0) {
/* mode_clock is clock in kHz for mode to be modeset on
this connector */
mode_clock = radeon_connector->pixelclock_for_modeset;
/* Maximum allowable input clock in kHz */
- max_tmds_clock = connector->max_tmds_clock;
+ max_tmds_clock = connector->display_info.max_tmds_clock;
DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds
input clock %d kHz.\n",
[PATCH 07/10] drm/edid: Clear the old cea_rev when there's no CEA extension in the new EDID
From: Ville Syrjälä It's not a good idea to leave stale cea_rev in the drm_display_info. The current EDID might not even have a CEA ext block in which case we'd end up leaving the stale value in place. Signed-off-by: Ville Syrjälä Acked-by: Christian König --- drivers/gpu/drm/drm_edid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index ef8ae691f7aa..48e529df344e 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3844,6 +3844,7 @@ static void drm_add_display_info(struct drm_connector *connector, /* driver figures it out in this case */ info->bpc = 0; info->color_formats = 0; + info->cea_rev = 0; if (edid->revision < 3) return; -- 2.7.4
[PATCH 08/10] drm/edid: Move dvi_dual/max_tmds_clock parsing out from drm_edid_to_eld()
From: Ville Syrjälä
drm_edid_to_eld() is just mean to cook up the ELD for the audio driver,
so having it parse non-audio related stuff seems just wrong, and
potentially could lead to that information not being even filled out
if the function doesn't even get called. Let's move that stuff to the
place where we parse the color formats and whatnot from the CEA ext
block.
Signed-off-by: Ville Syrjälä
Acked-by: Christian König
---
drivers/gpu/drm/drm_edid.c | 64 +-
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 48e529df344e..ec77bd3e1f08 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3253,17 +3253,12 @@ static void fixup_detailed_cea_mode_clock(struct
drm_display_mode *mode)
}
static void
-parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
+drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
{
- struct drm_display_info *info = &connector->display_info;
u8 len = cea_db_payload_len(db);
- if (len >= 6) {
+ if (len >= 6)
connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
- info->dvi_dual = db[6] & 1;
- }
- if (len >= 7)
- info->max_tmds_clock = db[7] * 5000;
if (len >= 8) {
connector->latency_present[0] = db[8] >> 7;
connector->latency_present[1] = (db[8] >> 6) & 1;
@@ -3277,19 +3272,15 @@ parse_hdmi_vsdb(struct drm_connector *connector, const
u8 *db)
if (len >= 12)
connector->audio_latency[1] = db[12];
- DRM_DEBUG_KMS("HDMI: DVI dual %d, "
- "max TMDS clock %d, "
- "latency present %d %d, "
- "video latency %d %d, "
- "audio latency %d %d\n",
- info->dvi_dual,
- info->max_tmds_clock,
- (int) connector->latency_present[0],
- (int) connector->latency_present[1],
- connector->video_latency[0],
- connector->video_latency[1],
- connector->audio_latency[0],
- connector->audio_latency[1]);
+ DRM_DEBUG_KMS("HDMI: latency present %d %d, "
+ "video latency %d %d, "
+ "audio latency %d %d\n",
+ connector->latency_present[0],
+ connector->latency_present[1],
+ connector->video_latency[0],
+ connector->video_latency[1],
+ connector->audio_latency[0],
+ connector->audio_latency[1]);
}
static void
@@ -3350,7 +3341,6 @@ EXPORT_SYMBOL(drm_edid_get_monitor_name);
*/
void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
{
- struct drm_display_info *info = &connector->display_info;
uint8_t *eld = connector->eld;
u8 *cea;
u8 *db;
@@ -3367,9 +3357,6 @@ void drm_edid_to_eld(struct drm_connector *connector,
struct edid *edid)
connector->video_latency[1] = 0;
connector->audio_latency[1] = 0;
- info->max_tmds_clock = 0;
- info->dvi_dual = false;
-
cea = drm_find_cea_extension(edid);
if (!cea) {
DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
@@ -3419,7 +3406,7 @@ void drm_edid_to_eld(struct drm_connector *connector,
struct edid *edid)
case VENDOR_BLOCK:
/* HDMI Vendor-Specific Data Block */
if (cea_db_is_hdmi_vsdb(db))
- parse_hdmi_vsdb(connector, db);
+ drm_parse_hdmi_vsdb_audio(connector,
db);
break;
default:
break;
@@ -3800,6 +3787,25 @@ static void drm_parse_hdmi_deep_color_info(struct
drm_connector *connector,
}
}
+static void
+drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
+{
+ struct drm_display_info *info = &connector->display_info;
+ u8 len = cea_db_payload_len(db);
+
+ if (len >= 6)
+ info->dvi_dual = db[6] & 1;
+ if (len >= 7)
+ info->max_tmds_clock = db[7] * 5000;
+
+ DRM_DEBUG_KMS("HDMI: DVI dual %d, "
+ "max TMDS clock %d kHz\n",
+ info->dvi_dual,
+ info->max_tmds_clock);
+
+ drm_parse_hdmi_deep_color_info(connector, db);
+}
+
static void drm_parse_cea_ext(struct drm_connector *connector,
struct edid *edid)
{
@@ -3826,10 +3832,8 @@ static void drm_parse_cea_ext(struct drm_connector
*connector,
for_each_cea_db(edid_ext, i, start, end) {
const u8 *db = &edid_ext[i];
- if (!cea_db_is_hdmi_vsdb(db))
-
[PATCH 10/10] drm/i915: Account for sink max TMDS clock when checking the port clock
From: Ville Syrjälä
It's perfectly legal for the sink to support 12bpc only for
some lower resolution modes, while the higher resolution modes
can only be used with 8bpc. So let's take the sink's max TMDS clock
into account before we go and decide that a particular mode can
be used with 12bpc.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_hdmi.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 8d49800064df..8d46f5836746 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1220,10 +1220,17 @@ static int hdmi_port_clock_limit(struct intel_hdmi
*hdmi,
int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
if (respect_downstream_limits) {
+ struct intel_connector *connector = hdmi->attached_connector;
+ const struct drm_display_info *info =
&connector->base.display_info;
+
if (hdmi->dp_dual_mode.max_tmds_clock)
max_tmds_clock = min(max_tmds_clock,
hdmi->dp_dual_mode.max_tmds_clock);
- if (!hdmi->has_hdmi_sink)
+
+ if (info->max_tmds_clock)
+ max_tmds_clock = min(max_tmds_clock,
+info->max_tmds_clock);
+ else if (!hdmi->has_hdmi_sink)
max_tmds_clock = min(max_tmds_clock, 165000);
}
--
2.7.4
[PATCH 06/10] drm/edid: Reduce the number of times we parse the CEA extension block
From: Ville Syrjälä
Instead of parsing parts of the CEA extension block in two places
to determine supported color formats and whatnot, let's just
consolidate it to one function. This also makes it possible to neatly
flatten drm_assign_hdmi_deep_color_info().
Signed-off-by: Ville Syrjälä
Acked-by: Christian König
---
drivers/gpu/drm/drm_edid.c | 185 +
1 file changed, 88 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index caa84a056779..ef8ae691f7aa 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -3733,105 +3733,110 @@ bool drm_rgb_quant_range_selectable(struct edid *edid)
}
EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
-/*
- * Parse the CEA extension according to CEA-861-B.
- * Return true if HDMI deep color supported, false if not or unknown.
- */
-static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
-struct drm_connector *connector)
+static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
+ const u8 *hdmi)
{
struct drm_display_info *info = &connector->display_info;
- u8 *edid_ext, *hdmi;
- int i;
- int start_offset, end_offset;
unsigned int dc_bpc = 0;
- edid_ext = drm_find_cea_extension(edid);
- if (!edid_ext)
- return false;
+ /* HDMI supports at least 8 bpc */
+ info->bpc = 8;
- if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
- return false;
+ if (cea_db_payload_len(hdmi) < 6)
+ return;
+
+ if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
+ dc_bpc = 10;
+ info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
+ DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
+ connector->name);
+ }
+
+ if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
+ dc_bpc = 12;
+ info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
+ DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
+ connector->name);
+ }
+
+ if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
+ dc_bpc = 16;
+ info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
+ DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
+ connector->name);
+ }
+
+ if (dc_bpc == 0) {
+ DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
+ connector->name);
+ return;
+ }
+
+ DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
+ connector->name, dc_bpc);
+ info->bpc = dc_bpc;
/*
-* Because HDMI identifier is in Vendor Specific Block,
-* search it from all data blocks of CEA extension.
+* Deep color support mandates RGB444 support for all video
+* modes and forbids YCRCB422 support for all video modes per
+* HDMI 1.3 spec.
*/
- for_each_cea_db(edid_ext, i, start_offset, end_offset) {
- if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
- /* HDMI supports at least 8 bpc */
- info->bpc = 8;
-
- hdmi = &edid_ext[i];
- if (cea_db_payload_len(hdmi) < 6)
- return false;
-
- if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
- dc_bpc = 10;
- info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
- DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
- connector->name);
- }
+ info->color_formats = DRM_COLOR_FORMAT_RGB444;
- if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
- dc_bpc = 12;
- info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
- DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
- connector->name);
- }
+ /* YCRCB444 is optional according to spec. */
+ if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
+ info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
+ DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
+ connector->name);
+ }
- if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
- dc_bpc = 16;
- info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
- DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
- connector->name);
- }
+ /*
+* Spec says that if any deep color mode is supported a
[PATCH 09/10] drm/i915: Replace a bunch of connector->base.display_info with a local variable
From: Ville Syrjälä
Reduce the eyesore with a local variable.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8e464e089794..34ca03e621ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12657,22 +12657,22 @@ static void
connected_sink_compute_bpp(struct intel_connector *connector,
struct intel_crtc_state *pipe_config)
{
+ const struct drm_display_info *info = &connector->base.display_info;
int bpp = pipe_config->pipe_bpp;
DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
- connector->base.base.id,
- connector->base.name);
+ connector->base.base.id,
+ connector->base.name);
/* Don't use an invalid EDID bpc value */
- if (connector->base.display_info.bpc &&
- connector->base.display_info.bpc * 3 < bpp) {
+ if (info->bpc != 0 && info->bpc * 3 < bpp) {
DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported
max of %d\n",
- bpp, connector->base.display_info.bpc*3);
- pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
+ bpp, info->bpc * 3);
+ pipe_config->pipe_bpp = info->bpc * 3;
}
/* Clamp bpp to 8 on screens without EDID 1.4 */
- if (connector->base.display_info.bpc == 0 && bpp > 24) {
+ if (info->bpc == 0 && bpp > 24) {
DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit
of 24\n",
bpp);
pipe_config->pipe_bpp = 24;
--
2.7.4
[PATCH 1/2] drm/fb_cma_helper: Add drm_fb_cma_setup_fence() helper
Hi Marek,
Am Montag, den 26.09.2016, 15:01 +0200 schrieb Marek Vasut:
> Add new drm_fb_cma_setup_fence() helper function extracted from the
> imx-drm driver. This function checks if the plane has DMABUF attached
> to it and if so, sets up the fence on which the atomic helper can wait.
>
> Signed-off-by: Marek Vasut
> Cc: Daniel Vetter
> Cc: Lucas Stach
> ---
> drivers/gpu/drm/drm_fb_cma_helper.c | 26 ++
> include/drm/drm_fb_cma_helper.h | 3 +++
> 2 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
> b/drivers/gpu/drm/drm_fb_cma_helper.c
> index 1fd6eac..2441707 100644
> --- a/drivers/gpu/drm/drm_fb_cma_helper.c
> +++ b/drivers/gpu/drm/drm_fb_cma_helper.c
> @@ -23,8 +23,10 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> +#include
>
> #define DEFAULT_FBDEFIO_DELAY_MS 50
>
> @@ -265,6 +267,30 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct
> drm_framebuffer *fb,
> }
> EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
>
> +/**
> + * drm_fb_cma_setup_fence() - Set up the fence for atomic helper to wait on
I don't really like the naming of the helper. It's not setting up any
fence, it's either extracting it from the plane and/or attaching it to
the planestate, so I would have expected the name to include extract or
attach.
> + * @plane: Which plane
> + * @state: Plane state to check
s/check/attach fence to
> + *
> + * If the plane fb has an dma-buf attached, fish out the exclusive
> + * fence for the atomic helper to wait on.
> + */
> +void drm_fb_cma_setup_fence(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + struct dma_buf *dma_buf;
> +
> + if ((plane->state->fb == state->fb) || !state->fb)
> + return;
> +
> + dma_buf = drm_fb_cma_get_gem_obj(state->fb, 0)->base.dma_buf;
> + if (!dma_buf)
> + return;
> +
> + state->fence = reservation_object_get_excl_rcu(dma_buf->resv);
> +}
> +EXPORT_SYMBOL_GPL(drm_fb_cma_setup_fence);
> +
> #ifdef CONFIG_DEBUG_FS
> static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file
> *m)
> {
> diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
> index f313211..fc122d3 100644
> --- a/include/drm/drm_fb_cma_helper.h
> +++ b/include/drm/drm_fb_cma_helper.h
> @@ -41,6 +41,9 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device
> *dev,
> struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
> unsigned int plane);
>
> +void drm_fb_cma_setup_fence(struct drm_plane *plane,
> + struct drm_plane_state *state);
> +
> #ifdef CONFIG_DEBUG_FS
> struct seq_file;
>
[PATCH 2/2] drm/imx: Switch to drm_fb_cma_setup_fence() helper
Am Montag, den 26.09.2016, 15:01 +0200 schrieb Marek Vasut:
> Remove the common code from the driver and use the drm_fb_cma_setup_fence()
> helper instead. Moveover, call the helper from prepare_fb() plane hook .
>
> Signed-off-by: Marek Vasut
> Cc: Daniel Vetter
> Cc: Lucas Stach
One nit inline, otherwise looks good and is:
Tested-by: Lucas Stach
> ---
> drivers/gpu/drm/imx/imx-drm-core.c | 30 +-
> drivers/gpu/drm/imx/ipuv3-plane.c | 8
> 2 files changed, 9 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
> b/drivers/gpu/drm/imx/imx-drm-core.c
> index 98df09c..c7faa1f 100644
> --- a/drivers/gpu/drm/imx/imx-drm-core.c
> +++ b/drivers/gpu/drm/imx/imx-drm-core.c
> @@ -18,7 +18,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include
> #include
> @@ -151,38 +150,11 @@ static int imx_drm_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> -static int imx_drm_atomic_commit(struct drm_device *dev,
> - struct drm_atomic_state *state,
> - bool nonblock)
> -{
> - struct drm_plane_state *plane_state;
> - struct drm_plane *plane;
> - struct dma_buf *dma_buf;
> - int i;
> -
> - /*
> - * If the plane fb has an dma-buf attached, fish out the exclusive
> - * fence for the atomic helper to wait on.
> - */
> - for_each_plane_in_state(state, plane, plane_state, i) {
> - if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
> - dma_buf = drm_fb_cma_get_gem_obj(plane_state->fb,
> - 0)->base.dma_buf;
> - if (!dma_buf)
> - continue;
> - plane_state->fence =
> - reservation_object_get_excl_rcu(dma_buf->resv);
> - }
> - }
> -
> - return drm_atomic_helper_commit(dev, state, nonblock);
> -}
> -
> static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
> .fb_create = drm_fb_cma_create,
> .output_poll_changed = imx_drm_output_poll_changed,
> .atomic_check = imx_drm_atomic_check,
> - .atomic_commit = imx_drm_atomic_commit,
> + .atomic_commit = drm_atomic_helper_commit,
> };
>
> static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
> diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
> b/drivers/gpu/drm/imx/ipuv3-plane.c
> index ce22d0a..50615e3 100644
> --- a/drivers/gpu/drm/imx/ipuv3-plane.c
> +++ b/drivers/gpu/drm/imx/ipuv3-plane.c
> @@ -250,6 +250,13 @@ static const struct drm_plane_funcs ipu_plane_funcs = {
> .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> };
>
> +static int ipu_plane_prepare_fb(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + drm_fb_cma_setup_fence(plane, state);
Blank line here to match the style in this driver.
> + return 0;
> +}
> +
> static int ipu_plane_atomic_check(struct drm_plane *plane,
> struct drm_plane_state *state)
> {
> @@ -442,6 +449,7 @@ static void ipu_plane_atomic_update(struct drm_plane
> *plane,
> }
>
> static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
> + .prepare_fb = ipu_plane_prepare_fb,
> .atomic_check = ipu_plane_atomic_check,
> .atomic_disable = ipu_plane_atomic_disable,
> .atomic_update = ipu_plane_atomic_update,
[Bug 97909] X-Plane 10 crashes with SIGSEGV on radeonsi
https://bugs.freedesktop.org/show_bug.cgi?id=97909 --- Comment #3 from Nicolai Hähnle --- Hi Christian, that really shouldn't happen. Can you provide an apitrace that shows the problem? My guess is that the index buffer tracking gets into an odd state because of the previous BufferData-related errors, but I don't yet see where that would be exactly. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/1226e013/attachment.html>
[PATCH 0/6] drm/exynos: g2d: rework sleep and runtime PM
Dear Tobias,
On 2016-09-27 17:50, Tobias Jakobi wrote:
> Hello everyone,
>
> as discussed with Marek I have broken down my initial patch into smaller
> piecer.
>
> Anyway, this series fixes a regression introduced by commit
> b05984e21a7e000bf5074ace00d7a574944b2c16.
>
> With best wishes,
> Tobias
Patches looks really nice! However I didn't have time to test them on
the real
hardware.
You can add my:
Acked-by: Marek Szyprowski
> Tobias Jakobi (6):
>Revert "drm/exynos: g2d: fix system and runtime pm integration"
>drm/exynos: g2d: move PM management to runqueue worker
>drm/exynos: g2d: remove runqueue nodes in g2d_{close,remove}()
>drm/exynos: g2d: wait for engine to finish
>drm/exynos: g2d: use autosuspend mode for PM runtime
>drm/exynos: g2d: simplify g2d_free_runqueue_node()
>
> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 237
> +---
> 1 file changed, 188 insertions(+), 49 deletions(-)
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
[PATCH libdrm] modetest: Allow the user to specify the plane ID
From: Ville Syrjälä
Devices can have multiple planes, so allow the user to choose between
them.
Signed-off-by: Ville Syrjälä
---
tests/modetest/modetest.c | 28 ++--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index dedd28621ef8..c390d875e37b 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -704,6 +704,7 @@ struct pipe_arg {
};
struct plane_arg {
+ uint32_t plane_id; /* the id of plane to use */
uint32_t crtc_id; /* the id of CRTC to bind to */
bool has_position;
int32_t x, y;
@@ -958,7 +959,7 @@ static int set_plane(struct device *dev, struct plane_arg
*p)
{
drmModePlane *ovr;
uint32_t handles[4] = {0}, pitches[4] = {0}, offsets[4] = {0};
- uint32_t plane_id = 0;
+ uint32_t plane_id;
struct bo *plane_bo;
uint32_t plane_flags = 0;
int crtc_x, crtc_y, crtc_w, crtc_h;
@@ -982,16 +983,26 @@ static int set_plane(struct device *dev, struct plane_arg
*p)
return -1;
}
- for (i = 0; i < dev->resources->plane_res->count_planes && !plane_id;
i++) {
+ plane_id = p->plane_id;
+
+ for (i = 0; i < dev->resources->plane_res->count_planes; i++) {
ovr = dev->resources->planes[i].plane;
- if (!ovr || !format_support(ovr, p->fourcc))
+ if (!ovr)
+ continue;
+
+ if (plane_id && plane_id != ovr->plane_id)
+ continue;
+
+ if (!format_support(ovr, p->fourcc))
continue;
- if ((ovr->possible_crtcs & (1 << pipe)) && !ovr->crtc_id)
+ if ((ovr->possible_crtcs & (1 << pipe)) && !ovr->crtc_id) {
plane_id = ovr->plane_id;
+ break;
+ }
}
- if (!plane_id) {
+ if (i == dev->resources->plane_res->count_planes) {
fprintf(stderr, "no unused plane available for CRTC %u\n",
crtc->crtc->crtc_id);
return -1;
@@ -1359,6 +1370,11 @@ static int parse_plane(struct plane_arg *plane, const
char *p)
{
char *end;
+ plane->plane_id = strtoul(p, &end, 10);
+ if (*end != '@')
+ return -EINVAL;
+
+ p = end + 1;
plane->crtc_id = strtoul(p, &end, 10);
if (*end != ':')
return -EINVAL;
@@ -1430,7 +1446,7 @@ static void usage(char *name)
fprintf(stderr, "\t-p\tlist CRTCs and planes (pipes)\n");
fprintf(stderr, "\n Test options:\n\n");
- fprintf(stderr, "\t-P
:x[++][*][@]\tset a plane\n");
+ fprintf(stderr, "\t-P
@:x[++][*][@]\tset a plane\n");
fprintf(stderr, "\t-s
[,][@]:[-][@]\tset
a mode\n");
fprintf(stderr, "\t-C\ttest hw cursor\n");
fprintf(stderr, "\t-v\ttest vsynced page flipping\n");
--
2.7.4
[Bug 97961] radeon: Failed to allocate virtual address for buffer
https://bugs.freedesktop.org/show_bug.cgi?id=97961 Bug ID: 97961 Summary: radeon: Failed to allocate virtual address for buffer Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Gallium/radeonsi Assignee: dri-devel at lists.freedesktop.org Reporter: vedran at miletic.net QA Contact: dri-devel at lists.freedesktop.org On a Kabini system using kernel 4.8-rc8, Mesa and LLVM git, running GROMACS OpenCL example 1536 from [1] results in radeon: Failed to allocate virtual address for buffer: radeon:size : 4096 bytes radeon:alignment : 4096 bytes radeon:domains : 2 radeon:va: 0x0948b000 radeon: Failed to deallocate virtual address for buffer: radeon:size : 4096 bytes radeon:va: 0x948b000 radeon: Failed to allocate virtual address for buffer: radeon:size : 4096 bytes radeon:alignment : 4096 bytes radeon:domains : 2 radeon:va: 0x0948b000 radeon: Failed to deallocate virtual address for buffer: radeon:size : 4096 bytes radeon:va: 0x948b000 This is one of the larger examples, so it requires more memory than the previous ones. I will test the largest example (3072) soon, and I expect it to crash the same way. This is a regression. It will be very hard to bisect LLVM and kernel on this machine as it is really slow, but Mesa is likely bisectable. Let me know if it is worth it. [1] ftp://ftp.gromacs.org/pub/benchmarks/water_GMX50_bare.tar.gz -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/64f41177/attachment-0001.html>
[Bug 97961] radeon: Failed to allocate virtual address for buffer
https://bugs.freedesktop.org/show_bug.cgi?id=97961 Vedran MiletiÄ changed: What|Removed |Added Keywords||regression --- Comment #1 from Vedran MiletiÄ --- GROMACS 2016 runs vanilla on Mesa, but it requires LLVM 4.0, matching libclc, and the following patch for Mesa: [1] https://lists.freedesktop.org/archives/mesa-dev/2016-September/129305.html -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/04fde68f/attachment.html>
[PATCH 2/7] drm/doc: Polish for drm_plane.[hc]
On Wed, Sep 28, 2016 at 11:11:52AM +0300, Jani Nikula wrote:
> On Wed, 28 Sep 2016, Rafael Antognolli wrote:
> > Hi Daniel,
> >
> > On Wed, Sep 21, 2016 at 10:59:25AM +0200, Daniel Vetter wrote:
> >> diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
> >> index 1407715736a5..256219bfd07b 100644
> >> --- a/include/drm/drm_plane.h
> >> +++ b/include/drm/drm_plane.h
> >> @@ -319,10 +319,48 @@ struct drm_plane_funcs {
> >>void (*early_unregister)(struct drm_plane *plane);
> >> };
> >>
> >> +/**
> >> + * enum drm_plane_type - uapi plane type enumeration
> >> + *
> >> + * For historical reasons not all planes are made the same. This
> >> enumeration is
> >> + * used to tell the different types of planes apart to implement the
> >> different
> >> + * uapi semantics for them. For userspace which is universal plane aware
> >> and
> >> + * which is using that atomic IOCTL there's no difference between these
> >> planes
> >> + * (beyong what the driver and hardware can support of course).
> >> + *
> >> + * For compatibility with legacy userspace, only overlay planes are made
> >> + * available to userspace by default. Userspace clients may set the
> >> + * DRM_CLIENT_CAP_UNIVERSAL_PLANES client capability bit to indicate that
> >> they
> >> + * wish to receive a universal plane list containing all plane types. See
> >> also
> >> + * drm_for_each_legacy_plane().
> >> + */
> >> enum drm_plane_type {
> >> - DRM_PLANE_TYPE_OVERLAY,
> >> + /**
> >> + * @DRM_PLANE_TYPE_PRIMARY:
> >> + *
> >> + * Primary planes represent a "main" plane for a CRTC. Primary planes
> >> + * are the planes operated upon by CRTC modesetting and flipping
> >> + * operations described in the page_flip and set_config hooks in struct
> >> + * &drm_crtc_funcs.
> >> + */
> >>DRM_PLANE_TYPE_PRIMARY,
> >> +
> >> + /**
> >> + * @DRM_PLANE_TYPE_CURSOR:
> >> + *
> >> + * Cursor planes represent a "cursor" plane for a CRTC. Cursor planes
> >> + * are the planes operated upon by the DRM_IOCTL_MODE_CURSOR and
> >> + * DRM_IOCTL_MODE_CURSOR2 IOCTLs.
> >> + */
> >>DRM_PLANE_TYPE_CURSOR,
> >> +
> >> + /**
> >> + * @DRM_PLANE_TYPE_OVERLAY:
> >> + *
> >> + * Overlay planes represent all non-primary, non-cursor planes. Some
> >> + * drivers refer to these types of planes as "sprites" internally.
> >> + */
> >> + DRM_PLANE_TYPE_OVERLAY,
> >> };
> >
> > This is changing the order (and consequently the values) of these enums.
> > But it is not updated in libdrm. I noticed this is causing an issue when
> > playing with robclark's version of kmscube (branch atomic):
> >
> > https://github.com/robclark/kmscube/tree/atomic
> >
> > It looks like IGT also uses this macro from libdrm:
> >
> > $ git grep -n DRM_PLANE_TYPE_PRIMARY
> > lib/igt_kms.c:1398: case DRM_PLANE_TYPE_PRIMARY:
> > tests/kms_frontbuffer_tracking.c:2302: drm.plane_types[i] ==
> > DRM_PLANE_TYPE_PRIMARY)
> > tests/kms_frontbuffer_tracking.c:2602: drm.plane_types[i] ==
> > DRM_PLANE_TYPE_PRIMARY) {
> > tests/kms_frontbuffer_tracking.c:2741: drm.plane_types[i] ==
> > DRM_PLANE_TYPE_PRIMARY)
> >
> > Anyway, should we update it on libdrm, bring the order back to its
> > original values, or something else? Or am I missing something?
>
> You're absolutely right. But you're missing the fix has already landed
> in drm-misc tree:
>
> commit 226714dc7c6af6d0acee449eb2afce08d128edad
> Author: Daniel Vetter
> Date: Fri Sep 23 08:35:25 2016 +0200
>
> drm: Fix plane type uabi breakage
>
> BR,
> Jani.
Oh, I was sure I had checked drm-intel-nightly too, but I clearly
didn't. Sorry for the noise.
Regards,
Rafael
[PATCH] drm/vc4: Fix races when the CS reads from render targets.
With the introduction of bin/render pipelining, the previous job may
not be completed when we start binning the next one. If the previous
job wrote our VBO, IB, or CS textures, then the binning stage might
get stale or uninitialized results.
Fixes the major rendering failure in glmark2 -b terrain.
Signed-off-by: Eric Anholt
Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and
rendering jobs")
Cc: stable at vger.kernel.org
---
drivers/gpu/drm/vc4/vc4_drv.h | 19 ++-
drivers/gpu/drm/vc4/vc4_gem.c | 13 +
drivers/gpu/drm/vc4/vc4_render_cl.c | 21 +
drivers/gpu/drm/vc4/vc4_validate.c | 17 ++---
4 files changed, 62 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 428e24919ef1..f696b752886b 100644
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -122,9 +122,16 @@ to_vc4_dev(struct drm_device *dev)
struct vc4_bo {
struct drm_gem_cma_object base;
- /* seqno of the last job to render to this BO. */
+ /* seqno of the last job to render using this BO. */
uint64_t seqno;
+ /* seqno of the last job to use the RCL to write to this BO.
+*
+* Note that this doesn't include binner overflow memory
+* writes.
+*/
+ uint64_t write_seqno;
+
/* List entry for the BO's position in either
* vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
*/
@@ -216,6 +223,9 @@ struct vc4_exec_info {
/* Sequence number for this bin/render job. */
uint64_t seqno;
+ /* Latest write_seqno of any BO that binning depends on. */
+ uint64_t bin_dep_seqno;
+
/* Last current addresses the hardware was processing when the
* hangcheck timer checked on us.
*/
@@ -230,6 +240,13 @@ struct vc4_exec_info {
struct drm_gem_cma_object **bo;
uint32_t bo_count;
+ /* List of BOs that are being written by the RCL. Other than
+* the binner temporary storage, this is all the BOs written
+* by the job.
+*/
+ struct drm_gem_cma_object *rcl_write_bo[4];
+ uint32_t rcl_write_bo_count;
+
/* Pointers for our position in vc4->job_list */
struct list_head head;
diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
index b262c5c26f10..ae1609e739ef 100644
--- a/drivers/gpu/drm/vc4/vc4_gem.c
+++ b/drivers/gpu/drm/vc4/vc4_gem.c
@@ -471,6 +471,11 @@ vc4_update_bo_seqnos(struct vc4_exec_info *exec, uint64_t
seqno)
list_for_each_entry(bo, &exec->unref_list, unref_head) {
bo->seqno = seqno;
}
+
+ for (i = 0; i < exec->rcl_write_bo_count; i++) {
+ bo = to_vc4_bo(&exec->rcl_write_bo[i]->base);
+ bo->write_seqno = seqno;
+ }
}
/* Queues a struct vc4_exec_info for execution. If no job is
@@ -673,6 +678,14 @@ vc4_get_bcl(struct drm_device *dev, struct vc4_exec_info
*exec)
goto fail;
ret = vc4_validate_shader_recs(dev, exec);
+ if (ret)
+ goto fail;
+
+ /* Block waiting on any previous rendering into the CS's VBO,
+* IB, or textures, so that pixels are actually written by the
+* time we try to read them.
+*/
+ ret = vc4_wait_for_seqno(dev, exec->bin_dep_seqno, ~0ull, true);
fail:
drm_free_large(temp);
diff --git a/drivers/gpu/drm/vc4/vc4_render_cl.c
b/drivers/gpu/drm/vc4/vc4_render_cl.c
index 0f12418725e5..08886a309757 100644
--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
@@ -45,6 +45,8 @@ struct vc4_rcl_setup {
struct drm_gem_cma_object *rcl;
u32 next_offset;
+
+ u32 next_write_bo_index;
};
static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)
@@ -407,6 +409,8 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info
*exec,
if (!*obj)
return -EINVAL;
+ exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj;
+
if (surf->offset & 0xf) {
DRM_ERROR("MSAA write must be 16b aligned.\n");
return -EINVAL;
@@ -417,7 +421,8 @@ static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info
*exec,
static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
struct drm_gem_cma_object **obj,
-struct drm_vc4_submit_rcl_surface *surf)
+struct drm_vc4_submit_rcl_surface *surf,
+bool is_write)
{
uint8_t tiling = VC4_GET_FIELD(surf->bits,
VC4_LOADSTORE_TILE_BUFFER_TILING);
@@ -440,6 +445,9 @@ static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
if (!*obj)
return -EINVAL;
+ if (is_write)
+ exec->rcl_write_bo[exec->rcl_write_bo_cou
[Bug 97471] kworker consumes 100% of a cpu core when screen sleeps with amdgpu kernel driver.
https://bugs.freedesktop.org/show_bug.cgi?id=97471 --- Comment #9 from Jan Vesely --- (In reply to Alex Deucher from comment #8) > Created attachment 126818 [details] [review] > possible fix > > Does this patch help? modified version of the patch helps on my setup. (patch modified to apply on top of ROCK kernel) -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/87addfba/attachment.html>
[PATCH v3] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Inki Dae wrote:
> 2016-09-28 18:06 GMT+09:00 Tobias Jakobi :
>> Hello Inki,
>>
>>
>> Inki Dae wrote:
>>>
>>>
>>> 2016ë
09ì 28ì¼ 09:03ì Tobias Jakobi ì´(ê°) ì´ ê¸:
Hey Inki,
Inki Dae wrote:
>
>
> 2016ë
09ì 28ì¼ 01:52ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Hello Andrzej,
>>
>>
>> Andrzej Hajda wrote:
>>> On 27.09.2016 13:22, Tobias Jakobi wrote:
Hello Inki,
Inki Dae wrote:
> 2016ë
09ì 26ì¼ 20:36ì Tobias Jakobi ì´(ê°) ì´ ê¸:
>> Only manipulate the MXR_CFG and MXR_LAYER_CFG registers once
>> in mixer_cfg_layer().
>> Trigger this via atomic flush.
>>
>> Changes in v2:
>> - issue mixer_cfg_layer() in mixer_disable()
>> - rename fields as suggested by Andrzej
>> - added docu to mixer context struct
>> - simplify mixer_win_reset() as well
>>
>> Changes in v3:
>> - simplify some conditions as suggested by Inki
>> - add docu to mixer_cfg_layer()
>> - fold switch statements into a single one
>>
>> Signed-off-by: Tobias Jakobi
>> ---
>> drivers/gpu/drm/exynos/exynos_mixer.c | 135
>> ++
>> drivers/gpu/drm/exynos/regs-mixer.h | 2 +
>> 2 files changed, 92 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
>> b/drivers/gpu/drm/exynos/exynos_mixer.c
>> index 1e78d57..4f06f4d 100644
>> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
>> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
>> @@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
>>DRM_FORMAT_NV21,
>> };
>>
>> +/*
>> + * Mixer context structure.
>> + *
>> + * @crtc: The HDMI CRTC attached to the mixer.
>> + * @planes: Array of plane objects for each of the mixer windows.
>> + * @active_windows: Cache of the mixer's hardware state.
>> + * Tracks which mixer windows are active/inactive.
>> + * @pipe: The CRTC index.
>> + * @flags: Bitfield build from the mixer_flag_bits enumerator.
>> + * @mixer_resources: A struct containing registers, clocks, etc.
>> + * @mxr_ver: The hardware revision/version of the mixer.
>> + */
>> struct mixer_context {
>>struct platform_device *pdev;
>>struct device *dev;
>>struct drm_device *drm_dev;
>>struct exynos_drm_crtc *crtc;
>>struct exynos_drm_plane planes[MIXER_WIN_NR];
>> + unsigned long active_windows;
>>int pipe;
>>unsigned long flags;
>>
>> @@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct
>> mixer_context *ctx, unsigned int height)
>>mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
>> }
>>
>> -static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int
>> win,
>> - unsigned int priority, bool enable)
>> +/**
>> + * mixer_cfg_layer - apply layer configuration to hardware
>> + * @ctx: mixer context
>> + *
>> + * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
>> + * using the 'active_windows' field of the the mixer content, and
>> + * the pixel format of the framebuffers associated with the enabled
>> + * windows.
>> + *
>> + * Has to be called under mixer lock.
>> + */
>> +static void mixer_cfg_layer(struct mixer_context *ctx)
>> {
>>struct mixer_resources *res = &ctx->mixer_res;
>> - u32 val = enable ? ~0 : 0;
>> -
>> - switch (win) {
>> - case 0:
>> - mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP0_ENABLE);
>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>> - MXR_LAYER_CFG_GRP0_VAL(priority),
>> - MXR_LAYER_CFG_GRP0_MASK);
>> - break;
>> - case 1:
>> - mixer_reg_writemask(res, MXR_CFG, val,
>> MXR_CFG_GRP1_ENABLE);
>> - mixer_reg_writemask(res, MXR_LAYER_CFG,
>> - MXR_LAYER_CFG_GRP1_VAL(priority),
>> - MXR_LAYER_CFG_GRP1_MASK);
>> + unsigned int win;
>>
>> - break;
>> - case VP_DEFAULT_WIN:
>> - if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
>> - vp_reg_writemask(res, VP_ENA
[Bug 94900] HD6950 GPU lockup loop with various steam games (octodad[always], saints row 4[always], dead island[always], grid autosport[sometimes])
https://bugs.freedesktop.org/show_bug.cgi?id=94900 Heiko changed: What|Removed |Added Attachment #125271|0 |1 is obsolete|| --- Comment #28 from Heiko --- Created attachment 126832 --> https://bugs.freedesktop.org/attachment.cgi?id=126832&action=edit Possible fix for the lockups The more I look at the sb code the more I dislike it :/ Anyhow, looks like the GCM pass is b0rked and doesn't like unused ops at all. The problem with that octodad trace is that with a pass through fold_assoc() an ADD_INT op becomes unused, but isn't removed prior to GCM. GCM then moves it up to the front of the shader (because there are no users), where the op's src values aren't defined (in that particular case the loop counter variable). GCM also moves ops up, if the usage count isn't fulfilled yet. Well that's when things get really broken, since it seems to move the loop counter -- or at least the initializer -- to fulfill the usage count. And well, then the GPU finally locks up on the shader (or if mesa is compiled in debug mode, sb shows unset registers), probably due to endlessly looping. I tried to fix GCM, but everytime I thought I've did the right thing, I got either unscheduled ops or wrong levels for the basic blocks. Also, the DONT_HOIST stuff doesn't really seem to work that well either. So I decided to fix the input feeded into the GCM pass, by iteratively removing all unused ops in dce_cleanup. This could also be reducing amount of instructions, that weren't actually removed before. Also optimized valtable's use_count(), which gets called 1500+ times for the octodad trace and did iterate over the whole use_info list every time... The (untidied) patch fixes octodad for me. Would be nice, if someone could test the other problematic games (be sure to test with a debug build, to get an exception rather than a lockup). If it works there as well, I'd clean things up. @Marek, what's the best/usual way to test for performance/instruction count in mesa changes. I noticed those 'helped'/'hurt'/'+-%' infos and some runtime numbers in commit messages, but I don't know how they are produced :/ -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/986d2aa7/attachment.html>
[Bug 94900] HD6950 GPU lockup loop with various steam games (octodad[always], saints row 4[always], dead island[always], grid autosport[sometimes])
https://bugs.freedesktop.org/show_bug.cgi?id=94900 --- Comment #29 from Marek Olšák --- (In reply to Heiko from comment #28) > @Marek, what's the best/usual way to test for performance/instruction count > in mesa changes. I noticed those 'helped'/'hurt'/'+-%' infos and some > runtime numbers in commit messages, but I don't know how they are produced :/ There is no way to get stats for r600g easily. Intel and radeonsi developers use their private shader-db repositories and generate their own stats. Intel have "helped/hurt +-%" stats, while we have much more detailed stats for radeonsi. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/4b003535/attachment-0001.html>
[PATCH v2 00/10] drm/edid: Clean up display_info stuff
On Wed, Sep 28, 2016 at 9:51 AM, wrote: > From: Ville Syrjälä > > Rebased the series (previous version [1]) mostly due to code > shuffling. i915 specific bits still need to be eyeballed by someone. > > Series available here: > git://github.com/vsyrjala/linux.git hdmi_sink_tmds_limit_4 > > [1] https://lists.freedesktop.org/archives/dri-devel/2016-August/114634.html Patches 1-8 are: Reviewed-by: Alex Deucher > > Ville Syrjälä (10): > drm/edid: Clear old audio latency values before parsing the new EDID > drm/edid: Clear old dvi_dual/max_tmds_clock before parsing the new > EDID > drm/edid: Make max_tmds_clock kHz instead of MHz > drm/edid: Move dvi_dual/max_tmds_clock to drm_display_info > drm/edid: Don't pass around drm_display_info needlessly > drm/edid: Reduce the number of times we parse the CEA extension block > drm/edid: Clear the old cea_rev when there's no CEA extension in the > new EDID > drm/edid: Move dvi_dual/max_tmds_clock parsing out from > drm_edid_to_eld() > drm/i915: Replace a bunch of connector->base.display_info with a local > variable > drm/i915: Account for sink max TMDS clock when checking the port clock > > drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 +- > drivers/gpu/drm/drm_edid.c | 248 > + > drivers/gpu/drm/i915/intel_display.c | 14 +- > drivers/gpu/drm/i915/intel_hdmi.c | 9 +- > drivers/gpu/drm/radeon/radeon_connectors.c | 4 +- > include/drm/drm_connector.h| 15 +- > 6 files changed, 159 insertions(+), 135 deletions(-) > > -- > 2.7.4 > > ___ > dri-devel mailing list > dri-devel at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 76490] Hang during boot when DPM is on (R9 270X)
https://bugs.freedesktop.org/show_bug.cgi?id=76490
--- Comment #117 from Daniel Exner ---
(In reply to Alex Deucher from comment #116)
> Created attachment 126814 [details] [review]
> possible fix
>
> Does this patch help?
I applied the patch on Kernel 4.8.0-rc8-00771-g8ab293e: result is a stable
system as before, so at least it didn't introduce a regression.
Then I disabled the override for my card below:
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c
index e6abc09..bcaa675 100644
--- a/drivers/gpu/drm/radeon/si_dpm.c
+++ b/drivers/gpu/drm/radeon/si_dpm.c
@@ -2924,7 +2924,6 @@ struct si_dpm_quirk {
/* cards with dpm stability problems */
static struct si_dpm_quirk si_dpm_quirk_list[] = {
/* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
- { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
{ PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
Result is the same as without your patch: black screen and non responsive
system.
Should I also revert "drm/radeon: load different smc firmware on some SI
variants"?
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[Bug 76490] Hang during boot when DPM is on (R9 270X)
https://bugs.freedesktop.org/show_bug.cgi?id=76490
--- Comment #118 from Alex Deucher ---
(In reply to Daniel Exner from comment #117)
> (In reply to Alex Deucher from comment #116)
> > Created attachment 126814 [details] [review] [review]
> > possible fix
> >
> > Does this patch help?
>
> I applied the patch on Kernel 4.8.0-rc8-00771-g8ab293e: result is a stable
> system as before, so at least it didn't introduce a regression.
>
> Then I disabled the override for my card below:
>
> diff --git a/drivers/gpu/drm/radeon/si_dpm.c
> b/drivers/gpu/drm/radeon/si_dpm.c
> index e6abc09..bcaa675 100644
> --- a/drivers/gpu/drm/radeon/si_dpm.c
> +++ b/drivers/gpu/drm/radeon/si_dpm.c
> @@ -2924,7 +2924,6 @@ struct si_dpm_quirk {
> /* cards with dpm stability problems */
> static struct si_dpm_quirk si_dpm_quirk_list[] = {
> /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */
> - { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 12 },
> { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 12 },
> { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0x2015, 0, 12 },
> { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 9 },
>
> Result is the same as without your patch: black screen and non responsive
> system.
Ok.
>
> Should I also revert "drm/radeon: load different smc firmware on some SI
> variants"?
No.
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linux-next: Tree for Sep 28 (drivers/gpu/drm/amd/amdgpu/amdgpu.ko)
> -Original Message- > From: Randy Dunlap [mailto:rdunlap at infradead.org] > Sent: Wednesday, September 28, 2016 1:10 PM > To: Stephen Rothwell; linux-next at vger.kernel.org > Cc: linux-kernel at vger.kernel.org; dri-devel; Deucher, Alexander; Koenig, > Christian > Subject: Re: linux-next: Tree for Sep 28 > (drivers/gpu/drm/amd/amdgpu/amdgpu.ko) > > On 09/27/16 23:56, Stephen Rothwell wrote: > > Hi all, > > > > Changes since 20160927: > > > > on i386: > > ERROR: "amd_set_clockgating_by_smu" > [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! > DRM_AMD_POWERPLAY needs to be set. Fixed in the attached patch. Alex > > Full randconfig file is attached. > > -- > ~Randy -- next part -- A non-text attachment was scrubbed... Name: 0001-drm-amdgpu-remove-DRM_AMD_POWERPLAY.patch Type: application/octet-stream Size: 5600 bytes Desc: 0001-drm-amdgpu-remove-DRM_AMD_POWERPLAY.patch URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/1382d16c/attachment-0001.obj>
[PATCH 0/6] drm/exynos: g2d: rework sleep and runtime PM
Hello Marek,
Marek Szyprowski wrote:
> Dear Tobias,
>
>
> On 2016-09-27 17:50, Tobias Jakobi wrote:
>> Hello everyone,
>>
>> as discussed with Marek I have broken down my initial patch into
>> smaller piecer.
>>
>> Anyway, this series fixes a regression introduced by commit
>> b05984e21a7e000bf5074ace00d7a574944b2c16.
>>
>> With best wishes,
>> Tobias
>
> Patches looks really nice! However I didn't have time to test them on
> the real
> hardware.
thanks for having a look!
I have just tested the split version of the patch on top of 4.8-rc8, and
can confirm that all the tests in upstream libdrm are working.
With best wishes,
Tobias
> You can add my:
> Acked-by: Marek Szyprowski
>
>> Tobias Jakobi (6):
>>Revert "drm/exynos: g2d: fix system and runtime pm integration"
>>drm/exynos: g2d: move PM management to runqueue worker
>>drm/exynos: g2d: remove runqueue nodes in g2d_{close,remove}()
>>drm/exynos: g2d: wait for engine to finish
>>drm/exynos: g2d: use autosuspend mode for PM runtime
>>drm/exynos: g2d: simplify g2d_free_runqueue_node()
>>
>> drivers/gpu/drm/exynos/exynos_drm_g2d.c | 237
>> +---
>> 1 file changed, 188 insertions(+), 49 deletions(-)
>>
>
> Best regards
[pull] radeon and amdgpu drm-next-4.9
Hi Dave, Some additional fixes for 4.9: - The rest of Christian's GTT rework which fixes a long standing bug in the GPUVM code among other things - Changes to the pci shutdown callbacks for certain hypervisors - Fix hpd interrupt storms on eDP panels which have the hpd interrupt enabled by the bios - misc cleanups and bug fixes The following changes since commit beb86f29c9c7f2d04f9a42c4c61cc469c3689779: drm/amd/amdgpu: Clean up afmt allocation in DCEv6. (v2) (2016-09-22 14:15:59 -0400) are available in the git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-4.9 for you to fetch changes up to a481daa88fd4d6b54f25348972bba10b5f6a84d0: drm/radeon: always apply pci shutdown callbacks (2016-09-28 16:16:27 -0400) Alex Deucher (11): drm/amdgpu: add version bump for raster config programming drm/amdgpu/vce: take all rings into account for idle checks drm/amdgpu/si/dpm: sync up quirks from radeon drm/radeon/si/dpm: fix phase shedding setup drm/amdgpu/si/dpm: fix phase shedding setup drm/amdgpu/dce10: disable hpd on local panels drm/amdgpu/dce11: disable hpd on local panels drm/amdgpu/dce8: disable hpd on local panels drm/amdgpu/dce6: disable hpd on local panels drm/amdgpu: always apply pci shutdown callbacks (v2) drm/radeon: always apply pci shutdown callbacks Christian König (13): drm/amdgpu: fix addr handling in amdgpu_vm_bo_update_mapping drm/amdgpu: add a custom GTT memory manager v2 drm/amdgpu: remove unused member from struct amdgpu_bo drm/amdgpu: rename all rbo variable to abo v2 drm/amdgpu: allocate GTT space for shadow VM page tables drm/amdgpu: cleanup VM shadow BO unreferencing drm/amdgpu: fix initializing the VM last eviction counter drm/amdgpu: fix initializing the VM BO shadow drm/amdgpu: fix amdgpu_move_blit on 32bit systems drm/amdgpu: fix BO move offsets drm/amdgpu: free userptrs even if GTT isn't bound drm/amdgpu: fix GART_DEBUGFS define drm/amdgpu: improve VM PTE trace points Flora Cui (2): drm/amdgpu: fix amdgpu_vm_bo_update param error drm/amdgpu: fix gtt_mgr bo's offset Grazvydas Ignotas (4): drm/amdgpu: clear ring pointer in amdgpu_device on teardown drm/amdgpu: don't leave dangling pointers around drm/amdgpu/i2c: add const where appropriate drm/amdgpu/vce3: don't forget to tear down some rings Nils Wallménius (1): drm/amdgpu: Constify tables Rex Zhu (1): drm/amdgpu: bypass vce clock if vce is idle on Fiji. Tom St Denis (1): drm/amd/amdgpu: Various cleanups for DCEv6 drivers/gpu/drm/amd/amdgpu/Makefile| 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c| 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c| 42 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 44 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 22 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c| 239 + drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c| 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h| 14 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 58 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h| 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c| 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c| 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 67 -- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 59 ++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 59 ++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 130 +-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 84 +--- drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 12 +- drivers/gpu/drm/amd/amdgpu/si_dpm.c| 15 +- drivers/gpu/drm/amd/amdgpu/sislands_smc.h | 1 + drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 +- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +- .../gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 12 +- drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c | 10 +- .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.h | 2 +- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c | 13 +- .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.h| 2 +- drivers/gpu/drm/radeon/radeon_drv.c| 7 +- drivers/gpu/drm/radeon
-next trees
On Tue, Sep 27, 2016 at 11:31 PM, Dave Airlie wrote: > Hey all, > > Back from a week off, I've hoovered up everything and backmerged -rc8 on top. > > If I've missed anything please let me know, I haven't seen next trees > for exynos or nouveau, as possibly a few others, but those are the > main two I noticed. Just one last set of bug fixes I sent out a few minutes ago. Alex
[PATCH v4] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Hello everyone, the recent discussion about this patch has made me realise that the purpose of the patch, and in particular what it does, and what does not, was too unclear. Hence I'm resending the patch with a (hopefully) improved and expanded commit description. With best wishes, Tobias Tobias Jakobi (1): drm/exynos: mixer: configure layers once in mixer_atomic_flush() drivers/gpu/drm/exynos/exynos_mixer.c | 135 ++ drivers/gpu/drm/exynos/regs-mixer.h | 2 + 2 files changed, 92 insertions(+), 45 deletions(-) -- 2.7.3
[PATCH v4] drm/exynos: mixer: configure layers once in mixer_atomic_flush()
Consider the following scenario:
- mixer hardware block is present including video processor
- userspace uses atomic DRM API
- userspace uses all available planes
The following call sequence (simplified) now happens when
userspace issues an atomic commit.
(1) mixer_atomic_begin()
(2) mixer_update_plane() [for 1st mixer plane]
(3) mixer_update_plane() [for 2nd mixer plane]
(4) mixer_update_plane() [for video plane]
(5) mixer_atomic_flush()
For the 1st and 2nd mixer plane mixer_update_plane() internally
calls mixer_graph_buffer(), for the video plane vp_video_buffer()
is called.
Both mixer_graph_buffer() and vp_video_buffer() setup registers
and issue these calls near the end.
- mixer_cfg_layer() & mixer_cfg_gfx_blend() [mixer]
- mixer_cfg_layer() & mixer_cfg_vp_blend() [VP]
mixer_cfg_layer() manipulates the MXR_CFG and MXR_LAYER_CFG
register.
So for each atomic commit we have 6x mixer_reg_writemask().
By rewriting mixer_cfg_layer() and moving it to the atomic
flush step, we reduce this to 2x mixer_reg_writemask().
This is the initial step to consolidate manipulation of MXR_CFG
and MXR_LAYER_CFG to mixer_atomic_flush(). A follow-up patch
is going to move mixer_cfg_scan() and mixer_cfg_rgb_fmt()
as well.
To point out:
- this is not fixing any bugs
- this is not going to improve performance (at least not
noticeable)
This is merely some micro-optimisation and the aforementioned
consolidation of register manipulation.
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/exynos/exynos_mixer.c | 135 ++
drivers/gpu/drm/exynos/regs-mixer.h | 2 +
2 files changed, 92 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c
b/drivers/gpu/drm/exynos/exynos_mixer.c
index 1e78d57..4f06f4d 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -93,12 +93,25 @@ static const uint32_t vp_formats[] = {
DRM_FORMAT_NV21,
};
+/*
+ * Mixer context structure.
+ *
+ * @crtc: The HDMI CRTC attached to the mixer.
+ * @planes: Array of plane objects for each of the mixer windows.
+ * @active_windows: Cache of the mixer's hardware state.
+ * Tracks which mixer windows are active/inactive.
+ * @pipe: The CRTC index.
+ * @flags: Bitfield build from the mixer_flag_bits enumerator.
+ * @mixer_resources: A struct containing registers, clocks, etc.
+ * @mxr_ver: The hardware revision/version of the mixer.
+ */
struct mixer_context {
struct platform_device *pdev;
struct device *dev;
struct drm_device *drm_dev;
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[MIXER_WIN_NR];
+ unsigned long active_windows;
int pipe;
unsigned long flags;
@@ -418,37 +431,70 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx,
unsigned int height)
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
}
-static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win,
- unsigned int priority, bool enable)
+/**
+ * mixer_cfg_layer - apply layer configuration to hardware
+ * @ctx: mixer context
+ *
+ * This configures the MXR_CFG and MXR_LAYER_CFG hardware registers
+ * using the 'active_windows' field of the the mixer content, and
+ * the pixel format of the framebuffers associated with the enabled
+ * windows.
+ *
+ * Has to be called under mixer lock.
+ */
+static void mixer_cfg_layer(struct mixer_context *ctx)
{
struct mixer_resources *res = &ctx->mixer_res;
- u32 val = enable ? ~0 : 0;
-
- switch (win) {
- case 0:
- mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP0_VAL(priority),
- MXR_LAYER_CFG_GRP0_MASK);
- break;
- case 1:
- mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_GRP1_VAL(priority),
- MXR_LAYER_CFG_GRP1_MASK);
+ unsigned int win;
- break;
- case VP_DEFAULT_WIN:
- if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) {
- vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
- mixer_reg_writemask(res, MXR_CFG, val,
- MXR_CFG_VP_ENABLE);
- mixer_reg_writemask(res, MXR_LAYER_CFG,
- MXR_LAYER_CFG_VP_VAL(priority),
- MXR_LAYER_CFG_VP_MASK);
+ struct exynos_drm_plane_state *state;
+ struct drm_framebuffer *fb;
+ unsigned int priority;
+ u32 mxr_cfg = 0, mxr_layer_cfg = 0, vp_enable = 0;
+ bool enable;
+
+ for (win =
[PATCH][v2] drm/sun4i: rgb: Enable panel after controller
Hi, On Mon, Sep 26, 2016 at 08:21:45PM +1000, Jonathan Liu wrote: > The panel should be enabled after the controller so that we do not have > visual glitches on the panel while the controller is setup. Similarly, > the panel should be disabled before the controller. > > Signed-off-by: Jonathan Liu Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/2e997576/attachment-0001.sig>
[PATCH] drm/sun4i: rgb: Enable panel after controller
Hi Sean, On Tue, Sep 27, 2016 at 10:42:09AM -0400, Sean Paul wrote: > As an aside, it seems like (from the diff, I haven't looked at the > code) the bridge_pre_enable and bridge_post_disable calls are missing, > and the enable/disable calls are in the wrong place. You're right. I have to push more bridges support patches in the upcoming weeks, I'll take care of that. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -- next part -- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: not available URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/416b0a37/attachment.sig>
[PATCH] drm: Restore lost drm_framebuffer_unreference in drm_mode_page_flip_ioctl
Commit 43968d7b806d ("drm: Extract drm_plane.[hc]") was not the simple
cut'n'paste we presumed, somehow it introduced a leak of the page flip
target's framebuffer.
Fixes: 43968d7b806d ("drm: Extract drm_plane.[hc]")
Signed-off-by: Chris Wilson
Cc: Daniel Vetter
Cc: Sean Paul
---
drivers/gpu/drm/drm_plane.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index cd0d475bf3c3..783aef8acab7 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -898,6 +898,8 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
out:
if (ret && crtc->funcs->page_flip_target)
drm_crtc_vblank_put(crtc);
+ if (fb)
+ drm_framebuffer_unreference(fb);
if (crtc->primary->old_fb)
drm_framebuffer_unreference(crtc->primary->old_fb);
crtc->primary->old_fb = NULL;
--
2.9.3
[Bug 141741] drm:radeon_get_bios [radeon]] *ERROR* Unable to locate a BIOS ROM
https://bugzilla.kernel.org/show_bug.cgi?id=141741 David Martos changed: What|Removed |Added CC||davidmartos96 at gmail.com --- Comment #18 from David Martos --- I can say that I am also affected by this problem. Same errors as the ones posted here and the ones posted in https://bugzilla.kernel.org/show_bug.cgi?id=120321 I tried with different OS's with kernel >4.5 (Antergos and Fedora) and all of them give the same results. Using the fallback kernel 4.5 for Fedora gives no problems whatsoever -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 97471] kworker consumes 100% of a cpu core when screen sleeps with amdgpu kernel driver.
https://bugs.freedesktop.org/show_bug.cgi?id=97471 --- Comment #10 from Malcolm Lewis --- (In reply to Alex Deucher from comment #8) > Created attachment 126818 [details] [review] > possible fix > > Does this patch help? Hi I can confirm the patch also works for me, both with the Laptop screen, laptop and HDMI attached screen and just the HDMI screen. Kernel used: 4.8.0-rc8-2.g991ee60-default OS: openSUSE Tumbleweed 20160927 Note, there is no dce_v6_0.c file, so had to tweak your patch. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20160928/a0132cb0/attachment.html>
[PATCH 1/2] drm/vc4: Increase timeout for HDMI_SCHEDULER_CONTROL changes.
Fixes occasional debug spew at boot when connected directly through
HDMI, and probably confusing the HDMI state machine when we go trying
to poke registers for the enable sequence too soon.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 4452f3631cac..5770d6704f4b 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -369,7 +369,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
- VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1);
+ VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
WARN_ONCE(ret, "Timeout waiting for "
"VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
} else {
@@ -381,7 +381,7 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder
*encoder)
~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
-VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1);
+VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
WARN_ONCE(ret, "Timeout waiting for "
"!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
}
--
2.9.3
[PATCH 2/2] drm/vc4: Add support for interlaced modes on HDMI.
We just needed to initialize a few more fields.
Signed-off-by: Eric Anholt
---
drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++---
drivers/gpu/drm/vc4/vc4_hdmi.c | 12
drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
3 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 8fc2b731b59a..d575f8aa3273 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -428,13 +428,24 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
PV_VERTB_VFP) |
VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
+
+ /* We set up first field even mode for HDMI. VEC's
+* NTSC mode would want first field odd instead, once
+* we support it (to do so, set ODD_FIRST and put the
+* delay in VSYNCD_EVEN instead).
+*/
+ CRTC_WRITE(PV_V_CONTROL,
+ PV_VCONTROL_CONTINUOUS |
+ PV_VCONTROL_INTERLACE |
+ VC4_SET_FIELD(mode->htotal / 2,
+PV_VCONTROL_ODD_DELAY));
+ CRTC_WRITE(PV_VSYNCD_EVEN, 0);
+ } else {
+ CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
}
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
- CRTC_WRITE(PV_V_CONTROL,
- PV_VCONTROL_CONTINUOUS |
- (interlace ? PV_VCONTROL_INTERLACE : 0));
CRTC_WRITE(PV_CONTROL,
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index 5770d6704f4b..6095e48fcf46 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -246,7 +246,7 @@ static struct drm_connector *vc4_hdmi_connector_init(struct
drm_device *dev,
connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT);
- connector->interlace_allowed = 0;
+ connector->interlace_allowed = true;
connector->doublescan_allowed = 0;
drm_mode_connector_attach_encoder(connector, encoder);
@@ -278,8 +278,8 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder
*encoder,
bool debug_dump_regs = false;
bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
- u32 vactive = (mode->vdisplay >>
- ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
+ bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+ u32 vactive = mode->vdisplay >> interlaced;
u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
VC4_HDMI_VERTA_VSP) |
VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
@@ -288,6 +288,10 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder
*encoder,
u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
VC4_HDMI_VERTB_VBP));
+ u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
+ VC4_SET_FIELD(mode->vtotal - mode->vsync_end -
+ interlaced,
+ VC4_HDMI_VERTB_VBP));
if (debug_dump_regs) {
DRM_INFO("HDMI regs before:\n");
@@ -319,7 +323,7 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder
*encoder,
HDMI_WRITE(VC4_HDMI_VERTA0, verta);
HDMI_WRITE(VC4_HDMI_VERTA1, verta);
- HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
+ HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
HD_WRITE(VC4_HD_VID_CTL,
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index 160942a9180e..fec7b5ef058b 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -183,6 +183,9 @@
# define PV_CONTROL_EN BIT(0)
#define PV_V_CONTROL 0x04
+# define PV_VCONTROL_ODD_DELAY_MASKVC4_MASK(22, 6)
+# define PV_VCONTROL_ODD_DELAY_SHIFT 6
+# define PV_VCONTROL_ODD_FIRST BIT(5)
# define PV_VCONTROL_INTERLACE BIT(4)
# define PV_VCONTROL_CONTINUOUSBIT(1)
# define PV_VCONTROL_VIDEN BIT(0)
--
2.9.3
[PATCH 2/2] drm/vc4: Add support for interlaced modes on HDMI.
Mark yao writes:
> On 2016å¹´09æ29æ¥ 10:20, Eric Anholt wrote:
>> We just needed to initialize a few more fields.
>>
>> Signed-off-by: Eric Anholt
>> ---
>> drivers/gpu/drm/vc4/vc4_crtc.c | 17 ++---
>> drivers/gpu/drm/vc4/vc4_hdmi.c | 12
>> drivers/gpu/drm/vc4/vc4_regs.h | 3 +++
>> 3 files changed, 25 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
>> index 8fc2b731b59a..d575f8aa3273 100644
>> --- a/drivers/gpu/drm/vc4/vc4_crtc.c
>> +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
>> @@ -428,13 +428,24 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc
>> *crtc)
>> VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
>> PV_VERTB_VFP) |
>> VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
>> +
>> +/* We set up first field even mode for HDMI. VEC's
>> + * NTSC mode would want first field odd instead, once
>> + * we support it (to do so, set ODD_FIRST and put the
>> + * delay in VSYNCD_EVEN instead).
>> + */
>> +CRTC_WRITE(PV_V_CONTROL,
>> + PV_VCONTROL_CONTINUOUS |
>> + PV_VCONTROL_INTERLACE |
>> + VC4_SET_FIELD(mode->htotal / 2,
>> + PV_VCONTROL_ODD_DELAY));
>> +CRTC_WRITE(PV_VSYNCD_EVEN, 0);
>> +} else {
>> +CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
>> }
>>
>> CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
>>
>> -CRTC_WRITE(PV_V_CONTROL,
>> - PV_VCONTROL_CONTINUOUS |
>> - (interlace ? PV_VCONTROL_INTERLACE : 0));
>>
>> CRTC_WRITE(PV_CONTROL,
>> VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
>> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
>> index 5770d6704f4b..6095e48fcf46 100644
>> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
>> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
>> @@ -246,7 +246,7 @@ static struct drm_connector
>> *vc4_hdmi_connector_init(struct drm_device *dev,
>> connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
>> DRM_CONNECTOR_POLL_DISCONNECT);
>>
>> -connector->interlace_allowed = 0;
>> +connector->interlace_allowed = true;
>> connector->doublescan_allowed = 0;
>>
>> drm_mode_connector_attach_encoder(connector, encoder);
>> @@ -278,8 +278,8 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder
>> *encoder,
>> bool debug_dump_regs = false;
>> bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
>> bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
>> -u32 vactive = (mode->vdisplay >>
>> - ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
>> +bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
>> +u32 vactive = mode->vdisplay >> interlaced;
>
> How about use mode->crtc_vdisplay:
>
> see this:
> drm_mode_set_crtcinfo()
>
> if (p->flags & DRM_MODE_FLAG_INTERLACE) {
> if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
> p->crtc_vdisplay /= 2;
> p->crtc_vsync_start /= 2;
> p->crtc_vsync_end /= 2;
> p->crtc_vtotal /= 2;
> }
> }
That would require setting up the adjust_flags, and I thought in the DRM
we were trying to move away from using it. Also it would be pretty
strange to use just this one field from crtc_*.
-- next part --
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[PATCH V2 1/2] drm/fb_cma_helper: Add drm_fb_cma_extract_and_attach_fence() helper
Add new drm_fb_cma_extract_and_attach_fence() helper function extracted
from the imx-drm driver. This function checks if the plane has DMABUF
attached to it, extracts the exclusive fence from it and attaches it
to the plane state for the atomic helper to wait on it.
Signed-off-by: Marek Vasut
Cc: Daniel Vetter
Cc: Lucas Stach
---
V2: Rename the function to drm_fb_cma_extract_and_attach_fence()
and clarify the documentation (thanks to Lucas Stach)
---
drivers/gpu/drm/drm_fb_cma_helper.c | 27 +++
include/drm/drm_fb_cma_helper.h | 3 +++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
b/drivers/gpu/drm/drm_fb_cma_helper.c
index 1fd6eac..74c7188 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -23,8 +23,10 @@
#include
#include
#include
+#include
#include
#include
+#include
#define DEFAULT_FBDEFIO_DELAY_MS 50
@@ -265,6 +267,31 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct
drm_framebuffer *fb,
}
EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
+/**
+ * drm_fb_cma_extract_and_attach_fence() - Extract fence from plane and attach
to planestate
+ * @plane: Which plane
+ * @state: Plane state attach fence to
+ *
+ * If the plane fb has an dma-buf attached, fish out the exclusive
+ * fence and attach it to plane state for the atomic helper to wait
+ * on.
+ */
+void drm_fb_cma_extract_and_attach_fence(struct drm_plane *plane,
+struct drm_plane_state *state)
+{
+ struct dma_buf *dma_buf;
+
+ if ((plane->state->fb == state->fb) || !state->fb)
+ return;
+
+ dma_buf = drm_fb_cma_get_gem_obj(state->fb, 0)->base.dma_buf;
+ if (!dma_buf)
+ return;
+
+ state->fence = reservation_object_get_excl_rcu(dma_buf->resv);
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_extract_and_attach_fence);
+
#ifdef CONFIG_DEBUG_FS
static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file *m)
{
diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
index f313211..d514faa 100644
--- a/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@ -41,6 +41,9 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device
*dev,
struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
unsigned int plane);
+void drm_fb_cma_extract_and_attach_fence(struct drm_plane *plane,
+struct drm_plane_state *state);
+
#ifdef CONFIG_DEBUG_FS
struct seq_file;
--
2.9.3
[PATCH V2 2/2] drm/imx: Switch to drm_fb_cma_extract_and_attach_fence() helper
Remove the common code from the driver and use the
drm_fb_cma_extract_and_attach_fence() helper instead.
Moveover, call the helper from prepare_fb() plane hook .
Signed-off-by: Marek Vasut
Cc: Daniel Vetter
Cc: Lucas Stach
---
V2: - Rename the function to drm_fb_cma_extract_and_attach_fence()
- Add missing newline
---
drivers/gpu/drm/imx/imx-drm-core.c | 30 +-
drivers/gpu/drm/imx/ipuv3-plane.c | 9 +
2 files changed, 10 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
b/drivers/gpu/drm/imx/imx-drm-core.c
index 98df09c..c7faa1f 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -18,7 +18,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -151,38 +150,11 @@ static int imx_drm_atomic_check(struct drm_device *dev,
return ret;
}
-static int imx_drm_atomic_commit(struct drm_device *dev,
-struct drm_atomic_state *state,
-bool nonblock)
-{
- struct drm_plane_state *plane_state;
- struct drm_plane *plane;
- struct dma_buf *dma_buf;
- int i;
-
- /*
-* If the plane fb has an dma-buf attached, fish out the exclusive
-* fence for the atomic helper to wait on.
-*/
- for_each_plane_in_state(state, plane, plane_state, i) {
- if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
- dma_buf = drm_fb_cma_get_gem_obj(plane_state->fb,
-0)->base.dma_buf;
- if (!dma_buf)
- continue;
- plane_state->fence =
- reservation_object_get_excl_rcu(dma_buf->resv);
- }
- }
-
- return drm_atomic_helper_commit(dev, state, nonblock);
-}
-
static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
.fb_create = drm_fb_cma_create,
.output_poll_changed = imx_drm_output_poll_changed,
.atomic_check = imx_drm_atomic_check,
- .atomic_commit = imx_drm_atomic_commit,
+ .atomic_commit = drm_atomic_helper_commit,
};
static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
b/drivers/gpu/drm/imx/ipuv3-plane.c
index ce22d0a..eb115a3 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -250,6 +250,14 @@ static const struct drm_plane_funcs ipu_plane_funcs = {
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
};
+static int ipu_plane_prepare_fb(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ drm_fb_cma_extract_and_attach_fence(plane, state);
+
+ return 0;
+}
+
static int ipu_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
@@ -442,6 +450,7 @@ static void ipu_plane_atomic_update(struct drm_plane *plane,
}
static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
+ .prepare_fb = ipu_plane_prepare_fb,
.atomic_check = ipu_plane_atomic_check,
.atomic_disable = ipu_plane_atomic_disable,
.atomic_update = ipu_plane_atomic_update,
--
2.9.3
[PATCH 2/2] drm/imx: Switch to drm_fb_cma_setup_fence() helper
On 09/28/2016 03:57 PM, Lucas Stach wrote:
> Am Montag, den 26.09.2016, 15:01 +0200 schrieb Marek Vasut:
>> Remove the common code from the driver and use the drm_fb_cma_setup_fence()
>> helper instead. Moveover, call the helper from prepare_fb() plane hook .
>>
>> Signed-off-by: Marek Vasut
>> Cc: Daniel Vetter
>> Cc: Lucas Stach
>
> One nit inline, otherwise looks good and is:
>
> Tested-by: Lucas Stach
>
>> ---
>> drivers/gpu/drm/imx/imx-drm-core.c | 30 +-
>> drivers/gpu/drm/imx/ipuv3-plane.c | 8
>> 2 files changed, 9 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/imx/imx-drm-core.c
>> b/drivers/gpu/drm/imx/imx-drm-core.c
>> index 98df09c..c7faa1f 100644
>> --- a/drivers/gpu/drm/imx/imx-drm-core.c
>> +++ b/drivers/gpu/drm/imx/imx-drm-core.c
>> @@ -18,7 +18,6 @@
>> #include
>> #include
>> #include
>> -#include
>> #include
>> #include
>> #include
>> @@ -151,38 +150,11 @@ static int imx_drm_atomic_check(struct drm_device *dev,
>> return ret;
>> }
>>
>> -static int imx_drm_atomic_commit(struct drm_device *dev,
>> - struct drm_atomic_state *state,
>> - bool nonblock)
>> -{
>> -struct drm_plane_state *plane_state;
>> -struct drm_plane *plane;
>> -struct dma_buf *dma_buf;
>> -int i;
>> -
>> -/*
>> - * If the plane fb has an dma-buf attached, fish out the exclusive
>> - * fence for the atomic helper to wait on.
>> - */
>> -for_each_plane_in_state(state, plane, plane_state, i) {
>> -if ((plane->state->fb != plane_state->fb) && plane_state->fb) {
>> -dma_buf = drm_fb_cma_get_gem_obj(plane_state->fb,
>> - 0)->base.dma_buf;
>> -if (!dma_buf)
>> -continue;
>> -plane_state->fence =
>> -reservation_object_get_excl_rcu(dma_buf->resv);
>> -}
>> -}
>> -
>> -return drm_atomic_helper_commit(dev, state, nonblock);
>> -}
>> -
>> static const struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
>> .fb_create = drm_fb_cma_create,
>> .output_poll_changed = imx_drm_output_poll_changed,
>> .atomic_check = imx_drm_atomic_check,
>> -.atomic_commit = imx_drm_atomic_commit,
>> +.atomic_commit = drm_atomic_helper_commit,
>> };
>>
>> static void imx_drm_atomic_commit_tail(struct drm_atomic_state *state)
>> diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c
>> b/drivers/gpu/drm/imx/ipuv3-plane.c
>> index ce22d0a..50615e3 100644
>> --- a/drivers/gpu/drm/imx/ipuv3-plane.c
>> +++ b/drivers/gpu/drm/imx/ipuv3-plane.c
>> @@ -250,6 +250,13 @@ static const struct drm_plane_funcs ipu_plane_funcs = {
>> .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
>> };
>>
>> +static int ipu_plane_prepare_fb(struct drm_plane *plane,
>> +struct drm_plane_state *state)
>> +{
>> +drm_fb_cma_setup_fence(plane, state);
>
> Blank line here to match the style in this driver.
Done, thanks.
>> +return 0;
>> +}
>> +
>> static int ipu_plane_atomic_check(struct drm_plane *plane,
>>struct drm_plane_state *state)
>> {
>> @@ -442,6 +449,7 @@ static void ipu_plane_atomic_update(struct drm_plane
>> *plane,
>> }
>>
>> static const struct drm_plane_helper_funcs ipu_plane_helper_funcs = {
>> +.prepare_fb = ipu_plane_prepare_fb,
>> .atomic_check = ipu_plane_atomic_check,
>> .atomic_disable = ipu_plane_atomic_disable,
>> .atomic_update = ipu_plane_atomic_update,
>
>
--
Best regards,
Marek Vasut
[PATCH 1/2] drm/fb_cma_helper: Add drm_fb_cma_setup_fence() helper
On 09/28/2016 03:55 PM, Lucas Stach wrote:
> Hi Marek,
>
> Am Montag, den 26.09.2016, 15:01 +0200 schrieb Marek Vasut:
>> Add new drm_fb_cma_setup_fence() helper function extracted from the
>> imx-drm driver. This function checks if the plane has DMABUF attached
>> to it and if so, sets up the fence on which the atomic helper can wait.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Daniel Vetter
>> Cc: Lucas Stach
>> ---
>> drivers/gpu/drm/drm_fb_cma_helper.c | 26 ++
>> include/drm/drm_fb_cma_helper.h | 3 +++
>> 2 files changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c
>> b/drivers/gpu/drm/drm_fb_cma_helper.c
>> index 1fd6eac..2441707 100644
>> --- a/drivers/gpu/drm/drm_fb_cma_helper.c
>> +++ b/drivers/gpu/drm/drm_fb_cma_helper.c
>> @@ -23,8 +23,10 @@
>> #include
>> #include
>> #include
>> +#include
>> #include
>> #include
>> +#include
>>
>> #define DEFAULT_FBDEFIO_DELAY_MS 50
>>
>> @@ -265,6 +267,30 @@ struct drm_gem_cma_object
>> *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
>> }
>> EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
>>
>> +/**
>> + * drm_fb_cma_setup_fence() - Set up the fence for atomic helper to wait on
>
> I don't really like the naming of the helper. It's not setting up any
> fence, it's either extracting it from the plane and/or attaching it to
> the planestate, so I would have expected the name to include extract or
> attach.
>
>> + * @plane: Which plane
>> + * @state: Plane state to check
>
> s/check/attach fence to
Both fixed in V2, thanks.
>> + *
>> + * If the plane fb has an dma-buf attached, fish out the exclusive
>> + * fence for the atomic helper to wait on.
>> + */
>> +void drm_fb_cma_setup_fence(struct drm_plane *plane,
>> +struct drm_plane_state *state)
>> +{
>> +struct dma_buf *dma_buf;
>> +
>> +if ((plane->state->fb == state->fb) || !state->fb)
>> +return;
>> +
>> +dma_buf = drm_fb_cma_get_gem_obj(state->fb, 0)->base.dma_buf;
>> +if (!dma_buf)
>> +return;
>> +
>> +state->fence = reservation_object_get_excl_rcu(dma_buf->resv);
>> +}
>> +EXPORT_SYMBOL_GPL(drm_fb_cma_setup_fence);
>> +
>> #ifdef CONFIG_DEBUG_FS
>> static void drm_fb_cma_describe(struct drm_framebuffer *fb, struct seq_file
>> *m)
>> {
>> diff --git a/include/drm/drm_fb_cma_helper.h
>> b/include/drm/drm_fb_cma_helper.h
>> index f313211..fc122d3 100644
>> --- a/include/drm/drm_fb_cma_helper.h
>> +++ b/include/drm/drm_fb_cma_helper.h
>> @@ -41,6 +41,9 @@ struct drm_framebuffer *drm_fb_cma_create(struct
>> drm_device *dev,
>> struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer
>> *fb,
>> unsigned int plane);
>>
>> +void drm_fb_cma_setup_fence(struct drm_plane *plane,
>> +struct drm_plane_state *state);
>> +
>> #ifdef CONFIG_DEBUG_FS
>> struct seq_file;
>>
>
>
--
Best regards,
Marek Vasut
[PATCH] drm: Add frame CRC debugfs files only for drivers that have CRTC
vgem does not do modeset, looping through non-existent CRTC's while
registering drm_minor in
'commit 48c787899882 ("drm: Add API for capturing frame CRCs")'
caused kernel oops. So, let's add CRC debugfs files
only for those drivers that do modeset.
Signed-off-by: Dhinakaran Pandiyan
Cc: Tomeu Vizoso
Cc: Daniel Vetter
Cc: Emil Velikov
---
drivers/gpu/drm/drm_drv.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 70d2543..294404f 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -208,6 +208,7 @@ static int drm_minor_register(struct drm_device *dev,
unsigned int type)
struct drm_crtc *crtc;
unsigned long flags;
int ret;
+ bool is_modeset;
DRM_DEBUG("\n");
@@ -221,7 +222,8 @@ static int drm_minor_register(struct drm_device *dev,
unsigned int type)
return ret;
}
- if (type == DRM_MINOR_PRIMARY) {
+ is_modeset = drm_core_check_feature(dev, DRIVER_MODESET);
+ if (type == DRM_MINOR_PRIMARY && is_modeset) {
drm_for_each_crtc(crtc, dev) {
ret = drm_debugfs_crtc_add(crtc);
if (ret)
@@ -255,12 +257,14 @@ static void drm_minor_unregister(struct drm_device *dev,
unsigned int type)
struct drm_minor *minor;
struct drm_crtc *crtc;
unsigned long flags;
+ bool is_modeset;
minor = *drm_minor_get_slot(dev, type);
if (!minor || !device_is_registered(minor->kdev))
return;
- if (type == DRM_MINOR_PRIMARY) {
+ is_modeset = drm_core_check_feature(dev, DRIVER_MODESET);
+ if (type == DRM_MINOR_PRIMARY && is_modeset) {
drm_for_each_crtc(crtc, dev)
drm_debugfs_crtc_remove(crtc);
}
--
2.7.4
linux-next: Tree for Sep 28 (drivers/gpu/drm/amd/amdgpu/amdgpu.ko)
On 09/27/16 23:56, Stephen Rothwell wrote: > Hi all, > > Changes since 20160927: > on i386: ERROR: "amd_set_clockgating_by_smu" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! Full randconfig file is attached. -- ~Randy -- next part -- # # Automatically generated file; DO NOT EDIT. # Linux/i386 4.8.0-rc8 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf32-i386" CONFIG_ARCH_DEFCONFIG="arch/x86/configs/i386_defconfig" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y CONFIG_ARCH_MMAP_RND_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_BITS_MAX=16 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 CONFIG_NEED_DMA_MAP_STATE=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_HWEIGHT=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_X86_32_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_DEBUG_RODATA=y CONFIG_PGTABLE_LEVELS=3 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_EXTABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # # General setup # CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_CROSS_COMPILE="" # CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_HAVE_KERNEL_GZIP=y CONFIG_HAVE_KERNEL_BZIP2=y CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set CONFIG_KERNEL_LZ4=y CONFIG_DEFAULT_HOSTNAME="(none)" # CONFIG_SYSVIPC is not set # CONFIG_POSIX_MQUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y # CONFIG_FHANDLE is not set # CONFIG_USELIB is not set # CONFIG_AUDIT is not set CONFIG_HAVE_ARCH_AUDITSYSCALL=y # # IRQ subsystem # CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_CHIP=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_IRQ_DOMAIN_DEBUG=y CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y # # Timers subsystem # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ_COMMON=y # CONFIG_HZ_PERIODIC is not set CONFIG_NO_HZ_IDLE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # # CPU/Task time and stats accounting # CONFIG_TICK_CPU_ACCOUNTING=y CONFIG_IRQ_TIME_ACCOUNTING=y # # RCU Subsystem # CONFIG_TREE_RCU=y CONFIG_RCU_EXPERT=y CONFIG_SRCU=y CONFIG_TASKS_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_FANOUT=32 CONFIG_RCU_FANOUT_LEAF=16 # CONFIG_RCU_FAST_NO_HZ is not set # CONFIG_TREE_RCU_TRACE is not set CONFIG_RCU_KTHREAD_PRIO=0 CONFIG_RCU_NOCB_CPU=y CONFIG_RCU_NOCB_CPU_NONE=y # CONFIG_RCU_NOCB_CPU_ZERO is not set # CONFIG_RCU_NOCB_CPU_ALL is not set # CONFIG_RCU_EXPEDITE_BOOT is not set CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_CGROUP_SCHED=y # CONFIG_FAIR_GROUP_SCHED is not set CONFIG_RT_GROUP_SCHED=y # CONFIG_CGROUP_PIDS is not set # CONFIG_CGROUP_FREEZER is not set # CONFIG_CPUSETS is not set CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y # CONFIG_CGROUP_PERF is not set # CONFIG_CGROUP_DEBUG is not set # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_SCHED_AUTOGROUP is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" # CONFIG_RD_GZIP is not set CONFIG_RD_BZIP2=y # CONFIG_RD_LZMA is not set CONFIG_RD_XZ=y # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_ANON_INODES=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_BPF=y CONFIG_EXPERT=y # CONFIG_MULTIUSER is not set CONFIG_SGETMASK_SYSCALL=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_PRINTK is not set CONFIG_BUG=y # CONFIG_PCSPKR_PLATFORM is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y # CONFIG_TIMERFD is not set CONFIG_EVENT
