[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Inki Dae
2014-08-06 16:43 GMT+09:00 Thierry Reding :
> On Wed, Aug 06, 2014 at 04:11:54PM +0900, Inki Dae wrote:
>> On 2014? 08? 05? 20:12, Thierry Reding wrote:
> [...]
>> > I think that low power mode is more often used for command transmission
>> > (in host-driven mode). I'm not sure how much sense it really makes to
>> > transmit video data in low power mode. It also seems like low power mode
>> > is what all peripherals need to support (if they can do command mode).
>> > Hence I'd like to propose the attached patch that makes all command
>> > messages use low power mode.
>>
>> To use low power mode, I think SoC drivers should add more codes:
>> checking xxx_MSG_LPM, and maybe disabling HS clock. My patch does
>> exactly that,
>> http://www.spinics.net/lists/linux-samsung-soc/msg34866.html
>
> I agree in general that DSI host drivers need to check the flags to make
> a decision about which mode to enable. But your patch also introduces
> additional flags that I don't think are necessary (at least for any of
> the use-cases discussed so far).
>
> As I understand it the MIPI_DSI_MODE_CMD_LPM and MIPI_DSI_MODE_VIDEO_LPM
> flags that you introduce would advertise that the device only supports
> low power mode for command or video modes respectively. However, I doubt

Not so. My intention is to add LPM support for video and command data
transfers because mipi-dsi framework enforces implicitly using HS mode
for
by default.

> that there really are devices that only support low power video mode. It
> wouldn't make much sense because you'd get a maximum of 10 MHz for the
> clock, which is about 1.6 frames per second at 1920x1080 resolution (not
> counting blanking). And even with lower resolutions such as 1024x768 it
> would be somewhere around 4 frames per second. And I think it's
> reasonable to assume that we'll see that kind of resolution become very
> rare in the future.
>
> So my point is that devices which support video mode will always support
> high speed mode for video transmission too. Similarly, if a device
> supports command mode, then it will likely support it in low-power mode,
> and optionally in high speed mode too.
>
>> And what I and Andrzej don't make sure is non-continuous clock mode. Do
>> you know how non-continuous clock mode is related to HS clock?
>
> As far as I can tell non-continuous mode simply means that the host can
> turn off the HS clock after a high-speed transmission. I think Andrzej
> mentioned this already in another subthread, but this is an optional
> mode that peripherals can support if they have extra circuitry that
> provides an internal clock. Peripherals that don't have such circuitry
> may rely on the HS clock to perform in between transmissions and
> therefore require the HS clock to be always on (continuous mode). That's
> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
> peripheral supports non-continuous mode and therefore the host can turn
> the HS clock off after high-speed transmissions.

What I don't make sure is this sentence. With
MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
One is,
1. host controller will generates signals if a bit of a register
related to non-contiguous clock mode is set or unset.
2. And then video data is transmitted to panel in HS mode.
3. And then D-PHY detects LP-11 signal (positive and negative lane all
are high).
4. And then D-PHY disables HS clock of host controller.
5. At this time, operation mode of host controller becomes LPM.

Other is,
1. host controller will generates signals if a bit of a register
related to non-contiguous clock mode is set or unset.
2. And then D-PHY detects LP-11 signal (positive and negative lane all
are high).
3. And then video data is transmitted to panel in LPM.
4. At this time, operation mode of host controller becomes LPM.

It seems that you says latter case.

I really know that with non-contiguous clock mode, HS clock of host
controller can be disabled. My question is who controls HS clock in
this case. D-PHY or host controller?
In other words, with LPM and MIPI_DSI_CLOCK_NON_CONTIUOUS flags,
should the host driver check these two flags to disable HS clock? or
In this case, does the D-PHY disable HS clock regardless of host
driver?

I think we should make sure that to handle LP and HS modes correctly.

>
> If a device doesn't specify that flag then the host needs to keep the HS
> clock running all the time.
>
>> > The .transfer() function was really designed with initialization
>> > commands in mind, so it doesn't deal with mixing video data and commands
>> > anyway and for initialization low-power mode should be fast enough. The
>> > downside is that it may not be optimal for some peripherals, but it
>> > gives us a good solution for the general case since it should support
>> > all devices.
>> >
>> > If we absolutely must have faster initialization, or if we come across a
>> > device that can only initialize in high speed mode, then I think we
>> > should int

[PATCH 3/3] drm: Use vblank_disable_and_save in drm_vblank_cleanup()

2014-08-07 Thread Mario Kleiner
On 08/06/2014 03:57 PM, Daniel Vetter wrote:
> On Wed, Aug 06, 2014 at 01:51:41PM +0300, Ville Syrj?l? wrote:
>> On Wed, Aug 06, 2014 at 03:22:46AM +0200, Mario Kleiner wrote:
>>> Calling vblank_disable_fn() will cause that function to no-op
>>> if !dev->vblank_disable_allowed for some kms drivers, e.g.,
>>> on nouveau-kms. This can cause the gpu vblank irq's to not get
>>> disabled before freeing the dev->vblank array, so if a
>>> vblank irq fires and calls into drm_handle_vblank() after
>>> drm_vblank_cleanup() completes, it will cause use-after-free
>>> access to dev->vblank array.
>>>
>>> Call vblank_disable_and_save unconditionally, so vblank irqs
>>> are guaranteed to be off, before we delete the data structures
>>> on which they operate.
>>>
>>> Signed-off-by: Mario Kleiner 
>>> Cc: stable at vger.kernel.org
> Imo cc: stable isn't justified for these patches which fix stuff that
> normal users don't really see (driver load failure and module reload for
> kms drivers never tends to happen for normal users).
>
> So I've dropped that and pulled the 2 patches Ville reviewd into my
> topic/vblank-rework branch for 3.18.
>
> Thanks, Daniel

Ok, good with me, thanks. Ville, thanks for the review. I'll review and 
test your vblank series next week when i have access to suitable 
machines and enough time. I need to go through this in single-step mode, 
vblank on/off changes always make me nervous, given how dependent my 
main application is on this for its timing, so i want to move through it 
in slow motion.

Btw. wrt to nouveau "No idea what games nouveau is playign with that 
flag, but this patch should be fine at least for drivers that don't do 
such things." (Villes comment).

Nouveau currently doesn't support hw vblank counter queries at all. The 
dev->driver->get_vblank_count() is just hooked up to drm_vblank_count(), 
so it's a no-op. Therefore nouveau can't allow disabling of vblank irq 
during "normal" operation as it would lose all vblank counts during the 
off period. That's why it leaves dev->vblank_disable_allowed = false;

Pre NV-50 apparently doesn't have any hw vblank counter register, but 
NV50+ seems to have one. I'll probably give implementing this a try for 
3.18 if nobody else does.

I'm not sure about all the new embedded drivers, if they have hw vblank 
counters?

thanks,
-mario

>
>> No idea what games nouveau is playign with that flag, but this patch
>> should be fine at least for drivers that don't do such things.
>>
>> Reviewed-by: Ville Syrj?l? 
>>
>>> ---
>>>   drivers/gpu/drm/drm_irq.c | 5 -
>>>   1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
>>> index 89e91e3..22e2bba9 100644
>>> --- a/drivers/gpu/drm/drm_irq.c
>>> +++ b/drivers/gpu/drm/drm_irq.c
>>> @@ -164,6 +164,7 @@ static void vblank_disable_fn(unsigned long arg)
>>>   void drm_vblank_cleanup(struct drm_device *dev)
>>>   {
>>> int crtc;
>>> +   unsigned long irqflags;
>>>   
>>> /* Bail if the driver didn't call drm_vblank_init() */
>>> if (dev->num_crtcs == 0)
>>> @@ -171,7 +172,9 @@ void drm_vblank_cleanup(struct drm_device *dev)
>>>   
>>> for (crtc = 0; crtc < dev->num_crtcs; crtc++) {
>>> del_timer_sync(&dev->vblank[crtc].disable_timer);
>>> -   vblank_disable_fn((unsigned long)&dev->vblank[crtc]);
>>> +   spin_lock_irqsave(&dev->vbl_lock, irqflags);
>>> +   vblank_disable_and_save(dev, crtc);
>>> +   spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
>>> }
>>>   
>>> kfree(dev->vblank);
>>> -- 
>>> 1.9.1
>>>
>>> ___
>>> dri-devel mailing list
>>> dri-devel at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>> -- 
>> Ville Syrj?l?
>> Intel OTC
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel



[Bug 81644] Random crashes on RadeonSI with Chromium.

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81644

--- Comment #44 from Maciej  ---
Testing Oibaf repo with kernel 3.16 under Ubuntu Gnome 14.04 - no issues after
few hours using Chrome Beta (even tried with #ignore-gpu-blacklist flag). At
least on my machine (7770) this issue looks to be Ubuntu 14.04 only.

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[Bug 81644] Random crashes on RadeonSI with Chromium.

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81644

--- Comment #45 from Aaron B  ---
I'm on Arch, from Mint, and have the issue on both. If you still don't have a
crash for a while, lets start comparing chrome/DE settings. I'm on an R9 270X,
which is a 7850 reclocked AFAIK.

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[Bug 82279] New: SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

  Priority: medium
Bug ID: 82279
  Assignee: dri-devel at lists.freedesktop.org
   Summary: SDL applications crash when changing video mode:
double free or corruption
  Severity: normal
Classification: Unclassified
OS: Linux (All)
  Reporter: xamaniqinqu at gmail.com
  Hardware: x86-64 (AMD64)
Status: NEW
   Version: git
 Component: Drivers/Gallium/radeonsi
   Product: Mesa

Created attachment 104195
  --> https://bugs.freedesktop.org/attachment.cgi?id=104195&action=edit
GDB backtrace of Dosbox crash.

Overview:
SDL applications crash when changing video mode, "corrupted double-linked
list" and "double free or corruption" are printed to stderr. The applications
tested are Dosbox and Enemy Territory: Quake Wars.

Steps to reproduce:
1) Install an abandonware game such as Commander Keen 4 
2) Run it in Dosbox
3) Depending on the game, press a key to start the game proper

Actual results:
The application crashes upon changing video mode.

Expected results:
The application changes video mode without causing a crash.

Build date and platform:
Build date of all components: 2014-08-07
Platform: Gentoo GNU/Linux x86_64
Linux kernel version: 3.16

Additional information:
Bisecting revealed the culprit commit to be
"58d2afa2232060b88f9c444ce7a0d6e63c841bb2: radeonsi: fix leaking the bound
state on destruction v2". See attachments for backtraces.

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[Bug 82279] SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

--- Comment #1 from Remco Zoet  ---
Created attachment 104196
  --> https://bugs.freedesktop.org/attachment.cgi?id=104196&action=edit
GDB full backtrace of Dosbox crash.

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[Bug 82279] SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

Remco Zoet  changed:

   What|Removed |Added

   Keywords||bisected

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[Bug 82279] [bisected] SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

Remco Zoet  changed:

   What|Removed |Added

Summary|SDL applications crash when |[bisected] SDL applications
   |changing video mode: double |crash when changing video
   |free or corruption  |mode: double free or
   ||corruption

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[Bug 82279] [bisected] SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

--- Comment #2 from Remco Zoet  ---
Some additional information: the crash (obviously) only occurs when Dosbox uses
opengl rendering. For this, 'output=opengl' or 'output=openglnb' needs to be
set in ~/${USER}/.dosbox/dosbox-${VERSION}.conf.

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[Bug 82279] SDL applications crash when changing video mode: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

Remco Zoet  changed:

   What|Removed |Added

Summary|[bisected] SDL applications |SDL applications crash when
   |crash when changing video   |changing video mode: double
   |mode: double free or|free or corruption
   |corruption  |

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[Bug 82279] SDL applications crash when changing video mode on radeonsi: double free or corruption

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

Remco Zoet  changed:

   What|Removed |Added

Summary|SDL applications crash when |SDL applications crash when
   |changing video mode: double |changing video mode on
   |free or corruption  |radeonsi: double free or
   ||corruption

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[Bug 82279] [bisected] double free or corruption on context destruction with postprocessing enabled

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

Michel D?nzer  changed:

   What|Removed |Added

 CC||deathsimple at vodafone.de
Summary|SDL applications crash when |[bisected] double free or
   |changing video mode on  |corruption on context
   |radeonsi: double free or|destruction with
   |corruption  |postprocessing enabled

--- Comment #3 from Michel D?nzer  ---
AFAICT this only happens if postprocessing is enabled via one of the pp_*
driconf options or environment variables.

(In reply to comment #0)
> Bisecting revealed the culprit commit to be
> "58d2afa2232060b88f9c444ce7a0d6e63c841bb2: radeonsi: fix leaking the bound
> state on destruction v2".

Christian, any ideas?

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[RFC PATCH] drm/mipi-dsi: add some generic functions for DCS

2014-08-07 Thread Andrzej Hajda
Hi YoungJun, Thierry,

On 07/31/2014 06:14 AM, YoungJun Cho wrote:
> This patch adds some generic functions for DCS like below
> to standize on common APIs rather than per-driver
> implementations.
>
> mipi_dcs_enter_sleep_mode() / mipi_dcs_exit_sleep_mode()
> - These are required to disable / enable all blocks inside
>   the display module.
>
> mipi_dcs_set_display_off() / mipi_dcs_set_display_on()
> - These are required to stop / start displaying the image
>   data on the display device.
>
> mipi_dcs_set_tear_off() / mipi_dcs_set_tear_on()
> - These are required to turn off or on the display module's
>   TE output signal on the TE signal line.

I wonder if it wouldn't be better to make these functions inline.

Regards
Andrzej

>
> mipi_dsi_set_maximum_return_packet_size()
> - Although it is not related with DCS, it is required before
>   using mipi_dsi_dcs_read() to specify the maximum size of
>   the payload in a long packet.
>
> Signed-off-by: YoungJun Cho 
> Acked-by: Inki Dae 
> Acked-by: Kyungmin Park 
> ---
>  drivers/gpu/drm/drm_mipi_dsi.c | 113 
> +
>  include/drm/drm_mipi_dsi.h |  14 +
>  2 files changed, 127 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c
> index 6b2bbda..ba506d7 100644
> --- a/drivers/gpu/drm/drm_mipi_dsi.c
> +++ b/drivers/gpu/drm/drm_mipi_dsi.c
> @@ -269,6 +269,119 @@ ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, 
> unsigned int channel,
>  }
>  EXPORT_SYMBOL(mipi_dsi_dcs_read);
>  
> +/**
> + * mipi_dsi_set_maximum_return_packet_size
> + * - specify the maximum size of the payload in a Long packet transmitted 
> from
> + *   peripheral back to the host processor
> + * @dsi: DSI peripheral device
> + * @size: the maximum size of the payload
> + */
> +int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi,
> + u16 size)
> +{
> + const struct mipi_dsi_host_ops *ops = dsi->host->ops;
> + struct mipi_dsi_msg msg;
> +
> + if (!ops || !ops->transfer)
> + return -ENOSYS;
> +
> + memset(&msg, 0, sizeof(msg));
> + msg.channel = dsi->channel;
> + msg.type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE;
> + msg.tx_len = sizeof(size);
> + msg.tx_buf = (const void *)(&size);
> +
> + return ops->transfer(dsi->host, &msg);
> +}
> +EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size);
> +
> +/**
> + * mipi_dcs_enter_sleep_mode - disable all unnecessary blocks inside the 
> display
> + * module except interface communication
> + * @dsi: DSI peripheral device
> + */
> +int mipi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi)
> +{
> + u8 data = MIPI_DCS_ENTER_SLEEP_MODE;
> +
> + return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
> + sizeof(data));
> +}
> +EXPORT_SYMBOL(mipi_dcs_enter_sleep_mode);
> +
> +/**
> + * mipi_dcs_exit_sleep_mode - enable all blocks inside the display module
> + * @dsi: DSI peripheral device
> + */
> +int mipi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi)
> +{
> + u8 data = MIPI_DCS_EXIT_SLEEP_MODE;
> +
> + return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
> + sizeof(data));
> +}
> +EXPORT_SYMBOL(mipi_dcs_exit_sleep_mode);
> +
> +/**
> + * mipi_dcs_set_display_off - stop displaying the image data on the display 
> device
> + * @dsi: DSI peripheral device
> + */
> +int mipi_dcs_set_display_off(struct mipi_dsi_device *dsi)
> +{
> + u8 data = MIPI_DCS_SET_DISPLAY_OFF;
> +
> + return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
> + sizeof(data));
> +}
> +EXPORT_SYMBOL(mipi_dcs_set_display_off);
> +
> +/**
> + * mipi_dcs_set_display_on - start displaying the image data on the display 
> device
> + * @dsi: DSI peripheral device
> + */
> +int mipi_dcs_set_display_on(struct mipi_dsi_device *dsi)
> +{
> + u8 data = MIPI_DCS_SET_DISPLAY_ON;
> +
> + return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
> + sizeof(data));
> +}
> +EXPORT_SYMBOL(mipi_dcs_set_display_on);
> +
> +/**
> + * mipi_dcs_set_tear_off - turn off the display module's Tearing Effect 
> output
> + * signal on the TE signal line
> + * @dsi: DSI peripheral device
> + */
> +int mipi_dcs_set_tear_off(struct mipi_dsi_device *dsi)
> +{
> + u8 data = MIPI_DCS_SET_TEAR_OFF;
> +
> + return mipi_dsi_dcs_write(dsi, dsi->channel, (const void *)&data,
> + sizeof(data));
> +}
> +EXPORT_SYMBOL(mipi_dcs_set_tear_off);
> +
> +/**
> + * mipi_dcs_set_tear_on - turn on the display module's Tearing Effect output
> + *signal on the TE signal line.
> + * @dsi: DSI peripheral device
> + * @mode: the Tearing Effect output line mode
> + *  - MIPI_DCS_TEAR_MODE_VBLANK: the TE outpu

[Bug 81644] Random crashes on RadeonSI with Chromium.

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=81644

--- Comment #46 from Michel D?nzer  ---
(In reply to comment #43)
> any special commands you append to the radeon driver ?

If you're still using radeon.hard_reset=1, you might try dropping that.

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[Bug 82253] JanusVR Browser rendering misses floors on radeonsi, works on intel

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82253

Michel D?nzer  changed:

   What|Removed |Added

   Assignee|dri-devel at lists.freedesktop |mesa-dev at 
lists.freedesktop.
   |.org|org
  Component|Drivers/Gallium/radeonsi|Mesa core

--- Comment #4 from Michel D?nzer  ---
Could be an issue in st/mesa or other driver-independent Gallium code then.

Does glretrace also report a few OpenGL API errors like these on intel?

5946: message: major api error 1: GL_INVALID_OPERATION in Inside glBegin/glEnd
5947 @0 glTranslatef(x = 2.85, y = 0, z = 0)
5947: warning: glGetError(glTranslatef) = GL_INVALID_OPERATION

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[Bug 18154] DRM support for addressing >32 bits on 32 bit cores

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=18154

--- Comment #4 from Michel D?nzer  ---
(In reply to comment #3)
> Created attachment 104143 [details] [review]
> Fix ttm_bus_placement.base type to accomodate >32 bit physical addresses

You should probably split up the TTM and radeon changes into separate patches.
Then, please submit them to the dri-devel mailing list directly.

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[Bug 82279] [bisected] double free or corruption on context destruction with postprocessing enabled

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

--- Comment #4 from Christian K?nig  ---
(In reply to comment #3)
> AFAICT this only happens if postprocessing is enabled via one of the pp_*
> driconf options or environment variables.
> 
> (In reply to comment #0)
> > Bisecting revealed the culprit commit to be
> > "58d2afa2232060b88f9c444ce7a0d6e63c841bb2: radeonsi: fix leaking the bound
> > state on destruction v2".
> 
> Christian, any ideas?

That looks like a bug in the post processing cleanup to me. The context the
shaders belong to is destroyed before pp_free is called to destroy the shaders
created from that context.

Since the bisected patch explicitly destroys all bound shaders of a context if
the context is destroyed we get a double free of the shader.

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[PATCH 3/3] drm: Use vblank_disable_and_save in drm_vblank_cleanup()

2014-08-07 Thread Daniel Vetter
On Thu, Aug 7, 2014 at 2:50 AM, Mario Kleiner
 wrote:
> I'm not sure about all the new embedded drivers, if they have hw vblank
> counters?

Quick grep says a lot don't have it or at least not implemented - they
use drm_vblank_count. Thinking about this, should we use that as a
signal to also set dev->vblnka_disable_allowed = false in
drm_vblank_init?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


Dual-channel DSI

2014-08-07 Thread Andrzej Hajda
Hi Thierry,

Nice case.

On 08/05/2014 05:39 PM, Thierry Reding wrote:
> Hi everyone,
>
> I've been working on adding support for a panel that uses what's
> commonly known as dual-channel DSI. Sometimes this is referred to as
> ganged-mode as well.
>
> What is it, you ask? It's essentially a hack to work around the band-
> width restrictions of DSI, albeit one that's been commonly implemented
> by several SoC vendors.
>
> This typically works by equipping a peripheral with two DSI interfaces,
> each of which driving one half of the screen (symmetric left-right mode)
> or every other line (symmetric odd-even mode). Apparently there can be
> asymmetric modes in addition to those two, but they seem to be the
> common ones. Often both of the DSI interfaces need to be configured
> using DCS commands and vendor specific registers.
>
> A single display controller is typically used video data transmission.
> This is necessary to provide synchronization and avoid tearing and all
> kinds of other ugliness. For this to work both DSI controllers need to
> be made aware of which chunk of the video data stream is addressing
> them.
>
> From a software perspective, this poses two problems:
>
> 1) A dual-channel device is composed of two DSI peripheral devices which
>cannot be programmed independently of each other. A typical example
>is that the frame memory extents need to be configured differently
>for each of the devices (using the DCS set_column_address and
>set_page_address commands). Therefore each device must know of the
>other, or there must be a driver that binds against a dummy device
>that pulls in the two real devices.

I am not sure if I understand correctly, but I see it rather as one
device with two dsi-slave interfaces. Probably panel driver can
create dsi dummy device to program some registers
via second dsi interface but the panel will be attached to one control bus.
It seems to be very similar to mfd/i2c devices with two or more i2c
addresses.

>
> 2) On the DSI host side, each of the controller instances needs to know
>the intimate details of the other controller (or alternatively, one
>controller needs to be a "master" and the other a "slave").

The question is if they need to communicate each other, or they have
to have similar configurations applied?

>
> I'm looking for feedback on how this is handled on other SoCs, hence
> adding a few people that I know are working on DSI as well (or have in
> the past). If you know of any other people that might have useful advice
> on this topic, feel free to include them.
>
> Another goal of this discussion is to come up with a somewhat standard
> way to represent this in device tree (oh no!) so that panels can be
> easily reused on different SoCs.
>
> What I currently have for Tegra is something along these lines:
>
>   dsi at 5430 {
>   nvidia,ganged-mode = <&dsib>;
>
>   panel at 0 {
>   compatible = "sharp,lq101r1sx01";
>   reg = <0>;
>
>   secondary = <&secondary>;
>   };
>   };
>
>   dsib: dsi at 5440 {
>   nvidia,ganged-mode;
>
>   secondary: panel at 0 {
>   reg = <0>;
>   };
>   };
>
> There are a couple of other properties in those nodes, such as
> regulators and such, but I've omitted them so that the discussion can
> focus on the important bits.
>
> In the above the panel driver will bind against dsi at 5430/panel at 0 and
> use the "secondary" property to obtain a reference to the DSI peripheral
> device of the second DSI interface of the device.
>
> Similarly, the dsi at 5430 primary DSI host will obtain a reference to
> a "slave" DSI host via the "nvidia,ganged-mode" property. The secondary
> DSI host dsi at 5440 will know that it's not a fully functional DSI
> output by the presence of the empty "nvidia,ganged-mode" property.
>
> Using the above I can get things to work, but it seems somewhat kludgy.
> For example it assumes that both DSI hosts are the same type. I'm not
> sure if it makes sense for dual-channel to use completely different DSI
> hosts given that they need to be very tightly coupled (take input from
> the same display controller, use the same PLL, ...). It's also kind of
> redundant to have to specify the dual relationship twice (once for the
> peripheral and once for the DSI hosts). There's also the issue that we
> should really be specifying a compatible string for the secondary
> instance of the DSI peripheral, but that would mean that it will bind
> against the same driver and then both would be programmed independently
> in the same way (without taking into account the differences between the
> two interfaces).
>
> One alternative to the above could be something like this:
>
>   dsi at 5430 {
>   nvidia,ganged-mode = <&dsib>;
>   nvidia,panel = <&panel>
>
>   prim

[PATCH 2/5] drm/radeon: add userptr flag to limit it to anonymous memory v2

2014-08-07 Thread Daniel Vetter
On Wed, Aug 06, 2014 at 11:45:48PM -0400, Jerome Glisse wrote:
> On Wed, Aug 06, 2014 at 10:24:31PM +0200, Daniel Vetter wrote:
> > On Wed, Aug 06, 2014 at 02:34:16PM -0400, Jerome Glisse wrote:
> > > On Wed, Aug 06, 2014 at 07:17:25PM +0200, Christian K?nig wrote:
> > > > Am 06.08.2014 um 18:08 schrieb Jerome Glisse:
> > > > >On Wed, Aug 06, 2014 at 08:55:28AM +0200, Christian K?nig wrote:
> > > > >>Am 06.08.2014 um 00:13 schrieb Jerome Glisse:
> > > > >>>On Tue, Aug 05, 2014 at 07:45:21PM +0200, Christian K?nig wrote:
> > > > Am 05.08.2014 um 19:39 schrieb Jerome Glisse:
> > > > >On Tue, Aug 05, 2014 at 06:05:29PM +0200, Christian K?nig wrote:
> > > > >>From: Christian K?nig 
> > > > >>
> > > > >>Avoid problems with writeback by limiting userptr to anonymous 
> > > > >>memory.
> > > > >>
> > > > >>v2: add commit and code comments
> > > > >I guess, i have not expressed myself clearly. This is bogus, you 
> > > > >pretend
> > > > >you want to avoid writeback issue but you still allow userspace to 
> > > > >map
> > > > >file backed pages (which by the way might be a regular bo object 
> > > > >from
> > > > >another device for instance and that would be fun).
> > > > >
> > > > >So this patch is a no go and i would rather see that this userptr 
> > > > >to
> > > > >be restricted to anon vma only no matter what. No flags here.
> > > > Mapping of non anonymous memory (e.g. everything get_user_pages 
> > > > won't fail
> > > > with) is restricted to read only access by the GPU.
> > > > 
> > > > I'm fine with making it a hard requirement for all mappings if you 
> > > > say it's
> > > > a must have.
> > > > 
> > > > >>>Well for time being you should force read only. The way you 
> > > > >>>implement write
> > > > >>>is broken. Here is how it can abuse to allow write to a file backed 
> > > > >>>mmap.
> > > > >>>
> > > > >>>mmap(fixaddress,fixedsize,NOFD)
> > > > >>>userptr_ioctl(fixedaddress, RADEON_GEM_USERPTR_ANONONLY)
> > > > >>>// bo is created successfully because fixedaddress is part of anonvma
> > > > >>>munmap(fixedaddress,fixedsize)
> > > > >>>// radeon get mmu_notifier_range_start callback and unbind page from 
> > > > >>>the
> > > > >>>// bo but radeon does not know there was an unmap.
> > > > >>>mmap(fixaddress,fixedsize,fd_to_this_read_only_file_i_want_to_write_to)
> > > > >>>radeon_ioctl_use_my_userptrbo
> > > > >>>// bo is bind again by radeon and because all flag are set at 
> > > > >>>creation
> > > > >>>// it is map with write permission allowing someone to write to a 
> > > > >>>file
> > > > >>>// that might be read only for the user.
> > > > >>>//
> > > > >>>// Script kiddies it's time to learn about gpu ...
> > > > >>>
> > > > >>>Of course if you this patch (kind of selling my own junk here) :
> > > > >>>
> > > > >>>http://www.spinics.net/lists/linux-mm/msg75878.html
> > > > >>>
> > > > >>>then you could know inside the range_start that you should remove the
> > > > >>>write permission and that it should be rechecked on next bind.
> > > > >>>
> > > > >>>Note that i have not read much of your code so maybe you handle this
> > > > >>>case somehow.
> > > > >>I've stumbled over this attack vector as well and it's the reason why 
> > > > >>I've
> > > > >>moved checking the access rights to the bind callback instead of BO 
> > > > >>creation
> > > > >>time with V5 of the patch.
> > > > >>
> > > > >>This way you get an -EFAULT if you try something like this on command
> > > > >>submission time.
> > > > >So you seem immune to that issue but you are still not checking if the 
> > > > >anon
> > > > >vma is writeable which you should again security concern here.
> > > > 
> > > > We check the access rights of the pointer using:
> > > > >if (!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
> > > > >(long)gtt->userptr,
> > > > >   ttm->num_pages * PAGE_SIZE))
> > > > >return -EFAULT;
> > > > 
> > > > Shouldn't that be enough?
> > > 
> > > No, access_ok only check against special area on some architecture and i 
> > > am
> > > pretty sure on x86 the VERIFY_WRITE or VERIFY_READ is just flat out 
> > > ignored.
> > > 
> > > What you need to test is the vma vm_flags somethings like
> > > 
> > > if (write && !(vma->vm_flags VM_WRITE))
> > >return -EPERM;
> > > 
> > > Which need to happen on all bind.
> > 
> > access_ok is _only_ valid in combination with copy_from/to_user and
> > friends and is an optimization of the access checks depending upon
> > architecture. You always need them both, one alone is useless.
> 
> ENOPARSE, access_ok will always return the same value for a given address at 
> least
> on x86 so if address supplied at ioctl time is a valid userspace address then 
> it
> will still be a valid userspace address at buffer object bind time (note that 
> the
> user address is immutable here). So access_ok can be done once and only once 
> inside
> 

[PATCH 3/3] drm: Use vblank_disable_and_save in drm_vblank_cleanup()

2014-08-07 Thread Daniel Vetter
On Thu, Aug 7, 2014 at 2:50 AM, Mario Kleiner
 wrote:
> Ok, good with me, thanks. Ville, thanks for the review. I'll review and test
> your vblank series next week when i have access to suitable machines and
> enough time. I need to go through this in single-step mode, vblank on/off
> changes always make me nervous, given how dependent my main application is
> on this for its timing, so i want to move through it in slow motion.

btw I've pulled in your patches and the one's from Ville that I think
are sane into a topic branch, in case that helps:

http://cgit.freedesktop.org/drm-intel/log/?h=topic/vblank-rework

Cheers, Daniel
-- 
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Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Thierry Reding
 this time, operation mode of host controller becomes LPM.
> 
> It seems that you says latter case.

No. High speed clock and low power mode are orthogonal. Non-continuous
mode simply means that the clock lane enters LP-11 between HS
transmissions (see 5.6 "Clock Management" of the DSI specification).

For low power mode the clock is embedded in the signal on the data lane
and therefore independent of the high speed clock.

A peripheral device will set the MIPI_DSI_CLOCK_NON_CONTINUOUS flag if
it supports non-continuous mode of operation. That is, it has own
circuitry to generate a clock that can be used for clocked operations
between high-speed transmissions (when the HS clock isn't available).

> I really know that with non-contiguous clock mode, HS clock of host
> controller can be disabled. My question is who controls HS clock in
> this case. D-PHY or host controller?

I suspect it's usually the host controller. But does it matter? From a
software perspective we usually only access the host controller, so the
D-PHY is usually completely hidden (except maybe for some registers in
the host controller to configure it).

> In other words, with LPM and MIPI_DSI_CLOCK_NON_CONTIUOUS flags,
> should the host driver check these two flags to disable HS clock? or
> In this case, does the D-PHY disable HS clock regardless of host
> driver?

Like I said, low power mode and non-continuous clock are not directly
related. Peripherals may require the HS clock to be always on and still
use low power mode for transmissions.

> >> Do you intend to control transfer mode - HS or LPM - only for command
> >> data? If so, we would need only one flag, i.e., MIPI_DSI_MODE_HS.
> >
> > We already have that flag, it's called MIPI_DSI_MSG_USE_LPM. Given the
> > above discussion I think it may still be worthwhile to invert the
> > meaning of the flag and rename it MIPI_DSI_MSG_USE_HS, so that all
> > messages are indeed sent in low power mode by default.
> 
> Yes, it may be reasonable. But I'm not sure that there is no any issue
> in case of transmitting always video data in HS mode.

Like I said, with low power mode you can't meet the bandwidth
requirements of any reasonable resolution and framerate, so I would
assume that video data can always be transmitted in HS mode. So even if
some device required video data transmission to use low power mode, then
that should be considered the oddball peripheral and it could be handled
by an extra flag.

By default we should still assume high-speed mode for video data packet
transmissions. We can address those quirks when we actually encounter
peripherals that don't work under those assumptions.

Thierry
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[PATCH v2 2/2] drm/exynos: dsi: add LPM (Low Power Mode) transfer support

2014-08-07 Thread Inki Dae
On 2014? 07? 29? 22:16, Andrzej Hajda wrote:
> On 07/29/2014 02:08 PM, Inki Dae wrote:
>> On 2014? 07? 29? 20:39, Andrzej Hajda wrote:
>>> On 07/29/2014 05:42 AM, Inki Dae wrote:
 On 2014? 07? 29? 00:50, Andrzej Hajda wrote:
> On 07/28/2014 04:00 AM, Inki Dae wrote:
>> This patch adds LPM transfer support for video or command data.
>>
>> With this patch, Exynos MIPI DSI controller can transfer command or
>> video data with HS or LP mode in accordance with mode_flags set
>> by LCD Panel driver.
>>
>> Changelog v2: Enable High Speed clock only in case of stand by request.
>>
>> Signed-off-by: Inki Dae 
>> Acked-by: Kyungmin Park 
>> ---
>>  drivers/gpu/drm/exynos/exynos_drm_dsi.c |   22 --
>>  1 file changed, 20 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c 
>> b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> index 5e78d45..1bed105 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
>> @@ -493,8 +493,11 @@ static int exynos_dsi_enable_clock(struct 
>> exynos_dsi *dsi)
>>  | DSIM_ESC_PRESCALER(esc_div)
>>  | DSIM_LANE_ESC_CLK_EN_CLK
>>  | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
>> -| DSIM_BYTE_CLK_SRC(0)
>> -| DSIM_TX_REQUEST_HSCLK;
>> +| DSIM_BYTE_CLK_SRC(0);
>> +
>> +if (!(dsi->mode_flags & MIPI_DSI_MODE_CMD_LPM))
>> +reg |= DSIM_TX_REQUEST_HSCLK;
>> +
>>  writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
>>  
>>  return 0;
>> @@ -553,6 +556,18 @@ static void exynos_dsi_set_phy_ctrl(struct 
>> exynos_dsi *dsi)
>>  writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
>>  }
>>  
>> +static void exynos_dsi_enable_hs_clock(struct exynos_dsi *dsi,
>> +bool enable)
>> +{
>> +u32 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
>> +
>> +reg &= ~DSIM_TX_REQUEST_HSCLK;
>> +if (enable)
>> +reg |= DSIM_TX_REQUEST_HSCLK;
>> +
>> +writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
>> +}
>> +
> I have tested DSIM_TX_REQUEST_HSCLK bit on trats device(video mode HS) -
> it works with and without the bit set.
 If you can test thmorstat board, you will face with that its panel is
 not worked.
>>> So it means this panel requires proper driving of this bit, but it does
>>> not prove it is
>>> LPM related.
>>>
> So I start to suspect this bit is not just for simply enable/disable HS
> clock as function name suggests, do you know what is its
> exact meaning? The specs are quite succinct on it.
 HSCLK only has meaning when it is used with CmdLpdt and TxLpdt bits.
>>> This sounds very strange. DSI specs and D-PHY specs says clearly
>>> that LPM transmissions are unrelated to HS clock [1][2]. Even timing
>>> diagrams
>>> in Exynos specs shows no dependency of LPM transmissions on HS clock.
>>> And the
>>> description of TxRequestHsClk bit says "HS clock request for HS transfer
>>> at clock lane (Turn
>>> on HS clock)".
>> There are three System power states of D-PHY, Low-Power mode, High-Speed
>> mode and Ultra-Low Power mode. High-Speed mode needs 80Mbps ~ 1Gbps per
>> Lane. Therefore, to use HS mode, HS clock should be enabled. On the
>> other hand, LP mode needs only 10MHz (max).
>>
>> So do you really think LP mode will be worked well with HS clock
>> enabled? The purpose of LP mode is to reduce power consumption while
>> transmitting data. Can you reduce the power consumption in LP mode with
>> HS clock enabled?
> 
> As MIPI specs says "All DSI transmitters and receivers shall support
> continuous clock
> behavior on the Clock Lane, and optionally may support non-continuous
> clock behavior"
> and "For continuous clock behavior, the Clock Lane remains in high-speed
> mode generating
> active clock signals between HS data packet transmissions".
> This means that HS clock should be on even in LP mode, unless panel
> supports non-continuous clock

We know what the spec says. As I mentioned already before and in other
threads, the important thing is how we should handle HS clock in
mipi-dsi framework and host driver.

To make sure that,
1. In case of supporting non-continuous clock mode, who should control
HS clock of host controller properly every time D-PHY detected LP-11? by
D-PHY hw regardless of host driver? So  in this case, doesn't the host
driver need to check MSG_LPM flag and to control HS clock before host
controller transmits command data in LPM?
One more thing, in this case, is the operation mode HS mode or LP mode
while transmitting command data - there would be LP-11 signal between
command packets 

Dual-channel DSI

2014-08-07 Thread Thierry Reding
On Thu, Aug 07, 2014 at 08:53:47AM +0200, Andrzej Hajda wrote:
> Hi Thierry,
> 
> Nice case.
> 
> On 08/05/2014 05:39 PM, Thierry Reding wrote:
> > Hi everyone,
> >
> > I've been working on adding support for a panel that uses what's
> > commonly known as dual-channel DSI. Sometimes this is referred to as
> > ganged-mode as well.
> >
> > What is it, you ask? It's essentially a hack to work around the band-
> > width restrictions of DSI, albeit one that's been commonly implemented
> > by several SoC vendors.
> >
> > This typically works by equipping a peripheral with two DSI interfaces,
> > each of which driving one half of the screen (symmetric left-right mode)
> > or every other line (symmetric odd-even mode). Apparently there can be
> > asymmetric modes in addition to those two, but they seem to be the
> > common ones. Often both of the DSI interfaces need to be configured
> > using DCS commands and vendor specific registers.
> >
> > A single display controller is typically used video data transmission.
> > This is necessary to provide synchronization and avoid tearing and all
> > kinds of other ugliness. For this to work both DSI controllers need to
> > be made aware of which chunk of the video data stream is addressing
> > them.
> >
> > From a software perspective, this poses two problems:
> >
> > 1) A dual-channel device is composed of two DSI peripheral devices which
> >cannot be programmed independently of each other. A typical example
> >is that the frame memory extents need to be configured differently
> >for each of the devices (using the DCS set_column_address and
> >set_page_address commands). Therefore each device must know of the
> >other, or there must be a driver that binds against a dummy device
> >that pulls in the two real devices.
> 
> I am not sure if I understand correctly, but I see it rather as one
> device with two dsi-slave interfaces. Probably panel driver can
> create dsi dummy device to program some registers
> via second dsi interface but the panel will be attached to one control bus.
> It seems to be very similar to mfd/i2c devices with two or more i2c
> addresses.

They are in fact attached to two different control busses. The DSI
controllers that talk to each are separate. On Tegra they are the same
type of IP block, but still two separate instances (with their own
clock, reset, etc. inputs).

So the panel driver can't create a dummy device to talk to the second
DSI interface because the second DSI interface uses a different DSI
host.

> > 2) On the DSI host side, each of the controller instances needs to know
> >the intimate details of the other controller (or alternatively, one
> >controller needs to be a "master" and the other a "slave").
> 
> The question is if they need to communicate each other, or they have
> to have similar configurations applied?

On Tegra at least the configuration needs to be almost the same. There
are two registers that may need to be programmed differently. But they
don't have to communicate with each other. Essentially the two registers
that require different programming define which parts of the display
controller's data stream they need to capture and turn into DSI packets.

Theoretically it would be possible to make this work with two completely
different DSI controllers, but in practice I'd expect that to never
happen. So I'm not sure we need to consider the case where the register
layout is different between the two DSI host controllers.

> > I'm looking for feedback on how this is handled on other SoCs, hence
> > adding a few people that I know are working on DSI as well (or have in
> > the past). If you know of any other people that might have useful advice
> > on this topic, feel free to include them.
> >
> > Another goal of this discussion is to come up with a somewhat standard
> > way to represent this in device tree (oh no!) so that panels can be
> > easily reused on different SoCs.
> >
> > What I currently have for Tegra is something along these lines:
> >
> > dsi at 5430 {
> > nvidia,ganged-mode = <&dsib>;
> >
> > panel at 0 {
> > compatible = "sharp,lq101r1sx01";
> > reg = <0>;
> >
> > secondary = <&secondary>;
> > };
> > };
> >
> > dsib: dsi at 5440 {
> > nvidia,ganged-mode;
> >
> > secondary: panel at 0 {
> > reg = <0>;
> > };
> > };
> >
> > There are a couple of other properties in those nodes, such as
> > regulators and such, but I've omitted them so that the discussion can
> > focus on the important bits.
> >
> > In the above the panel driver will bind against dsi at 5430/panel at 0 
> > and
> > use the "secondary" property to obtain a reference to the DSI peripheral
> > device of the second DSI interface of the device.
> >
> > Similarly, the dsi at 5430 primary DSI host will obtain a reference to
> > a "slave" D

[PATCH] drm/panel/simple: add optronics B101XTN01.0

2014-08-07 Thread Thierry Reding
On Wed, Aug 06, 2014 at 04:31:30PM -0400, Rob Clark wrote:
> LVDS panel, make/model described as:
> 
> AU Optronics Corporation - B101XTN01.0 (H/W:0A)
> 
> See:
> http://www.encore-electronic.com/media/B101XTN01.0.pdf

I've made it a custom to mention which board a panel is used on in the
commit message and I've requested others to do the same. The idea was
that it would give some kind of indication where to find the hardware if
somebody wanted to test or look at for reference.

> 
> Signed-off-by: Rob Clark 
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 27 +++
>  1 file changed, 27 insertions(+)

This is missing device tree binding documentation.

> 
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index a251361..16119ba 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -447,6 +447,29 @@ static const struct panel_desc samsung_ltn101nt05 = {
>   },
>  };
>  
> +static const struct drm_display_mode optronics_lvds_mode = {

Can you please name this according to the model for consistency with
other panels?

> + .clock = 72000,
> + .hdisplay = 1366,
> + .hsync_start = 1366 + 20,
> + .hsync_end = 1366 + 20 + 70,
> + .htotal = 1366 + 20 + 70,
> + .vdisplay = 768,
> + .vsync_start = 768 + 14,
> + .vsync_end = 768 + 14 + 42,
> + .vtotal = 768 + 14 + 42,
> + .vrefresh = 60,
> + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
> +};
> +
> +static const struct panel_desc optronics_lvds = {
> + .modes = &optronics_lvds_mode,
> + .num_modes = 1,
> + .size = {
> + .width = 1366,
> + .height = 768,

This needs to be the physical dimension in mm.

> + },
> +};

There's now also a new field called .bpc which contains the number of
bits per color (usually 6 or 8). Can you provide that as well? According
to the datasheet you linked to it should be 6.

> +
>  static const struct of_device_id platform_of_match[] = {
>   {
>   .compatible = "auo,b101aw03",
> @@ -476,6 +499,10 @@ static const struct of_device_id platform_of_match[] = {
>   .compatible = "samsung,ltn101nt05",
>   .data = &samsung_ltn101nt05,
>   }, {
> + .compatible = "optronics,b101xtn01",


[PATCH 2/5] drm/radeon: add userptr flag to limit it to anonymous memory v2

2014-08-07 Thread Christian König
From: Christian K?nig 

Avoid problems with writeback by limiting userptr to anonymous memory.

v2: add commit and code comments

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon_gem.c |  3 ++-
 drivers/gpu/drm/radeon/radeon_ttm.c | 10 ++
 include/uapi/drm/radeon_drm.h   |  1 +
 3 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 993ab22..032736b 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -290,7 +290,8 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
return -EACCES;

/* reject unknown flag values */
-   if (args->flags & ~RADEON_GEM_USERPTR_READONLY)
+   if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
+   RADEON_GEM_USERPTR_ANONONLY))
return -EINVAL;

/* readonly pages not tested on older hardware */
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c 
b/drivers/gpu/drm/radeon/radeon_ttm.c
index b20933f..12e37b1 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -538,6 +538,16 @@ static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
if (current->mm != gtt->usermm)
return -EPERM;

+   if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
+   /* check that we only pin down anonymous memory
+  to prevent problems with writeback */
+   unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
+   struct vm_area_struct *vma;
+   vma = find_vma(gtt->usermm, gtt->userptr);
+   if (!vma || vma->vm_file || vma->vm_end < end)
+   return -EPERM;
+   }
+
do {
unsigned num_pages = ttm->num_pages - pinned;
uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 3a9f209..9720e1a 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -816,6 +816,7 @@ struct drm_radeon_gem_create {
  * perform any operation.
  */
 #define RADEON_GEM_USERPTR_READONLY(1 << 0)
+#define RADEON_GEM_USERPTR_ANONONLY(1 << 1)

 struct drm_radeon_gem_userptr {
uint64_taddr;
-- 
1.9.1



[PATCH 3/5] drm/radeon: add userptr flag to directly validate the BO to GTT

2014-08-07 Thread Christian König
From: Christian K?nig 

This way we test userptr availability at BO creation time instead of first use.

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon_gem.c | 18 +-
 include/uapi/drm/radeon_drm.h   |  1 +
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 032736b..4506560 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -291,7 +291,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,

/* reject unknown flag values */
if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
-   RADEON_GEM_USERPTR_ANONONLY))
+   RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE))
return -EINVAL;

/* readonly pages not tested on older hardware */
@@ -312,6 +312,22 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
if (r)
goto release_object;

+   if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
+   down_read(¤t->mm->mmap_sem);
+   r = radeon_bo_reserve(bo, true);
+   if (r) {
+   up_read(¤t->mm->mmap_sem);
+   goto release_object;
+   }
+
+   radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT);
+   r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+   radeon_bo_unreserve(bo);
+   up_read(¤t->mm->mmap_sem);
+   if (r)
+   goto release_object;
+   }
+
r = drm_gem_handle_create(filp, gobj, &handle);
/* drop reference from allocate - handle holds it now */
drm_gem_object_unreference_unlocked(gobj);
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 9720e1a..5dc61c2 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -817,6 +817,7 @@ struct drm_radeon_gem_create {
  */
 #define RADEON_GEM_USERPTR_READONLY(1 << 0)
 #define RADEON_GEM_USERPTR_ANONONLY(1 << 1)
+#define RADEON_GEM_USERPTR_VALIDATE(1 << 2)

 struct drm_radeon_gem_userptr {
uint64_taddr;
-- 
1.9.1



[PATCH 4/5] drm/radeon: add userptr flag to register MMU notifier v3

2014-08-07 Thread Christian König
From: Christian K?nig 

Whenever userspace mapping related to our userptr change
we wait for it to become idle and unmap it from GTT.

v2: rebased, fix mutex unlock in error path
v3: improve commit message

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/Kconfig|   1 +
 drivers/gpu/drm/radeon/Makefile|   2 +-
 drivers/gpu/drm/radeon/radeon.h|  12 ++
 drivers/gpu/drm/radeon/radeon_device.c |   2 +
 drivers/gpu/drm/radeon/radeon_gem.c|   9 +-
 drivers/gpu/drm/radeon/radeon_mn.c | 272 +
 drivers/gpu/drm/radeon/radeon_object.c |   1 +
 include/uapi/drm/radeon_drm.h  |   1 +
 8 files changed, 298 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/radeon_mn.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index b066bb3..358b6e8 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -115,6 +115,7 @@ config DRM_RADEON
select HWMON
select BACKLIGHT_CLASS_DEVICE
select INTERVAL_TREE
+   select MMU_NOTIFIER
help
  Choose this option if you have an ATI Radeon graphics card.  There
  are both PCI and AGP versions.  You don't need to choose this to
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 0013ad0..c7fa1ae 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -80,7 +80,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o 
\
trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
-   ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o
+   ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o radeon_mn.o

 # add async DMA block
 radeon-y += \
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6f38a23..542da82 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -65,6 +65,7 @@
 #include 
 #include 
 #include 
+#include 

 #include 
 #include 
@@ -487,6 +488,9 @@ struct radeon_bo {

struct ttm_bo_kmap_obj  dma_buf_vmap;
pid_t   pid;
+
+   struct radeon_mn*mn;
+   struct interval_tree_node   mn_it;
 };
 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)

@@ -1725,6 +1729,11 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
   struct radeon_ring *cpB);
 void radeon_test_syncing(struct radeon_device *rdev);

+/*
+ * MMU Notifier
+ */
+int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
+void radeon_mn_unregister(struct radeon_bo *bo);

 /*
  * Debugfs
@@ -2372,6 +2381,9 @@ struct radeon_device {
/* tracking pinned memory */
u64 vram_pin_size;
u64 gart_pin_size;
+
+   struct mutexmn_lock;
+   DECLARE_HASHTABLE(mn_hash, 7);
 };

 bool radeon_is_px(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c 
b/drivers/gpu/drm/radeon/radeon_device.c
index c8ea050..c58f84f 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1270,6 +1270,8 @@ int radeon_device_init(struct radeon_device *rdev,
init_rwsem(&rdev->pm.mclk_lock);
init_rwsem(&rdev->exclusive_lock);
init_waitqueue_head(&rdev->irq.vblank_queue);
+   mutex_init(&rdev->mn_lock);
+   hash_init(rdev->mn_hash);
r = radeon_gem_init(rdev);
if (r)
return r;
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 4506560..2a6fbf1 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -291,7 +291,8 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,

/* reject unknown flag values */
if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
-   RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE))
+   RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE |
+   RADEON_GEM_USERPTR_REGISTER))
return -EINVAL;

/* readonly pages not tested on older hardware */
@@ -312,6 +313,12 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
if (r)
goto release_object;

+   if (args->flags & RADEON_GEM_USERPTR_REGISTER) {
+   r = radeon_mn_register(bo, args->addr);
+   if (r)
+   goto release_object;
+   }
+
if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
down_read(¤t->mm->mmap_sem);
r = radeon_bo_reserve(bo, true);
diff --git a/drivers/gpu/drm/radeon/radeon_mn.c 
b/drivers/gpu/drm/radeon/radeon_mn.c
new file mode 100644
index 000..0157bc2
--- /dev/null
+++ b/dri

[PATCH 1/5] drm/radeon: add userptr support v8

2014-08-07 Thread Christian König
From: Christian K?nig 

This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.

It imposes several restrictions upon the memory being mapped:

1. It must be page aligned (both start/end addresses, i.e ptr and size).

2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).

3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.

4. The BO is only mapped readonly for now, so no write support.

5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.

Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.

v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits

Signed-off-by: Christian K?nig 
Reviewed-by: Alex Deucher  (v4)
Reviewed-by: J?r?me Glisse  (v4)
---
 drivers/gpu/drm/radeon/radeon.h|   6 ++
 drivers/gpu/drm/radeon/radeon_cs.c |  25 +-
 drivers/gpu/drm/radeon/radeon_drv.c|   5 +-
 drivers/gpu/drm/radeon/radeon_gem.c|  68 
 drivers/gpu/drm/radeon/radeon_kms.c|   1 +
 drivers/gpu/drm/radeon/radeon_object.c |   3 +
 drivers/gpu/drm/radeon/radeon_prime.c  |  10 +++
 drivers/gpu/drm/radeon/radeon_ttm.c| 145 +
 drivers/gpu/drm/radeon/radeon_vm.c |   3 +
 include/uapi/drm/radeon_drm.h  |  16 
 10 files changed, 279 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 9e1732e..6f38a23 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2138,6 +2138,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void 
*data,
  struct drm_file *filp);
 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp);
+int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
+struct drm_file *filp);
 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 struct drm_file *file_priv);
 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
@@ -2871,6 +2873,10 @@ extern void radeon_legacy_set_clock_gating(struct 
radeon_device *rdev, int enabl
 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int 
enable);
 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 
domain);
 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
+extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
+uint32_t flags);
+extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
+extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc 
*mc, u64 base);
 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc 
*mc);
 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c 
b/drivers/gpu/drm/radeon/radeon_cs.c
index ee712c1..1321491 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -78,7 +78,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
struct radeon_cs_chunk *chunk;
struct radeon_cs_buckets buckets;
unsigned i, j;
-   bool duplicate;
+   bool duplicate, need_mmap_lock = false;
+   int r;

if (p->chunk_relocs_idx == -1) {
return 0;
@@ -164,6 +165,19 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser 
*p)
p->relocs[i].allowed_domains = domain;
}

+   if (radeon_ttm_tt_has_userptr(p->relocs[i].robj->tbo.ttm)) {
+   uint32_t domain = p->relocs[i].prefered_domains;
+   if (!(domain & RADEON_GEM_DOMAIN_GTT)) {
+   DRM_ERROR("Only RADEON_GEM_DOMAIN_GTT is "
+ "allowed for userptr BOs\n");
+   return -EINVAL;
+   }
+   need_mmap_lock = true;
+   domain = RADEON_GEM_DOMAIN_GTT;
+   p->relocs[i].prefered_domains = domain;
+   p->relocs[i].allowed_domains = domain;

[PATCH 5/5] drm/radeon: allow userptr write access under certain conditions

2014-08-07 Thread Christian König
From: Christian K?nig 

It needs to be anonymous memory (no file mappings)
and we are requried to install an MMU notifier.

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon_gem.c | 19 ---
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index 2a6fbf1..01b5894 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -285,19 +285,24 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
if (offset_in_page(args->addr | args->size))
return -EINVAL;

-   /* we only support read only mappings for now */
-   if (!(args->flags & RADEON_GEM_USERPTR_READONLY))
-   return -EACCES;
-
/* reject unknown flag values */
if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE |
RADEON_GEM_USERPTR_REGISTER))
return -EINVAL;

-   /* readonly pages not tested on older hardware */
-   if (rdev->family < CHIP_R600)
-   return -EINVAL;
+   if (args->flags & RADEON_GEM_USERPTR_READONLY) {
+   /* readonly pages not tested on older hardware */
+   if (rdev->family < CHIP_R600)
+   return -EINVAL;
+
+   } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) ||
+  !(args->flags & RADEON_GEM_USERPTR_REGISTER)) {
+
+   /* if we want to write to it we must require anonymous
+  memory and install a MMU notifier */
+   return -EACCES;
+   }

down_read(&rdev->exclusive_lock);

-- 
1.9.1



[PATCH 2/5] drm/radeon: add userptr flag to limit it to anonymous memory v2

2014-08-07 Thread Christian König
Am 07.08.2014 um 08:55 schrieb Daniel Vetter:
> On Wed, Aug 06, 2014 at 11:45:48PM -0400, Jerome Glisse wrote:
>> On Wed, Aug 06, 2014 at 10:24:31PM +0200, Daniel Vetter wrote:
>>> On Wed, Aug 06, 2014 at 02:34:16PM -0400, Jerome Glisse wrote:
 On Wed, Aug 06, 2014 at 07:17:25PM +0200, Christian K?nig wrote:
> Am 06.08.2014 um 18:08 schrieb Jerome Glisse:
>> On Wed, Aug 06, 2014 at 08:55:28AM +0200, Christian K?nig wrote:
>>> Am 06.08.2014 um 00:13 schrieb Jerome Glisse:
 On Tue, Aug 05, 2014 at 07:45:21PM +0200, Christian K?nig wrote:
> Am 05.08.2014 um 19:39 schrieb Jerome Glisse:
>> On Tue, Aug 05, 2014 at 06:05:29PM +0200, Christian K?nig wrote:
>>> From: Christian K?nig 
>>>
>>> Avoid problems with writeback by limiting userptr to anonymous 
>>> memory.
>>>
>>> v2: add commit and code comments
>> I guess, i have not expressed myself clearly. This is bogus, you 
>> pretend
>> you want to avoid writeback issue but you still allow userspace to 
>> map
>> file backed pages (which by the way might be a regular bo object from
>> another device for instance and that would be fun).
>>
>> So this patch is a no go and i would rather see that this userptr to
>> be restricted to anon vma only no matter what. No flags here.
> Mapping of non anonymous memory (e.g. everything get_user_pages won't 
> fail
> with) is restricted to read only access by the GPU.
>
> I'm fine with making it a hard requirement for all mappings if you 
> say it's
> a must have.
>
 Well for time being you should force read only. The way you implement 
 write
 is broken. Here is how it can abuse to allow write to a file backed 
 mmap.

 mmap(fixaddress,fixedsize,NOFD)
 userptr_ioctl(fixedaddress, RADEON_GEM_USERPTR_ANONONLY)
 // bo is created successfully because fixedaddress is part of anonvma
 munmap(fixedaddress,fixedsize)
 // radeon get mmu_notifier_range_start callback and unbind page from 
 the
 // bo but radeon does not know there was an unmap.
 mmap(fixaddress,fixedsize,fd_to_this_read_only_file_i_want_to_write_to)
 radeon_ioctl_use_my_userptrbo
 // bo is bind again by radeon and because all flag are set at creation
 // it is map with write permission allowing someone to write to a file
 // that might be read only for the user.
 //
 // Script kiddies it's time to learn about gpu ...

 Of course if you this patch (kind of selling my own junk here) :

 http://www.spinics.net/lists/linux-mm/msg75878.html

 then you could know inside the range_start that you should remove the
 write permission and that it should be rechecked on next bind.

 Note that i have not read much of your code so maybe you handle this
 case somehow.
>>> I've stumbled over this attack vector as well and it's the reason why 
>>> I've
>>> moved checking the access rights to the bind callback instead of BO 
>>> creation
>>> time with V5 of the patch.
>>>
>>> This way you get an -EFAULT if you try something like this on command
>>> submission time.
>> So you seem immune to that issue but you are still not checking if the 
>> anon
>> vma is writeable which you should again security concern here.
> We check the access rights of the pointer using:
>> if (!access_ok(write ? VERIFY_WRITE : VERIFY_READ,
>> (long)gtt->userptr,
>>ttm->num_pages * PAGE_SIZE))
>> return -EFAULT;
> Shouldn't that be enough?
 No, access_ok only check against special area on some architecture and i am
 pretty sure on x86 the VERIFY_WRITE or VERIFY_READ is just flat out 
 ignored.

 What you need to test is the vma vm_flags somethings like

 if (write && !(vma->vm_flags VM_WRITE))
 return -EPERM;

 Which need to happen on all bind.

That seems to be unnecessary, since get_user_pages will check that for 
us anyway.


>>> access_ok is _only_ valid in combination with copy_from/to_user and
>>> friends and is an optimization of the access checks depending upon
>>> architecture. You always need them both, one alone is useless.
>> ENOPARSE, access_ok will always return the same value for a given address at 
>> least
>> on x86 so if address supplied at ioctl time is a valid userspace address 
>> then it
>> will still be a valid userspace address at buffer object bind time (note 
>> that the
>> user address is immutable here). So access_ok can be done once and only once 
>> inside
>> the ioctl and then for the write permission you need to recheck the vma each 
>> time
>> you bind the object (or rather each t

[PATCH] drm/panel: simple: Use devm_gpiod_get_optional()

2014-08-07 Thread Thierry Reding
On Fri, Jul 25, 2014 at 11:47:25PM +0900, Alexandre Courbot wrote:
> Use the new devm_gpiod_get_optional() to simplify the probe code.
> 
> Signed-off-by: Alexandre Courbot 
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 12 +---
>  1 file changed, 5 insertions(+), 7 deletions(-)

For some reason I thought I had already applied this, but apparently I
was mistaken. Applied now, thanks.

Thierry
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[PATCH] drm/radeon: Always flush VM again on < CIK

2014-08-07 Thread Michel Dänzer
From: Michel D?nzer 

Not doing this causes piglit hangs[0] on my Cape Verde card. No issues on
Bonaire and Kaveri though.

[0] Same symptoms as those fixed on CIK by 'drm/radeon: set VM base addr
using the PFP v2'.

Signed-off-by: Michel D?nzer 
---
 drivers/gpu/drm/radeon/radeon_vm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
b/drivers/gpu/drm/radeon/radeon_vm.c
index ccae4d9..898cbb7 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -238,7 +238,9 @@ void radeon_vm_flush(struct radeon_device *rdev,
uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);

/* if we can't remember our last VM flush then flush now! */
-   if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
+   /* XXX figure out why we have to flush all the time before CIK */
+   if (rdev->family < CHIP_BONAIRE ||
+   !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
trace_radeon_vm_flush(pd_addr, ring, vm->id);
vm->pd_gpu_addr = pd_addr;
radeon_ring_vm_flush(rdev, ring, vm);
-- 
2.0.1



[GIT PULL] drm/panel: Changes for v3.17-rc1

2014-08-07 Thread Thierry Reding
Hi Dave,

The following changes since commit 7171511eaec5bf23fb06078f59784a3a0626b38f:

  Linux 3.16-rc1 (2014-06-15 17:45:28 -1000)

are available in the git repository at:

  git://anongit.freedesktop.org/tegra/linux tags/drm/panel/for-3.17-rc1

for you to fetch changes up to 9746c61960b63d2cea41333bca00c60f032052bb:

  drm/panel: simple: Use devm_gpiod_get_optional() (2014-08-07 09:35:27 +0200)

Thanks,
Thierry


drm/panel: Changes for v3.17-rc1

Panels can now be more finely controlled via .prepare() and .unprepare()
callbacks in addition to .enable() and .disable(). New kerneldoc details
what they are supposed to do and when they should be called.

The simple panel driver gained support for a couple of new panels and it
is now possible to specify additional delays during power up and power
down sequences if panels require it.

DSI devices can now advertise that they support non-continuous clock
mode which will allow DSI host controllers to disable the high speed
clock after transmissions to save power.


Ajay Kumar (15):
  drm/panel: add .prepare() and .unprepare() functions
  drm/panel: Provide convenience wrapper for .get_modes()
  drm/panel: ld9040: Add dummy prepare and unprepare routines
  drm/panel: s6e8aa0: Add dummy prepare and unprepare routines
  drm/panel: simple: Add dummy prepare and unprepare routines
  drm/exynos: dpi: Add support for panel prepare and unprepare routines
  drm/exynos: dsi: Add support for panel prepare and unprepare routines
  drm/tegra: Add support for panel prepare and unprepare routines
  drm/panel: ld9040: Add proper definition for prepare and unprepare
  drm/panel: s6e8aa0: Add proper definition for prepare and unprepare
  drm/panel: simple: Add proper definition for prepare and unprepare
  drm/panel: simple: Support delays in panel functions
  drm/panel: simple: Add AUO B133HTN01 panel support
  drm/exynos: Move DP setup into commit()
  drm/exynos: dp: Modify driver to support drm_panel

Alban Bedel (1):
  drm/panel: simple: add support for InnoLux N156BGE-L21 panel

Alexandre Courbot (3):
  drm/dsi: Flag for non-continuous clock behavior
  drm/panel: Set non-continuous clock flag on supporting panels
  drm/panel: simple: Use devm_gpiod_get_optional()

Boris BREZILLON (1):
  drm/panel: add support for Foxlink FL500WVR00-A0T panel

Russell King (2):
  drm/panel: consolidate unnecessary explicit dependencies
  drm/panel: make DRM_PANEL_LD9040 depend on SPI

St?phane Marchesin (1):
  drm/panel: simple: Add bits-per-color support

Thierry Reding (7):
  drm/dsi: Make mipi_dsi_dcs_write() return ssize_t
  drm/dsi: Use peripheral's channel for DCS commands
  drm/panel: s6e8aa0: Use static inline for upcasting
  drm/panel: simple: Add Innolux N116BGE panel support
  drm/panel: simple: Remove simple-panel compatible
  drm/panel: ld9040: Replace upcasting macro by function
  drm/dsi: Replace upcasting macro by function

 .../devicetree/bindings/panel/auo,b133htn01.txt|   7 +
 .../bindings/panel/foxlink,fl500wvr00-a0t.txt  |   7 +
 .../devicetree/bindings/panel/innolux,n116bge.txt  |   7 +
 .../bindings/panel/innolux,n156bge-l21.txt |   7 +
 drivers/gpu/drm/drm_mipi_dsi.c |  14 +-
 drivers/gpu/drm/exynos/Kconfig |   1 +
 drivers/gpu/drm/exynos/exynos_dp_core.c| 112 +---
 drivers/gpu/drm/exynos/exynos_dp_core.h|   3 +-
 drivers/gpu/drm/exynos/exynos_drm_dpi.c|   8 +-
 drivers/gpu/drm/exynos/exynos_drm_dsi.c|  13 +-
 drivers/gpu/drm/panel/Kconfig  |   7 +-
 drivers/gpu/drm/panel/panel-ld9040.c   |  21 ++-
 drivers/gpu/drm/panel/panel-s6e8aa0.c  |  29 ++-
 drivers/gpu/drm/panel/panel-simple.c   | 203 +++--
 drivers/gpu/drm/tegra/output.c |   2 +
 include/drm/drm_mipi_dsi.h |  21 ++-
 include/drm/drm_panel.h|  58 ++
 17 files changed, 447 insertions(+), 73 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/panel/auo,b133htn01.txt
 create mode 100644 
Documentation/devicetree/bindings/panel/foxlink,fl500wvr00-a0t.txt
 create mode 100644 Documentation/devicetree/bindings/panel/innolux,n116bge.txt
 create mode 100644 
Documentation/devicetree/bindings/panel/innolux,n156bge-l21.txt
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[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Inki Dae
On 2014? 08? 07? 15:58, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
>> 2014-08-06 16:43 GMT+09:00 Thierry Reding :
>>> On Wed, Aug 06, 2014 at 04:11:54PM +0900, Inki Dae wrote:
 On 2014? 08? 05? 20:12, Thierry Reding wrote:
>>> [...]
> I think that low power mode is more often used for command transmission
> (in host-driven mode). I'm not sure how much sense it really makes to
> transmit video data in low power mode. It also seems like low power mode
> is what all peripherals need to support (if they can do command mode).
> Hence I'd like to propose the attached patch that makes all command
> messages use low power mode.

 To use low power mode, I think SoC drivers should add more codes:
 checking xxx_MSG_LPM, and maybe disabling HS clock. My patch does
 exactly that,
 http://www.spinics.net/lists/linux-samsung-soc/msg34866.html
>>>
>>> I agree in general that DSI host drivers need to check the flags to make
>>> a decision about which mode to enable. But your patch also introduces
>>> additional flags that I don't think are necessary (at least for any of
>>> the use-cases discussed so far).
>>>
>>> As I understand it the MIPI_DSI_MODE_CMD_LPM and MIPI_DSI_MODE_VIDEO_LPM
>>> flags that you introduce would advertise that the device only supports
>>> low power mode for command or video modes respectively. However, I doubt
>>
>> Not so. My intention is to add LPM support for video and command data
>> transfers because mipi-dsi framework enforces implicitly using HS mode
>> for by default.
> 
> No, it doesn't enforce anything at this point. Everyone is free to use
> whatever they see fit. Drivers that require low power mode for command
> transmission can set the MIPI_DSI_MSG_USE_LPM flag in messages. For
> video there's no way to specify what a given peripheral uses, so DSI
> host controller drivers are free to do whatever they want.
> 
> So for command data we already have a means, and for video data I don't
> think it makes sense to use low power mode. Therefore I don't think
> these new flags are necessary.
> 
>>> that there really are devices that only support low power video mode. It
>>> wouldn't make much sense because you'd get a maximum of 10 MHz for the
>>> clock, which is about 1.6 frames per second at 1920x1080 resolution (not
>>> counting blanking). And even with lower resolutions such as 1024x768 it
>>> would be somewhere around 4 frames per second. And I think it's
>>> reasonable to assume that we'll see that kind of resolution become very
>>> rare in the future.
>>>
>>> So my point is that devices which support video mode will always support
>>> high speed mode for video transmission too. Similarly, if a device
>>> supports command mode, then it will likely support it in low-power mode,
>>> and optionally in high speed mode too.
>>>
 And what I and Andrzej don't make sure is non-continuous clock mode. Do
 you know how non-continuous clock mode is related to HS clock?
>>>
>>> As far as I can tell non-continuous mode simply means that the host can
>>> turn off the HS clock after a high-speed transmission. I think Andrzej
>>> mentioned this already in another subthread, but this is an optional
>>> mode that peripherals can support if they have extra circuitry that
>>> provides an internal clock. Peripherals that don't have such circuitry
>>> may rely on the HS clock to perform in between transmissions and
>>> therefore require the HS clock to be always on (continuous mode). That's
>>> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
>>> peripheral supports non-continuous mode and therefore the host can turn
>>> the HS clock off after high-speed transmissions.
>>
>> What I don't make sure is this sentence. With
>> MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
>> One is,
>> 1. host controller will generates signals if a bit of a register
>> related to non-contiguous clock mode is set or unset.
>> 2. And then video data is transmitted to panel in HS mode.
>> 3. And then D-PHY detects LP-11 signal (positive and negative lane all
>> are high).
>> 4. And then D-PHY disables HS clock of host controller.
>> 5. At this time, operation mode of host controller becomes LPM.
>>
>> Other is,
>> 1. host controller will generates signals if a bit of a register
>> related to non-contiguous clock mode is set or unset.
>> 2. And then D-PHY detects LP-11 signal (positive and negative lane all
>> are high).
>> 3. And then video data is transmitted to panel in LPM.
>> 4. At this time, operation mode of host controller becomes LPM.
>>
>> It seems that you says latter case.
> 
> No. High speed clock and low power mode are orthogonal. Non-continuous
> mode simply means that the clock lane enters LP-11 between HS
> transmissions (see 5.6 "Clock Management" of the DSI specification).
>

It seems that clock lane enters LP-11 regardless of HS clock enabled if
non-continous mode is used. Right

[GIT PULL] drm/tegra: Changes for v3.17-rc1

2014-08-07 Thread Thierry Reding
Hi Dave,

The following changes since commit e2215321ff180f280d83837f57f3a84f8b6dda0d:

  drm/tegra: Implement race-free hotplug detection (2014-07-08 11:31:36 +1000)

are available in the git repository at:

  git://anongit.freedesktop.org/tegra/linux tags/drm/tegra/for-3.17-rc1

for you to fetch changes up to ef70728c7a6571a1a7115031e932b811f1740b2e:

  drm/tegra: add MODULE_DEVICE_TABLEs (2014-08-04 10:07:39 +0200)

The starting commit of this pull might look somewhat more arbitrary than
it really is. I chose that as the earliest commit in you drm-next tree
that prevented a somewhat strange merge conflict between the race-free
hotplug detection patches and one of the patches in this pull request.
Note also that this pulls in the first commit of the drm/panel pull
request to resolve a build-time dependency, so it should be safe to
merge both pull requests in arbitrary order.

Thierry


drm/tegra: Changes for v3.17-rc1

Mostly some cleanup all over the place. Pitch alignment limitations of
the display controller are now honored and job submission is 64-bit
safe.

The SOR output (used for eDP) properly configures sync signal polarities
according to the display mode rather than hard-coding them to some value
and the number of bits per color is now taken from the panel rather than
hard-coded to properly support 24-bit vs. 18-bit panels.

The DSI controller now properly supports non-continuous clock mode.

GEM objects can now have their flags and tiling mode modified via IOCTLs
to allow buffers imported from Nouveau to be properly displayed. Newer
generations of the Tegra display controller can also detile block linear
buffers at scan-out time.

Finally the driver now properly exports MODULE_DEVICE_TABLEs to allow it
to be automatically loaded when built as a module.


Alexandre Courbot (2):
  drm/dsi: Flag for non-continuous clock behavior
  drm/tegra: dsi - Handle non-continuous clock flag

Dan Carpenter (1):
  drm/tegra: sor - missing unlock on error

Stephen Warren (1):
  drm/tegra: add MODULE_DEVICE_TABLEs

St?phane Marchesin (1):
  drm/tegra: sor - Use bits-per-color from panel

Thierry Reding (9):
  Merge branch 'drm/dsi/for-next' into drm/tegra/for-next
  drm/tegra: Implement more tiling modes
  drm/tegra: Add SET/GET_TILING IOCTLs
  drm/tegra: Add SET/GET_FLAGS IOCTLs
  drm/tegra: Allow non-authenticated processes to create buffer objects
  drm/tegra: Make job submission 64-bit safe
  drm/tegra: sor - Configure proper sync polarities
  drm/tegra: Properly align stride for framebuffers
  drm/tegra: dc - Reset controller on driver remove

 drivers/gpu/drm/tegra/dc.c| 123 ++---
 drivers/gpu/drm/tegra/dc.h|   5 +
 drivers/gpu/drm/tegra/dpaux.c |   1 +
 drivers/gpu/drm/tegra/drm.c   | 208 ++
 drivers/gpu/drm/tegra/drm.h   |  10 +-
 drivers/gpu/drm/tegra/dsi.c   |   4 +-
 drivers/gpu/drm/tegra/fb.c|  13 ++-
 drivers/gpu/drm/tegra/gem.c   |   5 +-
 drivers/gpu/drm/tegra/gem.h   |  16 +++-
 drivers/gpu/drm/tegra/gr2d.c  |   1 +
 drivers/gpu/drm/tegra/gr3d.c  |   1 +
 drivers/gpu/drm/tegra/hdmi.c  |   1 +
 drivers/gpu/drm/tegra/sor.c   |  21 -
 drivers/gpu/host1x/job.c  |  22 ++---
 include/drm/drm_mipi_dsi.h|   2 +
 include/linux/host1x.h|  15 +--
 include/uapi/drm/tegra_drm.h  |  46 ++
 17 files changed, 427 insertions(+), 67 deletions(-)
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[PATCH] drm/panel: simple: Use devm_gpiod_get_optional()

2014-08-07 Thread Alexandre Courbot
Ping, Thierry?

On Fri, Jul 25, 2014 at 11:47 PM, Alexandre Courbot  
wrote:
> Use the new devm_gpiod_get_optional() to simplify the probe code.
>
> Signed-off-by: Alexandre Courbot 
> ---
>  drivers/gpu/drm/panel/panel-simple.c | 12 +---
>  1 file changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index a251361..91bf566 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -185,16 +185,14 @@ static int panel_simple_probe(struct device *dev, const 
> struct panel_desc *desc)
> if (IS_ERR(panel->supply))
> return PTR_ERR(panel->supply);
>
> -   panel->enable_gpio = devm_gpiod_get(dev, "enable");
> +   panel->enable_gpio = devm_gpiod_get_optional(dev, "enable");
> if (IS_ERR(panel->enable_gpio)) {
> err = PTR_ERR(panel->enable_gpio);
> -   if (err != -ENOENT) {
> -   dev_err(dev, "failed to request GPIO: %d\n", err);
> -   return err;
> -   }
> +   dev_err(dev, "failed to request GPIO: %d\n", err);
> +   return err;
> +   }
>
> -   panel->enable_gpio = NULL;
> -   } else {
> +   if (panel->enable_gpio) {
> err = gpiod_direction_output(panel->enable_gpio, 0);
> if (err < 0) {
> dev_err(dev, "failed to setup GPIO: %d\n", err);
> --
> 2.0.2
>


Dual-channel DSI

2014-08-07 Thread Andrzej Hajda
On 08/07/2014 09:25 AM, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 08:53:47AM +0200, Andrzej Hajda wrote:
>> Hi Thierry,
>>
>> Nice case.
>>
>> On 08/05/2014 05:39 PM, Thierry Reding wrote:
>>> Hi everyone,
>>>
>>> I've been working on adding support for a panel that uses what's
>>> commonly known as dual-channel DSI. Sometimes this is referred to as
>>> ganged-mode as well.
>>>
>>> What is it, you ask? It's essentially a hack to work around the band-
>>> width restrictions of DSI, albeit one that's been commonly implemented
>>> by several SoC vendors.
>>>
>>> This typically works by equipping a peripheral with two DSI interfaces,
>>> each of which driving one half of the screen (symmetric left-right mode)
>>> or every other line (symmetric odd-even mode). Apparently there can be
>>> asymmetric modes in addition to those two, but they seem to be the
>>> common ones. Often both of the DSI interfaces need to be configured
>>> using DCS commands and vendor specific registers.
>>>
>>> A single display controller is typically used video data transmission.
>>> This is necessary to provide synchronization and avoid tearing and all
>>> kinds of other ugliness. For this to work both DSI controllers need to
>>> be made aware of which chunk of the video data stream is addressing
>>> them.
>>>
>>> From a software perspective, this poses two problems:
>>>
>>> 1) A dual-channel device is composed of two DSI peripheral devices which
>>>cannot be programmed independently of each other. A typical example
>>>is that the frame memory extents need to be configured differently
>>>for each of the devices (using the DCS set_column_address and
>>>set_page_address commands). Therefore each device must know of the
>>>other, or there must be a driver that binds against a dummy device
>>>that pulls in the two real devices.
>> I am not sure if I understand correctly, but I see it rather as one
>> device with two dsi-slave interfaces. Probably panel driver can
>> create dsi dummy device to program some registers
>> via second dsi interface but the panel will be attached to one control bus.
>> It seems to be very similar to mfd/i2c devices with two or more i2c
>> addresses.
> They are in fact attached to two different control busses. The DSI
> controllers that talk to each are separate. On Tegra they are the same
> type of IP block, but still two separate instances (with their own
> clock, reset, etc. inputs).
>
> So the panel driver can't create a dummy device to talk to the second
> DSI interface because the second DSI interface uses a different DSI
> host.

Why different DSI host does not allow that? The only thing panel needs
is the reference to another DSI host and this can be provided via
DT direct phandle or video interface.
>
>>> 2) On the DSI host side, each of the controller instances needs to know
>>>the intimate details of the other controller (or alternatively, one
>>>controller needs to be a "master" and the other a "slave").
>> The question is if they need to communicate each other, or they have
>> to have similar configurations applied?
> On Tegra at least the configuration needs to be almost the same. There
> are two registers that may need to be programmed differently. But they
> don't have to communicate with each other. Essentially the two registers
> that require different programming define which parts of the display
> controller's data stream they need to capture and turn into DSI packets.
>
> Theoretically it would be possible to make this work with two completely
> different DSI controllers, but in practice I'd expect that to never
> happen. So I'm not sure we need to consider the case where the register
> layout is different between the two DSI host controllers.

So maybe the configuration could be provided by the panel.

>
>>> I'm looking for feedback on how this is handled on other SoCs, hence
>>> adding a few people that I know are working on DSI as well (or have in
>>> the past). If you know of any other people that might have useful advice
>>> on this topic, feel free to include them.
>>>
>>> Another goal of this discussion is to come up with a somewhat standard
>>> way to represent this in device tree (oh no!) so that panels can be
>>> easily reused on different SoCs.
>>>
>>> What I currently have for Tegra is something along these lines:
>>>
>>> dsi at 5430 {
>>> nvidia,ganged-mode = <&dsib>;
>>>
>>> panel at 0 {
>>> compatible = "sharp,lq101r1sx01";
>>> reg = <0>;
>>>
>>> secondary = <&secondary>;
>>> };
>>> };
>>>
>>> dsib: dsi at 5440 {
>>> nvidia,ganged-mode;
>>>
>>> secondary: panel at 0 {
>>> reg = <0>;
>>> };
>>> };
>>>
>>> There are a couple of other properties in those nodes, such as
>>> regulators and such, but I've omitted them so that the discussion can
>>> focus on the important bit

Dual-channel DSI

2014-08-07 Thread Thierry Reding
gt; So maybe the configuration could be provided by the panel.

What configuration? I suppose one idea would be for the panel driver to
set the type of dual-channel mode that it's using. Panels can typically
be configured to do symmetric left-right or symmetric odd-even. I think
technically it's possible to have asymmetric modes, too, but to be
honest I don't want to think about those yet.

So I think it's reasonable for the DSI device to provide information as
to what mode it's using. Perhaps that could be done as part of the slave
setup.

> > I've come up with another alternative that works:
> >
> > dsi at 5430 {
> > panel: panel at 0 {
> > compatible = "sharp,lq101r1sx01";
> > reg = <0>;
> > };
> > };
> >
> > dsi at 5440 {
> > panel at 0 {
> > compatible = "sharp,lq101r1sx01";
> > reg = <0>;
> >
> > master = <&panel>;
> > };
> > };
> 
> But here you have again two compatibles and two devices in DT representing
> one HW device.

Because that's what they really are. There are two different devices,
it's just that they happen to be driving two separate halves of the same
panel.

> I am not sure if it is better. If you do not like video
> interfaces
> maybe better would be sth like this:
> 
>   dsi at 5430 {
>   panel: panel at 0 {
>   compatible = "sharp,lq101r1sx01";
>   reg = <0>;
>   secondary_dsi = <&dsiB>;
>   };
>   };
> 
>   dsiB: dsi at 5440 {
>   };

That's pretty much the same thing that I proposed, except that it
reverses the link between the two. In fact I tried something similar to
that before, but it has a couple of problems: if the secondary device
does not have a compatible string (that's probably not valid in device
tree to begin with) then there's no way for the device to report what
format it expects or what number of lanes it uses. But those are
parameters that are needed to set up the DSI (and display controllers).

One other problem with the above is that the dependency implied by your
"secondary_dsi" property is the wrong way around. The above would mean
that &panel requires &dsiB's services to function, but that's not the
case. If anything it's the other way around. &panel could still work
standalone (though only drive the left half of the screen).

Thierry
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[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Thierry Reding
On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote:
> On 2014? 08? 07? 15:58, Thierry Reding wrote:
> > On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
> >> 2014-08-06 16:43 GMT+09:00 Thierry Reding :
[...]
> >>> As far as I can tell non-continuous mode simply means that the host can
> >>> turn off the HS clock after a high-speed transmission. I think Andrzej
> >>> mentioned this already in another subthread, but this is an optional
> >>> mode that peripherals can support if they have extra circuitry that
> >>> provides an internal clock. Peripherals that don't have such circuitry
> >>> may rely on the HS clock to perform in between transmissions and
> >>> therefore require the HS clock to be always on (continuous mode). That's
> >>> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
> >>> peripheral supports non-continuous mode and therefore the host can turn
> >>> the HS clock off after high-speed transmissions.
> >>
> >> What I don't make sure is this sentence. With
> >> MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
> >> One is,
> >> 1. host controller will generates signals if a bit of a register
> >> related to non-contiguous clock mode is set or unset.
> >> 2. And then video data is transmitted to panel in HS mode.
> >> 3. And then D-PHY detects LP-11 signal (positive and negative lane all
> >> are high).
> >> 4. And then D-PHY disables HS clock of host controller.
> >> 5. At this time, operation mode of host controller becomes LPM.
> >>
> >> Other is,
> >> 1. host controller will generates signals if a bit of a register
> >> related to non-contiguous clock mode is set or unset.
> >> 2. And then D-PHY detects LP-11 signal (positive and negative lane all
> >> are high).
> >> 3. And then video data is transmitted to panel in LPM.
> >> 4. At this time, operation mode of host controller becomes LPM.
> >>
> >> It seems that you says latter case.
> >
> > No. High speed clock and low power mode are orthogonal. Non-continuous
> > mode simply means that the clock lane enters LP-11 between HS
> > transmissions (see 5.6 "Clock Management" of the DSI specification).
> >
> 
> It seems that clock lane enters LP-11 regardless of HS clock enabled if
> non-continous mode is used. Right?

No, I think as long as HS clock is enabled the clock lane won't enter
LP-11. Non-continuous mode means that the controller can disable the HS
clock between HS transmissions. So in non-continuous mode the clock lane
can enter LP-11 because the controller disables the HS clock.

In continuous mode, then the clock will never be disabled, hence the
clock lane will never enter LP-11.

> And also it seems that non-continous mode is different from LPM at all
> because with non-continuous mode, command data is transmitted to panel
> in HS mode, but with LPM, command data is transmitted to panel in LP
> mode. Also right?

No. I think you can send command data to the peripheral in low power
mode in both continuous and non-continuous clock modes.

> If so, shouldn't the host driver disable HS clock, in case of LP mode,
> before the host driver transmits command data?

No. If the peripheral doesn't support non-continuous mode, then the HS
clock must never be turned off. On the other hand, if the peripheral
supports non-continuous mode, then the DSI host should automatically
disable the HS clock between high-speed transmissions. That means if a
packet is transmitted in low power mode the DSI host will not be
transmitting in high-speed mode and therefore disable the HS clock.

Obviously if the controller can't do that automatically then it might be
necessary to explicitly do that in the driver. But I doubt that any DSI
controller wouldn't be able to do that automatically. On Tegra we have a
control bit that enables non-continuous mode:

DSI_HS_CLK_CTRL: control for the HS clock lane
  - 0 = CONTINUOUS: HS clock is on all the time
  - 1 = TX_ONLY: HS clock is only active during HS transmissions

> And  it seems that only one of these two flags, MSG_LPM and NON-CONTINUOUS,
> should be set by panel driver because with NON-CONTINUOUS clock mode, host
> controller generate clock and data lane signals regardless of controlling
> HS clock.

No. Non-continuous mode is something that's specific to the peripheral
and is always valid, whereas the MSG_LPM flag is only used to mark a
packet to be transmitted in low power mode (as opposed to high speed
mode). For peripherals that don't support non-continuous mode the
NON_CONTINUOUS flag needs to be set. But the driver for the peripheral
can still initiate low power mode packet transmissions by setting the
MSG_LPM flag.

Thierry
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[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #9 from LiNuxXer  ---
(In reply to Kertesz Laszlo from comment #3)
> [...]
> Additionally, even if fglrx eables turbo core boost, sometimes something
> weird happens and even the nominal speed is reported as maximum, in effect
> you can have even as low as 1.8 GHz (3.2GHz CPU) after an initial turbo
> boosted speed which lasts a few seconds. This happened to me sometimes
> (almost 50% of times) when i was compiling with 4 threads on my older
> A8-5500. I suppose its some internal downclocking mechanism kicking in at
> the wrong time because the reported temperatures were ~55C (default cooler). 
> 
> In contrast this never happened with radeon and if one thread was used it
> could have 4 GHz for hours (runaway flash in browser for example). 4 threads
> (compile) usually settled all cores at a stable ~3.7-3.8 GHz (temps up to
> 60C, default cooler). These are values on the A8-6500 (3.5GHz nominal/4.1
> GHz turbo speed from which never exceeded 4.0 as long as i monitored it).

I can confirm your findings. It looks like using fglrx will lead to longer
periods of exceeding the TDP significantly, and then suddenly it takes drastic
measures to compensate for that. From my observations I believe that it even
manipulates core affinity if only two cores are busy (having them on the same
module will save a lot of power if the whole other module can be slowed down).

With a bapm-patched radeon driver, nothing similar can be observed. Besides
saving up to 12W in console mode as compared to fglrx, the cores are able to
run at high frequencies forever with no abrupt measures to be seen.

Thank you for pointing this out. I have posted my detailed results at
http://unix.stackexchange.com/a/148918/79761 in case you're interested.

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[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #10 from LiNuxXer  ---
(In reply to Alex Deucher from comment #8)
> I'm not sure why you don't think you need a GPU driver installed.  When the
> driver is installed it not only allows the GPU to dynamically adjust it
> clocks and voltages up for performance, but also enables low power states
> and turns off certain blocks when they are not in use, so overall, you'll
> probably save more power with the GPU driver loaded than just leaving the
> GPU in the state set up by the bios.

1) You're absolutely right. radeon outperforms fglrx significantly in console
mode (in my case 10W up to 12W when disabling the output) (and not to mention
the Turbo Core performance which is much smoother).

2) You inspired me to look at all this more systematically. I have posted my
detailed results at http://unix.stackexchange.com/a/148918/79761 -- in short,
the radeon driver is an excellent piece of software (and is in fact saving my
*** regarding processor choice, applying the bapm enabling patch you proposed).

3) One question remains -- can't bapm enabling become at least a parameter? Or
is it already?

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[Bug 82162] Syslog flooded by [drm:radeon_gem_object_create] errors

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82162

--- Comment #19 from Marek Ol??k  ---
Could you please set a breakpoint in si_texture_get_cmask_info and print:

rscreen->tiling_info AND rscreen->info

OR

pipe_interleave_bytes AND num_pipes

Thanks.

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[Intel-gfx] [PATCH 0/6] Rename DP training vswing/pre-emph defines

2014-08-07 Thread Damien Lespiau
On Tue, Aug 05, 2014 at 04:38:16PM +0530, sonika.jindal at intel.com wrote:
> From: Sonika Jindal 
> 
> Rename the defines to have levels instead of values for vswing and pre-emph
> levels as the values may differ in other scenarios like low vswing of eDP 1.4
> where the values are different.
> Updated in all the drivers as well

Hi Sonika,

Oops, another mess in this series :) If there's a need to rework the
series and add/remove patches, the best way to send a v2 is to actually
resend the whole series, otherwise someone will get it wrong and won't
apply the right patches.

So, could you resend the whole series again with the patches generated
by Daniel's review comment and with the explanation copy/pasted in all
the driver patches (as Jingoo Han asked). It's fair enough to track why
the rename was needed in driver-specific patches instead of relying on
the cover letter.

Thanks,

-- 
Damien


ipu-v3 build fix

2014-08-07 Thread Dave Airlie
does ipu-v3 need to

select GENERIC_IRQ_CHIP

otherwise on my arm test builds I get a failure to link due to missing
irq symbols.

Dave.


[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Inki Dae
On 2014? 08? 07? 18:09, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 15:58, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
 2014-08-06 16:43 GMT+09:00 Thierry Reding :
> [...]
> As far as I can tell non-continuous mode simply means that the host can
> turn off the HS clock after a high-speed transmission. I think Andrzej
> mentioned this already in another subthread, but this is an optional
> mode that peripherals can support if they have extra circuitry that
> provides an internal clock. Peripherals that don't have such circuitry
> may rely on the HS clock to perform in between transmissions and
> therefore require the HS clock to be always on (continuous mode). That's
> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
> peripheral supports non-continuous mode and therefore the host can turn
> the HS clock off after high-speed transmissions.

 What I don't make sure is this sentence. With
 MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
 One is,
 1. host controller will generates signals if a bit of a register
 related to non-contiguous clock mode is set or unset.
 2. And then video data is transmitted to panel in HS mode.
 3. And then D-PHY detects LP-11 signal (positive and negative lane all
 are high).
 4. And then D-PHY disables HS clock of host controller.
 5. At this time, operation mode of host controller becomes LPM.

 Other is,
 1. host controller will generates signals if a bit of a register
 related to non-contiguous clock mode is set or unset.
 2. And then D-PHY detects LP-11 signal (positive and negative lane all
 are high).
 3. And then video data is transmitted to panel in LPM.
 4. At this time, operation mode of host controller becomes LPM.

 It seems that you says latter case.
>>>
>>> No. High speed clock and low power mode are orthogonal. Non-continuous
>>> mode simply means that the clock lane enters LP-11 between HS
>>> transmissions (see 5.6 "Clock Management" of the DSI specification).
>>>
>>
>> It seems that clock lane enters LP-11 regardless of HS clock enabled if
>> non-continous mode is used. Right?
> 
> No, I think as long as HS clock is enabled the clock lane won't enter
> LP-11. Non-continuous mode means that the controller can disable the HS
> clock between HS transmissions. So in non-continuous mode the clock lane
> can enter LP-11 because the controller disables the HS clock.

It makes me a little bit confusing. You said "if HS clock is enabled,
the the clock lane won't enter LP-11" But you said again "the clock lane
can enter LP-11 because the controller disables the HS clock" What is
the meaning?

> 
> In continuous mode, then the clock will never be disabled, hence the
> clock lane will never enter LP-11.
> 
>> And also it seems that non-continous mode is different from LPM at all
>> because with non-continuous mode, command data is transmitted to panel
>> in HS mode, but with LPM, command data is transmitted to panel in LP
>> mode. Also right?
> 
> No. I think you can send command data to the peripheral in low power
> mode in both continuous and non-continuous clock modes.
> 
>> If so, shouldn't the host driver disable HS clock, in case of LP mode,
>> before the host driver transmits command data?
> 
> No. If the peripheral doesn't support non-continuous mode, then the HS
> clock must never be turned off. On the other hand, if the peripheral
> supports non-continuous mode, then the DSI host should automatically
> disable the HS clock between high-speed transmissions. That means if a
> packet is transmitted in low power mode the DSI host will not be
> transmitting in high-speed mode and therefore disable the HS clock.

What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
for LPM transfer, lanes should be LP-11 state and also HS clock of the
host controller should be disabled.

Your comment, "if a packet is transmitted in low power mode the DSI host
will not be transmitting in high-speed mode and therefor disable the HS
clock" would mean same as my question.

> 
> Obviously if the controller can't do that automatically then it might be
> necessary to explicitly do that in the driver. But I doubt that any DSI
> controller wouldn't be able to do that automatically. On Tegra we have a
> control bit that enables non-continuous mode:
> 
>   DSI_HS_CLK_CTRL: control for the HS clock lane
> - 0 = CONTINUOUS: HS clock is on all the time
> - 1 = TX_ONLY: HS clock is only active during HS transmissions

MIPI-DSI of Exynos SoC also has similar bit but the spec doesn't
describe it enough. Thanks for information.

I will try to get more information about above comments from HW guys if
I can contact them.

Thanks,
Inki Dae

> 
>> And  it seems that only one of these two flags, MSG_LPM and

[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Thierry Reding
ower mode the DSI host will not be
> > transmitting in high-speed mode and therefore disable the HS clock.
> 
> What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
> for LPM transfer, lanes should be LP-11 state and also HS clock of the
> host controller should be disabled.

No. I don't think any transmissions can happen when all lanes are in
LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet
should be transmitted in low power mode (see LP Transmission in 2.1
"Definitions" of the MIPI DSI specification).

For low power transmissions, only data lane 0 is used (with a clock
embedded in the signal), therefore the clock lane (driven by the HS
clock) can be in LP-11.

Thierry
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[PATCH] drm/radeon: Adding UVD handle basis fps estimation v2

2014-08-07 Thread Christian König
From: Marco A Benatto 

Adding a Frames Per Second estimation logic on UVD handles
when it has being used. This estimation is per handle basis
and will help on DPM profile calculation.

v2 (chk): fix timestamp type, move functions around and
  cleanup code a bit.

Signed-off-by: Marco A Benatto 
Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon.h | 10 ++
 drivers/gpu/drm/radeon/radeon_uvd.c | 64 +
 2 files changed, 68 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 9e1732e..e92f6cb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1617,6 +1617,15 @@ int radeon_pm_get_type_index(struct radeon_device *rdev,
 #define RADEON_UVD_STACK_SIZE  (1024*1024)
 #define RADEON_UVD_HEAP_SIZE   (1024*1024)

+#define RADEON_UVD_FPS_EVENTS_MAX 8
+#define RADEON_UVD_DEFAULT_FPS 60
+
+struct radeon_uvd_fps {
+   uint64_ttimestamp;
+   uint8_t event_index;
+   uint8_t events[RADEON_UVD_FPS_EVENTS_MAX];
+};
+
 struct radeon_uvd {
struct radeon_bo*vcpu_bo;
void*cpu_addr;
@@ -1626,6 +1635,7 @@ struct radeon_uvd {
struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
unsignedimg_size[RADEON_MAX_UVD_HANDLES];
struct delayed_work idle_work;
+   struct radeon_uvd_fps   fps_info[RADEON_MAX_UVD_HANDLES];
 };

 int radeon_uvd_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c 
b/drivers/gpu/drm/radeon/radeon_uvd.c
index 6bf55ec..ef5667a 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -237,6 +237,51 @@ void radeon_uvd_force_into_uvd_segment(struct radeon_bo 
*rbo)
rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
 }

+static void radeon_uvd_fps_clear_events(struct radeon_device *rdev, int idx)
+{
+   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
+   unsigned i;
+
+   fps->timestamp = jiffies_64;
+   fps->event_index = 0;
+   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++)
+   fps->events[i] = 0;
+}
+
+static void radeon_uvd_fps_note_event(struct radeon_device *rdev, int idx)
+{
+   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
+   uint64_t timestamp = jiffies_64;
+   unsigned rate = 0;
+
+   uint8_t index = fps->event_index++;
+   fps->event_index %= RADEON_UVD_FPS_EVENTS_MAX;
+
+   rate = div64_u64(HZ, max(timestamp - fps->timestamp, 1ULL));
+
+   fps->timestamp = timestamp;
+   fps->events[index] = min(rate, 120u);
+}
+
+static unsigned radeon_uvd_estimate_fps(struct radeon_device *rdev, int idx)
+{
+   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
+   unsigned i, valid = 0, count = 0;
+
+   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++) {
+   /* We should ignore zero values */
+   if (fps->events[i] != 0) {
+   count += fps->events[i];
+   valid++;
+   }
+   }
+
+   if (valid > 0)
+   return count / valid;
+   else
+   return RADEON_UVD_DEFAULT_FPS;
+}
+
 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
 {
int i, r;
@@ -419,8 +464,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, 
struct radeon_bo *bo,

/* create or decode, validate the handle */
for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
-   if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
+   if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
+   radeon_uvd_fps_note_event(p->rdev, i);
return 0;
+   }
}

/* handle not found try to alloc a new one */
@@ -428,6 +475,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, 
struct radeon_bo *bo,
if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
p->rdev->uvd.filp[i] = p->filp;
p->rdev->uvd.img_size[i] = img_size;
+   radeon_uvd_fps_clear_events(p->rdev, i);
return 0;
}
}
@@ -763,7 +811,7 @@ int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, 
int ring,
 static void radeon_uvd_count_handles(struct radeon_device *rdev,
 unsigned *sd, unsigned *hd)
 {
-   unsigned i;
+   unsigned i, fps_rate = 0;

*sd = 0;
*hd = 0;
@@ -772,10 +820,13 @@ static void radeon_uvd_count_handles(struct radeon_device 
*rdev,
if (!atomic_read(&rdev->uvd.handles[i]))
continue;

-   if (rdev->uvd.img_size[i] >= 720*576)
-   ++(*hd);
-   else
-   ++(*sd);
+   fps_rate = 

[PATCH] drm/panel/simple: add optronics B101XTN01.0

2014-08-07 Thread Rob Clark
On Thu, Aug 7, 2014 at 3:33 AM, Thierry Reding  
wrote:
> On Wed, Aug 06, 2014 at 04:31:30PM -0400, Rob Clark wrote:
>> LVDS panel, make/model described as:
>>
>> AU Optronics Corporation - B101XTN01.0 (H/W:0A)
>>
>> See:
>> http://www.encore-electronic.com/media/B101XTN01.0.pdf
>
> I've made it a custom to mention which board a panel is used on in the
> commit message and I've requested others to do the same. The idea was
> that it would give some kind of indication where to find the hardware if
> somebody wanted to test or look at for reference.

It's just a free-standing panel, which (in this case) can be plugged
to an ifc6410 (and I think various other inforce boards..) looks like
a standard(ish) 41 pin connector.

>>
>> Signed-off-by: Rob Clark 
>> ---
>>  drivers/gpu/drm/panel/panel-simple.c | 27 +++
>>  1 file changed, 27 insertions(+)
>
> This is missing device tree binding documentation.

there is nothing new, so I assume you just mean adding the compatible
string to a list?

>>
>> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
>> b/drivers/gpu/drm/panel/panel-simple.c
>> index a251361..16119ba 100644
>> --- a/drivers/gpu/drm/panel/panel-simple.c
>> +++ b/drivers/gpu/drm/panel/panel-simple.c
>> @@ -447,6 +447,29 @@ static const struct panel_desc samsung_ltn101nt05 = {
>>   },
>>  };
>>
>> +static const struct drm_display_mode optronics_lvds_mode = {
>
> Can you please name this according to the model for consistency with
> other panels?
>
>> + .clock = 72000,
>> + .hdisplay = 1366,
>> + .hsync_start = 1366 + 20,
>> + .hsync_end = 1366 + 20 + 70,
>> + .htotal = 1366 + 20 + 70,
>> + .vdisplay = 768,
>> + .vsync_start = 768 + 14,
>> + .vsync_end = 768 + 14 + 42,
>> + .vtotal = 768 + 14 + 42,
>> + .vrefresh = 60,
>> + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
>> +};
>> +
>> +static const struct panel_desc optronics_lvds = {
>> + .modes = &optronics_lvds_mode,
>> + .num_modes = 1,
>> + .size = {
>> + .width = 1366,
>> + .height = 768,
>
> This needs to be the physical dimension in mm.
>
>> + },
>> +};
>
> There's now also a new field called .bpc which contains the number of
> bits per color (usually 6 or 8). Can you provide that as well? According
> to the datasheet you linked to it should be 6.

well, that was a follow-on question I had as soon as I find a
different 8bpc panel.. but ok, nice that this was added.

>> +
>>  static const struct of_device_id platform_of_match[] = {
>>   {
>>   .compatible = "auo,b101aw03",
>> @@ -476,6 +499,10 @@ static const struct of_device_id platform_of_match[] = {
>>   .compatible = "samsung,ltn101nt05",
>>   .data = &samsung_ltn101nt05,
>>   }, {
>> + .compatible = "optronics,b101xtn01",
>
> From the commit message this panel is from AU Optronics, so it should
> use the auo vendor prefix.

so, "auo,b101xtn01" works for everyone?

BR,
-R

> Thierry


[PATCH] drm: Restore drm_file->is_master

2014-08-07 Thread Chris Wilson
Despite the claims of

commit 48ba813701eb14b3008edefef4a0789b328e278c
Author: David Herrmann 
Date:   Tue Jul 22 18:46:09 2014 +0200

drm: drop redundant drm_file->is_master

drm_file->is_master is not synomous with having drm_file->master ==
drm_file->minor->master. This is because drm_file->master is the same
for all drm_files of the same generation and so when there is a master,
every drm_file believes itself to be the master. Confusion ensues and
things go pear shaped when one file is closed and there is no master
anymore.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82283
Signed-off-by: Chris Wilson 
Cc: Alex Deucher 
Cc: Daniel Vetter 
Cc: David Herrmann 
---
 drivers/gpu/drm/drm_drv.c  |  5 ++---
 drivers/gpu/drm/drm_fops.c | 12 ++--
 include/drm/drmP.h |  3 ++-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index a1863d8..76cdb51 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -198,6 +198,7 @@ int drm_setmaster_ioctl(struct drm_device *dev, void *data,
if (unlikely(ret != 0))
drm_master_put(&file_priv->minor->master);
}
+   file_priv->is_master = ret == 0;

 out_unlock:
mutex_unlock(&dev->master_mutex);
@@ -213,13 +214,11 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void 
*data,
if (!drm_is_master(file_priv))
goto out_unlock;

-   if (!file_priv->minor->master)
-   goto out_unlock;
-
ret = 0;
if (dev->driver->master_drop)
dev->driver->master_drop(dev, file_priv, false);
drm_master_put(&file_priv->minor->master);
+   file_priv->is_master = false;

 out_unlock:
mutex_unlock(&dev->master_mutex);
diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
index c0166ba..083f7b9 100644
--- a/drivers/gpu/drm/drm_fops.c
+++ b/drivers/gpu/drm/drm_fops.c
@@ -196,6 +196,7 @@ static int drm_open_helper(struct file *filp, struct 
drm_minor *minor)

/* take another reference for the copy in the local file priv */
priv->master = drm_master_get(priv->minor->master);
+   priv->is_master = true;
priv->authenticated = 1;

if (dev->driver->master_create) {
@@ -434,12 +435,11 @@ int drm_release(struct inode *inode, struct file *filp)
}
mutex_unlock(&dev->struct_mutex);

-   if (file_priv->minor->master == file_priv->master) {
-   /* drop the reference held my the minor */
-   if (dev->driver->master_drop)
-   dev->driver->master_drop(dev, file_priv, true);
-   drm_master_put(&file_priv->minor->master);
-   }
+   /* drop the reference held my the minor */
+   if (dev->driver->master_drop)
+   dev->driver->master_drop(dev, file_priv, true);
+   drm_master_put(&file_priv->minor->master);
+   file_priv->is_master = false;
}

/* drop the master reference held by the file priv */
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 0ffce5c..70a6598 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -378,6 +378,7 @@ struct drm_prime_file_private {

 /** File private data */
 struct drm_file {
+   bool is_master:1;
unsigned authenticated :1;
/* true when the client has asked us to expose stereo 3D mode flags */
unsigned stereo_allowed :1;
@@ -1177,7 +1178,7 @@ static inline bool drm_is_primary_client(const struct 
drm_file *file_priv)
  */
 static inline bool drm_is_master(const struct drm_file *file)
 {
-   return file->master && file->master == file->minor->master;
+   return file->is_master;
 }

 /**/
-- 
1.9.1



[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Inki Dae
On 2014? 08? 07? 20:09, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 07:49:03PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 18:09, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote:
 On 2014? 08? 07? 15:58, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
>> 2014-08-06 16:43 GMT+09:00 Thierry Reding :
>>> [...]
>>> As far as I can tell non-continuous mode simply means that the host can
>>> turn off the HS clock after a high-speed transmission. I think Andrzej
>>> mentioned this already in another subthread, but this is an optional
>>> mode that peripherals can support if they have extra circuitry that
>>> provides an internal clock. Peripherals that don't have such circuitry
>>> may rely on the HS clock to perform in between transmissions and
>>> therefore require the HS clock to be always on (continuous mode). That's
>>> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
>>> peripheral supports non-continuous mode and therefore the host can turn
>>> the HS clock off after high-speed transmissions.
>>
>> What I don't make sure is this sentence. With
>> MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
>> One is,
>> 1. host controller will generates signals if a bit of a register
>> related to non-contiguous clock mode is set or unset.
>> 2. And then video data is transmitted to panel in HS mode.
>> 3. And then D-PHY detects LP-11 signal (positive and negative lane all
>> are high).
>> 4. And then D-PHY disables HS clock of host controller.
>> 5. At this time, operation mode of host controller becomes LPM.
>>
>> Other is,
>> 1. host controller will generates signals if a bit of a register
>> related to non-contiguous clock mode is set or unset.
>> 2. And then D-PHY detects LP-11 signal (positive and negative lane all
>> are high).
>> 3. And then video data is transmitted to panel in LPM.
>> 4. At this time, operation mode of host controller becomes LPM.
>>
>> It seems that you says latter case.
>
> No. High speed clock and low power mode are orthogonal. Non-continuous
> mode simply means that the clock lane enters LP-11 between HS
> transmissions (see 5.6 "Clock Management" of the DSI specification).
>

 It seems that clock lane enters LP-11 regardless of HS clock enabled if
 non-continous mode is used. Right?
>>>
>>> No, I think as long as HS clock is enabled the clock lane won't enter
>>> LP-11. Non-continuous mode means that the controller can disable the HS
>>> clock between HS transmissions. So in non-continuous mode the clock lane
>>> can enter LP-11 because the controller disables the HS clock.
>>
>> It makes me a little bit confusing. You said "if HS clock is enabled,
>> the the clock lane won't enter LP-11" But you said again "the clock lane
>> can enter LP-11 because the controller disables the HS clock" What is
>> the meaning?
> 
> It means that if the HS clock is enabled, then the clock lane is not in
> LP-11. When the HS clock stops, then the clock lane enters LP-11.
> 
>>> In continuous mode, then the clock will never be disabled, hence the
>>> clock lane will never enter LP-11.
>>>
 And also it seems that non-continous mode is different from LPM at all
 because with non-continuous mode, command data is transmitted to panel
 in HS mode, but with LPM, command data is transmitted to panel in LP
 mode. Also right?
>>>
>>> No. I think you can send command data to the peripheral in low power
>>> mode in both continuous and non-continuous clock modes.
>>>
 If so, shouldn't the host driver disable HS clock, in case of LP mode,
 before the host driver transmits command data?
>>>
>>> No. If the peripheral doesn't support non-continuous mode, then the HS
>>> clock must never be turned off. On the other hand, if the peripheral
>>> supports non-continuous mode, then the DSI host should automatically
>>> disable the HS clock between high-speed transmissions. That means if a
>>> packet is transmitted in low power mode the DSI host will not be
>>> transmitting in high-speed mode and therefore disable the HS clock.
>>
>> What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
>> for LPM transfer, lanes should be LP-11 state and also HS clock of the
>> host controller should be disabled.
> 
> No. I don't think any transmissions can happen when all lanes are in
> LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet
> should be transmitted in low power mode (see LP Transmission in 2.1
> "Definitions" of the MIPI DSI specification).
> 

Hm.. I see. I meant,

if (flags & MIPI_DSI_MSG_USE_LPM)
   disable HS clock <- required.

transmit command data <- in LPM.

Thanks,
Inki Dae

> For low power transmissions, only data lane 0 is used (with a clock
> embedded in the signal), therefore th

i915 kernel warning

2014-08-07 Thread Mihai Donțu
On Wed, 6 Aug 2014 22:29:54 +0200 Daniel Vetter wrote:
> On Wed, Aug 06, 2014 at 10:03:46PM +0300, Mihai Don?u wrote:
> > Hi,
> > 
> > This just happened to me:
> > 
> > Aug  6 21:37:37 mdontu-l kernel: [ cut here ]
> > Aug  6 21:37:37 mdontu-l kernel: WARNING: CPU: 3 PID: 4823 at 
> > drivers/gpu/drm/i915/intel_display.c:3313 
> > intel_crtc_wait_for_pending_flips+0x16c/0x180()
> > Aug  6 21:37:37 mdontu-l kernel: Modules linked in: hdaps(O) tp_smapi(O) 
> > thinkpad_ec(O) vboxnetadp(O) vboxnetflt(O) vboxdrv(O) iwldvm iwlwifi e1000e
> > Aug  6 21:37:37 mdontu-l kernel: CPU: 3 PID: 4823 Comm: X Tainted: G
> >O  3.16.0-gentoo #2
> > Aug  6 21:37:37 mdontu-l kernel: Hardware name: LENOVO 4178A4G/4178A4G, 
> > BIOS 83ET76WW (1.46 ) 07/05/2013
> > Aug  6 21:37:37 mdontu-l kernel:  0009 88041d63fbf8 
> > 93c212a4 
> > Aug  6 21:37:37 mdontu-l kernel:  88041d63fc30 930e3a2d 
> >  880427b7c000
> > Aug  6 21:37:37 mdontu-l kernel:  880426f380a8 880426ddf800 
> > 880426ddf800 88041d63fc40
> > Aug  6 21:37:37 mdontu-l kernel: Call Trace:
> > Aug  6 21:37:37 mdontu-l kernel:  [] dump_stack+0x45/0x56
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > warn_slowpath_common+0x7d/0xa0
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > warn_slowpath_null+0x1a/0x20
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > intel_crtc_wait_for_pending_flips+0x16c/0x180
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > __wake_up_sync+0x20/0x20
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > intel_crtc_disable_planes+0x33/0x1c0
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > ironlake_crtc_disable+0x50/0x970
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > drm_modeset_lock+0x2f/0xd0
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > mutex_lock+0x12/0x30
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > intel_crtc_update_dpms+0x6f/0xa0
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > intel_connector_dpms+0x59/0x70
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > drm_mode_obj_set_property_ioctl+0x399/0x3a0
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > drm_mode_connector_property_set_ioctl+0x30/0x40
> > Aug  6 21:37:37 mdontu-l kernel:  [] drm_ioctl+0x1df/0x680
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > backlight_generate_event+0x5c/0x80
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > brightness_store+0x91/0xd0
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > fsnotify+0x27c/0x350
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > do_vfs_ioctl+0x2c8/0x490
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > __sb_end_write+0x31/0x60
> > Aug  6 21:37:37 mdontu-l kernel:  [] ? 
> > vfs_write+0x1c2/0x200
> > Aug  6 21:37:37 mdontu-l kernel:  [] SyS_ioctl+0x41/0x80
> > Aug  6 21:37:37 mdontu-l kernel:  [] 
> > system_call_fastpath+0x16/0x1b
> > Aug  6 21:37:37 mdontu-l kernel: ---[ end trace 131b19886670715a ]---
> 
> If you can reproduce this somehow, please boot with drm.debug=0xe and
> attach the complete dmesg up to the WARNING. We seem to loose track of
> pageflips under obscure circumstances sometimes. We have more band-aids
> queued up, but fixing the underlying issue would be better ofc.

I don't know how to reproduce it, but I've added the option to my
kernel command line. It does not seem to introduce any noticeable
performance degradation so I'll keep it on until the issue reappears.

Thanks,

> > X appeared to have stopped rendering (or nothing goes through), but the
> > applications worked fine (I still had sound from a video). My video
> > card is:
> > 
> > 00:02.0 VGA compatible controller: Intel Corporation 2nd Generation Core 
> > Processor Family Integrated Graphics Controller (rev 09) (prog-if 00 [VGA 
> > controller])
> > Subsystem: Lenovo Device 21d0
> > Flags: bus master, fast devsel, latency 0, IRQ 43
> > Memory at f140 (64-bit, non-prefetchable) [size=4M]
> > Memory at e000 (64-bit, prefetchable) [size=256M]
> > I/O ports at 6000 [size=64]
> > Expansion ROM at  [disabled]
> > Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit-
> > Capabilities: [d0] Power Management version 2
> > Capabilities: [a4] PCI Advanced Features
> > Kernel driver in use: i915
> > 
> > I was able to switch to the terminal and reboot.
> > 
> > I suspect this is new in 3.16 and I've noticed some other oddities
> > since I upgraded from 3.15.8:
> >  * when adjusting the screen brightness, the minimum setting is now
> >"LCD off";
> >  * when watching a video in fullscreen, I can see a flicker every 10s
> >or so.

-- 
Mihai Don?u


[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Thierry Reding
HS mode, but with LPM, command data is transmitted to panel in LP
> >>>> mode. Also right?
> >>>
> >>> No. I think you can send command data to the peripheral in low power
> >>> mode in both continuous and non-continuous clock modes.
> >>>
> >>>> If so, shouldn't the host driver disable HS clock, in case of LP mode,
> >>>> before the host driver transmits command data?
> >>>
> >>> No. If the peripheral doesn't support non-continuous mode, then the HS
> >>> clock must never be turned off. On the other hand, if the peripheral
> >>> supports non-continuous mode, then the DSI host should automatically
> >>> disable the HS clock between high-speed transmissions. That means if a
> >>> packet is transmitted in low power mode the DSI host will not be
> >>> transmitting in high-speed mode and therefore disable the HS clock.
> >>
> >> What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
> >> for LPM transfer, lanes should be LP-11 state and also HS clock of the
> >> host controller should be disabled.
> >
> > No. I don't think any transmissions can happen when all lanes are in
> > LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet
> > should be transmitted in low power mode (see LP Transmission in 2.1
> > "Definitions" of the MIPI DSI specification).
> >
> 
> Hm.. I see. I meant,
> 
> if (flags & MIPI_DSI_MSG_USE_LPM)
>disable HS clock <- required.
> 
> transmit command data <- in LPM.

No. Disabling the HS clock is not required for LPM mode. In fact if the
peripheral specifies that it doesn't support non-continuous mode then
the HS clock must *never* be disabled as long as the peripheral is in
use.

MIPI_DSI_MSG_USE_LPM and MIPI_DSI_CLOCK_NON_CONTINUOUS are unrelated and
need to be considered separately.

Thierry
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[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #11 from Alex Deucher  ---
(In reply to LiNuxXer from comment #10)
> 
> 3) One question remains -- can't bapm enabling become at least a parameter?
> Or is it already?

Yes, I can add a module parameter to force it on.

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[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #12 from Alex Deucher  ---
Created attachment 145411
  --> https://bugzilla.kernel.org/attachment.cgi?id=145411&action=edit
add a bapm module parameter

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[PATCH] drm/radeon: add bapm module parameter

2014-08-07 Thread Alex Deucher
Add a module paramter to enable bapm on APUs.  It's disabled
by default on certain APUs due to stability issues.  This
option makes it easier to test and to enable it on systems that
are stable.

bug:
https://bugzilla.kernel.org/show_bug.cgi?id=81021

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/kv_dpm.c  |  5 -
 drivers/gpu/drm/radeon/radeon.h  |  1 +
 drivers/gpu/drm/radeon/radeon_drv.c  |  4 
 drivers/gpu/drm/radeon/trinity_dpm.c | 24 +++-
 4 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index 9ef8c38..c667d83 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -2726,7 +2726,10 @@ int kv_dpm_init(struct radeon_device *rdev)
pi->caps_sclk_ds = true;
pi->enable_auto_thermal_throttling = true;
pi->disable_nb_ps3_in_battery = false;
-   pi->bapm_enable = true;
+   if (radeon_bapm == 0)
+   pi->bapm_enable = false;
+   else
+   pi->bapm_enable = true;
pi->voltage_drop_t = 0;
pi->caps_sclk_throttle_low_notification = false;
pi->caps_fps = false; /* true? */
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 511191f..ef8b23d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -106,6 +106,7 @@ extern int radeon_vm_size;
 extern int radeon_vm_block_size;
 extern int radeon_deep_color;
 extern int radeon_use_pflipirq;
+extern int radeon_bapm;

 /*
  * Copy from radeon_drv.h so we don't have to include both and have conflicting
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 5b18af9..a410f41 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -182,6 +182,7 @@ int radeon_vm_size = 8;
 int radeon_vm_block_size = -1;
 int radeon_deep_color = 0;
 int radeon_use_pflipirq = 2;
+int radeon_bapm = -1;

 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -261,6 +262,9 @@ module_param_named(deep_color, radeon_deep_color, int, 
0444);
 MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = 
disable, 1 = as fallback, 2 = exclusive (default))");
 module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);

+MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
+module_param_named(bapm, radeon_bapm, int, 0444);
+
 static struct pci_device_id pciidlist[] = {
radeon_PCI_IDS
 };
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c 
b/drivers/gpu/drm/radeon/trinity_dpm.c
index 32e50be..57f7800 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -1874,16 +1874,22 @@ int trinity_dpm_init(struct radeon_device *rdev)
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
pi->at[i] = TRINITY_AT_DFLT;

-   /* There are stability issues reported on with
-* bapm enabled when switching between AC and battery
-* power.  At the same time, some MSI boards hang
-* if it's not enabled and dpm is enabled.  Just enable
-* it for MSI boards right now.
-*/
-   if (rdev->pdev->subsystem_vendor == 0x1462)
-   pi->enable_bapm = true;
-   else
+   if (radeon_bapm == -1) {
+   /* There are stability issues reported on with
+* bapm enabled when switching between AC and battery
+* power.  At the same time, some MSI boards hang
+* if it's not enabled and dpm is enabled.  Just enable
+* it for MSI boards right now.
+*/
+   if (rdev->pdev->subsystem_vendor == 0x1462)
+   pi->enable_bapm = true;
+   else
+   pi->enable_bapm = false;
+   } else if (radeon_bapm == 0) {
pi->enable_bapm = false;
+   } else {
+   pi->enable_bapm = true;
+   }
pi->enable_nbps_policy = true;
pi->enable_sclk_ds = true;
pi->enable_gfx_power_gating = true;
-- 
1.8.3.1



[Bug 82162] Syslog flooded by [drm:radeon_gem_object_create] errors

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82162

--- Comment #20 from sarnex  ---
(In reply to comment #19)
> Could you please set a breakpoint in si_texture_get_cmask_info and print:
> 
> rscreen->tiling_info AND rscreen->info
> 
> OR
> 
> pipe_interleave_bytes AND num_pipes
> 
> Thanks.

Hi Marek, 

As I said earlier I don't know what I'm doing with GDB.I set the breakpoint
with "b si_texture_get_cmask_info", please let me know if that is wrong.

Here is the output from all of those:

(gdb) p rscreen->tiling_info
value has been optimized out
(gdb) p rscreen->info
value has been optimized out


(gdb) p pipe_interleave_bytes
$1 = 256
(gdb) p num_pipes
$2 = 12

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[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Inki Dae
On 2014? 08? 07? 22:17, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 10:05:44PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 20:09, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 07:49:03PM +0900, Inki Dae wrote:
 On 2014? 08? 07? 18:09, Thierry Reding wrote:
> On Thu, Aug 07, 2014 at 04:51:18PM +0900, Inki Dae wrote:
>> On 2014? 08? 07? 15:58, Thierry Reding wrote:
>>> On Thu, Aug 07, 2014 at 02:09:19AM +0900, Inki Dae wrote:
 2014-08-06 16:43 GMT+09:00 Thierry Reding >>> gmail.com>:
> [...]
> As far as I can tell non-continuous mode simply means that the host 
> can
> turn off the HS clock after a high-speed transmission. I think Andrzej
> mentioned this already in another subthread, but this is an optional
> mode that peripherals can support if they have extra circuitry that
> provides an internal clock. Peripherals that don't have such circuitry
> may rely on the HS clock to perform in between transmissions and
> therefore require the HS clock to be always on (continuous mode). 
> That's
> what the MIPI_DSI_CLOCK_NON_CONTINUOUS flag is: it advertises that the
> peripheral supports non-continuous mode and therefore the host can 
> turn
> the HS clock off after high-speed transmissions.

 What I don't make sure is this sentence. With
 MIPI_DSI_CLOCK_NON_CONTIUOUS flag, I guess two possible operations.
 One is,
 1. host controller will generates signals if a bit of a register
 related to non-contiguous clock mode is set or unset.
 2. And then video data is transmitted to panel in HS mode.
 3. And then D-PHY detects LP-11 signal (positive and negative lane all
 are high).
 4. And then D-PHY disables HS clock of host controller.
 5. At this time, operation mode of host controller becomes LPM.

 Other is,
 1. host controller will generates signals if a bit of a register
 related to non-contiguous clock mode is set or unset.
 2. And then D-PHY detects LP-11 signal (positive and negative lane all
 are high).
 3. And then video data is transmitted to panel in LPM.
 4. At this time, operation mode of host controller becomes LPM.

 It seems that you says latter case.
>>>
>>> No. High speed clock and low power mode are orthogonal. Non-continuous
>>> mode simply means that the clock lane enters LP-11 between HS
>>> transmissions (see 5.6 "Clock Management" of the DSI specification).
>>>
>>
>> It seems that clock lane enters LP-11 regardless of HS clock enabled if
>> non-continous mode is used. Right?
>
> No, I think as long as HS clock is enabled the clock lane won't enter
> LP-11. Non-continuous mode means that the controller can disable the HS
> clock between HS transmissions. So in non-continuous mode the clock lane
> can enter LP-11 because the controller disables the HS clock.

 It makes me a little bit confusing. You said "if HS clock is enabled,
 the the clock lane won't enter LP-11" But you said again "the clock lane
 can enter LP-11 because the controller disables the HS clock" What is
 the meaning?
>>>
>>> It means that if the HS clock is enabled, then the clock lane is not in
>>> LP-11. When the HS clock stops, then the clock lane enters LP-11.
>>>
> In continuous mode, then the clock will never be disabled, hence the
> clock lane will never enter LP-11.
>
>> And also it seems that non-continous mode is different from LPM at all
>> because with non-continuous mode, command data is transmitted to panel
>> in HS mode, but with LPM, command data is transmitted to panel in LP
>> mode. Also right?
>
> No. I think you can send command data to the peripheral in low power
> mode in both continuous and non-continuous clock modes.
>
>> If so, shouldn't the host driver disable HS clock, in case of LP mode,
>> before the host driver transmits command data?
>
> No. If the peripheral doesn't support non-continuous mode, then the HS
> clock must never be turned off. On the other hand, if the peripheral
> supports non-continuous mode, then the DSI host should automatically
> disable the HS clock between high-speed transmissions. That means if a
> packet is transmitted in low power mode the DSI host will not be
> transmitting in high-speed mode and therefore disable the HS clock.

 What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
 for LPM transfer, lanes should be LP-11 state and also HS clock of the
 host controller should be disabled.
>>>
>>> No. I don't think any transmissions can happen when all lanes are in
>>> LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet
>>> should be transmitted in low power mode (s

[Bug 82279] [bisected] double free or corruption on context destruction with postprocessing enabled

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82279

--- Comment #5 from Remco Zoet  ---
I can now confirm that the crash only occurs with postprocessing enabled
through driconf. Apparently, there was still a .drirc present on my /home
partition from an earlier installation that had the 'pp_jimenezmlaa' and
'force_s3tc_enable' options enabled. Resetting .drirc to defaults allows me to
run all SDL applications normally.

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ipu-v3 build fix

2014-08-07 Thread Fabio Estevam
On Thu, Aug 7, 2014 at 7:32 AM, Dave Airlie  wrote:
> does ipu-v3 need to
>
> select GENERIC_IRQ_CHIP
>
> otherwise on my arm test builds I get a failure to link due to missing
> irq symbols.

Which defconfig you use in order to trigger the failure?


[PATCH v2 1/2] drm/mipi-dsi: add (LPM) Low Power Mode transfer support

2014-08-07 Thread Thierry Reding
;if HS clock is enabled,
> >>>> the the clock lane won't enter LP-11" But you said again "the clock lane
> >>>> can enter LP-11 because the controller disables the HS clock" What is
> >>>> the meaning?
> >>>
> >>> It means that if the HS clock is enabled, then the clock lane is not in
> >>> LP-11. When the HS clock stops, then the clock lane enters LP-11.
> >>>
> >>>>> In continuous mode, then the clock will never be disabled, hence the
> >>>>> clock lane will never enter LP-11.
> >>>>>
> >>>>>> And also it seems that non-continous mode is different from LPM at all
> >>>>>> because with non-continuous mode, command data is transmitted to panel
> >>>>>> in HS mode, but with LPM, command data is transmitted to panel in LP
> >>>>>> mode. Also right?
> >>>>>
> >>>>> No. I think you can send command data to the peripheral in low power
> >>>>> mode in both continuous and non-continuous clock modes.
> >>>>>
> >>>>>> If so, shouldn't the host driver disable HS clock, in case of LP mode,
> >>>>>> before the host driver transmits command data?
> >>>>>
> >>>>> No. If the peripheral doesn't support non-continuous mode, then the HS
> >>>>> clock must never be turned off. On the other hand, if the peripheral
> >>>>> supports non-continuous mode, then the DSI host should automatically
> >>>>> disable the HS clock between high-speed transmissions. That means if a
> >>>>> packet is transmitted in low power mode the DSI host will not be
> >>>>> transmitting in high-speed mode and therefore disable the HS clock.
> >>>>
> >>>> What is LPM you think? I thought LPM is LP-11 and HS clock disabled. So
> >>>> for LPM transfer, lanes should be LP-11 state and also HS clock of the
> >>>> host controller should be disabled.
> >>>
> >>> No. I don't think any transmissions can happen when all lanes are in
> >>> LP-11 state. The MIPI_DSI_MSG_USE_LPM is used to specify that a packet
> >>> should be transmitted in low power mode (see LP Transmission in 2.1
> >>> "Definitions" of the MIPI DSI specification).
> >>>
> >>
> >> Hm.. I see. I meant,
> >>
> >> if (flags & MIPI_DSI_MSG_USE_LPM)
> >>disable HS clock <- required.
> >>
> >> transmit command data <- in LPM.
> > 
> > No. Disabling the HS clock is not required for LPM mode. In fact if the
> > peripheral specifies that it doesn't support non-continuous mode then
> > the HS clock must *never* be disabled as long as the peripheral is in
> > use.
> > 
> > MIPI_DSI_MSG_USE_LPM and MIPI_DSI_CLOCK_NON_CONTINUOUS are unrelated and
> > need to be considered separately.
> 
> I mentioned already LPM and NON_CONTINUOUS are unrelated.
> 
> It seems that you say the only way to transfer command data in LPM is
> non-continuous clock mode.

No, that's not what I'm saying.

> However, you said and also the spec says, "Non-continuous mode simply
> means that the clock lane enters LP-11 between HS transmissions".
> Doesn't *between HS transmissions" mean the command data is transmitted
> in HS, *not in LPM*, and clock lane enters LP-11 between them?

Not necessarily. You can transmit command packets in high-speed mode,
but you don't have to. If you transmit packets in low power mode, then
the HS clock isn't involved in the transmission and the clock lane may
enter LP-11 during the whole transmission (if non-continuous mode is
enabled).

> We have one lcd panel, nt35502a, which needs LPM transfer support
> because it should receive some initial commands with LPM by default
> hardware setting, and we faced with that the panel didn't work without
> disabling HS clock before transmitting command data. How can you explain
> that?

The specification clearly says that (5.6.1 "Clock Requirements"):

All DSI transmitters and receivers shall support continuous
clock behavior on the Clock Lane, and optionally may support
non-continuous clock behavior.

So if you need to "disable HS clock" for command data to be successfully
transmitted, either the panel doesn't comply to the specification, or
whatever you do to "disable HS clock" doesn't do what you think it does.

Thierry
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[PATCH] drm/radeon: Always flush VM again on < CIK

2014-08-07 Thread Alex Deucher
On Thu, Aug 7, 2014 at 3:46 AM, Michel D?nzer  wrote:
> From: Michel D?nzer 
>
> Not doing this causes piglit hangs[0] on my Cape Verde card. No issues on
> Bonaire and Kaveri though.
>
> [0] Same symptoms as those fixed on CIK by 'drm/radeon: set VM base addr
> using the PFP v2'.
>
> Signed-off-by: Michel D?nzer 

We should be using PFP as much as possible.  Does the attached patch help?

Alex

> ---
>  drivers/gpu/drm/radeon/radeon_vm.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
> b/drivers/gpu/drm/radeon/radeon_vm.c
> index ccae4d9..898cbb7 100644
> --- a/drivers/gpu/drm/radeon/radeon_vm.c
> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> @@ -238,7 +238,9 @@ void radeon_vm_flush(struct radeon_device *rdev,
> uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
>
> /* if we can't remember our last VM flush then flush now! */
> -   if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
> +   /* XXX figure out why we have to flush all the time before CIK */
> +   if (rdev->family < CHIP_BONAIRE ||
> +   !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
> trace_radeon_vm_flush(pd_addr, ring, vm->id);
> vm->pd_gpu_addr = pd_addr;
> radeon_ring_vm_flush(rdev, ring, vm);
> --
> 2.0.1
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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[Bug 82162] Syslog flooded by [drm:radeon_gem_object_create] errors

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82162

--- Comment #21 from Marek Ol??k  ---
Thanks. The real problem is that num_pipes is 12. That's good to know. I guess
I just need to get the number of pipes from GB_TILE_MODE, because that's what
we need for CMASK and HTILE calculations. That would be P8 or 8 pipes.

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[Bug 82162] Syslog flooded by [drm:radeon_gem_object_create] errors

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82162

--- Comment #22 from sarnex  ---
(In reply to comment #21)
> Thanks. The real problem is that num_pipes is 12. That's good to know. I
> guess I just need to get the number of pipes from GB_TILE_MODE, because
> that's what we need for CMASK and HTILE calculations. That would be P8 or 8
> pipes.

Awesome, any more information you need from me? I can test any fixes.

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[PATCH 2/2] drm/radeon: allow zero sized BOs for fences

2014-08-07 Thread Christian König
From: Christian K?nig 

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/radeon/radeon_drv.c| 3 ++-
 drivers/gpu/drm/radeon/radeon_object.c | 2 +-
 drivers/gpu/drm/radeon/radeon_vm.c | 3 +++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index a773830..f788170 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -84,9 +84,10 @@
  *   2.39.0 - Add INFO query for number of active CUs
  *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
  *CS to GPU
+ *   2.41.0 - Allow zero sized BOs
  */
 #define KMS_DRIVER_MAJOR   2
-#define KMS_DRIVER_MINOR   40
+#define KMS_DRIVER_MINOR   41
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
b/drivers/gpu/drm/radeon/radeon_object.c
index 480c87d..9dd670e 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -154,7 +154,7 @@ int radeon_bo_create(struct radeon_device *rdev,

size = ALIGN(size, PAGE_SIZE);

-   if (kernel) {
+   if (kernel || size == 0) {
type = ttm_bo_type_kernel;
} else if (sg) {
type = ttm_bo_type_sg;
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
b/drivers/gpu/drm/radeon/radeon_vm.c
index ccae4d9..a80f856 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -877,6 +877,9 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
uint32_t flags;
int r;

+   if (bo_va->bo && radeon_bo_size(bo_va->bo) == 0)
+   return 0;
+
if (!bo_va->it.start) {
dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
bo_va->bo, vm);
-- 
1.9.1



[PATCH 1/2] drm/ttm: allow zero sized kernel allocations

2014-08-07 Thread Christian König
From: Christian K?nig 

This patch allows to create zero sized TTM buffer
objects for driver internal use.

Signed-off-by: Christian K?nig 
---
 drivers/gpu/drm/ttm/ttm_bo.c  | 4 ++--
 drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index 3da89d5..0b96a3b 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -309,7 +309,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object 
*bo,
if (ret)
goto out_err;

-   if (mem->mem_type != TTM_PL_SYSTEM) {
+   if (bo->ttm->num_pages && mem->mem_type != TTM_PL_SYSTEM) {
ret = ttm_tt_bind(bo->ttm, mem);
if (ret)
goto out_err;
@@ -1107,7 +1107,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
}

num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
-   if (num_pages == 0) {
+   if (type != ttm_bo_type_kernel && num_pages == 0) {
pr_err("Illegal buffer object size\n");
if (destroy)
(*destroy)(bo);
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c 
b/drivers/gpu/drm/ttm/ttm_bo_util.c
index 30e5d90..8354195 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -63,7 +63,7 @@ int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
if (unlikely(ret != 0))
return ret;

-   if (new_mem->mem_type != TTM_PL_SYSTEM) {
+   if (ttm->num_pages && new_mem->mem_type != TTM_PL_SYSTEM) {
ret = ttm_tt_bind(ttm, new_mem);
if (unlikely(ret != 0))
return ret;
-- 
1.9.1



Any help needed?

2014-08-07 Thread Marco Benatto
Hi all,

I'm Marco Benatto, I've been helping on [PATCH] drm/radeon: Adding UVD
handle basis fps estimation v2 once it has already been sent I'd like to
know if there's any pending task that someone would like help?


Please let me know whether there is some.

Thanks,

-- 
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Linux user ID: #506236
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[PATCH] drm/radeon: Adding UVD handle basis fps estimation v2

2014-08-07 Thread Alex Deucher
On Thu, Aug 7, 2014 at 7:33 AM, Christian K?nig  
wrote:
> From: Marco A Benatto 
>
> Adding a Frames Per Second estimation logic on UVD handles
> when it has being used. This estimation is per handle basis
> and will help on DPM profile calculation.
>
> v2 (chk): fix timestamp type, move functions around and
>   cleanup code a bit.

Will this really help much?  I thought the problem was mainly due to
sclk and mclk for post processing.

Alex

>
> Signed-off-by: Marco A Benatto 
> Signed-off-by: Christian K?nig 
> ---
>  drivers/gpu/drm/radeon/radeon.h | 10 ++
>  drivers/gpu/drm/radeon/radeon_uvd.c | 64 
> +
>  2 files changed, 68 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 9e1732e..e92f6cb 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -1617,6 +1617,15 @@ int radeon_pm_get_type_index(struct radeon_device 
> *rdev,
>  #define RADEON_UVD_STACK_SIZE  (1024*1024)
>  #define RADEON_UVD_HEAP_SIZE   (1024*1024)
>
> +#define RADEON_UVD_FPS_EVENTS_MAX 8
> +#define RADEON_UVD_DEFAULT_FPS 60
> +
> +struct radeon_uvd_fps {
> +   uint64_ttimestamp;
> +   uint8_t event_index;
> +   uint8_t events[RADEON_UVD_FPS_EVENTS_MAX];
> +};
> +
>  struct radeon_uvd {
> struct radeon_bo*vcpu_bo;
> void*cpu_addr;
> @@ -1626,6 +1635,7 @@ struct radeon_uvd {
> struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
> unsignedimg_size[RADEON_MAX_UVD_HANDLES];
> struct delayed_work idle_work;
> +   struct radeon_uvd_fps   fps_info[RADEON_MAX_UVD_HANDLES];
>  };
>
>  int radeon_uvd_init(struct radeon_device *rdev);
> diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c 
> b/drivers/gpu/drm/radeon/radeon_uvd.c
> index 6bf55ec..ef5667a 100644
> --- a/drivers/gpu/drm/radeon/radeon_uvd.c
> +++ b/drivers/gpu/drm/radeon/radeon_uvd.c
> @@ -237,6 +237,51 @@ void radeon_uvd_force_into_uvd_segment(struct radeon_bo 
> *rbo)
> rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
>  }
>
> +static void radeon_uvd_fps_clear_events(struct radeon_device *rdev, int idx)
> +{
> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
> +   unsigned i;
> +
> +   fps->timestamp = jiffies_64;
> +   fps->event_index = 0;
> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++)
> +   fps->events[i] = 0;
> +}
> +
> +static void radeon_uvd_fps_note_event(struct radeon_device *rdev, int idx)
> +{
> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
> +   uint64_t timestamp = jiffies_64;
> +   unsigned rate = 0;
> +
> +   uint8_t index = fps->event_index++;
> +   fps->event_index %= RADEON_UVD_FPS_EVENTS_MAX;
> +
> +   rate = div64_u64(HZ, max(timestamp - fps->timestamp, 1ULL));
> +
> +   fps->timestamp = timestamp;
> +   fps->events[index] = min(rate, 120u);
> +}
> +
> +static unsigned radeon_uvd_estimate_fps(struct radeon_device *rdev, int idx)
> +{
> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
> +   unsigned i, valid = 0, count = 0;
> +
> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++) {
> +   /* We should ignore zero values */
> +   if (fps->events[i] != 0) {
> +   count += fps->events[i];
> +   valid++;
> +   }
> +   }
> +
> +   if (valid > 0)
> +   return count / valid;
> +   else
> +   return RADEON_UVD_DEFAULT_FPS;
> +}
> +
>  void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file 
> *filp)
>  {
> int i, r;
> @@ -419,8 +464,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, 
> struct radeon_bo *bo,
>
> /* create or decode, validate the handle */
> for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
> -   if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
> +   if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
> +   radeon_uvd_fps_note_event(p->rdev, i);
> return 0;
> +   }
> }
>
> /* handle not found try to alloc a new one */
> @@ -428,6 +475,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, 
> struct radeon_bo *bo,
> if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
> p->rdev->uvd.filp[i] = p->filp;
> p->rdev->uvd.img_size[i] = img_size;
> +   radeon_uvd_fps_clear_events(p->rdev, i);
> return 0;
> }
> }
> @@ -763,7 +811,7 @@ int radeon_uvd_get_destroy_msg(struct radeon_device 
> *rdev, int ring,
>  static void radeon_uvd_count_handles(struct radeon_device *rdev,
>  unsigned *sd, unsigned *hd)
>  {
> -   

[Bug 60879] [radeonsi] X11 can't start with acceleration enabled

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=60879

--- Comment #83 from Pali Roh?r  ---
With last version of mesa from git with v2 I'm still getting black screen with
these errors in dmesg:

[   36.661540] radeon :05:00.0: GPU fault detected: 147 0x06625201
[   36.661548] radeon :05:00.0:   VM_CONTEXT1_PROTECTION_FAULT_ADDR  
0x0A4FB8B3
[   36.661551] radeon :05:00.0:   VM_CONTEXT1_PROTECTION_FAULT_STATUS
0x02052001
[   36.661555] VM fault (0x01, vmid 1) at page 172996787, read from CB_CMASK
(82

@Tom Stellard: Can you look at it?

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[PATCH 2/2] drm/radeon: allow zero sized BOs for fences

2014-08-07 Thread Jerome Glisse
On Thu, Aug 07, 2014 at 04:30:33PM +0200, Christian K?nig wrote:
> From: Christian K?nig 


Can we get proper change log with motivation for doing that, use case,
why it can not be done any other ways ...

Change log is invaluable information and empty change log is the worst
thing ever.

> 
> Signed-off-by: Christian K?nig 
> ---
>  drivers/gpu/drm/radeon/radeon_drv.c| 3 ++-
>  drivers/gpu/drm/radeon/radeon_object.c | 2 +-
>  drivers/gpu/drm/radeon/radeon_vm.c | 3 +++
>  3 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a773830..f788170 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -84,9 +84,10 @@
>   *   2.39.0 - Add INFO query for number of active CUs
>   *   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
>   *CS to GPU
> + *   2.41.0 - Allow zero sized BOs
>   */
>  #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 40
> +#define KMS_DRIVER_MINOR 41
>  #define KMS_DRIVER_PATCHLEVEL0
>  int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
>  int radeon_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
> b/drivers/gpu/drm/radeon/radeon_object.c
> index 480c87d..9dd670e 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -154,7 +154,7 @@ int radeon_bo_create(struct radeon_device *rdev,
>  
>   size = ALIGN(size, PAGE_SIZE);
>  
> - if (kernel) {
> + if (kernel || size == 0) {
>   type = ttm_bo_type_kernel;
>   } else if (sg) {
>   type = ttm_bo_type_sg;
> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
> b/drivers/gpu/drm/radeon/radeon_vm.c
> index ccae4d9..a80f856 100644
> --- a/drivers/gpu/drm/radeon/radeon_vm.c
> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> @@ -877,6 +877,9 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
>   uint32_t flags;
>   int r;
>  
> + if (bo_va->bo && radeon_bo_size(bo_va->bo) == 0)
> + return 0;
> +
>   if (!bo_va->it.start) {
>   dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
>   bo_va->bo, vm);
> -- 
> 1.9.1
> 
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> http://lists.freedesktop.org/mailman/listinfo/dri-devel


[PATCH] drm/panel/simple: add optronics B101XTN01.0

2014-08-07 Thread Thierry Reding
On Thu, Aug 07, 2014 at 08:50:22AM -0400, Rob Clark wrote:
> On Thu, Aug 7, 2014 at 3:33 AM, Thierry Reding  
> wrote:
> > On Wed, Aug 06, 2014 at 04:31:30PM -0400, Rob Clark wrote:
> >> LVDS panel, make/model described as:
> >>
> >> AU Optronics Corporation - B101XTN01.0 (H/W:0A)
> >>
> >> See:
> >> http://www.encore-electronic.com/media/B101XTN01.0.pdf
> >
> > I've made it a custom to mention which board a panel is used on in the
> > commit message and I've requested others to do the same. The idea was
> > that it would give some kind of indication where to find the hardware if
> > somebody wanted to test or look at for reference.
> 
> It's just a free-standing panel, which (in this case) can be plugged
> to an ifc6410 (and I think various other inforce boards..) looks like
> a standard(ish) 41 pin connector.

Well, it certainly doesn't have to be exclusively used on a board. I
guess if it isn't shipped with the IFC6410 as standard, maybe you could
simply mention that it's been tested on an IFC6410.

What I like to avoid is that people submit panel patches that are not
tested on real hardware.

> >> Signed-off-by: Rob Clark 
> >> ---
> >>  drivers/gpu/drm/panel/panel-simple.c | 27 +++
> >>  1 file changed, 27 insertions(+)
> >
> > This is missing device tree binding documentation.
> 
> there is nothing new, so I assume you just mean adding the compatible
> string to a list?

There's no such list. You should add a new file, named after the
compatible string and stick it along with all the others into
Documentation/devicetree/bindings/panel. You can simply use one of the
other bindings that are derived from simple-panel as template and adjust
for the panel-specifics. There are a couple from AUO in that directory
already, so it should be easy.

> >>  static const struct of_device_id platform_of_match[] = {
> >>   {
> >>   .compatible = "auo,b101aw03",
> >> @@ -476,6 +499,10 @@ static const struct of_device_id platform_of_match[] 
> >> = {
> >>   .compatible = "samsung,ltn101nt05",
> >>   .data = &samsung_ltn101nt05,
> >>   }, {
> >> + .compatible = "optronics,b101xtn01",
> >
> > From the commit message this panel is from AU Optronics, so it should
> > use the auo vendor prefix.
> 
> so, "auo,b101xtn01" works for everyone?

Yeah, that's consistent with the other ones from AUO, so looking good to
me.

Thierry
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[PATCH 3/3] drm: Use vblank_disable_and_save in drm_vblank_cleanup()

2014-08-07 Thread Mario Kleiner
On 08/07/2014 08:50 AM, Daniel Vetter wrote:
> On Thu, Aug 7, 2014 at 2:50 AM, Mario Kleiner
>  wrote:
>> I'm not sure about all the new embedded drivers, if they have hw vblank
>> counters?
> Quick grep says a lot don't have it or at least not implemented - they
> use drm_vblank_count. Thinking about this, should we use that as a
> signal to also set dev->vblnka_disable_allowed = false in
> drm_vblank_init?
> -Daniel

dev->vblank_disable_allowed = false; is already the default set in 
drm_vblank_init().
I think it was the idea of that flag that drivers which support a somewhat 
correct vblank dis/enable (= have useable hw vblank counters) opt-in to the 
vblank disable after some idle time by setting it to true.

The strange thing is that unconditional dev->vblank_disable_allowed = 
true in drm_vblank_post_modeset()?
It's there since the first introduction of the flag.

The i915, gma500, armada and exynos drivers explicitely set the flag to 
true to opt-in to the auto vblank disable. radeon gets it implicitely 
set by calling the vblank_post_modeset function. Tegra also gets it via 
the post_modeset, and nouveau on old cards with nv04 display engine.

armada, exynos and tegra don't have proper hw vblank counter queries, 
but opt-in, so those will lose vblank counts whenever vblank irqs get 
turned off.

It's a bit all over the place.
-mario



[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #13 from LiNuxXer  ---
(In reply to Alex Deucher from comment #11)
> Yes, I can add a module parameter to force it on.

That's great news, thank you! I was beginning to think that I'd have to compile
my kernel from now on.

BTW, I noticed that /sys/kernel/debug/dri/0/radeon_pm_info will report "power
level 1" when /sys/devices/system/cpu/cpufreq/boost is set to 0 (with bapm
patch, didn't test the unpatched version), while it always reported "power
level 0" in my console scenario under all other circumstances. Since I could
not notice any difference in power consumption, I was wondering what this
actually means.

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[Bug 81021] AMD CPUs w/ Integrated Graphics (APUs) And Turbo Core Only Boost If "fglrx" Module Is Loaded

2014-08-07 Thread bugzilla-dae...@bugzilla.kernel.org
https://bugzilla.kernel.org/show_bug.cgi?id=81021

--- Comment #14 from Alex Deucher  ---
The information in radeon_pm_info represents the current GPU power state.  It
will vary dynamically with GPU load.  E.g., if you are rendering stuff on your
desktop, the GPU clocks and voltages will ramp up/down on demand.  In the
console without X running, there is no GPU engine load so the clocks stay low. 
Note that display requirements can also influence the GPU power state.  E.g.,
if you have a large display that requires higher display clocks, the GPU may
have to boost the power state to accomodate the higher voltage requirements of
the display.

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[patch] drm/radeon: add a check for allocation failure

2014-08-07 Thread Dan Carpenter
We can easily return -ENOMEM here if kzalloc() fails.

Signed-off-by: Dan Carpenter 

diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
b/drivers/gpu/drm/radeon/radeon_vm.c
index ccae4d9..d15d987 100644
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -483,6 +483,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
/* add a clone of the bo_va to clear the old address */
struct radeon_bo_va *tmp;
tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL);
+   if (!tmp)
+   return -ENOMEM;
tmp->it.start = bo_va->it.start;
tmp->it.last = bo_va->it.last;
tmp->vm = vm;


[patch] drm/radeon: add a check for allocation failure

2014-08-07 Thread Alex Deucher
On Thu, Aug 7, 2014 at 11:27 AM, Dan Carpenter  
wrote:
> We can easily return -ENOMEM here if kzalloc() fails.
>
> Signed-off-by: Dan Carpenter 
>
> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
> b/drivers/gpu/drm/radeon/radeon_vm.c
> index ccae4d9..d15d987 100644
> --- a/drivers/gpu/drm/radeon/radeon_vm.c
> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> @@ -483,6 +483,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
> /* add a clone of the bo_va to clear the old address 
> */
> struct radeon_bo_va *tmp;
> tmp = kzalloc(sizeof(struct radeon_bo_va), 
> GFP_KERNEL);
> +   if (!tmp)
> +   return -ENOMEM;

We need to drop the lock here too.  I'll apply and fix it up.  Thanks!

Alex

> tmp->it.start = bo_va->it.start;
> tmp->it.last = bo_va->it.last;
> tmp->vm = vm;
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[PATCH] drm/radeon: Adding UVD handle basis fps estimation v2

2014-08-07 Thread Christian König
Am 07.08.2014 um 16:32 schrieb Alex Deucher:
> On Thu, Aug 7, 2014 at 7:33 AM, Christian K?nig  
> wrote:
>> From: Marco A Benatto 
>>
>> Adding a Frames Per Second estimation logic on UVD handles
>> when it has being used. This estimation is per handle basis
>> and will help on DPM profile calculation.
>>
>> v2 (chk): fix timestamp type, move functions around and
>>cleanup code a bit.
> Will this really help much?  I thought the problem was mainly due to
> sclk and mclk for post processing.

It should at least handle the UVD side for upclocking when you get a lot 
of streams / fps. And at on my NI the patch seems to do exactly that.

Switching sclk and mclk for post processing is a different task, and I 
actually have no idea what to do with them.

Christian.

>
> Alex
>
>> Signed-off-by: Marco A Benatto 
>> Signed-off-by: Christian K?nig 
>> ---
>>   drivers/gpu/drm/radeon/radeon.h | 10 ++
>>   drivers/gpu/drm/radeon/radeon_uvd.c | 64 
>> +
>>   2 files changed, 68 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon.h 
>> b/drivers/gpu/drm/radeon/radeon.h
>> index 9e1732e..e92f6cb 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -1617,6 +1617,15 @@ int radeon_pm_get_type_index(struct radeon_device 
>> *rdev,
>>   #define RADEON_UVD_STACK_SIZE  (1024*1024)
>>   #define RADEON_UVD_HEAP_SIZE   (1024*1024)
>>
>> +#define RADEON_UVD_FPS_EVENTS_MAX 8
>> +#define RADEON_UVD_DEFAULT_FPS 60
>> +
>> +struct radeon_uvd_fps {
>> +   uint64_ttimestamp;
>> +   uint8_t event_index;
>> +   uint8_t events[RADEON_UVD_FPS_EVENTS_MAX];
>> +};
>> +
>>   struct radeon_uvd {
>>  struct radeon_bo*vcpu_bo;
>>  void*cpu_addr;
>> @@ -1626,6 +1635,7 @@ struct radeon_uvd {
>>  struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
>>  unsignedimg_size[RADEON_MAX_UVD_HANDLES];
>>  struct delayed_work idle_work;
>> +   struct radeon_uvd_fps   fps_info[RADEON_MAX_UVD_HANDLES];
>>   };
>>
>>   int radeon_uvd_init(struct radeon_device *rdev);
>> diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c 
>> b/drivers/gpu/drm/radeon/radeon_uvd.c
>> index 6bf55ec..ef5667a 100644
>> --- a/drivers/gpu/drm/radeon/radeon_uvd.c
>> +++ b/drivers/gpu/drm/radeon/radeon_uvd.c
>> @@ -237,6 +237,51 @@ void radeon_uvd_force_into_uvd_segment(struct radeon_bo 
>> *rbo)
>>  rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
>>   }
>>
>> +static void radeon_uvd_fps_clear_events(struct radeon_device *rdev, int idx)
>> +{
>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>> +   unsigned i;
>> +
>> +   fps->timestamp = jiffies_64;
>> +   fps->event_index = 0;
>> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++)
>> +   fps->events[i] = 0;
>> +}
>> +
>> +static void radeon_uvd_fps_note_event(struct radeon_device *rdev, int idx)
>> +{
>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>> +   uint64_t timestamp = jiffies_64;
>> +   unsigned rate = 0;
>> +
>> +   uint8_t index = fps->event_index++;
>> +   fps->event_index %= RADEON_UVD_FPS_EVENTS_MAX;
>> +
>> +   rate = div64_u64(HZ, max(timestamp - fps->timestamp, 1ULL));
>> +
>> +   fps->timestamp = timestamp;
>> +   fps->events[index] = min(rate, 120u);
>> +}
>> +
>> +static unsigned radeon_uvd_estimate_fps(struct radeon_device *rdev, int idx)
>> +{
>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>> +   unsigned i, valid = 0, count = 0;
>> +
>> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++) {
>> +   /* We should ignore zero values */
>> +   if (fps->events[i] != 0) {
>> +   count += fps->events[i];
>> +   valid++;
>> +   }
>> +   }
>> +
>> +   if (valid > 0)
>> +   return count / valid;
>> +   else
>> +   return RADEON_UVD_DEFAULT_FPS;
>> +}
>> +
>>   void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file 
>> *filp)
>>   {
>>  int i, r;
>> @@ -419,8 +464,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser 
>> *p, struct radeon_bo *bo,
>>
>>  /* create or decode, validate the handle */
>>  for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
>> -   if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
>> +   if (atomic_read(&p->rdev->uvd.handles[i]) == handle) {
>> +   radeon_uvd_fps_note_event(p->rdev, i);
>>  return 0;
>> +   }
>>  }
>>
>>  /* handle not found try to alloc a new one */
>> @@ -428,6 +475,7 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, 
>> struct radeon_bo *bo,
>>  if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
>>

[patch] drm/radeon: add a check for allocation failure

2014-08-07 Thread Christian König
I'm 100% sure that I've fixed that as well with a follow up patch. Looks 
like that one didn't made it into 3.17

Christian.

Am 07.08.2014 um 17:31 schrieb Alex Deucher:
> On Thu, Aug 7, 2014 at 11:27 AM, Dan Carpenter  
> wrote:
>> We can easily return -ENOMEM here if kzalloc() fails.
>>
>> Signed-off-by: Dan Carpenter 
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>> b/drivers/gpu/drm/radeon/radeon_vm.c
>> index ccae4d9..d15d987 100644
>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>> @@ -483,6 +483,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
>>  /* add a clone of the bo_va to clear the old 
>> address */
>>  struct radeon_bo_va *tmp;
>>  tmp = kzalloc(sizeof(struct radeon_bo_va), 
>> GFP_KERNEL);
>> +   if (!tmp)
>> +   return -ENOMEM;
> We need to drop the lock here too.  I'll apply and fix it up.  Thanks!
>
> Alex
>
>>  tmp->it.start = bo_va->it.start;
>>  tmp->it.last = bo_va->it.last;
>>  tmp->vm = vm;
>> ___
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>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel



[PATCH] drm/radeon: Always flush VM again on < CIK

2014-08-07 Thread Marek Olšák
So what's difference between WRITE_DATA with PFP vs ME? Would it also
be preferable for DMA_DATA and COPY_DATA?

Marek

On Thu, Aug 7, 2014 at 3:59 PM, Alex Deucher  wrote:
> On Thu, Aug 7, 2014 at 3:46 AM, Michel D?nzer  wrote:
>> From: Michel D?nzer 
>>
>> Not doing this causes piglit hangs[0] on my Cape Verde card. No issues on
>> Bonaire and Kaveri though.
>>
>> [0] Same symptoms as those fixed on CIK by 'drm/radeon: set VM base addr
>> using the PFP v2'.
>>
>> Signed-off-by: Michel D?nzer 
>
> We should be using PFP as much as possible.  Does the attached patch help?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/radeon/radeon_vm.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>> b/drivers/gpu/drm/radeon/radeon_vm.c
>> index ccae4d9..898cbb7 100644
>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>> @@ -238,7 +238,9 @@ void radeon_vm_flush(struct radeon_device *rdev,
>> uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
>>
>> /* if we can't remember our last VM flush then flush now! */
>> -   if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>> +   /* XXX figure out why we have to flush all the time before CIK */
>> +   if (rdev->family < CHIP_BONAIRE ||
>> +   !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>> trace_radeon_vm_flush(pd_addr, ring, vm->id);
>> vm->pd_gpu_addr = pd_addr;
>> radeon_ring_vm_flush(rdev, ring, vm);
>> --
>> 2.0.1
>>
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>
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>


[PATCH] drm/radeon: Always flush VM again on < CIK

2014-08-07 Thread Christian König
The GFX CP is split up into two different engines - the PFP and the ME 
(starting with SI you additionally get the CE as well).

The PFP is responsible for reading commands out of memory and forwarding 
it to the ME (or the CE). Some commands can be executed on the PFP as 
well, like simple register writes, but most commands can only run on the ME.

The PFP and the ME are connected through a 8 entry ring buffer (IIRC), 
so when you do something on the ME the PFP depends on you need to block 
the PFP for the ME to finish it's operation.

It strongly depends on what we want to do if we should use the PFP or 
the ME, but in most cases (like writing to memory) it's only the ME that 
can do the operation anyway.

Regards,
Christian.

Am 07.08.2014 um 17:38 schrieb Marek Ol??k:
> So what's difference between WRITE_DATA with PFP vs ME? Would it also
> be preferable for DMA_DATA and COPY_DATA?
>
> Marek
>
> On Thu, Aug 7, 2014 at 3:59 PM, Alex Deucher  wrote:
>> On Thu, Aug 7, 2014 at 3:46 AM, Michel D?nzer  wrote:
>>> From: Michel D?nzer 
>>>
>>> Not doing this causes piglit hangs[0] on my Cape Verde card. No issues on
>>> Bonaire and Kaveri though.
>>>
>>> [0] Same symptoms as those fixed on CIK by 'drm/radeon: set VM base addr
>>> using the PFP v2'.
>>>
>>> Signed-off-by: Michel D?nzer 
>> We should be using PFP as much as possible.  Does the attached patch help?
>>
>> Alex
>>
>>> ---
>>>   drivers/gpu/drm/radeon/radeon_vm.c | 4 +++-
>>>   1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>>> b/drivers/gpu/drm/radeon/radeon_vm.c
>>> index ccae4d9..898cbb7 100644
>>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>>> @@ -238,7 +238,9 @@ void radeon_vm_flush(struct radeon_device *rdev,
>>>  uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
>>>
>>>  /* if we can't remember our last VM flush then flush now! */
>>> -   if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>>> +   /* XXX figure out why we have to flush all the time before CIK */
>>> +   if (rdev->family < CHIP_BONAIRE ||
>>> +   !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>>>  trace_radeon_vm_flush(pd_addr, ring, vm->id);
>>>  vm->pd_gpu_addr = pd_addr;
>>>  radeon_ring_vm_flush(rdev, ring, vm);
>>> --
>>> 2.0.1
>>>
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[PATCH 2/2] drm/radeon: allow zero sized BOs for fences

2014-08-07 Thread Christian König
Am 07.08.2014 um 17:01 schrieb Jerome Glisse:
> On Thu, Aug 07, 2014 at 04:30:33PM +0200, Christian K?nig wrote:
>> From: Christian K?nig 
>
> Can we get proper change log with motivation for doing that, use case,
> why it can not be done any other ways ...
>
> Change log is invaluable information and empty change log is the worst
> thing ever.

Yeah, sorry. Actually wanted to send out only the first one to get an 
opinion on that before proceeding.

Going to add a proper commit message,
Christian.

>
>> Signed-off-by: Christian K?nig 
>> ---
>>   drivers/gpu/drm/radeon/radeon_drv.c| 3 ++-
>>   drivers/gpu/drm/radeon/radeon_object.c | 2 +-
>>   drivers/gpu/drm/radeon/radeon_vm.c | 3 +++
>>   3 files changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
>> b/drivers/gpu/drm/radeon/radeon_drv.c
>> index a773830..f788170 100644
>> --- a/drivers/gpu/drm/radeon/radeon_drv.c
>> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
>> @@ -84,9 +84,10 @@
>>*   2.39.0 - Add INFO query for number of active CUs
>>*   2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
>>*CS to GPU
>> + *   2.41.0 - Allow zero sized BOs
>>*/
>>   #define KMS_DRIVER_MAJOR   2
>> -#define KMS_DRIVER_MINOR40
>> +#define KMS_DRIVER_MINOR41
>>   #define KMS_DRIVER_PATCHLEVEL  0
>>   int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
>>   int radeon_driver_unload_kms(struct drm_device *dev);
>> diff --git a/drivers/gpu/drm/radeon/radeon_object.c 
>> b/drivers/gpu/drm/radeon/radeon_object.c
>> index 480c87d..9dd670e 100644
>> --- a/drivers/gpu/drm/radeon/radeon_object.c
>> +++ b/drivers/gpu/drm/radeon/radeon_object.c
>> @@ -154,7 +154,7 @@ int radeon_bo_create(struct radeon_device *rdev,
>>   
>>  size = ALIGN(size, PAGE_SIZE);
>>   
>> -if (kernel) {
>> +if (kernel || size == 0) {
>>  type = ttm_bo_type_kernel;
>>  } else if (sg) {
>>  type = ttm_bo_type_sg;
>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>> b/drivers/gpu/drm/radeon/radeon_vm.c
>> index ccae4d9..a80f856 100644
>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>> @@ -877,6 +877,9 @@ int radeon_vm_bo_update(struct radeon_device *rdev,
>>  uint32_t flags;
>>  int r;
>>   
>> +if (bo_va->bo && radeon_bo_size(bo_va->bo) == 0)
>> +return 0;
>> +
>>  if (!bo_va->it.start) {
>>  dev_err(rdev->dev, "bo %p don't has a mapping in vm %p\n",
>>  bo_va->bo, vm);
>> -- 
>> 1.9.1
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel



[PATCH] drm/radeon: Always flush VM again on < CIK

2014-08-07 Thread Alex Deucher
On Thu, Aug 7, 2014 at 11:38 AM, Marek Ol??k  wrote:
> So what's difference between WRITE_DATA with PFP vs ME? Would it also
> be preferable for DMA_DATA and COPY_DATA?

The PFP comes before the ME in the pipeline.  Note that there is no
PFP (or CE) on the compute queues so we can't use PFP (or CE) for
compute.  According to the internal gfx teams, we should use PFP
whenever possible since the PFP is rarely as busy as the ME.  Note
also that the engine bit is not always consistent (for some packets 0
= ME, 1 = PFP and for others 1= ME and 0 = PFP).

Alex

>
> Marek
>
> On Thu, Aug 7, 2014 at 3:59 PM, Alex Deucher  wrote:
>> On Thu, Aug 7, 2014 at 3:46 AM, Michel D?nzer  wrote:
>>> From: Michel D?nzer 
>>>
>>> Not doing this causes piglit hangs[0] on my Cape Verde card. No issues on
>>> Bonaire and Kaveri though.
>>>
>>> [0] Same symptoms as those fixed on CIK by 'drm/radeon: set VM base addr
>>> using the PFP v2'.
>>>
>>> Signed-off-by: Michel D?nzer 
>>
>> We should be using PFP as much as possible.  Does the attached patch help?
>>
>> Alex
>>
>>> ---
>>>  drivers/gpu/drm/radeon/radeon_vm.c | 4 +++-
>>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
>>> b/drivers/gpu/drm/radeon/radeon_vm.c
>>> index ccae4d9..898cbb7 100644
>>> --- a/drivers/gpu/drm/radeon/radeon_vm.c
>>> +++ b/drivers/gpu/drm/radeon/radeon_vm.c
>>> @@ -238,7 +238,9 @@ void radeon_vm_flush(struct radeon_device *rdev,
>>> uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
>>>
>>> /* if we can't remember our last VM flush then flush now! */
>>> -   if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>>> +   /* XXX figure out why we have to flush all the time before CIK */
>>> +   if (rdev->family < CHIP_BONAIRE ||
>>> +   !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
>>> trace_radeon_vm_flush(pd_addr, ring, vm->id);
>>> vm->pd_gpu_addr = pd_addr;
>>> radeon_ring_vm_flush(rdev, ring, vm);
>>> --
>>> 2.0.1
>>>
>>> ___
>>> dri-devel mailing list
>>> dri-devel at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>>
>> ___
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
>>


[patch] drm/radeon: add a check for allocation failure

2014-08-07 Thread Dan Carpenter
On Thu, Aug 07, 2014 at 11:31:15AM -0400, Alex Deucher wrote:
> On Thu, Aug 7, 2014 at 11:27 AM, Dan Carpenter  
> wrote:
> > We can easily return -ENOMEM here if kzalloc() fails.
> >
> > Signed-off-by: Dan Carpenter 
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_vm.c 
> > b/drivers/gpu/drm/radeon/radeon_vm.c
> > index ccae4d9..d15d987 100644
> > --- a/drivers/gpu/drm/radeon/radeon_vm.c
> > +++ b/drivers/gpu/drm/radeon/radeon_vm.c
> > @@ -483,6 +483,8 @@ int radeon_vm_bo_set_addr(struct radeon_device *rdev,
> > /* add a clone of the bo_va to clear the old 
> > address */
> > struct radeon_bo_va *tmp;
> > tmp = kzalloc(sizeof(struct radeon_bo_va), 
> > GFP_KERNEL);
> > +   if (!tmp)
> > +   return -ENOMEM;
> 
> We need to drop the lock here too.  I'll apply and fix it up.  Thanks!
> 

Gar.  I'm sorry.  I thought it looked easier than it was.

Also I really should have caught that in my qc.  :/  I'm not sure what
happened.

regards,
dan carpenter



[PATCH] drm: Restore drm_file->is_master

2014-08-07 Thread David Herrmann
Hi

On Thu, Aug 7, 2014 at 3:04 PM, Chris Wilson  
wrote:
> Despite the claims of
>
> commit 48ba813701eb14b3008edefef4a0789b328e278c
> Author: David Herrmann 
> Date:   Tue Jul 22 18:46:09 2014 +0200
>
> drm: drop redundant drm_file->is_master
>
> drm_file->is_master is not synomous with having drm_file->master ==
> drm_file->minor->master. This is because drm_file->master is the same
> for all drm_files of the same generation and so when there is a master,
> every drm_file believes itself to be the master. Confusion ensues and
> things go pear shaped when one file is closed and there is no master
> anymore.

Uagh, embarrassing. A revert is fine with me, but I'll try to review
your patch once I get home.

Thanks
David

> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82283
> Signed-off-by: Chris Wilson 
> Cc: Alex Deucher 
> Cc: Daniel Vetter 
> Cc: David Herrmann 
> ---
>  drivers/gpu/drm/drm_drv.c  |  5 ++---
>  drivers/gpu/drm/drm_fops.c | 12 ++--
>  include/drm/drmP.h |  3 ++-
>  3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
> index a1863d8..76cdb51 100644
> --- a/drivers/gpu/drm/drm_drv.c
> +++ b/drivers/gpu/drm/drm_drv.c
> @@ -198,6 +198,7 @@ int drm_setmaster_ioctl(struct drm_device *dev, void 
> *data,
> if (unlikely(ret != 0))
> drm_master_put(&file_priv->minor->master);
> }
> +   file_priv->is_master = ret == 0;
>
>  out_unlock:
> mutex_unlock(&dev->master_mutex);
> @@ -213,13 +214,11 @@ int drm_dropmaster_ioctl(struct drm_device *dev, void 
> *data,
> if (!drm_is_master(file_priv))
> goto out_unlock;
>
> -   if (!file_priv->minor->master)
> -   goto out_unlock;
> -
> ret = 0;
> if (dev->driver->master_drop)
> dev->driver->master_drop(dev, file_priv, false);
> drm_master_put(&file_priv->minor->master);
> +   file_priv->is_master = false;
>
>  out_unlock:
> mutex_unlock(&dev->master_mutex);
> diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c
> index c0166ba..083f7b9 100644
> --- a/drivers/gpu/drm/drm_fops.c
> +++ b/drivers/gpu/drm/drm_fops.c
> @@ -196,6 +196,7 @@ static int drm_open_helper(struct file *filp, struct 
> drm_minor *minor)
>
> /* take another reference for the copy in the local file priv 
> */
> priv->master = drm_master_get(priv->minor->master);
> +   priv->is_master = true;
> priv->authenticated = 1;
>
> if (dev->driver->master_create) {
> @@ -434,12 +435,11 @@ int drm_release(struct inode *inode, struct file *filp)
> }
> mutex_unlock(&dev->struct_mutex);
>
> -   if (file_priv->minor->master == file_priv->master) {
> -   /* drop the reference held my the minor */
> -   if (dev->driver->master_drop)
> -   dev->driver->master_drop(dev, file_priv, 
> true);
> -   drm_master_put(&file_priv->minor->master);
> -   }
> +   /* drop the reference held my the minor */
> +   if (dev->driver->master_drop)
> +   dev->driver->master_drop(dev, file_priv, true);
> +   drm_master_put(&file_priv->minor->master);
> +   file_priv->is_master = false;
> }
>
> /* drop the master reference held by the file priv */
> diff --git a/include/drm/drmP.h b/include/drm/drmP.h
> index 0ffce5c..70a6598 100644
> --- a/include/drm/drmP.h
> +++ b/include/drm/drmP.h
> @@ -378,6 +378,7 @@ struct drm_prime_file_private {
>
>  /** File private data */
>  struct drm_file {
> +   bool is_master:1;
> unsigned authenticated :1;
> /* true when the client has asked us to expose stereo 3D mode flags */
> unsigned stereo_allowed :1;
> @@ -1177,7 +1178,7 @@ static inline bool drm_is_primary_client(const struct 
> drm_file *file_priv)
>   */
>  static inline bool drm_is_master(const struct drm_file *file)
>  {
> -   return file->master && file->master == file->minor->master;
> +   return file->is_master;
>  }
>
>  /**/
> --
> 1.9.1
>


[Bug 82162] Syslog flooded by [drm:radeon_gem_object_create] errors

2014-08-07 Thread bugzilla-dae...@freedesktop.org
https://bugs.freedesktop.org/show_bug.cgi?id=82162

--- Comment #23 from mmstickman at gmail.com ---
Would be nice to get a patch out for the stable mesa builds as they are also
affected by this bug.

-- 
You are receiving this mail because:
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[PATCH] drm/radeon: Adding UVD handle basis fps estimation v2

2014-08-07 Thread Alex Deucher
On Thu, Aug 7, 2014 at 11:32 AM, Christian K?nig
 wrote:
> Am 07.08.2014 um 16:32 schrieb Alex Deucher:
>
>> On Thu, Aug 7, 2014 at 7:33 AM, Christian K?nig 
>> wrote:
>>>
>>> From: Marco A Benatto 
>>>
>>> Adding a Frames Per Second estimation logic on UVD handles
>>> when it has being used. This estimation is per handle basis
>>> and will help on DPM profile calculation.
>>>
>>> v2 (chk): fix timestamp type, move functions around and
>>>cleanup code a bit.
>>
>> Will this really help much?  I thought the problem was mainly due to
>> sclk and mclk for post processing.
>
>
> It should at least handle the UVD side for upclocking when you get a lot of
> streams / fps. And at on my NI the patch seems to do exactly that.
>
> Switching sclk and mclk for post processing is a different task, and I
> actually have no idea what to do with them.

At this point we always choose the plain UVD state anyway so this
patch would only take effect if we re-enabled the dynamic UVD state
selection.  For the post processing, we probably need a hint we can
pass to the driver in the CS ioctl to denote what state we need.
Although if we did that, this could would largely be moot.  That said,
newer asics support dynamic UVD clocks so we really only need
something like that for older asics and I guess VCE.

Alex

>
> Christian.
>
>
>>
>> Alex
>>
>>> Signed-off-by: Marco A Benatto 
>>> Signed-off-by: Christian K?nig 
>>> ---
>>>   drivers/gpu/drm/radeon/radeon.h | 10 ++
>>>   drivers/gpu/drm/radeon/radeon_uvd.c | 64
>>> +
>>>   2 files changed, 68 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/radeon.h
>>> b/drivers/gpu/drm/radeon/radeon.h
>>> index 9e1732e..e92f6cb 100644
>>> --- a/drivers/gpu/drm/radeon/radeon.h
>>> +++ b/drivers/gpu/drm/radeon/radeon.h
>>> @@ -1617,6 +1617,15 @@ int radeon_pm_get_type_index(struct radeon_device
>>> *rdev,
>>>   #define RADEON_UVD_STACK_SIZE  (1024*1024)
>>>   #define RADEON_UVD_HEAP_SIZE   (1024*1024)
>>>
>>> +#define RADEON_UVD_FPS_EVENTS_MAX 8
>>> +#define RADEON_UVD_DEFAULT_FPS 60
>>> +
>>> +struct radeon_uvd_fps {
>>> +   uint64_ttimestamp;
>>> +   uint8_t event_index;
>>> +   uint8_t events[RADEON_UVD_FPS_EVENTS_MAX];
>>> +};
>>> +
>>>   struct radeon_uvd {
>>>  struct radeon_bo*vcpu_bo;
>>>  void*cpu_addr;
>>> @@ -1626,6 +1635,7 @@ struct radeon_uvd {
>>>  struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
>>>  unsignedimg_size[RADEON_MAX_UVD_HANDLES];
>>>  struct delayed_work idle_work;
>>> +   struct radeon_uvd_fps   fps_info[RADEON_MAX_UVD_HANDLES];
>>>   };
>>>
>>>   int radeon_uvd_init(struct radeon_device *rdev);
>>> diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
>>> b/drivers/gpu/drm/radeon/radeon_uvd.c
>>> index 6bf55ec..ef5667a 100644
>>> --- a/drivers/gpu/drm/radeon/radeon_uvd.c
>>> +++ b/drivers/gpu/drm/radeon/radeon_uvd.c
>>> @@ -237,6 +237,51 @@ void radeon_uvd_force_into_uvd_segment(struct
>>> radeon_bo *rbo)
>>>  rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
>>>   }
>>>
>>> +static void radeon_uvd_fps_clear_events(struct radeon_device *rdev, int
>>> idx)
>>> +{
>>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>>> +   unsigned i;
>>> +
>>> +   fps->timestamp = jiffies_64;
>>> +   fps->event_index = 0;
>>> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++)
>>> +   fps->events[i] = 0;
>>> +}
>>> +
>>> +static void radeon_uvd_fps_note_event(struct radeon_device *rdev, int
>>> idx)
>>> +{
>>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>>> +   uint64_t timestamp = jiffies_64;
>>> +   unsigned rate = 0;
>>> +
>>> +   uint8_t index = fps->event_index++;
>>> +   fps->event_index %= RADEON_UVD_FPS_EVENTS_MAX;
>>> +
>>> +   rate = div64_u64(HZ, max(timestamp - fps->timestamp, 1ULL));
>>> +
>>> +   fps->timestamp = timestamp;
>>> +   fps->events[index] = min(rate, 120u);
>>> +}
>>> +
>>> +static unsigned radeon_uvd_estimate_fps(struct radeon_device *rdev, int
>>> idx)
>>> +{
>>> +   struct radeon_uvd_fps *fps = &rdev->uvd.fps_info[idx];
>>> +   unsigned i, valid = 0, count = 0;
>>> +
>>> +   for (i = 0; i < RADEON_UVD_FPS_EVENTS_MAX; i++) {
>>> +   /* We should ignore zero values */
>>> +   if (fps->events[i] != 0) {
>>> +   count += fps->events[i];
>>> +   valid++;
>>> +   }
>>> +   }
>>> +
>>> +   if (valid > 0)
>>> +   return count / valid;
>>> +   else
>>> +   return RADEON_UVD_DEFAULT_FPS;
>>> +}
>>> +
>>>   void radeon_uvd_free_handles(struct radeon_device *rdev, struct
>>> drm_file *filp)
>>>   {
>>>  int i, r;
>>> @@ -419,8 +464,10 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser
>>> *p, struct radeon_bo *bo,
>>>
>>>  

[pull] radeon drm-next-3.17

2014-08-07 Thread Alex Deucher
Hi Dave,

Latest version of the userptr stuff after yesterday's discussions.
If you're ok with it, please apply, otherwise, we'll push to 3.18.

The following changes since commit 21d70354bba9965a098382fc4d7fb17e138111f3:

  drm: move drm_stub.c to drm_drv.c (2014-08-06 19:10:44 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-3.17

for you to fetch changes up to 893faf6f6f401135a763062948f979c7747a7b65:

  drm/radeon: allow userptr write access under certain conditions (2014-08-07 
18:00:41 -0400)


Christian K?nig (5):
  drm/radeon: add userptr support v8
  drm/radeon: add userptr flag to limit it to anonymous memory v2
  drm/radeon: add userptr flag to directly validate the BO to GTT
  drm/radeon: add userptr flag to register MMU notifier v3
  drm/radeon: allow userptr write access under certain conditions

 drivers/gpu/drm/Kconfig|   1 +
 drivers/gpu/drm/radeon/Makefile|   2 +-
 drivers/gpu/drm/radeon/radeon.h|  18 +++
 drivers/gpu/drm/radeon/radeon_cs.c |  25 ++-
 drivers/gpu/drm/radeon/radeon_device.c |   2 +
 drivers/gpu/drm/radeon/radeon_drv.c|   5 +-
 drivers/gpu/drm/radeon/radeon_gem.c|  97 
 drivers/gpu/drm/radeon/radeon_kms.c|   1 +
 drivers/gpu/drm/radeon/radeon_mn.c | 272 +
 drivers/gpu/drm/radeon/radeon_object.c |   4 +
 drivers/gpu/drm/radeon/radeon_prime.c  |  10 ++
 drivers/gpu/drm/radeon/radeon_ttm.c| 155 +++
 drivers/gpu/drm/radeon/radeon_vm.c |   3 +
 include/uapi/drm/radeon_drm.h  |  19 +++
 14 files changed, 610 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/radeon/radeon_mn.c


[git pull] drm merge window pull

2014-08-07 Thread Dave Airlie

Hi Linus,

like all good pull reqs this ends with a revert, so it must mean we 
tested it,

This pull is missing nouveau, Ben has been stuck trying to track down a 
very longstanding bug that revealed itself due to some other changes, I've 
asked him to send you a direct pull request for nouveau once he cleans 
things up. I'm away until Monday so don't want to delay things, you can 
make a decision on that when he sends it, I have my phone so I can ack 
things just not really merge much.

It has one trivial conflict with your tree in armada_drv.c, and also the 
pull request contains some component changes that are already in your 
tree, the base tree from Russell went via Greg's tree already, but some 
stuff still shows up in here that doesn't when I merge my tree into yours.

otherwise all pretty standard graphics fare, one new driver and changes 
all over the place.

New drivers: sti kms driver for STMicroelectronics chipsets stih416 and 
stih407.

core:
lots of cleanups to the drm core
DP MST helper code merged
universal cursor planes.
render nodes enabled by default

panel:
better panel interfaces
new panel support
non-continuous cock advertising ability

ttm:
shrinker fixes

i915: 
hopefully ditched UMS support
runtime pm fixes
psr tracking and locking - now enabled by default
userptr fixes
backlight brightness fixes
MST support merged 
runtime PM for dpms
primary planes locking fixes
gen8 hw semaphore support
fbc fixes
runtime PM on SOix sleep state hw.
mmio base page flipping
lots of vlv/chv fixes.
universal cursor planes

radeon:
Hawaii fixes
display scalar support for non-fixed mode displays
new firmware format support
dpm on more asics by default
GPUVM improvements
uncached and wc GTT buffers
BOs > visible VRAM

exynos:
i80 interface support
module auto-loading
ipp driver consolidated.

armada:
irq handling in crtc layer only
crtc renumbering
add component support
DT interaction changes.

tegra:
load as module fixes
eDP bpp and sync polarity fixed
DSI non-continuous clock mode support
better support for importing buffers from nouveau

msm:
mdp5/adq8084 v1.3 hw enablement
devicetree clk changse
ifc6410 board working

tda998x:
component support
DT documentation update

vmwgfx:
fix compat shader namespace

The following changes since commit 19583ca584d6f574384e17fe7613dfaeadcdc4a6:

  Linux 3.16 (2014-08-03 15:25:02 -0700)

are available in the git repository at:

  git://people.freedesktop.org/~airlied/linux drm-next

for you to fetch changes up to 7963e9db1b1f842fdc53309baa8714d38e9f5681:

  Revert "drm: drop redundant drm_file->is_master" (2014-08-08 07:30:53 +1000)


Ajay Kumar (15):
  drm/panel: add .prepare() and .unprepare() functions
  drm/panel: Provide convenience wrapper for .get_modes()
  drm/panel: ld9040: Add dummy prepare and unprepare routines
  drm/panel: s6e8aa0: Add dummy prepare and unprepare routines
  drm/panel: simple: Add dummy prepare and unprepare routines
  drm/exynos: dpi: Add support for panel prepare and unprepare routines
  drm/exynos: dsi: Add support for panel prepare and unprepare routines
  drm/tegra: Add support for panel prepare and unprepare routines
  drm/panel: ld9040: Add proper definition for prepare and unprepare
  drm/panel: s6e8aa0: Add proper definition for prepare and unprepare
  drm/panel: simple: Add proper definition for prepare and unprepare
  drm/panel: simple: Support delays in panel functions
  drm/panel: simple: Add AUO B133HTN01 panel support
  drm/exynos: Move DP setup into commit()
  drm/exynos: dp: Modify driver to support drm_panel

Akash Goel (1):
  drm/i915: Added write-enable pte bit supportt

Alban Bedel (1):
  drm/panel: simple: add support for InnoLux N156BGE-L21 panel

Alban Browaeys (1):
  drm/exynos: g2d: add exynos4212 as a compatible device.

Alex Deucher (25):
  drm/radeon/dpm: add support for SVI2 voltage for SI
  drm/radeon: disable gfx cgcg on cik
  drm/radeon: add new firmware header definitions (v3)
  drm/radeon/si: Add support for new ucode format (v3)
  drm/radeon/cik: Add support for new ucode format (v5)
  drm/radeon: enable display scaling on all connectors (v2)
  drm/radeon: consolidate vga and dvi get_modes functions (v2)
  drm/radeon: restructure edid fetching
  drm/radeon: use a fetch function to get the edid
  drm/radeon: track pinned memory (v2)
  drm/radeon: use vram/gart pinned size in radeon_gem_info_ioctl
  drm/radeon: use vram/gart pinned size in radeon_do_test_move

[PATCH 1/9] drm: Add drm driver for Rockchip Socs

2014-08-07 Thread mark yao
This patch is a DRM Driver for Rockchip Socs, driver provides an abstraction
for the graphics hardware, such as lcd controller and connector interface.

Signed-off-by: mark yao 
---
changes since v1:

Adviced by Daniel Vetter:
- Switch to universal plane API's
---
 drivers/gpu/drm/Kconfig   |2 +
 drivers/gpu/drm/Makefile  |1 +
 drivers/gpu/drm/rockchip/Kconfig  |   40 ++
 drivers/gpu/drm/rockchip/Makefile |   12 +
 drivers/gpu/drm/rockchip/rockchip_drm_connector.c |  412 
 drivers/gpu/drm/rockchip/rockchip_drm_connector.h |   36 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c   |  600 +
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h   |  128 
 drivers/gpu/drm/rockchip/rockchip_drm_fb.c|   48 ++
 drivers/gpu/drm/rockchip/rockchip_drm_fb.h|   28 +
 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c |   63 ++
 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h |   24 +
 drivers/gpu/drm/rockchip/rockchip_drm_gem.c   |  163 +
 drivers/gpu/drm/rockchip/rockchip_drm_gem.h   |   40 ++
 drivers/gpu/drm/rockchip/rockchip_drm_lcdc.c  |  722 +
 drivers/gpu/drm/rockchip/rockchip_drm_lcdc.h  |  131 
 include/uapi/drm/rockchip_drm.h   |  110 
 17 files changed, 2560 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/Kconfig
 create mode 100644 drivers/gpu/drm/rockchip/Makefile
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_connector.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_connector.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_drv.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_drv.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fb.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fb.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_fbdev.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_gem.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_gem.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_lcdc.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_lcdc.h
 create mode 100644 include/uapi/drm/rockchip_drm.h

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f512004..5951c2c 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -170,6 +170,8 @@ config DRM_SAVAGE

 source "drivers/gpu/drm/exynos/Kconfig"

+source "drivers/gpu/drm/rockchip/Kconfig"
+
 source "drivers/gpu/drm/vmwgfx/Kconfig"

 source "drivers/gpu/drm/gma500/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index dd2ba42..40babd2 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/
 obj-$(CONFIG_DRM_VIA)  +=via/
 obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/
 obj-$(CONFIG_DRM_EXYNOS) +=exynos/
+obj-$(CONFIG_DRM_ROCKCHIP) +=rockchip/
 obj-$(CONFIG_DRM_GMA500) += gma500/
 obj-$(CONFIG_DRM_UDL) += udl/
 obj-$(CONFIG_DRM_AST) += ast/
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
new file mode 100644
index 000..592e999
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -0,0 +1,40 @@
+config DRM_ROCKCHIP
+   tristate "DRM Support for Rockchip"
+   depends on DRM
+   select DRM_KMS_HELPER
+   select DRM_KMS_FB_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_GEM_CMA_HELPER
+   select DRM_PANEL
+   select FB_CFB_FILLRECT
+   select FB_CFB_COPYAREA
+   select FB_CFB_IMAGEBLIT
+   select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
+   select VIDEOMODE_HELPERS
+   select OF
+   help
+ Choose this option if you have a Rockchip soc chipset.
+ This driver provides kernel mode setting and buffer
+ management to userspace. This driver does not provides
+ 2D or 3D acceleration; acceleration is performed by other
+ IP found on the SoC.
+
+config DRM_ROCKCHIP_LCDC
+   bool "ROCKCHIP DRM LCDC"
+   depends on DRM_ROCKCHIP
+   select FB_MODE_HELPERS
+   help
+ Choose this option if you want to use Rockchip lcdc for DRM.
+ The driver provides an abstraction for Rockchip lcd controller,
+ lcd controller is the display interface from memory frame buffer
+ to display device.
+
+config DRM_ROCKCHIP_CONNECTOR
+   bool "ROCKCHIP DRM CONNECTOR"
+   depends on OF && DRM_ROCKCHIP && DRM_ROCKCHIP_LCDC
+   select FB_MODE_HELPERS
+   select VIDEOMODE_HELPERS
+   help
+ Choose this option if you want to use Rockchip Primary DISPLAY.
+ The driver provides an abstraction for Rockchip display devices,
+ such as lcd plane, lvds, edp , mipi, etc.
diff --git a/drivers/gpu/drm/rockchip/Makefile 
b/drivers/gpu/drm/rockchip/Makefile
new file mode 100644
index

[sbc_gxx] kernel BUG at include/linux/mtd/map.h:148!

2014-08-07 Thread Brian Norris
Hi,

On Tue, Aug 05, 2014 at 08:08:57PM -0400, Nick Krause wrote:
> On Tue, Aug 5, 2014 at 9:59 AM, Fengguang Wu  
> wrote:
> > Hello,
> >
> > This is an old BUG that still lives in linux-next.
> >
> > [4.284620] device id = 2670
> > [4.286157] SBC-GXx flash: IO:0x258-0x259 MEM:0xdc000-0xd
> > [4.287060] [ cut here ]
> > [4.287722] kernel BUG at include/linux/mtd/map.h:148!
> > [4.288048] invalid opcode:  [#1] PREEMPT SMP
>
> I am new , here and will try to trace your issue on linus's tree
> unless there is a major difference between Linus's tree and
> linux-next.
> If there is please let me known before I start tracing this.

This is a known issue, and Fengguang has reported this before:

  http://lists.infradead.org/pipermail/linux-mtd/2014-March/053019.html

I'm still not quite sure how to solve this one. It seems to be a
limitation of the kconfig language.

Brian


[sbc_gxx] kernel BUG at include/linux/mtd/map.h:148!

2014-08-07 Thread Nick Krause
On Thu, Aug 7, 2014 at 6:46 PM, Brian Norris
 wrote:
> Hi,
>
> On Tue, Aug 05, 2014 at 08:08:57PM -0400, Nick Krause wrote:
>> On Tue, Aug 5, 2014 at 9:59 AM, Fengguang Wu  
>> wrote:
>> > Hello,
>> >
>> > This is an old BUG that still lives in linux-next.
>> >
>> > [4.284620] device id = 2670
>> > [4.286157] SBC-GXx flash: IO:0x258-0x259 MEM:0xdc000-0xd
>> > [4.287060] [ cut here ]
>> > [4.287722] kernel BUG at include/linux/mtd/map.h:148!
>> > [4.288048] invalid opcode:  [#1] PREEMPT SMP
>>
>> I am new , here and will try to trace your issue on linus's tree
>> unless there is a major difference between Linus's tree and
>> linux-next.
>> If there is please let me known before I start tracing this.
>
> This is a known issue, and Fengguang has reported this before:
>
>   http://lists.infradead.org/pipermail/linux-mtd/2014-March/053019.html
>
> I'm still not quite sure how to solve this one. It seems to be a
> limitation of the kconfig language.
>
> Brian


I am and banned from the lists but trying to get back on, if you want
my help please
let me known. I will read this bug report first but just tell me if
you want some help.
Cheers Nick