[PATCH] ttm: use NULL instead of 0 for ttm_bo_reserve()'s pointer arg.
On Sunday, June 15, 2014 9:11 AM, Martin Kepplinger wrote: > > Fix a sparse warning: ttm_bo_reserve()'s last argument is a > pointer to a struct, so use NULL as nullpointer. > > Signed-off-by: Martin Kepplinger Reviewed-by: Jingoo Han Best regards, Jingoo Han > --- > this applies to next-20140613. Please ignore if annoyingly irrelevant. > > drivers/gpu/drm/ttm/ttm_bo.c | 14 +++--- > 1 file changed, 7 insertions(+), 7 deletions(-)
[Bug 80071] New: rendering errors with radeonsi and civilization 5 (V)
16 0 r . . 5 6 5 0 . . 0 16 0 0 0 0 0 0 0 None 0x089 0 tc 0 16 0 r y . 5 6 5 0 . . 0 24 8 0 0 0 0 0 0 None 0x08a 0 tc 0 16 0 r . . 5 6 5 0 . . 0 24 8 0 0 0 0 0 0 None 0x08b 24 tc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 0 0 None 0x08c 24 tc 0 32 0 r . . 8 8 8 8 . . 0 0 0 0 0 0 0 0 0 None 0x08d 24 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x08e 24 tc 0 32 0 r . . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x08f 0 tc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 0 0 None 0x090 0 tc 0 16 0 r y . 5 6 5 0 . . 0 16 0 16 16 16 0 0 0 Slow 0x091 32 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x092 24 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 16 16 16 16 0 0 Slow 0x093 0 tc 0 16 0 r y . 5 6 5 0 . . 0 0 0 0 0 0 0 4 1 None 0x094 0 tc 0 16 0 r y . 5 6 5 0 . . 0 0 0 0 0 0 0 8 1 None 0x095 0 tc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 4 1 None 0x096 0 tc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 8 1 None 0x097 24 tc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 4 1 None 0x098 24 tc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 8 1 None 0x099 24 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 4 1 None 0x09a 24 tc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 8 1 None 0x09b 0 dc 0 16 0 r y . 5 6 5 0 . . 0 0 0 0 0 0 0 0 0 None 0x09c 0 dc 0 16 0 r . . 5 6 5 0 . . 0 0 0 0 0 0 0 0 0 None 0x09d 0 dc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 0 0 None 0x09e 0 dc 0 16 0 r . . 5 6 5 0 . . 0 16 0 0 0 0 0 0 0 None 0x09f 0 dc 0 16 0 r y . 5 6 5 0 . . 0 24 8 0 0 0 0 0 0 None 0x0a0 0 dc 0 16 0 r . . 5 6 5 0 . . 0 24 8 0 0 0 0 0 0 None 0x0a1 24 dc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 0 0 None 0x0a2 24 dc 0 32 0 r . . 8 8 8 8 . . 0 0 0 0 0 0 0 0 0 None 0x0a3 24 dc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x0a4 24 dc 0 32 0 r . . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x0a5 0 dc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 0 0 None 0x0a6 0 dc 0 16 0 r y . 5 6 5 0 . . 0 16 0 16 16 16 0 0 0 Slow 0x0a7 24 dc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 0 0 None 0x0a8 24 dc 0 32 0 r y . 8 8 8 8 . . 0 24 8 16 16 16 16 0 0 Slow 0x0a9 0 dc 0 16 0 r y . 5 6 5 0 . . 0 0 0 0 0 0 0 4 1 None 0x0aa 0 dc 0 16 0 r y . 5 6 5 0 . . 0 0 0 0 0 0 0 8 1 None 0x0ab 0 dc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 4 1 None 0x0ac 0 dc 0 16 0 r y . 5 6 5 0 . . 0 16 0 0 0 0 0 8 1 None 0x0ad 24 dc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 4 1 None 0x0ae 24 dc 0 32 0 r y . 8 8 8 8 . . 0 0 0 0 0 0 0 8 1 None 0x0af 24 dc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 4 1 None 0x0b0 24 dc 0 32 0 r y . 8 8 8 8 . . 0 24 8 0 0 0 0 8 1 None radeonsi is git build till commit cc615d06db0332fc6e673b55632bcc7bf957b44b mesa dev is git build till commit 4133c7126c8c694ee4b05da1f312c411c0f6fdeb X log is attached. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/bb55f298/attachment-0001.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 --- Comment #1 from Paulo Dias --- Created attachment 101129 --> https://bugs.freedesktop.org/attachment.cgi?id=101129&action=edit rendering errors, smoke -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/b4d03f02/attachment.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 --- Comment #2 from Paulo Dias --- Created attachment 101130 --> https://bugs.freedesktop.org/attachment.cgi?id=101130&action=edit rendering errors, light -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/e2548295/attachment.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 --- Comment #3 from Paulo Dias --- i forgot to add, llvm is svn build 1:3.5~svn210990-1~exp1. also the same game works without errors with intel + same mesa git -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/4e3a2fc3/attachment.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 Paulo Dias changed: What|Removed |Added Attachment #101129|text/plain |image/jpeg mime type|| -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/e83352b1/attachment.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 Paulo Dias changed: What|Removed |Added Attachment #101130|text/plain |image/jpeg mime type|| -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/20c0e86c/attachment.html>
[Bug 80071] rendering errors with radeonsi and civilization 5 (V)
https://bugs.freedesktop.org/show_bug.cgi?id=80071 Paulo Dias changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |DUPLICATE --- Comment #4 from Paulo Dias --- *** This bug has been marked as a duplicate of bug 80015 *** -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/b442e4ae/attachment.html>
[Bug 80015] Transparency glitches in native Civilization 5 (Civ5) port
https://bugs.freedesktop.org/show_bug.cgi?id=80015 Paulo Dias changed: What|Removed |Added CC||paulo.miguel.dias at gmail.com --- Comment #3 from Paulo Dias --- *** Bug 80071 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/dd3d6378/attachment.html>
[Bug 80015] Transparency glitches in native Civilization 5 (Civ5) port
https://bugs.freedesktop.org/show_bug.cgi?id=80015 --- Comment #4 from smoki --- (In reply to comment #2) > Created attachment 10 [details] [review] > patch > > It seems the game relies on specific behavior of inversesqrt, which is > undefined when x <= 0 according to GLSL spec. The attached patch uses > V_RSQ_CLAMP_F32 instead of V_RSQ_LEGACY_F32 for int_AMDGPU_rsq, this fixed > the issue for me. Thanks Vadim, that fixed it for me too :). -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/d94c3a5d/attachment-0001.html>
[Bug 44800] Radeon HD 6450 CAICOS screen corruption and kernel crashes
https://bugs.freedesktop.org/show_bug.cgi?id=44800 --- Comment #15 from Marko Kohtala --- I tried with Ubuntu 13.10 live, and the screen corruption appeared. So it was not a BIOS fix. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/7349fc56/attachment.html>
[Bug 76284] [radeon] dota2, applying new screen resolution corrupts display
https://bugs.freedesktop.org/show_bug.cgi?id=76284 --- Comment #6 from Michel D?nzer --- Does the same thing happen if you switch between 'Window' and 'Borderless Window' mode? AFAICT dota2 never actually changes screen resolution when changing any of these settings, apparently it merely changes some internal state. BTW, I can always exit the game with Alt-F4, no need to guess where any buttons are located. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/0dfc2c91/attachment.html>
[Bug 79850] [awesomenauts][radeonsi] pageflip is clearly missing vblank with vsync on
https://bugs.freedesktop.org/show_bug.cgi?id=79850 --- Comment #11 from Michel D?nzer --- (In reply to comment #7) > can_flip returns true. Does radeon_do_pageflip() fail then? If so, can you narrow down why? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/00ec7752/attachment.html>
[Bug 79997] [Dell Inspiron 6400] Laptop screen is turned off, needs shutdown to work again
https://bugs.freedesktop.org/show_bug.cgi?id=79997 --- Comment #1 from Michel D?nzer --- Please attach /var/log/Xorg.0.log and the output of dmesg and glxinfo, preferably captured after the problem occurred. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/026349e0/attachment.html>
[PATCH v14 01/10] [media] v4l2: add new V4L2_PIX_FMT_RGB666 pixel format.
On Mon, Jun 16, 2014 at 12:11:15PM +0200, Denis Carikli wrote: > That new macro is needed by the imx_drm staging driver > for supporting the QVGA display of the eukrea-cpuimx51 board. As I said probably around v10 time, I already have this patch queued, and I was going to send it to Greg before the previous merge window, but due to the number of patches I was already carrying, it was lost amongst the trees. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it.
[PATCH v14 02/10] imx-drm: Add RGB666 support for parallel display.
On Mon, Jun 16, 2014 at 12:11:16PM +0200, Denis Carikli wrote: > Signed-off-by: Denis Carikli > Acked-by: Philipp Zabel As I said probably around v10 time, I already have this patch queued, and I was going to send it to Greg before the previous merge window, but due to the number of patches I was already carrying, it was lost amongst the trees. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it.
[PATCH v14 03/10] imx-drm: Correct BGR666 and the board's dts that use them.
On Mon, Jun 16, 2014 at 12:11:17PM +0200, Denis Carikli wrote: > The current BGR666 is not consistent with the other color mapings like BGR24. > BGR666 should be in the same byte order than BGR24. > > Signed-off-by: Denis Carikli > Acked-by: Philipp Zabel As I said probably around v10 time, I already have this patch queued, and I was going to send it to Greg before the previous merge window, but due to the number of patches I was already carrying, it was lost amongst the trees. -- FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly improving, and getting towards what was expected from it.
radeon: screen garbled after page allocator change, was: Re: [patch v2 3/3] mm: page_alloc: fair zone allocator policy
Hi! On Mon, 28 Apr 2014 10:09:17 +0200, I wrote: > On Sun, 27 Apr 2014 15:55:29 -0400, Jerome Glisse > wrote: > > If my ugly patch works does this quirk also work ? > > Unfortunately they both don't; see my other email, > <http://news.gmane.org/find-root.php?message_id=%3C87sioxq3rx.fsf%40schwinge.name%3E>. > [...] hacked around as follows: [...] > If needed, I can try to capture more data, but someone who has knowledge > of PCI bus architecture and Linux kernel code (so, not me), might > probably already see what's wrong. The problem "solved itself": the machine recently died of hardware failure. ;-| Gr??e, Thomas -- next part -- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 472 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/1d7ae43b/attachment-0001.sig>
[PATCH v14 02/10] imx-drm: Add RGB666 support for parallel display.
Signed-off-by: Denis Carikli
Acked-by: Philipp Zabel
---
ChangeLog v13->v14:
- Rebased
ChangeLog v9->v13:
- Rebased
ChangeLog v8->v9:
- Rebased.
- Added Philipp Zabel's ack.
- Shortened the patch title.
ChangeLog v8->v9:
- Removed the Cc. They are now set in git-send-email directly.
- Rebased.
ChangeLog v7->v8:
- Shrinked even more the Cc list.
ChangeLog v6->v7:
- Shrinked even more the Cc list.
ChangeLog v5->v6:
- Remove people not concerned by this patch from the Cc list.
ChangeLog v3->v5:
- Use the correct RGB order.
ChangeLog v2->v3:
- Added some interested people in the Cc list.
- Removed the commit message long desciption that was just a copy of the short
description.
- Rebased the patch.
- Fixed a copy-paste error in the ipu_dc_map_clear parameter.
---
.../bindings/staging/imx-drm/fsl-imx-drm.txt |4 ++--
drivers/gpu/ipu-v3/ipu-dc.c|9 +
drivers/staging/imx-drm/parallel-display.c |2 ++
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index e75f0e5..c0eb95a 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -60,8 +60,8 @@ Required properties:
- compatible: Should be "fsl,imx-parallel-display"
Optional properties:
- interface_pix_fmt: How this display is connected to the
- display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
- and "lvds666".
+ display interface. Currently supported types: "rgb24", "rgb565", "bgr666",
+ "rgb666" and "lvds666".
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
channel
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 2326c75..100d410 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -93,6 +93,7 @@ enum ipu_dc_map {
IPU_DC_MAP_BGR666,
IPU_DC_MAP_LVDS666,
IPU_DC_MAP_BGR24,
+ IPU_DC_MAP_RGB666,
};
struct ipu_dc {
@@ -161,6 +162,8 @@ static int ipu_pixfmt_to_map(u32 fmt)
return IPU_DC_MAP_LVDS666;
case V4L2_PIX_FMT_BGR24:
return IPU_DC_MAP_BGR24;
+ case V4L2_PIX_FMT_RGB666:
+ return IPU_DC_MAP_RGB666;
default:
return -EINVAL;
}
@@ -452,6 +455,12 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
+ /* rgb666 */
+ ipu_dc_map_clear(priv, IPU_DC_MAP_RGB666);
+ ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 0, 5, 0xfc); /* blue */
+ ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 1, 11, 0xfc); /* green */
+ ipu_dc_map_config(priv, IPU_DC_MAP_RGB666, 2, 17, 0xfc); /* red */
+
return 0;
}
diff --git a/drivers/staging/imx-drm/parallel-display.c
b/drivers/staging/imx-drm/parallel-display.c
index b567832..64b34336 100644
--- a/drivers/staging/imx-drm/parallel-display.c
+++ b/drivers/staging/imx-drm/parallel-display.c
@@ -218,6 +218,8 @@ static int imx_pd_bind(struct device *dev, struct device
*master, void *data)
imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB565;
else if (!strcmp(fmt, "bgr666"))
imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666;
+ else if (!strcmp(fmt, "rgb666"))
+ imxpd->interface_pix_fmt = V4L2_PIX_FMT_RGB666;
else if (!strcmp(fmt, "lvds666"))
imxpd->interface_pix_fmt = v4l2_fourcc('L', 'V', 'D',
'6');
}
--
1.7.9.5
[PATCH v14 01/10] [media] v4l2: add new V4L2_PIX_FMT_RGB666 pixel format.
That new macro is needed by the imx_drm staging driver
for supporting the QVGA display of the eukrea-cpuimx51 board.
Signed-off-by: Denis Carikli
Acked-by: Mauro Carvalho Chehab
Acked-by: Laurent Pinchart
Acked-by: Philipp Zabel
---
ChangeLog v13->v14:
- None
ChangeLog v10->v13:
- No changes
ChangeLog v9->v10:
- Rebased on top of:
"211e7f2 [media] DocBook media: drop the old incorrect packed RGB table"
- Added Philipp Zabel's Ack.
ChangeLog v8->v9:
- Removed the Cc. They are now set in git-send-email directly.
ChangeLog v7->v8:
- Added Mauro Carvalho Chehab back to the list of Cc
ChangeLog v6->v7:
- Shrinked even more the Cc list.
ChangeLog v5->v6:
- Remove people not concerned by this patch from the Cc list.
ChangeLog v3->v4:
- Added Laurent Pinchart's Ack.
ChangeLog v2->v3:
- Added some interested people in the Cc list.
- Added Mauro Carvalho Chehab's Ack.
- Added documentation.
---
.../DocBook/media/v4l/pixfmt-packed-rgb.xml| 39
include/uapi/linux/videodev2.h |1 +
2 files changed, 40 insertions(+)
diff --git a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml
b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml
index e1c4f8b..88a7fe1 100644
--- a/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml
+++ b/Documentation/DocBook/media/v4l/pixfmt-packed-rgb.xml
@@ -279,6 +279,45 @@ colorspace
V4L2_COLORSPACE_SRGB.
+
+ V4L2_PIX_FMT_RGB666
+ 'RGBH'
+
+ r5
+ r4
+ r3
+ r2
+ r1
+ r0
+ g5
+ g4
+
+ g3
+ g2
+ g1
+ g0
+ b5
+ b4
+ b3
+ b2
+
+ b1
+ b0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
V4L2_PIX_FMT_BGR24
'BGR3'
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 168ff50..08cac01 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -299,6 +299,7 @@ struct v4l2_pix_format {
#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16 RGB-5-5-5
BE */
#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16 RGB-5-6-5
BE */
#define V4L2_PIX_FMT_BGR666 v4l2_fourcc('B', 'G', 'R', 'H') /* 18 BGR-6-6-6
*/
+#define V4L2_PIX_FMT_RGB666 v4l2_fourcc('R', 'G', 'B', 'H') /* 18 RGB-6-6-6
*/
#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B', 'G', 'R', '3') /* 24 BGR-8-8-8
*/
#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R', 'G', 'B', '3') /* 24 RGB-8-8-8
*/
#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B', 'G', 'R', '4') /* 32
BGR-8-8-8-8 */
--
1.7.9.5
[PATCH v14 03/10] imx-drm: Correct BGR666 and the board's dts that use them.
The current BGR666 is not consistent with the other color mapings like BGR24.
BGR666 should be in the same byte order than BGR24.
Signed-off-by: Denis Carikli
Acked-by: Philipp Zabel
---
ChangeLog v13->v14:
- Rebased
ChangeLog v10->v13:
- Rebased
ChangeLog v9->v10:
- Rebased.
- Added Philipp Zabel's Ack.
- Included Lothar Wa?mann's suggestion about imx-ldb.c.
- Shortened the patch title
ChangeLog v8->v9:
- Removed the Cc. They are now set in git-send-email directly.
ChangeLog v7->v8:
- Shrinked even more the Cc list.
ChangeLog v6->v7:
- Shrinked even more the Cc list.
ChangeLog v5->v6:
- Remove people not concerned by this patch from the Cc list.
- Added a better explanation of the change.
ChangeLog v5:
- New patch.
---
arch/arm/boot/dts/imx51-apf51dev.dts |2 +-
arch/arm/boot/dts/imx53-m53evk.dts |2 +-
drivers/gpu/ipu-v3/ipu-dc.c |4 ++--
drivers/staging/imx-drm/imx-ldb.c|4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts
b/arch/arm/boot/dts/imx51-apf51dev.dts
index c5a9a24..7b3851d 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -18,7 +18,7 @@
display at di1 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "bgr666";
+ interface-pix-fmt = "rgb666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts
b/arch/arm/boot/dts/imx53-m53evk.dts
index d5d146a..4b036b4 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -24,7 +24,7 @@
soc {
display1: display at di1 {
compatible = "fsl,imx-parallel-display";
- interface-pix-fmt = "bgr666";
+ interface-pix-fmt = "rgb666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1>;
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 100d410..9974d41 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -439,9 +439,9 @@ int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
/* bgr666 */
ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
- ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
+ ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 17, 0xfc); /* blue */
ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
- ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
+ ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 5, 0xfc); /* red */
/* lvds666 */
ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
diff --git a/drivers/staging/imx-drm/imx-ldb.c
b/drivers/staging/imx-drm/imx-ldb.c
index 7e3f019..5d22e40 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -188,11 +188,11 @@ static void imx_ldb_encoder_prepare(struct drm_encoder
*encoder)
switch (imx_ldb_ch->chno) {
case 0:
pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
- V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
+ V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_RGB666;
break;
case 1:
pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
- V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
+ V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_RGB666;
break;
default:
dev_err(ldb->dev, "unable to config di%d panel format\n",
--
1.7.9.5
[PATCH v14 04/10] imx-drm: use defines for clock polarity settings
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- Rebased
ChangeLog 12->v13:
- No changes
ChangeLog 11->v12:
- Improved the define names to match the hardware:
ENABLE_POL is not a clock signal but instead an enable signal.
ChangeLog v9->v10:
- New patch which was splitted out from:
"staging: imx-drm: Use de-active and pixelclk-active display-timings.".
- Fixes many issues in "staging: imx-drm: Use de-active and pixelclk-active
display-timings.":
- More clear meaning of the polarity settings.
- The SET_CLK_POL and SET_DE_POL masks are not
needed anymore.
---
drivers/gpu/ipu-v3/ipu-di.c |4 ++--
drivers/staging/imx-drm/ipuv3-crtc.c |4 ++--
include/video/imx-ipu-v3.h |8 +++-
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index c490ba4..d00f357 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct
ipu_di_signal_cfg *sig)
}
}
- if (sig->clk_pol)
+ if (sig->clk_pol == CLK_POL_POSEDGE)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
@@ -606,7 +606,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct
ipu_di_signal_cfg *sig)
reg = ipu_di_read(di, DI_POL);
reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
- if (sig->enable_pol)
+ if (sig->enable_pol == ENABLE_POL_HIGH)
reg |= DI_POL_DRDY_POLARITY_15;
if (sig->data_pol)
reg |= DI_POL_DRDY_DATA_POLARITY;
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c
b/drivers/staging/imx-drm/ipuv3-crtc.c
index 720868b..7fec438 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -165,8 +165,8 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = 1;
- sig_cfg.clk_pol = 0;
+ sig_cfg.enable_pol = ENABLE_POL_HIGH;
+ sig_cfg.clk_pol = CLK_POL_NEGEDGE;
sig_cfg.width = mode->hdisplay;
sig_cfg.height = mode->vdisplay;
sig_cfg.pixel_fmt = out_pixel_fmt;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 3e43e22..305 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -27,6 +27,12 @@ enum ipuv3_type {
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
+#define CLK_POL_NEGEDGE0
+#define CLK_POL_POSEDGE1
+
+#define ENABLE_POL_LOW 0
+#define ENABLE_POL_HIGH1
+
/*
* Bitfield of Display Interface signal polarities.
*/
@@ -37,7 +43,7 @@ struct ipu_di_signal_cfg {
unsigned clksel_en:1;
unsigned clkidle_en:1;
unsigned data_pol:1;/* true = inverted */
- unsigned clk_pol:1; /* true = rising edge */
+ unsigned clk_pol:1;
unsigned enable_pol:1;
unsigned Hsync_pol:1; /* true = active high */
unsigned Vsync_pol:1;
--
1.7.9.5
[PATCH v14 07/10] imx-drm: Use drm_display_mode timings flags.
The previous hardware behaviour was kept if the
flags are not set.
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- Rebased
ChangeLog v12->v13:
- This patch doesn't need the DRM_MODE_FLAG_POL_*_PRESERVE flags anymore.
- code cleanup to improve readability:
- ENABLE_POL_PRESERVE is now gone
- Less modifications in ipu_di_init_sync_panel
- more readable modifications in int ipu_crtc_mode_set
ChangeLog v11->v12:
- Rebased: It now uses the following new flags defines names:
CLK_POL, ENABLE_POL
- The inversions in ipuv3-crtc.c are now fixed.
- ipuv3-crtc.c was still using mode->private_flags
from the previous versions of this patchset, that's now fixed.
ChangeLog v10->v11:
- This patch was splitted-out and adapted from:
"Prepare imx-drm for extra display-timings retrival."
- The display-timings dt specific part was removed.
- The flags names were changed to use the DRM ones from:
"drm: drm_display_mode: add signal polarity flags"
---
drivers/gpu/ipu-v3/ipu-di.c |2 ++
drivers/staging/imx-drm/ipuv3-crtc.c | 18 --
include/video/imx-ipu-v3.h |4 ++--
3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-di.c b/drivers/gpu/ipu-v3/ipu-di.c
index d00f357..1a1e116 100644
--- a/drivers/gpu/ipu-v3/ipu-di.c
+++ b/drivers/gpu/ipu-v3/ipu-di.c
@@ -597,6 +597,8 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct
ipu_di_signal_cfg *sig)
if (sig->clk_pol == CLK_POL_POSEDGE)
di_gen |= DI_GEN_POLARITY_DISP_CLK;
+ else if (sig->clk_pol == CLK_POL_NEGEDGE)
+ di_gen &= ~DI_GEN_POLARITY_DISP_CLK;
ipu_di_write(di, di_gen, DI_GENERAL);
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c
b/drivers/staging/imx-drm/ipuv3-crtc.c
index 7fec438..7fdf575 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -165,8 +165,22 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
sig_cfg.Vsync_pol = 1;
- sig_cfg.enable_pol = ENABLE_POL_HIGH;
- sig_cfg.clk_pol = CLK_POL_NEGEDGE;
+ if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_POSEDGE)
+ sig_cfg.clk_pol = CLK_POL_POSEDGE;
+ else if (mode->pol_flags & DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE)
+ sig_cfg.clk_pol = CLK_POL_NEGEDGE;
+ else
+ /* If no PIXDATA flags were set, keep the old behaviour */
+ sig_cfg.clk_pol = CLK_POL_NEGEDGE;
+
+ if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_HIGH)
+ sig_cfg.enable_pol = ENABLE_POL_HIGH;
+ else if (mode->pol_flags & DRM_MODE_FLAG_POL_DE_LOW)
+ sig_cfg.enable_pol = ENABLE_POL_LOW;
+ else
+ /* If no DE flags were set, keep the old behaviour */
+ sig_cfg.enable_pol = ENABLE_POL_HIGH;
+
sig_cfg.width = mode->hdisplay;
sig_cfg.height = mode->vdisplay;
sig_cfg.pixel_fmt = out_pixel_fmt;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 305..e660522 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -43,10 +43,10 @@ struct ipu_di_signal_cfg {
unsigned clksel_en:1;
unsigned clkidle_en:1;
unsigned data_pol:1;/* true = inverted */
- unsigned clk_pol:1;
- unsigned enable_pol:1;
unsigned Hsync_pol:1; /* true = active high */
unsigned Vsync_pol:1;
+ u8 clk_pol;
+ u8 enable_pol;
u16 width;
u16 height;
--
1.7.9.5
[PATCH v2 1/7] mfd: add atmel-hlcdc driver
2014-06-15 16:48 GMT+02:00 Boris BREZILLON : > > > Hello JJ, > > On 15/06/2014 10:53, Jean-Jacques Hiblot wrote: > > On 06/09/2014 06:04 PM, Boris BREZILLON wrote: > >> The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5 > >> family or sama5d3 family) exposes 2 subdevices: > >> - a display controller (controlled by a DRM driver) > >> - a PWM chip > >> > >> Add support for the MFD device which will just retrieve HLCDC clocks and > >> create a regmap so that subdevices can access the HLCDC register range > >> concurrently. > >> > >> Signed-off-by: Boris BREZILLON > >> --- > >> .../devicetree/bindings/mfd/atmel-hlcdc.txt| 41 > >> drivers/mfd/Kconfig| 11 ++ > >> drivers/mfd/Makefile | 1 + > [...] > >> +memset(&config, 0, sizeof(config)); > >> +config.reg_bits = 32; > >> +config.val_bits = 32; > >> +config.reg_stride = 4; > >> +config.max_register = (resource_size(res) / 4) - 1; > >> +hlcdc->regmap = devm_regmap_init_mmio_clk(dev, "periph_clk", regs, > >> + &config); > > I don't think it's necessary to use "periph_clk" here. This clock will > > always be running because the HLCDC needs it to work (it's not just an > > interface clock). In the end it's just some extra work for each register > > access. > > Yes, I thought about removing this clk from regmap registration too (for > the exact same reason: avoiding extra enable/disable work when accessing > registers), but ATM I do not prepare/enable periph_clk in the hlcdc-pwm > driver, this means the regmap won't work until the hlcdc-dc driver has > probed the display controller device. > > How about preparing/enabling the periph_clk in the MFD device, so that > PWM and Display Controller subdevices won't have to bother about this > clk, and the regmap will work as expected ? > Or, should we just prepare/enable the periph clock in each subdevices ? I think the latest is the best approach. This way the PWM and the DRM driver can handle their clock gating independently. BTW it's quite probable that the PWM don't really needs this clock except for register access. > > > > Best Regards, > > Boris > > -- > Boris Brezillon, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com >
[PATCH v14 05/10] ARM: dts: imx5*, imx6*: correct display-timings nodes.
The imx-drm driver can't use the de-active and pixelclk-active display-timings properties yet. Instead the data-enable and the pixel data clock polarity are hardcoded in the imx-drm driver. So theses properties are now set to keep the same behaviour when imx-drm will start using them. Signed-off-by: Denis Carikli --- ChangeLog v13->v14: - None ChangeLog v10->v11: - imx53-tx53-x03x.dts change was removed because it already had the correct setting. ChangeLog v9->v10: - New patch that was splitted out of: "staging imx-drm: Use de-active and pixelclk-active display-timings." --- arch/arm/boot/dts/imx51-babbage.dts |2 ++ arch/arm/boot/dts/imx53-m53evk.dts|2 ++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi |2 ++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi |2 ++ arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi |2 ++ arch/arm/boot/dts/imx6qdl-sabreauto.dtsi |2 ++ arch/arm/boot/dts/imx6qdl-sabrelite.dtsi |2 ++ arch/arm/boot/dts/imx6qdl-sabresd.dtsi|2 ++ 8 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts index ee51a10..b64a9e3 100644 --- a/arch/arm/boot/dts/imx51-babbage.dts +++ b/arch/arm/boot/dts/imx51-babbage.dts @@ -56,6 +56,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 4b036b4..d03ced7 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -41,6 +41,8 @@ vfront-porch = <9>; vsync-len = <3>; vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index d3125f0..7f993d6 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -512,6 +512,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 532347f..e06cf9e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -534,6 +534,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 4c4b175..bcf5178 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -353,6 +353,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 009abd6..230bbc6 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -405,6 +405,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 6df6127..9f6b406 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -353,6 +353,8 @@ vfront-porch = <7>; hsync-len = <60>; vsync-len = <10>; + de-active = <1>; + pixelclk-active = <0>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/i
[PATCH v14 10/10] ARM: dts: mbimx51sd: Add CMO-QVGA backlight support.
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- None
ChangeLog v11->v13:
- No changes
ChangeLog v9->v11:
- Now uses the drm-panel instead of the display-timings.
ChangeLog v8->v9:
- Removed the Cc. They are now set in git-send-email directly.
- The backlight is now on at boot.
ChangeLog v6->v7:
- Shrinked even more the Cc list.
ChangeLog v5->v6:
- Reordered the Cc list.
ChangeLog v3->v5:
- Updated to the new GPIO defines.
ChangeLog v2->v3:
- Splitted out from the patch that added support for the cpuimx51/mbimxsd51
boards.
- This patch now only adds backlight support.
- Added some interested people in the Cc list, and removed some people that
might be annoyed by the receiving of that patch which is unrelated to their
subsystem.
---
.../imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
index d273d09..6e36dae 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
@@ -17,9 +17,19 @@
model = "Eukrea MBIMXSD51 with the CMO-QVGA Display";
compatible = "eukrea,mbimxsd51-baseboard-cmo-qvga",
"eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51";
+ backlight: backlight {
+ compatible = "gpio-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_backlight_1>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ default-brightness-level = <1>;
+ default-on;
+ };
+
panel: panel {
compatible = "eukrea,mbimxsd51-cmo-qvga", "simple-panel";
power-supply = <®_lcd_3v3>;
+ backlight = <&backlight>;
};
reg_lcd_3v3: lcd-en {
--
1.7.9.5
[PATCH v14 06/10] drm: drm_display_mode: add signal polarity flags
We need a way to pass signal polarity informations
between DRM panels, and the display drivers.
To do that, a pol_flags field was added to drm_display_mode.
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- Fixed DRM_MODE_FLAG_POL_DE_HIGH's description.
ChangeLog v12->v13:
- Added Docbook documentation for pol_flags the struct field.
- Removed the _PRESERVE defines: it was used by patches
against the imx_drm driver. Now theses patches have been
adapted not to require that defines.
ChangeLog v11->v12:
- Rebased: This patch now applies against drm_modes.h
- Rebased: It now uses the new DRM_MODE_FLAG_POL_DE flags defines names
ChangeLog v10->v11:
- Since the imx-drm won't be able to retrive its regulators
from the device tree when using display-timings nodes,
and that I was told that the drm simple-panel driver
already supported that, I then, instead, added what was
lacking to make the eukrea displays work with the
drm-simple-panel driver.
That required a way to get back the display polarity
informations from the imx-drm driver without affecting
userspace.
---
Documentation/DocBook/drm.tmpl | 30 ++
include/drm/drm_modes.h|6 ++
2 files changed, 36 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index 7df3134..22d435f 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -2292,6 +2292,36 @@ void intel_crt_init(struct drm_device *dev)
and height_mm fields are only used
internally
during EDID parsing and should not be set when creating modes
manually.
+
+The pol_flags value represents the
display
+signal polarity flags, it can be a combination of
+
+
+DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE
+
+ drive pixel data on falling edge, sample data on rising
edge.
+
+
+
+DRM_MODE_FLAG_POL_PIXDATA_POSEDGE
+
+ Drive pixel data on rising edge, sample data on falling edge.
+
+
+
+DRM_MODE_FLAG_POL_DE_LOW
+
+ data-enable pulse is active low
+
+
+
+DRM_MODE_FLAG_POL_DE_HIGH
+
+ data-enable pulse is active high
+
+
+
+
int (*mode_valid)(struct drm_connector *connector,
diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
index 91d0582..c5cbe31 100644
--- a/include/drm/drm_modes.h
+++ b/include/drm/drm_modes.h
@@ -93,6 +93,11 @@ enum drm_mode_status {
#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
+#define DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE BIT(1)
+#define DRM_MODE_FLAG_POL_PIXDATA_POSEDGE BIT(2)
+#define DRM_MODE_FLAG_POL_DE_LOW BIT(3)
+#define DRM_MODE_FLAG_POL_DE_HIGH BIT(4)
+
struct drm_display_mode {
/* Header */
struct list_head head;
@@ -144,6 +149,7 @@ struct drm_display_mode {
int vrefresh; /* in Hz */
int hsync; /* in kHz */
enum hdmi_picture_aspect picture_aspect_ratio;
+ unsigned int pol_flags;
};
/* mode specified on the command line */
--
1.7.9.5
[PATCH v14 08/10] drm/panel: Add Eukrea mbimxsd51 displays.
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- None
ChangeLog v12->v13:
- Added a note explaining why the size is zero in
the eukrea_mbimxsd51_dvi(s)vga structs.
ChangeLog v11->v12:
- Rebased: It now uses the new DRM_MODE_FLAG_POL_DE flags defines names
ChangeLog v10->v11:
- New patch.
---
.../bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt |7 ++
.../bindings/panel/eukrea,mbimxsd51-dvi-svga.txt |7 ++
.../bindings/panel/eukrea,mbimxsd51-dvi-vga.txt|7 ++
drivers/gpu/drm/panel/panel-simple.c | 83
4 files changed, 104 insertions(+)
create mode 100644
Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt
create mode 100644
Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt
create mode 100644
Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt
diff --git
a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt
b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt
new file mode 100644
index 000..03679d0
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-cmo-qvga.txt
@@ -0,0 +1,7 @@
+Eukrea CMO-QVGA (320x240 pixels) TFT LCD panel
+
+Required properties:
+- compatible: should be "eukrea,mbimxsd51-cmo-qvga"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git
a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt
b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt
new file mode 100644
index 000..f408c9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-svga.txt
@@ -0,0 +1,7 @@
+Eukrea DVI-SVGA (800x600 pixels) DVI output.
+
+Required properties:
+- compatible: should be "eukrea,mbimxsd51-dvi-svga"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git
a/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt
b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt
new file mode 100644
index 000..8ea90da
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/eukrea,mbimxsd51-dvi-vga.txt
@@ -0,0 +1,7 @@
+Eukrea DVI-VGA (640x480 pixels) DVI output.
+
+Required properties:
+- compatible: should be "eukrea,mbimxsd51-dvi-vga"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c
b/drivers/gpu/drm/panel/panel-simple.c
index a251361..adc40a7 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -403,6 +403,80 @@ static const struct panel_desc edt_etm0700g0dh6 = {
},
};
+static const struct drm_display_mode eukrea_mbimxsd51_cmoqvga_mode = {
+ .clock = 6500,
+ .hdisplay = 320,
+ .hsync_start = 320 + 38,
+ .hsync_end = 320 + 38 + 20,
+ .htotal = 320 + 38 + 20 + 30,
+ .vdisplay = 240,
+ .vsync_start = 240 + 15,
+ .vsync_end = 240 + 15 + 4,
+ .vtotal = 240 + 15 + 4 + 3,
+ .vrefresh = 60,
+ .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_NEGEDGE |
+DRM_MODE_FLAG_POL_DE_LOW,
+};
+
+static const struct panel_desc eukrea_mbimxsd51_cmoqvga = {
+ .modes = &eukrea_mbimxsd51_cmoqvga_mode,
+ .num_modes = 1,
+ .size = {
+ .width = 73,
+ .height = 56,
+ },
+};
+
+static const struct drm_display_mode eukrea_mbimxsd51_dvisvga_mode = {
+ .clock = 44333,
+ .hdisplay = 800,
+ .hsync_start = 800 + 112,
+ .hsync_end = 800 + 112 + 32,
+ .htotal = 800 + 112 + 32 + 80,
+ .vdisplay = 600,
+ .vsync_start = 600 + 3,
+ .vsync_end = 600 + 3 + 17,
+ .vtotal = 600 + 3 + 17 + 4,
+ .vrefresh = 60,
+ .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_POSEDGE |
+DRM_MODE_FLAG_POL_DE_HIGH,
+};
+
+static const struct panel_desc eukrea_mbimxsd51_dvisvga = {
+ .modes = &eukrea_mbimxsd51_dvisvga_mode,
+ .num_modes = 1,
+ /* This is a DVI adapter for external displays */
+ .size = {
+ .width = 0,
+ .height = 0,
+ },
+};
+
+static const struct drm_display_mode eukrea_mbimxsd51_dvivga_mode = {
+ .clock = 23750,
+ .hdisplay = 640,
+ .hsync_start = 640 + 80,
+ .hsync_end = 640 + 80 + 16,
+ .htotal = 640 + 80 + 16 + 64,
+ .vdisplay = 480,
+ .vsync_start = 480 + 3,
+ .vsync_end = 480 + 3 + 13,
+ .vtotal = 480 + 3 + 13 + 4,
+ .vrefresh = 60,
+ .pol_flags = DRM_MODE_FLAG_POL_PIXDATA_POSEDGE |
+DRM_MODE_FLAG_POL_DE_HIGH,
+};
+
+static const struct panel_desc eukrea_mbimxsd51_dvivga = {
+ .modes = &eukrea_mbimxsd51_dvivga_mode,
+ .num_modes = 1,
+ /* This is a DVI adapter for external displays */
+
[PATCH v14 09/10] ARM: dts: mbimx51sd: Add display support.
The CMO-QVGA, DVI-SVGA and DVI-VGA are added.
Signed-off-by: Denis Carikli
---
ChangeLog v13->v14:
- None
ChangeLog v10->v13:
- Rebased
- Removed enable-active-high in reg_lcd_3v3: its GPIO
already has the GPIO_ACTIVE_HIGH flag.
Without this removal, the display was off at boot
and powering it off and on was necessary to get an
image on it after the boot.
ChangeLog v10->v11:
- Now uses the drm-panel instead of the display-timings.
This is to get regulator support, which is lacking in
the imx-drm driver when using the display-timings.
ChangeLog v9->v10:
- Rebased
- Now enables the cmo-qvga regulator at boot.
ChangeLog v8->v9:
- Removed the Cc. They are now set in git-send-email directly.
- updated pixelclk-active after the following patch:
"imx-drm: Match ipu_di_signal_cfg's clk_pol with its description."
ChangeLog v7->v8:
- Rebased the patch: added the now required imx-drm node.
- Adapted the svga clock-frequency value in order to still
be able to display an image after the following commit:
"imx-drm: ipu-v3: more inteligent DI clock selection"
ChangeLog v6->v7:
- Shrinked even more the Cc list.
- Since the pingrp headers were removed, the references
to it where replaced by the actual pins.
- Added the targets to arch/arm/boot/dts/Makefile
ChangeLog v5->v6:
- Reordered the Cc list.
ChangeLog v3->v5:
- Updated to new GPIO defines.
- Updated to new licenses checkpatch requirements.
- one whitespace cleanup.
ChangeLog v2->v3:
- Splitted out from the patch that added support for the cpuimx51/mbimxsd51
boards.
- This patch now only adds display support.
- Added some interested people in the Cc list, and removed some people that
might be annoyed by the receiving of that patch which is unrelated to their
subsystem.
- rebased and reworked the dts displays addition.
- Also rebased and reworked the fsl,pins usage.
---
arch/arm/boot/dts/Makefile |3 ++
.../imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts | 40
.../imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts | 28 +++
.../imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts | 28 +++
.../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 49
5 files changed, 148 insertions(+)
create mode 100644
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
create mode 100644
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts
create mode 100644
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0f1e8be..f0ec7b7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -177,6 +177,9 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx51-babbage.dtb \
imx51-digi-connectcore-jsk.dtb \
imx51-eukrea-mbimxsd51-baseboard.dtb \
+ imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dtb \
+ imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dtb \
+ imx51-eukrea-mbimxsd51-baseboard-dvi-vga.dtb \
imx53-ard.dtb \
imx53-m53evk.dtb \
imx53-mba53.dtb \
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
new file mode 100644
index 000..d273d09
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-cmo-qvga.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2013 Eukr?a Electromatique
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx51-eukrea-mbimxsd51-baseboard.dts"
+
+/ {
+ model = "Eukrea MBIMXSD51 with the CMO-QVGA Display";
+ compatible = "eukrea,mbimxsd51-baseboard-cmo-qvga",
"eukrea,mbimxsd51-baseboard", "eukrea,cpuimx51", "fsl,imx51";
+
+ panel: panel {
+ compatible = "eukrea,mbimxsd51-cmo-qvga", "simple-panel";
+ power-supply = <®_lcd_3v3>;
+ };
+
+ reg_lcd_3v3: lcd-en {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
+ regulator-name = "lcd-3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ };
+};
+
+&display {
+ status = "okay";
+ fsl,panel = <&panel>;
+};
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts
b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard-dvi-svga.dts
new fil
[Bug 79980] Random radeonsi crashes
https://bugs.freedesktop.org/show_bug.cgi?id=79980 --- Comment #10 from Andy Furniss --- (In reply to comment #9) > (In reply to comment #8) > > optimize SI VM handling + use lower_32_bits where appropriate reverted - the > > latter just so I could revert the former. > > > > I'll see if I am stable over the next couple of days like this. > > I am stable so far with the above reverted. Spoke too soon, I just locked. Wasn't quite the same as before in that screen stayed on displaying normal rather that off/on + junk. Wasn't doing anything GPU related (accepting I always am with glamor), was doing a big compile, so memory pressure I guess. Also just add to the mix, after thinking I was stable yesterday I upgraded gcc and updated llvm and mesa so they were different in several ways, though I haven't rebuilt kernel. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/0e3c5d90/attachment.html>
[Bug 80029] [bisected] HDMI Errors on drm-next & Linus's tree
https://bugs.freedesktop.org/show_bug.cgi?id=80029 --- Comment #19 from Alex Deucher --- I've added the fix to my drm-fixes tree. It is correct. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/c44937ae/attachment.html>
[PATCH] imx-drm: imx-hdmi: fix hdmi hotplug detection initial state
On Wed, Jun 11, 2014 at 5:17 AM, Russell King - ARM Linux
wrote:
> The problem here is that we need more inteligence from CCF in order to
> do that - we need it to be able to reprogram the dividers so that the
> IPU DI0 clock remains at 148.5MHz while increasing the output of
> pll5_video_div three-fold.
>
> Another solution would be to source the LDB clock from PLL3 at 480MHz,
> this gives a pixel clock of 68.6MHz (3sf). The other options are
Ok, I have tried this approach:
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -441,8 +441,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
cpu_is_imx6dl()) {
- clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
- clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+ clk_set_parent(clk[ldb_di0_sel], clk[pll3_usb_otg]);
+ clk_set_parent(clk[ldb_di1_sel], clk[pll3_usb_otg]);
}
and it allows HDMI and LVDS to be displayed if I boot with the HDMI
kernel connected. Would this be an acceptable solution in the
meantime?
[Bug 78111] New: APU turbo core boost not working when radeon.dpm=1
https://bugzilla.kernel.org/show_bug.cgi?id=78111 Bug ID: 78111 Summary: APU turbo core boost not working when radeon.dpm=1 Product: Drivers Version: 2.5 Kernel Version: 3.14.6 Hardware: x86-64 OS: Linux Tree: Mainline Status: NEW Severity: normal Priority: P1 Component: Video(DRI - non Intel) Assignee: drivers_video-dri at kernel-bugs.osdl.org Reporter: bgz.marko at gmail.com Regression: No I am testing with A6-1450 APU on Arch Linux. If I pass radeon.dpm=1 parameter at boot and start a single core workload then turbostat will report max frequency of about 1000 MHz: Core CPU Avg_MHz Bzy_MHz TSC_MHz time - - 262 998 998 5** 0 0 12 998 998 5** 1 1 998 998 998 2 2 16 998 998 3 3 21 998 998 "cpupower frequency-info" reports that boost state support is supported, but not active: boost state support: Supported: yes Active: no However, when dynamic power management is disabled (radeon.dpm=0), turbostat reports higher frequencies for single core load, up to 1300 Mhz: Core CPU Avg_MHz Bzy_MHz TSC_MHz time - - 3201214 998 5** 0 0 91226 998 5** 1 1 131194 998 2 2 411143 998 3 312161216 998 "cpupower frequency-info" confirms that boost is now active. boost state support: Supported: yes Active: yes -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33
https://bugs.freedesktop.org/show_bug.cgi?id=72921 --- Comment #15 from Alex Deucher --- (In reply to comment #14) > So what should I do with this? How long do I wait for a fix for this? I > would really not want to replace my motherboard just to use my APU. You can either disable dpm (I can add a quirk in the meantime to disable it by default for your board), or wait for the fix. I'm not sure how long it will take to track down exactly what is going wrong. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/5561046b/attachment.html>
[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33
https://bugs.freedesktop.org/show_bug.cgi?id=72921 --- Comment #16 from Alex Deucher --- Created attachment 101179 --> https://bugs.freedesktop.org/attachment.cgi?id=101179&action=edit possible fix Maybe there is some problem with the clocks or voltage in the highest power level. Does the attached patch help? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/575079e0/attachment.html>
[Bug 78111] APU turbo core boost not working when radeon.dpm=1
https://bugzilla.kernel.org/show_bug.cgi?id=78111 Alex Deucher changed: What|Removed |Added CC||alexdeucher at gmail.com --- Comment #1 from Alex Deucher --- Please attach your dmesg output with radeon.dpm=1 -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 78111] APU turbo core boost not working when radeon.dpm=1
https://bugzilla.kernel.org/show_bug.cgi?id=78111 --- Comment #2 from Alex Deucher --- Created attachment 139971 --> https://bugzilla.kernel.org/attachment.cgi?id=139971&action=edit enable bapm The attached patch will allow the GPU and CPU to share TDP, but note that this is disabled by default at the moment. -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 75917] backlight switches off when starting X - since kernel-3.13
https://bugs.freedesktop.org/show_bug.cgi?id=75917 --- Comment #14 from Alex Deucher --- Fix is upstream: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=f2bc561610962693be61425cf913778586d8f9c1 and will make it's way back to stable kernels as well. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/82614389/attachment.html>
[Bug 75917] backlight switches off when starting X - since kernel-3.13
https://bugs.freedesktop.org/show_bug.cgi?id=75917 Alex Deucher changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/f50f7d21/attachment.html>
[Bug 74551] Unable to enable ACPI
https://bugzilla.kernel.org/show_bug.cgi?id=74551 --- Comment #10 from maxis11 --- 3.16-rc1 still buggy -- You are receiving this mail because: You are watching the assignee of the bug.
[Bug 75276] Implement VGPR Register Spilling
https://bugs.freedesktop.org/show_bug.cgi?id=75276 --- Comment #26 from Tom Stellard --- I've pushed a work-arond for the crash to LLVM trunk, so if you use the latest version of LLVM from svn/git these games should not crash, but there may be some mis-rendering. When I come up with a proper fix, I will post it to this bug (this could be a while). -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/16567d8a/attachment.html>
[RFC PATCH 4/4] cpufreq: tegra: Register a minimum EMC frequency based on the CPU clock
Instead of setting a direct correlation to the CPU frequency. This allows
for other devices to influence the final effective EMC frequency.
In the future, this should be done instead by an ACTMON driver,
which would also take load stats into account when calculating the
floor EMC frequency.
Signed-off-by: Tomeu Vizoso
---
drivers/cpufreq/tegra-cpufreq.c | 20 +---
1 file changed, 5 insertions(+), 15 deletions(-)
diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c
index 8084c7f..64935f8 100644
--- a/drivers/cpufreq/tegra-cpufreq.c
+++ b/drivers/cpufreq/tegra-cpufreq.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
static struct cpufreq_frequency_table freq_table[] = {
{ .frequency = 216000 },
@@ -44,7 +45,6 @@ static struct cpufreq_frequency_table freq_table[] = {
static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
-static struct clk *emc_clk;
static bool pll_x_prepared;
static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
@@ -96,15 +96,15 @@ static int tegra_target(struct cpufreq_policy *policy,
unsigned int index)
int ret = 0;
/*
-* Vote on memory bus frequency based on cpu frequency
+* Set minimum memory bus frequency based on cpu frequency
* This sets the minimum frequency, display or avp may request higher
*/
if (rate >= 816000)
- clk_set_rate(emc_clk, 6); /* cpu 816 MHz, emc max */
+ tegra124_emc_set_floor(6); /* cpu 816 MHz, emc max */
else if (rate >= 456000)
- clk_set_rate(emc_clk, 3); /* cpu 456 MHz, emc 150Mhz */
+ tegra124_emc_set_floor(3); /* cpu 456 MHz, emc 150Mhz */
else
- clk_set_rate(emc_clk, 1); /* emc 50Mhz */
+ tegra124_emc_set_floor(1); /* emc 50Mhz */
/*
* target freq == pll_p, don't need to take extra reference to pll_x_clk
@@ -141,14 +141,12 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
if (policy->cpu >= NUM_CPUS)
return -EINVAL;
- clk_prepare_enable(emc_clk);
clk_prepare_enable(cpu_clk);
/* FIXME: what's the actual transition time? */
ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
if (ret) {
clk_disable_unprepare(cpu_clk);
- clk_disable_unprepare(emc_clk);
return ret;
}
@@ -160,7 +158,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
clk_disable_unprepare(cpu_clk);
- clk_disable_unprepare(emc_clk);
return 0;
}
@@ -194,19 +191,12 @@ static int __init tegra_cpufreq_init(void)
if (IS_ERR(pll_p_clk))
return PTR_ERR(pll_p_clk);
- emc_clk = clk_get_sys("cpu", "emc");
- if (IS_ERR(emc_clk)) {
- clk_put(cpu_clk);
- return PTR_ERR(emc_clk);
- }
-
return cpufreq_register_driver(&tegra_cpufreq_driver);
}
static void __exit tegra_cpufreq_exit(void)
{
cpufreq_unregister_driver(&tegra_cpufreq_driver);
- clk_put(emc_clk);
clk_put(cpu_clk);
}
--
1.9.3
[RFC PATCH 4/4] cpufreq: tegra: Register a minimum EMC frequency based on the CPU clock
The tegra-cpufreq driver is only for Tegra20, an upcoming driver for
Tegra124 will be separate, so this is not needed.
Thanks,
- Mikko
On 06/16/2014 04:35 PM, Tomeu Vizoso wrote:
> Instead of setting a direct correlation to the CPU frequency. This allows
> for other devices to influence the final effective EMC frequency.
>
> In the future, this should be done instead by an ACTMON driver,
> which would also take load stats into account when calculating the
> floor EMC frequency.
>
> Signed-off-by: Tomeu Vizoso
> ---
> drivers/cpufreq/tegra-cpufreq.c | 20 +---
> 1 file changed, 5 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c
> index 8084c7f..64935f8 100644
> --- a/drivers/cpufreq/tegra-cpufreq.c
> +++ b/drivers/cpufreq/tegra-cpufreq.c
> @@ -26,6 +26,7 @@
> #include
> #include
> #include
> +#include
>
> static struct cpufreq_frequency_table freq_table[] = {
> { .frequency = 216000 },
> @@ -44,7 +45,6 @@ static struct cpufreq_frequency_table freq_table[] = {
> static struct clk *cpu_clk;
> static struct clk *pll_x_clk;
> static struct clk *pll_p_clk;
> -static struct clk *emc_clk;
> static bool pll_x_prepared;
>
> static unsigned int tegra_get_intermediate(struct cpufreq_policy *policy,
> @@ -96,15 +96,15 @@ static int tegra_target(struct cpufreq_policy *policy,
> unsigned int index)
> int ret = 0;
>
> /*
> - * Vote on memory bus frequency based on cpu frequency
> + * Set minimum memory bus frequency based on cpu frequency
>* This sets the minimum frequency, display or avp may request higher
>*/
> if (rate >= 816000)
> - clk_set_rate(emc_clk, 6); /* cpu 816 MHz, emc max */
> + tegra124_emc_set_floor(6); /* cpu 816 MHz, emc max */
> else if (rate >= 456000)
> - clk_set_rate(emc_clk, 3); /* cpu 456 MHz, emc 150Mhz */
> + tegra124_emc_set_floor(3); /* cpu 456 MHz, emc 150Mhz */
> else
> - clk_set_rate(emc_clk, 1); /* emc 50Mhz */
> + tegra124_emc_set_floor(1); /* emc 50Mhz */
>
> /*
>* target freq == pll_p, don't need to take extra reference to pll_x_clk
> @@ -141,14 +141,12 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
> if (policy->cpu >= NUM_CPUS)
> return -EINVAL;
>
> - clk_prepare_enable(emc_clk);
> clk_prepare_enable(cpu_clk);
>
> /* FIXME: what's the actual transition time? */
> ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
> if (ret) {
> clk_disable_unprepare(cpu_clk);
> - clk_disable_unprepare(emc_clk);
> return ret;
> }
>
> @@ -160,7 +158,6 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
> static int tegra_cpu_exit(struct cpufreq_policy *policy)
> {
> clk_disable_unprepare(cpu_clk);
> - clk_disable_unprepare(emc_clk);
> return 0;
> }
>
> @@ -194,19 +191,12 @@ static int __init tegra_cpufreq_init(void)
> if (IS_ERR(pll_p_clk))
> return PTR_ERR(pll_p_clk);
>
> - emc_clk = clk_get_sys("cpu", "emc");
> - if (IS_ERR(emc_clk)) {
> - clk_put(cpu_clk);
> - return PTR_ERR(emc_clk);
> - }
> -
> return cpufreq_register_driver(&tegra_cpufreq_driver);
> }
>
> static void __exit tegra_cpufreq_exit(void)
> {
> cpufreq_unregister_driver(&tegra_cpufreq_driver);
> - clk_put(emc_clk);
> clk_put(cpu_clk);
> }
>
>
[PATCH v14 09/10] ARM: dts: mbimx51sd: Add display support.
On 06/16/2014 12:11 PM, Denis Carikli wrote:> + reg_lcd_3v3: lcd-en {
> +compatible = "regulator-fixed";
> +pinctrl-names = "default";
> +pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
> +regulator-name = "lcd-3v3";
> +regulator-min-microvolt = <330>;
> +regulator-max-microvolt = <330>;
> +gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
> +regulator-boot-on;
> +};
> +};
This is wrong, I'll fix it in the next serie.
What it really does is to make regulator-fixed think that the gpio is
active low, the bindings documentation(fixed-regulator.txt) says:
> - enable-active-high: Polarity of GPIO is Active high
> If this property is missing, the default assumed is Active low.
Then regulator-boot-on will make it think that the regulator is already
on and so the regulator will be disabled.
From the bindings documentation (regulator.txt):
> regulator-boot-on: bootloader/firmware enabled regulator
Which result at the lcd regulator being physically powered on at boot.
I didn't see that because powering it on at boot is what I want.
How can I do that beside doing it in userspace by issuing the following
commands:
echo 4 > /sys/devices/display-subsystem/graphics/fb0/blank
echo 0 > /sys/devices/display-subsystem/graphics/fb0/blank
Denis.
[PATCH v2 1/7] mfd: add atmel-hlcdc driver
Hello Lee,
On 16/06/2014 14:50, Lee Jones wrote:
>> The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
>> family or sama5d3 family) exposes 2 subdevices:
>> - a display controller (controlled by a DRM driver)
>> - a PWM chip
>>
>> Add support for the MFD device which will just retrieve HLCDC clocks and
>> create a regmap so that subdevices can access the HLCDC register range
>> concurrently.
>>
>> Signed-off-by: Boris BREZILLON
>> ---
>> .../devicetree/bindings/mfd/atmel-hlcdc.txt| 41
>> drivers/mfd/Kconfig| 11 ++
>> drivers/mfd/Makefile | 1 +
>> drivers/mfd/atmel-hlcdc.c | 116
>> +
>> include/linux/mfd/atmel-hlcdc.h| 78 ++
>> 5 files changed, 247 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
>> create mode 100644 drivers/mfd/atmel-hlcdc.c
>> create mode 100644 include/linux/mfd/atmel-hlcdc.h
>> diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
>> b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
>> new file mode 100644
>> index 000..f5b69cb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
>> @@ -0,0 +1,41 @@
>> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
>> +
>> +Required properties:
>> + - compatible: value should be one of the following:
>> + "atmel,sama5d3-hlcdc"
>> + - reg: base address and size of the HLCDC device registers.
>> + - clock-names: the name of the 3 clocks requested by the HLCDC device.
>> + Should contain "periph_clk", "sys_clk" and "slow_clk".
>> + - clocks: should contain the 3 clocks requested by the HLCDC device.
>> +
>> +The HLCDC IP exposes two subdevices:
>> + - a PWM chip: see Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
>> + - a Display Controller: see
>> Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
>> +
>> +Example:
>> +
>> +hlcdc: hlcdc at f003 {
>> +compatible = "atmel,sama5d3-hlcdc";
>> +reg = <0xf003 0x2000>;
>> +clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
>> +clock-names = "periph_clk","sys_clk", "slow_clk";
>> +status = "disabled";
> Not sure you really want to disable the the node in the example.
Nope, I'll remove this line.
>> +hlcdc-display-controller {
>> +compatible = "atmel,hlcdc-dc";
>> +interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> I assume you're using the 3rd parameter for flags. If so, please use
> the defines.
No, the third parameter encodes the irq priority (from 0 to 7 IIRC).
>> +pinctrl-names = "default", "rgb-444", "rgb-565",
>> "rgb-666", "rgb-888";
>> +pinctrl-0 = <&pinctrl_lcd_base>;
>> +pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>;
>> +pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
>> +pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb666>;
>> +pinctrl-4 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
>> +};
>> +
>> +hlcdc_pwm: hlcdc-pwm {
>> +compatible = "atmel,hlcdc-pwm";
>> +pinctrl-names = "default";
>> +pinctrl-0 = <&pinctrl_lcd_pwm>;
>> +#pwm-cells = <3>;
>> +};
>> +};
>> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
>> index ee8204c..82777f6 100644
>> --- a/drivers/mfd/Kconfig
>> +++ b/drivers/mfd/Kconfig
>> @@ -59,6 +59,17 @@ config MFD_AAT2870_CORE
>>additional drivers must be enabled in order to use the
>>functionality of the device.
>>
>> +config MFD_ATMEL_HLCDC
>> +tristate "Atmel HLCDC (High LCD Controller)"
> What's the difference between a high and a low controller?
I don't know exactly.
I guess the name changed when the LCD Controller design changed.
Maybe "High-end LCD Controller" would be better...
Nicolas, can you help me on this one ?
>
>> +select MFD_CORE
>> +select REGMAP_MMIO
>> +help
>> + Choose this option if you have an ATMEL SoC with an HLCDC (High
>> + LCD Controller) IP (i.e. at91sam9n12, at91sam9x5 family or sama5d3
>> + family).
>> + This MFD device exposes two subdevices: a PWM chip and a Display
>> + Controller.
>> +
>> config MFD_BCM590XX
>> tristate "Broadcom BCM590xx PMUs"
>> select MFD_CORE
>> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
>> index 8afedba..5f25b0d 100644
>> --- a/drivers/mfd/Makefile
>> +++ b/drivers/mfd/Makefile
>> @@ -156,6 +156,7 @@ obj-$(CONFIG_MFD_PM8921_CORE)+= pm8921-core.o ssbi.o
>> obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
>> obj-$(CONFIG_MFD_TPS65090) += tps65090.o
>> obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
>> +obj-$(CONFIG_MFD_ATMEL_HLCDC)
[RFC PATCH 1/4] memory: tegra124-emc: Add EMC driver
Adds functionality for registering memory bandwidth needs and setting
the EMC clock rate based on that.
Also adds API for setting floor and ceiling frequency rates.
Signed-off-by: Tomeu Vizoso
---
.../bindings/arm/tegra/nvidia,tegra124-emc.txt | 26
drivers/memory/Kconfig | 8 +
drivers/memory/Makefile| 1 +
drivers/memory/tegra124-emc.c | 173 +
include/linux/platform_data/tegra_emc.h| 23 +++
5 files changed, 231 insertions(+)
create mode 100644
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
create mode 100644 drivers/memory/tegra124-emc.c
diff --git
a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
new file mode 100644
index 000..88e6a55
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
@@ -0,0 +1,26 @@
+Tegra124 External Memory Controller
+
+Properties:
+- compatible : Should contain "nvidia,tegra124-emc".
+- reg : Should contain the register range of the device
+- #address-cells : Should be 1
+- #size-cells : Should be 0
+- nvidia,mc : phandle to the mc bus connected to EMC.
+- clocks : phandle to EMC, EMC shared bus override, and all parent clocks.
+- clock-names : name of each clock.
+- nvidia,pmc : phandle to the PMC syscon node.
+- max-clock-frequency : optional, specifies the maximum EMC rate in kHz.
+
+Child device nodes describe the memory settings for different configurations
and
+clock rates.
+
+Example:
+
+ memory-controller at 7001b000 {
+ compatible = "nvidia,tegra124-emc";
+ reg = <0x7001b000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA124_CLK_EMC>;
+ clock-names = "emc";
+ };
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index c59e9c9..48fa0dd 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -61,6 +61,14 @@ config TEGRA30_MC
analysis, especially for IOMMU/SMMU(System Memory Management
Unit) module.
+config TEGRA124_EMC
+ tristate "Tegra124 External Memory Controller (EMC) driver"
+ default y
+ depends on ARCH_TEGRA_124_SOC
+ help
+ This driver is for the External Memory Controller (EMC) module
+ available in Tegra124 SoCs.
+
config FSL_IFC
bool
depends on FSL_SOC
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index 71160a2..0b7290b 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
obj-$(CONFIG_TEGRA30_MC) += tegra30-mc.o
+obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
diff --git a/drivers/memory/tegra124-emc.c b/drivers/memory/tegra124-emc.c
new file mode 100644
index 000..b7a54a5
--- /dev/null
+++ b/drivers/memory/tegra124-emc.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see
[RFC PATCH 2/4] ARM: tegra: Add Tegra124 EMC support
Add a device node for the EMC found on Tegra124.
Signed-off-by: Tomeu Vizoso
---
arch/arm/boot/dts/tegra124.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 6e6bc4e..5aa42ff 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -449,6 +449,15 @@
clock-names = "pclk", "clk32k_in";
};
+ memory-controller at 7001b000 {
+ compatible = "nvidia,tegra124-emc";
+ reg = <0x00 0x7001b000 0x00 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car 57>;
+ clock-names = "emc";
+ };
+
sdhci at 0,700b {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b 0x0 0x200>;
--
1.9.3
[PATCH v2 1/7] mfd: add atmel-hlcdc driver
> The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
> family or sama5d3 family) exposes 2 subdevices:
> - a display controller (controlled by a DRM driver)
> - a PWM chip
>
> Add support for the MFD device which will just retrieve HLCDC clocks and
> create a regmap so that subdevices can access the HLCDC register range
> concurrently.
>
> Signed-off-by: Boris BREZILLON
> ---
> .../devicetree/bindings/mfd/atmel-hlcdc.txt| 41
> drivers/mfd/Kconfig| 11 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/atmel-hlcdc.c | 116
> +
> include/linux/mfd/atmel-hlcdc.h| 78 ++
> 5 files changed, 247 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> create mode 100644 drivers/mfd/atmel-hlcdc.c
> create mode 100644 include/linux/mfd/atmel-hlcdc.h
> diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> new file mode 100644
> index 000..f5b69cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> @@ -0,0 +1,41 @@
> +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
> +
> +Required properties:
> + - compatible: value should be one of the following:
> + "atmel,sama5d3-hlcdc"
> + - reg: base address and size of the HLCDC device registers.
> + - clock-names: the name of the 3 clocks requested by the HLCDC device.
> + Should contain "periph_clk", "sys_clk" and "slow_clk".
> + - clocks: should contain the 3 clocks requested by the HLCDC device.
> +
> +The HLCDC IP exposes two subdevices:
> + - a PWM chip: see Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
> + - a Display Controller: see
> Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
> +
> +Example:
> +
> + hlcdc: hlcdc at f003 {
> + compatible = "atmel,sama5d3-hlcdc";
> + reg = <0xf003 0x2000>;
> + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
> + clock-names = "periph_clk","sys_clk", "slow_clk";
> + status = "disabled";
Not sure you really want to disable the the node in the example.
> + hlcdc-display-controller {
> + compatible = "atmel,hlcdc-dc";
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
I assume you're using the 3rd parameter for flags. If so, please use
the defines.
> + pinctrl-names = "default", "rgb-444", "rgb-565",
> "rgb-666", "rgb-888";
> + pinctrl-0 = <&pinctrl_lcd_base>;
> + pinctrl-1 = <&pinctrl_lcd_base &pinctrl_lcd_rgb444>;
> + pinctrl-2 = <&pinctrl_lcd_base &pinctrl_lcd_rgb565>;
> + pinctrl-3 = <&pinctrl_lcd_base &pinctrl_lcd_rgb666>;
> + pinctrl-4 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
> + };
> +
> + hlcdc_pwm: hlcdc-pwm {
> + compatible = "atmel,hlcdc-pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcd_pwm>;
> + #pwm-cells = <3>;
> + };
> + };
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index ee8204c..82777f6 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -59,6 +59,17 @@ config MFD_AAT2870_CORE
> additional drivers must be enabled in order to use the
> functionality of the device.
>
> +config MFD_ATMEL_HLCDC
> + tristate "Atmel HLCDC (High LCD Controller)"
What's the difference between a high and a low controller?
> + select MFD_CORE
> + select REGMAP_MMIO
> + help
> + Choose this option if you have an ATMEL SoC with an HLCDC (High
> + LCD Controller) IP (i.e. at91sam9n12, at91sam9x5 family or sama5d3
> + family).
> + This MFD device exposes two subdevices: a PWM chip and a Display
> + Controller.
> +
> config MFD_BCM590XX
> tristate "Broadcom BCM590xx PMUs"
> select MFD_CORE
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 8afedba..5f25b0d 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -156,6 +156,7 @@ obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o
> obj-$(CONFIG_TPS65911_COMPARATOR)+= tps65911-comparator.o
> obj-$(CONFIG_MFD_TPS65090) += tps65090.o
> obj-$(CONFIG_MFD_AAT2870_CORE) += aat2870-core.o
> +obj-$(CONFIG_MFD_ATMEL_HLCDC)+= atmel-hlcdc.o
> obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
> obj-$(CONFIG_MFD_PALMAS) += palmas.o
> obj-$(CONFIG_MFD_VIPERBOARD)+= viperboard.o
> diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c
> new file mode 100644
> index 000..e4636e8
> --- /dev/null
> +++ b/drivers/mfd/atmel-hlcdc.c
> @@ -0,0 +1,116 @@
> +/*
> + * Copyright (C) 2014 Free Electro
[RFC PATCH 0/4] Tegra124: EMC scaling
Hi, here is an initial implementation of EMC scaling for Tegra124, I'm most interested in feedback on the approach. The present incarnation is very much specific to Tegra, but I'm sure that we could find an API that can be shared across SoC families. I have looked at using existing frameworks (common clock, pm_qos and devfreq) to cover this use case, but it always felt like trying to fit a square peg in a round hole. These are our requirements: 1. Ceiling frequencies (for thermal and other power management components) 2. Floor frequencies (determined from load statistics that are often maintained by some firmware, to avoid frequent interrupts) 3. Let misc. device drivers such as display controllers or USB set their bandwidth requirements, which would be aggregated to calculate the final effective frequency. 4. The EMC on the Tegra124 has per-consumer latency allowance registers that influence how memory access requests are arbitrated, and these depend on the clock frequency. 1 and 2 could be implemented as additions to the common clock framework, but I feel that 3 should live at a higher level (as not all clocks are used to drive memory buses), and 4 doesn't seem related to clocks at all. For past discussions on this see: https://lkml.org/lkml/2014/5/13/469 Tomeu Vizoso (4): memory: tegra124-emc: Add EMC driver ARM: tegra: Add Tegra124 EMC support drm/tegra: Request memory bandwidth for the display controller cpufreq: tegra: Register a minimum EMC frequency based on the CPU clock .../bindings/arm/tegra/nvidia,tegra124-emc.txt | 26 arch/arm/boot/dts/tegra124.dtsi| 9 ++ drivers/cpufreq/tegra-cpufreq.c| 20 +-- drivers/gpu/drm/tegra/dc.c | 9 ++ drivers/memory/Kconfig | 8 + drivers/memory/Makefile| 1 + drivers/memory/tegra124-emc.c | 173 + include/linux/platform_data/tegra_emc.h| 23 +++ 8 files changed, 254 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt create mode 100644 drivers/memory/tegra124-emc.c -- 1.9.3
[RFC PATCH 3/4] drm/tegra: Request memory bandwidth for the display controller
Request it based solely on the current mode's refresh rate. More accurate requirements can be requested in future patches. Signed-off-by: Tomeu Vizoso --- drivers/gpu/drm/tegra/dc.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index ef40381..6739d69 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "dc.h" #include "drm.h" @@ -683,6 +684,8 @@ static void tegra_crtc_disable(struct drm_crtc *crtc) } drm_vblank_off(drm, dc->pipe); + + tegra124_emc_reserve_bandwidth(TEGRA_EMC_CONSUMER_DISP1, 0); } static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, @@ -769,6 +772,7 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc, struct tegra_dc *dc = to_tegra_dc(crtc); struct tegra_dc_window window; u32 value; + unsigned long bandwidth; int err; drm_vblank_pre_modeset(crtc->dev, dc->pipe); @@ -809,6 +813,11 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc, if (err < 0) dev_err(dc->dev, "failed to enable root plane\n"); + bandwidth = mode->clock * window.bits_per_pixel / 8; + err = tegra124_emc_reserve_bandwidth(TEGRA_EMC_CONSUMER_DISP1, bandwidth); + if (err) + dev_err(dc->dev, "failed to reserve EMC bandwidth: %d\n", err); + return 0; } -- 1.9.3
[RFC PATCH 1/4] memory: tegra124-emc: Add EMC driver
It should be mentioned that calling clk_set_rate on the EMC clock
currently does absolutely nothing (except probably returning an error).
The rate switching sequence is not implemented (nor is the clock tree
entirely correct. For example, the kernel thinks that PLL_M is disabled).
Another note: I am currently implementing an actmon driver. I'm not
entirely enthusiastic about the downstream style of managing EMC rate
policy in the actmon driver, but haven't yet given much thought to it.
Yet another note: I think the exported API should not be SoC-specific,
so s/tegra124_/tegra_/.
Thanks,
- Mikko
On 06/16/2014 04:35 PM, Tomeu Vizoso wrote:
> Adds functionality for registering memory bandwidth needs and setting
> the EMC clock rate based on that.
>
> Also adds API for setting floor and ceiling frequency rates.
>
> Signed-off-by: Tomeu Vizoso
> ---
> .../bindings/arm/tegra/nvidia,tegra124-emc.txt | 26
> drivers/memory/Kconfig | 8 +
> drivers/memory/Makefile| 1 +
> drivers/memory/tegra124-emc.c | 173
> +
> include/linux/platform_data/tegra_emc.h| 23 +++
> 5 files changed, 231 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> create mode 100644 drivers/memory/tegra124-emc.c
>
> diff --git
> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> new file mode 100644
> index 000..88e6a55
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> @@ -0,0 +1,26 @@
> +Tegra124 External Memory Controller
> +
> +Properties:
> +- compatible : Should contain "nvidia,tegra124-emc".
> +- reg : Should contain the register range of the device
> +- #address-cells : Should be 1
> +- #size-cells : Should be 0
> +- nvidia,mc : phandle to the mc bus connected to EMC.
> +- clocks : phandle to EMC, EMC shared bus override, and all parent clocks.
> +- clock-names : name of each clock.
> +- nvidia,pmc : phandle to the PMC syscon node.
> +- max-clock-frequency : optional, specifies the maximum EMC rate in kHz.
> +
> +Child device nodes describe the memory settings for different configurations
> and
> +clock rates.
> +
> +Example:
> +
> + memory-controller at 7001b000 {
> + compatible = "nvidia,tegra124-emc";
> + reg = <0x7001b000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&tegra_car TEGRA124_CLK_EMC>;
> + clock-names = "emc";
> + };
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index c59e9c9..48fa0dd 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -61,6 +61,14 @@ config TEGRA30_MC
> analysis, especially for IOMMU/SMMU(System Memory Management
> Unit) module.
>
> +config TEGRA124_EMC
> + tristate "Tegra124 External Memory Controller (EMC) driver"
> + default y
> + depends on ARCH_TEGRA_124_SOC
> + help
> + This driver is for the External Memory Controller (EMC) module
> + available in Tegra124 SoCs.
> +
> config FSL_IFC
> bool
> depends on FSL_SOC
> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> index 71160a2..0b7290b 100644
> --- a/drivers/memory/Makefile
> +++ b/drivers/memory/Makefile
> @@ -11,3 +11,4 @@ obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
> obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
> obj-$(CONFIG_TEGRA20_MC)+= tegra20-mc.o
> obj-$(CONFIG_TEGRA30_MC)+= tegra30-mc.o
> +obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
> diff --git a/drivers/memory/tegra124-emc.c b/drivers/memory/tegra124-emc.c
> new file mode 100644
> index 000..b7a54a5
> --- /dev/null
> +++ b/drivers/memory/tegra124-emc.c
> @@ -0,0 +1,173 @@
> +/*
> + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see
[PATCH v2 1/7] mfd: add atmel-hlcdc driver
On 16/06/2014 19:03, Lee Jones wrote:
> On Mon, 16 Jun 2014, Boris BREZILLON wrote:
>> On 16/06/2014 14:50, Lee Jones wrote:
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
Add support for the MFD device which will just retrieve HLCDC clocks and
create a regmap so that subdevices can access the HLCDC register range
concurrently.
Signed-off-by: Boris BREZILLON
---
.../devicetree/bindings/mfd/atmel-hlcdc.txt| 41
drivers/mfd/Kconfig| 11 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/atmel-hlcdc.c | 116
+
include/linux/mfd/atmel-hlcdc.h| 78 ++
5 files changed, 247 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
create mode 100644 drivers/mfd/atmel-hlcdc.c
create mode 100644 include/linux/mfd/atmel-hlcdc.h
diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
new file mode 100644
index 000..f5b69cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> [...]
>
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-dc";
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
>>> I assume you're using the 3rd parameter for flags. If so, please use
>>> the defines.
>> No, the third parameter encodes the irq priority (from 0 to 7 IIRC).
> Ah okay. Can you point me to the documentation for this IRQ
> controller please? I'd like to have a quick peek. It might be worth
> defining the priority to prevent confusion, also you definitely should
> document it in your binding.
Here's Atmel's irq chip DT bindings documentation:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/arm/atmel-aic.txt
I'll describe interrupt fields in the HLCDC DT bindings doc.
>
> [...]
>
+static struct platform_driver atmel_hlcdc_driver = {
+ .probe = atmel_hlcdc_probe,
+ .remove = atmel_hlcdc_remove,
+ .driver = {
+ .name = "atmel-hlcdc",
+ .owner = THIS_MODULE,
+ .of_match_table = atmel_hlcdc_match,
>>> Is this driver DT only?
>> Yes it is.
> So it should depend on OF in the Kconfig entry.
>
Absolutely, I'll add the dependency.
Thanks,
Boris
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[PATCH v2 1/7] mfd: add atmel-hlcdc driver
On Mon, 16 Jun 2014, Boris BREZILLON wrote:
> On 16/06/2014 14:50, Lee Jones wrote:
> >> The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
> >> family or sama5d3 family) exposes 2 subdevices:
> >> - a display controller (controlled by a DRM driver)
> >> - a PWM chip
> >>
> >> Add support for the MFD device which will just retrieve HLCDC clocks and
> >> create a regmap so that subdevices can access the HLCDC register range
> >> concurrently.
> >>
> >> Signed-off-by: Boris BREZILLON
> >> ---
> >> .../devicetree/bindings/mfd/atmel-hlcdc.txt| 41
> >> drivers/mfd/Kconfig| 11 ++
> >> drivers/mfd/Makefile | 1 +
> >> drivers/mfd/atmel-hlcdc.c | 116
> >> +
> >> include/linux/mfd/atmel-hlcdc.h| 78 ++
> >> 5 files changed, 247 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >> create mode 100644 drivers/mfd/atmel-hlcdc.c
> >> create mode 100644 include/linux/mfd/atmel-hlcdc.h
> >> diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >> b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
> >> new file mode 100644
> >> index 000..f5b69cb
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt
[...]
> >> + hlcdc-display-controller {
> >> + compatible = "atmel,hlcdc-dc";
> >> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> > I assume you're using the 3rd parameter for flags. If so, please use
> > the defines.
>
> No, the third parameter encodes the irq priority (from 0 to 7 IIRC).
Ah okay. Can you point me to the documentation for this IRQ
controller please? I'd like to have a quick peek. It might be worth
defining the priority to prevent confusion, also you definitely should
document it in your binding.
[...]
> >> +static struct platform_driver atmel_hlcdc_driver = {
> >> + .probe = atmel_hlcdc_probe,
> >> + .remove = atmel_hlcdc_remove,
> >> + .driver = {
> >> + .name = "atmel-hlcdc",
> >> + .owner = THIS_MODULE,
> >> + .of_match_table = atmel_hlcdc_match,
> > Is this driver DT only?
>
> Yes it is.
So it should depend on OF in the Kconfig entry.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
[Bug 78111] APU turbo core boost not working when radeon.dpm=1
https://bugzilla.kernel.org/show_bug.cgi?id=78111 Kertesz Laszlo changed: What|Removed |Added CC||laszlo.kertesz at gmail.com --- Comment #3 from Kertesz Laszlo --- I reported basicalle the same thing in bug #62861. How dangerous can this change be? As in would i have to worry about frying the APU? -- You are receiving this mail because: You are watching the assignee of the bug.
[PATCH] drm/msm: update and activate iommu support
This changes activates the iommu support for MDP5, through the
platform config structure.
Iommu support is also slightly modified in order to make sure
that MDP iommu is properly cleaned up if a probe deferral is
requested. Before this change, IOMMU faults would occur if the
probe failed (-EPROBE_DEFER).
Signed-off-by: Stephane Viau
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 28 +++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 6 ++
drivers/gpu/drm/msm/msm_iommu.c | 21 +++--
drivers/gpu/drm/msm/msm_mmu.h | 1 +
5 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 2967b19..62ee5cd 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
@@ -20,6 +20,10 @@
#include "msm_mmu.h"
#include "mdp5_kms.h"
+static const char *iommu_ports[] = {
+ "mdp_0",
+};
+
static struct mdp5_platform_config *mdp5_get_config(struct platform_device
*dev);
uint32_t __read_mostly _mdp5_pipe_vig_base;
@@ -201,6 +205,12 @@ static void mdp5_preclose(struct msm_kms *kms, struct
drm_file *file)
static void mdp5_destroy(struct msm_kms *kms)
{
struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
+ struct msm_mmu *mmu = mdp5_kms->mmu;
+
+ if (mmu) {
+ mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
+ mmu->funcs->destroy(mmu);
+ }
kfree(mdp5_kms);
}
@@ -313,10 +323,6 @@ fail:
return ret;
}
-static const char *iommu_ports[] = {
- "mdp_0",
-};
-
static int get_clk(struct platform_device *pdev, struct clk **clkp,
const char *name)
{
@@ -406,17 +412,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
mmu = msm_iommu_new(dev, config->iommu);
if (IS_ERR(mmu)) {
ret = PTR_ERR(mmu);
+ dev_err(dev->dev, "failed to init iommu: %d\n", ret);
goto fail;
}
+
ret = mmu->funcs->attach(mmu, iommu_ports,
ARRAY_SIZE(iommu_ports));
- if (ret)
+ if (ret) {
+ dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
+ mmu->funcs->destroy(mmu);
goto fail;
+ }
} else {
dev_info(dev->dev, "no iommu, fallback to phys "
"contig buffers for scanout\n");
mmu = NULL;
}
+ mdp5_kms->mmu = mmu;
mdp5_kms->id = msm_register_mmu(dev, mmu);
if (mdp5_kms->id < 0) {
@@ -445,5 +457,11 @@ static struct mdp5_platform_config *mdp5_get_config(struct
platform_device *dev)
#ifdef CONFIG_OF
/* TODO */
#endif
+ config.iommu = iommu_domain_alloc(&platform_bus_type, 0);
+ /* TODO hard-coded in downstream mdss, but should it be? */
+ config.max_clk = 2;
+ /* TODO get from DT: */
+ config.smp_blk_cnt = 22;
+
return &config;
}
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
index 6a89b04..20ea748 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
@@ -41,6 +41,7 @@ struct mdp5_kms {
/* mapper-id used to request GEM buffer mapped for scanout: */
int id;
+ struct msm_mmu *mmu;
/* for tracking smp allocation amongst pipes: */
mdp5_smp_state_t smp_state;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index bb8026d..690d7e7 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -278,6 +278,7 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj, int
id,
uint32_t *iova)
{
struct msm_gem_object *msm_obj = to_msm_bo(obj);
+ struct drm_device *dev = obj->dev;
int ret = 0;
if (!msm_obj->domain[id].iova) {
@@ -285,6 +286,11 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj,
int id,
struct msm_mmu *mmu = priv->mmus[id];
struct page **pages = get_pages(obj);
+ if (!mmu) {
+ dev_err(dev->dev, "null MMU pointer\n");
+ return -EINVAL;
+ }
+
if (IS_ERR(pages))
return PTR_ERR(pages);
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 92b7459..198b2fe 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -28,7 +28,7 @@ static int msm_fault_handler(struct iommu_domain *iommu,
struct device *dev,
unsigned long iova, int flags, void *arg)
{
DBG("*** fault: iova=%08lx, flags=%d", iova, flags);
-
[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33
https://bugs.freedesktop.org/show_bug.cgi?id=72921 --- Comment #17 from Collin --- (In reply to comment #16) > Created attachment 101179 [details] [review] > possible fix > > Maybe there is some problem with the clocks or voltage in the highest power > level. Does the attached patch help? Where and how do I apply this patch to... wherever it's supposed to go? And will it work on a Richland APU? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/dc2077a4/attachment.html>
[Bug 75917] backlight switches off when starting X - since kernel-3.13
https://bugs.freedesktop.org/show_bug.cgi?id=75917 --- Comment #15 from sfievet --- I just applied the fixed against 3.15.0, and it does work as reported. The 5s delay at X startup is a bit annoying but acceptable... In my case it actually happens twice : - at X startup - at session start (presumably when the XFCE power manager tool starts up) Thank you for helping us out -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/7f01e239/attachment.html>
[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33
https://bugs.freedesktop.org/show_bug.cgi?id=72921 --- Comment #18 from Alex Deucher --- (In reply to comment #17) > (In reply to comment #16) > > Created attachment 101179 [details] [review] [review] > > possible fix > > > > Maybe there is some problem with the clocks or voltage in the highest power > > level. Does the attached patch help? > > Where and how do I apply this patch to... wherever it's supposed to go? And > will it work on a Richland APU? It applies to the kernel. You need to apply the patch and build and install the kernel. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/46aa9a14/attachment.html>
[Bug 72921] DPM Power Cycle with AMD A8-6600K & MSI FM2-A55M-E33
https://bugs.freedesktop.org/show_bug.cgi?id=72921 --- Comment #19 from Alex Deucher --- Created attachment 101191 --> https://bugs.freedesktop.org/attachment.cgi?id=101191&action=edit testing patch Here's another kernel patch to try. Please try this independent of any other patches on this bug. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/76f508d1/attachment.html>
[Bug 78111] APU turbo core boost not working when radeon.dpm=1
https://bugzilla.kernel.org/show_bug.cgi?id=78111 --- Comment #4 from Alex Deucher --- You may get system or GPU hangs, but it shouldn't fry anything. -- You are receiving this mail because: You are watching the assignee of the bug.
[RFC PATCH 1/4] memory: tegra124-emc: Add EMC driver
On 06/16/2014 07:35 AM, Tomeu Vizoso wrote:
> Adds functionality for registering memory bandwidth needs and setting
> the EMC clock rate based on that.
>
> Also adds API for setting floor and ceiling frequency rates.
> diff --git
> a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> new file mode 100644
> index 000..88e6a55
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra124-emc.txt
> @@ -0,0 +1,26 @@
> +Tegra124 External Memory Controller
> +
> +Properties:
> +- compatible : Should contain "nvidia,tegra124-emc".
> +- reg : Should contain the register range of the device
> +- #address-cells : Should be 1
> +- #size-cells : Should be 0
> +- nvidia,mc : phandle to the mc bus connected to EMC.
> +- clocks : phandle to EMC, EMC shared bus override, and all parent clocks.
> +- clock-names : name of each clock.
> +- nvidia,pmc : phandle to the PMC syscon node.
> +- max-clock-frequency : optional, specifies the maximum EMC rate in kHz.
> +
> +Child device nodes describe the memory settings for different configurations
> and
> +clock rates.
How do the child nodes do that? The binding needs to specify the format
of the child node. This binding looks quite anaemic vs.
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt; I
would expect that this binding needs all the EMC register data from the
tegra20-emc binding too. Can the two bindings be identical?
Can you explain what the nvidia,mc and nvidia,pmc references are needed
for? Hopefully, this driver isn't going to reach into those devices and
touch their registers directly.
> diff --git a/include/linux/platform_data/tegra_emc.h
> b/include/linux/platform_data/tegra_emc.h
A header file that defines platform data format isn't the correct place
to put the definitions of public APIs. I'd expect something more like
.
> +#ifdef CONFIG_TEGRA124_EMC
> +int tegra124_emc_reserve_bandwidth(unsigned int consumer, unsigned long
> rate);
> +void tegra124_emc_set_floor(unsigned long freq);
> +void tegra124_emc_set_ceiling(unsigned long freq);
> +#else
> +int tegra124_emc_reserve_bandwidth(unsigned int consumer, unsigned long rate)
> +{ return -ENODEV; }
> +void tegra124_emc_set_floor(unsigned long freq)
> +{ return; }
> +void tegra124_emc_set_ceiling(unsigned long freq)
> +{ return; }
> +#endif
I'll repeat what I said off-list so that we can have the whole
conversation on the list:
That looks like a custom Tegra-specific API. I think it'd be much better
to integrate this into the common clock framework as a standard clock
constraints API. There are other use-cases for clock constraints besides
EMC scaling (e.g. some in audio on Tegra, and I'm sure many on other
SoCs too).
See https://lkml.org/lkml/2014/5/16/569 for some previous discussion on
this topic.
[RFC PATCH 3/4] drm/tegra: Request memory bandwidth for the display controller
On 06/16/2014 07:35 AM, Tomeu Vizoso wrote: > Request it based solely on the current mode's refresh rate. More > accurate requirements can be requested in future patches. > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > + bandwidth = mode->clock * window.bits_per_pixel / 8; > + err = tegra124_emc_reserve_bandwidth(TEGRA_EMC_CONSUMER_DISP1, > bandwidth); DISP1 shouldn't be hard-coded here; the code should use DISP1 or DISP2 based on head or DC identity. We certainly have some boards capable of dual-head operation.
[PATCH] drm/msm: update and activate iommu support
On Mon, Jun 16, 2014 at 2:20 PM, Stephane Viau wrote:
> This changes activates the iommu support for MDP5, through the
> platform config structure.
>
> Iommu support is also slightly modified in order to make sure
> that MDP iommu is properly cleaned up if a probe deferral is
> requested. Before this change, IOMMU faults would occur if the
> probe failed (-EPROBE_DEFER).
So, this looks like it is really two patches.. one making
-EPROBE_DEFER work properly, and the other adding the missing bits for
mdp5 which so far are only on downstream kernel.
Could you split this patch into two, so I can queue the -EPROBE_DEFER
fix for a 3.16 -fixes pull req?
BR,
-R
> Signed-off-by: Stephane Viau
> ---
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 28 +++-
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 +
> drivers/gpu/drm/msm/msm_gem.c | 6 ++
> drivers/gpu/drm/msm/msm_iommu.c | 21 +++--
> drivers/gpu/drm/msm/msm_mmu.h | 1 +
> 5 files changed, 50 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> index 2967b19..62ee5cd 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> @@ -20,6 +20,10 @@
> #include "msm_mmu.h"
> #include "mdp5_kms.h"
>
> +static const char *iommu_ports[] = {
> + "mdp_0",
> +};
> +
> static struct mdp5_platform_config *mdp5_get_config(struct platform_device
> *dev);
>
> uint32_t __read_mostly _mdp5_pipe_vig_base;
> @@ -201,6 +205,12 @@ static void mdp5_preclose(struct msm_kms *kms, struct
> drm_file *file)
> static void mdp5_destroy(struct msm_kms *kms)
> {
> struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
> + struct msm_mmu *mmu = mdp5_kms->mmu;
> +
> + if (mmu) {
> + mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
> + mmu->funcs->destroy(mmu);
> + }
> kfree(mdp5_kms);
> }
>
> @@ -313,10 +323,6 @@ fail:
> return ret;
> }
>
> -static const char *iommu_ports[] = {
> - "mdp_0",
> -};
> -
> static int get_clk(struct platform_device *pdev, struct clk **clkp,
> const char *name)
> {
> @@ -406,17 +412,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
> mmu = msm_iommu_new(dev, config->iommu);
> if (IS_ERR(mmu)) {
> ret = PTR_ERR(mmu);
> + dev_err(dev->dev, "failed to init iommu: %d\n", ret);
> goto fail;
> }
> +
> ret = mmu->funcs->attach(mmu, iommu_ports,
> ARRAY_SIZE(iommu_ports));
> - if (ret)
> + if (ret) {
> + dev_err(dev->dev, "failed to attach iommu: %d\n",
> ret);
> + mmu->funcs->destroy(mmu);
> goto fail;
> + }
> } else {
> dev_info(dev->dev, "no iommu, fallback to phys "
> "contig buffers for scanout\n");
> mmu = NULL;
> }
> + mdp5_kms->mmu = mmu;
>
> mdp5_kms->id = msm_register_mmu(dev, mmu);
> if (mdp5_kms->id < 0) {
> @@ -445,5 +457,11 @@ static struct mdp5_platform_config
> *mdp5_get_config(struct platform_device *dev)
> #ifdef CONFIG_OF
> /* TODO */
> #endif
> + config.iommu = iommu_domain_alloc(&platform_bus_type, 0);
> + /* TODO hard-coded in downstream mdss, but should it be? */
> + config.max_clk = 2;
> + /* TODO get from DT: */
> + config.smp_blk_cnt = 22;
> +
> return &config;
> }
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
> index 6a89b04..20ea748 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
> @@ -41,6 +41,7 @@ struct mdp5_kms {
>
> /* mapper-id used to request GEM buffer mapped for scanout: */
> int id;
> + struct msm_mmu *mmu;
>
> /* for tracking smp allocation amongst pipes: */
> mdp5_smp_state_t smp_state;
> diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
> index bb8026d..690d7e7 100644
> --- a/drivers/gpu/drm/msm/msm_gem.c
> +++ b/drivers/gpu/drm/msm/msm_gem.c
> @@ -278,6 +278,7 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj,
> int id,
> uint32_t *iova)
> {
> struct msm_gem_object *msm_obj = to_msm_bo(obj);
> + struct drm_device *dev = obj->dev;
> int ret = 0;
>
> if (!msm_obj->domain[id].iova) {
> @@ -285,6 +286,11 @@ int msm_gem_get_iova_locked(struct drm_gem_object *obj,
> int id,
> struct msm_mmu *mmu = priv->mmus[id];
> struct page **pages = get_pages(obj);
>
> + if (!mmu) {
> +
[Bug 80004] Serious Sam 3 BFE - incorrect weapon rendering
https://bugs.freedesktop.org/show_bug.cgi?id=80004 --- Comment #4 from Vitaliy Filippov --- Anyone? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/2365ec18/attachment.html>
[PATCH] imx-drm: imx-hdmi: fix hdmi hotplug detection initial state
On Mon, Jun 16, 2014 at 11:13:02AM -0300, Fabio Estevam wrote:
> On Wed, Jun 11, 2014 at 5:17 AM, Russell King - ARM Linux
> wrote:
>
> > The problem here is that we need more inteligence from CCF in order to
> > do that - we need it to be able to reprogram the dividers so that the
> > IPU DI0 clock remains at 148.5MHz while increasing the output of
> > pll5_video_div three-fold.
> >
> > Another solution would be to source the LDB clock from PLL3 at 480MHz,
> > this gives a pixel clock of 68.6MHz (3sf). The other options are
>
> Ok, I have tried this approach:
>
> --- a/arch/arm/mach-imx/clk-imx6q.c
> +++ b/arch/arm/mach-imx/clk-imx6q.c
> @@ -441,8 +441,8 @@ static void __init imx6q_clocks_init(struct device_node
> *ccm
>
> if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
> cpu_is_imx6dl()) {
> - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
> - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
> + clk_set_parent(clk[ldb_di0_sel], clk[pll3_usb_otg]);
> + clk_set_parent(clk[ldb_di1_sel], clk[pll3_usb_otg]);
> }
>
> and it allows HDMI and LVDS to be displayed if I boot with the HDMI
> kernel connected. Would this be an acceptable solution in the
> meantime?
I have no objection to that as an interim solution, but it does leave
me wondering whether this causes LDB to change the USB OTG clocks.
Might it be worth printing something, just in case someone finds
USB OTG breaks and wonders why?
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
[PATCH 1/2] drm/radeon: update mode_valid testing for DP
When we have a passive adapter validate the clocks
against the HMDI/DVI limits.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_connectors.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 933c5c3..cfb2c8f 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1549,6 +1549,8 @@ out:
static int radeon_dp_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
struct radeon_connector *radeon_connector =
to_radeon_connector(connector);
struct radeon_connector_atom_dig *radeon_dig_connector =
radeon_connector->con_priv;
@@ -1579,14 +1581,23 @@ static int radeon_dp_mode_valid(struct drm_connector
*connector,
return MODE_PANEL;
}
}
- return MODE_OK;
} else {
if ((radeon_dig_connector->dp_sink_type ==
CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
- (radeon_dig_connector->dp_sink_type ==
CONNECTOR_OBJECT_ID_eDP))
+ (radeon_dig_connector->dp_sink_type ==
CONNECTOR_OBJECT_ID_eDP)) {
return radeon_dp_mode_valid_helper(connector, mode);
- else
- return MODE_OK;
+ } else {
+ if (ASIC_IS_DCE6(rdev) &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
+ /* HDMI 1.3+ supports max clock of 340 Mhz */
+ if (mode->clock > 34)
+ return MODE_CLOCK_HIGH;
+ } else {
+ if (mode->clock > 165000)
+ return MODE_CLOCK_HIGH;
+ }
+ }
}
+
+ return MODE_OK;
}
static const struct drm_connector_helper_funcs
radeon_dp_connector_helper_funcs = {
--
1.8.3.1
[PATCH 2/2] drm/radeon: improve dvi_mode_valid
Make sure we have an HDMI monitor before validating modes with
clocks >165 Mhz on single link connections.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_connectors.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index cfb2c8f..1b9177e 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1288,17 +1288,15 @@ static int radeon_dvi_mode_valid(struct drm_connector
*connector,
(radeon_connector->connector_object_id ==
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
(radeon_connector->connector_object_id ==
CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
return MODE_OK;
- else if (radeon_connector->connector_object_id ==
CONNECTOR_OBJECT_ID_HDMI_TYPE_A) {
- if (ASIC_IS_DCE6(rdev)) {
- /* HDMI 1.3+ supports max clock of 340 Mhz */
- if (mode->clock > 34)
- return MODE_CLOCK_HIGH;
- else
- return MODE_OK;
- } else
+ else if (ASIC_IS_DCE6(rdev) &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
+ /* HDMI 1.3+ supports max clock of 340 Mhz */
+ if (mode->clock > 34)
return MODE_CLOCK_HIGH;
- } else
+ else
+ return MODE_OK;
+ } else {
return MODE_CLOCK_HIGH;
+ }
}
/* check against the max pixel clock */
--
1.8.3.1
i915 power management documentation
thanks. Same with INSTDONE registers? GEN7 seems to have 4 x 32 bit INSTDONE registers, but not even intel gpu tools can decode them. Coudnt find anything in the registers reference docs. BR, Gabor 2014-06-02 19:02 GMT+02:00 Sylvain BERTRAND : > On Mon, Jun 02, 2014 at 06:45:59PM +0200, Daniel Vetter wrote: > > The hw guys don't yet allow us to publish docs for this. We're working on > > it. For now your best guess is to look at the code or ask around on the > > #intel-gfx irc channel. > > Fear of US patent trolls? > > regards, > > -- > Sylvain > -- next part -- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/dri-devel/attachments/20140616/a05873ff/attachment.html>
