[Bug 65761] HD 7970M Hybrid - hangs and errors and rmmod causes crash

2013-12-07 Thread bugzilla-dae...@bugzilla.kernel.org 
https://bugzilla.kernel.org/show_bug.cgi?id=65761

--- Comment #6 from Christoph Haag  ---
Created attachment 117761
  --> https://bugzilla.kernel.org/attachment.cgi?id=117761&action=edit
dmesg with drm-fixes-3.12-radeon-poweroff branch

Hm, I think it kind of works with drm-fixes-3.12-radeon-poweroff.

There seems to be no error in dmesg and X works fine.


I have monitored /sys/kernel/debug/vgaswitcheroo/switch a while.

Unfortunately most of the time it says
0:IGD:+:Pwr::00:02.0
1:DIS: :DynPwr::01:00.0

I have seen it say
0:IGD:+:Pwr::00:02.0
1:DIS: :DynOff::01:00.0
But I don't know really know how I got it to switch and whether it was
something I did at all.

Then, unprovoked, it switched to on ("DynPwr") again.
(There's nothing running on the radeon GPU, only X with xcompmgr on intel and
radeon is configured as provideroffloadsink)


I don't know how to coax it to power the gpu off. But at least it CAN work
already.




Maybe this is useful, maybe not:
With the radeon in idle I have this:
$ cat /sys/kernel/debug/dri/1/radeon_pm_info
uvdvclk: 0 dclk: 0
power level 0sclk: 3 mclk: 15000 vddc: 825 vddci: 850 pcie gen: 3

with glxgears I have this:
$ cat /sys/kernel/debug/dri/1/radeon_pm_info
uvdvclk: 0 dclk: 0
power level 2sclk: 85000 mclk: 12 vddc: 1050 vddci: 975 pcie gen: 3

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[Bug 65761] HD 7970M Hybrid - hangs and errors and rmmod causes crash

2013-12-07 Thread bugzilla-dae...@bugzilla.kernel.org 
https://bugzilla.kernel.org/show_bug.cgi?id=65761

--- Comment #7 from Christoph Haag  ---
Created attachment 117771
  --> https://bugzilla.kernel.org/attachment.cgi?id=117771&action=edit
Same as "117761: dmesg with drm-fixes-3.12-radeon-poweroff branch", but with
rmmod radeon and modprobe radeon

Okay, I exited X and from a tty did rmmod radeon. It produced the same error in
dmesg than it does on 3.13, see attached file...

Then with modprobe radeon I got the GPU lockup CP stall for more than
1msec, but interestingly only once and then it worked.

The radeon gpu was at DynOff then.

As soon as I started X, the gpu was powered on to DynPwr again. Not even
configured as provideroffloadsink or so, just the X startup and presumably
hardware detection powered it up and it does not go back to DynOff.

But again, knowing that runpm itself works without errors is encouraging.

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[Bug 72425] New: divide by zero error in radeon_surface.c when opening chrome with WebGL enabled

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=72425

  Priority: medium
Bug ID: 72425
  Assignee: dri-devel at lists.freedesktop.org
   Summary: divide by zero error in radeon_surface.c when opening
chrome with WebGL enabled
  Severity: normal
Classification: Unclassified
OS: All
  Reporter: crwulff at gmail.com
  Hardware: Other
Status: NEW
   Version: unspecified
 Component: libdrm
   Product: DRI

Created attachment 90384
  --> https://bugs.freedesktop.org/attachment.cgi?id=90384&action=edit
Fix divide by zero in radeon_surface

Passing a tile_split of zero to eg_surface_init_2d causes a divide by zero
error. Launching chromium with WebGL enabled on a AMD Llano (A8-3850) exhibits
this behavior and webgl then fails to work. The attached patch fixes the
problem and allows WebGL to work in chrome on this platform.

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[Bug 72369] glitches in serious sam 3 with the sb shader backend

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=72369

--- Comment #2 from Vadim Girlin  ---
Created attachment 90386
  --> https://bugs.freedesktop.org/attachment.cgi?id=90386&action=edit
patch

Does this patch help?

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[Bug 72369] glitches in serious sam 3 with the sb shader backend

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=72369

--- Comment #3 from Andre Heider  ---
Yes it does, thanks Vadim!

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[Bug 65771] Oops after starting nouveau with NVAA / NV50 (Nvidia 8200)

2013-12-07 Thread bugzilla-dae...@bugzilla.kernel.org 
https://bugzilla.kernel.org/show_bug.cgi?id=65771

--- Comment #3 from dirk.neukirchen at student.hu-berlin.de ---
the card does come up after adding

drm/nouveau/clk: Add support for NVAA/NVAC

http://cgit.freedesktop.org/nouveau/linux-2.6/commit/?h=drm-nouveau-next&id=a7e4201f0f7d47e03b851f06f8987856e8d33083

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[PATCH] drm/edid: add quirk for BPC in Samsung NP700G7A-S01PL notebook

2013-12-07 Thread Rafał Miłecki 
This bug in EDID was exposed by:

commit eccea7920cfb009c2fa40e9ecdce8c36f61cab66
Author: Alex Deucher 
Date:   Mon Mar 26 15:12:54 2012 -0400

drm/radeon/kms: improve bpc handling (v2)

Which resulted in kind of regression in 3.5. This fixes
https://bugs.freedesktop.org/show_bug.cgi?id=70934

Signed-off-by: Rafa? Mi?ecki 
Cc: stable at vger.kernel.org
---
 drivers/gpu/drm/drm_edid.c |8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f1764ec..a1b4f2b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -68,6 +68,8 @@
 #define EDID_QUIRK_DETAILED_SYNC_PP(1 << 6)
 /* Force reduced-blanking timings for detailed modes */
 #define EDID_QUIRK_FORCE_REDUCED_BLANKING  (1 << 7)
+/* Force 8bpc */
+#define EDID_QUIRK_FORCE_8BPC  (1 << 8)

 struct detailed_mode_closure {
struct drm_connector *connector;
@@ -128,6 +130,9 @@ static struct edid_quirk {

/* Medion MD 30217 PG */
{ "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
+
+   /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
+   { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
 };

 /*
@@ -3421,6 +3426,9 @@ int drm_add_edid_modes(struct drm_connector *connector, 
struct edid *edid)

drm_add_display_info(edid, &connector->display_info);

+   if (quirks & EDID_QUIRK_FORCE_8BPC)
+   connector->display_info.bpc = 8;
+
return num_modes;
 }
 EXPORT_SYMBOL(drm_add_edid_modes);
-- 
1.7.10.4

[PATCH] drm/nouveau/falcon: use vmalloc to create firwmare copies

2013-12-07 Thread Ilia Mirkin 
Some firmware images may be large (64K), so using kmalloc memory is
inappropriate for them. Use vmalloc instead, to avoid high-order
allocation failures.

Signed-off-by: Ilia Mirkin 
Cc: stable at vger.kernel.org
---

Couldn't get video decoding started on a long-running system due to high-order
allocation failures. This seems like a fine use-case for vmalloc.

 drivers/gpu/drm/nouveau/core/engine/falcon.c | 20 +++-
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c 
b/drivers/gpu/drm/nouveau/core/engine/falcon.c
index e03fc8e..5e077e4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/falcon.c
+++ b/drivers/gpu/drm/nouveau/core/engine/falcon.c
@@ -56,6 +56,16 @@ _nouveau_falcon_wr32(struct nouveau_object *object, u64 
addr, u32 data)
nv_wr32(falcon, falcon->addr + addr, data);
 }

+static void *
+vmemdup(const void *src, size_t len)
+{
+   void *p = vmalloc(len);
+
+   if (p)
+   memcpy(p, src, len);
+   return p;
+}
+
 int
 _nouveau_falcon_init(struct nouveau_object *object)
 {
@@ -111,7 +121,7 @@ _nouveau_falcon_init(struct nouveau_object *object)

ret = request_firmware(&fw, name, &device->pdev->dev);
if (ret == 0) {
-   falcon->code.data = kmemdup(fw->data, fw->size, 
GFP_KERNEL);
+   falcon->code.data = vmemdup(fw->data, fw->size);
falcon->code.size = fw->size;
falcon->data.data = NULL;
falcon->data.size = 0;
@@ -134,7 +144,7 @@ _nouveau_falcon_init(struct nouveau_object *object)
return ret;
}

-   falcon->data.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
+   falcon->data.data = vmemdup(fw->data, fw->size);
falcon->data.size = fw->size;
release_firmware(fw);
if (!falcon->data.data)
@@ -149,7 +159,7 @@ _nouveau_falcon_init(struct nouveau_object *object)
return ret;
}

-   falcon->code.data = kmemdup(fw->data, fw->size, GFP_KERNEL);
+   falcon->code.data = vmemdup(fw->data, fw->size);
falcon->code.size = fw->size;
release_firmware(fw);
if (!falcon->code.data)
@@ -235,8 +245,8 @@ _nouveau_falcon_fini(struct nouveau_object *object, bool 
suspend)
if (!suspend) {
nouveau_gpuobj_ref(NULL, &falcon->core);
if (falcon->external) {
-   kfree(falcon->data.data);
-   kfree(falcon->code.data);
+   vfree(falcon->data.data);
+   vfree(falcon->code.data);
falcon->code.data = NULL;
}
}
-- 
1.8.3.2

[Bug 72387] Tearing at one specific part of the screen on CAYMAN

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=72387

--- Comment #2 from Kai  ---
Created attachment 90433
  --> https://bugs.freedesktop.org/attachment.cgi?id=90433&action=edit
dmesg output for DRM/radeon

I'm seeing this too with a PITCAIRN chip (stack detailed below). Though the
tearing (one, 27" monitor with 2560x1440, KDE 4.11, composited) appears like
five ccentimeters from the top whenever there is fast movement or quick image
changes. I'm not seeing this with Catalyst.

(Sorry for not reporting this earlier, but I totally forgot to.)

No error/warning (except not finding some cyrillic font) is logged to
Xorg.0.log ? do you still want to have it?

Stack used:
GPU: "PITCAIRN" (ChipID = 0x6819)
Linux: 3.12.1
libdrm: 2.4.49-2 (Debian package)
LLVM: SVN:trunk/r195435
libclc: Git:master/8e0ea3a263
Mesa: Git:master/aad2511c6d
GLAMOR: Git:master/b418b13126
DDX: Git:master/d571d6af70
KWin: 4.11.3-2 (Debian package)

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[Bug 70706] Regression in fbconfig

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=70706

Dieter N?tzel  changed:

   What|Removed |Added

 CC||dri-devel at lists.freedesktop
   ||.org

--- Comment #7 from Dieter N?tzel  ---
(In reply to comment #5)
> To me this issue seems to appear randomly - sometimes KDE starts with
> working compositing, but most often it does not.

Same, here.
When it starts _with_ compositing, then error message appears.
_Without _ compositing glxinfo runs OK and GL performance is nearly 25% better!

Q3A goes from ~53 fps to 66 fps (640x480 window on 1920x1080 screen) with my
poor Duron 1800/RV730 AGP.

So is there a possibility, that we can disable compositing on the fly, when GL
apps starts?

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[Bug 70706] Regression in fbconfig

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=70706

--- Comment #8 from Dennis Schridde  ---
(In reply to comment #7)
> (In reply to comment #5)
> > To me this issue seems to appear randomly - sometimes KDE starts with
> > working compositing, but most often it does not.
> 
> Same, here.
> When it starts _with_ compositing, then error message appears.
> _Without _ compositing glxinfo runs OK and GL performance is nearly 25%
> better!

In the current session I did not get compositing but the mentioned message in
~/.xession-errors:
kwin(2492): Failed to get visual from fbconfig 
kwin(2492) KWin::OpenGLBackend::setFailed: Creating the OpenGL rendering
failed:  "Could not initialize the buffer" 
kwin(2492): Failed to initialize compositing, compositing disabled 

glxinfo currently does not work, either:
Error: couldn't find RGB GLX visual or fbconfig
Error: couldn't find RGB GLX visual or fbconfig
name of display: :0
[...]

So the current session seems to be a case of "without compositing, with glxinfo
error". Which also seems to make sense: Something is preventing GL apps from
working, which also affects glxinfo.

A quick test shows that EGL does not seem to be affected:
$ eglinfo
EGL API version: 1.4
EGL vendor string: Mesa Project
EGL version string: 1.4 (Gallium)
EGL client APIs: OpenGL OpenGL_ES OpenGL_ES2 
[...]

Also the X11 variants of the *gears (egl,es1,es2) programs work:
$ eglgears_x11 
EGL_VERSION = 1.4 (Gallium)

But the "screen variants do not (though I do not remember ever before testing
them, so I cannot tell whether this is a regression):
$ eglgears_screen 
EGL_VERSION = 1.4 (Gallium)
EGLUT: failed to choose a config

I can confirm this with KWin (stripped from unrelated output):
$ kwin
kwin(3945): Failed to get visual from fbconfig 
kwin(3945) KWin::OpenGLBackend::setFailed: Creating the OpenGL rendering
failed:  "Could not initialize the buffer" 
QObject::connect: Cannot connect (null)::resetCompositing() to
KWin::Compositor::restart()
kwin(3945): Failed to initialize compositing, compositing disabled 
kwin(3945): Consult
http://techbase.kde.org/Projects/KWin/4.0-release-notes#Setting_up 

$ kwin_gles
OpenGL vendor string:   X.Org
OpenGL renderer string: Gallium 0.4 on AMD REDWOOD
OpenGL version string:  OpenGL ES 3.0 Mesa 9.2.4
OpenGL shading language version string: OpenGL ES GLSL ES 3.0
[...]

> So is there a possibility, that we can disable compositing on the fly, when
> GL apps starts?

I think that is a completely unrelated issue that belongs on
https://bugs.kde.org/ and should be reported against KWin.

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[Bug 72457] New: Crash in hwmon_attributes_visible

2013-12-07 Thread bugzilla-dae...@freedesktop.org 
https://bugs.freedesktop.org/show_bug.cgi?id=72457

  Priority: medium
Bug ID: 72457
  Assignee: dri-devel at lists.freedesktop.org
   Summary: Crash in hwmon_attributes_visible
  Severity: normal
Classification: Unclassified
OS: Linux (All)
  Reporter: g02maran at gmail.com
  Hardware: x86-64 (AMD64)
Status: NEW
   Version: XOrg CVS
 Component: DRM/Radeon
   Product: DRI

Created attachment 90435
  --> https://bugs.freedesktop.org/attachment.cgi?id=90435&action=edit
patch

I tried the drm-fixes-3.13 branch but it crashes for me in
hwmon_attributes_visible. If I revert commit
ec39f64bba3421c2060fcbd1aeb6eec81fe0a42d (drm/radeon/dpm: Convert
to use devm_hwmon_register_with_groups) the crash disappears.

The attached patch fixes the issue for me. I only had a problem with the
hwmon_attributes_visible function, but looking at the code it seems to me that
the same fix is needed in radeon_hwmon_show_temp_thresh as well.

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[Bug 66241] radeon fails to initialise the monitor

2013-12-07 Thread bugzilla-dae...@bugzilla.kernel.org 
https://bugzilla.kernel.org/show_bug.cgi?id=66241

Chris Rankin  changed:

   What|Removed |Added

 Kernel Version|3.12.2  |3.12.2,3.12.3

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[PATCH 00/13] drm/msm: apq8060a and apq8x74 support

2013-12-07 Thread Rob Clark 
Here is an early look at what I have lined up so far for 3.14, to give
anyone who might care a chance to review.  The main highlights are:

 + add support for apq8060a/bstem board: mdp4 display controller plus
   a320 gpu, fairly similar to apq8064 but without an IOMMU

 + add support for apq8074/dragonboard: new mdp5 display controller
   plus a330 gpu.  The major difference is the display controller
   block, the gpu is fairly similar (few changes in initialization)

The apq8074 bits manage to get a bit of configuration from DT, since
the downstream kernel for apq8x74 (snapdragon 800) devices is using
DT.  The intention is to introduce properly reviewed and documented
DT bindings in subsequent patches, but (as much as is possible) also
maintain compatibility with downstream android driver bindings, in
order to simplify porting the driver to existing devices.

Still missing for mdp5 (compared to what is already supported in mdp4)
is hwcursor, and plane support.  But hopefully there will be time to
finish up some of that and the DT bindings before 3.14 merge window.

Rob Clark (13):
  drm/msm: COMPILE_TEST support
  drm/msm: add missing MODULE_FIRMWARE()s
  drm/msm: fix bus scaling
  drm/msm: add support for non-IOMMU systems
  drm/msm: add support for msm8060ab/bstem
  drm/msm: move mdp4 -> mdp/mdp4
  drm/msm: resync generated headers
  drm/msm: mdp4_format -> mdp_format
  drm/msm: split out msm_kms.h
  drm/msm: move irq utils to mdp_kms
  drm/msm: add hdmi support for apq8x74/mdp5
  drm/msm: add mdp5/apq8x74
  drm/msm: add a330/apq8x74

 drivers/gpu/drm/msm/Kconfig |3 +-
 drivers/gpu/drm/msm/Makefile|   21 +-
 drivers/gpu/drm/msm/NOTES   |   20 +-
 drivers/gpu/drm/msm/adreno/a2xx.xml.h   |  125 ++-
 drivers/gpu/drm/msm/adreno/a3xx.xml.h   |  116 ++-
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |  190 +++-
 drivers/gpu/drm/msm/adreno/a3xx_gpu.h   |4 +
 drivers/gpu/drm/msm/adreno/adreno_common.xml.h  |  171 ++--
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |   25 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |9 +
 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h |   30 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h   |8 +-
 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h   |8 +-
 drivers/gpu/drm/msm/dsi/sfpb.xml.h  |8 +-
 drivers/gpu/drm/msm/hdmi/hdmi.c |  201 +++--
 drivers/gpu/drm/msm/hdmi/hdmi.h |   38 +-
 drivers/gpu/drm/msm/hdmi/hdmi.xml.h |   83 +-
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c  |   71 ++
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c   |  139 ++-
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c|  157 
 drivers/gpu/drm/msm/hdmi/qfprom.xml.h   |8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 1033 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c|  753 
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c |  303 +++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c |   93 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c |  397 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h |  214 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c   |  253 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 1036 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c|  569 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c |  258 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c |  111 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c |  350 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h |  213 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   |  389 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c |  173 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h |   41 +
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h|   78 ++
 drivers/gpu/drm/msm/mdp/mdp_format.c|   71 ++
 drivers/gpu/drm/msm/mdp/mdp_kms.c   |  144 +++
 drivers/gpu/drm/msm/mdp/mdp_kms.h   |   97 +++
 drivers/gpu/drm/msm/mdp4/mdp4.xml.h | 1061 ---
 drivers/gpu/drm/msm/mdp4/mdp4_crtc.c|  753 
 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c |  305 ---
 drivers/gpu/drm/msm/mdp4/mdp4_format.c  |   72 --
 drivers/gpu/drm/msm/mdp4/mdp4_irq.c |  203 -
 drivers/gpu/drm/msm/mdp4/mdp4_kms.c |  380 
 drivers/gpu/drm/msm/mdp4/mdp4_kms.h |  240 -
 drivers/gpu/drm/msm/mdp4/mdp4_plane.c   |  253 --
 drivers/gpu/drm/msm/msm_drv.c   |  126 ++-
 drivers/gpu/drm/msm/msm_drv.h   |   66 +-
 drivers/gpu/drm/msm/msm_fb.c|1 +
 drivers/gpu/drm/msm/msm_gem.c   |  170 ++--
 drivers/gpu/drm/msm/msm_gem.h   |5 +
 drivers/gpu/drm/msm/msm_gpu.c   |   39 +-
 drivers/gpu/dr

[PATCH 01/13] drm/msm: COMPILE_TEST support

2013-12-07 Thread Rob Clark 
With a simple stub, we can get COMPILE_TEST support.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Kconfig |  3 +--
 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c |  2 --
 drivers/gpu/drm/msm/msm_drv.h   | 11 +++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index f39ab75..bb103fb 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -2,8 +2,7 @@
 config DRM_MSM
tristate "MSM DRM"
depends on DRM
-   depends on ARCH_MSM
-   depends on ARCH_MSM8960
+   depends on (ARCH_MSM && ARCH_MSM8960) || (ARM && COMPILE_TEST)
select DRM_KMS_HELPER
select SHMEM
select TMPFS
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c 
b/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
index 5e0dcae..3799ccc 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
+++ b/drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
@@ -15,8 +15,6 @@
  * this program.  If not, see .
  */

-#include 
-
 #include "mdp4_kms.h"

 #include "drm_crtc.h"
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index d39f086..8823a88 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -31,6 +31,17 @@
 #include 
 #include 

+
+#if defined(CONFIG_ARCH_MSM)
+#  include 
+#elif defined(CONFIG_COMPILE_TEST)
+/* stubs we need for compile-test: */
+static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
+{
+   return NULL;
+}
+#endif
+
 #ifndef CONFIG_OF
 #include 
 #include 
-- 
1.8.4.2

[PATCH 03/13] drm/msm: fix bus scaling

2013-12-07 Thread Rob Clark 
This got a bit broken with original patches when re-arranging things to
move dependencies on mach-msm inside #ifndef OF.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 11 +++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  3 +++
 drivers/gpu/drm/msm/msm_gpu.c   | 20 +---
 drivers/gpu/drm/msm/msm_gpu.h   |  4 
 4 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 035bd13..d9e72a6 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -414,6 +414,9 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
gpu->fast_rate = config->fast_rate;
gpu->slow_rate = config->slow_rate;
gpu->bus_freq  = config->bus_freq;
+#ifdef CONFIG_MSM_BUS_SCALING
+   gpu->bus_scale_table = config->bus_scale_table;
+#endif

DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
@@ -436,12 +439,17 @@ fail:
  * The a3xx device:
  */

+#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
+#  include 
+#endif
+
 static int a3xx_probe(struct platform_device *pdev)
 {
static struct adreno_platform_config config = {};
 #ifdef CONFIG_OF
/* TODO */
 #else
+   struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
uint32_t version = socinfo_get_version();
if (cpu_is_apq8064ab()) {
config.fast_rate = 45000;
@@ -473,6 +481,9 @@ static int a3xx_probe(struct platform_device *pdev)
config.rev = ADRENO_REV(3, 0, 5, 0);

}
+#  ifdef CONFIG_MSM_BUS_SCALING
+   config.bus_scale_table = pdata->bus_scale_table;
+#  endif
 #endif
pdev->dev.platform_data = &config;
a3xx_pdev = pdev;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index f73abfb..451b741 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -70,6 +70,9 @@ struct adreno_gpu {
 struct adreno_platform_config {
struct adreno_rev rev;
uint32_t fast_rate, slow_rate, bus_freq;
+#ifdef CONFIG_MSM_BUS_SCALING
+   struct msm_bus_scale_pdata *bus_scale_table;
+#endif
 };

 #define ADRENO_IDLE_TIMEOUT (20 * 1000)
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 4583d61..71f105f 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -25,20 +25,10 @@

 #ifdef CONFIG_MSM_BUS_SCALING
 #include 
-#include 
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
+static void bs_init(struct msm_gpu *gpu)
 {
-   struct drm_device *dev = gpu->dev;
-   struct kgsl_device_platform_data *pdata;
-
-   if (!pdev) {
-   dev_err(dev->dev, "could not find dtv pdata\n");
-   return;
-   }
-
-   pdata = pdev->dev.platform_data;
-   if (pdata->bus_scale_table) {
-   gpu->bsc = 
msm_bus_scale_register_client(pdata->bus_scale_table);
+   if (gpu->bus_scale_table) {
+   gpu->bsc = msm_bus_scale_register_client(gpu->bus_scale_table);
DBG("bus scale client: %08x", gpu->bsc);
}
 }
@@ -59,7 +49,7 @@ static void bs_set(struct msm_gpu *gpu, int idx)
}
 }
 #else
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) {}
+static void bs_init(struct msm_gpu *gpu) {}
 static void bs_fini(struct msm_gpu *gpu) {}
 static void bs_set(struct msm_gpu *gpu, int idx) {}
 #endif
@@ -452,7 +442,7 @@ int msm_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
goto fail;
}

-   bs_init(gpu, pdev);
+   bs_init(gpu);

return 0;

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 8cd829e..08d0842 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -85,7 +85,11 @@ struct msm_gpu {
struct regulator *gpu_reg, *gpu_cx;
struct clk *ebi1_clk, *grp_clks[5];
uint32_t fast_rate, slow_rate, bus_freq;
+
+#ifdef CONFIG_MSM_BUS_SCALING
+   struct msm_bus_scale_pdata *bus_scale_table;
uint32_t bsc;
+#endif

/* Hang Detction: */
 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */
-- 
1.8.4.2

[PATCH 02/13] drm/msm: add missing MODULE_FIRMWARE()s

2013-12-07 Thread Rob Clark 
Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a0b9d8a..d7bc51b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -53,6 +53,11 @@ static const struct adreno_info gpulist[] = {
},
 };

+MODULE_FIRMWARE("a300_pm4.fw");
+MODULE_FIRMWARE("a300_pfp.fw");
+MODULE_FIRMWARE("a330_pm4.fw");
+MODULE_FIRMWARE("a330_pfp.fw");
+
 #define RB_SIZESZ_32K
 #define RB_BLKSIZE 16

-- 
1.8.4.2

[PATCH 05/13] drm/msm: add support for msm8060ab/bstem

2013-12-07 Thread Rob Clark 
This adds the necessary configuration for the APQ8060A SoC (dual-core
krait + a320 gpu) as found on the bstem board.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 16 +---
 drivers/gpu/drm/msm/hdmi/hdmi.c   |  4 ++--
 drivers/gpu/drm/msm/mdp4/mdp4_kms.c   |  4 
 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 16fe15d..f4aa815 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -219,7 +219,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
/* Load PM4: */
ptr = (uint32_t *)(adreno_gpu->pm4->data);
len = adreno_gpu->pm4->size / 4;
-   DBG("loading PM4 ucode version: %u", ptr[0]);
+   DBG("loading PM4 ucode version: %x", ptr[1]);

gpu_write(gpu, REG_AXXX_CP_DEBUG,
AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE |
@@ -231,7 +231,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
/* Load PFP: */
ptr = (uint32_t *)(adreno_gpu->pfp->data);
len = adreno_gpu->pfp->size / 4;
-   DBG("loading PFP ucode version: %u", ptr[0]);
+   DBG("loading PFP ucode version: %x", ptr[5]);

gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
for (i = 1; i < len; i++)
@@ -469,7 +469,7 @@ static int a3xx_probe(struct platform_device *pdev)
config.slow_rate = 2700;
config.bus_freq  = 4;
config.rev = ADRENO_REV(3, 2, 1, 0);
-   } else if (cpu_is_apq8064() || cpu_is_msm8960ab()) {
+   } else if (cpu_is_apq8064()) {
config.fast_rate = 4;
config.slow_rate = 2700;
config.bus_freq  = 4;
@@ -482,6 +482,16 @@ static int a3xx_probe(struct platform_device *pdev)
else
config.rev = ADRENO_REV(3, 2, 0, 0);

+   } else if (cpu_is_msm8960ab()) {
+   config.fast_rate = 4;
+   config.slow_rate = 32000;
+   config.bus_freq  = 4;
+
+   if (SOCINFO_VERSION_MINOR(version) == 0)
+   config.rev = ADRENO_REV(3, 2, 1, 0);
+   else
+   config.rev = ADRENO_REV(3, 2, 1, 1);
+
} else if (cpu_is_msm8930()) {
config.fast_rate = 4;
config.slow_rate = 2700;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 50d11df..32f26f8 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -122,7 +122,7 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder 
*encoder)

hdmi->mvs = devm_regulator_get(&pdev->dev, "8901_hdmi_mvs");
if (IS_ERR(hdmi->mvs))
-   hdmi->mvs = devm_regulator_get(&pdev->dev, "hdmi_mvs");
+   hdmi->mvs = devm_regulator_get(&pdev->dev, "8921_hdmi_mvs");
if (IS_ERR(hdmi->mvs)) {
ret = PTR_ERR(hdmi->mvs);
dev_err(dev->dev, "failed to get mvs regulator: %d\n", ret);
@@ -230,7 +230,7 @@ static int hdmi_dev_probe(struct platform_device *pdev)
config.ddc_data_gpio = 71;
config.hpd_gpio  = 72;
config.pmic_gpio = 13 + NR_GPIO_IRQS;
-   } else if (cpu_is_msm8960()) {
+   } else if (cpu_is_msm8960() || cpu_is_msm8960ab()) {
config.phy_init  = hdmi_phy_8960_init;
config.ddc_clk_gpio  = 100;
config.ddc_data_gpio = 101;
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c 
b/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
index bab8cbc..2e2ae16 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
@@ -32,7 +32,9 @@ static int mdp4_hw_init(struct msm_kms *kms)

pm_runtime_get_sync(dev->dev);

+   mdp4_enable(mdp4_kms);
version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
+   mdp4_disable(mdp4_kms);

major = FIELD(version, MDP4_VERSION_MAJOR);
minor = FIELD(version, MDP4_VERSION_MINOR);
@@ -328,9 +330,11 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
 * have left things on, in which case we'll start getting faults if
 * we don't disable):
 */
+   mdp4_enable(mdp4_kms);
mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
+   mdp4_disable(mdp4_kms);
mdelay(16);

if (config->iommu) {
-- 
1.8.4.2

[PATCH 04/13] drm/msm: add support for non-IOMMU systems

2013-12-07 Thread Rob Clark 
Add a VRAM carveout that is used for systems which do not have an IOMMU.

The VRAM carveout uses CMA.  The arch code must setup a CMA pool for the
device (preferrably in highmem.. a 256m-512m VRAM pool in lowmem is not
cool).  The user can configure the VRAM pool size using msm.vram module
param.

Technically, the abstraction of IOMMU behind msm_mmu is not strictly
needed, but it simplifies the GEM code a bit, and will be useful later
when I add support for a2xx devices with GPUMMU, so I decided to keep
this part.

It appears to be possible to configure the GPU to restrict access to
addresses within the VRAM pool, but this is not done yet.  So for now
the GPU will refuse to load if there is no sort of mmu.  Once address
based limits are supported and tested to confirm that we aren't giving
the GPU access to arbitrary memory, this restriction can be lifted

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile|   1 +
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |  15 ++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |  13 ++-
 drivers/gpu/drm/msm/mdp4/mdp4_kms.c |  29 +++---
 drivers/gpu/drm/msm/msm_drv.c   |  87 +---
 drivers/gpu/drm/msm/msm_drv.h   |  21 ++--
 drivers/gpu/drm/msm/msm_gem.c   | 170 +---
 drivers/gpu/drm/msm/msm_gem.h   |   5 +
 drivers/gpu/drm/msm/msm_gpu.c   |  19 ++--
 drivers/gpu/drm/msm/msm_gpu.h   |   2 +-
 drivers/gpu/drm/msm/msm_iommu.c | 148 +++
 drivers/gpu/drm/msm/msm_mmu.h   |  47 +
 12 files changed, 410 insertions(+), 147 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/msm_iommu.c
 create mode 100644 drivers/gpu/drm/msm/msm_mmu.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index e5fa12b..ca62457 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -24,6 +24,7 @@ msm-y := \
msm_gem_prime.o \
msm_gem_submit.o \
msm_gpu.o \
+   msm_iommu.o \
msm_ringbuffer.o

 msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index d9e72a6..16fe15d 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -426,7 +426,20 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
if (ret)
goto fail;

-   return &a3xx_gpu->base.base;
+   if (!gpu->mmu) {
+   /* TODO we think it is possible to configure the GPU to
+* restrict access to VRAM carveout.  But the required
+* registers are unknown.  For now just bail out and
+* limp along with just modesetting.  If it turns out
+* to not be possible to restrict access, then we must
+* implement a cmdstream validator.
+*/
+   dev_err(dev->dev, "No memory protection without IOMMU\n");
+   ret = -ENXIO;
+   goto fail;
+   }
+
+   return gpu;

 fail:
if (a3xx_gpu)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c 
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index d7bc51b..3f1c7b2 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -17,6 +17,7 @@

 #include "adreno_gpu.h"
 #include "msm_gem.h"
+#include "msm_mmu.h"

 struct adreno_info {
struct adreno_rev rev;
@@ -291,6 +292,7 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
struct adreno_rev rev)
 {
+   struct msm_mmu *mmu;
int i, ret;

/* identify gpu: */
@@ -338,10 +340,13 @@ int adreno_gpu_init(struct drm_device *drm, struct 
platform_device *pdev,
if (ret)
return ret;

-   ret = msm_iommu_attach(drm, gpu->base.iommu,
-   iommu_ports, ARRAY_SIZE(iommu_ports));
-   if (ret)
-   return ret;
+   mmu = gpu->base.mmu;
+   if (mmu) {
+   ret = mmu->funcs->attach(mmu, iommu_ports,
+   ARRAY_SIZE(iommu_ports));
+   if (ret)
+   return ret;
+   }

gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs),
MSM_BO_UNCACHED);
diff --git a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c 
b/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
index 8972ac3..bab8cbc 100644
--- a/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/mdp4/mdp4_kms.c
@@ -17,6 +17,7 @@


 #include "msm_drv.h"
+#include "msm_mmu.h"
 #include "mdp4_kms.h"

 static struct mdp4_platform_config *mdp4_get_config(struct platform_device 
*dev);
@@ -260,6 +261,7 @@ struct msm_kms *mdp4_kms_init(struct drm_device *dev)
struct mdp4_platform_config *config = mdp4_get_config(pdev);
struct mdp4_kms *mdp4_kms;
struct msm_kms *km

[PATCH 08/13] drm/msm: mdp4_format -> mdp_format

2013-12-07 Thread Rob Clark 
This can be shared between mdp4 and mdp5.  Both use the same set of
parameters to describe the format to the hw.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile   |  1 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c   |  4 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c | 72 --
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c|  2 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h| 28 +---
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c  |  4 +-
 drivers/gpu/drm/msm/mdp/mdp_format.c   | 71 +
 drivers/gpu/drm/msm/mdp/mdp_kms.h  | 42 +
 8 files changed, 129 insertions(+), 95 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp_format.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp_kms.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 6df1118..33d7fac 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -12,6 +12,7 @@ msm-y := \
hdmi/hdmi_i2c.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8x60.o \
+   mdp/mdp_format.o \
mdp/mdp4/mdp4_crtc.o \
mdp/mdp4/mdp4_dtv_encoder.o \
mdp/mdp4/mdp4_format.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index d0ff390..c11400a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -262,8 +262,8 @@ static void blend_setup(struct drm_crtc *crtc)
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
int idx = idxs[pipe_id];
if (idx > 0) {
-   const struct mdp4_format *format =
-   
to_mdp4_format(msm_framebuffer_format(plane->fb));
+   const struct mdp_format *format =
+   
to_mdp_format(msm_framebuffer_format(plane->fb));
alpha[idx-1] = format->alpha_enable;
}
mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, 
stages[idx]);
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c
deleted file mode 100644
index 17330b0..000
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (C) 2013 Red Hat
- * Author: Rob Clark 
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see .
- */
-
-
-#include "msm_drv.h"
-#include "mdp4_kms.h"
-
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt) { \
-   .base = { .pixel_format = DRM_FORMAT_ ## name }, \
-   .bpc_a = BPC ## a ## A,  \
-   .bpc_r = BPC ## r,   \
-   .bpc_g = BPC ## g,   \
-   .bpc_b = BPC ## b,   \
-   .unpack = { e0, e1, e2, e3 },\
-   .alpha_enable = alpha,   \
-   .unpack_tight = tight,   \
-   .cpp = c,\
-   .unpack_count = cnt, \
-   }
-
-#define BPC0A 0
-
-static const struct mdp4_format formats[] = {
-   /*  name  a  r  g  b   e0 e1 e2 e3  alpha   tight  cpp cnt */
-   FMT(ARGB, 8, 8, 8, 8,  1, 0, 2, 3,  true,   true,  4,  4),
-   FMT(XRGB, 8, 8, 8, 8,  1, 0, 2, 3,  false,  true,  4,  4),
-   FMT(RGB888,   0, 8, 8, 8,  1, 0, 2, 0,  false,  true,  3,  3),
-   FMT(BGR888,   0, 8, 8, 8,  2, 0, 1, 0,  false,  true,  3,  3),
-   FMT(RGB565,   0, 5, 6, 5,  1, 0, 2, 0,  false,  true,  2,  3),
-   FMT(BGR565,   0, 5, 6, 5,  2, 0, 1, 0,  false,  true,  2,  3),
-};
-
-uint32_t mdp4_get_formats(enum mdp4_pipe pipe_id, uint32_t *pixel_formats,
-   uint32_t max_formats)
-{
-   uint32_t i;
-   for (i = 0; i < ARRAY_SIZE(formats); i++) {
-   const struct mdp4_format *f = &formats[i];
-
-   if (i == max_formats)
-   break;
-
-   pixel_formats[i] = f->base.pixel_format;
-   }
-
-   return i;
-}
-
-const struct msm_format *mdp4_get_format(struct msm_kms *kms, uint32_t format)
-{
-

[PATCH 09/13] drm/msm: split out msm_kms.h

2013-12-07 Thread Rob Clark 
Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c |  1 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h   |  1 +
 drivers/gpu/drm/msm/msm_drv.c |  1 +
 drivers/gpu/drm/msm/msm_drv.h | 30 
 drivers/gpu/drm/msm/msm_fb.c  |  1 +
 drivers/gpu/drm/msm/msm_kms.h | 57 +++
 6 files changed, 61 insertions(+), 30 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/msm_kms.h

diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c 
b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
index 823eee5..197b348 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_connector.c
@@ -17,6 +17,7 @@

 #include 

+#include "msm_kms.h"
 #include "hdmi.h"

 struct hdmi_connector {
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
index ede0266..d5e6819 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
@@ -19,6 +19,7 @@
 #define __MDP4_KMS_H__

 #include "msm_drv.h"
+#include "msm_kms.h"
 #include "mdp/mdp_kms.h"
 #include "mdp4.xml.h"

diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2e3d746..8b3097a 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -17,6 +17,7 @@

 #include "msm_drv.h"
 #include "msm_gpu.h"
+#include "msm_kms.h"

 static void msm_fb_output_poll_changed(struct drm_device *dev)
 {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 3f9ba33..13a25f9 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -136,36 +136,6 @@ void __msm_fence_worker(struct work_struct *work);
(_cb)->func = _func; \
} while (0)

-/* As there are different display controller blocks depending on the
- * snapdragon version, the kms support is split out and the appropriate
- * implementation is loaded at runtime.  The kms module is responsible
- * for constructing the appropriate planes/crtcs/encoders/connectors.
- */
-struct msm_kms_funcs {
-   /* hw initialization: */
-   int (*hw_init)(struct msm_kms *kms);
-   /* irq handling: */
-   void (*irq_preinstall)(struct msm_kms *kms);
-   int (*irq_postinstall)(struct msm_kms *kms);
-   void (*irq_uninstall)(struct msm_kms *kms);
-   irqreturn_t (*irq)(struct msm_kms *kms);
-   int (*enable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
-   void (*disable_vblank)(struct msm_kms *kms, struct drm_crtc *crtc);
-   /* misc: */
-   const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t 
format);
-   long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
-   struct drm_encoder *encoder);
-   /* cleanup: */
-   void (*preclose)(struct msm_kms *kms, struct drm_file *file);
-   void (*destroy)(struct msm_kms *kms);
-};
-
-struct msm_kms {
-   const struct msm_kms_funcs *funcs;
-};
-
-struct msm_kms *mdp4_kms_init(struct drm_device *dev);
-
 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);

 int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index 0286c0e..81bafdf 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -16,6 +16,7 @@
  */

 #include "msm_drv.h"
+#include "msm_kms.h"

 #include "drm_crtc.h"
 #include "drm_crtc_helper.h"
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
new file mode 100644
index 000..e42973c
--- /dev/null
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+
+#ifndef __MSM_KMS_H__
+#define __MSM_KMS_H__
+
+#include 
+#include 
+
+#include "msm_drv.h"
+
+/* As there are different display controller blocks depending on the
+ * snapdragon version, the kms support is split out and the appropriate
+ * implementation is loaded at runtime.  The kms module is responsible
+ * for constructing the appropriate planes/crtcs/encoders/connectors.
+ */
+struct msm_kms_funcs {
+   /* hw initialization: */
+   int (*hw_init)(struct msm_kms *kms);
+   /* irq handling: */
+   void (*irq_preinstall)(struct msm_kms *kms);
+   int (*irq_postinstall)(struct msm_kms

[PATCH 07/13] drm/msm: resync generated headers

2013-12-07 Thread Rob Clark 
resync to latest envytools db, add mdp5 registers

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a2xx.xml.h  |  125 ++-
 drivers/gpu/drm/msm/adreno/a3xx.xml.h  |  116 ++-
 drivers/gpu/drm/msm/adreno/adreno_common.xml.h |  171 ++--
 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h|   30 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h  |8 +-
 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h  |8 +-
 drivers/gpu/drm/msm/dsi/sfpb.xml.h |8 +-
 drivers/gpu/drm/msm/hdmi/hdmi.xml.h|   83 +-
 drivers/gpu/drm/msm/hdmi/qfprom.xml.h  |8 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h|   88 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c   |2 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h|7 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h| 1036 
 drivers/gpu/drm/msm/mdp/mdp_common.xml.h   |   78 ++
 14 files changed, 1525 insertions(+), 243 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp_common.xml.h

diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h 
b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 9588098..85d615e 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git

 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml  (
327 bytes, from 2013-07-05 19:21:12)
-- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2013-03-31 16:51:27)
-- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml   (  
31003 bytes, from 2013-09-19 18:50:16)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml   (   
8983 bytes, from 2013-07-24 01:38:36)
-- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml  (   
9759 bytes, from 2013-09-10 00:52:33)
-- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml   (  
51983 bytes, from 2013-09-10 00:52:32)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml   (
364 bytes, from 2013-11-30 14:47:15)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   
1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml  (  
32814 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (   
8900 bytes, from 2013-10-22 23:57:49)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml(  
10574 bytes, from 2013-11-13 05:44:45)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml  (  
53644 bytes, from 2013-11-30 15:07:33)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml  (   
8344 bytes, from 2013-11-30 14:49:47)

 Copyright (C) 2013 by the following authors:
 - Rob Clark  (robclark)
@@ -202,6 +203,12 @@ enum a2xx_rb_copy_sample_select {
SAMPLE_0123 = 6,
 };

+enum adreno_mmu_clnt_beh {
+   BEH_NEVR = 0,
+   BEH_TRAN_RNG = 1,
+   BEH_TRAN_FLT = 2,
+};
+
 enum sq_tex_clamp {
SQ_TEX_WRAP = 0,
SQ_TEX_MIRROR = 1,
@@ -238,6 +245,92 @@ enum sq_tex_filter {

 #define REG_A2XX_CP_PFP_UCODE_DATA 0x00c1

+#define REG_A2XX_MH_MMU_CONFIG 0x0040
+#define A2XX_MH_MMU_CONFIG_MMU_ENABLE  0x0001
+#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE   0x0002
+#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK0x0030
+#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT   4
+static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum 
adreno_mmu_clnt_beh val)
+{
+   return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & 
A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK0x00c0
+#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT   6
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum 
adreno_mmu_clnt_beh val)
+{
+   return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & 
A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK   0x0300
+#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT  8
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum 
adreno_mmu_clnt_beh val)
+{
+   return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & 
A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
+}
+#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK   0x0c00
+#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT  10
+static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum 
adreno_mmu_clnt_beh val)
+{
+   ret

[PATCH 11/13] drm/msm: add hdmi support for apq8x74/mdp5

2013-12-07 Thread Rob Clark 
The HDMI block is basically the same between older SoC's with mdp4
display controller, and newer ones with mdp5.

So mostly this consists of better abstracting out the different sets of
regulators, clks, etc.  In particular, for regulators and clks we can
split it up by what is needed for hot plug detect to work, and what is
needed to light up the display.

Also, 8x74 has a new phy.. a very simple one, but split out into a
different mmio space.  And with mdp5, the irq is shared with mdp, so we
don't directly register our own irq handler.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile  |   1 +
 drivers/gpu/drm/msm/hdmi/hdmi.c   | 199 ++
 drivers/gpu/drm/msm/hdmi/hdmi.h   |  38 --
 drivers/gpu/drm/msm/hdmi/hdmi_bridge.c|  71 +++
 drivers/gpu/drm/msm/hdmi/hdmi_connector.c | 138 ++---
 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c  | 157 +++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c   |  10 +-
 drivers/gpu/drm/msm/msm_drv.h |   4 +-
 8 files changed, 511 insertions(+), 107 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/hdmi/hdmi_phy_8x74.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 68221f6..2698ccd 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -12,6 +12,7 @@ msm-y := \
hdmi/hdmi_i2c.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8x60.o \
+   hdmi/hdmi_phy_8x74.o \
mdp/mdp_format.o \
mdp/mdp_kms.o \
mdp/mdp4/mdp4_crtc.o \
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index 32f26f8..6f1588a 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -41,7 +41,7 @@ void hdmi_set_mode(struct hdmi *hdmi, bool power_on)
power_on ? "Enable" : "Disable", ctrl);
 }

-static irqreturn_t hdmi_irq(int irq, void *dev_id)
+irqreturn_t hdmi_irq(int irq, void *dev_id)
 {
struct hdmi *hdmi = dev_id;

@@ -71,13 +71,13 @@ void hdmi_destroy(struct kref *kref)
 }

 /* initialize connector */
-int hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
+struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder)
 {
struct hdmi *hdmi = NULL;
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = hdmi_pdev;
struct hdmi_platform_config *config;
-   int ret;
+   int i, ret;

if (!pdev) {
dev_err(dev->dev, "no hdmi device\n");
@@ -99,6 +99,7 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder 
*encoder)

hdmi->dev = dev;
hdmi->pdev = pdev;
+   hdmi->config = config;
hdmi->encoder = encoder;

/* not sure about which phy maps to which msm.. probably I miss some */
@@ -114,44 +115,70 @@ int hdmi_init(struct drm_device *dev, struct drm_encoder 
*encoder)
goto fail;
}

-   hdmi->mmio = msm_ioremap(pdev, "hdmi_msm_hdmi_addr", "HDMI");
+   hdmi->mmio = msm_ioremap(pdev, config->mmio_name, "HDMI");
if (IS_ERR(hdmi->mmio)) {
ret = PTR_ERR(hdmi->mmio);
goto fail;
}

-   hdmi->mvs = devm_regulator_get(&pdev->dev, "8901_hdmi_mvs");
-   if (IS_ERR(hdmi->mvs))
-   hdmi->mvs = devm_regulator_get(&pdev->dev, "8921_hdmi_mvs");
-   if (IS_ERR(hdmi->mvs)) {
-   ret = PTR_ERR(hdmi->mvs);
-   dev_err(dev->dev, "failed to get mvs regulator: %d\n", ret);
-   goto fail;
+   BUG_ON(config->hpd_reg_cnt > ARRAY_SIZE(hdmi->hpd_regs));
+   for (i = 0; i < config->hpd_reg_cnt; i++) {
+   struct regulator *reg;
+
+   reg = devm_regulator_get(&pdev->dev, config->hpd_reg_names[i]);
+   if (IS_ERR(reg)) {
+   ret = PTR_ERR(reg);
+   dev_err(dev->dev, "failed to get hpd regulator: %s 
(%d)\n",
+   config->hpd_reg_names[i], ret);
+   goto fail;
+   }
+
+   hdmi->hpd_regs[i] = reg;
}

-   hdmi->mpp0 = devm_regulator_get(&pdev->dev, "8901_mpp0");
-   if (IS_ERR(hdmi->mpp0))
-   hdmi->mpp0 = NULL;
+   BUG_ON(config->pwr_reg_cnt > ARRAY_SIZE(hdmi->pwr_regs));
+   for (i = 0; i < config->pwr_reg_cnt; i++) {
+   struct regulator *reg;

-   hdmi->clk = devm_clk_get(&pdev->dev, "core_clk");
-   if (IS_ERR(hdmi->clk)) {
-   ret = PTR_ERR(hdmi->clk);
-   dev_err(dev->dev, "failed to get 'clk': %d\n", ret);
-   goto fail;
+   reg = devm_regulator_get(&pdev->dev, config->pwr_reg_names[i]);
+   if (IS_ERR(reg)) {
+   ret = PTR_ERR(reg);
+   dev_err(dev->dev, "failed to get pwr regulator: %s 
(%d)\n",
+   confi

[PATCH 12/13] drm/msm: add mdp5/apq8x74

2013-12-07 Thread Rob Clark 
Add support for the new MDP5 display controller block.  The mapping
between parts of the display controller and KMS is:

  plane   -> PIPE{RGBn,VIGn} \
  crtc-> LM (layer mixer)|-> MDP "device"
  encoder -> INTF/
  connector -> HDMI/DSI/eDP/etc  --> other device(s)

Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc.  (Ie. the
register interface is same, just different bases.)

Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.

And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile|   7 +-
 drivers/gpu/drm/msm/NOTES   |  20 +-
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 569 
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 258 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 111 ++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 350 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 213 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c   | 389 +++
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c | 173 +
 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h |  41 ++
 drivers/gpu/drm/msm/msm_drv.c   |  38 +-
 11 files changed, 2166 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 2698ccd..4f977a5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -17,10 +17,15 @@ msm-y := \
mdp/mdp_kms.o \
mdp/mdp4/mdp4_crtc.o \
mdp/mdp4/mdp4_dtv_encoder.o \
-   mdp/mdp4/mdp4_format.o \
mdp/mdp4/mdp4_irq.o \
mdp/mdp4/mdp4_kms.o \
mdp/mdp4/mdp4_plane.o \
+   mdp/mdp5/mdp5_crtc.o \
+   mdp/mdp5/mdp5_encoder.o \
+   mdp/mdp5/mdp5_irq.o \
+   mdp/mdp5/mdp5_kms.o \
+   mdp/mdp5/mdp5_plane.o \
+   mdp/mdp5/mdp5_smp.o \
msm_drv.o \
msm_fb.o \
msm_gem.o \
diff --git a/drivers/gpu/drm/msm/NOTES b/drivers/gpu/drm/msm/NOTES
index e036f6c1..9c4255b 100644
--- a/drivers/gpu/drm/msm/NOTES
+++ b/drivers/gpu/drm/msm/NOTES
@@ -4,7 +4,7 @@ In the current snapdragon SoC's, we have (at least) 3 different
 display controller blocks at play:
  + MDP3 - ?? seems to be what is on geeksphone peak device
  + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
- + MDSS - snapdragon 800
+ + MDP5 - snapdragon 800

 (I don't have a completely clear picture on which display controller
 maps to which part #)
@@ -46,6 +46,24 @@ and treat the MDP4 block's irq as "the" irq.  Even though 
the connectors
 may have their own irqs which they install themselves.  For this reason
 the display controller is the "master" device.

+For MDP5, the mapping is:
+
+  plane   -> PIPE{RGBn,VIGn} \
+  crtc-> LM (layer mixer)|-> MDP "device"
+  encoder -> INTF/
+  connector -> HDMI/DSI/eDP/etc  --> other device(s)
+
+Unlike MDP4, it appears we can get by with a single encoder, rather
+than needing a different implementation for DTV, DSI, etc.  (Ie. the
+register interface is same, just different bases.)
+
+Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI,
+etc) are routed through MDP.
+
+And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
+which blocks need to be allocated to the active pipes based on fetch
+stride.
+
 Each connector probably ends up being a separate device, just for the
 logistics of finding/mapping io region, irq, etc.  Idealy we would
 have a better way than just stashing the platform device in a global
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
new file mode 100644
index 000..71a3b23
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -0,0 +1,569 @@
+/*
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULA

[PATCH 13/13] drm/msm: add a330/apq8x74

2013-12-07 Thread Rob Clark 
Add support for adreno 330.  Not too much different, just a few
differences in initial configuration plus setting OCMEM base.
Userspace support is already in upstream mesa.

Note that the existing DT code is simply using the bindings from
downstream android kernel, to simplify porting of this driver to
existing devices.  These do not constitute any committed/stable
DT ABI.  The addition of proper DT bindings will be a subsequent
patch, at which point (as best as possible) I will try to support
either upstream bindings or what is found in downstream android
kernel, so that existing device DT files can be used.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/adreno/a3xx_gpu.c   | 148 
 drivers/gpu/drm/msm/adreno/a3xx_gpu.h   |   4 +
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |   7 +-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |   6 ++
 drivers/gpu/drm/msm/msm_iommu.c |   2 +-
 5 files changed, 144 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index f4aa815..ff7c971 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -15,6 +15,10 @@
  * this program.  If not, see .
  */

+#ifdef CONFIG_MSM_OCMEM
+#  include 
+#endif
+
 #include "a3xx_gpu.h"

 #define A3XX_INT0_MASK \
@@ -63,6 +67,7 @@ static void a3xx_me_init(struct msm_gpu *gpu)
 static int a3xx_hw_init(struct msm_gpu *gpu)
 {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+   struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(adreno_gpu);
uint32_t *ptr, len;
int i, ret;

@@ -105,6 +110,21 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x00ff);
gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x00a4);

+   } else if (adreno_is_a330v2(adreno_gpu)) {
+   /*
+* Most of the VBIF registers on 8974v2 have the correct
+* values at power on, so we won't modify those if we don't
+* need to
+*/
+   /* Enable 1k sort: */
+   gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
+   gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x00a4);
+   /* Enable WR-REQ: */
+   gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x3f);
+   gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x303);
+   /* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
+   gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
+
} else if (adreno_is_a330(adreno_gpu)) {
/* Set up 16 deep read/write request queues: */
gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
@@ -121,10 +141,10 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
/* Set up VBIF_ROUND_ROBIN_QOS_ARB: */
gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
/* Set up AOOO: */
-   gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x);
-   gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x);
+   gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x003f);
+   gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
/* Enable 1K sort: */
-   gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001);
+   gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x00a4);
/* Disable VBIF clock gating. This is to enable AXI running
 * higher frequency than GPU:
@@ -162,14 +182,23 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x0001);

/* Enable Clock gating: */
-   gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
-
-   /* Set the OCMEM base address for A330 */
-//TODO:
-// if (adreno_is_a330(adreno_gpu)) {
-// gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
-// (unsigned int)(a3xx_gpu->ocmem_base >> 14));
-// }
+   if (adreno_is_a320(adreno_gpu))
+   gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfff);
+   else if (adreno_is_a330v2(adreno_gpu))
+   gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0x);
+   else if (adreno_is_a330(adreno_gpu))
+   gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffc);
+
+   if (adreno_is_a330v2(adreno_gpu))
+   gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
+   else if (adreno_is_a330(adreno_gpu))
+   gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x);
+
+   /* Set the OCMEM base address for A330, etc */
+   if (a3xx_gpu->ocmem_hdl) {
+   gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
+   (unsigned int)(a3xx_gpu->ocmem_base >> 14));
+   }

[PATCH 10/13] drm/msm: move irq utils to mdp_kms

2013-12-07 Thread Rob Clark 
We'll want basically the same thing for mdp5, so refactor it out so it
can be shared.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile|   1 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c|  20 ++--
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c |   4 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c | 142 +++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c |  16 ++-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h |  26 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c   |   2 +-
 drivers/gpu/drm/msm/mdp/mdp_kms.c   | 144 
 drivers/gpu/drm/msm/mdp/mdp_kms.h   |  57 +-
 drivers/gpu/drm/msm/msm_kms.h   |  11 ++
 10 files changed, 254 insertions(+), 169 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp_kms.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 33d7fac..68221f6 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -13,6 +13,7 @@ msm-y := \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8x60.o \
mdp/mdp_format.o \
+   mdp/mdp_kms.o \
mdp/mdp4/mdp4_crtc.o \
mdp/mdp4/mdp4_dtv_encoder.o \
mdp/mdp4/mdp4_format.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index c11400a..1964f4f 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -66,15 +66,15 @@ struct mdp4_crtc {
/* for unref'ing cursor bo's after scanout completes: */
struct drm_flip_work unref_cursor_work;

-   struct mdp4_irq vblank;
-   struct mdp4_irq err;
+   struct mdp_irq vblank;
+   struct mdp_irq err;
 };
 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)

 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
 {
struct msm_drm_private *priv = crtc->dev->dev_private;
-   return to_mdp4_kms(priv->kms);
+   return to_mdp4_kms(to_mdp_kms(priv->kms));
 }

 static void update_fb(struct drm_crtc *crtc, bool async,
@@ -93,7 +93,7 @@ static void update_fb(struct drm_crtc *crtc, bool async,

if (!async) {
/* enable vblank to pick up the old_fb */
-   mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
+   mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
}
 }

@@ -145,7 +145,7 @@ static void request_pending(struct drm_crtc *crtc, uint32_t 
pending)
struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);

atomic_or(pending, &mdp4_crtc->pending);
-   mdp4_irq_register(get_kms(crtc), &mdp4_crtc->vblank);
+   mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 }

 static void pageflip_cb(struct msm_fence_cb *cb)
@@ -210,9 +210,9 @@ static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
if (enabled != mdp4_crtc->enabled) {
if (enabled) {
mdp4_enable(mdp4_kms);
-   mdp4_irq_register(mdp4_kms, &mdp4_crtc->err);
+   mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
} else {
-   mdp4_irq_unregister(mdp4_kms, &mdp4_crtc->err);
+   mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
mdp4_disable(mdp4_kms);
}
mdp4_crtc->enabled = enabled;
@@ -571,14 +571,14 @@ static const struct drm_crtc_helper_funcs 
mdp4_crtc_helper_funcs = {
.load_lut = mdp4_crtc_load_lut,
 };

-static void mdp4_crtc_vblank_irq(struct mdp4_irq *irq, uint32_t irqstatus)
+static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 {
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, 
vblank);
struct drm_crtc *crtc = &mdp4_crtc->base;
struct msm_drm_private *priv = crtc->dev->dev_private;
unsigned pending;

-   mdp4_irq_unregister(get_kms(crtc), &mdp4_crtc->vblank);
+   mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);

pending = atomic_xchg(&mdp4_crtc->pending, 0);

@@ -593,7 +593,7 @@ static void mdp4_crtc_vblank_irq(struct mdp4_irq *irq, 
uint32_t irqstatus)
}
 }

-static void mdp4_crtc_err_irq(struct mdp4_irq *irq, uint32_t irqstatus)
+static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 {
struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
struct drm_crtc *crtc = &mdp4_crtc->base;
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
index 3799ccc..067ed03 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
@@ -35,7 +35,7 @@ struct mdp4_dtv_encoder {
 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
 {
struct msm_drm_private *priv = encoder->dev->dev_private;
-   return to_mdp4_kms(

[PATCH 06/13] drm/msm: move mdp4 -> mdp/mdp4

2013-12-07 Thread Rob Clark 
There are some little bits and pieces that mdp4 and mdp5 can share, so
move things around so that we can have both in a common parent
directory.

Signed-off-by: Rob Clark 
---
 drivers/gpu/drm/msm/Makefile|   12 +-
 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h | 1061 +++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c|  753 
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c |  303 +++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c  |   72 ++
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c |  203 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c |  391 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h |  240 +
 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c   |  253 ++
 drivers/gpu/drm/msm/mdp4/mdp4.xml.h | 1061 ---
 drivers/gpu/drm/msm/mdp4/mdp4_crtc.c|  753 
 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c |  303 ---
 drivers/gpu/drm/msm/mdp4/mdp4_format.c  |   72 --
 drivers/gpu/drm/msm/mdp4/mdp4_irq.c |  203 -
 drivers/gpu/drm/msm/mdp4/mdp4_kms.c |  391 -
 drivers/gpu/drm/msm/mdp4/mdp4_kms.h |  240 -
 drivers/gpu/drm/msm/mdp4/mdp4_plane.c   |  253 --
 17 files changed, 3282 insertions(+), 3282 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_format.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_irq.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.c
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
 create mode 100644 drivers/gpu/drm/msm/mdp/mdp4/mdp4_plane.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4.xml.h
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_crtc.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_dtv_encoder.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_format.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_irq.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.c
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_kms.h
 delete mode 100644 drivers/gpu/drm/msm/mdp4/mdp4_plane.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index ca62457..6df1118 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -12,12 +12,12 @@ msm-y := \
hdmi/hdmi_i2c.o \
hdmi/hdmi_phy_8960.o \
hdmi/hdmi_phy_8x60.o \
-   mdp4/mdp4_crtc.o \
-   mdp4/mdp4_dtv_encoder.o \
-   mdp4/mdp4_format.o \
-   mdp4/mdp4_irq.o \
-   mdp4/mdp4_kms.o \
-   mdp4/mdp4_plane.o \
+   mdp/mdp4/mdp4_crtc.o \
+   mdp/mdp4/mdp4_dtv_encoder.o \
+   mdp/mdp4/mdp4_format.o \
+   mdp/mdp4/mdp4_irq.o \
+   mdp/mdp4/mdp4_kms.o \
+   mdp/mdp4/mdp4_plane.o \
msm_drv.o \
msm_fb.o \
msm_gem.o \
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h 
b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
new file mode 100644
index 000..9908ffe
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -0,0 +1,1061 @@
+#ifndef MDP4_XML
+#define MDP4_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git 
repository:
+http://github.com/freedreno/envytools/
+git clone https://github.com/freedreno/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/msm.xml (
595 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   
1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml   (  
19332 bytes, from 2013-10-07 16:36:48)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (  
11712 bytes, from 2013-08-17 17:13:43)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml(
344 bytes, from 2013-08-11 19:26:32)
+- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml (   
1544 bytes, from 2013-08-16 19:17:05)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml (
600 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml   (  
19288 bytes, from 2013-08-11 18:14:15)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark  (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following con