Re: [PATCH] drm/gem: add mutex lock when using drm_gem_mmap_obj
Op 26-06-13 04:14, Seung-Woo Kim schreef:
> From: YoungJun Cho
>
> The drm_gem_mmap_obj() has to be protected with dev->struct_mutex,
> but some caller functions do not. So it adds mutex lock to missing
> callers and adds WARN_ON assertion whether drm_gem_mmap_obj() is
> called with mutex lock or not.
>
> Signed-off-by: YoungJun Cho
> Signed-off-by: Seung-Woo Kim
> Signed-off-by: Kyungmin Park
> CC: Laurent Pinchart
> CC: Rob Clark
> ---
> This patch is based on drm-next branch.
>
> drivers/gpu/drm/drm_gem.c |4
> drivers/gpu/drm/drm_gem_cma_helper.c |3 +++
> drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c |3 +++
> 3 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> index 4321713..b19bba0 100644
> --- a/drivers/gpu/drm/drm_gem.c
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -661,6 +661,8 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> * the GEM object is not looked up based on its fake offset. To implement the
> * DRM mmap operation, drivers should use the drm_gem_mmap() function.
> *
> + * NOTE: This function has to be protected with dev->struct_mutex
> + *
> * Return 0 or success or -EINVAL if the object size is smaller than the VMA
> * size, or if no gem_vm_ops are provided.
> */
> @@ -669,6 +671,8 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned
> long obj_size,
> {
> struct drm_device *dev = obj->dev;
>
> + WARN_ON(!mutex_is_locked(&dev->struct_mutex));
>
Please don't use mutex_is_locked, use lockdep_assert_held, so the cost only
exists when PROVE_LOCKING is used..
I know some current code does it wrong, but that is the correct function to use.
~Maarten
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Re: [PATCH] drm/gem: add mutex lock when using drm_gem_mmap_obj
On Jun 26, 2013 4:13 PM, "Maarten Lankhorst" <
maarten.lankho...@canonical.com> wrote:
>
> Op 26-06-13 04:14, Seung-Woo Kim schreef:
> > From: YoungJun Cho
> >
> > The drm_gem_mmap_obj() has to be protected with dev->struct_mutex,
> > but some caller functions do not. So it adds mutex lock to missing
> > callers and adds WARN_ON assertion whether drm_gem_mmap_obj() is
> > called with mutex lock or not.
> >
> > Signed-off-by: YoungJun Cho
> > Signed-off-by: Seung-Woo Kim
> > Signed-off-by: Kyungmin Park
> > CC: Laurent Pinchart
> > CC: Rob Clark
> > ---
> > This patch is based on drm-next branch.
> >
> > drivers/gpu/drm/drm_gem.c |4
> > drivers/gpu/drm/drm_gem_cma_helper.c |3 +++
> > drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c |3 +++
> > 3 files changed, 10 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> > index 4321713..b19bba0 100644
> > --- a/drivers/gpu/drm/drm_gem.c
> > +++ b/drivers/gpu/drm/drm_gem.c
> > @@ -661,6 +661,8 @@ EXPORT_SYMBOL(drm_gem_vm_close);
> > * the GEM object is not looked up based on its fake offset. To
implement the
> > * DRM mmap operation, drivers should use the drm_gem_mmap() function.
> > *
> > + * NOTE: This function has to be protected with dev->struct_mutex
> > + *
> > * Return 0 or success or -EINVAL if the object size is smaller than
the VMA
> > * size, or if no gem_vm_ops are provided.
> > */
> > @@ -669,6 +671,8 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj,
unsigned long obj_size,
> > {
> > struct drm_device *dev = obj->dev;
> >
> > + WARN_ON(!mutex_is_locked(&dev->struct_mutex));
> >
> Please don't use mutex_is_locked, use lockdep_assert_held, so the cost
only exists when PROVE_LOCKING is used..
>
> I know some current code does it wrong, but that is the correct function
to use.
>
> ~Maarten
>
Thank you for nice comments!
I will update it again.
Best regards YJ
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Re: [PATCH] drm/gem: fix not to assign error value to gem name
On Wed, Jun 26, 2013 at 10:42:39AM +0900, Seung-Woo Kim wrote: > From: YoungJun Cho > > If idr_alloc() is failed, obj->name can be error value. Also > it cleans up duplicated flink processing code. You should mention that it is a regression from commit 2e928815c (drm: convert to idr_alloc()) > Signed-off-by: YoungJun Cho > Signed-off-by: Seung-Woo Kim > Signed-off-by: Kyungmin Park Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/gem: fix not to assign error value to gem name
On Jun 26, 2013 5:56 PM, "Chris Wilson" wrote: > > On Wed, Jun 26, 2013 at 10:42:39AM +0900, Seung-Woo Kim wrote: > > From: YoungJun Cho > > > > If idr_alloc() is failed, obj->name can be error value. Also > > it cleans up duplicated flink processing code. > > You should mention that it is a regression from > commit 2e928815c (drm: convert to idr_alloc()) > > > Signed-off-by: YoungJun Cho > > Signed-off-by: Seung-Woo Kim > > Signed-off-by: Kyungmin Park > > Reviewed-by: Chris Wilson > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre > Thank you for comments! I'll update commit msg. Best regards YJ ___ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 000/165] radeon drm-next patches
From: Alex Deucher These are the radeon patches for 3.11. Some of these patches are huge so, it might be easier to review things here: http://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-3.11-wip I'll send a formal pull in request in the next day or two. Highlights of this series: - DPM support (Dynamic Power Management) for r6xx-SI - Support for CIK (Sea Islands): modesetting, 3D, compute, UVD - ASPM support for R6xx-SI Since this is the initial public DPM code, it's still disabled by default until we get more community testing. Pass dpm=1 to the radeon module to enable it. Alex Deucher (164): drm/radeon: fix AVI infoframe generation drm/radeon: add backlight quirk for hybrid mac drm/radeon: add a reset work handler drm/radeon: add CIK chip families drm/radeon: add DCE8 macro for CIK drm/radeon: adapt to PCI BAR changes on CIK drm/radeon: add gpu init support for CIK (v9) drm/radeon: Add support for CIK GPU reset (v2) drm/radeon: add support for MC/VM setup on CIK (v6) drm/radeon/cik: stop page faults from hanging the system (v2) drm/radeon: add initial ucode loading for CIK (v5) drm/radeon: add support mc ucode loading on CIK (v2) drm/radeon: Add CP init for CIK (v7) drm/radeon: add IB and fence dispatch functions for CIK gfx (v7) drm/radeon: add ring and IB tests for CIK (v3) drm/radeon: implement async vm_flush for the CP (v7) drm/radeon: Add support for RLC init on CIK (v4) drm/radeon: add support for interrupts on CIK (v5) drm/radeon/cik: log and handle VM page fault interrupts drm/radeon/cik: add support for sDMA dma engines (v8) drm/radeon: implement async vm_flush for the sDMA (v6) drm/radeon/cik: add support for doing async VM pt updates (v5) drm/radeon/cik: fill in startup/shutdown callbacks (v4) drm/radeon: upstream ObjectID.h updates (v2) drm/radeon: upstream atombios.h updates (v2) drm/radeon: atombios power table updates (v2) drm/radeon: handle the integrated thermal controller on CI drm/radeon: update power state parsing for CI drm/radeon/dce8: add support for display watermark setup drm/radeon/cik: add hw cursor support (v2) drm/radeon/dce8: properly handle interlaced timing drm/radeon/dce8: crtc_set_base updates drm/radeon/atom: add DCE8 encoder support drm/radeon/atom: add support for new DVO tables drm/radeon: update DISPCLK programming for DCE8 drm/radeon: add support pll selection for DCE8 (v4) drm/radeon: Handle PPLL0 powerdown on DCE8 drm/radeon: use frac fb div on DCE8 drm/radeon: add SS override support for KB/KV drm/radeon: Update radeon_info_ioctl for CIK (v2) drm/radeon: add get_gpu_clock_counter() callback for cik drm/radeon: update CIK soft reset drm/radeon: add indirect register accessors for SMC registers drm/radeon: add get_xclk() callback for CIK drm/radeon/cik: add pcie_port indirect register accessors drm/radeon: update radeon_atom_get_clock_dividers() for SI drm/radeon: update radeon_atom_get_clock_dividers for CIK drm/radeon/cik: add srbm_select function drm/radeon: use callbacks for ring pointer handling drm/radeon: implement simple doorbell page allocator drm/radeon/cik: Add support for compute queues (v2) drm/radeon/cik: switch to type3 nop packet for compute rings drm/radeon: fix up ring functions for compute rings drm/radeon/cik: add support for compute interrupts drm/radeon/cik: add support for golden register init drm/radeon: add radeon_asic struct for CIK (v11) drm/radeon: add cik tile mode array query drm/radeon: add current Bonaire PCI ids drm/radeon: add current KB pci ids drm/radeon/kms: add accessors for RCU indirect space drm/radeon/evergreen: add indirect register accessors for CG registers drm/radeon: make get_temperature functions a callback drm/radeon: add support for thermal sensor on tn drm/radeon/kms: move ucode defines to a separate header drm/radeon: properly set up the RLC on ON/LN/TN (v3) drm/radeon/kms: add atom helper functions for dpm (v3) drm/radeon/kms: add new asic struct for rv6xx (v3) drm/radeon/kms: add common dpm infrastructure drm/radeon/kms: fix up rs780/rs880 display watermark calc for dpm drm/radeon/kms: fix up 6xx/7xx display watermark calc for dpm drm/radeon/kms: fix up dce4/5 display watermark calc for dpm drm/radeon/kms: fix up dce6 display watermark calc for dpm drm/radeon/kms: add common r600 dpm functions drm/radeon/kms: add dpm support for rs780/rs880 drm/radeon/kms: add dpm support for rv6xx drm/radeon/kms: add dpm support for rv7xx (v2) drm/radeon/kms: add dpm support for evergreen (v2) drm/radeon/kms: add dpm support for btc (v2) drm/radeon/kms: add dpm support for sumo asics drm/radeon/kms: add dpm support for trinity asics drm/radeon/dpm: let atom control display phy powergating drm/radeon: add dpm UVD handling for r7xx asics drm/radeon: add dpm UVD handling for evergreen/btc asics drm/radeon: add dpm UVD handling for sumo asics drm/
[PATCH 001/165] drm/radeon: fix AVI infoframe generation
From: Alex Deucher - remove adding 2 to checksum, this is incorrect. This was incorrectly introduced in: 92db7f6c860b8190571a9dc1fcbc16d003422fe8 http://lists.freedesktop.org/archives/dri-devel/2011-December/017717.html However, the off by 2 was due to adding the version twice. From the examples in the URL above: [Rafał Miłecki][RV620] fglrx: 0x7454: 00 A8 5E 79 R600_HDMI_VIDEOINFOFRAME_0 0x7458: 00 28 00 10 R600_HDMI_VIDEOINFOFRAME_1 0x745C: 00 48 00 28 R600_HDMI_VIDEOINFOFRAME_2 0x7460: 02 00 00 48 R600_HDMI_VIDEOINFOFRAME_3 === (0x82 + 0x2 + 0xD) + 0x1F8 = 0x289 -0x289 = 0x77 However, the payload sum is not 0x1f8, it's 0x1f6. 00 + A8 + 5E + 00 + 00 + 28 + 00 + 10 + 00 + 48 + 00 + 28 + 00 + 48 = 0x1f6 Bits 25:24 of HDMI_VIDEOINFOFRAME_3 are the packet version, not part of the payload. So the total would be: (0x82 + 0x2 + 0xD) + 0x1f6 = 0x287 -0x287 = 0x79 - properly emit the AVI infoframe version. This was not being emitted previous which is probably what caused the issue above. This should fix blank screen when HDMI audio is enabled on certain monitors. Signed-off-by: Alex Deucher Cc: sta...@vger.kernel.org Cc: Rafał Miłecki --- drivers/gpu/drm/radeon/evergreen_hdmi.c | 11 ++- drivers/gpu/drm/radeon/r600_hdmi.c | 11 ++- 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index ed7c8a7..b9c6f76 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c @@ -128,14 +128,7 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; uint32_t offset = dig->afmt->offset; uint8_t *frame = buffer + 3; - - /* Our header values (type, version, length) should be alright, Intel -* is using the same. Checksum function also seems to be OK, it works -* fine for audio infoframe. However calculated value is always lower -* by 2 in comparison to fglrx. It breaks displaying anything in case -* of TVs that strictly check the checksum. Hack it manually here to -* workaround this issue. */ - frame[0x0] += 2; + uint8_t *header = buffer; WREG32(AFMT_AVI_INFO0 + offset, frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); @@ -144,7 +137,7 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder, WREG32(AFMT_AVI_INFO2 + offset, frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); WREG32(AFMT_AVI_INFO3 + offset, - frame[0xC] | (frame[0xD] << 8)); + frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); } static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 456750a..e73b2a7 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -133,14 +133,7 @@ static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; uint32_t offset = dig->afmt->offset; uint8_t *frame = buffer + 3; - - /* Our header values (type, version, length) should be alright, Intel -* is using the same. Checksum function also seems to be OK, it works -* fine for audio infoframe. However calculated value is always lower -* by 2 in comparison to fglrx. It breaks displaying anything in case -* of TVs that strictly check the checksum. Hack it manually here to -* workaround this issue. */ - frame[0x0] += 2; + uint8_t *header = buffer; WREG32(HDMI0_AVI_INFO0 + offset, frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); @@ -149,7 +142,7 @@ static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, WREG32(HDMI0_AVI_INFO2 + offset, frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); WREG32(HDMI0_AVI_INFO3 + offset, - frame[0xC] | (frame[0xD] << 8)); + frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); } /* -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 003/165] drm/radeon: add a reset work handler
From: Alex Deucher
New asics support non-privileged IBs. This allows us
to skip IB checking in the driver since the hardware
will check the command buffers for us. When using
non-privileged IBs, if the CP encounters an illegal
register in the command stream, it will halt and generate
an interrupt. The CP needs to be reset to continue. For now
just do a full GPU reset when this happens.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_irq_kms.c | 18 ++
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 142ce6c..f5fccbb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1691,6 +1691,7 @@ struct radeon_device {
struct si_rlc rlc;
struct work_struct hotplug_work;
struct work_struct audio_work;
+ struct work_struct reset_work;
int num_crtc; /* number of crtcs */
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
bool audio_enabled;
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c
b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 5a99d43..dbffeca 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -82,6 +82,23 @@ static void radeon_hotplug_work_func(struct work_struct
*work)
}
/**
+ * radeon_irq_reset_work_func - execute gpu reset
+ *
+ * @work: work struct
+ *
+ * Execute scheduled gpu reset (cayman+).
+ * This function is called when the irq handler
+ * thinks we need a gpu reset.
+ */
+static void radeon_irq_reset_work_func(struct work_struct *work)
+{
+ struct radeon_device *rdev = container_of(work, struct radeon_device,
+ reset_work);
+
+ radeon_gpu_reset(rdev);
+}
+
+/**
* radeon_driver_irq_preinstall_kms - drm irq preinstall callback
*
* @dev: drm dev pointer
@@ -243,6 +260,7 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
INIT_WORK(&rdev->audio_work, r600_audio_update_hdmi);
+ INIT_WORK(&rdev->reset_work, radeon_irq_reset_work_func);
spin_lock_init(&rdev->irq.lock);
r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
--
1.7.7.5
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[PATCH 002/165] drm/radeon: add backlight quirk for hybrid mac
From: Alex Deucher Mac laptops with multiple GPUs apparently use the gmux driver for backlight control. Don't register a radeon backlight interface. We may need to add other pci ids for other hybrid mac laptops. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=65377 Signed-off-by: Alex Deucher Cc: sta...@vger.kernel.org --- drivers/gpu/drm/radeon/atombios_encoders.c |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 8406c82..4120d35 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -186,6 +186,13 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, u8 backlight_level; char bl_name[16]; + /* Mac laptops with multiple GPUs use the gmux driver for backlight +* so don't register a backlight device +*/ + if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && + (rdev->pdev->device == 0x6741)) + return; + if (!radeon_encoder->enc_priv) return; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 008/165] drm/radeon: Add support for CIK GPU reset (v2)
From: Alex Deucher
v2: split soft reset into compute and gfx. Still need
to make reset more fine grained, but this should be a
start.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 197 +
drivers/gpu/drm/radeon/cikd.h | 80 +
2 files changed, 277 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 28f68dc..e448ae2 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -27,9 +27,13 @@
#include
#include "drmP.h"
#include "radeon.h"
+#include "radeon_asic.h"
#include "cikd.h"
#include "atom.h"
+extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+
/*
* Core functions
*/
@@ -1190,3 +1194,196 @@ static void cik_gpu_init(struct radeon_device *rdev)
udelay(50);
}
+/**
+ * cik_gpu_is_lockup - check if the 3D engine is locked up
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon_ring structure holding ring information
+ *
+ * Check if the 3D engine is locked up (CIK).
+ * Returns true if the engine is locked, false if not.
+ */
+bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+ u32 srbm_status, srbm_status2;
+ u32 grbm_status, grbm_status2;
+ u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
+
+ srbm_status = RREG32(SRBM_STATUS);
+ srbm_status2 = RREG32(SRBM_STATUS2);
+ grbm_status = RREG32(GRBM_STATUS);
+ grbm_status2 = RREG32(GRBM_STATUS2);
+ grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
+ grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
+ grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
+ grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
+ if (!(grbm_status & GUI_ACTIVE)) {
+ radeon_ring_lockup_update(ring);
+ return false;
+ }
+ /* force CP activities */
+ radeon_ring_force_activity(rdev, ring);
+ return radeon_ring_test_lockup(rdev, ring);
+}
+
+/**
+ * cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Soft reset the GFX engine and CPG blocks (CIK).
+ * XXX: deal with reseting RLC and CPF
+ * Returns 0 for success.
+ */
+static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
+{
+ struct evergreen_mc_save save;
+ u32 grbm_reset = 0;
+
+ if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+ return 0;
+
+ dev_info(rdev->dev, "GPU GFX softreset \n");
+ dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
+ RREG32(GRBM_STATUS));
+ dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
+ RREG32(GRBM_STATUS2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
+ RREG32(GRBM_STATUS_SE0));
+ dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
+ RREG32(GRBM_STATUS_SE1));
+ dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
+ RREG32(GRBM_STATUS_SE2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
+ RREG32(GRBM_STATUS_SE3));
+ dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
+ RREG32(SRBM_STATUS));
+ dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
+ RREG32(SRBM_STATUS2));
+ evergreen_mc_stop(rdev, &save);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ /* Disable CP parsing/prefetching */
+ WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+
+ /* reset all the gfx block and all CPG blocks */
+ grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
+
+ dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
+ WREG32(GRBM_SOFT_RESET, grbm_reset);
+ (void)RREG32(GRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(GRBM_SOFT_RESET, 0);
+ (void)RREG32(GRBM_SOFT_RESET);
+ /* Wait a little for things to settle down */
+ udelay(50);
+ dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
+ RREG32(GRBM_STATUS));
+ dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
+ RREG32(GRBM_STATUS2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
+ RREG32(GRBM_STATUS_SE0));
+ dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
+ RREG32(GRBM_STATUS_SE1));
+ dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
+ RREG32(GRBM_STATUS_SE2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
+ RREG32(GRBM_STATUS_SE3));
+ dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
+ RREG32(SRBM_STATUS));
+ dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
+ RREG32(SRBM_STATUS2));
+ evergreen_mc_resume(rdev, &save);
+ return 0;
+}
+
+/**
+ * cik_compute_gpu
[PATCH 006/165] drm/radeon: adapt to PCI BAR changes on CIK
From: Alex Deucher
register BAR is now at PCI BAR 5.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_device.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index c24056b..4e97ff7 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1148,8 +1148,13 @@ int radeon_device_init(struct radeon_device *rdev,
/* Registers mapping */
/* TODO: block userspace mapping of io register */
spin_lock_init(&rdev->mmio_idx_lock);
- rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
- rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
+ if (rdev->family >= CHIP_BONAIRE) {
+ rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
+ rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
+ } else {
+ rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
+ rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
+ }
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
if (rdev->rmmio == NULL) {
return -ENOMEM;
--
1.7.7.5
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[PATCH 007/165] drm/radeon: add gpu init support for CIK (v9)
From: Alex Deucher
v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |2 +-
drivers/gpu/drm/radeon/cik.c| 1192 +++
drivers/gpu/drm/radeon/cikd.h | 253 +
drivers/gpu/drm/radeon/radeon.h | 30 +
4 files changed, 1476 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/cik.c
create mode 100644 drivers/gpu/drm/radeon/cikd.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 86c5e36..88d0601 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
- si_blit_shaders.o radeon_prime.o radeon_uvd.o
+ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
new file mode 100644
index 000..28f68dc
--- /dev/null
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -0,0 +1,1192 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#include
+#include
+#include
+#include
+#include "drmP.h"
+#include "radeon.h"
+#include "cikd.h"
+#include "atom.h"
+
+/*
+ * Core functions
+ */
+/**
+ * cik_tiling_mode_table_init - init the hw tiling table
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Starting with SI, the tiling setup is done globally in a
+ * set of 32 tiling modes. Rather than selecting each set of
+ * parameters per surface as on older asics, we just select
+ * which index in the tiling table we want to use, and the
+ * surface uses those parameters (CIK).
+ */
+static void cik_tiling_mode_table_init(struct radeon_device *rdev)
+{
+ const u32 num_tile_mode_states = 32;
+ const u32 num_secondary_tile_mode_states = 16;
+ u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
+ u32 num_pipe_configs;
+ u32 num_rbs = rdev->config.cik.max_backends_per_se *
+ rdev->config.cik.max_shader_engines;
+
+ switch (rdev->config.cik.mem_row_size_in_kb) {
+ case 1:
+ split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
+ break;
+ case 2:
+ default:
+ split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
+ break;
+ case 4:
+ split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
+ break;
+ }
+
+ num_pipe_configs = rdev->config.cik.max_tile_pipes;
+ if (num_pipe_configs > 8)
+ num_pipe_configs = 8; /* ??? */
+
+ if (num_pipe_configs == 8) {
+ for (reg_offset = 0; reg_offset < num_tile_mode_states;
reg_offset++) {
+ switch (reg_offset) {
+ case 0:
+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ break;
+ case 1:
+ gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE_NEW(
[PATCH 010/165] drm/radeon/cik: stop page faults from hanging the system (v2)
From: Alex Deucher Redirect invalid memory accesses to the default page instead of locking up the memory controller. v2: rebase on top of 2 level PTs Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 15 +-- drivers/gpu/drm/radeon/cikd.h | 11 +++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index a4e1b95..28a7531 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -1608,9 +1608,20 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev) /* enable context1-15 */ WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, (u32)(rdev->dummy_page.addr >> 12)); - WREG32(VM_CONTEXT1_CNTL2, 0); + WREG32(VM_CONTEXT1_CNTL2, 4); WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | - RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); + RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | + PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | + VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | + VALID_PROTECTION_FAULT_ENABLE_DEFAULT | + READ_PROTECTION_FAULT_ENABLE_INTERRUPT | + READ_PROTECTION_FAULT_ENABLE_DEFAULT | + WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); /* TC cache setup ??? */ WREG32(TC_CFG_L1_LOAD_POLICY0, 0); diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 071a781..0dab9c5 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -68,7 +68,18 @@ #define VM_CONTEXT0_CNTL 0x1410 #defineENABLE_CONTEXT (1 << 0) #definePAGE_TABLE_DEPTH(x) (((x) & 3) << 1) +#defineRANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) #defineRANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) +#defineDUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT(1 << 6) +#defineDUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) +#definePDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) +#definePDE0_PROTECTION_FAULT_ENABLE_DEFAULT(1 << 10) +#defineVALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) +#defineVALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) +#defineREAD_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) +#defineREAD_PROTECTION_FAULT_ENABLE_DEFAULT(1 << 16) +#defineWRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) +#defineWRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) #define VM_CONTEXT1_CNTL 0x1414 #define VM_CONTEXT0_CNTL2 0x1430 #define VM_CONTEXT1_CNTL2 0x1434 -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 011/165] drm/radeon: add initial ucode loading for CIK (v5)
From: Alex Deucher
Currently the driver required 6 sets of ucode:
1. pfp - pre-fetch parser, part of the GFX CP
2. me - micro engine, part of the GFX CP
3. ce - constant engine, part of the GFX CP
4. rlc - interrupt, etc. controller
5. mc - memory controller (discrete cards only)
6. mec - compute engines, part of Compute CP
V2: add documentation
V3: update MC ucode
V4: rebase
V5: update mc ucode
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c| 180 +++
drivers/gpu/drm/radeon/radeon.h |1 +
2 files changed, 181 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 28a7531..36e0fc9 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -31,10 +31,190 @@
#include "cikd.h"
#include "atom.h"
+/* GFX */
+#define CIK_PFP_UCODE_SIZE 2144
+#define CIK_ME_UCODE_SIZE 2144
+#define CIK_CE_UCODE_SIZE 2144
+/* compute */
+#define CIK_MEC_UCODE_SIZE 4192
+/* interrupts */
+#define BONAIRE_RLC_UCODE_SIZE 2048
+#define KB_RLC_UCODE_SIZE 2560
+#define KV_RLC_UCODE_SIZE 2560
+/* gddr controller */
+#define CIK_MC_UCODE_SIZE 7866
+
+MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
+MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
+MODULE_FIRMWARE("radeon/KAVERI_me.bin");
+MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
+MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
+MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
+MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
+MODULE_FIRMWARE("radeon/KABINI_me.bin");
+MODULE_FIRMWARE("radeon/KABINI_ce.bin");
+MODULE_FIRMWARE("radeon/KABINI_mec.bin");
+MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
+
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
+/**
+ * cik_init_microcode - load ucode images from disk
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Use the firmware interface to load the ucode images into
+ * the driver (not loaded into hw).
+ * Returns 0 on success, error on failure.
+ */
+static int cik_init_microcode(struct radeon_device *rdev)
+{
+ struct platform_device *pdev;
+ const char *chip_name;
+ size_t pfp_req_size, me_req_size, ce_req_size,
+ mec_req_size, rlc_req_size, mc_req_size;
+ char fw_name[30];
+ int err;
+
+ DRM_DEBUG("\n");
+
+ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
+
+ switch (rdev->family) {
+ case CHIP_BONAIRE:
+ chip_name = "BONAIRE";
+ pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
+ me_req_size = CIK_ME_UCODE_SIZE * 4;
+ ce_req_size = CIK_CE_UCODE_SIZE * 4;
+ mec_req_size = CIK_MEC_UCODE_SIZE * 4;
+ rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
+ mc_req_size = CIK_MC_UCODE_SIZE * 4;
+ break;
+ case CHIP_KAVERI:
+ chip_name = "KAVERI";
+ pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
+ me_req_size = CIK_ME_UCODE_SIZE * 4;
+ ce_req_size = CIK_CE_UCODE_SIZE * 4;
+ mec_req_size = CIK_MEC_UCODE_SIZE * 4;
+ rlc_req_size = KV_RLC_UCODE_SIZE * 4;
+ break;
+ case CHIP_KABINI:
+ chip_name = "KABINI";
+ pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
+ me_req_size = CIK_ME_UCODE_SIZE * 4;
+ ce_req_size = CIK_CE_UCODE_SIZE * 4;
+ mec_req_size = CIK_MEC_UCODE_SIZE * 4;
+ rlc_req_size = KB_RLC_UCODE_SIZE * 4;
+ break;
+ default: BUG();
+ }
+
+ DRM_INFO("Loading %s Microcode\n", chip_name);
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+ err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->pfp_fw->size != pfp_req_size) {
+ printk(KERN_ERR
+ "cik_cp: Bogus length %zu in firmware \"%s\"\n",
+ rdev->pfp_fw->size, fw_name);
+ err = -EINVAL;
+ goto out;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
+ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->me_fw->size != me_req_size) {
+ printk(KERN_ERR
+ "cik_cp: Bogus length %zu in firmware \"%s\"\n",
[PATCH 005/165] drm/radeon: add DCE8 macro for CIK
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index f5fccbb..b50a786 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1841,6 +1841,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); (rdev->flags & RADEON_IS_IGP)) #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) +#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) /* * BIOS helpers. -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 016/165] drm/radeon: implement async vm_flush for the CP (v7)
From: Alex Deucher
Update the page table base address and flush the
VM TLB using the CP.
v2: update for 2 level PTs
v3: use new packet for invalidate
v4: update SH_MEM* regs when flushing the VM
v5: add pfp sync, go back to old style vm TLB invalidate
v6: fix hdp flush packet count
v7: use old style HDP flush
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 79 ++
1 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0cf04f3..ba242eb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2698,3 +2698,82 @@ void cik_vm_fini(struct radeon_device *rdev)
{
}
+/**
+ * cik_vm_flush - cik vm flush using the CP
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Update the page table base and flush the VM TLB
+ * using the CP (CIK).
+ */
+void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
+{
+ struct radeon_ring *ring = &rdev->ring[ridx];
+
+ if (vm == NULL)
+ return;
+
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ if (vm->id < 8) {
+ radeon_ring_write(ring,
+ (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id
<< 2)) >> 2);
+ } else {
+ radeon_ring_write(ring,
+ (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id
- 8) << 2)) >> 2);
+ }
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+
+ /* update SH_MEM_* regs */
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, VMID(vm->id));
+
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, SH_MEM_BASES >> 2);
+ radeon_ring_write(ring, 0);
+
+ radeon_ring_write(ring, 0); /* SH_MEM_BASES */
+ radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
+ radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
+ radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
+
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, VMID(0));
+
+ /* HDP flush */
+ /* We should be using the WAIT_REG_MEM packet here like in
+* cik_fence_ring_emit(), but it causes the CP to hang in this
+* context...
+*/
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 0);
+
+ /* bits 0-15 are the VM contexts0-15 */
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 1 << vm->id);
+
+ /* sync PFP to ME, otherwise we might get invalid PFP reads */
+ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
+ radeon_ring_write(ring, 0x0);
+}
+
--
1.7.7.5
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[PATCH 004/165] drm/radeon: add CIK chip families
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_device.c |3 +++
drivers/gpu/drm/radeon/radeon_family.h |3 +++
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index b0dc0b6..c24056b 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -95,6 +95,9 @@ static const char radeon_family_name[][16] = {
"VERDE",
"OLAND",
"HAINAN",
+ "BONAIRE",
+ "KAVERI",
+ "KABINI",
"LAST",
};
diff --git a/drivers/gpu/drm/radeon/radeon_family.h
b/drivers/gpu/drm/radeon/radeon_family.h
index 36e9803..3c82890 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -93,6 +93,9 @@ enum radeon_family {
CHIP_VERDE,
CHIP_OLAND,
CHIP_HAINAN,
+ CHIP_BONAIRE,
+ CHIP_KAVERI,
+ CHIP_KABINI,
CHIP_LAST,
};
--
1.7.7.5
___
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 019/165] drm/radeon/cik: log and handle VM page fault interrupts
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 10 ++ drivers/gpu/drm/radeon/cikd.h |4 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 72c7e83..b70f017 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3676,6 +3676,16 @@ restart_ih: break; } break; + case 146: + case 147: + dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); + dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", + RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); + dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", + RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); + /* reset addr and status */ + WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); + break; case 176: /* GFX RB CP_INT */ case 177: /* GFX IB CP_INT */ radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index a282168..cc4f28e 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -95,6 +95,10 @@ #define VM_INVALIDATE_REQUEST 0x1478 #define VM_INVALIDATE_RESPONSE 0x147c +#defineVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC + +#defineVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC + #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 020/165] drm/radeon/cik: add support for sDMA dma engines (v8)
From: Alex Deucher
CIK has new asynchronous DMA engines called sDMA
(system DMA). Each engine supports 1 ring buffer
for kernel and gfx and 2 userspace queues for compute.
TODO: fill in the compute setup.
v2: update to the latest reset code
v3: remove ib_parse
v4: fix copy_dma()
v5: drop WIP compute sDMA queues
v6: rebase
v7: endian fixes for IB
v8: cleanup for release
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c| 745 ++-
drivers/gpu/drm/radeon/cikd.h | 130 +++
drivers/gpu/drm/radeon/radeon.h |1 +
3 files changed, 870 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b70f017..931169e 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -44,6 +44,9 @@
#define KV_RLC_UCODE_SIZE 2560
/* gddr controller */
#define CIK_MC_UCODE_SIZE 7866
+/* sdma */
+#define CIK_SDMA_UCODE_SIZE 1050
+#define CIK_SDMA_UCODE_VERSION 64
MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
@@ -51,16 +54,19 @@ MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
+MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
MODULE_FIRMWARE("radeon/KAVERI_me.bin");
MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
+MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
MODULE_FIRMWARE("radeon/KABINI_me.bin");
MODULE_FIRMWARE("radeon/KABINI_ce.bin");
MODULE_FIRMWARE("radeon/KABINI_mec.bin");
MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
+MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
extern int r600_ih_ring_alloc(struct radeon_device *rdev);
extern void r600_ih_ring_fini(struct radeon_device *rdev);
@@ -198,7 +204,8 @@ static int cik_init_microcode(struct radeon_device *rdev)
struct platform_device *pdev;
const char *chip_name;
size_t pfp_req_size, me_req_size, ce_req_size,
- mec_req_size, rlc_req_size, mc_req_size;
+ mec_req_size, rlc_req_size, mc_req_size,
+ sdma_req_size;
char fw_name[30];
int err;
@@ -220,6 +227,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
mec_req_size = CIK_MEC_UCODE_SIZE * 4;
rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
mc_req_size = CIK_MC_UCODE_SIZE * 4;
+ sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
break;
case CHIP_KAVERI:
chip_name = "KAVERI";
@@ -228,6 +236,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
ce_req_size = CIK_CE_UCODE_SIZE * 4;
mec_req_size = CIK_MEC_UCODE_SIZE * 4;
rlc_req_size = KV_RLC_UCODE_SIZE * 4;
+ sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
break;
case CHIP_KABINI:
chip_name = "KABINI";
@@ -236,6 +245,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
ce_req_size = CIK_CE_UCODE_SIZE * 4;
mec_req_size = CIK_MEC_UCODE_SIZE * 4;
rlc_req_size = KB_RLC_UCODE_SIZE * 4;
+ sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
break;
default: BUG();
}
@@ -298,6 +308,17 @@ static int cik_init_microcode(struct radeon_device *rdev)
err = -EINVAL;
}
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
+ err = request_firmware(&rdev->sdma_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->sdma_fw->size != sdma_req_size) {
+ printk(KERN_ERR
+ "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
+ rdev->sdma_fw->size, fw_name);
+ err = -EINVAL;
+ }
+
/* No MC ucode on APUs */
if (!(rdev->flags & RADEON_IS_IGP)) {
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin",
chip_name);
@@ -1425,6 +1446,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CALC, gb_addr_config);
+ WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config &
0x70);
+ WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config &
0x70);
cik_tiling_mode_table_init(rdev);
@@ -2136,6 +2159,578 @@ static int cik_cp_resume(struct radeon_device *rdev)
return 0;
}
+/*
+ * sDMA - System DMA
+ * Starting with CIK, the GPU has new asynchronous
+ * DMA engines. These engines are used for compute
+ * and gfx. There are two DMA engines (SDMA0, SDMA1)
+ * and each one supports 1 ring buffer used for gfx
+ * and 2 queues us
[PATCH 009/165] drm/radeon: add support for MC/VM setup on CIK (v6)
From: Alex Deucher
The vm callbacks are the same as the SI ones right now
(same regs and bits). We could share the SI variants, and
I may yet do that, but I figured I would add CIK specific
ones for now in case we need to change anything.
V2: add documentation, minor fixes.
V3: integrate vram offset fixes for APUs
V4: enable 2 level VM PTs
V5: index SH_MEM_* regs properly
V6: add ib_parse()
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 361 +
drivers/gpu/drm/radeon/cikd.h | 125 ++
drivers/gpu/drm/radeon/si.c |4 +-
3 files changed, 488 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e448ae2..a4e1b95 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -33,6 +33,7 @@
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
/*
* Core functions
@@ -1387,3 +1388,363 @@ int cik_asic_reset(struct radeon_device *rdev)
return cik_gfx_gpu_soft_reset(rdev);
}
+
+/* MC */
+/**
+ * cik_mc_program - program the GPU memory controller
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Set the location of vram, gart, and AGP in the GPU's
+ * physical address space (CIK).
+ */
+static void cik_mc_program(struct radeon_device *rdev)
+{
+ struct evergreen_mc_save save;
+ u32 tmp;
+ int i, j;
+
+ /* Initialize HDP */
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+ WREG32((0x2c14 + j), 0x);
+ WREG32((0x2c18 + j), 0x);
+ WREG32((0x2c1c + j), 0x);
+ WREG32((0x2c20 + j), 0x);
+ WREG32((0x2c24 + j), 0x);
+ }
+ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+
+ evergreen_mc_stop(rdev, &save);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ /* Lockout access through VGA aperture*/
+ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+ /* Update configuration */
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ rdev->mc.vram_start >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ rdev->mc.vram_end >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
+ rdev->vram_scratch.gpu_addr >> 12);
+ tmp = ((rdev->mc.vram_end >> 24) & 0x) << 16;
+ tmp |= ((rdev->mc.vram_start >> 24) & 0x);
+ WREG32(MC_VM_FB_LOCATION, tmp);
+ /* XXX double check these! */
+ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
+ WREG32(HDP_NONSURFACE_SIZE, 0x3FFF);
+ WREG32(MC_VM_AGP_BASE, 0);
+ WREG32(MC_VM_AGP_TOP, 0x0FFF);
+ WREG32(MC_VM_AGP_BOT, 0x0FFF);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ evergreen_mc_resume(rdev, &save);
+ /* we need to own VRAM, so turn off the VGA renderer here
+* to stop it overwriting our objects */
+ rv515_vga_render_disable(rdev);
+}
+
+/**
+ * cik_mc_init - initialize the memory controller driver params
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Look up the amount of vram, vram width, and decide how to place
+ * vram and gart within the GPU's physical address space (CIK).
+ * Returns 0 for success.
+ */
+static int cik_mc_init(struct radeon_device *rdev)
+{
+ u32 tmp;
+ int chansize, numchan;
+
+ /* Get VRAM informations */
+ rdev->mc.vram_is_ddr = true;
+ tmp = RREG32(MC_ARB_RAMCFG);
+ if (tmp & CHANSIZE_MASK) {
+ chansize = 64;
+ } else {
+ chansize = 32;
+ }
+ tmp = RREG32(MC_SHARED_CHMAP);
+ switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+ case 0:
+ default:
+ numchan = 1;
+ break;
+ case 1:
+ numchan = 2;
+ break;
+ case 2:
+ numchan = 4;
+ break;
+ case 3:
+ numchan = 8;
+ break;
+ case 4:
+ numchan = 3;
+ break;
+ case 5:
+ numchan = 6;
+ break;
+ case 6:
+ numchan = 10;
+ break;
+ case 7:
+ numchan = 12;
+ break;
+ case 8:
+ numchan = 16;
+ break;
+ }
+ rdev->mc.vram_width = numchan * chansize;
+ /* Could aper size report 0 ? */
+ rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
+ rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
+ /* size in MB on
[PATCH 023/165] drm/radeon/cik: fill in startup/shutdown callbacks (v4)
From: Alex Deucher
v2: update to latest driver changes
v3: properly tear down vm on suspend
v4: fix up irq init ordering
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 340 ++
1 files changed, 340 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index cf1e0b1..cbc64a2 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -73,6 +73,8 @@ extern void r600_ih_ring_fini(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
+extern void si_rlc_fini(struct radeon_device *rdev);
+extern int si_rlc_init(struct radeon_device *rdev);
#define BONAIRE_IO_MC_REGS_SIZE 36
@@ -4681,3 +4683,341 @@ restart_ih:
return IRQ_HANDLED;
}
+
+/*
+ * startup/shutdown callbacks
+ */
+/**
+ * cik_startup - program the asic to a functional state
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Programs the asic to a functional state (CIK).
+ * Called by cik_init() and cik_resume().
+ * Returns 0 for success, error for failure.
+ */
+static int cik_startup(struct radeon_device *rdev)
+{
+ struct radeon_ring *ring;
+ int r;
+
+ if (rdev->flags & RADEON_IS_IGP) {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+ !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
+ r = cik_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ } else {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+ !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
+ !rdev->mc_fw) {
+ r = cik_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
+ r = ci_mc_load_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load MC firmware!\n");
+ return r;
+ }
+ }
+
+ r = r600_vram_scratch_init(rdev);
+ if (r)
+ return r;
+
+ cik_mc_program(rdev);
+ r = cik_pcie_gart_enable(rdev);
+ if (r)
+ return r;
+ cik_gpu_init(rdev);
+
+ /* allocate rlc buffers */
+ r = si_rlc_init(rdev);
+ if (r) {
+ DRM_ERROR("Failed to init rlc BOs!\n");
+ return r;
+ }
+
+ /* allocate wb buffer */
+ r = radeon_wb_init(rdev);
+ if (r)
+ return r;
+
+ r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
+ return r;
+ }
+
+ r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
+ return r;
+ }
+
+ r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
+ return r;
+ }
+
+ /* Enable IRQ */
+ if (!rdev->irq.installed) {
+ r = radeon_irq_kms_init(rdev);
+ if (r)
+ return r;
+ }
+
+ r = cik_irq_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: IH init failed (%d).\n", r);
+ radeon_irq_kms_fini(rdev);
+ return r;
+ }
+ cik_irq_set(rdev);
+
+ ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
RADEON_WB_CP_RPTR_OFFSET,
+CP_RB0_RPTR, CP_RB0_WPTR,
+0, 0xf, RADEON_CP_PACKET2);
+ if (r)
+ return r;
+
+ ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
R600_WB_DMA_RPTR_OFFSET,
+SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET,
+SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET,
+2, 0xfffc, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
+ if (r)
+ return r;
+
+ ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
CAYMAN_WB_DMA1_RPTR_OFFSET,
+SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET,
+
[PATCH 014/165] drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)
From: Alex Deucher
For gfx ring only. Compute is still todo.
v2: add documentation
v3: update to latest reset changes, integrate emit update patch.
v4: fix count on wait_reg_mem for HDP flush
v5: use old hdp flush method for fence
v6: set valid bit for IB
v7: cleanup for release
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 134 +
drivers/gpu/drm/radeon/cikd.h | 120 +++-
2 files changed, 251 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 5712526..0b9c3c9 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1493,6 +1493,140 @@ static void cik_gpu_init(struct radeon_device *rdev)
}
/*
+ * GPU scratch registers helpers function.
+ */
+/**
+ * cik_scratch_init - setup driver info for CP scratch regs
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Set up the number and offset of the CP scratch registers.
+ * NOTE: use of CP scratch registers is a legacy inferface and
+ * is not used by default on newer asics (r6xx+). On newer asics,
+ * memory buffers are used for fences rather than scratch regs.
+ */
+static void cik_scratch_init(struct radeon_device *rdev)
+{
+ int i;
+
+ rdev->scratch.num_reg = 7;
+ rdev->scratch.reg_base = SCRATCH_REG0;
+ for (i = 0; i < rdev->scratch.num_reg; i++) {
+ rdev->scratch.free[i] = true;
+ rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
+ }
+}
+
+/**
+ * cik_fence_ring_emit - emit a fence on the gfx ring
+ *
+ * @rdev: radeon_device pointer
+ * @fence: radeon fence object
+ *
+ * Emits a fence sequnce number on the gfx ring and flushes
+ * GPU caches.
+ */
+void cik_fence_ring_emit(struct radeon_device *rdev,
+struct radeon_fence *fence)
+{
+ struct radeon_ring *ring = &rdev->ring[fence->ring];
+ u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+
+ /* EVENT_WRITE_EOP - flush caches, send int */
+ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
+EOP_TC_ACTION_EN |
+EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+EVENT_INDEX(5)));
+ radeon_ring_write(ring, addr & 0xfffc);
+ radeon_ring_write(ring, (upper_32_bits(addr) & 0x) | DATA_SEL(1) |
INT_SEL(2));
+ radeon_ring_write(ring, fence->seq);
+ radeon_ring_write(ring, 0);
+ /* HDP flush */
+ /* We should be using the new WAIT_REG_MEM special op packet here
+* but it causes the CP to hang
+*/
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 0);
+}
+
+void cik_semaphore_ring_emit(struct radeon_device *rdev,
+struct radeon_ring *ring,
+struct radeon_semaphore *semaphore,
+bool emit_wait)
+{
+ uint64_t addr = semaphore->gpu_addr;
+ unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT :
PACKET3_SEM_SEL_SIGNAL;
+
+ radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
+ radeon_ring_write(ring, addr & 0x);
+ radeon_ring_write(ring, (upper_32_bits(addr) & 0x) | sel);
+}
+
+/*
+ * IB stuff
+ */
+/**
+ * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
+ *
+ * @rdev: radeon_device pointer
+ * @ib: radeon indirect buffer object
+ *
+ * Emits an DE (drawing engine) or CE (constant engine) IB
+ * on the gfx ring. IBs are usually generated by userspace
+ * acceleration drivers and submitted to the kernel for
+ * sheduling on the ring. This function schedules the IB
+ * on the gfx ring for execution by the GPU.
+ */
+void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+ struct radeon_ring *ring = &rdev->ring[ib->ring];
+ u32 header, control = INDIRECT_BUFFER_VALID;
+
+ if (ib->is_const_ib) {
+ /* set switch buffer packet before const IB */
+ radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
+ radeon_ring_write(ring, 0);
+
+ header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
+ } else {
+ u32 next_rptr;
+ if (ring->rptr_save_reg) {
+ next_rptr = ring->wptr + 3 + 4;
+ radeon_ring_write(ring,
PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ radeon_ring_write(ring, ((ring->rptr_save_reg -
+
PACKET3_SET_UCONFIG_REG_START) >> 2));
+ radeon_ring_write(ring,
[PATCH 012/165] drm/radeon: add support mc ucode loading on CIK (v2)
From: Alex Deucher
Load the GDDR5 ucode and train the links.
v2: update ucode
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 116 +
drivers/gpu/drm/radeon/cikd.h | 16 ++
2 files changed, 132 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 36e0fc9..8eec582 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -65,6 +65,122 @@ extern void evergreen_mc_stop(struct radeon_device *rdev,
struct evergreen_mc_sa
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
+#define BONAIRE_IO_MC_REGS_SIZE 36
+
+static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
+{
+ {0x0070, 0x0440},
+ {0x0071, 0x80c01803},
+ {0x0072, 0x4004},
+ {0x0073, 0x0100},
+ {0x0074, 0x00ff},
+ {0x0075, 0x3400},
+ {0x0076, 0x0814},
+ {0x0077, 0x00cc08ec},
+ {0x0078, 0x0400},
+ {0x0079, 0x},
+ {0x007a, 0x0409},
+ {0x007c, 0x},
+ {0x007e, 0x4408a8e8},
+ {0x007f, 0x0304},
+ {0x0080, 0x},
+ {0x0082, 0x0001},
+ {0x0083, 0x0002},
+ {0x0084, 0xf3e4f400},
+ {0x0085, 0x052024e3},
+ {0x0087, 0x},
+ {0x0088, 0x0100},
+ {0x008a, 0x1c0a},
+ {0x008b, 0xff01},
+ {0x008d, 0xefff},
+ {0x008e, 0xfff3efff},
+ {0x008f, 0xfff3efbf},
+ {0x0092, 0xf7ff},
+ {0x0093, 0xff7f},
+ {0x0095, 0x00101101},
+ {0x0096, 0x0fff},
+ {0x0097, 0x00116fff},
+ {0x0098, 0x6001},
+ {0x0099, 0x1001},
+ {0x009a, 0x6000},
+ {0x009b, 0x1000},
+ {0x009f, 0x00b48000}
+};
+
+/* ucode loading */
+/**
+ * ci_mc_load_microcode - load MC ucode into the hw
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Load the GDDR MC ucode into the hw (CIK).
+ * Returns 0 on success, error on failure.
+ */
+static int ci_mc_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ u32 running, blackout = 0;
+ u32 *io_mc_regs;
+ int i, ucode_size, regs_size;
+
+ if (!rdev->mc_fw)
+ return -EINVAL;
+
+ switch (rdev->family) {
+ case CHIP_BONAIRE:
+ default:
+ io_mc_regs = (u32 *)&bonaire_io_mc_regs;
+ ucode_size = CIK_MC_UCODE_SIZE;
+ regs_size = BONAIRE_IO_MC_REGS_SIZE;
+ break;
+ }
+
+ running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
+
+ if (running == 0) {
+ if (running) {
+ blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
+ WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
+ }
+
+ /* reset the engine and set to writable */
+ WREG32(MC_SEQ_SUP_CNTL, 0x0008);
+ WREG32(MC_SEQ_SUP_CNTL, 0x0010);
+
+ /* load mc io regs */
+ for (i = 0; i < regs_size; i++) {
+ WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
+ WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
+ }
+ /* load the MC ucode */
+ fw_data = (const __be32 *)rdev->mc_fw->data;
+ for (i = 0; i < ucode_size; i++)
+ WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
+
+ /* put the engine back into the active state */
+ WREG32(MC_SEQ_SUP_CNTL, 0x0008);
+ WREG32(MC_SEQ_SUP_CNTL, 0x0004);
+ WREG32(MC_SEQ_SUP_CNTL, 0x0001);
+
+ /* wait for training to complete */
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
+ break;
+ udelay(1);
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
+ break;
+ udelay(1);
+ }
+
+ if (running)
+ WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
+ }
+
+ return 0;
+}
+
/**
* cik_init_microcode - load ucode images from disk
*
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 0dab9c5..2300ae0 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -139,6 +139,8 @@
#defineENABLE_ADVANCED_DRIVER_MODEL(1 << 6)
#defineMC_VM_FB_OFFSET
[PATCH 027/165] drm/radeon: handle the integrated thermal controller on CI
From: Alex Deucher
No support for reading the temperature yet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_atombios.c |6 ++
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 919c4d8..04e8dbd 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1033,6 +1033,7 @@ enum radeon_int_thermal_type {
THERMAL_TYPE_SUMO,
THERMAL_TYPE_NI,
THERMAL_TYPE_SI,
+ THERMAL_TYPE_CI,
};
struct radeon_voltage {
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index dea6f63c..cb3273b 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1927,6 +1927,7 @@ static const char *pp_lib_thermal_controller_names[] = {
"Northern Islands",
"Southern Islands",
"lm96163",
+ "Sea Islands",
};
union power_info {
@@ -2209,6 +2210,11 @@ static void
radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
+ } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_CISLANDS) {
+ DRM_INFO("Internal thermal controller %s fan control\n",
+(controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
+ rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
} else if ((controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
(controller->ucType ==
--
1.7.7.5
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 013/165] drm/radeon: Add CP init for CIK (v7)
From: Alex Deucher
Sets up the GFX ring and loads ucode for GFX and Compute.
Todo:
- handle compute queue setup.
v2: add documentation
v3: integrate with latest reset changes
v4: additional init fixes
v5: scratch reg write back no longer supported on CIK
v6: properly set CP_RB0_BASE_HI
v7: rebase
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |2 +-
drivers/gpu/drm/radeon/cik.c | 395 +
drivers/gpu/drm/radeon/cik_blit_shaders.c | 246 ++
drivers/gpu/drm/radeon/cik_blit_shaders.h | 32 +++
drivers/gpu/drm/radeon/cikd.h | 222
drivers/gpu/drm/radeon/radeon_cs.c|4 +-
6 files changed, 899 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/cik_blit_shaders.c
create mode 100644 drivers/gpu/drm/radeon/cik_blit_shaders.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 88d0601..292fd25 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -76,7 +76,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
- si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o
+ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 8eec582..5712526 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -30,6 +30,7 @@
#include "radeon_asic.h"
#include "cikd.h"
#include "atom.h"
+#include "cik_blit_shaders.h"
/* GFX */
#define CIK_PFP_UCODE_SIZE 2144
@@ -1491,6 +1492,400 @@ static void cik_gpu_init(struct radeon_device *rdev)
udelay(50);
}
+/*
+ * CP.
+ * On CIK, gfx and compute now have independant command processors.
+ *
+ * GFX
+ * Gfx consists of a single ring and can process both gfx jobs and
+ * compute jobs. The gfx CP consists of three microengines (ME):
+ * PFP - Pre-Fetch Parser
+ * ME - Micro Engine
+ * CE - Constant Engine
+ * The PFP and ME make up what is considered the Drawing Engine (DE).
+ * The CE is an asynchronous engine used for updating buffer desciptors
+ * used by the DE so that they can be loaded into cache in parallel
+ * while the DE is processing state update packets.
+ *
+ * Compute
+ * The compute CP consists of two microengines (ME):
+ * MEC1 - Compute MicroEngine 1
+ * MEC2 - Compute MicroEngine 2
+ * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
+ * The queues are exposed to userspace and are programmed directly
+ * by the compute runtime.
+ */
+/**
+ * cik_cp_gfx_enable - enable/disable the gfx CP MEs
+ *
+ * @rdev: radeon_device pointer
+ * @enable: enable or disable the MEs
+ *
+ * Halts or unhalts the gfx MEs.
+ */
+static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
+{
+ if (enable)
+ WREG32(CP_ME_CNTL, 0);
+ else {
+ WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
+ rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
+ }
+ udelay(50);
+}
+
+/**
+ * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Loads the gfx PFP, ME, and CE ucode.
+ * Returns 0 for success, -EINVAL if the ucode is not available.
+ */
+static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ int i;
+
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
+ return -EINVAL;
+
+ cik_cp_gfx_enable(rdev, false);
+
+ /* PFP */
+ fw_data = (const __be32 *)rdev->pfp_fw->data;
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
+ WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+
+ /* CE */
+ fw_data = (const __be32 *)rdev->ce_fw->data;
+ WREG32(CP_CE_UCODE_ADDR, 0);
+ for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
+ WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_CE_UCODE_ADDR, 0);
+
+ /* ME */
+ fw_data = (const __be32 *)rdev->me_fw->data;
+ WREG32(CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
+ WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_ME_RAM_WADDR, 0);
+
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ WREG32(CP_CE_UCODE_ADDR, 0);
+ WREG32(CP_ME_RAM_WADDR, 0);
+ WREG32(CP_ME_RAM_RADDR, 0);
+ return 0;
+}
+
+/**
+ * cik_cp_gfx_start - start the gfx ring
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Enables the ring and loads the cle
[PATCH 018/165] drm/radeon: add support for interrupts on CIK (v5)
From: Alex Deucher
Todo:
- handle interrupts for compute queues
v2: add documentation
v3: update to latest reset code
v4: update to latest illegal CP handling
v5: fix missing break in interrupt handler switch statement
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c| 840 +++
drivers/gpu/drm/radeon/cikd.h | 170
drivers/gpu/drm/radeon/radeon.h | 11 +
3 files changed, 1021 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index a44ede6..72c7e83 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -62,6 +62,8 @@ MODULE_FIRMWARE("radeon/KABINI_ce.bin");
MODULE_FIRMWARE("radeon/KABINI_mec.bin");
MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
+extern int r600_ih_ring_alloc(struct radeon_device *rdev);
+extern void r600_ih_ring_fini(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
@@ -2919,3 +2921,841 @@ static int cik_rlc_resume(struct radeon_device *rdev)
return 0;
}
+
+/*
+ * Interrupts
+ * Starting with r6xx, interrupts are handled via a ring buffer.
+ * Ring buffers are areas of GPU accessible memory that the GPU
+ * writes interrupt vectors into and the host reads vectors out of.
+ * There is a rptr (read pointer) that determines where the
+ * host is currently reading, and a wptr (write pointer)
+ * which determines where the GPU has written. When the
+ * pointers are equal, the ring is idle. When the GPU
+ * writes vectors to the ring buffer, it increments the
+ * wptr. When there is an interrupt, the host then starts
+ * fetching commands and processing them until the pointers are
+ * equal again at which point it updates the rptr.
+ */
+
+/**
+ * cik_enable_interrupts - Enable the interrupt ring buffer
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Enable the interrupt ring buffer (CIK).
+ */
+static void cik_enable_interrupts(struct radeon_device *rdev)
+{
+ u32 ih_cntl = RREG32(IH_CNTL);
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+
+ ih_cntl |= ENABLE_INTR;
+ ih_rb_cntl |= IH_RB_ENABLE;
+ WREG32(IH_CNTL, ih_cntl);
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ rdev->ih.enabled = true;
+}
+
+/**
+ * cik_disable_interrupts - Disable the interrupt ring buffer
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Disable the interrupt ring buffer (CIK).
+ */
+static void cik_disable_interrupts(struct radeon_device *rdev)
+{
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+ u32 ih_cntl = RREG32(IH_CNTL);
+
+ ih_rb_cntl &= ~IH_RB_ENABLE;
+ ih_cntl &= ~ENABLE_INTR;
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ WREG32(IH_CNTL, ih_cntl);
+ /* set rptr, wptr to 0 */
+ WREG32(IH_RB_RPTR, 0);
+ WREG32(IH_RB_WPTR, 0);
+ rdev->ih.enabled = false;
+ rdev->ih.rptr = 0;
+}
+
+/**
+ * cik_disable_interrupt_state - Disable all interrupt sources
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Clear all interrupt enable bits used by the driver (CIK).
+ */
+static void cik_disable_interrupt_state(struct radeon_device *rdev)
+{
+ u32 tmp;
+
+ /* gfx ring */
+ WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+ /* compute queues */
+ WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
+ WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
+ WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
+ WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
+ WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
+ WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
+ WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
+ WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
+ /* grbm */
+ WREG32(GRBM_INT_CNTL, 0);
+ /* vline/vblank, etc. */
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+ if (rdev->num_crtc >= 4) {
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+ }
+ if (rdev->num_crtc >= 6) {
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+ WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ }
+
+ /* dac hotplug */
+ WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
+
+ /* digital hotplug */
+ tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD1_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD2_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD3_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD4_INT_C
[PATCH 015/165] drm/radeon: add ring and IB tests for CIK (v3)
From: Alex Deucher
v2: add documenation
v3: update the latest ib changes
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 114 ++
1 files changed, 114 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0b9c3c9..0cf04f3 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1518,6 +1518,57 @@ static void cik_scratch_init(struct radeon_device *rdev)
}
/**
+ * cik_ring_test - basic gfx ring test
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon_ring structure holding ring information
+ *
+ * Allocate a scratch register and write to it using the gfx ring (CIK).
+ * Provides a basic gfx ring test to verify that the ring is working.
+ * Used by cik_cp_gfx_resume();
+ * Returns 0 on success, error on failure.
+ */
+int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ring_lock(rdev, ring, 3);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",
ring->idx, r);
+ radeon_scratch_free(rdev, scratch);
+ return r;
+ }
+ radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
+ radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >>
2));
+ radeon_ring_write(ring, 0xDEADBEEF);
+ radeon_ring_unlock_commit(rdev, ring);
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx,
i);
+ } else {
+ DRM_ERROR("radeon: ring %d test failed
(scratch(0x%04X)=0x%08X)\n",
+ ring->idx, scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ return r;
+}
+
+/**
* cik_fence_ring_emit - emit a fence on the gfx ring
*
* @rdev: radeon_device pointer
@@ -1626,6 +1677,69 @@ void cik_ring_ib_execute(struct radeon_device *rdev,
struct radeon_ib *ib)
radeon_ring_write(ring, control);
}
+/**
+ * cik_ib_test - basic gfx ring IB test
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon_ring structure holding ring information
+ *
+ * Allocate an IB and execute it on the gfx ring (CIK).
+ * Provides a basic gfx ring test to verify that IBs are working.
+ * Returns 0 on success, error on failure.
+ */
+int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+ struct radeon_ib ib;
+ uint32_t scratch;
+ uint32_t tmp = 0;
+ unsigned i;
+ int r;
+
+ r = radeon_scratch_get(rdev, &scratch);
+ if (r) {
+ DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+ return r;
+ }
+ WREG32(scratch, 0xCAFEDEAD);
+ r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
+ if (r) {
+ DRM_ERROR("radeon: failed to get ib (%d).\n", r);
+ return r;
+ }
+ ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
+ ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
+ ib.ptr[2] = 0xDEADBEEF;
+ ib.length_dw = 3;
+ r = radeon_ib_schedule(rdev, &ib, NULL);
+ if (r) {
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
+ return r;
+ }
+ r = radeon_fence_wait(ib.fence, false);
+ if (r) {
+ DRM_ERROR("radeon: fence wait failed (%d).\n", r);
+ return r;
+ }
+ for (i = 0; i < rdev->usec_timeout; i++) {
+ tmp = RREG32(scratch);
+ if (tmp == 0xDEADBEEF)
+ break;
+ DRM_UDELAY(1);
+ }
+ if (i < rdev->usec_timeout) {
+ DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
ib.fence->ring, i);
+ } else {
+ DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
+ scratch, tmp);
+ r = -EINVAL;
+ }
+ radeon_scratch_free(rdev, scratch);
+ radeon_ib_free(rdev, &ib);
+ return r;
+}
+
/*
* CP.
* On CIK, gfx and compute now have independant command processors.
--
1.7.7.5
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[PATCH 031/165] drm/radeon/dce8: properly handle interlaced timing
From: Alex Deucher
The register bits changed on DCE8 compared to previous
families.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_encoders.c |8 +++-
drivers/gpu/drm/radeon/cik_reg.h |3 +++
2 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 4120d35..4439419 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1962,7 +1962,13 @@ atombios_apply_encoder_quirks(struct drm_encoder
*encoder,
/* set scaler clears this on some chips */
if (ASIC_IS_AVIVO(rdev) &&
(!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT {
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE8(rdev)) {
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ WREG32(CIK_LB_DATA_FORMAT +
radeon_crtc->crtc_offset,
+ CIK_INTERLEAVE_EN);
+ else
+ WREG32(CIK_LB_DATA_FORMAT +
radeon_crtc->crtc_offset, 0);
+ } else if (ASIC_IS_DCE4(rdev)) {
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
WREG32(EVERGREEN_DATA_FORMAT +
radeon_crtc->crtc_offset,
EVERGREEN_INTERLEAVE_EN);
diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index b96dac0..58b29b5 100644
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -62,4 +62,7 @@
#define CIK_ALPHA_CONTROL 0x6af0
# define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1)
+#define CIK_LB_DATA_FORMAT0x6b00
+# define CIK_INTERLEAVE_EN (1 << 3)
+
#endif
--
1.7.7.5
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[PATCH 021/165] drm/radeon: implement async vm_flush for the sDMA (v6)
From: Alex Deucher
Update the page table base address and flush the
VM TLB using the sDMA.
V2: update for 2 level PTs
V3: update vm flush
V4: update SH_MEM* regs
V5: switch back to old style VM TLB invalidate
V6: fix packet formatting
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 70 ++
1 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 931169e..3c18a63 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3407,6 +3407,76 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx,
struct radeon_vm *vm)
radeon_ring_write(ring, 0x0);
}
+/**
+ * cik_dma_vm_flush - cik vm flush using sDMA
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Update the page table base and flush the VM TLB
+ * using sDMA (CIK).
+ */
+void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm
*vm)
+{
+ struct radeon_ring *ring = &rdev->ring[ridx];
+ u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
+ SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
+ u32 ref_and_mask;
+
+ if (vm == NULL)
+ return;
+
+ if (ridx == R600_RING_TYPE_DMA_INDEX)
+ ref_and_mask = SDMA0;
+ else
+ ref_and_mask = SDMA1;
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ if (vm->id < 8) {
+ radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR +
(vm->id << 2)) >> 2);
+ } else {
+ radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR +
((vm->id - 8) << 2)) >> 2);
+ }
+ radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+
+ /* update SH_MEM_* regs */
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
+ radeon_ring_write(ring, VMID(vm->id));
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SH_MEM_BASES >> 2);
+ radeon_ring_write(ring, 0);
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
+ radeon_ring_write(ring, 0);
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
+ radeon_ring_write(ring, 1);
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
+ radeon_ring_write(ring, 0);
+
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
+ radeon_ring_write(ring, VMID(0));
+
+ /* flush HDP */
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
extra_bits));
+ radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
+ radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
+ radeon_ring_write(ring, ref_and_mask); /* REFERENCE */
+ radeon_ring_write(ring, ref_and_mask); /* MASK */
+ radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL
*/
+
+ /* flush TLB */
+ radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
+ radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
+ radeon_ring_write(ring, 1 << vm->id);
+}
+
/*
* RLC
* The RLC is a multi-purpose microengine that handles a
--
1.7.7.5
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[PATCH 022/165] drm/radeon/cik: add support for doing async VM pt updates (v5)
From: Alex Deucher
Async page table updates using the sDMA engine. sDMA has a
special packet for updating entries for contiguous pages
that reduces overhead.
v2: add support for and use the CP for now.
v3: update for 2 level PTs
v4: rebase, fix DMA packet
v5: switch to using an IB
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 109 ++
1 files changed, 109 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 3c18a63..cf1e0b1 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3408,6 +3408,115 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx,
struct radeon_vm *vm)
}
/**
+ * cik_vm_set_page - update the page tables using sDMA
+ *
+ * @rdev: radeon_device pointer
+ * @ib: indirect buffer to fill with commands
+ * @pe: addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: access flags
+ *
+ * Update the page tables using CP or sDMA (CIK).
+ */
+void cik_vm_set_page(struct radeon_device *rdev,
+struct radeon_ib *ib,
+uint64_t pe,
+uint64_t addr, unsigned count,
+uint32_t incr, uint32_t flags)
+{
+ uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+ uint64_t value;
+ unsigned ndw;
+
+ if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) {
+ /* CP */
+ while (count) {
+ ndw = 2 + count * 2;
+ if (ndw > 0x3FFE)
+ ndw = 0x3FFE;
+
+ ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA,
ndw);
+ ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
+ WRITE_DATA_DST_SEL(1));
+ ib->ptr[ib->length_dw++] = pe;
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+ for (; ndw > 2; ndw -= 2, --count, pe += 8) {
+ if (flags & RADEON_VM_PAGE_SYSTEM) {
+ value = radeon_vm_map_gart(rdev, addr);
+ value &= 0xF000ULL;
+ } else if (flags & RADEON_VM_PAGE_VALID) {
+ value = addr;
+ } else {
+ value = 0;
+ }
+ addr += incr;
+ value |= r600_flags;
+ ib->ptr[ib->length_dw++] = value;
+ ib->ptr[ib->length_dw++] = upper_32_bits(value);
+ }
+ }
+ } else {
+ /* DMA */
+ if (flags & RADEON_VM_PAGE_SYSTEM) {
+ while (count) {
+ ndw = count * 2;
+ if (ndw > 0xE)
+ ndw = 0xE;
+
+ /* for non-physically contiguous pages (system)
*/
+ ib->ptr[ib->length_dw++] =
SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
+ ib->ptr[ib->length_dw++] = pe;
+ ib->ptr[ib->length_dw++] = upper_32_bits(pe);
+ ib->ptr[ib->length_dw++] = ndw;
+ for (; ndw > 0; ndw -= 2, --count, pe += 8) {
+ if (flags & RADEON_VM_PAGE_SYSTEM) {
+ value =
radeon_vm_map_gart(rdev, addr);
+ value &= 0xF000ULL;
+ } else if (flags &
RADEON_VM_PAGE_VALID) {
+ value = addr;
+ } else {
+ value = 0;
+ }
+ addr += incr;
+ value |= r600_flags;
+ ib->ptr[ib->length_dw++] = value;
+ ib->ptr[ib->length_dw++] =
upper_32_bits(value);
+ }
+ }
+ } else {
+ while (count) {
+ ndw = count;
+ if (ndw > 0x7)
+ ndw = 0x7;
+
+ if (flags & RADEON_VM_PAGE_VALID)
+ value = addr;
+ else
+
[PATCH 017/165] drm/radeon: Add support for RLC init on CIK (v4)
From: Alex Deucher
RLC handles the interrupt controller and other tasks
on the GPU.
v2: add documentation
v3: update programming sequence
v4: additional setup
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 142 +
drivers/gpu/drm/radeon/cikd.h | 47 ++
2 files changed, 189 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index ba242eb..a44ede6 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2777,3 +2777,145 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx,
struct radeon_vm *vm)
radeon_ring_write(ring, 0x0);
}
+/*
+ * RLC
+ * The RLC is a multi-purpose microengine that handles a
+ * variety of functions, the most important of which is
+ * the interrupt controller.
+ */
+/**
+ * cik_rlc_stop - stop the RLC ME
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Halt the RLC ME (MicroEngine) (CIK).
+ */
+static void cik_rlc_stop(struct radeon_device *rdev)
+{
+ int i, j, k;
+ u32 mask, tmp;
+
+ tmp = RREG32(CP_INT_CNTL_RING0);
+ tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+ WREG32(CP_INT_CNTL_RING0, tmp);
+
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+ RREG32(CB_CGTT_SCLK_CTRL);
+
+ tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffc;
+ WREG32(RLC_CGCG_CGLS_CTRL, tmp);
+
+ WREG32(RLC_CNTL, 0);
+
+ for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
+ for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
+ cik_select_se_sh(rdev, i, j);
+ for (k = 0; k < rdev->usec_timeout; k++) {
+ if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
+ break;
+ udelay(1);
+ }
+ }
+ }
+ cik_select_se_sh(rdev, 0x, 0x);
+
+ mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY |
TC1_MASTER_BUSY;
+ for (k = 0; k < rdev->usec_timeout; k++) {
+ if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
+ break;
+ udelay(1);
+ }
+}
+
+/**
+ * cik_rlc_start - start the RLC ME
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Unhalt the RLC ME (MicroEngine) (CIK).
+ */
+static void cik_rlc_start(struct radeon_device *rdev)
+{
+ u32 tmp;
+
+ WREG32(RLC_CNTL, RLC_ENABLE);
+
+ tmp = RREG32(CP_INT_CNTL_RING0);
+ tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+ WREG32(CP_INT_CNTL_RING0, tmp);
+
+ udelay(50);
+}
+
+/**
+ * cik_rlc_resume - setup the RLC hw
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Initialize the RLC registers, load the ucode,
+ * and start the RLC (CIK).
+ * Returns 0 for success, -EINVAL if the ucode is not available.
+ */
+static int cik_rlc_resume(struct radeon_device *rdev)
+{
+ u32 i, size;
+ u32 clear_state_info[3];
+ const __be32 *fw_data;
+
+ if (!rdev->rlc_fw)
+ return -EINVAL;
+
+ switch (rdev->family) {
+ case CHIP_BONAIRE:
+ default:
+ size = BONAIRE_RLC_UCODE_SIZE;
+ break;
+ case CHIP_KAVERI:
+ size = KV_RLC_UCODE_SIZE;
+ break;
+ case CHIP_KABINI:
+ size = KB_RLC_UCODE_SIZE;
+ break;
+ }
+
+ cik_rlc_stop(rdev);
+
+ WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC);
+ RREG32(GRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(GRBM_SOFT_RESET, 0);
+ RREG32(GRBM_SOFT_RESET);
+ udelay(50);
+
+ WREG32(RLC_LB_CNTR_INIT, 0);
+ WREG32(RLC_LB_CNTR_MAX, 0x8000);
+
+ cik_select_se_sh(rdev, 0x, 0x);
+ WREG32(RLC_LB_INIT_CU_MASK, 0x);
+ WREG32(RLC_LB_PARAMS, 0x00600408);
+ WREG32(RLC_LB_CNTL, 0x8004);
+
+ WREG32(RLC_MC_CNTL, 0);
+ WREG32(RLC_UCODE_CNTL, 0);
+
+ fw_data = (const __be32 *)rdev->rlc_fw->data;
+ WREG32(RLC_GPM_UCODE_ADDR, 0);
+ for (i = 0; i < size; i++)
+ WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(RLC_GPM_UCODE_ADDR, 0);
+
+ /* XXX */
+ clear_state_info[0] =
0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
+ clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
+ clear_state_info[2] = 0;//cik_default_size;
+ WREG32(RLC_GPM_SCRATCH_ADDR, 0x3d);
+ for (i = 0; i < 3; i++)
+ WREG32(RLC_GPM_SCRATCH_DATA, clear_state_info[i]);
+ WREG32(RLC_DRIVER_DMA_STATUS, 0);
+
+ cik_rlc_start(rdev);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 783cf60..a116020 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -497,10 +497,
[PATCH 036/165] drm/radeon: add support pll selection for DCE8 (v4)
From: Alex Deucher
v2: make PPLL0 is available for non-DP on CI
v3: rebase changes, update documentation
v4: fix kabini
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 48 +++-
1 files changed, 47 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 586c452..590e4eb 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1621,6 +1621,12 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc
*crtc)
*
* Asic specific PLL information
*
+ * DCE 8.x
+ * KB/KV
+ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
+ * CI
+ * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and
DAC
+ *
* DCE 6.1
* - PPLL2 is only available to UNIPHYA (both DP and non-DP)
* - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
@@ -1647,7 +1653,47 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
u32 pll_in_use;
int pll;
- if (ASIC_IS_DCE61(rdev)) {
+ if (ASIC_IS_DCE8(rdev)) {
+ if
(ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+ if (rdev->clock.dp_extclk)
+ /* skip PPLL programming if using ext clock */
+ return ATOM_PPLL_INVALID;
+ else {
+ /* use the same PPLL for all DP monitors */
+ pll = radeon_get_shared_dp_ppll(crtc);
+ if (pll != ATOM_PPLL_INVALID)
+ return pll;
+ }
+ } else {
+ /* use the same PPLL for all monitors with the same
clock */
+ pll = radeon_get_shared_nondp_ppll(crtc);
+ if (pll != ATOM_PPLL_INVALID)
+ return pll;
+ }
+ /* otherwise, pick one of the plls */
+ if ((rdev->family == CHIP_KAVERI) ||
+ (rdev->family == CHIP_KABINI)) {
+ /* KB/KV has PPLL1 and PPLL2 */
+ pll_in_use = radeon_get_pll_use_mask(crtc);
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
+ if (!(pll_in_use & (1 << ATOM_PPLL1)))
+ return ATOM_PPLL1;
+ DRM_ERROR("unable to allocate a PPLL\n");
+ return ATOM_PPLL_INVALID;
+ } else {
+ /* CI has PPLL0, PPLL1, and PPLL2 */
+ pll_in_use = radeon_get_pll_use_mask(crtc);
+ if (!(pll_in_use & (1 << ATOM_PPLL2)))
+ return ATOM_PPLL2;
+ if (!(pll_in_use & (1 << ATOM_PPLL1)))
+ return ATOM_PPLL1;
+ if (!(pll_in_use & (1 << ATOM_PPLL0)))
+ return ATOM_PPLL0;
+ DRM_ERROR("unable to allocate a PPLL\n");
+ return ATOM_PPLL_INVALID;
+ }
+ } else if (ASIC_IS_DCE61(rdev)) {
struct radeon_encoder_atom_dig *dig =
radeon_encoder->enc_priv;
--
1.7.7.5
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[PATCH 026/165] drm/radeon: atombios power table updates (v2)
From: Alex Deucher
v2: further updates
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios.h | 58 ++--
1 files changed, 54 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios.h
b/drivers/gpu/drm/radeon/atombios.h
index f19d9a6..7ba9588 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -7696,6 +7696,7 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16
#define ATOM_PP_THERMALCONTROLLER_LM96163 17
+#define ATOM_PP_THERMALCONTROLLER_CISLANDS 18
// Thermal controller 'combo type' to use an external controller for Fan
control and an internal controller for thermal.
// We probably should reserve the bit 0x80 for this use.
@@ -7738,6 +7739,8 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
// Add extra system parameters here, always adjust size to include all
fields.
USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
+USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
+USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
} ATOM_PPLIB_EXTENDEDHEADER;
ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
@@ -7759,7 +7762,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does
the driver control VDDCI independently from VDDC.
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x0001 // Enable
the 'regulator hot' feature.
#define ATOM_PP_PLATFORM_CAP_BACO 0x0002 // Does
the driver supports BACO state.
-
+#define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x0004 // Does
the driver supports new CAC voltage table.
typedef struct _ATOM_PPLIB_POWERPLAYTABLE
{
@@ -7820,7 +7823,7 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset;// Points
to ATOM_PPLIB_PhaseSheddingLimits_Table
-USHORT usReserved;
+USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@@ -7985,6 +7988,17 @@ typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
} ATOM_PPLIB_SI_CLOCK_INFO;
+typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
+{
+ USHORT usEngineClockLow;
+ UCHAR ucEngineClockHigh;
+
+ USHORT usMemoryClockLow;
+ UCHAR ucMemoryClockHigh;
+
+ UCHAR ucPCIEGen;
+ USHORT usPCIELane;
+} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
@@ -8102,8 +8116,8 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
typedef struct _ATOM_PPLIB_CAC_Leakage_Record
{
-USHORT usVddc; // We use this field for the "fake" standardized VDDC for
power calculations
-ULONG ulLeakageValue;
+USHORT usVddc; // We use this field for the "fake" standardized VDDC for
power calculations; For CI and newer, we use this as the real VDDC value.
+ULONG ulLeakageValue; // For CI and newer we use this as the "fake"
standar VDDC value.
}ATOM_PPLIB_CAC_Leakage_Record;
typedef struct _ATOM_PPLIB_CAC_Leakage_Table
@@ -8218,6 +8232,42 @@ typedef struct _ATOM_PPLIB_UVD_Table
//ATOM_PPLIB_UVD_State_Table states;
}ATOM_PPLIB_UVD_Table;
+
+typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
+{
+ USHORT usVoltage;
+ USHORT usSAMClockLow;
+ UCHAR ucSAMClockHigh;
+}ATOM_PPLIB_SAMClk_Voltage_Limit_Record;
+
+typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
+UCHAR numEntries;
+ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1];
+}ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
+
+typedef struct _ATOM_PPLIB_SAMU_Table
+{
+ UCHAR revid;
+ ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits;
+}ATOM_PPLIB_SAMU_Table;
+
+#define ATOM_PPM_A_A1
+#define ATOM_PPM_A_I2
+typedef struct _ATOM_PPLIB_PPM_Table
+{
+ UCHAR ucRevId;
+ UCHAR ucPpmDesign; //A+I or A+A
+ USHORT usCpuCoreNumber;
+ ULONG ulPlatformTDP;
+ ULONG ulSmallACPlatformTDP;
+ ULONG ulPlatformTDC;
+ ULONG ulSmallACPlatformTDC;
+ ULONG ulApuTDP;
+ ULONG ulDGpuTDP;
+ ULONG ulDGpuUlvPower;
+ ULONG ulTjmax;
+} ATOM_PPLIB_PPM_Table;
+
/**/
--
1.7.7.5
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[PATCH 038/165] drm/radeon: use frac fb div on DCE8
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 24eee7c..c7ad4b9 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -555,7 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, if (rdev->family < CHIP_RV770) radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; /* use frac fb div on APUs */ - if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) + if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; /* use frac fb div on RS780/RS880 */ if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 039/165] drm/radeon: add SS override support for KB/KV
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 88a55af..3236755 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1269,6 +1269,7 @@ union igp_info {
struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
+ struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
};
bool radeon_atombios_sideport_present(struct radeon_device *rdev)
@@ -1438,6 +1439,22 @@ static void radeon_atombios_get_igp_ss_overrides(struct
radeon_device *rdev,
break;
}
break;
+ case 8:
+ switch (id) {
+ case ASIC_INTERNAL_SS_ON_TMDS:
+ percentage =
le16_to_cpu(igp_info->info_8.usDVISSPercentage);
+ rate =
le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
+ break;
+ case ASIC_INTERNAL_SS_ON_HDMI:
+ percentage =
le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
+ rate =
le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
+ break;
+ case ASIC_INTERNAL_SS_ON_LVDS:
+ percentage =
le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
+ rate =
le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
+ break;
+ }
+ break;
default:
DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
break;
--
1.7.7.5
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[PATCH 024/165] drm/radeon: upstream ObjectID.h updates (v2)
From: Alex Deucher v2: further updates Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ObjectID.h | 40 + 1 files changed, 40 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h index ca4b038..0619269 100644 --- a/drivers/gpu/drm/radeon/ObjectID.h +++ b/drivers/gpu/drm/radeon/ObjectID.h @@ -69,6 +69,8 @@ #define ENCODER_OBJECT_ID_ALMOND 0x22 #define ENCODER_OBJECT_ID_TRAVIS 0x23 #define ENCODER_OBJECT_ID_NUTMEG 0x22 +#define ENCODER_OBJECT_ID_HDMI_ANX98050x26 + /* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14 @@ -86,6 +88,8 @@ #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20 #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21 #define ENCODER_OBJECT_ID_INTERNAL_VCE0x24 +#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25 +#define ENCODER_OBJECT_ID_INTERNAL_AMCLK 0x27 #define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO0xFF @@ -364,6 +368,14 @@ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) +#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT) + +#define ENCODER_INTERNAL_UNIPHY3_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_UNIPHY3 << OBJECT_ID_SHIFT) + #define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) @@ -392,6 +404,10 @@ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT) +#define ENCODER_HDMI_ANX9805_ENUM_ID1( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_HDMI_ANX9805 << OBJECT_ID_SHIFT) + // /* Connector Object ID definition - Shared with BIOS */ // @@ -461,6 +477,14 @@ GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + +#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) + #define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) @@ -473,6 +497,10 @@ GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) +#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ + CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) + #define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) @@ -541,6 +569,18 @@
[PATCH 040/165] drm/radeon: Update radeon_info_ioctl for CIK (v2)
From: Alex Deucher
v2: rebase changes, fix a couple missed cases
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_kms.c | 33 ++---
1 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
b/drivers/gpu/drm/radeon/radeon_kms.c
index 4f2d4f4..c650228 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -229,7 +229,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
*value = rdev->accel_working;
break;
case RADEON_INFO_TILING_CONFIG:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.tile_config;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.tile_config;
else if (rdev->family >= CHIP_CAYMAN)
*value = rdev->config.cayman.tile_config;
@@ -281,7 +283,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
*value = rdev->clock.spll.reference_freq * 10;
break;
case RADEON_INFO_NUM_BACKENDS:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.max_backends_per_se *
+ rdev->config.cik.max_shader_engines;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.max_backends_per_se *
rdev->config.si.max_shader_engines;
else if (rdev->family >= CHIP_CAYMAN)
@@ -298,7 +303,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
}
break;
case RADEON_INFO_NUM_TILE_PIPES:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.max_tile_pipes;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.max_tile_pipes;
else if (rdev->family >= CHIP_CAYMAN)
*value = rdev->config.cayman.max_tile_pipes;
@@ -316,7 +323,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
*value = 1;
break;
case RADEON_INFO_BACKEND_MAP:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ return -EINVAL;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.backend_map;
else if (rdev->family >= CHIP_CAYMAN)
*value = rdev->config.cayman.backend_map;
@@ -343,7 +352,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
*value = RADEON_IB_VM_MAX_SIZE;
break;
case RADEON_INFO_MAX_PIPES:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.max_cu_per_sh;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.max_cu_per_sh;
else if (rdev->family >= CHIP_CAYMAN)
*value = rdev->config.cayman.max_pipes_per_simd;
@@ -367,7 +378,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
value64 = radeon_get_gpu_clock_counter(rdev);
break;
case RADEON_INFO_MAX_SE:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.max_shader_engines;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.max_shader_engines;
else if (rdev->family >= CHIP_CAYMAN)
*value = rdev->config.cayman.max_shader_engines;
@@ -377,7 +390,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
*value = 1;
break;
case RADEON_INFO_MAX_SH_PER_SE:
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ *value = rdev->config.cik.max_sh_per_se;
+ else if (rdev->family >= CHIP_TAHITI)
*value = rdev->config.si.max_sh_per_se;
else
return -EINVAL;
@@ -407,6 +422,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
}
break;
case RADEON_INFO_SI_TILE_MODE_ARRAY:
+ if (rdev->family >= CHIP_BONAIRE) {
+ DRM_DEBUG_K
[PATCH 029/165] drm/radeon/dce8: add support for display watermark setup
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 537 +
drivers/gpu/drm/radeon/cikd.h | 11 +
2 files changed, 548 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index cbc64a2..228d399 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5021,3 +5021,540 @@ void cik_fini(struct radeon_device *rdev)
kfree(rdev->bios);
rdev->bios = NULL;
}
+
+/* display watermark setup */
+/**
+ * dce8_line_buffer_adjust - Set up the line buffer
+ *
+ * @rdev: radeon_device pointer
+ * @radeon_crtc: the selected display controller
+ * @mode: the current display mode on the selected display
+ * controller
+ *
+ * Setup up the line buffer allocation for
+ * the selected display controller (CIK).
+ * Returns the line buffer size in pixels.
+ */
+static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
+ struct radeon_crtc *radeon_crtc,
+ struct drm_display_mode *mode)
+{
+ u32 tmp;
+
+ /*
+* Line Buffer Setup
+* There are 6 line buffers, one for each display controllers.
+* There are 3 partitions per LB. Select the number of partitions
+* to enable based on the display width. For display widths larger
+* than 4096, you need use to use 2 display controllers and combine
+* them using the stereo blender.
+*/
+ if (radeon_crtc->base.enabled && mode) {
+ if (mode->crtc_hdisplay < 1920)
+ tmp = 1;
+ else if (mode->crtc_hdisplay < 2560)
+ tmp = 2;
+ else if (mode->crtc_hdisplay < 4096)
+ tmp = 0;
+ else {
+ DRM_DEBUG_KMS("Mode too big for LB!\n");
+ tmp = 0;
+ }
+ } else
+ tmp = 1;
+
+ WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
+ LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
+
+ if (radeon_crtc->base.enabled && mode) {
+ switch (tmp) {
+ case 0:
+ default:
+ return 4096 * 2;
+ case 1:
+ return 1920 * 2;
+ case 2:
+ return 2560 * 2;
+ }
+ }
+
+ /* controller not enabled, so no lb used */
+ return 0;
+}
+
+/**
+ * cik_get_number_of_dram_channels - get the number of dram channels
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Look up the number of video ram channels (CIK).
+ * Used for display watermark bandwidth calculations
+ * Returns the number of dram channels
+ */
+static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
+{
+ u32 tmp = RREG32(MC_SHARED_CHMAP);
+
+ switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+ case 0:
+ default:
+ return 1;
+ case 1:
+ return 2;
+ case 2:
+ return 4;
+ case 3:
+ return 8;
+ case 4:
+ return 3;
+ case 5:
+ return 6;
+ case 6:
+ return 10;
+ case 7:
+ return 12;
+ case 8:
+ return 16;
+ }
+}
+
+struct dce8_wm_params {
+ u32 dram_channels; /* number of dram channels */
+ u32 yclk; /* bandwidth per dram data pin in kHz */
+ u32 sclk; /* engine clock in kHz */
+ u32 disp_clk; /* display clock in kHz */
+ u32 src_width; /* viewport width */
+ u32 active_time; /* active display time in ns */
+ u32 blank_time;/* blank time in ns */
+ bool interlaced;/* mode is interlaced */
+ fixed20_12 vsc;/* vertical scale ratio */
+ u32 num_heads; /* number of active crtcs */
+ u32 bytes_per_pixel; /* bytes per pixel display + overlay */
+ u32 lb_size; /* line buffer allocated to pipe */
+ u32 vtaps; /* vertical scaler taps */
+};
+
+/**
+ * dce8_dram_bandwidth - get the dram bandwidth
+ *
+ * @wm: watermark calculation data
+ *
+ * Calculate the raw dram bandwidth (CIK).
+ * Used for display watermark bandwidth calculations
+ * Returns the dram bandwidth in MBytes/s
+ */
+static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
+{
+ /* Calculate raw DRAM Bandwidth */
+ fixed20_12 dram_efficiency; /* 0.7 */
+ fixed20_12 yclk, dram_channels, bandwidth;
+ fixed20_12 a;
+
+ a.full = dfixed_const(1000);
+ yclk.full = dfixed_const(wm->yclk);
+ yclk.full = dfixed_div(yclk, a);
+ dram_channels.full = dfixed_const(wm->dram_channels * 4);
+ a.full = dfixed_const(10);
+ dram_efficiency.full = dfixed_const(7);
+ dram_efficiency.full = dfixed_div(dram_efficiency, a);
+ bandwidth.full = dfix
[PATCH 041/165] drm/radeon: add get_gpu_clock_counter() callback for cik
From: Alex Deucher
Used for GPU clock counter snapshots.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 21 +
drivers/gpu/drm/radeon/cikd.h|4 +++-
drivers/gpu/drm/radeon/radeon_asic.h |5 +
3 files changed, 29 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 228d399..d241cfd 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -5558,3 +5558,24 @@ void dce8_bandwidth_update(struct radeon_device *rdev)
dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i],
lb_size, num_heads);
}
}
+
+/**
+ * cik_get_gpu_clock_counter - return GPU clock counter snapshot
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Fetches a GPU clock counter snapshot (SI).
+ * Returns the 64 bit clock counter snapshot.
+ */
+uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
+{
+ uint64_t clock;
+
+ mutex_lock(&rdev->gpu_clock_mutex);
+ WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
+ clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
+ ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
+ mutex_unlock(&rdev->gpu_clock_mutex);
+ return clock;
+}
+
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 3349e37..daa51ac 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -730,7 +730,9 @@
#define RLC_GPM_UCODE_ADDR0xC388
#define RLC_GPM_UCODE_DATA0xC38C
-
+#define RLC_GPU_CLOCK_COUNT_LSB 0xC390
+#define RLC_GPU_CLOCK_COUNT_MSB 0xC394
+#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
#define RLC_UCODE_CNTL0xC39C
#define RLC_CGCG_CGLS_CTRL0xC424
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index a72759e..248da72 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -553,4 +553,9 @@ u32 si_get_xclk(struct radeon_device *rdev);
uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
+/*
+ * cik
+ */
+uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
+
#endif
--
1.7.7.5
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[PATCH 042/165] drm/radeon: update CIK soft reset
From: Alex Deucher
Update to the newer programming model.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 387 +
drivers/gpu/drm/radeon/cikd.h | 12 ++
2 files changed, 253 insertions(+), 146 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index d241cfd..aaf7bba 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -72,9 +72,11 @@ extern int r600_ih_ring_alloc(struct radeon_device *rdev);
extern void r600_ih_ring_fini(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+extern bool evergreen_is_display_hung(struct radeon_device *rdev);
extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc
*mc);
extern void si_rlc_fini(struct radeon_device *rdev);
extern int si_rlc_init(struct radeon_device *rdev);
+static void cik_rlc_stop(struct radeon_device *rdev);
#define BONAIRE_IO_MC_REGS_SIZE 36
@@ -2733,56 +2735,9 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct
radeon_ring *ring)
return r;
}
-/**
- * cik_gpu_is_lockup - check if the 3D engine is locked up
- *
- * @rdev: radeon_device pointer
- * @ring: radeon_ring structure holding ring information
- *
- * Check if the 3D engine is locked up (CIK).
- * Returns true if the engine is locked, false if not.
- */
-bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
-{
- u32 srbm_status, srbm_status2;
- u32 grbm_status, grbm_status2;
- u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
-
- srbm_status = RREG32(SRBM_STATUS);
- srbm_status2 = RREG32(SRBM_STATUS2);
- grbm_status = RREG32(GRBM_STATUS);
- grbm_status2 = RREG32(GRBM_STATUS2);
- grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
- grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
- grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
- grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
- if (!(grbm_status & GUI_ACTIVE)) {
- radeon_ring_lockup_update(ring);
- return false;
- }
- /* force CP activities */
- radeon_ring_force_activity(rdev, ring);
- return radeon_ring_test_lockup(rdev, ring);
-}
-/**
- * cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
- *
- * @rdev: radeon_device pointer
- *
- * Soft reset the GFX engine and CPG blocks (CIK).
- * XXX: deal with reseting RLC and CPF
- * Returns 0 for success.
- */
-static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
+static void cik_print_gpu_status_regs(struct radeon_device *rdev)
{
- struct evergreen_mc_save save;
- u32 grbm_reset = 0;
-
- if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
- return 0;
-
- dev_info(rdev->dev, "GPU GFX softreset \n");
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
RREG32(GRBM_STATUS));
dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
@@ -2799,132 +2754,270 @@ static int cik_gfx_gpu_soft_reset(struct
radeon_device *rdev)
RREG32(SRBM_STATUS));
dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
RREG32(SRBM_STATUS2));
- evergreen_mc_stop(rdev, &save);
- if (radeon_mc_wait_for_idle(rdev)) {
- dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
- }
- /* Disable CP parsing/prefetching */
- WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+ dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
+ RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
+ dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
+RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
+}
- /* reset all the gfx block and all CPG blocks */
- grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
+/**
+ * cik_gpu_check_soft_reset - check which blocks are busy
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Check which blocks are busy and return the relevant reset
+ * mask to be used by cik_gpu_soft_reset().
+ * Returns a mask of the blocks to be reset.
+ */
+static u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
+{
+ u32 reset_mask = 0;
+ u32 tmp;
- dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
- WREG32(GRBM_SOFT_RESET, grbm_reset);
- (void)RREG32(GRBM_SOFT_RESET);
- udelay(50);
- WREG32(GRBM_SOFT_RESET, 0);
- (void)RREG32(GRBM_SOFT_RESET);
- /* Wait a little for things to settle down */
- udelay(50);
- dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
- RREG32(GRBM_STATUS));
- dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
- RREG32(GRBM_STATUS2));
- dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
- RREG32(GRBM_STATUS_SE0));
- dev_in
[PATCH 028/165] drm/radeon: update power state parsing for CI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index cb3273b..88a55af 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1945,6 +1945,7 @@ union pplib_clock_info {
struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
struct _ATOM_PPLIB_SI_CLOCK_INFO si;
+ struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
};
union pplib_power_state {
@@ -2353,6 +2354,15 @@ static bool
radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
}
+ } else if (rdev->family >= CHIP_BONAIRE) {
+ sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
+ sclk |= clock_info->ci.ucEngineClockHigh << 16;
+ mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
+ mclk |= clock_info->ci.ucMemoryClockHigh << 16;
+ rdev->pm.power_state[state_index].clock_info[mode_index].mclk =
mclk;
+ rdev->pm.power_state[state_index].clock_info[mode_index].sclk =
sclk;
+
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
+ VOLTAGE_NONE;
} else if (rdev->family >= CHIP_TAHITI) {
sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
sclk |= clock_info->si.ucEngineClockHigh << 16;
--
1.7.7.5
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[PATCH 030/165] drm/radeon/cik: add hw cursor support (v2)
From: Alex Deucher CIK (DCE8) hw cursors are programmed the same as evergreen (DCE4) with the following caveats: - cursors are now 128x128 pixels - new alpha blend enable bit v2: rebase Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik_reg.h| 65 +++ drivers/gpu/drm/radeon/radeon.h |7 +++ drivers/gpu/drm/radeon/radeon_cursor.c | 10 ++--- drivers/gpu/drm/radeon/radeon_display.c | 16 +++- drivers/gpu/drm/radeon/radeon_mode.h|2 + drivers/gpu/drm/radeon/radeon_reg.h |1 + 6 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/radeon/cik_reg.h diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h new file mode 100644 index 000..b96dac0 --- /dev/null +++ b/drivers/gpu/drm/radeon/cik_reg.h @@ -0,0 +1,65 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef __CIK_REG_H__ +#define __CIK_REG_H__ + +#define CIK_DC_GPIO_HPD_MASK 0x65b0 +#define CIK_DC_GPIO_HPD_A 0x65b4 +#define CIK_DC_GPIO_HPD_EN0x65b8 +#define CIK_DC_GPIO_HPD_Y 0x65bc + +/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */ +#define CIK_CUR_CONTROL 0x6998 +# define CIK_CURSOR_EN (1 << 0) +# define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8) +# define CIK_CURSOR_MONO0 +# define CIK_CURSOR_24_11 +# define CIK_CURSOR_24_8_PRE_MULT 2 +# define CIK_CURSOR_24_8_UNPRE_MULT 3 +# define CIK_CURSOR_2X_MAGNIFY (1 << 16) +# define CIK_CURSOR_FORCE_MC_ON (1 << 20) +# define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24) +# define CIK_CURSOR_URGENT_ALWAYS 0 +# define CIK_CURSOR_URGENT_1_8 1 +# define CIK_CURSOR_URGENT_1_4 2 +# define CIK_CURSOR_URGENT_3_8 3 +# define CIK_CURSOR_URGENT_1_2 4 +#define CIK_CUR_SURFACE_ADDRESS 0x699c +# define CIK_CUR_SURFACE_ADDRESS_MASK 0xf000 +#define CIK_CUR_SIZE 0x69a0 +#define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4 +#define CIK_CUR_POSITION 0x69a8 +#define CIK_CUR_HOT_SPOT 0x69ac +#define CIK_CUR_COLOR10x69b0 +#define CIK_CUR_COLOR20x69b4 +#define CIK_CUR_UPDATE0x69b8 +# define CIK_CURSOR_UPDATE_PENDING (1 << 0) +# define CIK_CURSOR_UPDATE_TAKEN(1 << 1) +# define CIK_CURSOR_UPDATE_LOCK (1 << 16) +# define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24) + +#define CIK_ALPHA_CONTROL 0x6af0 +# define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1) + +#endif diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 04e8dbd..b329e99 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -150,6 +150,13 @@ extern int radeon_fastfb; #define RADEON_RESET_MC(1 << 10) #define RADEON_RESET_DISPLAY (1 << 11) +/* max cursor sizes (in pixels) */ +#define CURSOR_WIDTH 64 +#define CURSOR_HEIGHT 64 + +#define CIK_CURSOR_WIDTH 128 +#define CIK_CURSOR_HEIGHT 128 + /* * Errata workarounds. */ diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c index b097d5b..9630e8d 100644 --- a/drivers/gpu/drm/radeon/radeon_cursor.c +++ b/drivers/gpu/drm/radeon/radeon_cursor.c @@ -27,9 +27,6 @@ #include #include "radeon.h" -#define CURSOR_WIDTH 64 -#de
[PATCH 043/165] drm/radeon: add indirect register accessors for SMC registers
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen_reg.h |4
drivers/gpu/drm/radeon/radeon.h| 17 +
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h
b/drivers/gpu/drm/radeon/evergreen_reg.h
index 881aba2..50948ac 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -24,6 +24,10 @@
#ifndef __EVERGREEN_REG_H__
#define __EVERGREEN_REG_H__
+/* trinity */
+#define TN_SMC_IND_INDEX_0 0x200
+#define TN_SMC_IND_DATA_0 0x204
+
/* evergreen */
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b329e99..9af0fa6 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1806,6 +1806,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg,
u32 v);
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
+#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
+#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask) \
do {\
uint32_t tmp_ = RREG32(reg);\
@@ -1844,6 +1846,21 @@ static inline void rv370_pcie_wreg(struct radeon_device
*rdev, uint32_t reg, uin
WREG32(RADEON_PCIE_DATA, (v));
}
+static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
+{
+ u32 r;
+
+ WREG32(TN_SMC_IND_INDEX_0, (reg));
+ r = RREG32(TN_SMC_IND_DATA_0);
+ return r;
+}
+
+static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+ WREG32(TN_SMC_IND_INDEX_0, (reg));
+ WREG32(TN_SMC_IND_DATA_0, (v));
+}
+
void r100_pll_errata_after_index(struct radeon_device *rdev);
--
1.7.7.5
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[PATCH 035/165] drm/radeon: update DISPCLK programming for DCE8
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 4ba5184..586c452 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -743,7 +743,7 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, * SetPixelClock provides the dividers */ args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); - if (ASIC_IS_DCE61(rdev)) + if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) args.v6.ucPpll = ATOM_EXT_PLL1; else if (ASIC_IS_DCE6(rdev)) args.v6.ucPpll = ATOM_PPLL0; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 033/165] drm/radeon/atom: add DCE8 encoder support
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_encoders.c | 27 ---
drivers/gpu/drm/radeon/radeon_display.c|5 +++--
2 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 4439419..1bf13b3 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -303,6 +303,7 @@ static inline bool radeon_encoder_is_digital(struct
drm_encoder *encoder)
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
return true;
default:
return false;
@@ -922,10 +923,14 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder,
int action, int panel_mo
args.v4.ucLaneNum = 4;
if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
- if (dp_clock == 27)
- args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
- else if (dp_clock == 54)
+ if (dp_clock == 54)
args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
+ else if (dp_clock == 324000)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
+ else if (dp_clock == 27)
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
+ else
+ args.v1.ucConfig |=
ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
}
args.v4.acConfig.ucDigSel = dig->dig_encoder;
args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
@@ -1019,6 +1024,7 @@ atombios_dig_transmitter_setup(struct drm_encoder
*encoder, int action, uint8_t
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
index = GetIndexIntoMasterTable(COMMAND,
UNIPHYTransmitterControl);
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
@@ -1278,6 +1284,9 @@ atombios_dig_transmitter_setup(struct drm_encoder
*encoder, int action, uint8_t
else
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
+ break;
}
if (is_dp)
args.v5.ucLaneNum = dp_lane_count;
@@ -1742,6 +1751,7 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int
mode)
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
radeon_atom_encoder_dpms_dig(encoder, mode);
break;
@@ -1879,6 +1889,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder
*encoder)
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
dig = radeon_encoder->enc_priv;
switch (dig->dig_encoder) {
@@ -1900,6 +1911,9 @@ atombios_set_encoder_crtc_source(struct drm_encoder
*encoder)
case 5:
args.v2.ucEncoderID =
ASIC_INT_DIG6_ENCODER_ID;
break;
+ case 6:
+ args.v2.ucEncoderID =
ASIC_INT_DIG7_ENCODER_ID;
+ break;
}
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
@@ -2015,6 +2029,9 @@ static int radeon_atom_pick_dig_encoder(struct
drm_encoder *encoder)
else
return 4;
break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
+ return 6;
+ break;
}
[PATCH 044/165] drm/radeon: add get_xclk() callback for CIK
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 22 ++
drivers/gpu/drm/radeon/cikd.h|7 +++
drivers/gpu/drm/radeon/radeon_asic.h |1 +
3 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index aaf7bba..0db0ebc 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -78,6 +78,28 @@ extern void si_rlc_fini(struct radeon_device *rdev);
extern int si_rlc_init(struct radeon_device *rdev);
static void cik_rlc_stop(struct radeon_device *rdev);
+/**
+ * cik_get_xclk - get the xclk
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Returns the reference clock used by the gfx engine
+ * (CIK).
+ */
+u32 cik_get_xclk(struct radeon_device *rdev)
+{
+u32 reference_clock = rdev->clock.spll.reference_freq;
+
+ if (rdev->flags & RADEON_IS_IGP) {
+ if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
+ return reference_clock / 2;
+ } else {
+ if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
+ return reference_clock / 4;
+ }
+ return reference_clock;
+}
+
#define BONAIRE_IO_MC_REGS_SIZE 36
static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 8afb334..f00e273 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -28,6 +28,13 @@
#define CIK_RB_BITMAP_WIDTH_PER_SH 2
+/* SMC IND registers */
+#define GENERAL_PWRMGT0xC020
+# define GPU_COUNTER_CLK(1 << 15)
+
+#define CG_CLKPIN_CNTL0xC05001A0
+# define XTALIN_DIVIDE (1 << 1)
+
#define VGA_HDP_CONTROL0x328
#defineVGA_MEMORY_DISABLE (1 << 4)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 248da72..05f75f7 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -557,5 +557,6 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk,
u32 dclk);
* cik
*/
uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
+u32 cik_get_xclk(struct radeon_device *rdev);
#endif
--
1.7.7.5
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[PATCH 046/165] drm/radeon: update radeon_atom_get_clock_dividers() for SI
From: Alex Deucher
SI uses v5 of the command table and uses a different table
for memory PLLs.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 3236755..774e354 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2732,7 +2732,8 @@ int radeon_atom_get_clock_dividers(struct radeon_device
*rdev,
break;
case 2:
case 3:
- /* r6xx, r7xx, evergreen, ni */
+ case 5:
+ /* r6xx, r7xx, evergreen, ni, si */
if (rdev->family <= CHIP_RV770) {
args.v2.ucAction = clock_type;
args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
@@ -2765,6 +2766,9 @@ int radeon_atom_get_clock_dividers(struct radeon_device
*rdev,
dividers->vco_mode = (args.v3.ucCntlFlag &
ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
} else {
+ /* for SI we use ComputeMemoryClockParam for
memory plls */
+ if (rdev->family >= CHIP_TAHITI)
+ return -EINVAL;
args.v5.ulClockParams = cpu_to_le32((clock_type
<< 24) | clock);
if (strobe_mode)
args.v5.ucInputFlag =
ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
--
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[PATCH 034/165] drm/radeon/atom: add support for new DVO tables
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_encoders.c |9 -
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 1bf13b3..092275d 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -487,11 +487,11 @@ static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
}
}
-
union dvo_encoder_control {
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
+ DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
};
void
@@ -541,6 +541,13 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action)
args.dvo_v3.usPixelClock =
cpu_to_le16(radeon_encoder->pixel_clock / 10);
args.dvo_v3.ucDVOConfig = 0; /* XXX */
break;
+ case 4:
+ /* DCE8 */
+ args.dvo_v4.ucAction = action;
+ args.dvo_v4.usPixelClock =
cpu_to_le16(radeon_encoder->pixel_clock / 10);
+ args.dvo_v4.ucDVOConfig = 0; /* XXX */
+ args.dvo_v4.ucBitPerColor =
radeon_atom_get_bpc(encoder);
+ break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
break;
--
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[PATCH 032/165] drm/radeon/dce8: crtc_set_base updates
From: Alex Deucher
Some new fields and DESKTOP_HEIGHT register moved.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 34 --
drivers/gpu/drm/radeon/cik_reg.h | 79
2 files changed, 108 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index d5df8fd..4ba5184 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1143,7 +1143,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
}
if (tiling_flags & RADEON_TILING_MACRO) {
- if (rdev->family >= CHIP_TAHITI)
+ if (rdev->family >= CHIP_BONAIRE)
+ tmp = rdev->config.cik.tile_config;
+ else if (rdev->family >= CHIP_TAHITI)
tmp = rdev->config.si.tile_config;
else if (rdev->family >= CHIP_CAYMAN)
tmp = rdev->config.cayman.tile_config;
@@ -1170,11 +1172,29 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
+ if (rdev->family >= CHIP_BONAIRE) {
+ /* XXX need to know more about the surface tiling mode
*/
+ fb_format |=
CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
+ }
} else if (tiling_flags & RADEON_TILING_MICRO)
fb_format |=
EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
- if ((rdev->family == CHIP_TAHITI) ||
- (rdev->family == CHIP_PITCAIRN))
+ if (rdev->family >= CHIP_BONAIRE) {
+ u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
+ u32 num_rb = rdev->config.cik.max_backends_per_se;
+ if (num_pipe_configs > 8)
+ num_pipe_configs = 8;
+ if (num_pipe_configs == 8)
+ fb_format |=
CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
+ else if (num_pipe_configs == 4) {
+ if (num_rb == 4)
+ fb_format |=
CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
+ else if (num_rb < 4)
+ fb_format |=
CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
+ } else if (num_pipe_configs == 2)
+ fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
+ } else if ((rdev->family == CHIP_TAHITI) ||
+ (rdev->family == CHIP_PITCAIRN))
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
else if (rdev->family == CHIP_VERDE)
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
@@ -1224,8 +1244,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset,
fb_pitch_pixels);
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
- WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
- target_fb->height);
+ if (rdev->family >= CHIP_BONAIRE)
+ WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ target_fb->height);
+ else
+ WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+ target_fb->height);
x &= ~3;
y &= ~1;
WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index 58b29b5..d71e46d 100644
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -29,6 +29,83 @@
#define CIK_DC_GPIO_HPD_EN0x65b8
#define CIK_DC_GPIO_HPD_Y 0x65bc
+#define CIK_GRPH_CONTROL 0x6804
+# define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
+# define CIK_GRPH_DEPTH_8BPP0
+# define CIK_GRPH_DEPTH_16BPP 1
+# define CIK_GRPH_DEPTH_32BPP 2
+# define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
+# define CIK_ADDR_SURF_2_BANK 0
+# define CIK_ADDR_SURF_4_BANK 1
+# define CIK_ADDR_SURF_8_BANK 2
+# define CIK_ADDR_SURF_16_BANK 3
+# define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
+# define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
+# define CIK_ADDR_SURF_BANK_WIDTH_1 0
+# define CIK_ADDR_SURF_BANK_WIDTH_2 1
+# define CIK_ADDR_SURF_BANK_WIDTH_4 2
+# define CIK_ADDR_SURF_BANK_WIDTH_8 3
+# define CIK_GRPH_FORMAT(x) (((x) & 0x7) <<
[PATCH 048/165] drm/radeon: add UVD support for CIK (v3)
From: Christian König
v2: agd5f: fix clock dividers setup for bonaire
v3: agd5f: rebase
Signed-off-by: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 111 ++
drivers/gpu/drm/radeon/cikd.h| 28 +
drivers/gpu/drm/radeon/radeon_asic.h |2 +
drivers/gpu/drm/radeon/radeon_uvd.c |8 +++
4 files changed, 149 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e8ea845..29e0cdd 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1495,6 +1495,9 @@ static void cik_gpu_init(struct radeon_device *rdev)
WREG32(DMIF_ADDR_CALC, gb_addr_config);
WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config &
0x70);
WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config &
0x70);
+ WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+ WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
cik_tiling_mode_table_init(rdev);
@@ -4906,6 +4909,16 @@ static int cik_startup(struct radeon_device *rdev)
return r;
}
+ r = cik_uvd_resume(rdev);
+ if (!r) {
+ r = radeon_fence_driver_start_ring(rdev,
+ R600_RING_TYPE_UVD_INDEX);
+ if (r)
+ dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
+ }
+ if (r)
+ rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
+
/* Enable IRQ */
if (!rdev->irq.installed) {
r = radeon_irq_kms_init(rdev);
@@ -4952,6 +4965,18 @@ static int cik_startup(struct radeon_device *rdev)
if (r)
return r;
+ ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+ if (ring->ring_size) {
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
+R600_WB_UVD_RPTR_OFFSET,
+UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
+0, 0xf, RADEON_CP_PACKET2);
+ if (!r)
+ r = r600_uvd_init(rdev);
+ if (r)
+ DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
+ }
+
r = radeon_ib_pool_init(rdev);
if (r) {
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
@@ -5013,6 +5038,8 @@ int cik_suspend(struct radeon_device *rdev)
radeon_vm_manager_fini(rdev);
cik_cp_enable(rdev, false);
cik_sdma_enable(rdev, false);
+ r600_uvd_rbc_stop(rdev);
+ radeon_uvd_suspend(rdev);
cik_irq_suspend(rdev);
radeon_wb_disable(rdev);
cik_pcie_gart_disable(rdev);
@@ -5096,6 +5123,13 @@ int cik_init(struct radeon_device *rdev)
ring->ring_obj = NULL;
r600_ring_init(rdev, ring, 256 * 1024);
+ r = radeon_uvd_init(rdev);
+ if (!r) {
+ ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
+ ring->ring_obj = NULL;
+ r600_ring_init(rdev, ring, 4096);
+ }
+
rdev->ih.ring_obj = NULL;
r600_ih_ring_init(rdev, 64 * 1024);
@@ -5150,6 +5184,7 @@ void cik_fini(struct radeon_device *rdev)
radeon_vm_manager_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev);
+ radeon_uvd_fini(rdev);
cik_pcie_gart_fini(rdev);
r600_vram_scratch_fini(rdev);
radeon_gem_fini(rdev);
@@ -5717,3 +5752,79 @@ uint64_t cik_get_gpu_clock_counter(struct radeon_device
*rdev)
return clock;
}
+static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
+ u32 cntl_reg, u32 status_reg)
+{
+ int r, i;
+ struct atom_clock_dividers dividers;
+ uint32_t tmp;
+
+ r = radeon_atom_get_clock_dividers(rdev,
COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
+ clock, false, ÷rs);
+ if (r)
+ return r;
+
+ tmp = RREG32_SMC(cntl_reg);
+ tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
+ tmp |= dividers.post_divider;
+ WREG32_SMC(cntl_reg, tmp);
+
+ for (i = 0; i < 100; i++) {
+ if (RREG32_SMC(status_reg) & DCLK_STATUS)
+ break;
+ mdelay(10);
+ }
+ if (i == 100)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
+{
+ int r = 0;
+
+ r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
+ if (r)
+ return r;
+
+ r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
+ return r;
+}
+
+int cik_uvd_resume(struct radeon_device *rdev)
+{
+ uint64_t addr;
+ uint32_t size;
+ int r;
+
+ r = radeon_uvd_res
[PATCH 049/165] drm/radeon/cik: add srbm_select function
From: Alex Deucher
Allows us to select instanced registers based on:
- ME (micro engine
- Pipe
- Queue
- VMID
Switch MC setup to use this new function.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 27 +--
1 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 29e0cdd..bb7dbc4 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -163,6 +163,29 @@ static const u32
bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
{0x009f, 0x00b48000}
};
+/**
+ * cik_srbm_select - select specific register instances
+ *
+ * @rdev: radeon_device pointer
+ * @me: selected ME (micro engine)
+ * @pipe: pipe
+ * @queue: queue
+ * @vmid: VMID
+ *
+ * Switches the currently active registers instances. Some
+ * registers are instanced per VMID, others are instanced per
+ * me/pipe/queue combination.
+ */
+static void cik_srbm_select(struct radeon_device *rdev,
+ u32 me, u32 pipe, u32 queue, u32 vmid)
+{
+ u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
+MEID(me & 0x3) |
+VMID(vmid & 0xf) |
+QUEUEID(queue & 0x7));
+ WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
+}
+
/* ucode loading */
/**
* ci_mc_load_microcode - load MC ucode into the hw
@@ -3351,7 +3374,7 @@ static int cik_pcie_gart_enable(struct radeon_device
*rdev)
/* XXX SH_MEM regs */
/* where to put LDS, scratch, GPUVM in FSA64 space */
for (i = 0; i < 16; i++) {
- WREG32(SRBM_GFX_CNTL, VMID(i));
+ cik_srbm_select(rdev, 0, 0, 0, i);
/* CP and shaders */
WREG32(SH_MEM_CONFIG, 0);
WREG32(SH_MEM_APE1_BASE, 1);
@@ -3364,7 +3387,7 @@ static int cik_pcie_gart_enable(struct radeon_device
*rdev)
WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
/* XXX SDMA RLC - todo */
}
- WREG32(SRBM_GFX_CNTL, 0);
+ cik_srbm_select(rdev, 0, 0, 0, 0);
cik_pcie_gart_tlb_flush(rdev);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
--
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[PATCH 037/165] drm/radeon: Handle PPLL0 powerdown on DCE8
From: Alex Deucher Only Bonaire has PPLL0. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 590e4eb..24eee7c 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1931,7 +1931,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) break; case ATOM_PPLL0: /* disable the ppll */ - if (ASIC_IS_DCE61(rdev)) + if ((rdev->family == CHIP_ARUBA) || (rdev->family == CHIP_BONAIRE)) atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 050/165] drm/radeon: use callbacks for ring pointer handling
From: Alex Deucher
Add callbacks to the radeon_ring struct to handle
rptr/wptr fetchs and wptr updates.
We currently use one version for all rings, but this
allows us to override with a ring specific versions.
Needed for compute rings on CIK.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |5 +++
drivers/gpu/drm/radeon/radeon_ring.c | 55 +
2 files changed, 46 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 9af0fa6..ad4e68a 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -695,6 +695,11 @@ struct radeon_ring {
u32 idx;
u64 last_semaphore_signal_addr;
u64 last_semaphore_wait_addr;
+ struct {
+ u32 (*get_rptr)(struct radeon_device *rdev,
struct radeon_ring *ring);
+ u32 (*get_wptr)(struct radeon_device *rdev,
struct radeon_ring *ring);
+ void(*set_wptr)(struct radeon_device *rdev,
struct radeon_ring *ring);
+ } funcs;
};
/*
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c
b/drivers/gpu/drm/radeon/radeon_ring.c
index e17faa7..53018e9 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -357,6 +357,38 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device
*rdev,
}
}
+static u32 radeon_ring_get_rptr(struct radeon_device *rdev,
+ struct radeon_ring *ring)
+{
+ u32 rptr;
+
+ if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
+ rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
+ else
+ rptr = RREG32(ring->rptr_reg);
+ rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+
+ return rptr;
+}
+
+static u32 radeon_ring_get_wptr(struct radeon_device *rdev,
+ struct radeon_ring *ring)
+{
+ u32 wptr;
+
+ wptr = RREG32(ring->wptr_reg);
+ wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+
+ return wptr;
+}
+
+static void radeon_ring_set_wptr(struct radeon_device *rdev,
+struct radeon_ring *ring)
+{
+ WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) &
ring->ptr_reg_mask);
+ (void)RREG32(ring->wptr_reg);
+}
+
/**
* radeon_ring_free_size - update the free size
*
@@ -367,13 +399,7 @@ bool radeon_ring_supports_scratch_reg(struct radeon_device
*rdev,
*/
void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring
*ring)
{
- u32 rptr;
-
- if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
- rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
- else
- rptr = RREG32(ring->rptr_reg);
- ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+ ring->rptr = ring->funcs.get_rptr(rdev, ring);
/* This works because ring_size is a power of 2 */
ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
ring->ring_free_dw -= ring->wptr;
@@ -458,8 +484,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct
radeon_ring *ring)
radeon_ring_write(ring, ring->nop);
}
DRM_MEMORYBARRIER();
- WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) &
ring->ptr_reg_mask);
- (void)RREG32(ring->wptr_reg);
+ ring->funcs.set_wptr(rdev, ring);
}
/**
@@ -561,7 +586,6 @@ void radeon_ring_lockup_update(struct radeon_ring *ring)
bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring
*ring)
{
unsigned long cjiffies, elapsed;
- uint32_t rptr;
cjiffies = jiffies;
if (!time_after(cjiffies, ring->last_activity)) {
@@ -569,8 +593,7 @@ bool radeon_ring_test_lockup(struct radeon_device *rdev,
struct radeon_ring *rin
radeon_ring_lockup_update(ring);
return false;
}
- rptr = RREG32(ring->rptr_reg);
- ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+ ring->rptr = ring->funcs.get_rptr(rdev, ring);
if (ring->rptr != ring->last_rptr) {
/* CP is still working no lockup */
radeon_ring_lockup_update(ring);
@@ -708,6 +731,10 @@ int radeon_ring_init(struct radeon_device *rdev, struct
radeon_ring *ring, unsig
ring->ptr_reg_shift = ptr_reg_shift;
ring->ptr_reg_mask = ptr_reg_mask;
ring->nop = nop;
+ /* set the ptr callbacks */
+ ring->funcs.get_rptr = &radeon_ring_get_rptr;
+ ring->funcs.get_wptr = &radeon_ring_get_wptr;
+ ring->funcs.set_wptr = &radeon_ring_set_wptr;
/* Allocate ring buffer */
if (ring->ring_obj == NULL) {
r = radeon_bo_create(rdev, ring->ring_size, PA
[PATCH 052/165] drm/radeon/cik: Add support for compute queues (v2)
From: Alex Deucher
On CIK, the compute rings work slightly differently than
on previous asics, however the basic concepts are the same.
The main differences:
- New MEC engines for compute queues
- Multiple queues per MEC:
- CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues
-KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues
- Queues can be allocated and scheduled by another queue
- New doorbell aperture allows you to assign space in the aperture
for the wptr which allows for userspace access to queues
v2: add wptr shadow, fix eop setup
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 528 +++-
drivers/gpu/drm/radeon/cikd.h | 62 +
drivers/gpu/drm/radeon/radeon.h| 19 ++
drivers/gpu/drm/radeon/radeon_cs.c |4 +-
4 files changed, 601 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 5c28fa5..9d2d6bb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1687,6 +1687,7 @@ int cik_ring_test(struct radeon_device *rdev, struct
radeon_ring *ring)
radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >>
2));
radeon_ring_write(ring, 0xDEADBEEF);
radeon_ring_unlock_commit(rdev, ring);
+
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(scratch);
if (tmp == 0xDEADBEEF)
@@ -2112,6 +2113,51 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
return 0;
}
+static u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
+struct radeon_ring *ring)
+{
+ u32 rptr;
+
+
+
+ if (rdev->wb.enabled) {
+ rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
+ } else {
+ cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
+ rptr = RREG32(CP_HQD_PQ_RPTR);
+ cik_srbm_select(rdev, 0, 0, 0, 0);
+ }
+ rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+
+ return rptr;
+}
+
+static u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
+struct radeon_ring *ring)
+{
+ u32 wptr;
+
+ if (rdev->wb.enabled) {
+ wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);
+ } else {
+ cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
+ wptr = RREG32(CP_HQD_PQ_WPTR);
+ cik_srbm_select(rdev, 0, 0, 0, 0);
+ }
+ wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
+
+ return wptr;
+}
+
+static void cik_compute_ring_set_wptr(struct radeon_device *rdev,
+ struct radeon_ring *ring)
+{
+ u32 wptr = (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask;
+
+ rdev->wb.wb[ring->wptr_offs/4] = cpu_to_le32(wptr);
+ WDOORBELL32(ring->doorbell_offset, wptr);
+}
+
/**
* cik_cp_compute_enable - enable/disable the compute CP MEs
*
@@ -2176,7 +,8 @@ static int cik_cp_compute_load_microcode(struct
radeon_device *rdev)
*/
static int cik_cp_compute_start(struct radeon_device *rdev)
{
- //todo
+ cik_cp_compute_enable(rdev, true);
+
return 0;
}
@@ -2190,10 +2237,171 @@ static int cik_cp_compute_start(struct radeon_device
*rdev)
*/
static void cik_cp_compute_fini(struct radeon_device *rdev)
{
+ int i, idx, r;
+
cik_cp_compute_enable(rdev, false);
- //todo
+
+ for (i = 0; i < 2; i++) {
+ if (i == 0)
+ idx = CAYMAN_RING_TYPE_CP1_INDEX;
+ else
+ idx = CAYMAN_RING_TYPE_CP2_INDEX;
+
+ if (rdev->ring[idx].mqd_obj) {
+ r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve MQD bo
failed\n", r);
+
+ radeon_bo_unpin(rdev->ring[idx].mqd_obj);
+ radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
+
+ radeon_bo_unref(&rdev->ring[idx].mqd_obj);
+ rdev->ring[idx].mqd_obj = NULL;
+ }
+ }
+}
+
+static void cik_mec_fini(struct radeon_device *rdev)
+{
+ int r;
+
+ if (rdev->mec.hpd_eop_obj) {
+ r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n",
r);
+ radeon_bo_unpin(rdev->mec.hpd_eop_obj);
+ radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
+
+ radeon_bo_unref(&rdev->mec.hpd_eop_obj);
+ rdev->mec.hpd_eop_obj = NULL;
+ }
+}
+
+#define MEC_HPD_SIZE 2048
+
+static int cik_mec_init(struct radeon_device *rdev)
+{
+ int r;
+ u32 *hpd;
+
+ /*
+* KV:2 MEC,
[PATCH 045/165] drm/radeon/cik: add pcie_port indirect register accessors
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 21 +
drivers/gpu/drm/radeon/cikd.h|3 +++
drivers/gpu/drm/radeon/radeon_asic.c |6 +-
drivers/gpu/drm/radeon/radeon_asic.h |2 ++
4 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0db0ebc..e8ea845 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -78,6 +78,27 @@ extern void si_rlc_fini(struct radeon_device *rdev);
extern int si_rlc_init(struct radeon_device *rdev);
static void cik_rlc_stop(struct radeon_device *rdev);
+/*
+ * Indirect registers accessor
+ */
+u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
+{
+ u32 r;
+
+ WREG32(PCIE_INDEX, reg);
+ (void)RREG32(PCIE_INDEX);
+ r = RREG32(PCIE_DATA);
+ return r;
+}
+
+void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+ WREG32(PCIE_INDEX, reg);
+ (void)RREG32(PCIE_INDEX);
+ WREG32(PCIE_DATA, v);
+ (void)RREG32(PCIE_DATA);
+}
+
/**
* cik_get_xclk - get the xclk
*
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index f00e273..d23809a 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -35,6 +35,9 @@
#define CG_CLKPIN_CNTL0xC05001A0
# define XTALIN_DIVIDE (1 << 1)
+#define PCIE_INDEX 0x38
+#define PCIE_DATA 0x3C
+
#define VGA_HDP_CONTROL0x328
#defineVGA_MEMORY_DISABLE (1 << 4)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index a2802b47..717b537 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -126,7 +126,11 @@ static void radeon_register_accessor_init(struct
radeon_device *rdev)
rdev->mc_rreg = &rs780_mc_rreg;
rdev->mc_wreg = &rs780_mc_wreg;
}
- if (rdev->family >= CHIP_R600) {
+
+ if (rdev->family >= CHIP_BONAIRE) {
+ rdev->pciep_rreg = &cik_pciep_rreg;
+ rdev->pciep_wreg = &cik_pciep_wreg;
+ } else if (rdev->family >= CHIP_R600) {
rdev->pciep_rreg = &r600_pciep_rreg;
rdev->pciep_wreg = &r600_pciep_wreg;
}
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 05f75f7..8c19e36 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -558,5 +558,7 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk,
u32 dclk);
*/
uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
u32 cik_get_xclk(struct radeon_device *rdev);
+uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
+void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
#endif
--
1.7.7.5
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 051/165] drm/radeon: implement simple doorbell page allocator
From: Alex Deucher
The doorbell aperture is a PCI BAR whose pages can be
mapped to compute resources for things like wptrs
for userspace queues.
This patch maps the BAR and sets up a simple allocator
to allocate pages from the BAR.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 38 +
drivers/gpu/drm/radeon/radeon.h| 21 +++
drivers/gpu/drm/radeon/radeon_device.c | 94
3 files changed, 153 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index bb7dbc4..5c28fa5 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -121,6 +121,44 @@ u32 cik_get_xclk(struct radeon_device *rdev)
return reference_clock;
}
+/**
+ * cik_mm_rdoorbell - read a doorbell dword
+ *
+ * @rdev: radeon_device pointer
+ * @offset: byte offset into the aperture
+ *
+ * Returns the value in the doorbell aperture at the
+ * requested offset (CIK).
+ */
+u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset)
+{
+ if (offset < rdev->doorbell.size) {
+ return readl(((void __iomem *)rdev->doorbell.ptr) + offset);
+ } else {
+ DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n",
offset);
+ return 0;
+ }
+}
+
+/**
+ * cik_mm_wdoorbell - write a doorbell dword
+ *
+ * @rdev: radeon_device pointer
+ * @offset: byte offset into the aperture
+ * @v: value to write
+ *
+ * Writes @v to the doorbell aperture at the
+ * requested offset (CIK).
+ */
+void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v)
+{
+ if (offset < rdev->doorbell.size) {
+ writel(v, ((void __iomem *)rdev->doorbell.ptr) + offset);
+ } else {
+ DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n",
offset);
+ }
+}
+
#define BONAIRE_IO_MC_REGS_SIZE 36
static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ad4e68a..a2a3430 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -556,6 +556,20 @@ struct radeon_scratch {
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
+/*
+ * GPU doorbell structures, functions & helpers
+ */
+struct radeon_doorbell {
+ u32 num_pages;
+ boolfree[1024];
+ /* doorbell mmio */
+ resource_size_t base;
+ resource_size_t size;
+ void __iomem*ptr;
+};
+
+int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
+void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
/*
* IRQS.
@@ -1711,6 +1725,7 @@ struct radeon_device {
struct radeon_gart gart;
struct radeon_mode_info mode_info;
struct radeon_scratch scratch;
+ struct radeon_doorbell doorbell;
struct radeon_mman mman;
struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
wait_queue_head_t fence_queue;
@@ -1784,6 +1799,9 @@ void r100_mm_wreg(struct radeon_device *rdev, uint32_t
reg, uint32_t v,
u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
+u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 offset);
+void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
+
/*
* Cast helper
*/
@@ -1833,6 +1851,9 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg,
u32 v);
#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
+#define RDOORBELL32(offset) cik_mm_rdoorbell(rdev, (offset))
+#define WDOORBELL32(offset, v) cik_mm_wdoorbell(rdev, (offset), (v))
+
/*
* Indirect registers accessor
*/
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 4e97ff7..82335e3 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -232,6 +232,94 @@ void radeon_scratch_free(struct radeon_device *rdev,
uint32_t reg)
}
/*
+ * GPU doorbell aperture helpers function.
+ */
+/**
+ * radeon_doorbell_init - Init doorbell driver information.
+ *
+ * @rdev: radeon_device pointer
+ *
+ * Init doorbell driver information (CIK)
+ * Returns 0 on success, error on failure.
+ */
+int radeon_doorbell_init(struct radeon_device *rdev)
+{
+ int i;
+
+ /* doorbell bar mapping */
+ rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
+ rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
+
+ /* limit to 4 MB for now */
+ if (rdev->doorbell.size > (4 * 1024 * 1024))
+ rdev->doorbell.size = 4 * 1024 * 1024;
+
+ rdev->doorbell.ptr = ioremap(rdev->
[PATCH 053/165] drm/radeon/cik: switch to type3 nop packet for compute rings
From: Alex Deucher Type 2 packets are deprecated on CIK MEC and we should use type 3 nop packets. Setting the count field to the max value (0x3fff) indicates that only one dword should be skipped like a type 2 packet. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 9d2d6bb..08dc4c2 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -5470,7 +5470,7 @@ static int cik_startup(struct radeon_device *rdev) ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, -0, 0xf, RADEON_CP_PACKET2); +0, 0xf, PACKET3(PACKET3_NOP, 0x3FFF)); if (r) return r; ring->me = 1; /* first MEC */ @@ -5484,7 +5484,7 @@ static int cik_startup(struct radeon_device *rdev) ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, CP_HQD_PQ_RPTR, CP_HQD_PQ_WPTR, -0, 0x, RADEON_CP_PACKET2); +0, 0x, PACKET3(PACKET3_NOP, 0x3FFF)); if (r) return r; /* dGPU only have 1 MEC */ -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 047/165] drm/radeon: update radeon_atom_get_clock_dividers for CIK
From: Alex Deucher
CIK uses a slightly different variant of the table structs
and params.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_atombios.c | 20 +++-
drivers/gpu/drm/radeon/radeon_mode.h |3 +++
2 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 774e354..bf3b924 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2700,6 +2700,8 @@ union get_clock_dividers {
struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
+ struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
+ struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
};
int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
@@ -2794,9 +2796,25 @@ int radeon_atom_get_clock_dividers(struct radeon_device
*rdev,
atom_execute_table(rdev->mode_info.atom_context, index,
(uint32_t *)&args);
- dividers->post_div = args.v4.ucPostDiv;
+ dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
dividers->real_clock = le32_to_cpu(args.v4.ulClock);
break;
+ case 6:
+ /* CI */
+ /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
+ args.v6_in.ulClock.ulComputeClockFlag = clock_type;
+ args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock);/* 10
khz */
+
+ atom_execute_table(rdev->mode_info.atom_context, index,
(uint32_t *)&args);
+
+ dividers->whole_fb_div =
le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
+ dividers->frac_fb_div =
le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
+ dividers->ref_div = args.v6_out.ucPllRefDiv;
+ dividers->post_div = args.v6_out.ucPllPostDiv;
+ dividers->flags = args.v6_out.ucPllCntlFlag;
+ dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
+ dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
+ break;
default:
return -EINVAL;
}
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
b/drivers/gpu/drm/radeon/radeon_mode.h
index 4ed0a4c..576511f 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -514,6 +514,9 @@ struct atom_clock_dividers {
bool enable_dithen;
u32 vco_mode;
u32 real_clock;
+ /* added for CI */
+ u32 post_divider;
+ u32 flags;
};
extern enum radeon_tv_std
--
1.7.7.5
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[PATCH 054/165] drm/radeon: fix up ring functions for compute rings
From: Alex Deucher
The compute rings use RELEASE_MEM rather then EOP
packets for writing fences and there is no SYNC_PFP_ME
packet on the compute rings.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 53 +
1 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 08dc4c2..596bfed 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1706,7 +1706,7 @@ int cik_ring_test(struct radeon_device *rdev, struct
radeon_ring *ring)
}
/**
- * cik_fence_ring_emit - emit a fence on the gfx ring
+ * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
*
* @rdev: radeon_device pointer
* @fence: radeon fence object
@@ -1714,8 +1714,8 @@ int cik_ring_test(struct radeon_device *rdev, struct
radeon_ring *ring)
* Emits a fence sequnce number on the gfx ring and flushes
* GPU caches.
*/
-void cik_fence_ring_emit(struct radeon_device *rdev,
-struct radeon_fence *fence)
+void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
+struct radeon_fence *fence)
{
struct radeon_ring *ring = &rdev->ring[fence->ring];
u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
@@ -1742,6 +1742,44 @@ void cik_fence_ring_emit(struct radeon_device *rdev,
radeon_ring_write(ring, 0);
}
+/**
+ * cik_fence_compute_ring_emit - emit a fence on the compute ring
+ *
+ * @rdev: radeon_device pointer
+ * @fence: radeon fence object
+ *
+ * Emits a fence sequnce number on the compute ring and flushes
+ * GPU caches.
+ */
+void cik_fence_compute_ring_emit(struct radeon_device *rdev,
+struct radeon_fence *fence)
+{
+ struct radeon_ring *ring = &rdev->ring[fence->ring];
+ u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+
+ /* RELEASE_MEM - flush caches, send int */
+ radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
+ radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
+EOP_TC_ACTION_EN |
+EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+EVENT_INDEX(5)));
+ radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
+ radeon_ring_write(ring, addr & 0xfffc);
+ radeon_ring_write(ring, upper_32_bits(addr));
+ radeon_ring_write(ring, fence->seq);
+ radeon_ring_write(ring, 0);
+ /* HDP flush */
+ /* We should be using the new WAIT_REG_MEM special op packet here
+* but it causes the CP to hang
+*/
+ radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+ radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+WRITE_DATA_DST_SEL(0)));
+ radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 0);
+}
+
void cik_semaphore_ring_emit(struct radeon_device *rdev,
struct radeon_ring *ring,
struct radeon_semaphore *semaphore,
@@ -4051,9 +4089,12 @@ void cik_vm_flush(struct radeon_device *rdev, int ridx,
struct radeon_vm *vm)
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 1 << vm->id);
- /* sync PFP to ME, otherwise we might get invalid PFP reads */
- radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
- radeon_ring_write(ring, 0x0);
+ /* compute doesn't have PFP */
+ if (ridx == RADEON_RING_TYPE_GFX_INDEX) {
+ /* sync PFP to ME, otherwise we might get invalid PFP reads */
+ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
+ radeon_ring_write(ring, 0x0);
+ }
}
/**
--
1.7.7.5
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[PATCH 055/165] drm/radeon/cik: add support for compute interrupts
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 121 --
1 files changed, 116 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 596bfed..5923ef7 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4631,6 +4631,8 @@ int cik_irq_set(struct radeon_device *rdev)
{
u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE |
PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
+ u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
+ u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
u32 grbm_int_cntl = 0;
@@ -4658,13 +4660,106 @@ int cik_irq_set(struct radeon_device *rdev)
dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
+ cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+ cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
+
/* enable CP interrupts on all rings */
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
DRM_DEBUG("cik_irq_set: sw int gfx\n");
cp_int_cntl |= TIME_STAMP_INT_ENABLE;
}
- /* TODO: compute queues! */
- /* CP_ME[1-2]_PIPE[0-3]_INT_CNTL */
+ if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
+ struct radeon_ring *ring =
&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
+ DRM_DEBUG("si_irq_set: sw int cp1\n");
+ if (ring->me == 1) {
+ switch (ring->pipe) {
+ case 0:
+ cp_m1p0 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 1:
+ cp_m1p1 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 2:
+ cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 3:
+ cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ default:
+ DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe
%d\n", ring->pipe);
+ break;
+ }
+ } else if (ring->me == 2) {
+ switch (ring->pipe) {
+ case 0:
+ cp_m2p0 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 1:
+ cp_m2p1 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 2:
+ cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 3:
+ cp_m2p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ default:
+ DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe
%d\n", ring->pipe);
+ break;
+ }
+ } else {
+ DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n",
ring->me);
+ }
+ }
+ if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
+ struct radeon_ring *ring =
&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
+ DRM_DEBUG("si_irq_set: sw int cp2\n");
+ if (ring->me == 1) {
+ switch (ring->pipe) {
+ case 0:
+ cp_m1p0 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 1:
+ cp_m1p1 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 2:
+ cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ case 3:
+ cp_m1p2 |= TIME_STAMP_INT_ENABLE;
+ break;
+ default:
+ DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe
%d\n", ring->pipe);
+ bre
[PATCH 056/165] drm/radeon/cik: add support for golden register init
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c | 438 ++
1 files changed, 438 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 5923ef7..e899c44 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -99,6 +99,439 @@ void cik_pciep_wreg(struct radeon_device *rdev, u32 reg,
u32 v)
(void)RREG32(PCIE_DATA);
}
+static const u32 bonaire_golden_spm_registers[] =
+{
+ 0x30800, 0xe0ff, 0xe000
+};
+
+static const u32 bonaire_golden_common_registers[] =
+{
+ 0xc770, 0x, 0x0800,
+ 0xc774, 0x, 0x0800,
+ 0xc798, 0x, 0x7fbf,
+ 0xc79c, 0x, 0x7faf
+};
+
+static const u32 bonaire_golden_registers[] =
+{
+ 0x3354, 0x0333, 0x0333,
+ 0x3350, 0x000c0fc0, 0x00040200,
+ 0x9a10, 0x0001, 0x00058208,
+ 0x3c000, 0x1fff, 0x0014,
+ 0x3c200, 0xfdfc0fff, 0x0100,
+ 0x3c234, 0x4000, 0x4200,
+ 0x9830, 0x, 0x,
+ 0x9834, 0xf00f, 0x0400,
+ 0x9838, 0x0002021c, 0x00020200,
+ 0xc78, 0x0080, 0x,
+ 0x5bb0, 0x00f0, 0x0070,
+ 0x5bc0, 0xf0311fff, 0x8030,
+ 0x98f8, 0x73773777, 0x12010001,
+ 0x350c, 0x0081, 0x408af000,
+ 0x7030, 0x31000111, 0x0011,
+ 0x2f48, 0x73773777, 0x12010001,
+ 0x220c, 0x7fb6, 0x0021a1b1,
+ 0x2210, 0x7fb6, 0x002021b1,
+ 0x2180, 0x7fb6, 0x2191,
+ 0x2218, 0x7fb6, 0x002121b1,
+ 0x221c, 0x7fb6, 0x002021b1,
+ 0x21dc, 0x7fb6, 0x2191,
+ 0x21e0, 0x7fb6, 0x2191,
+ 0x3628, 0x003f, 0x000a,
+ 0x362c, 0x003f, 0x000a,
+ 0x2ae4, 0x00073ffe, 0x22a2,
+ 0x240c, 0x07ff, 0x,
+ 0x8a14, 0xf03f, 0x0007,
+ 0x8bf0, 0x2001, 0x0001,
+ 0x8b24, 0x, 0x00ff,
+ 0x30a04, 0xff0f, 0x,
+ 0x28a4c, 0x07ff, 0x0600,
+ 0x4d8, 0x0fff, 0x0100,
+ 0x3e78, 0x0001, 0x0002,
+ 0x9100, 0x0300, 0x0362c688,
+ 0x8c00, 0x00ff, 0x0001,
+ 0xe40, 0x1fff, 0x1fff,
+ 0x9060, 0x007f, 0x0020,
+ 0x9508, 0x0001, 0x0001,
+ 0xac14, 0x03ff, 0x00f3,
+ 0xac0c, 0x, 0x1032
+};
+
+static const u32 bonaire_mgcg_cgcg_init[] =
+{
+ 0xc420, 0x, 0xfffc,
+ 0x30800, 0x, 0xe000,
+ 0x3c2a0, 0x, 0x0100,
+ 0x3c208, 0x, 0x0100,
+ 0x3c2c0, 0x, 0xc100,
+ 0x3c2c8, 0x, 0xc100,
+ 0x3c2c4, 0x, 0xc100,
+ 0x55e4, 0x, 0x00600100,
+ 0x3c280, 0x, 0x0100,
+ 0x3c214, 0x, 0x06000100,
+ 0x3c220, 0x, 0x0100,
+ 0x3c218, 0x, 0x06000100,
+ 0x3c204, 0x, 0x0100,
+ 0x3c2e0, 0x, 0x0100,
+ 0x3c224, 0x, 0x0100,
+ 0x3c200, 0x, 0x0100,
+ 0x3c230, 0x, 0x0100,
+ 0x3c234, 0x, 0x0100,
+ 0x3c250, 0x, 0x0100,
+ 0x3c254, 0x, 0x0100,
+ 0x3c258, 0x, 0x0100,
+ 0x3c25c, 0x, 0x0100,
+ 0x3c260, 0x, 0x0100,
+ 0x3c27c, 0x, 0x0100,
+ 0x3c278, 0x, 0x0100,
+ 0x3c210, 0x, 0x06000100,
+ 0x3c290, 0x, 0x0100,
+ 0x3c274, 0x, 0x0100,
+ 0x3c2b4, 0x, 0x0100,
+ 0x3c2b0, 0x, 0x0100,
+ 0x3c270, 0x, 0x0100,
+ 0x30800, 0x, 0xe000,
+ 0x3c020, 0x, 0x0001,
+ 0x3c024, 0x, 0x00030002,
+ 0x3c028, 0x, 0x00040007,
+ 0x3c02c, 0x, 0x00060005,
+ 0x3c030, 0x, 0x00090008,
+ 0x3c034, 0x, 0x0001,
+ 0x3c038, 0x, 0x00030002,
+ 0x3c03c, 0x, 0x00040007,
+ 0x3c040, 0x, 0x00060005,
+ 0x3c044, 0x, 0x00090008,
+ 0x3c048, 0x, 0x0001,
+ 0x3c04c, 0x, 0x00030002,
+ 0x3c050, 0x, 0x00040007,
+ 0x3c054, 0x, 0x00060005,
+ 0x3c058, 0x, 0x00090008,
+ 0x3c05c, 0x, 0x0001,
+ 0x3c060, 0x, 0x00030002,
+ 0x3c064, 0x, 0x00040007,
+ 0x3c068, 0x, 0x00060005,
+ 0x3c06c, 0x, 0x00090008,
+ 0x3c070, 0x, 0x0001,
+ 0x3c074, 0x, 0x00030002,
+ 0x3c078, 0x, 0x00040007,
+ 0x3c07c, 0x, 0x00060005,
+ 0x3c080, 0x, 0x00090008,
+ 0x3c084, 0x, 0x0001,
+ 0x3c088, 0x, 0x00030002,
+ 0x3c08c, 0x, 0x0
[PATCH 057/165] drm/radeon: add radeon_asic struct for CIK (v11)
From: Alex Deucher
v2: fix up for latest reset changes
v3: use CP for pt updates for now
v4: update for 2 level PTs
v5: update for ib_parse removal
v6: vm_flush api change
v7: rebase
v8: fix gfx ring function pointers
v9: fix vm_set_page function params
v10: update for compute changes
v11: cleanup for release
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 287 ++
drivers/gpu/drm/radeon/radeon_asic.h | 47 ++
2 files changed, 334 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 717b537..d60adb3 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1923,6 +1923,280 @@ static struct radeon_asic si_asic = {
},
};
+static struct radeon_asic ci_asic = {
+ .init = &cik_init,
+ .fini = &cik_fini,
+ .suspend = &cik_suspend,
+ .resume = &cik_resume,
+ .asic_reset = &cik_asic_reset,
+ .vga_set_state = &r600_vga_set_state,
+ .ioctl_wait_idle = NULL,
+ .gui_idle = &r600_gui_idle,
+ .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+ .get_xclk = &cik_get_xclk,
+ .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
+ .gart = {
+ .tlb_flush = &cik_pcie_gart_tlb_flush,
+ .set_page = &rs600_gart_set_page,
+ },
+ .vm = {
+ .init = &cik_vm_init,
+ .fini = &cik_vm_fini,
+ .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
+ .set_page = &cik_vm_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = {
+ .ib_execute = &cik_ring_ib_execute,
+ .ib_parse = &cik_ib_parse,
+ .emit_fence = &cik_fence_gfx_ring_emit,
+ .emit_semaphore = &cik_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &cik_ring_test,
+ .ib_test = &cik_ib_test,
+ .is_lockup = &cik_gfx_is_lockup,
+ .vm_flush = &cik_vm_flush,
+ },
+ [CAYMAN_RING_TYPE_CP1_INDEX] = {
+ .ib_execute = &cik_ring_ib_execute,
+ .ib_parse = &cik_ib_parse,
+ .emit_fence = &cik_fence_compute_ring_emit,
+ .emit_semaphore = &cik_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &cik_ring_test,
+ .ib_test = &cik_ib_test,
+ .is_lockup = &cik_gfx_is_lockup,
+ .vm_flush = &cik_vm_flush,
+ },
+ [CAYMAN_RING_TYPE_CP2_INDEX] = {
+ .ib_execute = &cik_ring_ib_execute,
+ .ib_parse = &cik_ib_parse,
+ .emit_fence = &cik_fence_compute_ring_emit,
+ .emit_semaphore = &cik_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &cik_ring_test,
+ .ib_test = &cik_ib_test,
+ .is_lockup = &cik_gfx_is_lockup,
+ .vm_flush = &cik_vm_flush,
+ },
+ [R600_RING_TYPE_DMA_INDEX] = {
+ .ib_execute = &cik_sdma_ring_ib_execute,
+ .ib_parse = &cik_ib_parse,
+ .emit_fence = &cik_sdma_fence_ring_emit,
+ .emit_semaphore = &cik_sdma_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &cik_sdma_ring_test,
+ .ib_test = &cik_sdma_ib_test,
+ .is_lockup = &cik_sdma_is_lockup,
+ .vm_flush = &cik_dma_vm_flush,
+ },
+ [CAYMAN_RING_TYPE_DMA1_INDEX] = {
+ .ib_execute = &cik_sdma_ring_ib_execute,
+ .ib_parse = &cik_ib_parse,
+ .emit_fence = &cik_sdma_fence_ring_emit,
+ .emit_semaphore = &cik_sdma_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &cik_sdma_ring_test,
+ .ib_test = &cik_sdma_ib_test,
+ .is_lockup = &cik_sdma_is_lockup,
+ .vm_flush = &cik_dma_vm_flush,
+ },
+ [R600_RING_TYPE_UVD_INDEX] = {
+ .ib_execute = &r600_uvd_ib_execute,
+ .emit_fence = &r600_uvd_fence_emit,
+ .emit_semaphore = &cayman_uvd_semaphore_emit,
+ .cs_parse = &radeon_uvd_cs_parse,
+ .ring_test = &r600_uvd_ring_test,
+ .ib_test = &r600_uvd_ib_test,
+ .is_lockup = &radeon_ring_test_lockup,
+
[PATCH 059/165] drm/radeon: add current Bonaire PCI ids
From: Alex Deucher
Signed-off-by: Alex Deucher
---
include/drm/drm_pciids.h |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index bb1bc48..23f89df 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -152,6 +152,14 @@
{0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_OLAND|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_BONAIRE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_HAINAN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
--
1.7.7.5
___
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[PATCH 058/165] drm/radeon: add cik tile mode array query
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/cik.c|4
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_drv.c |3 ++-
drivers/gpu/drm/radeon/radeon_kms.c | 14 +++---
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e899c44..2cf3521 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1059,6 +1059,7 @@ static void cik_tiling_mode_table_init(struct
radeon_device *rdev)
gb_tile_moden = 0;
break;
}
+ rdev->config.cik.tile_mode_array[reg_offset] =
gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
for (reg_offset = 0; reg_offset <
num_secondary_tile_mode_states; reg_offset++) {
@@ -1277,6 +1278,7 @@ static void cik_tiling_mode_table_init(struct
radeon_device *rdev)
gb_tile_moden = 0;
break;
}
+ rdev->config.cik.tile_mode_array[reg_offset] =
gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4),
gb_tile_moden);
}
} else if (num_rbs < 4) {
@@ -1402,6 +1404,7 @@ static void cik_tiling_mode_table_init(struct
radeon_device *rdev)
gb_tile_moden = 0;
break;
}
+ rdev->config.cik.tile_mode_array[reg_offset] =
gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4),
gb_tile_moden);
}
}
@@ -1619,6 +1622,7 @@ static void cik_tiling_mode_table_init(struct
radeon_device *rdev)
gb_tile_moden = 0;
break;
}
+ rdev->config.cik.tile_mode_array[reg_offset] =
gb_tile_moden;
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
for (reg_offset = 0; reg_offset <
num_secondary_tile_mode_states; reg_offset++) {
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d40d506..83f62aa 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1588,6 +1588,7 @@ struct cik_asic {
unsigned multi_gpu_tile_size;
unsigned tile_config;
+ uint32_t tile_mode_array[32];
};
union radeon_asic_config {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 094e7e5..02709e4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -74,9 +74,10 @@
* 2.31.0 - Add fastfb support for rs690
* 2.32.0 - new info request for rings working
* 2.33.0 - Add SI tiling mode array query
+ * 2.34.0 - Add CIK tiling mode array query
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 33
+#define KMS_DRIVER_MINOR 34
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
b/drivers/gpu/drm/radeon/radeon_kms.c
index c650228..49ff3d1 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -423,15 +423,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
break;
case RADEON_INFO_SI_TILE_MODE_ARRAY:
if (rdev->family >= CHIP_BONAIRE) {
- DRM_DEBUG_KMS("tile mode array is not implemented
yet\n");
+ value = rdev->config.cik.tile_mode_array;
+ value_size = sizeof(uint32_t)*32;
+ } else if (rdev->family >= CHIP_TAHITI) {
+ value = rdev->config.si.tile_mode_array;
+ value_size = sizeof(uint32_t)*32;
+ } else {
+ DRM_DEBUG_KMS("tile mode array is si+ only!\n");
return -EINVAL;
}
- if (rdev->family < CHIP_TAHITI) {
- DRM_DEBUG_KMS("tile mode array is si only!\n");
- return -EINVAL;
- }
- value = rdev->config.si.tile_mode_array;
- value_size = sizeof(uint32_t)*32;
break;
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
--
1.7.7.5
___
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[PATCH 061/165] drm/radeon/kms: add accessors for RCU indirect space
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |6 ++
drivers/gpu/drm/radeon/r600_reg.h |3 +++
drivers/gpu/drm/radeon/radeon.h| 17 +
3 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 0f89ce3..9009dd4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3120,10 +3120,8 @@ static void evergreen_gpu_init(struct radeon_device
*rdev)
u32 efuse_straps_4;
u32 efuse_straps_3;
- WREG32(RCU_IND_INDEX, 0x204);
- efuse_straps_4 = RREG32(RCU_IND_DATA);
- WREG32(RCU_IND_INDEX, 0x203);
- efuse_straps_3 = RREG32(RCU_IND_DATA);
+ efuse_straps_4 = RREG32_RCU(0x204);
+ efuse_straps_3 = RREG32_RCU(0x203);
tmp = (((efuse_straps_4 & 0xf) << 4) |
((efuse_straps_3 & 0xf000) >> 28));
} else {
diff --git a/drivers/gpu/drm/radeon/r600_reg.h
b/drivers/gpu/drm/radeon/r600_reg.h
index 909219b..58c86cc 100644
--- a/drivers/gpu/drm/radeon/r600_reg.h
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -31,6 +31,9 @@
#define R600_PCIE_PORT_INDEX0x0038
#define R600_PCIE_PORT_DATA 0x003c
+#define R600_RCU_INDEX 0x0100
+#define R600_RCU_DATA 0x0104
+
#define R600_MC_VM_FB_LOCATION 0x2180
#defineR600_MC_FB_BASE_MASK0x
#defineR600_MC_FB_BASE_SHIFT 0
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 83f62aa..0814aa7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1851,6 +1851,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32
offset, u32 v);
#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
+#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
+#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask) \
do {\
uint32_t tmp_ = RREG32(reg);\
@@ -1907,6 +1909,21 @@ static inline void tn_smc_wreg(struct radeon_device
*rdev, u32 reg, u32 v)
WREG32(TN_SMC_IND_DATA_0, (v));
}
+static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
+{
+ u32 r;
+
+ WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
+ r = RREG32(R600_RCU_DATA);
+ return r;
+}
+
+static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+ WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
+ WREG32(R600_RCU_DATA, (v));
+}
+
void r100_pll_errata_after_index(struct radeon_device *rdev);
--
1.7.7.5
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[PATCH 060/165] drm/radeon: add current KB pci ids
From: Alex Deucher
Signed-off-by: Alex Deucher
---
include/drm/drm_pciids.h | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 23f89df..34efaf6 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -588,6 +588,22 @@
{0x1002, 0x9808, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9809, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x980A, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_KABINI|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9900, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9901, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9903, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
--
1.7.7.5
___
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[PATCH 062/165] drm/radeon/evergreen: add indirect register accessors for CG registers
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen_reg.h |3 +++
drivers/gpu/drm/radeon/radeon.h| 17 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h
b/drivers/gpu/drm/radeon/evergreen_reg.h
index 50948ac..76630c6b 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -44,6 +44,9 @@
#define EVERGREEN_AUDIO_PLL1_DIV 0x5b4
#define EVERGREEN_AUDIO_PLL1_UNK 0x5bc
+#define EVERGREEN_CG_IND_ADDR 0x8f8
+#define EVERGREEN_CG_IND_DATA 0x8fc
+
#define EVERGREEN_AUDIO_ENABLE 0x5e78
#define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 0814aa7..e73c972 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1853,6 +1853,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32
offset, u32 v);
#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
+#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
+#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
#define WREG32_P(reg, val, mask) \
do {\
uint32_t tmp_ = RREG32(reg);\
@@ -1924,6 +1926,21 @@ static inline void r600_rcu_wreg(struct radeon_device
*rdev, u32 reg, u32 v)
WREG32(R600_RCU_DATA, (v));
}
+static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
+{
+ u32 r;
+
+ WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0x));
+ r = RREG32(EVERGREEN_CG_IND_DATA);
+ return r;
+}
+
+static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
+{
+ WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0x));
+ WREG32(EVERGREEN_CG_IND_DATA, (v));
+}
+
void r100_pll_errata_after_index(struct radeon_device *rdev);
--
1.7.7.5
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[PATCH 063/165] drm/radeon: make get_temperature functions a callback
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |7 ++-
drivers/gpu/drm/radeon/radeon_asic.c |8
drivers/gpu/drm/radeon/radeon_asic.h |5 +
drivers/gpu/drm/radeon/radeon_pm.c | 26 --
4 files changed, 19 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index e73c972..40053c8 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -220,11 +220,6 @@ int radeon_atom_get_clock_dividers(struct radeon_device
*rdev,
struct atom_clock_dividers *dividers);
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8
voltage_type);
void rs690_pm_info(struct radeon_device *rdev);
-extern int rv6xx_get_temp(struct radeon_device *rdev);
-extern int rv770_get_temp(struct radeon_device *rdev);
-extern int evergreen_get_temp(struct radeon_device *rdev);
-extern int sumo_get_temp(struct radeon_device *rdev);
-extern int si_get_temp(struct radeon_device *rdev);
extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
unsigned *tile_split);
@@ -1396,6 +1391,7 @@ struct radeon_asic {
void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
void (*set_clock_gating)(struct radeon_device *rdev, int
enable);
int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32
dclk);
+ int (*get_temperature)(struct radeon_device *rdev);
} pm;
/* pageflipping */
struct {
@@ -2065,6 +2061,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t
v);
#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev),
(l))
#define radeon_set_clock_gating(rdev, e)
(rdev)->asic->pm.set_clock_gating((rdev), (e))
#define radeon_set_uvd_clocks(rdev, v, d)
(rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
+#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
#define radeon_set_surface_reg(rdev, r, f, p, o, s)
((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
#define radeon_clear_surface_reg(rdev, r)
((rdev)->asic->surface.clear_reg((rdev), (r)))
#define radeon_bandwidth_update(rdev)
(rdev)->asic->display.bandwidth_update((rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index d60adb3..f127ea2 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1016,6 +1016,7 @@ static struct radeon_asic r600_asic = {
.get_pcie_lanes = &r600_get_pcie_lanes,
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
+ .get_temperature = &rv6xx_get_temp,
},
.pflip = {
.pre_page_flip = &rs600_pre_page_flip,
@@ -1104,6 +1105,7 @@ static struct radeon_asic rs780_asic = {
.get_pcie_lanes = NULL,
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
+ .get_temperature = &rv6xx_get_temp,
},
.pflip = {
.pre_page_flip = &rs600_pre_page_flip,
@@ -1202,6 +1204,7 @@ static struct radeon_asic rv770_asic = {
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = &radeon_atom_set_clock_gating,
.set_uvd_clocks = &rv770_set_uvd_clocks,
+ .get_temperature = &rv770_get_temp,
},
.pflip = {
.pre_page_flip = &rs600_pre_page_flip,
@@ -1300,6 +1303,7 @@ static struct radeon_asic evergreen_asic = {
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
.set_uvd_clocks = &evergreen_set_uvd_clocks,
+ .get_temperature = &evergreen_get_temp,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
@@ -1398,6 +1402,7 @@ static struct radeon_asic sumo_asic = {
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_uvd_clocks = &sumo_set_uvd_clocks,
+ .get_temperature = &sumo_get_temp,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
@@ -1496,6 +1501,7 @@ static struct radeon_asic btc_asic = {
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
.set_uvd_clocks = &evergreen_set_uvd_clocks,
+ .get_temperature = &evergreen_get_temp,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
@@ -1637,6 +1643,7 @@ static struct radeon_asic cayman_asic = {
.set_pcie_lanes = &r600_set_pcie_lanes,
.set_clock_gating = NULL,
.set_uvd_clocks = &
[PATCH 064/165] drm/radeon: add support for thermal sensor on tn
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ni.c |8
drivers/gpu/drm/radeon/nid.h |3 +++
drivers/gpu/drm/radeon/radeon_asic.c |1 +
drivers/gpu/drm/radeon/radeon_asic.h |1 +
4 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 8458330..f889461 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -692,6 +692,14 @@ out:
return err;
}
+int tn_get_temp(struct radeon_device *rdev)
+{
+ u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
+ int actual_temp = (temp / 8) - 49;
+
+ return actual_temp * 1000;
+}
+
/*
* Core functions
*/
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index e226faf..7b8da52 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -489,6 +489,9 @@
# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0)
# define CACHE_FLUSH_AND_INV_EVENT(0x16 << 0)
+/* TN SMU registers */
+#defineTN_CURRENT_GNB_TEMP 0x1F390
+
/*
* UVD
*/
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index f127ea2..5736377 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1783,6 +1783,7 @@ static struct radeon_asic trinity_asic = {
.set_pcie_lanes = NULL,
.set_clock_gating = NULL,
.set_uvd_clocks = &sumo_set_uvd_clocks,
+ .get_temperature = &tn_get_temp,
},
.pflip = {
.pre_page_flip = &evergreen_pre_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index f1dcb07..8507cae 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -486,6 +486,7 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder,
bool enable);
void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct
drm_display_mode *mode);
int evergreen_get_temp(struct radeon_device *rdev);
int sumo_get_temp(struct radeon_device *rdev);
+int tn_get_temp(struct radeon_device *rdev);
/*
* cayman
--
1.7.7.5
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[PATCH 065/165] drm/radeon/kms: move ucode defines to a separate header
From: Alex Deucher
Avoids confusion and duplication.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c|4 +--
drivers/gpu/drm/radeon/ni.c | 13 +
drivers/gpu/drm/radeon/r600.c | 25 +
drivers/gpu/drm/radeon/radeon_ucode.h | 47 +
4 files changed, 56 insertions(+), 33 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/radeon_ucode.h
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 9009dd4..6b559cb5 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -33,9 +33,7 @@
#include "avivod.h"
#include "evergreen_reg.h"
#include "evergreen_blit_shaders.h"
-
-#define EVERGREEN_PFP_UCODE_SIZE 1120
-#define EVERGREEN_PM4_UCODE_SIZE 1376
+#include "radeon_ucode.h"
static const u32 crtc_offsets[6] =
{
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index f889461..9284346 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -33,6 +33,7 @@
#include "atom.h"
#include "ni_reg.h"
#include "cayman_blit_shaders.h"
+#include "radeon_ucode.h"
extern bool evergreen_is_display_hung(struct radeon_device *rdev);
extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
@@ -47,18 +48,6 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device
*rdev);
extern void si_rlc_fini(struct radeon_device *rdev);
extern int si_rlc_init(struct radeon_device *rdev);
-#define EVERGREEN_PFP_UCODE_SIZE 1120
-#define EVERGREEN_PM4_UCODE_SIZE 1376
-#define EVERGREEN_RLC_UCODE_SIZE 768
-#define BTC_MC_UCODE_SIZE 6024
-
-#define CAYMAN_PFP_UCODE_SIZE 2176
-#define CAYMAN_PM4_UCODE_SIZE 2176
-#define CAYMAN_RLC_UCODE_SIZE 1024
-#define CAYMAN_MC_UCODE_SIZE 6037
-
-#define ARUBA_RLC_UCODE_SIZE 1536
-
/* Firmware Names */
MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
MODULE_FIRMWARE("radeon/BARTS_me.bin");
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6948eb8..6089261 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -38,18 +38,7 @@
#include "r600d.h"
#include "atom.h"
#include "avivod.h"
-
-#define PFP_UCODE_SIZE 576
-#define PM4_UCODE_SIZE 1792
-#define RLC_UCODE_SIZE 768
-#define R700_PFP_UCODE_SIZE 848
-#define R700_PM4_UCODE_SIZE 1360
-#define R700_RLC_UCODE_SIZE 1024
-#define EVERGREEN_PFP_UCODE_SIZE 1120
-#define EVERGREEN_PM4_UCODE_SIZE 1376
-#define EVERGREEN_RLC_UCODE_SIZE 768
-#define CAYMAN_RLC_UCODE_SIZE 1024
-#define ARUBA_RLC_UCODE_SIZE 1536
+#include "radeon_ucode.h"
/* Firmware Names */
MODULE_FIRMWARE("radeon/R600_pfp.bin");
@@ -2246,9 +2235,9 @@ int r600_init_microcode(struct radeon_device *rdev)
me_req_size = R700_PM4_UCODE_SIZE * 4;
rlc_req_size = R700_RLC_UCODE_SIZE * 4;
} else {
- pfp_req_size = PFP_UCODE_SIZE * 4;
- me_req_size = PM4_UCODE_SIZE * 12;
- rlc_req_size = RLC_UCODE_SIZE * 4;
+ pfp_req_size = R600_PFP_UCODE_SIZE * 4;
+ me_req_size = R600_PM4_UCODE_SIZE * 12;
+ rlc_req_size = R600_RLC_UCODE_SIZE * 4;
}
DRM_INFO("Loading %s Microcode\n", chip_name);
@@ -2331,13 +2320,13 @@ static int r600_cp_load_microcode(struct radeon_device
*rdev)
fw_data = (const __be32 *)rdev->me_fw->data;
WREG32(CP_ME_RAM_WADDR, 0);
- for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
+ for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
WREG32(CP_ME_RAM_DATA,
be32_to_cpup(fw_data++));
fw_data = (const __be32 *)rdev->pfp_fw->data;
WREG32(CP_PFP_UCODE_ADDR, 0);
- for (i = 0; i < PFP_UCODE_SIZE; i++)
+ for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
WREG32(CP_PFP_UCODE_DATA,
be32_to_cpup(fw_data++));
@@ -3839,7 +3828,7 @@ static int r600_rlc_init(struct radeon_device *rdev)
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
}
} else {
- for (i = 0; i < RLC_UCODE_SIZE; i++) {
+ for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
WREG32(RLC_UCODE_ADDR, i);
WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
}
diff --git a/drivers/gpu/drm/radeon/radeon_ucode.h
b/drivers/gpu/drm/radeon/radeon_ucode.h
new file mode 100644
index 000..d2642b0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_ucode.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2012 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to perm
Re: [PATCH 0/3] Fix backlight issues on some Windows 8 systems
On mar., 2013-06-25 at 17:08 +0100, Matthew Garrett wrote:
> On Sat, Jun 22, 2013 at 11:46:39PM +0200, Yves-Alexis Perez wrote:
>
> > Before Linux support for acpi_osi("Windows 2012") (and when booting with
> > acpi_osi="!Windows 2012"), brightness keys were handled by the kernel
> > just fine, whether in console, in the display manager or in my desktop
> > environment (Xfce). xfce4-power-manager just needs to be told that the
> > brightness keys are already handled and it doesn't need to do anything.
>
> Right, the kernel has special-casing to hook the backlight keys up to
> the ACPI backlight control. This is an awful thing, because there's no
> way to detect this case other than parsing a single driver-specific
> module parameter.
I'm not sure what that means. To detect what case exactly? That the
brightness is handled by video.ko?
>
> Could this functionality be duplicated across other backlight drivers?
> Not easily. The ACPI driver receives keypresses and performs backlight
> control. The i915 driver doesn't receive keypresses. We could easily tie
> certain keycodes into backlight events, but which backlight should they
> control? You're really starting to get into the kind of complex policy
> decision that's best left to userspace, which is where it should have
> been to begin with.
>
Well, I get the reasoning, but I'm not sure I agree. That means
userspace behavior is inconsistent depending on who does it
(gnome-power-manager, gnome-setting-daemon, whatever), and it usually
means there's nothing handling the brightness before those are running,
not to mention people not running them because they don't run a full
blown desktop environment (until someone starts thinking it's a good
idea to handle brightness in systemd).
And in the end, the user just want the brightness keys to correctly
handle the brightness, full stop. Having multiple brightness daemons
using different policies on different hardware is a nightmare for the
end user, imho. From a user point of view, having it handled all in the
kernel works really pretty fine and is completely transparent (I have to
admit that from that point of view, it was even better when it was
handled by the EC but those times seem long gone).
Regards,
--
Yves-Alexis
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Armada DRM driver on OLPC XO
Hi Russell,
Thanks a lot for writing the Armada DRM driver.
I have tested it on OLPC XO-1.75 (MMP2 aka Armada610) and OLPC XO-4 (MMP3
aka PXA2128). After a bit of fighting, I have it running. Could you share your
X driver, or your methodology for testing hardware cursors? I'd like to test
your work there too.
It's probably easiest to get your cubox driver merged before adding MMP2/MMP3
complications into the mix. At that point, I will hopefully have time to
follow up developing MMP2/MMP3 support, which will involve the points
mentioned below.
A hacky patch is also included below, which makes the driver run on this
platform. I'm prepared to do the heavy lifting in implementing these changes
properly, but any high level guidance would be appreciated, especially as I
am new to the world of graphics.
Ordered roughly from highest to lowest importance:
1. Device tree support
The OLPC XO boots entirely from the device tree, all clocks and things are
defined there. Your current display controller driver is close to
DT-compatibility, the only tricky bit is:
        clk = clk_get_sys("dovefb.0", "extclk");
Not sure how that would translate to DT, or if we can transform that into
something that works for both DT and platform devices. The norm in DT is
that a clock is associated to a specific device, so we could just pull it
off the platform device itself.
2. Panel support.
>From my reading of your patches, on the cubox you drive the hardware as if it
is connected to a panel, but actually it is connected to an encoder chip which
outputs a HDMI signal?
In the OLPC case, we actually have a dumb panel connected to the panel
interface, so we need some driver support there.
The panel definition should come from the device tree, but I already hit a
small headache there. The display controller driver (armada_drv) gets probed
before my panel driver, and armada_drm_load() is not happy if it completes
without a connector/encoder registered. We will either have to force a probe
order somehow, or make the driver be happy to be loaded without a
connector/encoder which would then appear later.
3. Register space conflicts
Already found a couple of register conflicts between your dove and the MMP
platforms. Your LCD_SPU_ADV_REG is something completely different here.
The high bits of the DMA_CTRL0 register is used to select a clock. Â In the
dove and MMP2 case these bits are 31:30 but on MMP3 this is 31:29. Also, OLPC
uses this field to select the LCD clock as a clock source, but your driver
chooses another clock for cubox. So we need ways to represent all of these
differences.
4. Video memory
The driver at the moment requires an area of RAM as video memory, but this
must actually be memory that Linux does not regard as normal available RAM,
since ioremap() is called on it. I guess in your platform code you look at
how much RAM is available and cut out a chunk for graphics memory. Then when
communicating to the MM core how much RAM is available, you do not tell it
about the graphics memory?
I realise I'm talking to the ARM MM guru here, but... can we do better? The
decision to have to "cut out" the memory as above would have to be made during
early boot, before we know if we even have a graphics driver to come along and
make use of that memory. In my case I have similarly hacked our firmware to do
the "cut out" operation when finalizing the DT before booting the kernel.
I would have hoped in a world with CMA and things like that we could now do a
bit better. I tried creating a coherent DMA allocation in armada_drm_load() to
be used as video memory, but this failed later when armada_gem_linear_back()
tried to ioremap it (you probably don't need reminding that ioremap on memory
otherwise available as RAM fails, http://lwn.net/Articles/409689/).
I realise that I can avoid that particular ioremap since we already have the
virtual address available, but I am left wondering how this memory is
accessed by DRM/GEM in other contexts (e.g. when it wants to write image data
in there). If that uses ioremap() as well, then we are in trouble.
5. Output paths
This is something we'll have to address for HDMI output support on OLPC, which
is the lowest priority item on this list, lets get the inbuilt panel going
first!
The way I read your code is that up to 2 CRTC addresses can be defined in
platform data. Each one then gets passed to armada_drm_crtc_create() and the
address is used as a base for register accesses.
Does that mean that the register list in the big armada_hw.h enum is
essentially duplicated exactly? Almost as if the system has 2 separate display
controllers?
Your register list essentially starts at offset 0xc0. What can be found at
offsets below that address?
On MMP2/MMP3 the situation is a bit different. 3 output paths are supported
- two panel paths, and one TV path (which is HDMI - direct output from the
SoC, no separate encoder chip necessary).
These paths are closely related, probably not
Re: [PATCH 0/3] Fix backlight issues on some Windows 8 systems
On mar., 2013-06-25 at 21:54 +0100, Matthew Garrett wrote: > On Tue, Jun 25, 2013 at 10:43:57PM +0200, Yves-Alexis Perez wrote: > > On mar., 2013-06-25 at 17:08 +0100, Matthew Garrett wrote: > > > Right, the kernel has special-casing to hook the backlight keys up to > > > the ACPI backlight control. This is an awful thing, because there's no > > > way to detect this case other than parsing a single driver-specific > > > module parameter. > > > > I'm not sure what that means. To detect what case exactly? That the > > brightness is handled by video.ko? > > That the kernel will automatically handle backlight key presses. Ok, so for detection by userspace? hal managed to do that just fine, it seems that upower doesn't, for some reason. > The behaviour is already inconsistent. If you have an ACPI backlight > interface, hitting the keys makes your brightness change without any > userspace help. If you don't, it doesn't. At least on the same (class of) hardware it always behaves the same. > > > And in the end, the user just want the brightness keys to correctly > > handle the brightness, full stop. Having multiple brightness daemons > > using different policies on different hardware is a nightmare for the > > end user, imho. From a user point of view, having it handled all in the > > kernel works really pretty fine and is completely transparent (I have to > > admit that from that point of view, it was even better when it was > > handled by the EC but those times seem long gone). > > I agree, we should standardise the behaviour. And the only way we can > standardise the behaviour is to leave it up to userspace. > It's pretty clear we disagree on this and that my opinion won't really matter here. But letting userspace handle that just means broken functionality for those who have the chance (apparently) to have an ACPI backlight interface. Regards, -- Yves-Alexis signature.asc Description: This is a digitally signed message part ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 0/3] Fix backlight issues on some Windows 8 systems
On mar., 2013-06-25 at 22:14 +0100, Matthew Garrett wrote: > On Tue, Jun 25, 2013 at 11:10:11PM +0200, Yves-Alexis Perez wrote: > > On mar., 2013-06-25 at 21:54 +0100, Matthew Garrett wrote: > > > I agree, we should standardise the behaviour. And the only way we can > > > standardise the behaviour is to leave it up to userspace. > > > > > It's pretty clear we disagree on this and that my opinion won't really > > matter here. But letting userspace handle that just means broken > > functionality for those who have the chance (apparently) to have an ACPI > > backlight interface. > > Which, as we've already established, you don't - Lenovo broke it. Your > Thinkpad claims to have 100 available levels, and most of them don't > work. The kernel has no way of knowing which levels work and which > don't, so leaving this up to the kernel won't actually fix your system > either. I was referring to “standardize the behaviour by leaving up to userspace”. A lot of thinkpads (for example) (all the pre-windows 8 ones) have a perfectly working ACPI backlight interface. Also, if the kernel has no way of knowing which levels work, I fail to see how userspace can do better. I understand that switching to intel_backlight instead of acpi_video0 follows what Windows 8 recommends but for me it looks orthogonal to the fact ACPI methods now have some awkward (Lenovo) or broken (Dell). I mean, it's not the first time firmware people break some kernel behavior. I know it's usually not easy to contact them, but shouldn't those methods be fixed, instead of somehow blindly switching to graphic drivers? -- Yves-Alexis signature.asc Description: This is a digitally signed message part ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 0/3] Fix backlight issues on some Windows 8 systems
On mar., 2013-06-25 at 22:33 +0100, Matthew Garrett wrote: > > I was referring to “standardize the behaviour by leaving up to > > userspace”. A lot of thinkpads (for example) (all the pre-windows 8 > > ones) have a perfectly working ACPI backlight interface. > > And this patchset won't alter their behaviour. Sorry if I was unclear and if my mail implied that. It was about your remark later in the thread (and the mail from Daniel Vetter) > > > Also, if the kernel has no way of knowing which levels work, I fail to > > see how userspace can do better. > > It can't. That's why this patchset disables the ACPI interface on > Windows 8 systems. > > > I understand that switching to intel_backlight instead of acpi_video0 > > follows what Windows 8 recommends but for me it looks orthogonal to the > > fact ACPI methods now have some awkward (Lenovo) or broken (Dell). I > > mean, it's not the first time firmware people break some kernel > > behavior. I know it's usually not easy to contact them, but shouldn't > > those methods be fixed, instead of somehow blindly switching to graphic > > drivers? > > No. The correct answer to all firmware issues is "Are we making the same > firmware calls as the version of Windows that this hardware thinks it's > running". If Windows 8 doesn't make these calls, we shouldn't make these > calls. But if that introduce regressions, shouldn't workarounds be found then? Sorry if I keep repeating that but brightness keys handling in-kernel is quite a useful feature and losing it (because of the “behave exactly like Windows 8 kernel” policy) is indeed a regression. -- Yves-Alexis signature.asc Description: This is a digitally signed message part ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Packard Bell EasyNote LV need i915.invert_brightness=1
[Daniel Vetter] > Nah, silence just means that your patch fell through the crack while I've > travelled around a bit. Thanks for poking, it's merged now for 3.11 (with > cc: stable) to my drm-intel-next-queued branch. I've slightly bikeshedded > the patch though for formatting. Right. Thank you. Btw, a related question. On the laptop in question, even when I use i915.invert_brightness=1, the kernel still seem to be confused about the brightness values. This causes the KDE system powerdevil to turn off the screen when I log into KDE. https://bugs.kde.org/show_bug.cgi?id=321580 > got some details about the problem, which can be seen from this shell run: % for interface in /sys/class/backlight/*; do echo $interface; cat $interface/max_brightness; cat $interface/actual_brightness; done /sys/class/backlight/acpi_video0 100 0 % The max_brightness value is 100, and the current brightness is 0, which actually is full brightness (and not black screen). This fools powerdevil into turning off the screen while believing it turn it on. Should not the ACPI backlight system also know about the inverted brightness setting, and adjust the /sys/ interface to get these values to behave consistently across all hardware models? Is there some other quirk table for acpi that also need to be updated? -- Happy hacking Petter Reinholdtsen ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 068/165] drm/radeon/kms: add new asic struct for rv6xx (v3)
From: Alex Deucher
Has a different dpm controller than r600.
v2: rebase on gpu reset changes
v3: rebase on get_xclk changes
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 96 --
1 files changed, 91 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 5736377..d9c8e9a 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1025,6 +1025,93 @@ static struct radeon_asic r600_asic = {
},
};
+static struct radeon_asic rv6xx_asic = {
+ .init = &r600_init,
+ .fini = &r600_fini,
+ .suspend = &r600_suspend,
+ .resume = &r600_resume,
+ .vga_set_state = &r600_vga_set_state,
+ .asic_reset = &r600_asic_reset,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .mc_wait_for_idle = &r600_mc_wait_for_idle,
+ .get_xclk = &r600_get_xclk,
+ .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+ .gart = {
+ .tlb_flush = &r600_pcie_gart_tlb_flush,
+ .set_page = &rs600_gart_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = {
+ .ib_execute = &r600_ring_ib_execute,
+ .emit_fence = &r600_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = &r600_cs_parse,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ .is_lockup = &r600_gfx_is_lockup,
+ },
+ [R600_RING_TYPE_DMA_INDEX] = {
+ .ib_execute = &r600_dma_ring_ib_execute,
+ .emit_fence = &r600_dma_fence_ring_emit,
+ .emit_semaphore = &r600_dma_semaphore_ring_emit,
+ .cs_parse = &r600_dma_cs_parse,
+ .ring_test = &r600_dma_ring_test,
+ .ib_test = &r600_dma_ib_test,
+ .is_lockup = &r600_dma_is_lockup,
+ }
+ },
+ .irq = {
+ .set = &r600_irq_set,
+ .process = &r600_irq_process,
+ },
+ .display = {
+ .bandwidth_update = &rv515_bandwidth_update,
+ .get_vblank_counter = &rs600_get_vblank_counter,
+ .wait_for_vblank = &avivo_wait_for_vblank,
+ .set_backlight_level = &atombios_set_backlight_level,
+ .get_backlight_level = &atombios_get_backlight_level,
+ },
+ .copy = {
+ .blit = &r600_copy_blit,
+ .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ .dma = &r600_copy_dma,
+ .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
+ .copy = &r600_copy_dma,
+ .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
+ },
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
+ .hpd = {
+ .init = &r600_hpd_init,
+ .fini = &r600_hpd_fini,
+ .sense = &r600_hpd_sense,
+ .set_polarity = &r600_hpd_set_polarity,
+ },
+ .pm = {
+ .misc = &r600_pm_misc,
+ .prepare = &rs600_pm_prepare,
+ .finish = &rs600_pm_finish,
+ .init_profile = &r600_pm_init_profile,
+ .get_dynpm_state = &r600_pm_get_dynpm_state,
+ .get_engine_clock = &radeon_atom_get_engine_clock,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .get_memory_clock = &radeon_atom_get_memory_clock,
+ .set_memory_clock = &radeon_atom_set_memory_clock,
+ .get_pcie_lanes = &r600_get_pcie_lanes,
+ .set_pcie_lanes = &r600_set_pcie_lanes,
+ .set_clock_gating = NULL,
+ .get_temperature = &rv6xx_get_temp,
+ },
+ .pflip = {
+ .pre_page_flip = &rs600_pre_page_flip,
+ .page_flip = &rs600_page_flip,
+ .post_page_flip = &rs600_post_page_flip,
+ },
+};
+
static struct radeon_asic rs780_asic = {
.init = &r600_init,
.fini = &r600_fini,
@@ -2286,16 +2373,15 @@ int radeon_asic_init(struct radeon_device *rdev)
rdev->asic = &r520_asic;
break;
case CHIP_R600:
+ rdev->asic = &r600_asic;
+ break;
case CHIP_RV610:
case CHIP_RV630:
case CHIP_RV620:
case CHIP_RV635:
case CHIP_RV670:
- rdev->asic = &r600_asic;
- if (rdev->family == CHIP_R600)
- rdev->has_uvd = false;
- else
- rdev->has_uvd = true;
+ rdev->asic = &rv6xx_asic;
+ rdev->has_uvd
[PATCH 070/165] drm/radeon/kms: fix up rs780/rs880 display watermark calc for dpm
From: Alex Deucher
calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/rs690.c | 291 +++-
1 files changed, 167 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 55880d5..d8ddfb3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -248,13 +248,16 @@ struct rs690_watermark {
};
static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
- struct radeon_crtc *crtc,
- struct rs690_watermark *wm)
+struct radeon_crtc *crtc,
+struct rs690_watermark *wm,
+bool low)
{
struct drm_display_mode *mode = &crtc->base.mode;
fixed20_12 a, b, c;
fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
+ fixed20_12 sclk, core_bandwidth, max_bandwidth;
+ u32 selected_sclk;
if (!crtc->base.enabled) {
/* FIXME: wouldn't it better to set priority mark to maximum */
@@ -262,6 +265,21 @@ static void rs690_crtc_bandwidth_compute(struct
radeon_device *rdev,
return;
}
+ if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) &&
+ (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
+ selected_sclk = radeon_dpm_get_sclk(rdev, low);
+ else
+ selected_sclk = rdev->pm.current_sclk;
+
+ /* sclk in Mhz */
+ a.full = dfixed_const(100);
+ sclk.full = dfixed_const(selected_sclk);
+ sclk.full = dfixed_div(sclk, a);
+
+ /* core_bandwidth = sclk(Mhz) * 16 */
+ a.full = dfixed_const(16);
+ core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
+
if (crtc->vsc.full > dfixed_const(2))
wm->num_line_pair.full = dfixed_const(2);
else
@@ -322,36 +340,36 @@ static void rs690_crtc_bandwidth_compute(struct
radeon_device *rdev,
wm->active_time.full = dfixed_div(wm->active_time, a);
/* Maximun bandwidth is the minimun bandwidth of all component */
- rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
+ max_bandwidth = core_bandwidth;
if (rdev->mc.igp_sideport_enabled) {
- if (rdev->pm.max_bandwidth.full >
rdev->pm.sideport_bandwidth.full &&
+ if (max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
rdev->pm.sideport_bandwidth.full)
- rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
+ max_bandwidth = rdev->pm.sideport_bandwidth;
read_delay_latency.full = dfixed_const(370 * 800 * 1000);
read_delay_latency.full = dfixed_div(read_delay_latency,
rdev->pm.igp_sideport_mclk);
} else {
- if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
+ if (max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
rdev->pm.k8_bandwidth.full)
- rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
- if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
+ max_bandwidth = rdev->pm.k8_bandwidth;
+ if (max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
rdev->pm.ht_bandwidth.full)
- rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
+ max_bandwidth = rdev->pm.ht_bandwidth;
read_delay_latency.full = dfixed_const(5000);
}
/* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
a.full = dfixed_const(16);
- rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
+ sclk.full = dfixed_mul(max_bandwidth, a);
a.full = dfixed_const(1000);
- rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
+ sclk.full = dfixed_div(a, sclk);
/* Determine chunk time
* ChunkTime = the time it takes the DCP to send one chunk of data
* to the LB which consists of pipeline delay and inter chunk gap
* sclk = system clock(ns)
*/
a.full = dfixed_const(256 * 13);
- chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
+ chunk_time.full = dfixed_mul(sclk, a);
a.full = dfixed_const(10);
chunk_time.full = dfixed_div(chunk_time, a);
@@ -415,175 +433,200 @@ static void rs690_crtc_bandwidth_compute(struct
radeon_device *rdev,
}
}
-void rs690_bandwidth_update(struct radeon_device *rdev)
+static void rs690_compute_mode_p
[PATCH 069/165] drm/radeon/kms: add common dpm infrastructure
From: Alex Deucher
This adds the common dpm (dynamic power management)
infrastructure:
- dpm callbacks
- dpm init/fini/suspend/resume
- dpm power state selection
No device specific code is enabled yet.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h | 100 +++-
drivers/gpu/drm/radeon/radeon_drv.c |4 +
drivers/gpu/drm/radeon/radeon_pm.c | 496 ++-
3 files changed, 591 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6c445f5..c43673c 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -96,6 +96,7 @@ extern int radeon_pcie_gen2;
extern int radeon_msi;
extern int radeon_lockup_timeout;
extern int radeon_fastfb;
+extern int radeon_dpm;
/*
* Copy from radeon_drv.h so we don't have to include both and have conflicting
@@ -1048,6 +1049,7 @@ struct radeon_wb {
enum radeon_pm_method {
PM_METHOD_PROFILE,
PM_METHOD_DYNPM,
+ PM_METHOD_DPM,
};
enum radeon_dynpm_state {
@@ -1073,11 +1075,23 @@ enum radeon_voltage_type {
};
enum radeon_pm_state_type {
+ /* not used for dpm */
POWER_STATE_TYPE_DEFAULT,
POWER_STATE_TYPE_POWERSAVE,
+ /* user selectable states */
POWER_STATE_TYPE_BATTERY,
POWER_STATE_TYPE_BALANCED,
POWER_STATE_TYPE_PERFORMANCE,
+ /* internal states */
+ POWER_STATE_TYPE_INTERNAL_UVD,
+ POWER_STATE_TYPE_INTERNAL_UVD_SD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD,
+ POWER_STATE_TYPE_INTERNAL_UVD_HD2,
+ POWER_STATE_TYPE_INTERNAL_UVD_MVC,
+ POWER_STATE_TYPE_INTERNAL_BOOT,
+ POWER_STATE_TYPE_INTERNAL_THERMAL,
+ POWER_STATE_TYPE_INTERNAL_ACPI,
+ POWER_STATE_TYPE_INTERNAL_ULV,
};
enum radeon_pm_profile_type {
@@ -1106,12 +1120,16 @@ struct radeon_pm_profile {
enum radeon_int_thermal_type {
THERMAL_TYPE_NONE,
+ THERMAL_TYPE_EXTERNAL,
+ THERMAL_TYPE_EXTERNAL_GPIO,
THERMAL_TYPE_RV6XX,
THERMAL_TYPE_RV770,
+ THERMAL_TYPE_ADT7473_WITH_INTERNAL,
THERMAL_TYPE_EVERGREEN,
THERMAL_TYPE_SUMO,
THERMAL_TYPE_NI,
THERMAL_TYPE_SI,
+ THERMAL_TYPE_EMC2103_WITH_INTERNAL,
THERMAL_TYPE_CI,
};
@@ -1166,6 +1184,60 @@ struct radeon_power_state {
*/
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
+struct radeon_ps {
+ u32 caps; /* vbios flags */
+ u32 class; /* vbios flags */
+ u32 class2; /* vbios flags */
+ /* UVD clocks */
+ u32 vclk;
+ u32 dclk;
+ /* asic priv */
+ void *ps_priv;
+};
+
+struct radeon_dpm_thermal {
+ /* thermal interrupt work */
+ struct work_struct work;
+ /* low temperature threshold */
+ intmin_temp;
+ /* high temperature threshold */
+ intmax_temp;
+ /* was interrupt low to high or high to low */
+ bool high_to_low;
+};
+
+struct radeon_dpm {
+ struct radeon_ps*ps;
+ /* number of valid power states */
+ int num_ps;
+ /* current power state that is active */
+ struct radeon_ps*current_ps;
+ /* requested power state */
+ struct radeon_ps*requested_ps;
+ /* boot up power state */
+ struct radeon_ps*boot_ps;
+ /* default uvd power state */
+ struct radeon_ps*uvd_ps;
+ enum radeon_pm_state_type state;
+ enum radeon_pm_state_type user_state;
+ u32 platform_caps;
+ u32 voltage_response_time;
+ u32 backbias_response_time;
+ void*priv;
+ u32 new_active_crtcs;
+ int new_active_crtc_count;
+ u32 current_active_crtcs;
+ int current_active_crtc_count;
+ /* special states active */
+ boolthermal_active;
+ /* thermal handling */
+ struct radeon_dpm_thermal thermal;
+};
+
+void radeon_dpm_enable_power_state(struct radeon_device *rdev,
+ enum radeon_pm_state_type dpm_state);
+
+
struct radeon_pm {
struct mutexmutex;
/* write locked while reprogramming mclk */
@@ -1219,6 +1291,9 @@ struct radeon_pm {
/* internal thermal controller on rv6xx+ */
enum radeon_int_thermal_type int_thermal_type;
struct device *int_hwmon_dev;
+ /* dpm */
+ booldpm_enabled;
+ struct radeon_dpm dpm;
};
int radeon_pm_get_type_index(struct radeon_device *rdev,
@@ -1416,7 +1491,7 @@ struct radeon_asic {
bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id
hpd);
void (*set_polarity)(struct radeon_device *rdev, enum
radeon_hpd_id hpd);
} h
[PATCH 071/165] drm/radeon/kms: fix up 6xx/7xx display watermark calc for dpm
From: Alex Deucher
Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/rv515.c | 224 +++
1 files changed, 132 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 21c7d7b..8ea1573 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -937,13 +937,16 @@ struct rv515_watermark {
};
static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
- struct radeon_crtc *crtc,
- struct rv515_watermark *wm)
+struct radeon_crtc *crtc,
+struct rv515_watermark *wm,
+bool low)
{
struct drm_display_mode *mode = &crtc->base.mode;
fixed20_12 a, b, c;
fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
+ fixed20_12 sclk;
+ u32 selected_sclk;
if (!crtc->base.enabled) {
/* FIXME: wouldn't it better to set priority mark to maximum */
@@ -951,6 +954,18 @@ static void rv515_crtc_bandwidth_compute(struct
radeon_device *rdev,
return;
}
+ /* rv6xx, rv7xx */
+ if ((rdev->family >= CHIP_RV610) &&
+ (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
+ selected_sclk = radeon_dpm_get_sclk(rdev, low);
+ else
+ selected_sclk = rdev->pm.current_sclk;
+
+ /* sclk in Mhz */
+ a.full = dfixed_const(100);
+ sclk.full = dfixed_const(selected_sclk);
+ sclk.full = dfixed_div(sclk, a);
+
if (crtc->vsc.full > dfixed_const(2))
wm->num_line_pair.full = dfixed_const(2);
else
@@ -1016,7 +1031,7 @@ static void rv515_crtc_bandwidth_compute(struct
radeon_device *rdev,
* sclk = system clock(Mhz)
*/
a.full = dfixed_const(600 * 1000);
- chunk_time.full = dfixed_div(a, rdev->pm.sclk);
+ chunk_time.full = dfixed_div(a, sclk);
read_delay_latency.full = dfixed_const(1000);
/* Determine the worst case latency
@@ -1077,152 +1092,177 @@ static void rv515_crtc_bandwidth_compute(struct
radeon_device *rdev,
}
}
-void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
+static void rv515_compute_mode_priority(struct radeon_device *rdev,
+ struct rv515_watermark *wm0,
+ struct rv515_watermark *wm1,
+ struct drm_display_mode *mode0,
+ struct drm_display_mode *mode1,
+ u32 *d1mode_priority_a_cnt,
+ u32 *d2mode_priority_a_cnt)
{
- struct drm_display_mode *mode0 = NULL;
- struct drm_display_mode *mode1 = NULL;
- struct rv515_watermark wm0;
- struct rv515_watermark wm1;
- u32 tmp;
- u32 d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
- u32 d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
fixed20_12 priority_mark02, priority_mark12, fill_rate;
fixed20_12 a, b;
- if (rdev->mode_info.crtcs[0]->base.enabled)
- mode0 = &rdev->mode_info.crtcs[0]->base.mode;
- if (rdev->mode_info.crtcs[1]->base.enabled)
- mode1 = &rdev->mode_info.crtcs[1]->base.mode;
- rs690_line_buffer_adjust(rdev, mode0, mode1);
-
- rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
- rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
-
- tmp = wm0.lb_request_fifo_depth;
- tmp |= wm1.lb_request_fifo_depth << 16;
- WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
+ *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
+ *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
if (mode0 && mode1) {
- if (dfixed_trunc(wm0.dbpp) > 64)
- a.full = dfixed_div(wm0.dbpp, wm0.num_line_pair);
+ if (dfixed_trunc(wm0->dbpp) > 64)
+ a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
else
- a.full = wm0.num_line_pair.full;
- if (dfixed_trunc(wm1.dbpp) > 64)
- b.full = dfixed_div(wm1.dbpp, wm1.num_line_pair);
+ a.full = wm0->num_line_pair.full;
+ if (dfixed_trunc(wm1->dbpp) > 64)
+ b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
else
- b.full = wm1.num_line_pair.full;
+ b.full = wm1->num_line_pair.full;
[PATCH 072/165] drm/radeon/kms: fix up dce4/5 display watermark calc for dpm
From: Alex Deucher
Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c | 89 ++-
1 files changed, 66 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index b9f64f0..63a1e6e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2122,7 +2122,8 @@ static void evergreen_program_watermarks(struct
radeon_device *rdev,
u32 lb_size, u32 num_heads)
{
struct drm_display_mode *mode = &radeon_crtc->base.mode;
- struct evergreen_wm_params wm;
+ struct evergreen_wm_params wm_low, wm_high;
+ u32 dram_channels;
u32 pixel_period;
u32 line_time = 0;
u32 latency_watermark_a = 0, latency_watermark_b = 0;
@@ -2138,39 +2139,81 @@ static void evergreen_program_watermarks(struct
radeon_device *rdev,
line_time = min((u32)mode->crtc_htotal * pixel_period,
(u32)65535);
priority_a_cnt = 0;
priority_b_cnt = 0;
+ dram_channels = evergreen_get_number_of_dram_channels(rdev);
+
+ /* watermark for high clocks */
+ if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
rdev->pm.dpm_enabled) {
+ wm_high.yclk =
+ radeon_dpm_get_mclk(rdev, false) * 10;
+ wm_high.sclk =
+ radeon_dpm_get_sclk(rdev, false) * 10;
+ } else {
+ wm_high.yclk = rdev->pm.current_mclk * 10;
+ wm_high.sclk = rdev->pm.current_sclk * 10;
+ }
- wm.yclk = rdev->pm.current_mclk * 10;
- wm.sclk = rdev->pm.current_sclk * 10;
- wm.disp_clk = mode->clock;
- wm.src_width = mode->crtc_hdisplay;
- wm.active_time = mode->crtc_hdisplay * pixel_period;
- wm.blank_time = line_time - wm.active_time;
- wm.interlaced = false;
+ wm_high.disp_clk = mode->clock;
+ wm_high.src_width = mode->crtc_hdisplay;
+ wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+ wm_high.blank_time = line_time - wm_high.active_time;
+ wm_high.interlaced = false;
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- wm.interlaced = true;
- wm.vsc = radeon_crtc->vsc;
- wm.vtaps = 1;
+ wm_high.interlaced = true;
+ wm_high.vsc = radeon_crtc->vsc;
+ wm_high.vtaps = 1;
if (radeon_crtc->rmx_type != RMX_OFF)
- wm.vtaps = 2;
- wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
- wm.lb_size = lb_size;
- wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
- wm.num_heads = num_heads;
+ wm_high.vtaps = 2;
+ wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
+ wm_high.lb_size = lb_size;
+ wm_high.dram_channels = dram_channels;
+ wm_high.num_heads = num_heads;
+
+ /* watermark for low clocks */
+ if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
rdev->pm.dpm_enabled) {
+ wm_low.yclk =
+ radeon_dpm_get_mclk(rdev, true) * 10;
+ wm_low.sclk =
+ radeon_dpm_get_sclk(rdev, true) * 10;
+ } else {
+ wm_low.yclk = rdev->pm.current_mclk * 10;
+ wm_low.sclk = rdev->pm.current_sclk * 10;
+ }
+
+ wm_low.disp_clk = mode->clock;
+ wm_low.src_width = mode->crtc_hdisplay;
+ wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+ wm_low.blank_time = line_time - wm_low.active_time;
+ wm_low.interlaced = false;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ wm_low.interlaced = true;
+ wm_low.vsc = radeon_crtc->vsc;
+ wm_low.vtaps = 1;
+ if (radeon_crtc->rmx_type != RMX_OFF)
+ wm_low.vtaps = 2;
+ wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
+ wm_low.lb_size = lb_size;
+ wm_low.dram_channels = dram_channels;
+ wm_low.num_heads = num_heads;
/* set for high clocks */
- latency_watermark_a = min(evergreen_latency_watermark(&wm),
(u32)65535);
+ latency_watermark_a =
min(evergreen_latency_watermark(&
[PATCH 073/165] drm/radeon/kms: fix up dce6 display watermark calc for dpm
From: Alex Deucher
Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 96 +++---
1 files changed, 71 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 813a8a9..882509a 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1792,7 +1792,8 @@ static void dce6_program_watermarks(struct radeon_device
*rdev,
u32 lb_size, u32 num_heads)
{
struct drm_display_mode *mode = &radeon_crtc->base.mode;
- struct dce6_wm_params wm;
+ struct dce6_wm_params wm_low, wm_high;
+ u32 dram_channels;
u32 pixel_period;
u32 line_time = 0;
u32 latency_watermark_a = 0, latency_watermark_b = 0;
@@ -1808,38 +1809,83 @@ static void dce6_program_watermarks(struct
radeon_device *rdev,
priority_a_cnt = 0;
priority_b_cnt = 0;
- wm.yclk = rdev->pm.current_mclk * 10;
- wm.sclk = rdev->pm.current_sclk * 10;
- wm.disp_clk = mode->clock;
- wm.src_width = mode->crtc_hdisplay;
- wm.active_time = mode->crtc_hdisplay * pixel_period;
- wm.blank_time = line_time - wm.active_time;
- wm.interlaced = false;
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- wm.interlaced = true;
- wm.vsc = radeon_crtc->vsc;
- wm.vtaps = 1;
- if (radeon_crtc->rmx_type != RMX_OFF)
- wm.vtaps = 2;
- wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
- wm.lb_size = lb_size;
if (rdev->family == CHIP_ARUBA)
- wm.dram_channels =
evergreen_get_number_of_dram_channels(rdev);
+ dram_channels =
evergreen_get_number_of_dram_channels(rdev);
else
- wm.dram_channels = si_get_number_of_dram_channels(rdev);
- wm.num_heads = num_heads;
+ dram_channels = si_get_number_of_dram_channels(rdev);
+
+ /* watermark for high clocks */
+ if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
rdev->pm.dpm_enabled) {
+ wm_high.yclk =
+ radeon_dpm_get_mclk(rdev, false) * 10;
+ wm_high.sclk =
+ radeon_dpm_get_sclk(rdev, false) * 10;
+ } else {
+ wm_high.yclk = rdev->pm.current_mclk * 10;
+ wm_high.sclk = rdev->pm.current_sclk * 10;
+ }
+
+ wm_high.disp_clk = mode->clock;
+ wm_high.src_width = mode->crtc_hdisplay;
+ wm_high.active_time = mode->crtc_hdisplay * pixel_period;
+ wm_high.blank_time = line_time - wm_high.active_time;
+ wm_high.interlaced = false;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ wm_high.interlaced = true;
+ wm_high.vsc = radeon_crtc->vsc;
+ wm_high.vtaps = 1;
+ if (radeon_crtc->rmx_type != RMX_OFF)
+ wm_high.vtaps = 2;
+ wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
+ wm_high.lb_size = lb_size;
+ wm_high.dram_channels = dram_channels;
+ wm_high.num_heads = num_heads;
+
+ /* watermark for low clocks */
+ if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
rdev->pm.dpm_enabled) {
+ wm_low.yclk =
+ radeon_dpm_get_mclk(rdev, true) * 10;
+ wm_low.sclk =
+ radeon_dpm_get_sclk(rdev, true) * 10;
+ } else {
+ wm_low.yclk = rdev->pm.current_mclk * 10;
+ wm_low.sclk = rdev->pm.current_sclk * 10;
+ }
+
+ wm_low.disp_clk = mode->clock;
+ wm_low.src_width = mode->crtc_hdisplay;
+ wm_low.active_time = mode->crtc_hdisplay * pixel_period;
+ wm_low.blank_time = line_time - wm_low.active_time;
+ wm_low.interlaced = false;
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ wm_low.interlaced = true;
+ wm_low.vsc = radeon_crtc->vsc;
+ wm_low.vtaps = 1;
+ if (radeon_crtc->rmx_type != RMX_OFF)
+ wm_low.vtaps = 2;
+ wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
+ wm_low.lb_size = lb_size;
+ wm_low.dram_channels = dram_channels;
+ wm_low.nu
[PATCH 074/165] drm/radeon/kms: add common r600 dpm functions
From: Alex Deucher
These are shared by rs780/rs880, rv6xx, and newer chips.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |3 +-
drivers/gpu/drm/radeon/r600_dpm.c | 678 +
drivers/gpu/drm/radeon/r600_dpm.h | 210
drivers/gpu/drm/radeon/r600d.h| 213
drivers/gpu/drm/radeon/radeon.h | 13 +
5 files changed, 1116 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/r600_dpm.c
create mode 100644 drivers/gpu/drm/radeon/r600_dpm.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 292fd25..a131a13 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -76,7 +76,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
- si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o
+ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
+ r600_dpm.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
new file mode 100644
index 000..91bc5ab
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -0,0 +1,678 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+
+#include "drmP.h"
+#include "radeon.h"
+#include "r600d.h"
+#include "r600_dpm.h"
+#include "atom.h"
+
+const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
+{
+ R600_UTC_DFLT_00,
+ R600_UTC_DFLT_01,
+ R600_UTC_DFLT_02,
+ R600_UTC_DFLT_03,
+ R600_UTC_DFLT_04,
+ R600_UTC_DFLT_05,
+ R600_UTC_DFLT_06,
+ R600_UTC_DFLT_07,
+ R600_UTC_DFLT_08,
+ R600_UTC_DFLT_09,
+ R600_UTC_DFLT_10,
+ R600_UTC_DFLT_11,
+ R600_UTC_DFLT_12,
+ R600_UTC_DFLT_13,
+ R600_UTC_DFLT_14,
+};
+
+const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
+{
+ R600_DTC_DFLT_00,
+ R600_DTC_DFLT_01,
+ R600_DTC_DFLT_02,
+ R600_DTC_DFLT_03,
+ R600_DTC_DFLT_04,
+ R600_DTC_DFLT_05,
+ R600_DTC_DFLT_06,
+ R600_DTC_DFLT_07,
+ R600_DTC_DFLT_08,
+ R600_DTC_DFLT_09,
+ R600_DTC_DFLT_10,
+ R600_DTC_DFLT_11,
+ R600_DTC_DFLT_12,
+ R600_DTC_DFLT_13,
+ R600_DTC_DFLT_14,
+};
+
+void r600_dpm_print_class_info(u32 class, u32 class2)
+{
+ printk("\tui class: ");
+ switch (class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
+ case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
+ default:
+ printk("none\n");
+ break;
+ case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
+ printk("battery\n");
+ break;
+ case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
+ printk("balanced\n");
+ break;
+ case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
+ printk("performance\n");
+ break;
+ }
+ printk("\tinternal class: ");
+ if (((class & ~ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 0) &&
+ (class2 == 0))
+ printk("none");
+ else {
+ if (class & ATOM_PPLIB_CLASSIFICATION_BOOT)
+ printk("boot ");
+ if (class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
+ printk("thermal ");
+ if (class & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
+ printk("limited_pwr ");
+ if (class & ATOM_PPLIB_CLASSIFICATION_REST)
+ printk("rest ");
+ if (class & ATOM_PPLIB_CLASSIFICAT
[PATCH 075/165] drm/radeon/kms: add dpm support for rs780/rs880
From: Alex Deucher
This adds dpm support for rs780/rs880 asics. This includes:
- clockgating
- dynamic engine clock scaling
- dynamic voltage scaling
set radeon.dpm=1 to enable it.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |2 +-
drivers/gpu/drm/radeon/radeon_asic.c | 12 +
drivers/gpu/drm/radeon/radeon_asic.h | 12 +
drivers/gpu/drm/radeon/radeon_pm.c |7 +
drivers/gpu/drm/radeon/rs780_dpm.c | 894 ++
drivers/gpu/drm/radeon/rs780_dpm.h | 109
drivers/gpu/drm/radeon/rs780d.h | 168 +++
7 files changed, 1203 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/rs780_dpm.c
create mode 100644 drivers/gpu/drm/radeon/rs780_dpm.h
create mode 100644 drivers/gpu/drm/radeon/rs780d.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index a131a13..e44b046 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -77,7 +77,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \
- r600_dpm.o
+ r600_dpm.o rs780_dpm.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index d9c8e9a..db3c930 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1194,6 +1194,18 @@ static struct radeon_asic rs780_asic = {
.set_clock_gating = NULL,
.get_temperature = &rv6xx_get_temp,
},
+ .dpm = {
+ .init = &rs780_dpm_init,
+ .setup_asic = &rs780_dpm_setup_asic,
+ .enable = &rs780_dpm_enable,
+ .disable = &rs780_dpm_disable,
+ .set_power_state = &rs780_dpm_set_power_state,
+ .display_configuration_changed =
&rs780_dpm_display_configuration_changed,
+ .fini = &rs780_dpm_fini,
+ .get_sclk = &rs780_dpm_get_sclk,
+ .get_mclk = &rs780_dpm_get_mclk,
+ .print_power_state = &rs780_dpm_print_power_state,
+ },
.pflip = {
.pre_page_flip = &rs600_pre_page_flip,
.page_flip = &rs600_page_flip,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index 8507cae..134bf57 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -396,6 +396,18 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev);
u32 r600_get_xclk(struct radeon_device *rdev);
uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
int rv6xx_get_temp(struct radeon_device *rdev);
+/* rs780 dpm */
+int rs780_dpm_init(struct radeon_device *rdev);
+int rs780_dpm_enable(struct radeon_device *rdev);
+void rs780_dpm_disable(struct radeon_device *rdev);
+int rs780_dpm_set_power_state(struct radeon_device *rdev);
+void rs780_dpm_setup_asic(struct radeon_device *rdev);
+void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
+void rs780_dpm_fini(struct radeon_device *rdev);
+u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
+u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
+void rs780_dpm_print_power_state(struct radeon_device *rdev,
+struct radeon_ps *ps);
/* uvd */
int r600_uvd_init(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 4f5422e..853a8a2 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1030,6 +1030,13 @@ int radeon_pm_init(struct radeon_device *rdev)
{
/* enable dpm on rv6xx+ */
switch (rdev->family) {
+ case CHIP_RS780:
+ case CHIP_RS880:
+ if (radeon_dpm == 1)
+ rdev->pm.pm_method = PM_METHOD_DPM;
+ else
+ rdev->pm.pm_method = PM_METHOD_PROFILE;
+ break;
default:
/* default to profile method */
rdev->pm.pm_method = PM_METHOD_PROFILE;
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c
b/drivers/gpu/drm/radeon/rs780_dpm.c
new file mode 100644
index 000..f594900
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -0,0 +1,894 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of
[PATCH 067/165] drm/radeon/kms: add atom helper functions for dpm (v3)
From: Alex Deucher
dpm needs access to atombios data and command tables
for setup and calculation of a number of parameters.
v2: endian fix
v3: fix mc reg table bug
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h | 33 ++
drivers/gpu/drm/radeon/radeon_atombios.c | 660 +-
drivers/gpu/drm/radeon/radeon_mode.h | 57 +++
3 files changed, 743 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f4cb768..6c445f5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -219,6 +219,39 @@ int radeon_atom_get_clock_dividers(struct radeon_device
*rdev,
bool strobe_mode,
struct atom_clock_dividers *dividers);
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8
voltage_type);
+int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
+ u16 voltage_level, u8 voltage_type,
+ u32 *gpio_value, u32 *gpio_mask);
+void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
+u32 eng_clock, u32 mem_clock);
+int radeon_atom_get_voltage_step(struct radeon_device *rdev,
+u8 voltage_type, u16 *voltage_step);
+int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
+ u8 voltage_type,
+ u16 nominal_voltage,
+ u16 *true_voltage);
+int radeon_atom_get_min_voltage(struct radeon_device *rdev,
+ u8 voltage_type, u16 *min_voltage);
+int radeon_atom_get_max_voltage(struct radeon_device *rdev,
+ u8 voltage_type, u16 *max_voltage);
+int radeon_atom_get_voltage_table(struct radeon_device *rdev,
+ u8 voltage_type,
+ struct atom_voltage_table *voltage_table);
+bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, u8 voltage_type);
+void radeon_atom_update_memory_dll(struct radeon_device *rdev,
+ u32 mem_clock);
+void radeon_atom_set_ac_timing(struct radeon_device *rdev,
+ u32 mem_clock);
+int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
+ u8 module_index,
+ struct atom_mc_reg_table *reg_table);
+int radeon_atom_get_memory_info(struct radeon_device *rdev,
+ u8 module_index, struct atom_memory_info
*mem_info);
+int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
+bool gddr5, u8 module_index,
+struct atom_memory_clock_range_table
*mclk_range_table);
+int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
+u16 voltage_id, u16 *voltage);
void rs690_pm_info(struct radeon_device *rdev);
extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index bf3b924..90401fd 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -56,10 +56,6 @@ extern void
radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
uint32_t supported_device);
-/* local */
-static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8
voltage_type,
- u16 voltage_id, u16 *voltage);
-
union atom_supported_devices {
struct _ATOM_SUPPORTED_DEVICES_INFO info;
struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
@@ -1516,6 +1512,10 @@ bool radeon_atombios_get_asic_ss_info(struct
radeon_device *rdev,
le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
ss->type =
ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
ss->rate =
le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
+ if ((crev == 2) &&
+ ((id == ASIC_INTERNAL_ENGINE_SS) ||
+(id == ASIC_INTERNAL_MEMORY_SS)))
+ ss->rate /= 100;
return true;
}
}
@@ -1530,6 +1530,9 @@ bool radeon_atombios_get_asic_ss_info(struct
radeon_device *rdev,
le16_to_cpu(ss_inf
[PATCH 082/165] drm/radeon/dpm: let atom control display phy powergating
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/sumo_dpm.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index 67c85c7..f103880 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -813,6 +813,12 @@ static void sumo_program_bootup_state(struct radeon_device
*rdev)
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
{
+/* This bit selects who handles display phy powergating.
+ * Clear the bit to let atom handle it.
+ * Set it to let the driver handle it.
+ * For now we just let atom handle it.
+ */
+#if 0
u32 v = RREG32(DOUT_SCRATCH3);
if (enable)
@@ -821,6 +827,7 @@ void sumo_take_smu_control(struct radeon_device *rdev, bool
enable)
v &= 0xFFFB;
WREG32(DOUT_SCRATCH3, v);
+#endif
}
static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
--
1.7.7.5
___
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 085/165] drm/radeon: add dpm UVD handling for sumo asics
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/sumo_dpm.c | 55 +
drivers/gpu/drm/radeon/sumod.h| 10 +++
2 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index f103880..cef25c4 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -811,6 +811,40 @@ static void sumo_program_bootup_state(struct radeon_device
*rdev)
sumo_power_level_enable(rdev, i, false);
}
+static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev)
+{
+ struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps);
+ struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps);
+
+ if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk)
&&
+ (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk))
+ return;
+
+ if (new_ps->levels[new_ps->num_levels - 1].sclk >=
+ current_ps->levels[current_ps->num_levels - 1].sclk)
+ return;
+
+ radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk,
+ rdev->pm.dpm.requested_ps->dclk);
+}
+
+static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev)
+{
+ struct sumo_ps *new_ps = sumo_get_ps(rdev->pm.dpm.requested_ps);
+ struct sumo_ps *current_ps = sumo_get_ps(rdev->pm.dpm.current_ps);
+
+ if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk)
&&
+ (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk))
+ return;
+
+ if (new_ps->levels[new_ps->num_levels - 1].sclk <
+ current_ps->levels[current_ps->num_levels - 1].sclk)
+ return;
+
+ radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk,
+ rdev->pm.dpm.requested_ps->dclk);
+}
+
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
{
/* This bit selects who handles display phy powergating.
@@ -1096,6 +1130,22 @@ static void sumo_cleanup_asic(struct radeon_device *rdev)
sumo_take_smu_control(rdev, false);
}
+static void sumo_uvd_init(struct radeon_device *rdev)
+{
+ u32 tmp;
+
+ tmp = RREG32(CG_VCLK_CNTL);
+ tmp &= ~VCLK_DIR_CNTL_EN;
+ WREG32(CG_VCLK_CNTL, tmp);
+
+ tmp = RREG32(CG_DCLK_CNTL);
+ tmp &= ~DCLK_DIR_CNTL_EN;
+ WREG32(CG_DCLK_CNTL, tmp);
+
+ /* 100 Mhz */
+ radeon_set_uvd_clocks(rdev, 1, 1);
+}
+
static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
int min_temp, int max_temp)
{
@@ -1188,6 +1238,8 @@ int sumo_dpm_set_power_state(struct radeon_device *rdev)
if (pi->enable_dynamic_patch_ps)
sumo_apply_state_adjust_rules(rdev);
+ if (pi->enable_dpm)
+ sumo_set_uvd_clock_before_set_eng_clock(rdev);
sumo_update_current_power_levels(rdev);
if (pi->enable_boost) {
sumo_enable_boost(rdev, false);
@@ -1211,6 +1263,8 @@ int sumo_dpm_set_power_state(struct radeon_device *rdev)
}
if (pi->enable_boost)
sumo_enable_boost(rdev, true);
+ if (pi->enable_dpm)
+ sumo_set_uvd_clock_after_set_eng_clock(rdev);
return 0;
}
@@ -1237,6 +1291,7 @@ void sumo_dpm_setup_asic(struct radeon_device *rdev)
sumo_program_acpi_power_level(rdev);
sumo_enable_acpi_pm(rdev);
sumo_take_smu_control(rdev, true);
+ sumo_uvd_init(rdev);
}
void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/sumod.h b/drivers/gpu/drm/radeon/sumod.h
index a5deba6..7c9c2d4 100644
--- a/drivers/gpu/drm/radeon/sumod.h
+++ b/drivers/gpu/drm/radeon/sumod.h
@@ -136,6 +136,16 @@
#define CG_SCLK_STATUS 0x604
# define SCLK_OVERCLK_DETECT (1 << 2)
+#define CG_DCLK_CNTL0x610
+# define DCLK_DIVIDER_MASK0x7f
+# define DCLK_DIR_CNTL_EN (1 << 8)
+#define CG_DCLK_STATUS 0x614
+# define DCLK_STATUS (1 << 0)
+#define CG_VCLK_CNTL0x618
+# define VCLK_DIVIDER_MASK0x7f
+# define VCLK_DIR_CNTL_EN (1 << 8)
+#define CG_VCLK_STATUS 0x61c
+
#define GENERAL_PWRMGT 0x63c
# define STATIC_PM_EN (1 << 1)
--
1.7.7.5
___
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[PATCH 083/165] drm/radeon: add dpm UVD handling for r7xx asics
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/rv770_dpm.c | 34 ++
drivers/gpu/drm/radeon/rv770_dpm.h |2 ++
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c
b/drivers/gpu/drm/radeon/rv770_dpm.c
index 8ea6d69..42f559a 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -1427,6 +1427,38 @@ int rv770_set_boot_state(struct radeon_device *rdev)
return 0;
}
+void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev)
+{
+ struct rv7xx_ps *new_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
+ struct rv7xx_ps *current_state = rv770_get_ps(rdev->pm.dpm.current_ps);
+
+ if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk)
&&
+ (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk))
+ return;
+
+ if (new_state->high.sclk >= current_state->high.sclk)
+ return;
+
+ radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk,
+ rdev->pm.dpm.requested_ps->dclk);
+}
+
+void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev)
+{
+ struct rv7xx_ps *new_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
+ struct rv7xx_ps *current_state = rv770_get_ps(rdev->pm.dpm.current_ps);
+
+ if ((rdev->pm.dpm.requested_ps->vclk == rdev->pm.dpm.current_ps->vclk)
&&
+ (rdev->pm.dpm.requested_ps->dclk == rdev->pm.dpm.current_ps->dclk))
+ return;
+
+ if (new_state->high.sclk < current_state->high.sclk)
+ return;
+
+ radeon_set_uvd_clocks(rdev, rdev->pm.dpm.requested_ps->vclk,
+ rdev->pm.dpm.requested_ps->dclk);
+}
+
int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev)
{
if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel))
!= PPSMC_Result_OK)
@@ -1950,6 +1982,7 @@ int rv770_dpm_set_power_state(struct radeon_device *rdev)
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
rv770_restrict_performance_levels_before_switch(rdev);
+ rv770_set_uvd_clock_before_set_eng_clock(rdev);
rv770_halt_smc(rdev);
rv770_upload_sw_state(rdev);
r7xx_program_memory_timing_parameters(rdev);
@@ -1959,6 +1992,7 @@ int rv770_dpm_set_power_state(struct radeon_device *rdev)
rv770_set_sw_state(rdev);
if (pi->dcodt)
rv770_program_dcodt_after_state_switch(rdev);
+ rv770_set_uvd_clock_after_set_eng_clock(rdev);
return 0;
}
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.h
b/drivers/gpu/drm/radeon/rv770_dpm.h
index bd6ea7b..e42c064 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.h
+++ b/drivers/gpu/drm/radeon/rv770_dpm.h
@@ -262,6 +262,8 @@ int rv770_resume_smc(struct radeon_device *rdev);
int rv770_set_sw_state(struct radeon_device *rdev);
int rv770_set_boot_state(struct radeon_device *rdev);
int rv7xx_parse_power_table(struct radeon_device *rdev);
+void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev);
+void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev);
/* smc */
int rv770_read_smc_soft_register(struct radeon_device *rdev,
--
1.7.7.5
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[PATCH 086/165] drm/radeon: add dpm UVD handling for TN asics (v2)
From: Alex Deucher
v2: fix typo noticed by Dan Carpenter
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ppsmc.h |1 +
drivers/gpu/drm/radeon/trinity_dpm.c | 220 ++
drivers/gpu/drm/radeon/trinity_dpm.h | 18 +++
drivers/gpu/drm/radeon/trinity_smc.c |5 +
drivers/gpu/drm/radeon/trinityd.h|5 +
5 files changed, 249 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h
index 8ef479a..3d0786f 100644
--- a/drivers/gpu/drm/radeon/ppsmc.h
+++ b/drivers/gpu/drm/radeon/ppsmc.h
@@ -75,6 +75,7 @@ typedef uint8_t PPSMC_Result;
#define PPSMC_MSG_PG_SIMD_Config((uint32_t) 0x108)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment((uint32_t) 0x11e)
+#define PPSMC_MSG_UVD_DPM_Config((uint32_t) 0x124)
typedef uint16_t PPSMC_Msg;
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c
b/drivers/gpu/drm/radeon/trinity_dpm.c
index c4779a6..1b3822f 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -866,6 +866,117 @@ static void trinity_program_bootup_state(struct
radeon_device *rdev)
trinity_power_level_enable_disable(rdev, i, false);
}
+static void trinity_setup_uvd_clock_table(struct radeon_device *rdev,
+ struct radeon_ps *rps)
+{
+ struct trinity_ps *ps = trinity_get_ps(rps);
+ u32 uvdstates = (ps->vclk_low_divider |
+ps->vclk_high_divider << 8 |
+ps->dclk_low_divider << 16 |
+ps->dclk_high_divider << 24);
+
+ WREG32_SMC(SMU_UVD_DPM_STATES, uvdstates);
+}
+
+static void trinity_setup_uvd_dpm_interval(struct radeon_device *rdev,
+ u32 interval)
+{
+ u32 p, u;
+ u32 tp = RREG32_SMC(PM_TP);
+ u32 val;
+ u32 xclk = sumo_get_xclk(rdev);
+
+ r600_calculate_u_and_p(interval, xclk, 16, &p, &u);
+
+ val = (p + tp - 1) / tp;
+
+ WREG32_SMC(SMU_UVD_DPM_CNTL, val);
+}
+
+static bool trinity_uvd_clocks_zero(struct radeon_ps *rps)
+{
+ if ((rps->vclk == 0) && (rps->dclk == 0))
+ return true;
+ else
+ return false;
+}
+
+static bool trinity_uvd_clocks_equal(struct radeon_ps *rps1,
+struct radeon_ps *rps2)
+{
+ struct trinity_ps *ps1 = trinity_get_ps(rps1);
+ struct trinity_ps *ps2 = trinity_get_ps(rps2);
+
+ if ((rps1->vclk == rps2->vclk) &&
+ (rps1->dclk == rps2->dclk) &&
+ (ps1->vclk_low_divider == ps2->vclk_low_divider) &&
+ (ps1->vclk_high_divider == ps2->vclk_high_divider) &&
+ (ps1->dclk_low_divider == ps2->dclk_low_divider) &&
+ (ps1->dclk_high_divider == ps2->dclk_high_divider))
+ return true;
+ else
+ return false;
+}
+
+static void trinity_setup_uvd_clocks(struct radeon_device *rdev,
+struct radeon_ps *current_rps,
+struct radeon_ps *new_rps)
+{
+ struct trinity_power_info *pi = trinity_get_pi(rdev);
+
+ if (pi->uvd_dpm) {
+ if (trinity_uvd_clocks_zero(new_rps) &&
+ !trinity_uvd_clocks_zero(current_rps)) {
+ trinity_setup_uvd_dpm_interval(rdev, 0);
+ } else if (!trinity_uvd_clocks_zero(new_rps)) {
+ trinity_setup_uvd_clock_table(rdev, new_rps);
+
+ if (trinity_uvd_clocks_zero(current_rps)) {
+ u32 tmp = RREG32(CG_MISC_REG);
+ tmp &= 0xfffd;
+ WREG32(CG_MISC_REG, tmp);
+
+ radeon_set_uvd_clocks(rdev, new_rps->vclk,
new_rps->dclk);
+
+ trinity_setup_uvd_dpm_interval(rdev, 3000);
+ }
+ }
+ trinity_uvd_dpm_config(rdev);
+ } else {
+ if (trinity_uvd_clocks_zero(new_rps) ||
+ trinity_uvd_clocks_equal(new_rps, current_rps))
+ return;
+
+ radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
+ }
+}
+
+static void trinity_set_uvd_clock_before_set_eng_clock(struct radeon_device
*rdev)
+{
+ struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps);
+ struct trinity_ps *current_ps = trinity_get_ps(rdev->pm.dpm.current_ps);
+
+ if (new_ps->levels[new_ps->num_levels - 1].sclk >=
+ current_ps->levels[current_ps->num_levels - 1].sclk)
+ return;
+
+ trinity_setup_uvd_clocks(rdev, rdev->pm.dpm.current_ps,
+rdev->pm.dpm.requested_ps);
+}
+
+static void trinity_set_uvd_clock_after_set_eng_clock(struct radeon_device
*rde
[PATCH 084/165] drm/radeon: add dpm UVD handling for evergreen/btc asics
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c | 62 ++
drivers/gpu/drm/radeon/btc_dpm.h |4 ++
drivers/gpu/drm/radeon/cypress_dpm.c | 10 +-
drivers/gpu/drm/radeon/cypress_dpm.h | 10 +
drivers/gpu/drm/radeon/rv770_dpm.c | 30 +---
drivers/gpu/drm/radeon/rv770_dpm.h |4 ++
drivers/gpu/drm/radeon/rv770_smc.h |1 +
7 files changed, 107 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 6780120..2662ef0 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -1510,6 +1510,46 @@ static int btc_init_smc_table(struct radeon_device *rdev)
pi->sram_end);
}
+static void btc_set_at_for_uvd(struct radeon_device *rdev)
+{
+ struct rv7xx_power_info *pi = rv770_get_pi(rdev);
+ struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
+ int idx = 0;
+
+ if (r600_is_uvd_state(radeon_new_state->class,
radeon_new_state->class2))
+ idx = 1;
+
+ if ((idx == 1) && !eg_pi->smu_uvd_hs) {
+ pi->rlp = 10;
+ pi->rmp = 100;
+ pi->lhp = 100;
+ pi->lmp = 10;
+ } else {
+ pi->rlp = eg_pi->ats[idx].rlp;
+ pi->rmp = eg_pi->ats[idx].rmp;
+ pi->lhp = eg_pi->ats[idx].lhp;
+ pi->lmp = eg_pi->ats[idx].lmp;
+ }
+
+}
+
+static void btc_notify_uvd_to_smc(struct radeon_device *rdev)
+{
+ struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
+ struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+
+ if (r600_is_uvd_state(radeon_new_state->class,
radeon_new_state->class2)) {
+ rv770_write_smc_soft_register(rdev,
+
RV770_SMC_SOFT_REGISTER_uvd_enabled, 1);
+ eg_pi->uvd_enabled = true;
+ } else {
+ rv770_write_smc_soft_register(rdev,
+
RV770_SMC_SOFT_REGISTER_uvd_enabled, 0);
+ eg_pi->uvd_enabled = false;
+ }
+}
+
static int btc_reset_to_default(struct radeon_device *rdev)
{
if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) !=
PPSMC_Result_OK)
@@ -1880,7 +1920,11 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_before_state_change(rdev);
+ rv770_set_uvd_clock_before_set_eng_clock(rdev);
rv770_halt_smc(rdev);
+ btc_set_at_for_uvd(rdev);
+ if (eg_pi->smu_uvd_hs)
+ btc_notify_uvd_to_smc(rdev);
cypress_upload_sw_state(rdev);
if (eg_pi->dynamic_ac_timing)
@@ -1890,6 +1934,7 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
+ rv770_set_uvd_clock_after_set_eng_clock(rdev);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_after_state_change(rdev);
@@ -2093,6 +2138,23 @@ int btc_dpm_init(struct radeon_device *rdev)
pi->mclk_edc_enable_threshold = 4;
eg_pi->mclk_edc_wr_enable_threshold = 4;
+ pi->rlp = RV770_RLP_DFLT;
+ pi->rmp = RV770_RMP_DFLT;
+ pi->lhp = RV770_LHP_DFLT;
+ pi->lmp = RV770_LMP_DFLT;
+
+ eg_pi->ats[0].rlp = RV770_RLP_DFLT;
+ eg_pi->ats[0].rmp = RV770_RMP_DFLT;
+ eg_pi->ats[0].lhp = RV770_LHP_DFLT;
+ eg_pi->ats[0].lmp = RV770_LMP_DFLT;
+
+ eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
+ eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
+ eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
+ eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
+
+ eg_pi->smu_uvd_hs = true;
+
pi->voltage_control =
radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);
diff --git a/drivers/gpu/drm/radeon/btc_dpm.h b/drivers/gpu/drm/radeon/btc_dpm.h
index a095d40..56b1957 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.h
+++ b/drivers/gpu/drm/radeon/btc_dpm.h
@@ -23,6 +23,10 @@
#ifndef __BTC_DPM_H__
#define __BTC_DPM_H__
+#define BTC_RLP_UVD_DFLT 20
+#define BTC_RMP_UVD_DFLT 50
+#define BTC_LHP_UVD_DFLT 50
+#define BTC_LMP_UVD_DFLT 20
#define BARTS_MGCGCGTSSMCTRL_DFLT 0x81944000
#define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e944000
#define CAICOS_MGCGCGTSSMCTRL_DFLT0x46944040
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
b/drivers/gpu/drm/radeon/cypress_dpm.c
index 2345c81..403ee15 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -690,7 +690,8 @@ int cypress
[PATCH 087/165] drm/radeon/kms: enable UVD as needed (v9)
From: Alex Deucher
When using UVD, the driver must switch to a special UVD power
state. In the CS ioctl, switch to the power state and schedule
work to change the power state back, when the work comes up,
check if uvd is still busy and if not, switch back to the user
state, otherwise, reschedule the work.
Note: We really need some better way to decide when to
switch out of the uvd power state. Switching power states
while playback is active make uvd angry.
V2: fix locking.
V3: switch from timer to delayed work
V4: check fence driver for UVD jobs, reduce timeout to
1 second and rearm timeout on activity
v5: rebase on new dpm tree
v6: rebase on interim uvd on demand changes
v7: fix UVD when DPM is disabled
v8: unify non-DPM and DPM UVD handling
v9: remove leftover idle work struct
Signed-off-by: Alex Deucher
Signed-off-by: Christian König
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_cs.c |1 +
drivers/gpu/drm/radeon/radeon_pm.c | 12 +++-
drivers/gpu/drm/radeon/radeon_uvd.c | 24 +++-
4 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 037773d..3b345cc 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1246,6 +1246,7 @@ struct radeon_dpm {
int current_active_crtc_count;
/* special states active */
boolthermal_active;
+ booluvd_active;
/* thermal handling */
struct radeon_dpm_thermal thermal;
};
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c
b/drivers/gpu/drm/radeon/radeon_cs.c
index 7e265a5..4f6b22b 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -550,6 +550,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
return r;
}
+ /* XXX pick SD/HD/MVC */
if (parser.ring == R600_RING_TYPE_UVD_INDEX)
radeon_uvd_note_usage(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index e6fce0b..5987580 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -699,7 +699,8 @@ static void radeon_dpm_change_power_state_locked(struct
radeon_device *rdev)
if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
/* add other state override checks here */
- if (!rdev->pm.dpm.thermal_active)
+ if ((!rdev->pm.dpm.thermal_active) &&
+ (!rdev->pm.dpm.uvd_active))
rdev->pm.dpm.state = rdev->pm.dpm.user_state;
}
dpm_state = rdev->pm.dpm.state;
@@ -769,8 +770,16 @@ void radeon_dpm_enable_power_state(struct radeon_device
*rdev,
case POWER_STATE_TYPE_INTERNAL_THERMAL:
rdev->pm.dpm.thermal_active = true;
break;
+ case POWER_STATE_TYPE_INTERNAL_UVD:
+ case POWER_STATE_TYPE_INTERNAL_UVD_SD:
+ case POWER_STATE_TYPE_INTERNAL_UVD_HD:
+ case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
+ case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
+ rdev->pm.dpm.uvd_active = true;
+ break;
default:
rdev->pm.dpm.thermal_active = false;
+ rdev->pm.dpm.uvd_active = false;
break;
}
rdev->pm.dpm.state = dpm_state;
@@ -1223,6 +1232,7 @@ static void radeon_pm_compute_clocks_dpm(struct
radeon_device *rdev)
radeon_dpm_change_power_state_locked(rdev);
mutex_unlock(&rdev->pm.mutex);
+
}
void radeon_pm_compute_clocks(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c
b/drivers/gpu/drm/radeon/radeon_uvd.c
index fdc77d1..ce5a10c 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -699,11 +699,19 @@ static void radeon_uvd_idle_work_handler(struct
work_struct *work)
struct radeon_device *rdev =
container_of(work, struct radeon_device, uvd.idle_work.work);
- if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0)
- radeon_set_uvd_clocks(rdev, 0, 0);
- else
+ if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
+ if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
rdev->pm.dpm_enabled) {
+ mutex_lock(&rdev->pm.mutex);
+ rdev->pm.dpm.uvd_active = false;
+ mutex_unlock(&rdev->pm.mutex);
+ radeon_pm_compute_clocks(rdev);
+ } else {
+ radeon_set_uvd_clocks(rdev, 0, 0);
+ }
+ } else {
schedule_delayed_work(&rdev->uvd.idle_work,
msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
+ }
}
void radeon_uvd_note_usage(struct radeo
[PATCH 088/165] drm/radeon/dpm: add helpers for extended power tables (v2)
From: Alex Deucher
This data will be needed for dpm on newer asics.
v2: fix typo in rebase
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/r600_dpm.c | 179 +
drivers/gpu/drm/radeon/r600_dpm.h |3 +
drivers/gpu/drm/radeon/radeon.h | 70 ++
3 files changed, 252 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c
b/drivers/gpu/drm/radeon/r600_dpm.c
index bf396a0..c9f9647 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -721,3 +721,182 @@ bool r600_is_internal_thermal_sensor(enum
radeon_int_thermal_type sensor)
return false;
}
}
+
+union power_info {
+ struct _ATOM_POWERPLAY_INFO info;
+ struct _ATOM_POWERPLAY_INFO_V2 info_2;
+ struct _ATOM_POWERPLAY_INFO_V3 info_3;
+ struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
+ struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
+ struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
+ struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
+ struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
+};
+
+union fan_info {
+ struct _ATOM_PPLIB_FANTABLE fan;
+ struct _ATOM_PPLIB_FANTABLE2 fan2;
+};
+
+static int r600_parse_clk_voltage_dep_table(struct
radeon_clock_voltage_dependency_table *radeon_table,
+
ATOM_PPLIB_Clock_Voltage_Dependency_Table *atom_table)
+{
+ u32 size = atom_table->ucNumEntries *
+ sizeof(struct radeon_clock_voltage_dependency_entry);
+ int i;
+
+ radeon_table->entries = kzalloc(size, GFP_KERNEL);
+ if (!radeon_table->entries)
+ return -ENOMEM;
+
+ for (i = 0; i < atom_table->ucNumEntries; i++) {
+ radeon_table->entries[i].clk =
le16_to_cpu(atom_table->entries[i].usClockLow) |
+ (atom_table->entries[i].ucClockHigh << 16);
+ radeon_table->entries[i].v =
le16_to_cpu(atom_table->entries[i].usVoltage);
+ }
+ radeon_table->count = atom_table->ucNumEntries;
+
+ return 0;
+}
+
+int r600_parse_extended_power_table(struct radeon_device *rdev)
+{
+ struct radeon_mode_info *mode_info = &rdev->mode_info;
+ union power_info *power_info;
+ union fan_info *fan_info;
+ ATOM_PPLIB_Clock_Voltage_Dependency_Table *dep_table;
+ int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
+u16 data_offset;
+ u8 frev, crev;
+ int ret, i;
+
+ if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
+ &frev, &crev, &data_offset))
+ return -EINVAL;
+ power_info = (union power_info *)(mode_info->atom_context->bios +
data_offset);
+
+ /* fan table */
+ if (power_info->pplib.usTableSize >= sizeof(struct
_ATOM_PPLIB_POWERPLAYTABLE3)) {
+ if (power_info->pplib3.usFanTableOffset) {
+ fan_info = (union fan_info
*)(mode_info->atom_context->bios + data_offset +
+
le16_to_cpu(power_info->pplib3.usFanTableOffset));
+ rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst;
+ rdev->pm.dpm.fan.t_min =
le16_to_cpu(fan_info->fan.usTMin);
+ rdev->pm.dpm.fan.t_med =
le16_to_cpu(fan_info->fan.usTMed);
+ rdev->pm.dpm.fan.t_high =
le16_to_cpu(fan_info->fan.usTHigh);
+ rdev->pm.dpm.fan.pwm_min =
le16_to_cpu(fan_info->fan.usPWMMin);
+ rdev->pm.dpm.fan.pwm_med =
le16_to_cpu(fan_info->fan.usPWMMed);
+ rdev->pm.dpm.fan.pwm_high =
le16_to_cpu(fan_info->fan.usPWMHigh);
+ if (fan_info->fan.ucFanTableFormat >= 2)
+ rdev->pm.dpm.fan.t_max =
le16_to_cpu(fan_info->fan2.usTMax);
+ else
+ rdev->pm.dpm.fan.t_max = 10900;
+ rdev->pm.dpm.fan.cycle_delay = 10;
+ rdev->pm.dpm.fan.ucode_fan_control = true;
+ }
+ }
+
+ /* clock dependancy tables */
+ if (power_info->pplib.usTableSize >= sizeof(struct
_ATOM_PPLIB_POWERPLAYTABLE4)) {
+ if (power_info->pplib4.usVddcDependencyOnSCLKOffset) {
+ dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table
*)
+ (mode_info->atom_context->bios + data_offset +
+
le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
+ ret =
r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
+ dep_table);
+ if (ret)
+ return ret;
+ }
+ if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
+ dep_ta
[PATCH 089/165] drm/radeon/dpm: track whether we are on AC or battery
From: Alex Deucher
Driver needs this information to validate power states.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_pm.c |7 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5bdb0bd..53aba4f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1314,6 +1314,7 @@ struct radeon_dpm {
u32 tdp_adjustment;
u16 load_line_slope;
bool power_control;
+ bool ac_power;
/* special states active */
boolthermal_active;
booluvd_active;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 5987580..9ac261f 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -1218,6 +1218,7 @@ static void radeon_pm_compute_clocks_dpm(struct
radeon_device *rdev)
mutex_lock(&rdev->pm.mutex);
+ /* update active crtc counts */
rdev->pm.dpm.new_active_crtcs = 0;
rdev->pm.dpm.new_active_crtc_count = 0;
list_for_each_entry(crtc,
@@ -1229,6 +1230,12 @@ static void radeon_pm_compute_clocks_dpm(struct
radeon_device *rdev)
}
}
+ /* update battery/ac status */
+ if (power_supply_is_system_supplied() > 0)
+ rdev->pm.dpm.ac_power = true;
+ else
+ rdev->pm.dpm.ac_power = false;
+
radeon_dpm_change_power_state_locked(rdev);
mutex_unlock(&rdev->pm.mutex);
--
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[PATCH 090/165] drm/radeon/dpm: fixup dynamic state adjust for sumo
From: Alex Deucher
Use a dedicated copy of the current power state since
we may have to adjust it on the fly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_pm.c | 13 -
drivers/gpu/drm/radeon/sumo_dpm.c |5 +
drivers/gpu/drm/radeon/sumo_dpm.h |1 +
4 files changed, 19 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 53aba4f..a4d8d97 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1294,6 +1294,7 @@ struct radeon_dpm {
struct radeon_ps*boot_ps;
/* default uvd power state */
struct radeon_ps*uvd_ps;
+ struct radeon_pshw_ps;
enum radeon_pm_state_type state;
enum radeon_pm_state_type user_state;
u32 platform_caps;
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 9ac261f..7ee8cf6 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -687,6 +687,17 @@ restart_search:
return NULL;
}
+static void radeon_dpm_update_requested_ps(struct radeon_device *rdev,
+ struct radeon_ps *ps)
+{
+ /* copy the ps to the hw ps and point the requested ps
+* at the hw state in case the driver wants to modify
+* the state dynamically.
+*/
+ rdev->pm.dpm.hw_ps = *ps;
+ rdev->pm.dpm.requested_ps = &rdev->pm.dpm.hw_ps;
+}
+
static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
{
int i;
@@ -707,7 +718,7 @@ static void radeon_dpm_change_power_state_locked(struct
radeon_device *rdev)
ps = radeon_dpm_pick_power_state(rdev, dpm_state);
if (ps)
- rdev->pm.dpm.requested_ps = ps;
+ radeon_dpm_update_requested_ps(rdev, ps);
else
return;
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c
b/drivers/gpu/drm/radeon/sumo_dpm.c
index cef25c4..3805302 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -1072,6 +1072,11 @@ static void sumo_apply_state_adjust_rules(struct
radeon_device *rdev)
u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
u32 i;
+ /* point to the hw copy since this function will modify the ps */
+ pi->hw_ps = *ps;
+ rdev->pm.dpm.hw_ps.ps_priv = &pi->hw_ps;
+ ps = &pi->hw_ps;
+
if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
return sumo_patch_thermal_state(rdev, ps, current_ps);
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.h
b/drivers/gpu/drm/radeon/sumo_dpm.h
index d041a6c..a40b62a 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.h
+++ b/drivers/gpu/drm/radeon/sumo_dpm.h
@@ -129,6 +129,7 @@ struct sumo_power_info {
bool enable_dynamic_patch_ps;
bool enable_dpm;
bool enable_boost;
+ struct sumo_ps hw_ps;
};
#define SUMO_UTC_DFLT_00 0x48
--
1.7.7.5
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[PATCH 091/165] drm/radeon/dpm: fixup dynamic state adjust for TN
From: Alex Deucher
Use a dedicated copy of the current power state since
we may have to adjust it on the fly.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/trinity_dpm.c |5 +
drivers/gpu/drm/radeon/trinity_dpm.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c
b/drivers/gpu/drm/radeon/trinity_dpm.c
index 1b3822f..0c1b50a 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.c
+++ b/drivers/gpu/drm/radeon/trinity_dpm.c
@@ -1379,6 +1379,11 @@ static void trinity_apply_state_adjust_rules(struct
radeon_device *rdev)
bool force_high;
u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count;
+ /* point to the hw copy since this function will modify the ps */
+ pi->hw_ps = *ps;
+ rdev->pm.dpm.hw_ps.ps_priv = &pi->hw_ps;
+ ps = &pi->hw_ps;
+
if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
return trinity_patch_thermal_state(rdev, ps, current_ps);
diff --git a/drivers/gpu/drm/radeon/trinity_dpm.h
b/drivers/gpu/drm/radeon/trinity_dpm.h
index 31100ac..c663aed 100644
--- a/drivers/gpu/drm/radeon/trinity_dpm.h
+++ b/drivers/gpu/drm/radeon/trinity_dpm.h
@@ -110,6 +110,7 @@ struct trinity_power_info {
bool enable_dpm;
bool enable_sclk_ds;
bool uvd_dpm;
+ struct trinity_ps hw_ps;
};
#define TRINITY_AT_DFLT30
--
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[PATCH 092/165] drm/radeon/dpm: fixup dynamic state adjust for btc (v2)
From: Alex Deucher
Use a dedicated copy of the current power state since
we may have to adjust it on the fly.
v2: fix up redundant state sets
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c | 340 ++
drivers/gpu/drm/radeon/btc_dpm.h |2 +
drivers/gpu/drm/radeon/cypress_dpm.h |1 +
drivers/gpu/drm/radeon/radeon.h | 13 ++
drivers/gpu/drm/radeon/radeon_pm.c | 43 -
drivers/gpu/drm/radeon/rv770_dpm.c | 10 +
6 files changed, 400 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 2662ef0..989592e 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -1152,6 +1152,164 @@ static const u32 turks_sysls_enable[] =
#endif
+u32 btc_valid_sclk[] =
+{
+ 5000, 1, 15000, 2, 25000, 3, 35000, 4, 45000,
5,
+ 55000, 6, 65000, 7, 75000, 8, 85000, 9, 95000,
10,
+ 105000, 11, 11500, 12, 125000, 13, 135000, 14, 145000,
15,
+ 155000, 16, 165000, 17, 175000, 18, 185000, 19, 195000,
20
+};
+
+static const struct radeon_blacklist_clocks btc_blacklist_clocks[] =
+{
+{ 1, 3, RADEON_SCLK_UP },
+{ 15000, 3, RADEON_SCLK_UP },
+{ 2, 3, RADEON_SCLK_UP },
+{ 25000, 3, RADEON_SCLK_UP }
+};
+
+static void btc_apply_voltage_dependency_rules(struct
radeon_clock_voltage_dependency_table *table,
+ u32 clock, u16 max_voltage, u16
*voltage)
+{
+ u32 i;
+
+ if ((table == NULL) || (table->count == 0))
+ return;
+
+ for (i= 0; i < table->count; i++) {
+ if (clock <= table->entries[i].clk) {
+ if (*voltage < table->entries[i].v)
+ *voltage = (u16)((table->entries[i].v <
max_voltage) ?
+ table->entries[i].v :
max_voltage);
+ return;
+ }
+ }
+
+ *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
+}
+
+static u32 btc_find_valid_clock(struct radeon_clock_array *clocks,
+ u32 max_clock, u32 requested_clock)
+{
+ unsigned int i;
+
+ if ((clocks == NULL) || (clocks->count == 0))
+ return (requested_clock < max_clock) ? requested_clock :
max_clock;
+
+ for (i = 0; i < clocks->count; i++) {
+ if (clocks->values[i] >= requested_clock)
+ return (clocks->values[i] < max_clock) ?
clocks->values[i] : max_clock;
+ }
+
+ return (clocks->values[clocks->count - 1] < max_clock) ?
+ clocks->values[clocks->count - 1] : max_clock;
+}
+
+static u32 btc_get_valid_mclk(struct radeon_device *rdev,
+ u32 max_mclk, u32 requested_mclk)
+{
+ return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values,
+ max_mclk, requested_mclk);
+}
+
+static u32 btc_get_valid_sclk(struct radeon_device *rdev,
+ u32 max_sclk, u32 requested_sclk)
+{
+ return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values,
+ max_sclk, requested_sclk);
+}
+
+static void btc_skip_blacklist_clocks(struct radeon_device *rdev,
+ const u32 max_sclk, const u32 max_mclk,
+ u32 *sclk, u32 *mclk)
+{
+ int i, num_blacklist_clocks;
+
+ if ((sclk == NULL) || (mclk == NULL))
+ return;
+
+ num_blacklist_clocks = ARRAY_SIZE(btc_blacklist_clocks);
+
+ for (i = 0; i < num_blacklist_clocks; i++) {
+ if ((btc_blacklist_clocks[i].sclk == *sclk) &&
+ (btc_blacklist_clocks[i].mclk == *mclk))
+ break;
+ }
+
+ if (i < num_blacklist_clocks) {
+ if (btc_blacklist_clocks[i].action == RADEON_SCLK_UP) {
+ *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1);
+
+ if (*sclk < max_sclk)
+ btc_skip_blacklist_clocks(rdev, max_sclk,
max_mclk, sclk, mclk);
+ }
+ }
+}
+
+static void btc_adjust_clock_combinations(struct radeon_device *rdev,
+ const struct
radeon_clock_and_voltage_limits *max_limits,
+ struct rv7xx_pl *pl)
+{
+
+ if ((pl->mclk == 0) || (pl->sclk == 0))
+ return;
+
+ if (pl->mclk == pl->sclk)
+ return;
+
+ if (pl->mclk > pl->sclk) {
+ if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) >
rdev->pm.dpm.dyn_state.mclk_sclk_ratio)
+ pl->sclk = btc_get_valid_sclk(rdev,
+
[PATCH 094/165] drm/radeon/cayman: update tdp limits in set_power_state
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ni_dpm.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index 635bf04..44016f2 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -3644,6 +3644,7 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) ret = ni_program_memory_timing_parameters(rdev); if (ret) return ret; + ni_populate_smc_tdp_limits(rdev); rv770_resume_smc(rdev); rv770_set_sw_state(rdev); ni_enable_smc_cac(rdev, true); -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 095/165] drm/radeon/dpm/rs780: restructure code
From: Alex Deucher
Needed to properly handle dynamic state adjustment.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/rs780_dpm.c | 52 ++--
1 files changed, 32 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c
b/drivers/gpu/drm/radeon/rs780_dpm.c
index a1497a6..8af1a04 100644
--- a/drivers/gpu/drm/radeon/rs780_dpm.c
+++ b/drivers/gpu/drm/radeon/rs780_dpm.c
@@ -71,10 +71,11 @@ static void rs780_get_pm_mode_parameters(struct
radeon_device *rdev)
static void rs780_voltage_scaling_enable(struct radeon_device *rdev, bool
enable);
-static int rs780_initialize_dpm_power_state(struct radeon_device *rdev)
+static int rs780_initialize_dpm_power_state(struct radeon_device *rdev,
+ struct radeon_ps *boot_ps)
{
struct atom_clock_dividers dividers;
- struct igp_ps *default_state = rs780_get_ps(rdev->pm.dpm.boot_ps);
+ struct igp_ps *default_state = rs780_get_ps(boot_ps);
int i, ret;
ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
@@ -104,7 +105,8 @@ static int rs780_initialize_dpm_power_state(struct
radeon_device *rdev)
return 0;
}
-static int rs780_initialize_dpm_parameters(struct radeon_device *rdev)
+static int rs780_initialize_dpm_parameters(struct radeon_device *rdev,
+ struct radeon_ps *boot_ps)
{
int ret = 0;
int i;
@@ -140,7 +142,7 @@ static int rs780_initialize_dpm_parameters(struct
radeon_device *rdev)
r600_vid_rt_set_vrt(rdev, R600_VOLTAGERESPONSETIME_DFLT);
r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
- ret = rs780_initialize_dpm_power_state(rdev);
+ ret = rs780_initialize_dpm_power_state(rdev, boot_ps);
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 0);
@@ -401,11 +403,13 @@ static void rs780_force_voltage_to_high(struct
radeon_device *rdev)
WREG32_P(GFX_MACRO_BYPASS_CNTL, 0, ~SPLL_BYPASS_CNTL);
}
-static int rs780_set_engine_clock_scaling(struct radeon_device *rdev)
+static int rs780_set_engine_clock_scaling(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps)
{
struct atom_clock_dividers min_dividers, max_dividers,
current_max_dividers;
- struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
- struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
+ struct igp_ps *new_state = rs780_get_ps(new_ps);
+ struct igp_ps *old_state = rs780_get_ps(old_ps);
int ret;
if ((new_state->sclk_high == old_state->sclk_high) &&
@@ -451,10 +455,12 @@ static int rs780_set_engine_clock_scaling(struct
radeon_device *rdev)
return 0;
}
-static void rs780_set_engine_clock_spc(struct radeon_device *rdev)
+static void rs780_set_engine_clock_spc(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps)
{
- struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
- struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
+ struct igp_ps *new_state = rs780_get_ps(new_ps);
+ struct igp_ps *old_state = rs780_get_ps(old_ps);
struct igp_power_info *pi = rs780_get_pi(rdev);
if ((new_state->sclk_high == old_state->sclk_high) &&
@@ -468,10 +474,12 @@ static void rs780_set_engine_clock_spc(struct
radeon_device *rdev)
}
-static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev)
+static void rs780_activate_engine_clk_scaling(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps)
{
- struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
- struct igp_ps *old_state = rs780_get_ps(rdev->pm.dpm.current_ps);
+ struct igp_ps *new_state = rs780_get_ps(new_ps);
+ struct igp_ps *old_state = rs780_get_ps(old_ps);
if ((new_state->sclk_high == old_state->sclk_high) &&
(new_state->sclk_low == old_state->sclk_low))
@@ -493,9 +501,10 @@ static u32 rs780_get_voltage_for_vddc_level(struct
radeon_device *rdev,
return pi->max_voltage;
}
-static void rs780_enable_voltage_scaling(struct radeon_device *rdev)
+static void rs780_enable_voltage_scaling(struct radeon_device *rdev,
+struct radeon_ps *new_ps)
{
- struct igp_ps *new_state = rs780_get_ps(rdev->pm.dpm.requested_ps);
+ struct igp_ps *new_state = rs780_get_ps(new_ps);
struct igp_power_info *pi = rs780_get_pi(rdev);
enum rs780_vddc_level vddc_high, vddc_low;
@@ -5
[PATCH 096/165] drm/radeon/dpm/rv6xx: restructure code
From: Alex Deucher
Needed to properly handle dynamic state adjustment.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/rv6xx_dpm.c | 115 +--
1 files changed, 69 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c
b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index fa4beb2..e8f07b1 100644
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -961,9 +961,11 @@ static void rv6xx_program_voltage_gpio_pins(struct
radeon_device *rdev)
rv6xx_get_master_voltage_mask(rdev));
}
-static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
bool enable)
+static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ bool enable)
{
- struct rv6xx_ps *new_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
+ struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
if (enable)
radeon_atom_set_voltage(rdev,
@@ -1039,9 +1041,10 @@ static void rv6xx_calculate_ap(struct radeon_device
*rdev,
}
-static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev)
+static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
+ struct radeon_ps *new_ps)
{
- struct rv6xx_ps *new_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
+ struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
@@ -1191,10 +1194,12 @@ static void rv6xx_program_display_gap(struct
radeon_device *rdev)
WREG32(CG_DISPLAY_GAP_CNTL, tmp);
}
-static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev)
+static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
+struct radeon_ps *new_ps,
+struct radeon_ps *old_ps)
{
- struct rv6xx_ps *new_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
- struct rv6xx_ps *old_state = rv6xx_get_ps(rdev->pm.dpm.current_ps);
+ struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
+ struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
u16 safe_voltage;
safe_voltage = (new_state->low.vddc >= old_state->low.vddc) ?
@@ -1207,9 +1212,10 @@ static void rv6xx_set_sw_voltage_to_safe(struct
radeon_device *rdev)
~SW_GPIO_INDEX_MASK);
}
-static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev)
+static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
+ struct radeon_ps *old_ps)
{
- struct rv6xx_ps *old_state = rv6xx_get_ps(rdev->pm.dpm.current_ps);
+ struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
old_state->low.vddc);
@@ -1218,10 +1224,12 @@ static void rv6xx_set_sw_voltage_to_low(struct
radeon_device *rdev)
~SW_GPIO_INDEX_MASK);
}
-static void rv6xx_set_safe_backbias(struct radeon_device *rdev)
+static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps)
{
- struct rv6xx_ps *new_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
- struct rv6xx_ps *old_state = rv6xx_get_ps(rdev->pm.dpm.current_ps);
+ struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
+ struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) &&
(old_state->low.flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE))
@@ -1230,10 +1238,12 @@ static void rv6xx_set_safe_backbias(struct
radeon_device *rdev)
WREG32_P(GENERAL_PWRMGT, 0, ~BACKBIAS_VALUE);
}
-static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev)
+static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
+struct radeon_ps *new_ps,
+struct radeon_ps *old_ps)
{
- struct rv6xx_ps *new_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
- struct rv6xx_ps *old_state = rv6xx_get_ps(rdev->pm.dpm.current_ps);
+ struct rv6xx_ps *new_state = rv6xx_get_ps(new_ps);
+ struct rv6xx_ps *old_state = rv6xx_get_ps(old_ps);
if ((new_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) !=
(old_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2))
@@ -1290,10 +1300,12 @@ static int rv6xx_step_sw_voltage(struct radeon_device
*rdev,
return 0;
}
-static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev)
+static int rv6xx_step_
[PATCH 098/165] drm/radeon/dpm/evergreen: restructure code
From: Alex Deucher
Needed to properly handle dynamic state adjustment.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c | 13 ---
drivers/gpu/drm/radeon/cypress_dpm.c | 62 +
drivers/gpu/drm/radeon/cypress_dpm.h | 20 ---
3 files changed, 53 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 3ae4de6..73a0ba3 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -2243,26 +2243,26 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
rv770_restrict_performance_levels_before_switch(rdev);
if (eg_pi->pcie_performance_request)
- cypress_notify_link_speed_change_before_state_change(rdev);
+ cypress_notify_link_speed_change_before_state_change(rdev,
new_ps, old_ps);
rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
rv770_halt_smc(rdev);
btc_set_at_for_uvd(rdev);
if (eg_pi->smu_uvd_hs)
btc_notify_uvd_to_smc(rdev);
- cypress_upload_sw_state(rdev);
+ cypress_upload_sw_state(rdev, new_ps);
if (eg_pi->dynamic_ac_timing)
- cypress_upload_mc_reg_table(rdev);
+ cypress_upload_mc_reg_table(rdev, new_ps);
- cypress_program_memory_timing_parameters(rdev);
+ cypress_program_memory_timing_parameters(rdev, new_ps);
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
if (eg_pi->pcie_performance_request)
- cypress_notify_link_speed_change_after_state_change(rdev);
+ cypress_notify_link_speed_change_after_state_change(rdev,
new_ps, old_ps);
btc_set_power_state_conditionally_enable_ulv(rdev);
@@ -2273,6 +2273,7 @@ int btc_dpm_enable(struct radeon_device *rdev)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
if (pi->gfx_clock_gating)
btc_cg_clock_gating_default(rdev);
@@ -2325,7 +2326,7 @@ int btc_dpm_enable(struct radeon_device *rdev)
btc_init_smc_table(rdev);
if (eg_pi->dynamic_ac_timing)
- cypress_populate_mc_reg_table(rdev);
+ cypress_populate_mc_reg_table(rdev, boot_ps);
cypress_program_response_times(rdev);
r7xx_start_smc(rdev);
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
b/drivers/gpu/drm/radeon/cypress_dpm.c
index c9026ed..1ce1f08 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -353,10 +353,10 @@ static u32 cypress_get_maximum_link_speed(struct
radeon_ps *radeon_state)
return 0;
}
-void cypress_notify_link_speed_change_after_state_change(struct radeon_device
*rdev)
+void cypress_notify_link_speed_change_after_state_change(struct radeon_device
*rdev,
+struct radeon_ps
*radeon_new_state,
+struct radeon_ps
*radeon_current_state)
{
- struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
- struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
u32 pcie_link_speed_target =
cypress_get_maximum_link_speed(radeon_new_state);
u32 pcie_link_speed_current =
cypress_get_maximum_link_speed(radeon_current_state);
u8 request;
@@ -373,10 +373,10 @@ void
cypress_notify_link_speed_change_after_state_change(struct radeon_device *r
}
}
-void cypress_notify_link_speed_change_before_state_change(struct radeon_device
*rdev)
+void cypress_notify_link_speed_change_before_state_change(struct radeon_device
*rdev,
+ struct radeon_ps
*radeon_new_state,
+ struct radeon_ps
*radeon_current_state)
{
- struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
- struct radeon_ps *radeon_current_state = rdev->pm.dpm.current_ps;
u32 pcie_link_speed_target =
cypress_get_maximum_link_speed(radeon_new_state);
u32 pcie_link_speed_current =
cypress_get_maximum_link_speed(radeon_current_state);
u8 request;
@@ -856,10 +856,10 @@ static void cypress_convert_mc_reg_table_to_smc(struct
radeon_device *rdev,
&mc_reg_table->data[4]);
}
-int cypress_upload_sw_state(struct radeon_device *rdev)
+int cypress_upload_sw_state(struct radeon_device *rdev,
+ struct radeon_ps *radeon_new_state)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
- struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
u16 address = pi->state_table_start +
[PATCH 097/165] drm/radeon/dpm/rv7xx: restructure code
From: Alex Deucher
Needed to properly handle dynamic state adjustment.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/btc_dpm.c |6 ++-
drivers/gpu/drm/radeon/cypress_dpm.c |6 ++-
drivers/gpu/drm/radeon/rv740_dpm.c |1 -
drivers/gpu/drm/radeon/rv770_dpm.c | 77 ++
drivers/gpu/drm/radeon/rv770_dpm.h |8 +++-
5 files changed, 55 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/radeon/btc_dpm.c b/drivers/gpu/drm/radeon/btc_dpm.c
index 79f5ed4..3ae4de6 100644
--- a/drivers/gpu/drm/radeon/btc_dpm.c
+++ b/drivers/gpu/drm/radeon/btc_dpm.c
@@ -2233,6 +2233,8 @@ void btc_dpm_reset_asic(struct radeon_device *rdev)
int btc_dpm_set_power_state(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
+ struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
btc_apply_state_adjust_rules(rdev);
@@ -2243,7 +2245,7 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_before_state_change(rdev);
- rv770_set_uvd_clock_before_set_eng_clock(rdev);
+ rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
rv770_halt_smc(rdev);
btc_set_at_for_uvd(rdev);
if (eg_pi->smu_uvd_hs)
@@ -2257,7 +2259,7 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
- rv770_set_uvd_clock_after_set_eng_clock(rdev);
+ rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_after_state_change(rdev);
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c
b/drivers/gpu/drm/radeon/cypress_dpm.c
index 22297b1..c9026ed 100644
--- a/drivers/gpu/drm/radeon/cypress_dpm.c
+++ b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -1930,13 +1930,15 @@ void cypress_dpm_disable(struct radeon_device *rdev)
int cypress_dpm_set_power_state(struct radeon_device *rdev)
{
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
+ struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
+ struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
rv770_restrict_performance_levels_before_switch(rdev);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_before_state_change(rdev);
- rv770_set_uvd_clock_before_set_eng_clock(rdev);
+ rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
rv770_halt_smc(rdev);
cypress_upload_sw_state(rdev);
@@ -1947,7 +1949,7 @@ int cypress_dpm_set_power_state(struct radeon_device
*rdev)
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
- rv770_set_uvd_clock_after_set_eng_clock(rdev);
+ rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_after_state_change(rdev);
diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c
b/drivers/gpu/drm/radeon/rv740_dpm.c
index d0d750e..7aa1608 100644
--- a/drivers/gpu/drm/radeon/rv740_dpm.c
+++ b/drivers/gpu/drm/radeon/rv740_dpm.c
@@ -29,7 +29,6 @@
#include "rv770_dpm.h"
#include "atom.h"
-struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
u32 rv740_get_decoded_reference_divider(u32 encoded_ref)
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c
b/drivers/gpu/drm/radeon/rv770_dpm.c
index f5efa4c..db1dfbc 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -1155,10 +1155,10 @@ static int rv770_populate_smc_mvdd_table(struct
radeon_device *rdev,
return 0;
}
-static int rv770_init_smc_table(struct radeon_device *rdev)
+static int rv770_init_smc_table(struct radeon_device *rdev,
+ struct radeon_ps *radeon_boot_state)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
- struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
RV770_SMC_STATETABLE *table = &pi->smc_statetable;
int ret;
@@ -1364,10 +1364,9 @@ static void rv770_enable_dynamic_pcie_gen2(struct
radeon_device *rdev,
WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
}
-static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev)
+static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev,
+ struct radeon_ps
*radeon_new_state)
{
- struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
-
if ((rdev->family == CHIP_RV730) ||
(rdev->family == CHIP_RV710) ||
(rdev->family == CHIP_RV740))
@@ -1376,10 +1375
