[PATCH] gpu: schedule gma500 stub driver for feature removal
In v3.3, the gma500 drm driver moved from staging to drm group by Alan Cox's 3abcf41fb patch. the gma500 drm driver should control brightness well and don't need gma500 stub driver anymore. So, my plan is remove gma500 stub driver at Dec. 2012. Signed-off-by: Lee, Chun-Yi --- Documentation/feature-removal-schedule.txt | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index a0ffac0..219d6f1 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -524,3 +524,14 @@ Files: arch/arm/mach-at91/at91cap9.c Why: The code is not actively maintained and platforms are now hard to find. Who: Nicolas Ferre Jean-Christophe PLAGNIOL-VILLARD + + + +What: Intel GMA500 Stub Driver +When: December 2012 +Why: In v3.3, the gma500 drm driver moved from staging to drm group by + Alan Cox's 3abcf41fb patch. the gma500 drm driver should control + brightness well and don't need gma500 stub driver anymore. + + So, my plan is remove gma500 stub driver at Dec. 2012. +Who: Lee, Chun-Yi -- 1.6.0.2 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH v2 00/14] updated exynos-drm-next.
On Fri, Mar 16, 2012 at 9:47 AM, Inki Dae wrote: > Hi, Dave and all. Hi Inki, I've taken most of these patches except for the G2D and Virtual drivers, If you can make the virtual driver rebase without G2D I don't see an issue with merging it, it didn't seem to apply cleanly here. But I don't think G2D is close enough for this merge window considering the security issues with exposing DMA engines without a lot of review. Dave. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 1/5] drm: add drm_property_change_is_valid
From: Paulo Zanoni
Move code from drm_mode_connector_property_set_ioctl to a new
function, so we can reuse this code when we add crtc properties.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c | 41 +
1 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6fdaf6f..1cadc11 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2910,6 +2910,26 @@ int drm_mode_connector_update_edid_property(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_mode_connector_update_edid_property);
+static int drm_property_change_is_valid(struct drm_property *property,
+ __u64 value)
+{
+ if (property->flags & DRM_MODE_PROP_IMMUTABLE)
+ return 0;
+ if (property->flags & DRM_MODE_PROP_RANGE) {
+ if (value < property->values[0])
+ return 0;
+ if (value > property->values[1])
+ return 0;
+ return 1;
+ } else {
+ int i;
+ for (i = 0; i < property->num_values; i++)
+ if (property->values[i] == value)
+ return 1;
+ return 0;
+ }
+}
+
int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
{
@@ -2946,28 +2966,9 @@ int drm_mode_connector_property_set_ioctl(struct
drm_device *dev,
}
property = obj_to_property(obj);
- if (property->flags & DRM_MODE_PROP_IMMUTABLE)
+ if (!drm_property_change_is_valid(property, out_resp->value))
goto out;
- if (property->flags & DRM_MODE_PROP_RANGE) {
- if (out_resp->value < property->values[0])
- goto out;
-
- if (out_resp->value > property->values[1])
- goto out;
- } else {
- int found = 0;
- for (i = 0; i < property->num_values; i++) {
- if (property->values[i] == out_resp->value) {
- found = 1;
- break;
- }
- }
- if (!found) {
- goto out;
- }
- }
-
/* Do DPMS ourselves */
if (property == connector->dev->mode_config.dpms_property) {
if (connector->funcs->dpms)
--
1.7.9.1
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[PATCH 2/5] drm: WARN() when drm_connector_attach_property fails
From: Paulo Zanoni
Also return void instead of int. We have more than 100 callers and
no one checks for the return value.
If this function fails the property won't be exposed by the get/set
ioctls, but we should probably survive. If this starts happening,
the solution will be to increase DRM_CONNECTOR_MAX_PROPERTY and
recompile the Kernel.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c |8 +++-
include/drm/drm_crtc.h |4 ++--
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 1cadc11..6260fc3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2659,7 +2659,7 @@ void drm_property_destroy(struct drm_device *dev, struct
drm_property *property)
}
EXPORT_SYMBOL(drm_property_destroy);
-int drm_connector_attach_property(struct drm_connector *connector,
+void drm_connector_attach_property(struct drm_connector *connector,
struct drm_property *property, uint64_t init_val)
{
int i;
@@ -2668,13 +2668,11 @@ int drm_connector_attach_property(struct drm_connector
*connector,
if (connector->property_ids[i] == 0) {
connector->property_ids[i] = property->base.id;
connector->property_values[i] = init_val;
- break;
+ return;
}
}
- if (i == DRM_CONNECTOR_MAX_PROPERTY)
- return -EINVAL;
- return 0;
+ WARN(1, "Failed to attach connector property\n");
}
EXPORT_SYMBOL(drm_connector_attach_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 2a0872c..21681fe 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -907,8 +907,8 @@ extern int drmfb_remove(struct drm_device *dev, struct
drm_framebuffer *fb);
extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX,
int maxY);
extern bool drm_crtc_in_use(struct drm_crtc *crtc);
-extern int drm_connector_attach_property(struct drm_connector *connector,
- struct drm_property *property, uint64_t
init_val);
+extern void drm_connector_attach_property(struct drm_connector *connector,
+ struct drm_property *property,
uint64_t init_val);
extern struct drm_property *drm_property_create(struct drm_device *dev, int
flags,
const char *name, int
num_values);
extern struct drm_property *drm_property_create_enum(struct drm_device *dev,
int flags,
--
1.7.9.1
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[PATCH 3/5] drm: add CRTC properties
From: Paulo Zanoni
Code based on the connector properties code.
Two new ioctls:
- DRM_IOCTL_MODE_CRTC_GETPROPERTIES
- DRM_IOCTL_MODE_CRTC_SETPROPERTY
The i915 driver needs this for the rotation and overscan compensation
properties. Other drivers might need this too.
v2: replace BUG_ON() for WARN(), fix bugs, add functions to get/set
the value
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c | 150
drivers/gpu/drm/drm_drv.c |4 +-
include/drm/drm.h |2 +
include/drm/drm_crtc.h | 28 -
include/drm/drm_mode.h | 13
5 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6260fc3..df00c29 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2712,6 +2712,55 @@ int drm_connector_property_get_value(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_property_get_value);
+void drm_crtc_attach_property(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t init_val)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == 0) {
+ crtc->property_ids[i] = property->base.id;
+ crtc->property_values[i] = init_val;
+ return;
+ }
+ }
+
+ WARN(1, "Failed to attach crtc property\n");
+}
+EXPORT_SYMBOL(drm_crtc_attach_property);
+
+int drm_crtc_property_set_value(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t value)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == property->base.id) {
+ crtc->property_values[i] = value;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(drm_crtc_property_set_value);
+
+int drm_crtc_property_get_value(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t *val)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == property->base.id) {
+ *val = crtc->property_values[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(drm_crtc_property_get_value);
+
int drm_mode_getproperty_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
{
@@ -2983,6 +3032,107 @@ out:
return ret;
}
+int drm_mode_crtc_get_properties_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_mode_crtc_get_properties *arg = data;
+ struct drm_mode_object *obj;
+ struct drm_crtc *crtc;
+ int ret = 0;
+ int i;
+ int copied = 0;
+ int props_count = 0;
+ uint32_t __user *props_ptr;
+ uint64_t __user *prop_values_ptr;
+
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
+ mutex_lock(&dev->mode_config.mutex);
+
+ obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
+ if (!obj) {
+ ret = -EINVAL;
+ goto out;
+ }
+ crtc = obj_to_crtc(obj);
+
+ for (props_count = 0; props_count < DRM_CRTC_MAX_PROPERTY &&
+crtc->property_ids[props_count] != 0; props_count++)
+ ;
+
+ /* This ioctl is called twice, once to determine how much space is
+* needed, and the 2nd time to fill it. */
+ if ((arg->count_props >= props_count) && props_count) {
+ copied = 0;
+ props_ptr = (uint32_t __user *)(unsigned long)(arg->props_ptr);
+ prop_values_ptr = (uint64_t __user *)(unsigned long)
+ (arg->prop_values_ptr);
+ for (i = 0; i < props_count; i++) {
+ if (put_user(crtc->property_ids[i],
+props_ptr + copied)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ if (put_user(crtc->property_values[i],
+prop_values_ptr + copied)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ copied++;
+ }
+ }
+ arg->count_props = props_count;
+out:
+ mutex_unlock(&dev->mode_config.mutex);
+ return ret;
+}
+
+int drm_mode_crtc_set_property_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_priv)
+{
+ struct drm_mode_crtc_set_property *arg = data;
+ struct drm_mode_object *obj;
+ struct drm_property *property
[PATCH 4/5] drm/i915: add 'rotation' CRTC property
From: Paulo Zanoni
This property is needed so we can inform the KVMr feature about our
current rotation: whenever we change the rotation, we should change
that property so that the KVMr knows that the screen is rotated.
How to reproduce the problem:
- on an AMT machine, enable KVM
- boot the machine, use xrandr to rotate the display
- use VNC to connect to the KVM
- try to use the mouse
v2: only create the property once
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |5 +++
drivers/gpu/drm/i915/intel_display.c | 66 ++
3 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7a00b7..7994c4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *rotation_property;
} drm_i915_private_t;
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..79e8b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2407,6 +2407,11 @@
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_ROTATION_MASK (3 << 14)
+#define PIPECONF_ROTATION_0 (0 << 14)
+#define PIPECONF_ROTATION_90 (1 << 14)
+#define PIPECONF_ROTATION_180(2 << 14)
+#define PIPECONF_ROTATION_270(3 << 14)
#define PIPECONF_BPP_MASK(0x00e0)
#define PIPECONF_BPP_8 (0<<5)
#define PIPECONF_BPP_10 (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 683002fb..4842de8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7625,6 +7625,50 @@ static void intel_crtc_reset(struct drm_crtc *crtc)
intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
}
+static void intel_crtc_set_rotation(struct drm_crtc *crtc,
+ uint64_t rotation)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = PIPECONF(intel_crtc->pipe);
+ u32 val = I915_READ(reg);
+
+ val &= ~PIPECONF_ROTATION_MASK;
+
+ switch (rotation) {
+ case 0:
+ val |= PIPECONF_ROTATION_0;
+ break;
+ case 90:
+ val |= PIPECONF_ROTATION_90;
+ break;
+ case 180:
+ val |= PIPECONF_ROTATION_180;
+ break;
+ case 270:
+ val |= PIPECONF_ROTATION_270;
+ break;
+ default:
+ DRM_ERROR("Unsupported rotation: %Lu\n", rotation);
+ val |= PIPECONF_ROTATION_0;
+ }
+
+ I915_WRITE(reg, val);
+}
+
+static int intel_crtc_set_property(struct drm_crtc *crtc,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (property == dev_priv->rotation_property)
+ intel_crtc_set_rotation(crtc, val);
+ return 0;
+}
+
static struct drm_crtc_helper_funcs intel_helper_funcs = {
.dpms = intel_crtc_dpms,
.mode_fixup = intel_crtc_mode_fixup,
@@ -7643,8 +7687,27 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.set_config = drm_crtc_helper_set_config,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
+ .set_property = intel_crtc_set_property,
};
+static void intel_attach_rotation_property(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_property *prop;
+
+ prop = dev_priv->rotation_property;
+ if (prop == NULL) {
+ prop = drm_property_create_range(dev, 0, "rotation", 0, 359);
+ if (prop == NULL)
+ return;
+
+ dev_priv->rotation_property = prop;
+ }
+
+ drm_crtc_attach_property(crtc, prop, 0);
+}
+
static void intel_crtc_init(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = dev->dev_private;
@@ -7664,6 +7727,9 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
intel_crtc->lut_b[i] = i;
}
+ if (INTEL_INFO(dev)->gen >= 5)
+ intel_attach_rotation_property(&intel_crtc->base);
+
/* Swap pipes & planes for FBC on p
[PATCH 5/5] drm/i915: add overscan compensation CRTC properties
From: Paulo Zanoni
They're named "underscan x" and "underscan y". The properties accept
values from 0 to 100, where 0 is "don't compensate" and 100 is "shrink
the screen as much as possible".
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h |2 +
drivers/gpu/drm/i915/intel_display.c | 110 +-
2 files changed, 111 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7994c4f..fb9062d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -781,6 +781,8 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
struct drm_property *rotation_property;
+ struct drm_property *x_underscan_property;
+ struct drm_property *y_underscan_property;
} drm_i915_private_t;
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 4842de8..b36572d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5620,6 +5620,77 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
return 12;
}
+/*
+ * The overscan compensation property (aka underscan property) has values from 0
+ * to 100, where 0 means that the compensation is disabled and 100 means the
+ * screen should shrink as much as possible. The current maximum supported
value
+ * (from the specifications) is "src/dst < 1.125".
+ *
+ * In short:
+ * - if val == 0 -> dst = src
+ * - if val == 100 -> dst = src * 8/9
+ * - dst can't be odd
+ * - dst can't be < src * 8 / (double)9
+ * - so the formulae, not considering rounding, should be:
+ * - dst = 9*src - prop*src/100 / 9
+ */
+static void ironlake_crtc_overscan_compensate(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ uint64_t prop_x = 0, prop_y = 0;
+ int tot_x, tot_y, src_x, src_y, dst_x, dst_y, pos_x, pos_y;
+ u32 reg;
+
+ drm_crtc_property_get_value(crtc, dev_priv->x_underscan_property,
+ &prop_x);
+ drm_crtc_property_get_value(crtc, dev_priv->y_underscan_property,
+ &prop_y);
+
+ if (prop_x == 0 && prop_y == 0 &&
+ !(dev_priv->pch_pf_size &&
+ (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP))) {
+ I915_WRITE(PF_CTL(pipe), 0);
+ I915_WRITE(PF_WIN_POS(pipe), 0);
+ I915_WRITE(PF_WIN_SZ(pipe), 0);
+ return;
+ }
+
+ reg = I915_READ(HTOTAL(pipe));
+ tot_x = (reg & 0xFFF) + 1;
+ reg = I915_READ(VTOTAL(pipe));
+ tot_y = (reg & 0xFFF) + 1;
+ reg = I915_READ(PIPESRC(pipe));
+ src_x = ((reg >> 16) & 0xFFF) + 1;
+ src_y = (reg & 0xFFF) + 1;
+
+ dst_x = (src_x * 9 - src_x * prop_x / 100 + 8) / 9;
+ dst_x &= ~1;
+ if (dst_x < ((src_x * 8 + 8) / 9))
+ dst_x += 2;
+
+ dst_y = (src_y * 9 - src_y * prop_y / 100 + 8) / 9;
+ dst_y &= ~1;
+ if (dst_y < ((src_y * 8 + 8) / 9))
+ dst_y += 2;
+
+ pos_x = (tot_x - dst_x) / 2;
+ pos_y = (tot_y - dst_y) / 2;
+
+ if (pos_x == 1)
+ pos_x = 0;
+ reg = I915_READ(PIPECONF(pipe));
+ if ((reg & PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
+ pos_y &= ~1;
+
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(PF_WIN_POS(pipe), (pos_x << 16) | pos_y);
+ I915_WRITE(PF_WIN_SZ(pipe), (dst_x << 16) | dst_y);
+}
+
+
static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@@ -6065,6 +6136,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
intel_update_watermarks(dev);
+ ironlake_crtc_overscan_compensate(crtc);
+
return ret;
}
@@ -7666,6 +7739,11 @@ static int intel_crtc_set_property(struct drm_crtc *crtc,
if (property == dev_priv->rotation_property)
intel_crtc_set_rotation(crtc, val);
+ if (property == dev_priv->x_underscan_property ||
+ property == dev_priv->y_underscan_property) {
+ drm_crtc_property_set_value(crtc, property, val);
+ ironlake_crtc_overscan_compensate(crtc);
+ }
return 0;
}
@@ -7708,6 +7786,34 @@ static void intel_attach_rotation_property(struct
drm_crtc *crtc)
drm_crtc_attach_property(crtc, prop, 0);
}
+static void intel_attach_underscan_properties(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = de
[PATCH 1/5 libdrm] modetest: fix some compiler warnings
From: Paulo Zanoni
Use unsigned int instead of int:
- modetest.c:89:1: warning: comparison between signed and unsigned integer
expressions [-Wsign-compare]
- modetest.c:97:1: warning: comparison between signed and unsigned integer
expressions [-Wsign-compare]
- modetest.c:117:1: warning: comparison between signed and unsigned integer
expressions [-Wsign-compare]
- modetest.c:772:16: warning: comparison between signed and unsigned integer
expressions [-Wsign-compare]
The 'fd' variable is global, we don't need to pass it as an argument:
- modetest.c:698:40: warning: unused parameter ‘fd’ [-Wunused-parameter]
We don't use the 'modeset' variable:
- modetest.c:725:8: warning: variable ‘modeset’ set but not used
[-Wunused-but-set-variable]
Signed-off-by: Paulo Zanoni
---
tests/modetest/modetest.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 229ab8a..c0f7ad7 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -70,7 +70,7 @@ struct type_name {
#define type_name_fn(res) \
char * res##_str(int type) { \
- int i; \
+ unsigned int i; \
for (i = 0; i < ARRAY_SIZE(res##_names); i++) { \
if (res##_names[i].type == type)\
return res##_names[i].name; \
@@ -695,7 +695,7 @@ void usage(char *name)
#define dump_resource(res) if (res) dump_##res()
-static int page_flipping_supported(int fd)
+static int page_flipping_supported(void)
{
/*FIXME: generic ioctl needed? */
return 1;
@@ -722,8 +722,8 @@ int main(int argc, char **argv)
int encoders = 0, connectors = 0, crtcs = 0, framebuffers = 0;
int test_vsync = 0;
char *modules[] = { "i915", "radeon", "nouveau", "vmwgfx" };
- char *modeset = NULL;
- int i, count = 0;
+ unsigned int i;
+ int count = 0;
struct connector con_args[2];
opterr = 0;
@@ -748,7 +748,6 @@ int main(int argc, char **argv)
test_vsync = 1;
break;
case 's':
- modeset = strdup(optarg);
con_args[count].crtc = -1;
if (sscanf(optarg, "%d:%64s",
&con_args[count].id,
@@ -780,7 +779,7 @@ int main(int argc, char **argv)
}
}
- if (test_vsync && !page_flipping_supported(fd)) {
+ if (test_vsync && !page_flipping_supported()) {
fprintf(stderr, "page flipping not supported by drm.\n");
return -1;
}
--
1.7.9.1
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[PATCH 2/5 libdrm] modetest: fix memory leak
From: Paulo Zanoni
Don't "continue" without freeing the connector.
192 bytes in 6 blocks are indirectly lost in loss record 6 of 12
at 0x4C2779D: malloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
by 0x4E30DD8: drmMalloc (xf86drm.c:147)
by 0x4E35024: drmAllocCpy (xf86drmMode.c:73)
by 0x4E35D69: drmModeGetConnector (xf86drmMode.c:507)
by 0x402F22: dump_connectors (modetest.c:181)
by 0x40261B: main (modetest.c:801)
Signed-off-by: Paulo Zanoni
---
tests/modetest/modetest.c | 21 ++---
1 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index c0f7ad7..2779d4f 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -198,17 +198,16 @@ void dump_connectors(void)
printf("%s%d", j > 0 ? ", " : "",
connector->encoders[j]);
printf("\n");
- if (!connector->count_modes)
- continue;
-
- printf(" modes:\n");
- printf(" name refresh (Hz) hdisp hss hse htot vdisp "
- "vss vse vtot)\n");
- for (j = 0; j < connector->count_modes; j++)
- dump_mode(&connector->modes[j]);
-
- printf(" props:\n");
- dump_props(connector);
+ if (connector->count_modes) {
+ printf(" modes:\n");
+ printf(" name refresh (Hz) hdisp hss hse htot vdisp "
+ "vss vse vtot)\n");
+ for (j = 0; j < connector->count_modes; j++)
+ dump_mode(&connector->modes[j]);
+
+ printf(" props:\n");
+ dump_props(connector);
+ }
drmModeFreeConnector(connector);
}
--
1.7.9.1
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[PATCH 3/5 libdrm] modetest: print more about our properties
From: Paulo Zanoni
In the future we'll have more than just connector properties, so create
a dump_prop function that can handle any property (instead of the
current dump_props function that only handles connector properties).
Also, make this function print a lot more information about the existing
properties.
Also change the printed indentation of the modes to make the output more
readable.
The previous function dump_props also segfaulted when we didn't have
enought permissions. The new function does not segfault in this case (by
checking for the return value of drmModeGetProperty).
Signed-off-by: Paulo Zanoni
---
tests/modetest/modetest.c | 92
1 files changed, 83 insertions(+), 9 deletions(-)
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 2779d4f..52c81a9 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -43,6 +43,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -144,7 +145,7 @@ void dump_encoders(void)
void dump_mode(drmModeModeInfo *mode)
{
- printf(" %s %d %d %d %d %d %d %d %d %d\n",
+ printf("\t%s %d %d %d %d %d %d %d %d %d\n",
mode->name,
mode->vrefresh,
mode->hdisplay,
@@ -158,16 +159,87 @@ void dump_mode(drmModeModeInfo *mode)
}
static void
-dump_props(drmModeConnector *connector)
+dump_blob(uint32_t blob_id)
+{
+ uint32_t i;
+ unsigned char *blob_data;
+ drmModePropertyBlobPtr blob;
+
+ blob = drmModeGetPropertyBlob(fd, blob_id);
+ blob_data = blob->data;
+
+ for (i = 0; i < blob->length; i++) {
+ if (i % 16 == 0)
+ printf("\n\t\t\t");
+ printf("%.2hhx", blob_data[i]);
+ }
+ printf("\n");
+
+ drmModeFreePropertyBlob(blob);
+}
+
+static void
+dump_prop(uint32_t prop_id, uint64_t value)
{
- drmModePropertyPtr props;
int i;
+ drmModePropertyPtr prop;
+
+ prop = drmModeGetProperty(fd, prop_id);
+
+ printf("\t%d", prop_id);
+ if (!prop) {
+ printf("\n");
+ return;
+ }
+
+ printf(" %s:\n", prop->name);
+
+ printf("\t\tflags:");
+ if (prop->flags & DRM_MODE_PROP_PENDING)
+ printf(" pending");
+ if (prop->flags & DRM_MODE_PROP_RANGE)
+ printf(" range");
+ if (prop->flags & DRM_MODE_PROP_IMMUTABLE)
+ printf(" immutable");
+ if (prop->flags & DRM_MODE_PROP_ENUM)
+ printf(" enum");
+ if (prop->flags & DRM_MODE_PROP_BLOB)
+ printf(" blob");
+ printf("\n");
- for (i = 0; i < connector->count_props; i++) {
- props = drmModeGetProperty(fd, connector->props[i]);
- printf("\t%s, flags %d\n", props->name, props->flags);
- drmModeFreeProperty(props);
+ if (prop->flags & DRM_MODE_PROP_RANGE) {
+ printf("\t\tvalues:");
+ for (i = 0; i < prop->count_values; i++)
+ printf(" %"PRIu64, prop->values[i]);
+ printf("\n");
+ }
+
+ if (prop->flags & DRM_MODE_PROP_ENUM) {
+ printf("\t\tenums:");
+ for (i = 0; i < prop->count_enums; i++)
+ printf(" %s=%llu", prop->enums[i].name,
+ prop->enums[i].value);
+ printf("\n");
+ } else {
+ assert(prop->count_enums == 0);
}
+
+ if (prop->flags & DRM_MODE_PROP_BLOB) {
+ printf("\t\tblobs:\n");
+ for (i = 0; i < prop->count_blobs; i++)
+ dump_blob(prop->blob_ids[i]);
+ printf("\n");
+ } else {
+ assert(prop->count_blobs == 0);
+ }
+
+ printf("\t\tvalue:");
+ if (prop->flags & DRM_MODE_PROP_BLOB)
+ dump_blob(value);
+ else
+ printf(" %"PRIu64"\n", value);
+
+ drmModeFreeProperty(prop);
}
void dump_connectors(void)
@@ -200,13 +272,15 @@ void dump_connectors(void)
if (connector->count_modes) {
printf(" modes:\n");
- printf(" name refresh (Hz) hdisp hss hse htot vdisp "
+ printf("\tname refresh (Hz) hdisp hss hse htot vdisp "
"vss vse vtot)\n");
for (j = 0; j < connector->count_modes; j++)
dump_mode(&connector->modes[j]);
printf(" props:\n");
- dump_props(connector);
+ for (j = 0; j < connector->count_props; j++)
+ dump_prop(connector->props[j],
+ connector->prop_values[j]);
}
drmModeFreeConnector(connector);
--
1.7.9.1
_
[PATCH 4/5 libdrm] Add support for CRTC properties
From: Paulo Zanoni
New library calls:
- drmModeCrtcGetProperties
- drmModeFreeCrtcProperties
- drmModeCrtcSetProperties
Signed-off-by: Paulo Zanoni
---
include/drm/drm.h |2 +
include/drm/drm_mode.h | 13
xf86drmMode.c | 79
xf86drmMode.h | 12 +++
4 files changed, 106 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 8adb9d5..45eef57 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -717,6 +717,8 @@ struct drm_get_cap {
#define DRM_IOCTL_MODE_GETPLANEDRM_IOWR(0xB6, struct
drm_mode_get_plane)
#define DRM_IOCTL_MODE_SETPLANEDRM_IOWR(0xB7, struct
drm_mode_set_plane)
#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
+#define DRM_IOCTL_MODE_CRTC_GETPROPERTIES DRM_IOWR(0xB9, struct
drm_mode_crtc_get_properties)
+#define DRM_IOCTL_MODE_CRTC_SETPROPERTYDRM_IOWR(0xBA, struct
drm_mode_crtc_set_property)
/**
* Device specific ioctls should only be in their respective headers
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index f36c61a..2bc6b83 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -250,6 +250,19 @@ struct drm_mode_connector_set_property {
__u32 connector_id;
};
+struct drm_mode_crtc_get_properties {
+ __u64 props_ptr;
+ __u64 prop_values_ptr;
+ __u32 count_props;
+ __u32 crtc_id;
+};
+
+struct drm_mode_crtc_set_property {
+ __u64 value;
+ __u32 prop_id;
+ __u32 crtc_id;
+};
+
struct drm_mode_get_blob {
__u32 blob_id;
__u32 length;
diff --git a/xf86drmMode.c b/xf86drmMode.c
index c809c44..67cbc02 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -974,3 +974,82 @@ void drmModeFreePlaneResources(drmModePlaneResPtr ptr)
drmFree(ptr->planes);
drmFree(ptr);
}
+
+drmModeCrtcPropertiesPtr drmModeCrtcGetProperties(int fd, uint32_t crtc_id)
+{
+ struct drm_mode_crtc_get_properties properties;
+ drmModeCrtcPropertiesPtr ret = NULL;
+ uint32_t count;
+
+retry:
+ memset(&properties, 0, sizeof(struct drm_mode_crtc_get_properties));
+ properties.crtc_id = crtc_id;
+
+ if (drmIoctl(fd, DRM_IOCTL_MODE_CRTC_GETPROPERTIES, &properties))
+ return 0;
+
+ count = properties.count_props;
+
+ if (count) {
+ properties.props_ptr = VOID2U64(drmMalloc(count *
+ sizeof(uint32_t)));
+ if (!properties.props_ptr)
+ goto err_allocs;
+ properties.prop_values_ptr = VOID2U64(drmMalloc(count *
+ sizeof(uint64_t)));
+ if (!properties.prop_values_ptr)
+ goto err_allocs;
+ }
+
+ if (drmIoctl(fd, DRM_IOCTL_MODE_CRTC_GETPROPERTIES, &properties))
+ goto err_allocs;
+
+ if (count < properties.count_props) {
+ drmFree(U642VOID(properties.props_ptr));
+ drmFree(U642VOID(properties.prop_values_ptr));
+ goto retry;
+ }
+ count = properties.count_props;
+
+ ret = drmMalloc(sizeof(*ret));
+ if (!ret)
+ goto err_allocs;
+
+ ret->count_props = count;
+ ret->props = drmAllocCpy(U642VOID(properties.props_ptr),
+count, sizeof(uint32_t));
+ ret->prop_values = drmAllocCpy(U642VOID(properties.prop_values_ptr),
+ count, sizeof(uint64_t));
+ if (ret->count_props && (!ret->props || !ret->prop_values)) {
+ drmFree(ret->props);
+ drmFree(ret->prop_values);
+ drmFree(ret);
+ ret = NULL;
+ }
+
+err_allocs:
+ drmFree(U642VOID(properties.props_ptr));
+ drmFree(U642VOID(properties.prop_values_ptr));
+ return ret;
+}
+
+void drmModeFreeCrtcProperties(drmModeCrtcPropertiesPtr ptr)
+{
+ if (!ptr)
+ return;
+ drmFree(ptr->props);
+ drmFree(ptr->prop_values);
+ drmFree(ptr);
+}
+
+int drmModeCrtcSetProperty(int fd, uint32_t crtc_id, uint32_t property_id,
+ uint64_t value)
+{
+ struct drm_mode_crtc_set_property prop;
+
+ prop.value = value;
+ prop.prop_id = property_id;
+ prop.crtc_id = crtc_id;
+
+ return DRM_IOCTL(fd, DRM_IOCTL_MODE_CRTC_SETPROPERTY, &prop);
+}
diff --git a/xf86drmMode.h b/xf86drmMode.h
index 991e3f9..f2733ec 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -281,6 +281,12 @@ typedef struct _drmModeConnector {
uint32_t *encoders; /**< List of encoder ids */
} drmModeConnector, *drmModeConnectorPtr;
+typedef struct _drmModeCrtcProperties {
+ uint32_t count_props;
+ uint32_t *props;
+ uint64_t *prop_values;
+} drmModeCrtcProperties, *drmModeCrtcPropertiesPtr;
+
type
[PATCH 5/5 libdrm] modetest: print CRTC properties
From: Paulo Zanoni
Signed-off-by: Paulo Zanoni
---
tests/modetest/modetest.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 52c81a9..58bb39e 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -291,7 +291,9 @@ void dump_connectors(void)
void dump_crtcs(void)
{
drmModeCrtc *crtc;
+ drmModeCrtcPropertiesPtr props;
int i;
+ uint32_t j;
printf("CRTCs:\n");
printf("id\tfb\tpos\tsize\n");
@@ -310,6 +312,17 @@ void dump_crtcs(void)
crtc->width, crtc->height);
dump_mode(&crtc->mode);
+ printf(" props:\n");
+ props = drmModeCrtcGetProperties(fd, crtc->crtc_id);
+ if (props) {
+ for (j = 0; j < props->count_props; j++)
+ dump_prop(props->props[j],
+ props->prop_values[j]);
+ drmModeFreeCrtcProperties(props);
+ } else {
+ printf("\tcould not get crtc properties\n");
+ }
+
drmModeFreeCrtc(crtc);
}
printf("\n");
--
1.7.9.1
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[PATCH 1/3 xf86-video-intel] Avoid duplicated code with intel_output_create_ranged_atom
From: Paulo Zanoni
Same change for intel_display.c and sna_display.c.
Signed-off-by: Paulo Zanoni
---
src/intel_display.c | 104 +
src/sna/sna_display.c | 104 +
2 files changed, 90 insertions(+), 118 deletions(-)
diff --git a/src/intel_display.c b/src/intel_display.c
index 11d0e2b..abdc372 100644
--- a/src/intel_display.c
+++ b/src/intel_display.c
@@ -992,6 +992,33 @@ intel_property_ignore(drmModePropertyPtr prop)
return FALSE;
}
+static void
+intel_output_create_ranged_atom(xf86OutputPtr output, Atom *atom,
+ const char *name, INT32 min, INT32 max,
+ uint64_t value, Bool immutable)
+{
+ int err;
+ INT32 atom_range[2];
+
+ atom_range[0] = min;
+ atom_range[1] = max;
+
+ *atom = MakeAtom(name, strlen(name), TRUE);
+
+ err = RRConfigureOutputProperty(output->randr_output, *atom, FALSE,
+ TRUE, immutable, 2, atom_range);
+ if (err != 0)
+ xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
+ "RRConfigureOutputProperty error, %d\n", err);
+
+ err = RRChangeOutputProperty(output->randr_output, *atom, XA_INTEGER,
+32, PropModeReplace, 1, &value, FALSE,
+TRUE);
+ if (err != 0)
+ xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
+ "RRChangeOutputProperty error, %d\n", err);
+}
+
#define BACKLIGHT_NAME "Backlight"
#define BACKLIGHT_DEPRECATED_NAME "BACKLIGHT"
static Atom backlight_atom, backlight_deprecated_atom;
@@ -1031,30 +1058,18 @@ intel_output_create_resources(xf86OutputPtr output)
drmModePropertyPtr drmmode_prop = p->mode_prop;
if (drmmode_prop->flags & DRM_MODE_PROP_RANGE) {
- INT32 range[2];
-
p->num_atoms = 1;
p->atoms = calloc(p->num_atoms, sizeof(Atom));
if (!p->atoms)
continue;
- p->atoms[0] = MakeAtom(drmmode_prop->name,
strlen(drmmode_prop->name), TRUE);
- range[0] = drmmode_prop->values[0];
- range[1] = drmmode_prop->values[1];
- err = RRConfigureOutputProperty(output->randr_output,
p->atoms[0],
- FALSE, TRUE,
- drmmode_prop->flags &
DRM_MODE_PROP_IMMUTABLE ? TRUE : FALSE,
- 2, range);
- if (err != 0) {
- xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
- "RRConfigureOutputProperty error,
%d\n", err);
- }
- err = RRChangeOutputProperty(output->randr_output,
p->atoms[0],
-XA_INTEGER, 32,
PropModeReplace, 1, &p->value, FALSE, TRUE);
- if (err != 0) {
- xf86DrvMsg(output->scrn->scrnIndex, X_ERROR,
- "RRChangeOutputProperty error,
%d\n", err);
- }
+ intel_output_create_ranged_atom(output, &p->atoms[0],
+ drmmode_prop->name,
+ drmmode_prop->values[0],
+ drmmode_prop->values[1],
+ p->value,
+ drmmode_prop->flags &
DRM_MODE_PROP_IMMUTABLE ? TRUE : FALSE);
+
} else if (drmmode_prop->flags & DRM_MODE_PROP_ENUM) {
p->num_atoms = drmmode_prop->count_enums + 1;
p->atoms = calloc(p->num_atoms, sizeof(Atom));
@@ -1090,50 +1105,21 @@ intel_output_create_resources(xf86OutputPtr output)
}
if (intel_output->backlight_iface) {
- INT32 data, backlight_range[2];
-
/* Set up the backlight property, which takes effect
* immediately and accepts values only within the
* backlight_range.
*/
- backlight_atom = MakeAtom(BACKLIGHT_NAME,
sizeof(BACKLIGHT_NAME) - 1, TRUE);
- backlight_deprecated_atom = MakeAtom(BACKLIGHT_DEPRECATED_NAME,
-
sizeof(BACKLIGHT_DEPRECATED_NAME) - 1, TRUE);
-
- backlight_range[0] = 0;
- backlight_range[1] = intel_output->backlight_max;
- err = RRConfigureOutputProperty(output->randr_output,
-
[PATCH 2/3 xf86-video-intel] Update the rotation property whenever we change the rotation.
From: Paulo Zanoni
Don't worry if that fails: only the KVMr feature will be affected.
We still need to change the sna/ code.
Signed-off-by: Paulo Zanoni
---
src/intel.h |3 ++
src/intel_display.c | 79 +++
src/intel_driver.c |2 +
3 files changed, 84 insertions(+), 0 deletions(-)
diff --git a/src/intel.h b/src/intel.h
index f806aea..29df531 100644
--- a/src/intel.h
+++ b/src/intel.h
@@ -644,4 +644,7 @@ static inline Bool intel_pixmap_is_offscreen(PixmapPtr
pixmap)
return priv && priv->offscreen;
}
+/* intel_display.c */
+void intel_crtc_leave_vt(ScrnInfoPtr scrn);
+
#endif /* _I830_H_ */
diff --git a/src/intel_display.c b/src/intel_display.c
index abdc372..dad0fe1 100644
--- a/src/intel_display.c
+++ b/src/intel_display.c
@@ -82,6 +82,7 @@ struct intel_crtc {
uint32_t rotate_fb_id;
xf86CrtcPtr crtc;
struct list link;
+ drmModePropertyPtr rotation_prop;
};
struct intel_property {
@@ -418,6 +419,44 @@ done:
return ret;
}
+static void
+intel_crtc_inform_rotation(xf86CrtcPtr crtc, Rotation rotation)
+{
+ struct intel_crtc *intel_crtc = crtc->driver_private;
+ int ret, int_rotation;
+
+ /* Try to inform the Kernel about our current rotation but don't
+* worry if that fails */
+ if (intel_crtc->rotation_prop->prop_id) {
+
+ switch (rotation) {
+ case RR_Rotate_0:
+ int_rotation = 0;
+ break;
+ case RR_Rotate_90:
+ int_rotation = 90;
+ break;
+ case RR_Rotate_180:
+ int_rotation = 180;
+ break;
+ case RR_Rotate_270:
+ int_rotation = 270;
+ break;
+ default:
+ int_rotation = 0;
+ }
+
+ ret = drmModeCrtcSetProperty(intel_crtc->mode->fd,
+crtc_id(intel_crtc),
+intel_crtc->rotation_prop->prop_id,
+int_rotation);
+ if (ret)
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_WARNING,
+ "Failed to set CRTC rotation: %s\n",
+ strerror(-ret));
+ }
+}
+
static Bool
intel_crtc_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
Rotation rotation, int x, int y)
@@ -464,6 +503,8 @@ intel_crtc_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr
mode,
crtc->y = saved_y;
crtc->rotation = saved_rotation;
crtc->mode = saved_mode;
+ } else {
+ intel_crtc_inform_rotation(crtc, rotation);
}
return ret;
}
@@ -640,12 +681,48 @@ intel_crtc_destroy(xf86CrtcPtr crtc)
intel_crtc->cursor = NULL;
}
+ if (intel_crtc->rotation_prop)
+ drmModeFreeProperty(intel_crtc->rotation_prop);
+
list_del(&intel_crtc->link);
free(intel_crtc);
crtc->driver_private = NULL;
}
+static void
+intel_crtc_load_properties(struct intel_mode *mode,
+ struct intel_crtc *crtc)
+{
+ unsigned int i;
+ drmModeCrtcPropertiesPtr props;
+ drmModePropertyPtr prop;
+
+ crtc->rotation_prop = NULL;
+
+ props = drmModeCrtcGetProperties(mode->fd, crtc_id(crtc));
+ if (props) {
+ for (i = 0; i < props->count_props; i++) {
+ prop = drmModeGetProperty(mode->fd, props->props[i]);
+ if (!strcmp(prop->name, "rotation"))
+ crtc->rotation_prop = prop;
+ else
+ drmModeFreeProperty(prop);
+ }
+ drmModeFreeCrtcProperties(props);
+ }
+}
+
+void
+intel_crtc_leave_vt(ScrnInfoPtr scrn)
+{
+ int i;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
+
+ for (i = 0; i < xf86_config->num_crtc; i++)
+ intel_crtc_inform_rotation(xf86_config->crtc[i], RR_Rotate_0);
+}
+
static const xf86CrtcFuncsRec intel_crtc_funcs = {
.dpms = intel_crtc_dpms,
.set_mode_major = intel_crtc_set_mode_major,
@@ -692,6 +769,8 @@ intel_crtc_init(ScrnInfoPtr scrn, struct intel_mode *mode,
int num)
intel_crtc->crtc = crtc;
list_add(&intel_crtc->link, &mode->crtcs);
+
+ intel_crtc_load_properties(mode, intel_crtc);
}
static Bool
diff --git a/src/intel_driver.c b/src/intel_driver.c
index 4265de8..98466a3 100644
--- a/src/intel_driver.c
+++ b/src/intel_driver.c
@@ -1115,6 +1115,8 @@ static void I830LeaveVT(int scrnIndex, int flags)
intel_screen_private *intel = intel_get_screen_private(scrn);
int ret;
+ intel_crtc_le
[PATCH 3/3 xf86-video-intel] Add underscan properties
From: Paulo Zanoni
In the Kernel side, these are crtc properties (since in the hardware,
underscan use the panel fitters, which are attached to the pipes).
Ideally we should make these as crtc properties too, but since xrandr
doesn't have support for them, we expose the atoms as output
properties. This is not the best solution, but making the kernel
underscan properties be output properties instead of crtc properties
would be even more wrong.
We still need to change the sna/ code.
Signed-off-by: Paulo Zanoni
---
src/intel_display.c | 98 ++-
1 files changed, 97 insertions(+), 1 deletions(-)
diff --git a/src/intel_display.c b/src/intel_display.c
index dad0fe1..f0cddce 100644
--- a/src/intel_display.c
+++ b/src/intel_display.c
@@ -83,6 +83,8 @@ struct intel_crtc {
xf86CrtcPtr crtc;
struct list link;
drmModePropertyPtr rotation_prop;
+ drmModePropertyPtr underscan_x_prop;
+ drmModePropertyPtr underscan_y_prop;
};
struct intel_property {
@@ -111,6 +113,8 @@ struct intel_output {
int backlight_max;
xf86OutputPtr output;
struct list link;
+ Atom underscan_x_atom;
+ Atom underscan_y_atom;
};
static void
@@ -683,6 +687,10 @@ intel_crtc_destroy(xf86CrtcPtr crtc)
if (intel_crtc->rotation_prop)
drmModeFreeProperty(intel_crtc->rotation_prop);
+ if (intel_crtc->underscan_x_prop)
+ drmModeFreeProperty(intel_crtc->underscan_x_prop);
+ if (intel_crtc->underscan_y_prop)
+ drmModeFreeProperty(intel_crtc->underscan_y_prop);
list_del(&intel_crtc->link);
free(intel_crtc);
@@ -699,6 +707,8 @@ intel_crtc_load_properties(struct intel_mode *mode,
drmModePropertyPtr prop;
crtc->rotation_prop = NULL;
+ crtc->underscan_x_prop = NULL;
+ crtc->underscan_y_prop = NULL;
props = drmModeCrtcGetProperties(mode->fd, crtc_id(crtc));
if (props) {
@@ -706,6 +716,10 @@ intel_crtc_load_properties(struct intel_mode *mode,
prop = drmModeGetProperty(mode->fd, props->props[i]);
if (!strcmp(prop->name, "rotation"))
crtc->rotation_prop = prop;
+ else if (!strcmp(prop->name, "underscan x"))
+ crtc->underscan_x_prop = prop;
+ else if (!strcmp(prop->name, "underscan y"))
+ crtc->underscan_y_prop = prop;
else
drmModeFreeProperty(prop);
}
@@ -1200,6 +1214,19 @@ intel_output_create_resources(xf86OutputPtr output)
intel_output->backlight_active_level,
FALSE);
}
+ intel_output_create_ranged_atom(output, &intel_output->underscan_x_atom,
+ "underscan x", 0, 100, 0, FALSE);
+ intel_output_create_ranged_atom(output, &intel_output->underscan_y_atom,
+ "underscan y", 0, 100, 0, FALSE);
+}
+
+static struct intel_crtc *
+intel_output_get_crtc(xf86OutputPtr output)
+{
+ if (output->crtc)
+ return output->crtc->driver_private;
+ else
+ return 0;
}
static Bool
@@ -1229,6 +1256,36 @@ intel_output_set_property(xf86OutputPtr output, Atom
property,
return TRUE;
}
+ if (property == intel_output->underscan_x_atom ||
+ property == intel_output->underscan_y_atom) {
+ uint32_t val;
+ struct intel_crtc *intel_crtc;
+ drmModePropertyPtr drm_prop;
+
+ val = *(uint32_t *)value->data;
+ if (value->type != XA_INTEGER || value->format != 32 ||
+ value->size != 1 || val > 100)
+ return FALSE;
+
+ intel_crtc = intel_output_get_crtc(output);
+ if (intel_crtc) {
+ if (property == intel_output->underscan_x_atom)
+ drm_prop = intel_crtc->underscan_x_prop;
+ else
+ drm_prop = intel_crtc->underscan_y_prop;
+
+ if (!drm_prop)
+ return FALSE;
+
+ drmModeCrtcSetProperty(mode->fd,
+ intel_crtc->mode_crtc->crtc_id,
+ drm_prop->prop_id,
+ (uint64_t) val);
+
+ }
+ return TRUE;
+ }
+
for (i = 0; i < intel_output->num_props; i++) {
struct intel_property *p = &intel_output->props[i];
@@ -1279,10 +1336,11 @@ static Bool
intel_output_get_property(xf86OutputPtr output, Atom property)
{
struct intel_output *intel_output = ou
Re: [PATCH 3/5] drm: add CRTC properties
On Tue, Mar 20, 2012 at 9:48 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Code based on the connector properties code.
>
> Two new ioctls:
> - DRM_IOCTL_MODE_CRTC_GETPROPERTIES
> - DRM_IOCTL_MODE_CRTC_SETPROPERTY
Just fyi, this is useful to me too.. I need a way to set rotation on a
crtc or a drm plane. So possibly we also need PLANE_{SET,GET}PROPERTY
ioctls? Or maybe the ioctl could just apply to either a plane or crtc
depending on the id passed? (Not sure if that is too weird sounding?)
BR,
-R
> The i915 driver needs this for the rotation and overscan compensation
> properties. Other drivers might need this too.
>
> v2: replace BUG_ON() for WARN(), fix bugs, add functions to get/set
> the value
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/drm_crtc.c | 150
>
> drivers/gpu/drm/drm_drv.c | 4 +-
> include/drm/drm.h | 2 +
> include/drm/drm_crtc.h | 28 -
> include/drm/drm_mode.h | 13
> 5 files changed, 195 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 6260fc3..df00c29 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -2712,6 +2712,55 @@ int drm_connector_property_get_value(struct
> drm_connector *connector,
> }
> EXPORT_SYMBOL(drm_connector_property_get_value);
>
> +void drm_crtc_attach_property(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t
> init_val)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == 0) {
> + crtc->property_ids[i] = property->base.id;
> + crtc->property_values[i] = init_val;
> + return;
> + }
> + }
> +
> + WARN(1, "Failed to attach crtc property\n");
> +}
> +EXPORT_SYMBOL(drm_crtc_attach_property);
> +
> +int drm_crtc_property_set_value(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t value)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == property->base.id) {
> + crtc->property_values[i] = value;
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL(drm_crtc_property_set_value);
> +
> +int drm_crtc_property_get_value(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t *val)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == property->base.id) {
> + *val = crtc->property_values[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL(drm_crtc_property_get_value);
> +
> int drm_mode_getproperty_ioctl(struct drm_device *dev,
> void *data, struct drm_file *file_priv)
> {
> @@ -2983,6 +3032,107 @@ out:
> return ret;
> }
>
> +int drm_mode_crtc_get_properties_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file_priv)
> +{
> + struct drm_mode_crtc_get_properties *arg = data;
> + struct drm_mode_object *obj;
> + struct drm_crtc *crtc;
> + int ret = 0;
> + int i;
> + int copied = 0;
> + int props_count = 0;
> + uint32_t __user *props_ptr;
> + uint64_t __user *prop_values_ptr;
> +
> + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> + return -EINVAL;
> +
> + mutex_lock(&dev->mode_config.mutex);
> +
> + obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
> + if (!obj) {
> + ret = -EINVAL;
> + goto out;
> + }
> + crtc = obj_to_crtc(obj);
> +
> + for (props_count = 0; props_count < DRM_CRTC_MAX_PROPERTY &&
> + crtc->property_ids[props_count] != 0; props_count++)
> + ;
> +
> + /* This ioctl is called twice, once to determine how much space is
> + * needed, and the 2nd time to fill it. */
> + if ((arg->count_props >= props_count) && props_count) {
> + copied = 0;
> + props_ptr = (uint32_t __user *)(unsigned
> long)(arg->props_ptr);
> + prop_values_ptr = (uint64_t __user *)(unsigned long)
> + (arg->prop_values_ptr);
> + for (i = 0; i < props_count; i++) {
> + if (put_user(crtc->property_ids[i],
> + props_ptr + copied)) {
> + ret = -EFAULT;
> + goto out;
> + }
> + if (put_user(crtc->property_values[i],
> +
Re: [PATCH 5/5] drm/i915: add overscan compensation CRTC properties
On Tue, Mar 20, 2012 at 10:48 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> They're named "underscan x" and "underscan y". The properties accept
> values from 0 to 100, where 0 is "don't compensate" and 100 is "shrink
> the screen as much as possible".
FWIW, the radeon driver already exposes something similar. It might
be worthwhile to try and use consistent naming and property options.
We have an "underscan" property:
static struct drm_prop_enum_list radeon_underscan_enum_list[] =
{ { UNDERSCAN_OFF, "off" },
{ UNDERSCAN_ON, "on" },
{ UNDERSCAN_AUTO, "auto" },
};
"off" disables underscan
"on" forces it on
"auto" tries to enable/disable underscan automatically based on EDID
information. RIght now we just check if the monitor is HDMI and the
mode is an standard HD mode, but IIRC, there is also a CEA extension
block that is supposed to tell you whether the monitor is overscanning
or not.
Then we have "underscan hborder" and "underscan vborder" to adjust the
amount of underscan. See radeon_display.c in the kernel.
Alex
>
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_display.c | 110
> +-
> 2 files changed, 111 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7994c4f..fb9062d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -781,6 +781,8 @@ typedef struct drm_i915_private {
> struct drm_property *broadcast_rgb_property;
> struct drm_property *force_audio_property;
> struct drm_property *rotation_property;
> + struct drm_property *x_underscan_property;
> + struct drm_property *y_underscan_property;
> } drm_i915_private_t;
>
> enum hdmi_force_audio {
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 4842de8..b36572d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5620,6 +5620,77 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
> return 12;
> }
>
> +/*
> + * The overscan compensation property (aka underscan property) has values
> from 0
> + * to 100, where 0 means that the compensation is disabled and 100 means the
> + * screen should shrink as much as possible. The current maximum supported
> value
> + * (from the specifications) is "src/dst < 1.125".
> + *
> + * In short:
> + * - if val == 0 -> dst = src
> + * - if val == 100 -> dst = src * 8/9
> + * - dst can't be odd
> + * - dst can't be < src * 8 / (double)9
> + * - so the formulae, not considering rounding, should be:
> + * - dst = 9*src - prop*src/100 / 9
> + */
> +static void ironlake_crtc_overscan_compensate(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + int pipe = intel_crtc->pipe;
> + uint64_t prop_x = 0, prop_y = 0;
> + int tot_x, tot_y, src_x, src_y, dst_x, dst_y, pos_x, pos_y;
> + u32 reg;
> +
> + drm_crtc_property_get_value(crtc, dev_priv->x_underscan_property,
> + &prop_x);
> + drm_crtc_property_get_value(crtc, dev_priv->y_underscan_property,
> + &prop_y);
> +
> + if (prop_x == 0 && prop_y == 0 &&
> + !(dev_priv->pch_pf_size &&
> + (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP))) {
> + I915_WRITE(PF_CTL(pipe), 0);
> + I915_WRITE(PF_WIN_POS(pipe), 0);
> + I915_WRITE(PF_WIN_SZ(pipe), 0);
> + return;
> + }
> +
> + reg = I915_READ(HTOTAL(pipe));
> + tot_x = (reg & 0xFFF) + 1;
> + reg = I915_READ(VTOTAL(pipe));
> + tot_y = (reg & 0xFFF) + 1;
> + reg = I915_READ(PIPESRC(pipe));
> + src_x = ((reg >> 16) & 0xFFF) + 1;
> + src_y = (reg & 0xFFF) + 1;
> +
> + dst_x = (src_x * 9 - src_x * prop_x / 100 + 8) / 9;
> + dst_x &= ~1;
> + if (dst_x < ((src_x * 8 + 8) / 9))
> + dst_x += 2;
> +
> + dst_y = (src_y * 9 - src_y * prop_y / 100 + 8) / 9;
> + dst_y &= ~1;
> + if (dst_y < ((src_y * 8 + 8) / 9))
> + dst_y += 2;
> +
> + pos_x = (tot_x - dst_x) / 2;
> + pos_y = (tot_y - dst_y) / 2;
> +
> + if (pos_x == 1)
> + pos_x = 0;
> + reg = I915_READ(PIPECONF(pipe));
> + if ((reg & PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
> + pos_y &= ~1;
> +
> + I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
> + I915_WRITE(PF_WIN_POS(pipe), (pos_x << 16) | pos_y);
> + I915_WRITE(PF_WIN_SZ(pipe), (dst_x << 16) | dst_y);
> +}
> +
> +
> static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>
CRTC properties patches
Hi Some time ago I posted a patch series to implement Kernel CRTC properties and a "rotation" property for the i915 driver. No one objected those patches, so now I'm resending the rebased versions, with some minor changes and also "overscan compensation" properties. The patches apply to the ~danvet/drm-intel tree, drm-intel-next-queued branch. Summary (i.e., tl;dr) - - CRTC properties seem to be the most correct way to solve some problems - "Rotation" property solves problems with Intel AMT KVM - "Overscan Compensation" properties solve problems with TVs/monitors that do overscan - patches for kernel, libdrm, and xf86-video-intel Definition of the problem - Some of the "features" of the Intel hardware have to be configured per pipe. In the DRM world, the pipe is abstracted as a CRTC, so the thing that makes most sense is to implement these features as CRTC properties. Why not connector properties? In theory, we can have more than one connector per each pipe, so we would have to keep synchronizing the properties with all the connectors associated with a pipe, and also update everything each time a connector changes pipe. If we can have the "correct" (IMHO) CRTC properties implementation, why make hackish connector properties? So far, there are two features that the i915 driver can/should implement as CRTC properties: "rotation" and "overscan compensation". Rotation (Disclaimer: this description is purely based on my own experiences with the feature and it represents only my own opinion, not Intel's opinion. The description might even be wrong.) Intel AMT has a feature called KVM (Keyboard, Video, Mouse). AFAIK, this is available for all machines labeled as "vPro" (like my Lenovo laptops). Once you enable this feature on your machine, you can remotely connect to the machine using standard VNC protocol (additionally, there are also non-standard features for a closed-source VNC client, but I've never used them). This is a very cool thing since you don't need to install any software on the KVM machine, and you can even reboot the machine and browse the BIOS using the VNC. The KVM implementation reads the "screen" directly from the video graphics registers (it's OS independent, remember?). The problem is: whenever the screen is rotated by X, the KVM implementation needs to know this, otherwise the mouse pointer will be moved to the wrong direction. How do we tell the KVM that the screen is rotated? We need to set some bits on the PIPECONF registers. So my implementation creates a CRTC property called "rotation" and then whenever X rotates the screen, xf86-video-intel updates the property, and everyone gets happy. The property is not exposed to the "users". This problem is very easy to reproduce: - acquire a vPro machine (bro tip: use magnets for faster acquiring) - configure AMT KVM (there's a "ctrl+p" menu somewhere when you boot) - boot the machine, use xrandr to rotate the screen - connect to the KVM through VNC (any client will do) - have fun trying to use the mouse Overscan Compensation (a.k.a. "Underscan") -- Recently we have enabled Interlaced modes in our driver. One of the problems remaining is that some TVs and monitors will enable overscan when you use Interlaced modes (actually, some enable overscan even on progressive modes, like my own TV). One possible solution to this problem would be to send an AVI infoframe that asks the TV to not overscan (this patch is on my TODO list), but most TVs/monitors don't repect the infoframes, so another solution is to use the panel fitters to compensate for overscan, and since this is independent from the TV/monitor, it should work with every device (even LVDS). I already have submitted to intel-gpu-tools a tool called "intel_panel_fitter" that does overscan compensation using the panel fitter (so people that don't have future kernels can already have overscan compensation). The tool works but requires you to be root, so now I am proposing two new CRTC properties: "underscan x" and "underscan y". When I implemented CRTC properties I followed the examples and made the ioctls require you to be DRM master, so we can't just rely on having our users calling the libdrm functions: we need to make X (or xf86-video-intel) expose the properties to the user. How do we expose those properties? I imagined 3 solutions: 1 - Change the xrandr protocol to include crtc properties. This would require a lot of releases, the code would take many months to arrive the distros. 2 - Implement a xorg.conf option to enable/disable underscan. At first this seems simple, but when you start thinking that the user wants underscan for just some modes on a specific output, and that sometimes compensation must be on and sometimes it must be off, it gets complicated: how do we specify this in xorg.conf? 3 - Do the hack I wanted to avoid inside the Kernel: expose th
Re: [PATCH 3/5] drm: add CRTC properties
On Tue, Mar 20, 2012 at 10:48 AM, Paulo Zanoni wrote:
> From: Paulo Zanoni
>
> Code based on the connector properties code.
>
> Two new ioctls:
> - DRM_IOCTL_MODE_CRTC_GETPROPERTIES
> - DRM_IOCTL_MODE_CRTC_SETPROPERTY
>
> The i915 driver needs this for the rotation and overscan compensation
> properties. Other drivers might need this too.
>
> v2: replace BUG_ON() for WARN(), fix bugs, add functions to get/set
> the value
>
Is there any reason why these can't just be exposed as connector
properties? While the hw features you are exposing are technically
part of the crtc block, so are most of the existing connector
properties (scalers, etc.). Plus, while the scalers/transforms are
part of the crtc hw, they only really make sense on certain
connectors. E.g., underscan isn't particularly useful on non-TMDS
capable connectors.
Alex
> Signed-off-by: Paulo Zanoni
> ---
> drivers/gpu/drm/drm_crtc.c | 150
>
> drivers/gpu/drm/drm_drv.c | 4 +-
> include/drm/drm.h | 2 +
> include/drm/drm_crtc.h | 28 -
> include/drm/drm_mode.h | 13
> 5 files changed, 195 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> index 6260fc3..df00c29 100644
> --- a/drivers/gpu/drm/drm_crtc.c
> +++ b/drivers/gpu/drm/drm_crtc.c
> @@ -2712,6 +2712,55 @@ int drm_connector_property_get_value(struct
> drm_connector *connector,
> }
> EXPORT_SYMBOL(drm_connector_property_get_value);
>
> +void drm_crtc_attach_property(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t
> init_val)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == 0) {
> + crtc->property_ids[i] = property->base.id;
> + crtc->property_values[i] = init_val;
> + return;
> + }
> + }
> +
> + WARN(1, "Failed to attach crtc property\n");
> +}
> +EXPORT_SYMBOL(drm_crtc_attach_property);
> +
> +int drm_crtc_property_set_value(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t value)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == property->base.id) {
> + crtc->property_values[i] = value;
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL(drm_crtc_property_set_value);
> +
> +int drm_crtc_property_get_value(struct drm_crtc *crtc,
> + struct drm_property *property, uint64_t *val)
> +{
> + int i;
> +
> + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> + if (crtc->property_ids[i] == property->base.id) {
> + *val = crtc->property_values[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +EXPORT_SYMBOL(drm_crtc_property_get_value);
> +
> int drm_mode_getproperty_ioctl(struct drm_device *dev,
> void *data, struct drm_file *file_priv)
> {
> @@ -2983,6 +3032,107 @@ out:
> return ret;
> }
>
> +int drm_mode_crtc_get_properties_ioctl(struct drm_device *dev, void *data,
> + struct drm_file *file_priv)
> +{
> + struct drm_mode_crtc_get_properties *arg = data;
> + struct drm_mode_object *obj;
> + struct drm_crtc *crtc;
> + int ret = 0;
> + int i;
> + int copied = 0;
> + int props_count = 0;
> + uint32_t __user *props_ptr;
> + uint64_t __user *prop_values_ptr;
> +
> + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> + return -EINVAL;
> +
> + mutex_lock(&dev->mode_config.mutex);
> +
> + obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
> + if (!obj) {
> + ret = -EINVAL;
> + goto out;
> + }
> + crtc = obj_to_crtc(obj);
> +
> + for (props_count = 0; props_count < DRM_CRTC_MAX_PROPERTY &&
> + crtc->property_ids[props_count] != 0; props_count++)
> + ;
> +
> + /* This ioctl is called twice, once to determine how much space is
> + * needed, and the 2nd time to fill it. */
> + if ((arg->count_props >= props_count) && props_count) {
> + copied = 0;
> + props_ptr = (uint32_t __user *)(unsigned
> long)(arg->props_ptr);
> + prop_values_ptr = (uint64_t __user *)(unsigned long)
> + (arg->prop_values_ptr);
> + for (i = 0; i < props_count; i++) {
> + if (put_user(crtc->property_ids[i],
> + props_ptr + copied)) {
> + ret = -EFAULT;
> + go
Re: [PATCH 1/5] drm: add drm_property_change_is_valid
On Tue, Mar 20, 2012 at 11:48:28AM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Move code from drm_mode_connector_property_set_ioctl to a new > function, so we can reuse this code when we add crtc properties. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/drm_crtc.c | 41 + > 1 files changed, 21 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c > index 6fdaf6f..1cadc11 100644 > --- a/drivers/gpu/drm/drm_crtc.c > +++ b/drivers/gpu/drm/drm_crtc.c > @@ -2910,6 +2910,26 @@ int drm_mode_connector_update_edid_property(struct > drm_connector *connector, > } > EXPORT_SYMBOL(drm_mode_connector_update_edid_property); > > +static int drm_property_change_is_valid(struct drm_property *property, > + __u64 value) static bool ... -- Ville Syrjälä Intel OTC ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Why do flush page cache twice when change TT's cache attribute
On Tue, Mar 20, 2012 at 10:15:02AM +0800, Scott Fang wrote:
> Can I do the optimization like:
>
> if (ttm->caching_state == tt_cached)
> -drm_clflush_pages(ttm->pages, ttm->num_pages);
> +for (i = 0; i < ttm->num_pages; ++i)
> + if (PageHighMem(ttm->pages[i]))
> +drm_clflush_pages(&ttm->pages[i], 1);
>
> only do flush cache when high memory and leave the linear memory flush in
> function set_memory_uc/wc?
So what are you trying to solve? I mean one way to fix this
is to do:
>
> 2012/3/20 Jerome Glisse
>
> > On Mon, 2012-03-19 at 23:11 +0800, Scott Fang wrote:
> > > In function ttm_tt_set_caching
> > > ,,,
> > >
> > > if (ttm->caching_state == tt_cached)
> > > drm_clflush_pages(ttm->pages, ttm->num_pages);
goto out;
> > >
> > > for (i = 0; i < ttm->num_pages; ++i) {
> > > cur_page = ttm->pages[i];
> > > if (likely(cur_page != NULL)) {
> > > ret = ttm_tt_set_page_caching(cur_page,
> > > ttm->caching_state,
> > > c_state);
> > > if (unlikely(ret != 0))
> > > goto out_err;
> > > }
> > > }
> >
out:
> > > ttm->caching_state = c_state;
> > >
> > > return 0;
Is the problem with calling page change twice making the machine slow?
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[Bug 29412] fans running at full-speed after resume from suspend with radeon and KMS
https://bugzilla.kernel.org/show_bug.cgi?id=29412 --- Comment #10 from Jon Dowland 2012-03-20 15:40:16 --- I'll have access to the machine again this Friday; I'll try it this weekend. Thanks! -- Configure bugmail: https://bugzilla.kernel.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are watching the assignee of the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 3/5] drm: add CRTC properties
On Tue, Mar 20, 2012 at 11:09:42AM -0400, Alex Deucher wrote:
> On Tue, Mar 20, 2012 at 10:48 AM, Paulo Zanoni wrote:
> > From: Paulo Zanoni
> >
> > Code based on the connector properties code.
> >
> > Two new ioctls:
> > - DRM_IOCTL_MODE_CRTC_GETPROPERTIES
> > - DRM_IOCTL_MODE_CRTC_SETPROPERTY
> >
> > The i915 driver needs this for the rotation and overscan compensation
> > properties. Other drivers might need this too.
> >
> > v2: replace BUG_ON() for WARN(), fix bugs, add functions to get/set
> > the value
> >
>
> Is there any reason why these can't just be exposed as connector
> properties? While the hw features you are exposing are technically
> part of the crtc block, so are most of the existing connector
> properties (scalers, etc.). Plus, while the scalers/transforms are
> part of the crtc hw, they only really make sense on certain
> connectors. E.g., underscan isn't particularly useful on non-TMDS
> capable connectors.
The reasons for this pretty much boil down to that we have quite a few
properties that belong to the crtc. Currently we abuse connector
properties for that because no one uses cloning, but imo that's not a
Great Idea. Other examples than rotation are blending/Z-order when using
planes, special options for color conversion (probably only on planes),
...
-Daniel
>
> Alex
>
>
> > Signed-off-by: Paulo Zanoni
> > ---
> > drivers/gpu/drm/drm_crtc.c | 150
> >
> > drivers/gpu/drm/drm_drv.c | 4 +-
> > include/drm/drm.h | 2 +
> > include/drm/drm_crtc.h | 28 -
> > include/drm/drm_mode.h | 13
> > 5 files changed, 195 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
> > index 6260fc3..df00c29 100644
> > --- a/drivers/gpu/drm/drm_crtc.c
> > +++ b/drivers/gpu/drm/drm_crtc.c
> > @@ -2712,6 +2712,55 @@ int drm_connector_property_get_value(struct
> > drm_connector *connector,
> > }
> > EXPORT_SYMBOL(drm_connector_property_get_value);
> >
> > +void drm_crtc_attach_property(struct drm_crtc *crtc,
> > + struct drm_property *property, uint64_t
> > init_val)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> > + if (crtc->property_ids[i] == 0) {
> > + crtc->property_ids[i] = property->base.id;
> > + crtc->property_values[i] = init_val;
> > + return;
> > + }
> > + }
> > +
> > + WARN(1, "Failed to attach crtc property\n");
> > +}
> > +EXPORT_SYMBOL(drm_crtc_attach_property);
> > +
> > +int drm_crtc_property_set_value(struct drm_crtc *crtc,
> > + struct drm_property *property, uint64_t
> > value)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> > + if (crtc->property_ids[i] == property->base.id) {
> > + crtc->property_values[i] = value;
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +EXPORT_SYMBOL(drm_crtc_property_set_value);
> > +
> > +int drm_crtc_property_get_value(struct drm_crtc *crtc,
> > + struct drm_property *property, uint64_t
> > *val)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
> > + if (crtc->property_ids[i] == property->base.id) {
> > + *val = crtc->property_values[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +EXPORT_SYMBOL(drm_crtc_property_get_value);
> > +
> > int drm_mode_getproperty_ioctl(struct drm_device *dev,
> > void *data, struct drm_file *file_priv)
> > {
> > @@ -2983,6 +3032,107 @@ out:
> > return ret;
> > }
> >
> > +int drm_mode_crtc_get_properties_ioctl(struct drm_device *dev, void *data,
> > + struct drm_file *file_priv)
> > +{
> > + struct drm_mode_crtc_get_properties *arg = data;
> > + struct drm_mode_object *obj;
> > + struct drm_crtc *crtc;
> > + int ret = 0;
> > + int i;
> > + int copied = 0;
> > + int props_count = 0;
> > + uint32_t __user *props_ptr;
> > + uint64_t __user *prop_values_ptr;
> > +
> > + if (!drm_core_check_feature(dev, DRIVER_MODESET))
> > + return -EINVAL;
> > +
> > + mutex_lock(&dev->mode_config.mutex);
> > +
> > + obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
> > + if (!obj) {
> > + ret = -EINVAL;
> > + goto out;
> > + }
> > + crtc = obj_to_crtc(obj);
> > +
> > + for (props_count = 0; props_count < DRM_CRTC_MAX_PROPERTY &&
> > + crtc->property_ids[props_count] != 0; props_count++)
> > + ;
> > +
[Bug 46713] HDMI audio played back at a wrong rate
https://bugs.freedesktop.org/show_bug.cgi?id=46713 Tvrtko Ursulin changed: What|Removed |Added Status|ASSIGNED|NEW --- Comment #19 from Tvrtko Ursulin 2012-03-20 08:57:42 PDT --- (In reply to comment #17) > If you wish, you can try switching to radeon and: > 1) Start playback > 2) Make sure speed is still wrong > 3) Execute: "avivotool regset 0x05b0 0x000ea600" > 4) Execute: "avivotool regset 0x05bc 0x0072" > > Does it help? Unfortunately not. First line speeds it up (way to much) and the second one brings it down into too slow territory again. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 4/5] drm/i915: add 'rotation' CRTC property
Hi Paulo,
thanks for a quick response posting the patches.
In my use of CRTC rotation properties, I need the change to be
synchronized with modeset. Your implementation activate the property
change immediately instead of staging it for next modeset. Do you think
it is ok for different drivers to behave differently when properties are
set? I can't allow glitches in the output when changing the rotation in
one frame and flipping the framebuffer to one of correct size and
content in another. This would mean I will have to stage the setting and
apply it at next modeset (different behavior). Or do I just have to wait
until we have an atomic modeset that can also set properties (Jesse can
you post your latest proposal ...)?
Do you think you could export the call registering the rotation
property? That way other drivers can reuse it and we don't risk multiple
properties with different ranges etc for the same logical property (like
400 mil degrees or 0-3, 1-4, UR,UD,CCW,CW ...). So some sort of standard
property create.
Then it would also be nice to define some rules in KMS of what should be
modeset params and what should be properties. Modeset params seems hard
to add (struct change) and properties seems very loosely defined and
device specific. Having something in between would be nice (standard and
easy to add), to make it easier to add things like plane z-order
(instead of driver specific ioctls or properties).
Maybe a new "atomic" modeset with just a list of {object_id,
property_id, value} making all params into properties and modeset more
dynamic. It would also solve the atomic modset, even with device
specific properties and future features.
Sorry for multiple topics, but they are sort of related.
/BR
/Marcus
On 03/20/2012 03:48 PM, Paulo Zanoni wrote:
From: Paulo Zanoni
This property is needed so we can inform the KVMr feature about our
current rotation: whenever we change the rotation, we should change
that property so that the KVMr knows that the screen is rotated.
How to reproduce the problem:
- on an AMT machine, enable KVM
- boot the machine, use xrandr to rotate the display
- use VNC to connect to the KVM
- try to use the mouse
v2: only create the property once
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |5 +++
drivers/gpu/drm/i915/intel_display.c | 66 ++
3 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7a00b7..7994c4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *rotation_property;
} drm_i915_private_t;
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..79e8b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2407,6 +2407,11 @@
#define PIPECONF_INTERLACED_DBL_ILK (4<< 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5<< 21) /* ilk/snb only */
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_ROTATION_MASK (3<< 14)
+#define PIPECONF_ROTATION_0 (0<< 14)
+#define PIPECONF_ROTATION_90 (1<< 14)
+#define PIPECONF_ROTATION_180(2<< 14)
+#define PIPECONF_ROTATION_270(3<< 14)
#define PIPECONF_BPP_MASK (0x00e0)
#define PIPECONF_BPP_8 (0<<5)
#define PIPECONF_BPP_10 (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 683002fb..4842de8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7625,6 +7625,50 @@ static void intel_crtc_reset(struct drm_crtc *crtc)
intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
}
+static void intel_crtc_set_rotation(struct drm_crtc *crtc,
+ uint64_t rotation)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = PIPECONF(intel_crtc->pipe);
+ u32 val = I915_READ(reg);
+
+ val&= ~PIPECONF_ROTATION_MASK;
+
+ switch (rotation) {
+ case 0:
+ val |= PIPECONF_ROTATION_0;
+ break;
+ case 90:
+ val |= PIPECONF_ROTATION_90;
+ break;
+ case 180:
+ val |= PIPECONF_ROTATION_180;
+ break;
+ case 270:
+ val |= PIPECONF_ROTATION_270;
+ break;
+ default:
+ DRM_ERROR("Unsupported rotation: %Lu\n", rotation);
+ val |= PIPECONF_ROTATION_0;
+ }
+
[Bug 44772] Radeon HD6950 (Cayman): Resuming from hibernation fails sometimes
https://bugs.freedesktop.org/show_bug.cgi?id=44772 --- Comment #6 from Harald Judt 2012-03-20 11:15:35 PDT --- The bug is still present with kernel-3.3 final. Further tests confirm that this is an issue specific to the HD6950 card. I swapped the card with a Radeon HD3650 (RV635 chipset) for testing while leaving the rest of the system configuration unchanged, and the problem was no longer reproducible and hibernating and resuming worked fine. If I change the power profile back from low to default, sometimes the system will freeze immediately when hibernating. Maybe some registers still don't get initialized/updated properly? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH] drm/radeon/kms: add info query for max pipes
The maximum number of pipes is needed by the user space compute
driver to calculate the number of wavefronts per thread group.
Signed-off-by: Tom Stellard
---
drivers/gpu/drm/radeon/radeon_drv.c |3 ++-
drivers/gpu/drm/radeon/radeon_kms.c | 13 +
include/drm/radeon_drm.h|2 ++
3 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 498d21d..ef7bb3f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -56,9 +56,10 @@
* 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
* 2.13.0 - virtual memory support, streamout
* 2.14.0 - add evergreen tiling informations
+ * 2.15.0 - add max_pipes query
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 14
+#define KMS_DRIVER_MINOR 15
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
b/drivers/gpu/drm/radeon/radeon_kms.c
index 1986eba..72d70eb 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -264,6 +264,19 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
return -EINVAL;
value = RADEON_IB_VM_MAX_SIZE;
break;
+ case RADEON_INFO_MAX_PIPES:
+ if (rdev->family >= CHIP_CAYMAN)
+ value = rdev->config.cayman.max_pipes_per_simd;
+ else if (rdev->family >= CHIP_CEDAR)
+ value = rdev->config.evergreen.max_pipes;
+ else if (rdev->family >= CHIP_RV770)
+ value = rdev->config.rv770.max_pipes;
+ else if (rdev->family >= CHIP_R600)
+ value = rdev->config.r600.max_pipes;
+ else {
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index cb2f0c3..6cde931 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -962,6 +962,8 @@ struct drm_radeon_cs {
#define RADEON_INFO_VA_START 0x0e
/* maximum size of ib using the virtual memory cs */
#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
+/* max pipes - needed for compute shaders */
+#define RADEON_INFO_MAX_PIPES 0x10
struct drm_radeon_info {
uint32_trequest;
--
1.7.7.6
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Re: [PATCH 4/5] drm/i915: add 'rotation' CRTC property
On Tue, Mar 20, 2012 at 05:48:14PM +0100, Marcus Lorentzon wrote:
> Then it would also be nice to define some rules in KMS of what should be
> modeset params and what should be properties. Modeset params seems hard
> to add (struct change) and properties seems very loosely defined and
> device specific. Having something in between would be nice (standard and
> easy to add), to make it easier to add things like plane z-order
> (instead of driver specific ioctls or properties).
> Maybe a new "atomic" modeset with just a list of {object_id,
> property_id, value} making all params into properties and modeset more
> dynamic. It would also solve the atomic modset, even with device
> specific properties and future features.
Great minds think alike ;) Exactly what I've suggested a few times
before. Unfortunately I haven't had the time to do any prototyping
yet.
--
Ville Syrjälä
Intel OTC
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[Bug 43278] RS482: Hibernation reliably hangs, suspend-to-RAM unreliably hangs
https://bugs.freedesktop.org/show_bug.cgi?id=43278 --- Comment #17 from Jonathan Nieder 2012-03-20 11:47:35 PDT --- (In reply to comment #10) >>> When trying the "drm.debug=0x6" and "no_console_suspend" parameters the >>> system sometimes didn't hangup on hibernate test - the test worked 3 >>> times in follow without hangup. >>> And second suspend to disk with the two parameters did not really >>> suspend - the power led continued to burn as described above - and the >>> screen turned to power safe mode - but after a second or two the screen >>> powered up again and showed the login screen of suspend mode. >>> But this could not be reproduced constantly - strange! >> Do you have logs from when this happened (they might be somewhere in >> /var/log/dmesg*)? > > Please find attached all the /var/log/dmesg* files with their timestamps > in ls.txt . That isn't quite what I meant. The timestamps aren't so helpful to us since we weren't there; we can't easily tell which suspend you are talking about. What kernel are you using these days? Does it still fail to hibernate when the radeon driver is loaded? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 45018] [bisected] rendering regression since added support for virtual address space on cayman v11
https://bugs.freedesktop.org/show_bug.cgi?id=45018 --- Comment #40 from Harald Judt 2012-03-20 11:50:26 PDT --- (In reply to comment #35) > (In reply to comment #34) > > Is there a way to disable radeon virtual addressing when loading the kernel? > > You can disable it in mesa. Just set ws->info.r600_virtual_address to FALSE > in > do_winsys_init() in radeon_drm_winsys.c. Thanks, as expected this also cures the garbled fonts in blender. (In reply to comment #37) > We can add a mesa option if we aren't able to get this fixed in time for the > next mesa release, but for now I'd prefer to leave it enabled otherwise most > users will just disable it and not test the current code which won't help in > getting it fixed. We're already 2 users affected and very willing to test and help ;-) What information could we provide to further improve the situation? -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[Bug 45018] [bisected] rendering regression since added support for virtual address space on cayman v11
https://bugs.freedesktop.org/show_bug.cgi?id=45018 --- Comment #41 from Alex Deucher 2012-03-20 12:11:26 PDT --- Are you still getting any messages like the following in your dmesg with the latest mesa from git? radeon :01:00.0: offset 0x20 is in reserved area 0x80 radeon :01:00.0: offset 0x20 is in reserved area 0x80 I pushed a patch yesterday that fixed up a missing va setup, although I don't think the driver should hit that path with cayman and vm support. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH] drm/radeon/kms: add info query for max pipes
On Tue, Mar 20, 2012 at 1:30 PM, Tom Stellard wrote:
> The maximum number of pipes is needed by the user space compute
> driver to calculate the number of wavefronts per thread group.
>
> Signed-off-by: Tom Stellard
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/radeon_drv.c | 3 ++-
> drivers/gpu/drm/radeon/radeon_kms.c | 13 +
> include/drm/radeon_drm.h | 2 ++
> 3 files changed, 17 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index 498d21d..ef7bb3f 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -56,9 +56,10 @@
> * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
> * 2.13.0 - virtual memory support, streamout
> * 2.14.0 - add evergreen tiling informations
> + * 2.15.0 - add max_pipes query
> */
> #define KMS_DRIVER_MAJOR 2
> -#define KMS_DRIVER_MINOR 14
> +#define KMS_DRIVER_MINOR 15
> #define KMS_DRIVER_PATCHLEVEL 0
> int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
> int radeon_driver_unload_kms(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
> b/drivers/gpu/drm/radeon/radeon_kms.c
> index 1986eba..72d70eb 100644
> --- a/drivers/gpu/drm/radeon/radeon_kms.c
> +++ b/drivers/gpu/drm/radeon/radeon_kms.c
> @@ -264,6 +264,19 @@ int radeon_info_ioctl(struct drm_device *dev, void
> *data, struct drm_file *filp)
> return -EINVAL;
> value = RADEON_IB_VM_MAX_SIZE;
> break;
> + case RADEON_INFO_MAX_PIPES:
> + if (rdev->family >= CHIP_CAYMAN)
> + value = rdev->config.cayman.max_pipes_per_simd;
> + else if (rdev->family >= CHIP_CEDAR)
> + value = rdev->config.evergreen.max_pipes;
> + else if (rdev->family >= CHIP_RV770)
> + value = rdev->config.rv770.max_pipes;
> + else if (rdev->family >= CHIP_R600)
> + value = rdev->config.r600.max_pipes;
> + else {
> + return -EINVAL;
> + }
> + break;
> default:
> DRM_DEBUG_KMS("Invalid request %d\n", info->request);
> return -EINVAL;
> diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
> index cb2f0c3..6cde931 100644
> --- a/include/drm/radeon_drm.h
> +++ b/include/drm/radeon_drm.h
> @@ -962,6 +962,8 @@ struct drm_radeon_cs {
> #define RADEON_INFO_VA_START 0x0e
> /* maximum size of ib using the virtual memory cs */
> #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
> +/* max pipes - needed for compute shaders */
> +#define RADEON_INFO_MAX_PIPES 0x10
>
> struct drm_radeon_info {
> uint32_t request;
> --
> 1.7.7.6
>
> ___
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> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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[PATCH] [RFC] dma-buf: mmap support
Let's have some competition here for dma_buf mmap support ;-) Compared to Rob Clarke's RFC I've ditched the prepare/finish hooks and corresponding ioctls on the dma_buf file. The major reason for that is that many people seem to be under the impression that this is also for synchronization with outstanding asynchronous processsing. I'm pretty massively opposed to this because: - It boils down reinventing a new rather general-purpose userspace synchronization interface. If we look at things like futexes, this is hard to get right. - Furthermore a lot of kernel code has to interact with this synchronization primitive. This smells a look like the dri1 hw_lock, a horror show I prefer not to reinvent. - Even more fun is that multiple different subsystems would interact here, so we have plenty of opportunities to create funny deadlock scenarios. I think synchronization is a wholesale different problem from data sharing and should be tackled as an orthogonal problem. Now we could demand that prepare/finish may only ensure cache coherency (as Rob intended), but that runs up into the next problem: We not only need mmap support to facilitate sw-only processing nodes in a pipeline (without jumping through hoops by importing the dma_buf into some sw-access only importer), which allows for a nicer ION->dma-buf upgrade path for existing Android userspace. We also need mmap support for existing importing subsystems to support existing userspace libraries. And a loot of these subsystems are expected to export coherent userspace mappings. So prepare/finish can only ever be optional and the exporter /needs/ to support coherent mappings. Given that mmap access is always somewhat fallback-y in nature I've decided to drop this optimization, instead of just making it optional. If we demonstrate a clear need for this, supported by benchmark results, we can always add it in again later as an optional extension. Other differences compared to Rob's RFC is the above mentioned support for mapping a dma-buf through facilities provided by the importer. Which results in mmap support no longer being optional. Note taht this dma-buf mmap patch does _not_ support every possible insanity an existing subsystem could pull of with mmap: Because it does not allow to intercept pagefaults and shoot down ptes importing subsystems can't add some magic of their own at these points (e.g. to automatically synchronize with outstanding rendering or set up some special resources). I've done a cursory read through a few mmap implementions of various subsytems and I'm hopeful that we can avoid this (and the complexity it'd bring with it). Additonally I've extended the documentation a bit to explain the hows and whys of this mmap extension. Comments, reviews and flames highly welcome. Cheers, Daniel --- Documentation/dma-buf-sharing.txt | 84 +--- drivers/base/dma-buf.c| 64 +++- include/linux/dma-buf.h | 16 +++ 3 files changed, 156 insertions(+), 8 deletions(-) diff --git a/Documentation/dma-buf-sharing.txt b/Documentation/dma-buf-sharing.txt index a6d4c37..c42a4a5 100644 --- a/Documentation/dma-buf-sharing.txt +++ b/Documentation/dma-buf-sharing.txt @@ -29,13 +29,6 @@ The buffer-user in memory, mapped into its own address space, so it can access the same area of memory. -*IMPORTANT*: [see https://lkml.org/lkml/2011/12/20/211 for more details] -For this first version, A buffer shared using the dma_buf sharing API: -- *may* be exported to user space using "mmap" *ONLY* by exporter, outside of - this framework. -- with this new iteration of the dma-buf api cpu access from the kernel has been - enable, see below for the details. - dma-buf operations for device dma only -- @@ -313,6 +306,83 @@ Access to a dma_buf from the kernel context involves three steps: enum dma_data_direction dir); +Direct Userspace Access/mmap Support + + +Being able to mmap an export dma-buf buffer object has 2 main use-cases: +- CPU fallback processing in a pipeline and +- supporting existing mmap interfaces in importers. + +1. CPU fallback processing in a pipeline + + In many processing pipelines it is sometimes required that the cpu can access + the data in a dma-buf (e.g. for thumbnail creation, snapshots, ...). To avoid + the need to handle this specially in userspace frameworks for buffer sharing + it's ideal if the dma_buf fd itself can be used to access the backing storage + from userspace using mmap. + + Furthermore Android's ION framework already supports this (and is otherwise + rather similar to dma-buf from a userspace consumer side with using fds as + handles, too). So it's beneficial to support this in a similar fashion on + dma-buf to have a good transition path for existing Android userspace. + + No special i
[PATCH 00/48] Add SI, TN support
From: Alex Deucher This patch set adds support for SI (Southern Islands discrete GPUs) and TN (Trinity APU). The patches are available here as well: http://people.freedesktop.org/~agd5f/si_tn/ New ucode for SI (TAHITI, PITCAIRN, VERDE) and TN (ARUBA) is available here: http://people.freedesktop.org/~agd5f/radeon_ucode/ Userspace code to follow. I included Tom's patch (0001) since patch 0032 depends on it. Alex Deucher (46): drm/radeon/kms: Upstream ObjectID.h updates drm/radeon/kms: upstream atombios.h updates drm/radeon/kms: upstream power table updates drm/radeon/kms: add SI chip families drm/radeon/kms: add initial DCE6 display watermark support drm/radeon/kms: fix up atom HPD gpio parsing for DCE6 drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bits drm/radeon/kms/atom: add support for crtc power gating drm/radeon/kms: DCE6 disp eng pll updates drm/radeon/kms/atom: add support for DCE6.x dig transmitters drm/radeon/kms: DP aux updates for DCE6 drm/radeon/kms: update comments about dig encoders/transmitters drm/radeon/kms/atom: add support for SI SetVoltage table drm/radeon/kms: update power table parsing for SI drm/radeon/kms: add support for internal thermal sensor on SI drm/radeon/kms: add gpu init support for SI drm/radeon/kms: Add support for SI GPU reset drm/radeon/kms: add support for MC/VM setup on SI drm/radeon/kms: add support for the CONST IB to the CS ioctl drm/radeon/kms: add VM CS checker for SI drm/radeon/kms: Only VM CS ioctl is supported on SI (v2) drm/radeon/kms: add ucode loading for SI drm/radeon/kms: add support for MC ucode loading on SI drm/radeon/kms: add support for CP setup on SI drm/radeon/kms: add IB and fence dispatch functions for SI drm/radeon/kms: Add support for RLC init on SI drm/radeon/kms: add support for interrupts on SI drm/radeon/kms: fill in startup/shutdown callbacks for SI drm/radeon/kms: add support for compute rings in CS ioctl on SI drm/radeon/kms: add radeon_asic struct for SI drm/radeon/kms: Add SI pci ids drm/radeon/kms: add trinity (TN) chip family drm/radeon/kms: no support for internal thermal sensor on TN yet drm/radeon/kms: DCE6.1 watermark updates for TN drm/radeon/kms: DCE6.1 disp eng pll updates drm/radeon/kms: Adjust pll picker for DCE6.1 drm/radeon/kms: disable PPLL0 on DCE6.1 when not in use drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls drm/radeon/kms: Add checks for TN in the DP bridge code drm/radeon/kms: cayman gpu init updates for trinity drm/radeon/kms: Update evergreen functions for trinity drm/radeon/kms/vm: set vram base offset properly for TN drm/radeon/kms: add support for ucode loading on trinity (v2) drm/radeon/kms: add radeon_asic struct for trinity drm/radeon/kms: add trinity pci ids drm/radeon/kms: update duallink checks for DCE6 Michel Dänzer (1): drm/radeon: Update radeon_info_ioctl for SI. (v2) Tom Stellard (1): drm/radeon/kms: add info query for max pipes drivers/gpu/drm/radeon/Makefile |2 +- drivers/gpu/drm/radeon/ObjectID.h |5 + drivers/gpu/drm/radeon/atombios.h | 1109 +++- drivers/gpu/drm/radeon/atombios_crtc.c | 100 +- drivers/gpu/drm/radeon/atombios_dp.c|6 +- drivers/gpu/drm/radeon/atombios_encoders.c | 71 +- drivers/gpu/drm/radeon/evergreen.c | 25 +- drivers/gpu/drm/radeon/evergreen_blit_kms.c |2 +- drivers/gpu/drm/radeon/ni.c | 141 +- drivers/gpu/drm/radeon/nid.h|1 + drivers/gpu/drm/radeon/r600.c | 25 +- drivers/gpu/drm/radeon/r600d.h |4 + drivers/gpu/drm/radeon/radeon.h | 55 +- drivers/gpu/drm/radeon/radeon_asic.c| 208 ++ drivers/gpu/drm/radeon/radeon_asic.h| 25 + drivers/gpu/drm/radeon/radeon_atombios.c| 78 +- drivers/gpu/drm/radeon/radeon_connectors.c |2 +- drivers/gpu/drm/radeon/radeon_cs.c | 63 +- drivers/gpu/drm/radeon/radeon_device.c |6 +- drivers/gpu/drm/radeon/radeon_display.c |2 +- drivers/gpu/drm/radeon/radeon_drv.c |3 +- drivers/gpu/drm/radeon/radeon_encoders.c|6 +- drivers/gpu/drm/radeon/radeon_family.h |4 + drivers/gpu/drm/radeon/radeon_kms.c | 32 +- drivers/gpu/drm/radeon/radeon_mode.h|2 +- drivers/gpu/drm/radeon/radeon_pm.c |7 + drivers/gpu/drm/radeon/radeon_reg.h |1 + drivers/gpu/drm/radeon/radeon_ring.c|1 + drivers/gpu/drm/radeon/si.c | 4128 +++ drivers/gpu/drm/radeon/si_blit_shaders.c| 252 ++ drivers/gpu/drm/radeon/si_blit_shaders.h| 32 + drivers/gpu/drm/radeon/si_reg.h | 33 + drivers/gpu/drm/radeon/sid.h| 886 ++ include/drm/drm_pciids.h| 54 + include/drm/radeon_drm.h|3 + 35 files changed, 7230 insertions(+),
[PATCH 01/48] drm/radeon/kms: add info query for max pipes
From: Tom Stellard
The maximum number of pipes is needed by the user space compute
driver to calculate the number of wavefronts per thread group.
Signed-off-by: Tom Stellard
---
drivers/gpu/drm/radeon/radeon_drv.c |3 ++-
drivers/gpu/drm/radeon/radeon_kms.c | 13 +
include/drm/radeon_drm.h|2 ++
3 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c
b/drivers/gpu/drm/radeon/radeon_drv.c
index 498d21d..ef7bb3f 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -56,9 +56,10 @@
* 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
* 2.13.0 - virtual memory support, streamout
* 2.14.0 - add evergreen tiling informations
+ * 2.15.0 - add max_pipes query
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 14
+#define KMS_DRIVER_MINOR 15
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c
b/drivers/gpu/drm/radeon/radeon_kms.c
index 1986eba..72d70eb 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -264,6 +264,19 @@ int radeon_info_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
return -EINVAL;
value = RADEON_IB_VM_MAX_SIZE;
break;
+ case RADEON_INFO_MAX_PIPES:
+ if (rdev->family >= CHIP_CAYMAN)
+ value = rdev->config.cayman.max_pipes_per_simd;
+ else if (rdev->family >= CHIP_CEDAR)
+ value = rdev->config.evergreen.max_pipes;
+ else if (rdev->family >= CHIP_RV770)
+ value = rdev->config.rv770.max_pipes;
+ else if (rdev->family >= CHIP_R600)
+ value = rdev->config.r600.max_pipes;
+ else {
+ return -EINVAL;
+ }
+ break;
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index cb2f0c3..6cde931 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -962,6 +962,8 @@ struct drm_radeon_cs {
#define RADEON_INFO_VA_START 0x0e
/* maximum size of ib using the virtual memory cs */
#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
+/* max pipes - needed for compute shaders */
+#define RADEON_INFO_MAX_PIPES 0x10
struct drm_radeon_info {
uint32_trequest;
--
1.7.7.5
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[PATCH 02/48] drm/radeon/kms: Upstream ObjectID.h updates
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ObjectID.h |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h index c61c3fe..ca4b038 100644 --- a/drivers/gpu/drm/radeon/ObjectID.h +++ b/drivers/gpu/drm/radeon/ObjectID.h @@ -85,6 +85,7 @@ #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20 #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21 +#define ENCODER_OBJECT_ID_INTERNAL_VCE0x24 #define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO0xFF @@ -387,6 +388,10 @@ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ ENCODER_OBJECT_ID_NUTMEG << OBJECT_ID_SHIFT) +#define ENCODER_VCE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ + GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ + ENCODER_OBJECT_ID_INTERNAL_VCE << OBJECT_ID_SHIFT) + // /* Connector Object ID definition - Shared with BIOS */ // -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 04/48] drm/radeon/kms: upstream power table updates
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios.h| 180 +++---
drivers/gpu/drm/radeon/radeon_atombios.c | 14 +-
2 files changed, 172 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios.h
b/drivers/gpu/drm/radeon/atombios.h
index 4760466..4b04ba3 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -7270,6 +7270,8 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER
#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control
will be implemented, do NOT show this in PPGen.
#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used
internally
#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15
+#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16
+#define ATOM_PP_THERMALCONTROLLER_LM96163 17
// Thermal controller 'combo type' to use an external controller for Fan
control and an internal controller for thermal.
// We probably should reserve the bit 0x80 for this use.
@@ -7285,6 +7287,7 @@ typedef struct _ATOM_PPLIB_STATE
UCHAR ucClockStateIndices[1]; // variable-sized
} ATOM_PPLIB_STATE;
+
typedef struct _ATOM_PPLIB_FANTABLE
{
UCHAR ucFanTableFormat;// Change this if the table
format changes or version changes so that the other fields are not the same.
@@ -7297,12 +7300,20 @@ typedef struct _ATOM_PPLIB_FANTABLE
USHORT usPWMHigh; // The PWM value at THigh.
} ATOM_PPLIB_FANTABLE;
+typedef struct _ATOM_PPLIB_FANTABLE2
+{
+ATOM_PPLIB_FANTABLE basicTable;
+USHORT usTMax; // The max temperature
+} ATOM_PPLIB_FANTABLE2;
+
typedef struct _ATOM_PPLIB_EXTENDEDHEADER
{
USHORT usSize;
ULONG ulMaxEngineClock; // For Overdrive.
ULONG ulMaxMemoryClock; // For Overdrive.
// Add extra system parameters here, always adjust size to include all
fields.
+USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
+USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
} ATOM_PPLIB_EXTENDEDHEADER;
ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
@@ -7325,6 +7336,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x0001 // Enable
the 'regulator hot' feature.
#define ATOM_PP_PLATFORM_CAP_BACO 0x0002 // Does
the driver supports BACO state.
+
typedef struct _ATOM_PPLIB_POWERPLAYTABLE
{
ATOM_COMMON_TABLE_HEADER sHeader;
@@ -7383,7 +7395,8 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
-USHORT usReserved[2];
+USHORT usVddcPhaseShedLimitsTableOffset;// Points
to ATOM_PPLIB_PhaseSheddingLimits_Table
+USHORT usReserved;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@@ -7393,8 +7406,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
ULONG ulNearTDPLimit;
ULONG ulSQRampingThreshold;
USHORT usCACLeakageTableOffset; // Points to
ATOM_PPLIB_CAC_Leakage_Table
-ULONG ulCACLeakage;// TBD, this
parameter is still under discussion. Change to ulReserved if not needed.
-ULONG ulReserved;
+ULONG ulCACLeakage;// The
iLeakage for driver calculated CAC leakage table
+USHORT usTDPODLimit;
+USHORT usLoadLineSlope; // in
milliOhms * 100
} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
ATOM_PPLIB_NONCLOCK_INFO::usClassification
@@ -7423,6 +7437,7 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
ATOM_PPLIB_NONCLOCK_INFO::usClassification2
#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001
#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002
+#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004
//Multi-View Codec (BD-3D)
ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x0001
@@ -7446,7 +7461,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING0x1000
#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x2000
-#define ATOM_PPLIB_DISALLOW_ON_DC0x4000
+
+#define ATOM_PPLIB_DISALLOW_ON_DC 0x4000
+
#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x8000
//memory related flags
@@ -7508,7 +7525,7 @@ typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
#define ATOM_PPLIB_R
[PATCH 05/48] drm/radeon/kms: add SI chip families
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_device.c |3 +++
drivers/gpu/drm/radeon/radeon_family.h |3 +++
3 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index d2870a0..2081972 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1638,6 +1638,7 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
(rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
+#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_TAHITI))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 49f7cb7..9b8dace 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -89,6 +89,9 @@ static const char radeon_family_name[][16] = {
"TURKS",
"CAICOS",
"CAYMAN",
+ "TAHITI",
+ "PITCAIRN",
+ "VERDE",
"LAST",
};
diff --git a/drivers/gpu/drm/radeon/radeon_family.h
b/drivers/gpu/drm/radeon/radeon_family.h
index ec2f1ea..71d626a 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -87,6 +87,9 @@ enum radeon_family {
CHIP_TURKS,
CHIP_CAICOS,
CHIP_CAYMAN,
+ CHIP_TAHITI,
+ CHIP_PITCAIRN,
+ CHIP_VERDE,
CHIP_LAST,
};
--
1.7.7.5
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[PATCH 06/48] drm/radeon/kms: add initial DCE6 display watermark support
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |2 +-
drivers/gpu/drm/radeon/radeon_asic.h |3 +
drivers/gpu/drm/radeon/si.c | 486 ++
drivers/gpu/drm/radeon/sid.h | 46
4 files changed, 536 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/si.c
create mode 100644 drivers/gpu/drm/radeon/sid.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 8410415..fa3e704 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -71,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \
- radeon_semaphore.o radeon_sa.o atombios_i2c.o
+ radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
b/drivers/gpu/drm/radeon/radeon_asic.h
index b8f0a16..007f0f6 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -461,4 +461,7 @@ void cayman_vm_set_page(struct radeon_device *rdev, struct
radeon_vm *vm,
unsigned pfn, uint64_t addr, uint32_t flags);
int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
+/* DCE6 - SI */
+void dce6_bandwidth_update(struct radeon_device *rdev);
+
#endif
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
new file mode 100644
index 000..39c64df
--- /dev/null
+++ b/drivers/gpu/drm/radeon/si.c
@@ -0,0 +1,486 @@
+/*
+ * Copyright 2011 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon.h"
+#include "radeon_asic.h"
+#include "radeon_drm.h"
+#include "sid.h"
+#include "atom.h"
+
+/* watermark setup */
+static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
+ struct radeon_crtc *radeon_crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *other_mode)
+{
+ u32 tmp;
+ /*
+* Line Buffer Setup
+* There are 3 line buffers, each one shared by 2 display controllers.
+* DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
+* the display controllers. The paritioning is done via one of four
+* preset allocations specified in bits 21:20:
+* 0 - half lb
+* 2 - whole lb, other crtc must be disabled
+*/
+ /* this can get tricky if we have two large displays on a paired group
+* of crtcs. Ideally for multiple large displays we'd assign them to
+* non-linked crtcs for maximum line buffer allocation.
+*/
+ if (radeon_crtc->base.enabled && mode) {
+ if (other_mode)
+ tmp = 0; /* 1/2 */
+ else
+ tmp = 2; /* whole */
+ } else
+ tmp = 0;
+
+ WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
+ DC_LB_MEMORY_CONFIG(tmp));
+
+ if (radeon_crtc->base.enabled && mode) {
+ switch (tmp) {
+ case 0:
+ default:
+ return 4096 * 2;
+ case 2:
+ return 8192 * 2;
+ }
+ }
+
+ /* controller not enabled, so no lb used */
+ return 0;
+}
+
+static u32 dce6_get_number_of_dram_channels(struct radeon_device *rdev)
+{
+ u32 tmp = RREG32(MC_SHARED_CHMAP);
+
+ switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
+
[PATCH 07/48] drm/radeon/kms: fix up atom HPD gpio parsing for DCE6
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_atombios.c |4 ++- drivers/gpu/drm/radeon/radeon_reg.h |1 + drivers/gpu/drm/radeon/si_reg.h | 33 ++ 3 files changed, 37 insertions(+), 1 deletions(-) create mode 100644 drivers/gpu/drm/radeon/si_reg.h diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 2554611..7e2ba25 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -253,7 +253,9 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device memset(&hpd, 0, sizeof(struct radeon_hpd)); - if (ASIC_IS_DCE4(rdev)) + if (ASIC_IS_DCE6(rdev)) + reg = SI_DC_GPIO_HPD_A; + else if (ASIC_IS_DCE4(rdev)) reg = EVERGREEN_DC_GPIO_HPD_A; else reg = AVIVO_DC_GPIO_HPD_A; diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h index 5098634..5d8f735 100644 --- a/drivers/gpu/drm/radeon/radeon_reg.h +++ b/drivers/gpu/drm/radeon/radeon_reg.h @@ -56,6 +56,7 @@ #include "r600_reg.h" #include "evergreen_reg.h" #include "ni_reg.h" +#include "si_reg.h" #define RADEON_MC_AGP_LOCATION 0x014c #defineRADEON_MC_AGP_START_MASK0x diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h new file mode 100644 index 000..eda938a --- /dev/null +++ b/drivers/gpu/drm/radeon/si_reg.h @@ -0,0 +1,33 @@ +/* + * Copyright 2010 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef __SI_REG_H__ +#define __SI_REG_H__ + +/* SI */ +#define SI_DC_GPIO_HPD_MASK 0x65b0 +#define SI_DC_GPIO_HPD_A 0x65b4 +#define SI_DC_GPIO_HPD_EN0x65b8 +#define SI_DC_GPIO_HPD_Y 0x65bc + +#endif -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 08/48] drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bits
From: Alex Deucher The hw no longer has the bits and the table is removed. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 72672ea..841ee3e 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -243,7 +243,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) /* adjust pm to dpms changes BEFORE enabling crtcs */ radeon_pm_compute_clocks(rdev); atombios_enable_crtc(crtc, ATOM_ENABLE); - if (ASIC_IS_DCE3(rdev)) + if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); atombios_blank_crtc(crtc, ATOM_DISABLE); drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); @@ -255,7 +255,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); if (radeon_crtc->enabled) atombios_blank_crtc(crtc, ATOM_ENABLE); - if (ASIC_IS_DCE3(rdev)) + if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); atombios_enable_crtc(crtc, ATOM_DISABLE); radeon_crtc->enabled = false; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 09/48] drm/radeon/kms/atom: add support for crtc power gating
From: Alex Deucher
Each pair of crtcs (0/1, 2/3, 4/5) can be power gated.
Make sure the power is applied when the crtc is in use and
only power down the pair when both are off.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 38
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 841ee3e..62ddf8d 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -231,6 +231,22 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int
state)
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t
*)&args);
}
+static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
+{
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
+ ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
+
+ memset(&args, 0, sizeof(args));
+
+ args.ucDispPipeId = radeon_crtc->crtc_id;
+ args.ucEnable = state;
+
+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t
*)&args);
+}
+
void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
{
struct drm_device *dev = crtc->dev;
@@ -242,6 +258,9 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
radeon_crtc->enabled = true;
/* adjust pm to dpms changes BEFORE enabling crtcs */
radeon_pm_compute_clocks(rdev);
+ /* disable crtc pair power gating before programming */
+ if (ASIC_IS_DCE6(rdev))
+ atombios_powergate_crtc(crtc, ATOM_DISABLE);
atombios_enable_crtc(crtc, ATOM_ENABLE);
if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
@@ -259,6 +278,25 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
atombios_enable_crtc(crtc, ATOM_DISABLE);
radeon_crtc->enabled = false;
+ /* power gating is per-pair */
+ if (ASIC_IS_DCE6(rdev)) {
+ struct drm_crtc *other_crtc;
+ struct radeon_crtc *other_radeon_crtc;
+ list_for_each_entry(other_crtc,
&rdev->ddev->mode_config.crtc_list, head) {
+ other_radeon_crtc = to_radeon_crtc(other_crtc);
+ if (((radeon_crtc->crtc_id == 0) &&
(other_radeon_crtc->crtc_id == 1)) ||
+ ((radeon_crtc->crtc_id == 1) &&
(other_radeon_crtc->crtc_id == 0)) ||
+ ((radeon_crtc->crtc_id == 2) &&
(other_radeon_crtc->crtc_id == 3)) ||
+ ((radeon_crtc->crtc_id == 3) &&
(other_radeon_crtc->crtc_id == 2)) ||
+ ((radeon_crtc->crtc_id == 4) &&
(other_radeon_crtc->crtc_id == 5)) ||
+ ((radeon_crtc->crtc_id == 5) &&
(other_radeon_crtc->crtc_id == 4))) {
+ /* if both crtcs in the pair are off,
enable power gating */
+ if (other_radeon_crtc->enabled == false)
+ atombios_powergate_crtc(crtc,
ATOM_ENABLE);
+ break;
+ }
+ }
+ }
/* adjust pm to dpms changes AFTER disabling crtcs */
radeon_pm_compute_clocks(rdev);
break;
--
1.7.7.5
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[PATCH 10/48] drm/radeon/kms: DCE6 disp eng pll updates
From: Alex Deucher
Rename the function to better match the functionality.
DCPLL became PLL0 on DCE6.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 15 ++-
drivers/gpu/drm/radeon/radeon_device.c |2 +-
drivers/gpu/drm/radeon/radeon_display.c |2 +-
drivers/gpu/drm/radeon/radeon_mode.h|2 +-
4 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 62ddf8d..6fe4a6d 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -737,7 +737,7 @@ union set_pixel_clock {
/* on DCE5, make sure the voltage is high enough to support the
* required disp clk.
*/
-static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
+static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
u32 dispclk)
{
u8 frev, crev;
@@ -767,7 +767,10 @@ static void atombios_crtc_set_dcpll(struct radeon_device
*rdev,
* SetPixelClock provides the dividers
*/
args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
- args.v6.ucPpll = ATOM_DCPLL;
+ if (ASIC_IS_DCE6(rdev))
+ args.v6.ucPpll = ATOM_PPLL0;
+ else
+ args.v6.ucPpll = ATOM_DCPLL;
break;
default:
DRM_ERROR("Unknown table version %d %d\n", frev, crev);
@@ -1521,10 +1524,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
}
-void radeon_atom_dcpll_init(struct radeon_device *rdev)
+void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
{
/* always set DCPLL */
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE6(rdev))
+ atombios_crtc_set_disp_eng_pll(rdev,
rdev->clock.default_dispclk);
+ else if (ASIC_IS_DCE4(rdev)) {
struct radeon_atom_ss ss;
bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
ASIC_INTERNAL_SS_ON_DCPLL,
@@ -1532,7 +1537,7 @@ void radeon_atom_dcpll_init(struct radeon_device *rdev)
if (ss_enabled)
atombios_crtc_program_ss(rdev, ATOM_DISABLE,
ATOM_DCPLL, &ss);
/* XXX: DCE5, make sure voltage, dispclk is high enough */
- atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
+ atombios_crtc_set_disp_eng_pll(rdev,
rdev->clock.default_dispclk);
if (ss_enabled)
atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL,
&ss);
}
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index 9b8dace..beeefb8 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -967,7 +967,7 @@ int radeon_resume_kms(struct drm_device *dev)
/* init dig PHYs, disp eng pll */
if (rdev->is_atom_bios) {
radeon_atom_encoder_init(rdev);
- radeon_atom_dcpll_init(rdev);
+ radeon_atom_disp_eng_pll_init(rdev);
}
/* reset hpd state */
radeon_hpd_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c
b/drivers/gpu/drm/radeon/radeon_display.c
index 1ebcef2..8086c96 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1296,7 +1296,7 @@ int radeon_modeset_init(struct radeon_device *rdev)
/* init dig PHYs, disp eng pll */
if (rdev->is_atom_bios) {
radeon_atom_encoder_init(rdev);
- radeon_atom_dcpll_init(rdev);
+ radeon_atom_disp_eng_pll_init(rdev);
}
/* initialize hpd */
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h
b/drivers/gpu/drm/radeon/radeon_mode.h
index 8a85598..f7eb5d8 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -491,7 +491,7 @@ extern int radeon_dp_get_panel_mode(struct drm_encoder
*encoder,
struct drm_connector *connector);
extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int
action, int panel_mode);
extern void radeon_atom_encoder_init(struct radeon_device *rdev);
-extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
+extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
int action, uint8_t lane_num,
uint8_t lane_set);
--
1.7.7.5
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[PATCH 11/48] drm/radeon/kms/atom: add support for DCE6.x dig transmitters
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_encoders.c | 57
1 files changed, 57 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index b88c460..28b55da 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -703,6 +703,7 @@ union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
};
void
@@ -723,6 +724,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder,
int action, uint8_t
int connector_object_id = 0;
int igp_lane_info = 0;
int dig_encoder = dig->dig_encoder;
+ int hpd_id = RADEON_HPD_NONE;
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
connector = radeon_get_connector_for_encoder_init(encoder);
@@ -738,6 +740,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder,
int action, uint8_t
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
+ hpd_id = radeon_connector->hpd.hpd;
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
connector_object_id =
@@ -1003,6 +1006,60 @@ atombios_dig_transmitter_setup(struct drm_encoder
*encoder, int action, uint8_t
args.v4.acConfig.fDualLinkConnector = 1;
}
break;
+ case 5:
+ args.v5.ucAction = action;
+ if (is_dp)
+ args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
+ else
+ args.v5.usSymClock =
cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (dig->linkb)
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
+ else
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ if (dig->linkb)
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
+ else
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ if (dig->linkb)
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
+ else
+ args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
+ break;
+ }
+ if (is_dp)
+ args.v5.ucLaneNum = dp_lane_count;
+ else if (radeon_encoder->pixel_clock > 165000)
+ args.v5.ucLaneNum = 8;
+ else
+ args.v5.ucLaneNum = 4;
+ args.v5.ucConnObjId = connector_object_id;
+ args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
+
+ if (is_dp && rdev->clock.dp_extclk)
+ args.v5.asConfig.ucPhyClkSrcId =
ENCODER_REFCLK_SRC_EXTCLK;
+ else
+ args.v5.asConfig.ucPhyClkSrcId = pll_id;
+
+ if (is_dp)
+ args.v5.asConfig.ucCoherentMode = 1; /* DP
requires coherent */
+ else if (radeon_encoder->devices &
(ATOM_DEVICE_DFP_SUPPORT)) {
+ if (dig->coherent_mode)
+ args.v5.asConfig.ucCoherentMode = 1;
+ }
+ if (hpd_id == RADEON_HPD_NONE)
+ args.v5.asConfig.ucHPDSel = 0;
+ else
+ args.v5.asConfig.ucHPDSel = hpd_id + 1;
+ args.v5.ucDigEncoderSel = 1 << dig_encoder;
+ args.v5.ucDPLaneSet = lane_set;
+ break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
break;
--
1.7.7.5
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[PATCH 12/48] drm/radeon/kms: DP aux updates for DCE6
From: Alex Deucher DCE6 requires a non-0 value for lpAuxRequest for the ProcessAuxChannelTransaction command table. Setting lpAuxRequest to 0 is a special case used by AsicInit for setting up the aux pads. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_dp.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 191218a..6c62be2 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -63,12 +63,12 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, memset(&args, 0, sizeof(args)); - base = (unsigned char *)rdev->mode_info.atom_context->scratch; + base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); memcpy(base, send, send_bytes); - args.v1.lpAuxRequest = 0; - args.v1.lpDataOut = 16; + args.v1.lpAuxRequest = 0 + 4; + args.v1.lpDataOut = 16 + 4; args.v1.ucDataOutLen = 0; args.v1.ucChannelID = chan->rec.i2c_id; args.v1.ucDelay = delay / 10; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 13/48] drm/radeon/kms: update comments about dig encoders/transmitters
From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_encoders.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 28b55da..45bb2fc 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -479,7 +479,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) * - 2 DIG encoder blocks. * DIG1/2 can drive UNIPHY0/1/2 link A or link B * - * DCE 4.0/5.0 + * DCE 4.0/5.0/6.0 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). * Supports up to 6 digital outputs * - 6 DIG encoder blocks. @@ -495,7 +495,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). * Supports up to 6 digital outputs * - 2 DIG encoder blocks. + * llano * DIG1/2 can drive UNIPHY0/1/2 link A or link B + * ontario + * DIG1 drives UNIPHY0/1/2 link A + * DIG2 drives UNIPHY0/1/2 link B * * Routing * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 14/48] drm/radeon/kms/atom: add support for SI SetVoltage table
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 -
drivers/gpu/drm/radeon/radeon_atombios.c | 39 +
2 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 2081972..03ab8ff 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -236,7 +236,6 @@ void radeon_pm_resume(struct radeon_device *rdev);
void radeon_combios_get_power_modes(struct radeon_device *rdev);
void radeon_atombios_get_power_modes(struct radeon_device *rdev);
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8
voltage_type);
-int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
void rs690_pm_info(struct radeon_device *rdev);
extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index 7e2ba25..afb127c 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -56,6 +56,10 @@ extern void
radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
uint32_t supported_device);
+/* local */
+static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8
voltage_type,
+ u16 voltage_id, u16 *voltage);
+
union atom_supported_devices {
struct _ATOM_SUPPORTED_DEVICES_INFO info;
struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
@@ -2283,6 +2287,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct
radeon_device *rdev,
union pplib_clock_info
*clock_info)
{
u32 sclk, mclk;
+ u16 vddc;
if (rdev->flags & RADEON_IS_IGP) {
if (rdev->family >= CHIP_PALM) {
@@ -2321,11 +2326,18 @@ static bool
radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
}
/* patch up vddc if necessary */
- if
(rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage ==
0xff01) {
- u16 vddc;
-
- if (radeon_atom_get_max_vddc(rdev, &vddc) == 0)
+ switch
(rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
+ case ATOM_VIRTUAL_VOLTAGE_ID0:
+ case ATOM_VIRTUAL_VOLTAGE_ID1:
+ case ATOM_VIRTUAL_VOLTAGE_ID2:
+ case ATOM_VIRTUAL_VOLTAGE_ID3:
+ if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
+
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
+&vddc) == 0)
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
+ break;
+ default:
+ break;
}
if (rdev->flags & RADEON_IS_IGP) {
@@ -2640,6 +2652,7 @@ union set_voltage {
struct _SET_VOLTAGE_PS_ALLOCATION alloc;
struct _SET_VOLTAGE_PARAMETERS v1;
struct _SET_VOLTAGE_PARAMETERS_V2 v2;
+ struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
};
void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8
voltage_type)
@@ -2666,6 +2679,11 @@ void radeon_atom_set_voltage(struct radeon_device *rdev,
u16 voltage_level, u8 v
args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
break;
+ case 3:
+ args.v3.ucVoltageType = voltage_type;
+ args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
+ args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
+ break;
default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
return;
@@ -2674,8 +2692,8 @@ void radeon_atom_set_voltage(struct radeon_device *rdev,
u16 voltage_level, u8 v
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t
*)&args);
}
-int radeon_atom_get_max_vddc(struct radeon_device *rdev,
-u16 *voltage)
+static int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8
voltage_type,
+ u16 voltage_id, u16 *voltage)
{
union set_voltage args;
int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
@@ -2696,6 +2714,15 @@ int radeon_atom_get_max_vddc(struct radeon_device *rdev,
*voltage = le16_to_cpu(args.v2.usVoltageLevel);
break;
+ case 3:
+ args.v3.ucVoltageType = voltage_type;
+ args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
+ args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
+
+ atom_execute_table(rdev->mode_info.atom_context, index,
(uint32_t *)&args);
+
+
[PATCH 15/48] drm/radeon/kms: update power table parsing for SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/radeon_atombios.c | 21 +
2 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 03ab8ff..aaad93d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -977,6 +977,7 @@ enum radeon_int_thermal_type {
THERMAL_TYPE_EVERGREEN,
THERMAL_TYPE_SUMO,
THERMAL_TYPE_NI,
+ THERMAL_TYPE_SI,
};
struct radeon_voltage {
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c
b/drivers/gpu/drm/radeon/radeon_atombios.c
index afb127c..f6e69b8 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1894,6 +1894,8 @@ static const char *pp_lib_thermal_controller_names[] = {
"emc2103",
"Sumo",
"Northern Islands",
+ "Southern Islands",
+ "lm96163",
};
union power_info {
@@ -1910,6 +1912,7 @@ union pplib_clock_info {
struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
+ struct _ATOM_PPLIB_SI_CLOCK_INFO si;
};
union pplib_power_state {
@@ -2167,6 +2170,11 @@ static void
radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
(controller->ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
+ } else if (controller->ucType ==
ATOM_PP_THERMALCONTROLLER_SISLANDS) {
+ DRM_INFO("Internal thermal controller %s fan control\n",
+(controller->ucFanParameters &
+ ATOM_PP_FANPARAMETERS_NOFAN) ? "without" :
"with");
+ rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
} else if ((controller->ucType ==
ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
(controller->ucType ==
@@ -2299,6 +2307,19 @@ static bool
radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
}
+ } else if (ASIC_IS_DCE6(rdev)) {
+ sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
+ sclk |= clock_info->si.ucEngineClockHigh << 16;
+ mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
+ mclk |= clock_info->si.ucMemoryClockHigh << 16;
+ rdev->pm.power_state[state_index].clock_info[mode_index].mclk =
mclk;
+ rdev->pm.power_state[state_index].clock_info[mode_index].sclk =
sclk;
+
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
+ VOLTAGE_SW;
+
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
+ le16_to_cpu(clock_info->si.usVDDC);
+
rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
+ le16_to_cpu(clock_info->si.usVDDCI);
} else if (ASIC_IS_DCE4(rdev)) {
sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
--
1.7.7.5
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[PATCH 16/48] drm/radeon/kms: add support for internal thermal sensor on SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|1 +
drivers/gpu/drm/radeon/radeon_pm.c |4
drivers/gpu/drm/radeon/si.c| 19 +++
drivers/gpu/drm/radeon/sid.h |8
4 files changed, 32 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index aaad93d..c75ccc7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -241,6 +241,7 @@ extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev);
+extern int si_get_temp(struct radeon_device *rdev);
extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
unsigned *tile_split);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index 3575129..a6dbefc 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -474,6 +474,9 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev,
case THERMAL_TYPE_SUMO:
temp = sumo_get_temp(rdev);
break;
+ case THERMAL_TYPE_SI:
+ temp = si_get_temp(rdev);
+ break;
default:
temp = 0;
break;
@@ -514,6 +517,7 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
case THERMAL_TYPE_EVERGREEN:
case THERMAL_TYPE_NI:
case THERMAL_TYPE_SUMO:
+ case THERMAL_TYPE_SI:
rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
if (IS_ERR(rdev->pm.int_hwmon_dev)) {
err = PTR_ERR(rdev->pm.int_hwmon_dev);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 39c64df..3e91429 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -28,6 +28,25 @@
#include "sid.h"
#include "atom.h"
+/* get temperature in millidegrees */
+int si_get_temp(struct radeon_device *rdev)
+{
+ u32 temp;
+ int actual_temp = 0;
+
+ temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
+ CTF_TEMP_SHIFT;
+
+ if (temp & 0x200)
+ actual_temp = 255;
+ else
+ actual_temp = temp & 0x1ff;
+
+ actual_temp = (actual_temp * 1000);
+
+ return actual_temp;
+}
+
/* watermark setup */
static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
struct radeon_crtc *radeon_crtc,
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 962cc17..f565a8f 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -24,6 +24,14 @@
#ifndef SI_H
#define SI_H
+#defineCG_MULT_THERMAL_STATUS 0x714
+#defineASIC_MAX_TEMP(x)((x) <<
0)
+#defineASIC_MAX_TEMP_MASK
0x01ff
+#defineASIC_MAX_TEMP_SHIFT 0
+#defineCTF_TEMP(x) ((x) <<
9)
+#defineCTF_TEMP_MASK
0x0003fe00
+#defineCTF_TEMP_SHIFT 9
+
#define MC_SHARED_CHMAP0x2004
#defineNOOFCHAN_SHIFT 12
#defineNOOFCHAN_MASK
0xf000
--
1.7.7.5
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[PATCH 17/48] drm/radeon/kms: add gpu init support for SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h | 32 ++
drivers/gpu/drm/radeon/si.c | 1005 +++
drivers/gpu/drm/radeon/sid.h| 201
3 files changed, 1238 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c75ccc7..972f167 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1370,6 +1370,37 @@ struct cayman_asic {
struct r100_gpu_lockup lockup;
};
+struct si_asic {
+ unsigned max_shader_engines;
+ unsigned max_pipes_per_simd;
+ unsigned max_tile_pipes;
+ unsigned max_simds_per_se;
+ unsigned max_backends_per_se;
+ unsigned max_texture_channel_caches;
+ unsigned max_gprs;
+ unsigned max_gs_threads;
+ unsigned max_hw_contexts;
+ unsigned sc_prim_fifo_size_frontend;
+ unsigned sc_prim_fifo_size_backend;
+ unsigned sc_hiz_tile_fifo_size;
+ unsigned sc_earlyz_tile_fifo_size;
+
+ unsigned num_shader_engines;
+ unsigned num_tile_pipes;
+ unsigned num_backends_per_se;
+ unsigned backend_disable_mask_per_asic;
+ unsigned backend_map;
+ unsigned num_texture_channel_caches;
+ unsigned mem_max_burst_length_bytes;
+ unsigned mem_row_size_in_kb;
+ unsigned shader_engine_tile_size;
+ unsigned num_gpus;
+ unsigned multi_gpu_tile_size;
+
+ unsigned tile_config;
+ struct r100_gpu_lockup lockup;
+};
+
union radeon_asic_config {
struct r300_asicr300;
struct r100_asicr100;
@@ -1377,6 +1408,7 @@ union radeon_asic_config {
struct rv770_asic rv770;
struct evergreen_asic evergreen;
struct cayman_asic cayman;
+ struct si_asic si;
};
/*
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 3e91429..dd9e7d3 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -28,6 +28,8 @@
#include "sid.h"
#include "atom.h"
+extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
+
/* get temperature in millidegrees */
int si_get_temp(struct radeon_device *rdev)
{
@@ -503,3 +505,1006 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
}
}
+/*
+ * Core functions
+ */
+static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
+ u32 num_tile_pipes,
+ u32 num_backends_per_asic,
+ u32 *backend_disable_mask_per_asic,
+ u32 num_shader_engines)
+{
+ u32 backend_map = 0;
+ u32 enabled_backends_mask = 0;
+ u32 enabled_backends_count = 0;
+ u32 num_backends_per_se;
+ u32 cur_pipe;
+ u32 swizzle_pipe[SI_MAX_PIPES];
+ u32 cur_backend = 0;
+ u32 i;
+ bool force_no_swizzle;
+
+ /* force legal values */
+ if (num_tile_pipes < 1)
+ num_tile_pipes = 1;
+ if (num_tile_pipes > rdev->config.si.max_tile_pipes)
+ num_tile_pipes = rdev->config.si.max_tile_pipes;
+ if (num_shader_engines < 1)
+ num_shader_engines = 1;
+ if (num_shader_engines > rdev->config.si.max_shader_engines)
+ num_shader_engines = rdev->config.si.max_shader_engines;
+ if (num_backends_per_asic < num_shader_engines)
+ num_backends_per_asic = num_shader_engines;
+ if (num_backends_per_asic > (rdev->config.si.max_backends_per_se *
num_shader_engines))
+ num_backends_per_asic = rdev->config.si.max_backends_per_se *
num_shader_engines;
+
+ /* make sure we have the same number of backends per se */
+ num_backends_per_asic = ALIGN(num_backends_per_asic,
num_shader_engines);
+ /* set up the number of backends per se */
+ num_backends_per_se = num_backends_per_asic / num_shader_engines;
+ if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
+ num_backends_per_se = rdev->config.si.max_backends_per_se;
+ num_backends_per_asic = num_backends_per_se *
num_shader_engines;
+ }
+
+ /* create enable mask and count for enabled backends */
+ for (i = 0; i < SI_MAX_BACKENDS; ++i) {
+ if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
+ enabled_backends_mask |= (1 << i);
+ ++enabled_backends_count;
+ }
+ if (enabled_backends_count == num_backends_per_asic)
+ break;
+ }
+
+ /* force the backends mask to match the current number of backends */
+ if (enabled_backends_count != num_backends_per_asic) {
+ u32 this_backend_enabled;
+ u32 shader_engine;
+ u32 backend_per_se;
+
+
[PATCH 18/48] drm/radeon/kms: Add support for SI GPU reset
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 100 ++
drivers/gpu/drm/radeon/sid.h | 70 +
2 files changed, 170 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index dd9e7d3..58ad900 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -29,6 +29,8 @@
#include "atom.h"
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
+extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
/* get temperature in millidegrees */
int si_get_temp(struct radeon_device *rdev)
@@ -1508,3 +1510,101 @@ static void si_gpu_init(struct radeon_device *rdev)
udelay(50);
}
+
+bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
+{
+ u32 srbm_status;
+ u32 grbm_status, grbm_status2;
+ u32 grbm_status_se0, grbm_status_se1;
+ struct r100_gpu_lockup *lockup = &rdev->config.si.lockup;
+ int r;
+
+ srbm_status = RREG32(SRBM_STATUS);
+ grbm_status = RREG32(GRBM_STATUS);
+ grbm_status2 = RREG32(GRBM_STATUS2);
+ grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
+ grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
+ if (!(grbm_status & GUI_ACTIVE)) {
+ r100_gpu_lockup_update(lockup, ring);
+ return false;
+ }
+ /* force CP activities */
+ r = radeon_ring_lock(rdev, ring, 2);
+ if (!r) {
+ /* PACKET2 NOP */
+ radeon_ring_write(ring, 0x8000);
+ radeon_ring_write(ring, 0x8000);
+ radeon_ring_unlock_commit(rdev, ring);
+ }
+ /* XXX deal with CP0,1,2 */
+ ring->rptr = RREG32(ring->rptr_reg);
+ return r100_gpu_cp_is_lockup(rdev, lockup, ring);
+}
+
+static int si_gpu_soft_reset(struct radeon_device *rdev)
+{
+ struct evergreen_mc_save save;
+ u32 grbm_reset = 0;
+
+ if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
+ return 0;
+
+ dev_info(rdev->dev, "GPU softreset \n");
+ dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
+ RREG32(GRBM_STATUS));
+ dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
+ RREG32(GRBM_STATUS2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
+ RREG32(GRBM_STATUS_SE0));
+ dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
+ RREG32(GRBM_STATUS_SE1));
+ dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
+ RREG32(SRBM_STATUS));
+ evergreen_mc_stop(rdev, &save);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ /* Disable CP parsing/prefetching */
+ WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
+
+ /* reset all the gfx blocks */
+ grbm_reset = (SOFT_RESET_CP |
+ SOFT_RESET_CB |
+ SOFT_RESET_DB |
+ SOFT_RESET_GDS |
+ SOFT_RESET_PA |
+ SOFT_RESET_SC |
+ SOFT_RESET_SPI |
+ SOFT_RESET_SX |
+ SOFT_RESET_TC |
+ SOFT_RESET_TA |
+ SOFT_RESET_VGT |
+ SOFT_RESET_IA);
+
+ dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
+ WREG32(GRBM_SOFT_RESET, grbm_reset);
+ (void)RREG32(GRBM_SOFT_RESET);
+ udelay(50);
+ WREG32(GRBM_SOFT_RESET, 0);
+ (void)RREG32(GRBM_SOFT_RESET);
+ /* Wait a little for things to settle down */
+ udelay(50);
+ dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
+ RREG32(GRBM_STATUS));
+ dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
+ RREG32(GRBM_STATUS2));
+ dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
+ RREG32(GRBM_STATUS_SE0));
+ dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
+ RREG32(GRBM_STATUS_SE1));
+ dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
+ RREG32(SRBM_STATUS));
+ evergreen_mc_resume(rdev, &save);
+ return 0;
+}
+
+int si_asic_reset(struct radeon_device *rdev)
+{
+ return si_gpu_soft_reset(rdev);
+}
+
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index cf06dcc..4c6ff1c 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -52,6 +52,8 @@
#define DMIF_ADDR_CONFIG 0xBD4
+#defineSRBM_STATUS 0xE50
+
#defineCC_SYS_RB_BACKEND_DISABLE 0xe80
#defineGC_USER_SYS_RB_BACKEND_DISABLE 0xe84
@@ -102,6 +104,74 @@
#defineGRBM_CNTL
[PATCH 19/48] drm/radeon/kms: add support for MC/VM setup on SI
From: Alex Deucher
Sets up the VM and adds support for the new VM ioctls.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 328 ++
drivers/gpu/drm/radeon/sid.h | 219
2 files changed, 547 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 58ad900..ad91c5f 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1608,3 +1608,331 @@ int si_asic_reset(struct radeon_device *rdev)
return si_gpu_soft_reset(rdev);
}
+/* MC */
+static void si_mc_program(struct radeon_device *rdev)
+{
+ struct evergreen_mc_save save;
+ u32 tmp;
+ int i, j;
+
+ /* Initialize HDP */
+ for (i = 0, j = 0; i < 32; i++, j += 0x18) {
+ WREG32((0x2c14 + j), 0x);
+ WREG32((0x2c18 + j), 0x);
+ WREG32((0x2c1c + j), 0x);
+ WREG32((0x2c20 + j), 0x);
+ WREG32((0x2c24 + j), 0x);
+ }
+ WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
+
+ evergreen_mc_stop(rdev, &save);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ /* Lockout access through VGA aperture*/
+ WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
+ /* Update configuration */
+ WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
+ rdev->mc.vram_start >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
+ rdev->mc.vram_end >> 12);
+ WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
+ rdev->vram_scratch.gpu_addr >> 12);
+ tmp = ((rdev->mc.vram_end >> 24) & 0x) << 16;
+ tmp |= ((rdev->mc.vram_start >> 24) & 0x);
+ WREG32(MC_VM_FB_LOCATION, tmp);
+ /* XXX double check these! */
+ WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
+ WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
+ WREG32(HDP_NONSURFACE_SIZE, 0x3FFF);
+ WREG32(MC_VM_AGP_BASE, 0);
+ WREG32(MC_VM_AGP_TOP, 0x0FFF);
+ WREG32(MC_VM_AGP_BOT, 0x0FFF);
+ if (radeon_mc_wait_for_idle(rdev)) {
+ dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+ }
+ evergreen_mc_resume(rdev, &save);
+ /* we need to own VRAM, so turn off the VGA renderer here
+* to stop it overwriting our objects */
+ rv515_vga_render_disable(rdev);
+}
+
+/* SI MC address space is 40 bits */
+static void si_vram_location(struct radeon_device *rdev,
+struct radeon_mc *mc, u64 base)
+{
+ mc->vram_start = base;
+ if (mc->mc_vram_size > (0xFFULL - base + 1)) {
+ dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
+ mc->real_vram_size = mc->aper_size;
+ mc->mc_vram_size = mc->aper_size;
+ }
+ mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
+ dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
+ mc->mc_vram_size >> 20, mc->vram_start,
+ mc->vram_end, mc->real_vram_size >> 20);
+}
+
+static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
+{
+ u64 size_af, size_bf;
+
+ size_af = ((0xFFULL - mc->vram_end) + mc->gtt_base_align) &
~mc->gtt_base_align;
+ size_bf = mc->vram_start & ~mc->gtt_base_align;
+ if (size_bf > size_af) {
+ if (mc->gtt_size > size_bf) {
+ dev_warn(rdev->dev, "limiting GTT\n");
+ mc->gtt_size = size_bf;
+ }
+ mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) -
mc->gtt_size;
+ } else {
+ if (mc->gtt_size > size_af) {
+ dev_warn(rdev->dev, "limiting GTT\n");
+ mc->gtt_size = size_af;
+ }
+ mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) &
~mc->gtt_base_align;
+ }
+ mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
+ dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
+ mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
+}
+
+static void si_vram_gtt_location(struct radeon_device *rdev,
+struct radeon_mc *mc)
+{
+ if (mc->mc_vram_size > 0xFFC000ULL) {
+ /* leave room for at least 1024M GTT */
+ dev_warn(rdev->dev, "limiting VRAM\n");
+ mc->real_vram_size = 0xFFC000ULL;
+ mc->mc_vram_size = 0xFFC000ULL;
+ }
+ si_vram_location(rdev, &rdev->mc, 0);
+ rdev->mc.gtt_base_align = 0;
+ si_gtt_location(rdev, mc);
+}
+
+static int si_mc_init(struct radeon_device *rdev)
+{
+ u32 tmp;
+ int chansize, numchan;
+
+ /* Get VRAM informations */
+ rdev->mc.vram_is_ddr = t
[PATCH 20/48] drm/radeon/kms: add support for the CONST IB to the CS ioctl
From: Alex Deucher
This adds a new chunk id to the CS ioctl to support the
INDIRECT_BUFFER_CONST packet.
On SI, the CP adds a new engine called the CE (Constant Engine)
which runs simulatenously with the DE (Drawing Engine, formerly
called the ME). This allows the CP to process two related IBs
simultaneously. The CE is tasked with loading the constant data
(constant buffers, resource descriptors, samplers, etc.) while
the DE loads context register state and issues drawing commands.
It's up to the userspace application to sychronize the CE and the
DE using special synchronization packets.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |3 ++
drivers/gpu/drm/radeon/radeon_cs.c | 47 ++
drivers/gpu/drm/radeon/radeon_ring.c |1 +
include/drm/radeon_drm.h |1 +
4 files changed, 52 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 972f167..f467fe5 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -632,6 +632,7 @@ struct radeon_ib {
uint32_t*ptr;
struct radeon_fence *fence;
unsignedvm_id;
+ boolis_const_ib;
};
/*
@@ -836,7 +837,9 @@ struct radeon_cs_parser {
int chunk_ib_idx;
int chunk_relocs_idx;
int chunk_flags_idx;
+ int chunk_const_ib_idx;
struct radeon_ib*ib;
+ struct radeon_ib*const_ib;
void*track;
unsignedfamily;
int parser_error;
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c
b/drivers/gpu/drm/radeon/radeon_cs.c
index d9d9f5a..087bd50 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -170,6 +170,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void
*data)
p->chunk_ib_idx = -1;
p->chunk_relocs_idx = -1;
p->chunk_flags_idx = -1;
+ p->chunk_const_ib_idx = -1;
p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
if (p->chunks_array == NULL) {
return -ENOMEM;
@@ -208,6 +209,12 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void
*data)
if (p->chunks[i].length_dw == 0)
return -EINVAL;
}
+ if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
+ p->chunk_const_ib_idx = i;
+ /* zero length CONST IB isn't useful */
+ if (p->chunks[i].length_dw == 0)
+ return -EINVAL;
+ }
if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
p->chunk_flags_idx = i;
/* zero length flags aren't useful */
@@ -389,6 +396,32 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device
*rdev,
if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
return 0;
+ if ((rdev->family >= CHIP_TAHITI) &&
+ (parser->chunk_const_ib_idx != -1)) {
+ ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
+ if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
+ DRM_ERROR("cs IB CONST too big: %d\n",
ib_chunk->length_dw);
+ return -EINVAL;
+ }
+ r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
+ ib_chunk->length_dw * 4);
+ if (r) {
+ DRM_ERROR("Failed to get const ib !\n");
+ return r;
+ }
+ parser->const_ib->is_const_ib = true;
+ parser->const_ib->length_dw = ib_chunk->length_dw;
+ /* Copy the packet into the IB */
+ if (DRM_COPY_FROM_USER(parser->const_ib->ptr,
ib_chunk->user_ptr,
+ ib_chunk->length_dw * 4)) {
+ return -EFAULT;
+ }
+ r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
+ if (r) {
+ return r;
+ }
+ }
+
ib_chunk = &parser->chunks[parser->chunk_ib_idx];
if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
@@ -424,11 +457,25 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device
*rdev,
if (r) {
DRM_ERROR("Failed to synchronize rings !\n");
}
+
+ if ((rdev->family >= CHIP_TAHITI) &&
+ (parser->chunk_const_ib_idx != -1)) {
+ parser->const_ib->vm_id = vm->id;
+ /* ib pool is bind at 0 in virtual address space to gpu_addr is
the
+
[PATCH 21/48] drm/radeon/kms: add VM CS checker for SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 309 ++
drivers/gpu/drm/radeon/sid.h | 31
2 files changed, 340 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ad91c5f..30b379e 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1882,6 +1882,315 @@ void si_pcie_gart_fini(struct radeon_device *rdev)
radeon_gart_fini(rdev);
}
+/* vm parser */
+static bool si_vm_reg_valid(u32 reg)
+{
+ /* context regs are fine */
+ if (reg >= 0x28000)
+ return true;
+
+ /* check config regs */
+ switch (reg) {
+ case GRBM_GFX_INDEX:
+ case VGT_VTX_VECT_EJECT_REG:
+ case VGT_CACHE_INVALIDATION:
+ case VGT_ESGS_RING_SIZE:
+ case VGT_GSVS_RING_SIZE:
+ case VGT_GS_VERTEX_REUSE:
+ case VGT_PRIMITIVE_TYPE:
+ case VGT_INDEX_TYPE:
+ case VGT_NUM_INDICES:
+ case VGT_NUM_INSTANCES:
+ case VGT_TF_RING_SIZE:
+ case VGT_HS_OFFCHIP_PARAM:
+ case VGT_TF_MEMORY_BASE:
+ case PA_CL_ENHANCE:
+ case PA_SU_LINE_STIPPLE_VALUE:
+ case PA_SC_LINE_STIPPLE_STATE:
+ case PA_SC_ENHANCE:
+ case SQC_CACHES:
+ case SPI_STATIC_THREAD_MGMT_1:
+ case SPI_STATIC_THREAD_MGMT_2:
+ case SPI_STATIC_THREAD_MGMT_3:
+ case SPI_PS_MAX_WAVE_ID:
+ case SPI_CONFIG_CNTL:
+ case SPI_CONFIG_CNTL_1:
+ case TA_CNTL_AUX:
+ return true;
+ default:
+ DRM_ERROR("Invalid register 0x%x in CS\n", reg);
+ return false;
+ }
+}
+
+static int si_vm_packet3_ce_check(struct radeon_device *rdev,
+ u32 *ib, struct radeon_cs_packet *pkt)
+{
+ switch (pkt->opcode) {
+ case PACKET3_NOP:
+ case PACKET3_SET_BASE:
+ case PACKET3_SET_CE_DE_COUNTERS:
+ case PACKET3_LOAD_CONST_RAM:
+ case PACKET3_WRITE_CONST_RAM:
+ case PACKET3_WRITE_CONST_RAM_OFFSET:
+ case PACKET3_DUMP_CONST_RAM:
+ case PACKET3_INCREMENT_CE_COUNTER:
+ case PACKET3_WAIT_ON_DE_COUNTER:
+ case PACKET3_CE_WRITE:
+ break;
+ default:
+ DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int si_vm_packet3_gfx_check(struct radeon_device *rdev,
+ u32 *ib, struct radeon_cs_packet *pkt)
+{
+ u32 idx = pkt->idx + 1;
+ u32 idx_value = ib[idx];
+ u32 start_reg, end_reg, reg, i;
+
+ switch (pkt->opcode) {
+ case PACKET3_NOP:
+ case PACKET3_SET_BASE:
+ case PACKET3_CLEAR_STATE:
+ case PACKET3_INDEX_BUFFER_SIZE:
+ case PACKET3_DISPATCH_DIRECT:
+ case PACKET3_DISPATCH_INDIRECT:
+ case PACKET3_ALLOC_GDS:
+ case PACKET3_WRITE_GDS_RAM:
+ case PACKET3_ATOMIC_GDS:
+ case PACKET3_ATOMIC:
+ case PACKET3_OCCLUSION_QUERY:
+ case PACKET3_SET_PREDICATION:
+ case PACKET3_COND_EXEC:
+ case PACKET3_PRED_EXEC:
+ case PACKET3_DRAW_INDIRECT:
+ case PACKET3_DRAW_INDEX_INDIRECT:
+ case PACKET3_INDEX_BASE:
+ case PACKET3_DRAW_INDEX_2:
+ case PACKET3_CONTEXT_CONTROL:
+ case PACKET3_INDEX_TYPE:
+ case PACKET3_DRAW_INDIRECT_MULTI:
+ case PACKET3_DRAW_INDEX_AUTO:
+ case PACKET3_DRAW_INDEX_IMMD:
+ case PACKET3_NUM_INSTANCES:
+ case PACKET3_DRAW_INDEX_MULTI_AUTO:
+ case PACKET3_STRMOUT_BUFFER_UPDATE:
+ case PACKET3_DRAW_INDEX_OFFSET_2:
+ case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
+ case PACKET3_DRAW_INDEX_INDIRECT_MULTI:
+ case PACKET3_MPEG_INDEX:
+ case PACKET3_WAIT_REG_MEM:
+ case PACKET3_MEM_WRITE:
+ case PACKET3_PFP_SYNC_ME:
+ case PACKET3_SURFACE_SYNC:
+ case PACKET3_EVENT_WRITE:
+ case PACKET3_EVENT_WRITE_EOP:
+ case PACKET3_EVENT_WRITE_EOS:
+ case PACKET3_SET_CONTEXT_REG:
+ case PACKET3_SET_CONTEXT_REG_INDIRECT:
+ case PACKET3_SET_SH_REG:
+ case PACKET3_SET_SH_REG_OFFSET:
+ case PACKET3_INCREMENT_DE_COUNTER:
+ case PACKET3_WAIT_ON_CE_COUNTER:
+ case PACKET3_WAIT_ON_AVAIL_BUFFER:
+ case PACKET3_ME_WRITE:
+ break;
+ case PACKET3_COPY_DATA:
+ if ((idx_value & 0xf00) == 0) {
+ reg = ib[idx + 3] * 4;
+ if (!si_vm_reg_valid(reg))
+ return -EINVAL;
+ }
+ break;
+ case PACKET3_WRITE_DATA:
+ if ((idx_value & 0xf00) == 0) {
+ start_reg = ib[idx + 1] * 4;
+ if (idx_value & 0x1) {
+ if (!si_vm_reg_valid(start_reg))
+ return -EINVAL;
+ } else {
+
[PATCH 22/48] drm/radeon/kms: Only VM CS ioctl is supported on SI (v2)
From: Alex Deucher
v2: avoid double free.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_cs.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c
b/drivers/gpu/drm/radeon/radeon_cs.c
index 087bd50..5e459a3 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -253,6 +253,13 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void
*data)
return -EINVAL;
}
+ /* we only support VM on SI+ */
+ if ((p->rdev->family >= CHIP_TAHITI) &&
+ ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
+ DRM_ERROR("VM required on SI+!\n");
+ return -EINVAL;
+ }
+
if (radeon_cs_get_ring(p, ring, priority))
return -EINVAL;
--
1.7.7.5
___
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 23/48] drm/radeon/kms: add ucode loading for SI
From: Alex Deucher
Currently the driver required 5 sets of ucode:
1. pfp - pre-fetch parser, part of the CP
2. me - micro engine, part of the CP
3. ce - constant engine, part of the CP
4. rlc - interrupt controller
5. mc - memory controller
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h |1 +
drivers/gpu/drm/radeon/si.c | 155 +++
2 files changed, 156 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f467fe5..f1c2f58 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1527,6 +1527,7 @@ struct radeon_device {
const struct firmware *pfp_fw; /* r6/700 PFP firmware */
const struct firmware *rlc_fw; /* r6/700 RLC firmware */
const struct firmware *mc_fw; /* NI MC firmware */
+ const struct firmware *ce_fw; /* SI CE firmware */
struct r600_blit r600_blit;
struct r600_vram_scratch vram_scratch;
int msi_enabled; /* msi enabled */
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 30b379e..0938c21 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -21,6 +21,10 @@
*
* Authors: Alex Deucher
*/
+#include
+#include
+#include
+#include
#include "drmP.h"
#include "radeon.h"
#include "radeon_asic.h"
@@ -28,6 +32,28 @@
#include "sid.h"
#include "atom.h"
+#define SI_PFP_UCODE_SIZE 2144
+#define SI_PM4_UCODE_SIZE 2144
+#define SI_CE_UCODE_SIZE 2144
+#define SI_RLC_UCODE_SIZE 2048
+#define SI_MC_UCODE_SIZE 7769
+
+MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
+MODULE_FIRMWARE("radeon/TAHITI_me.bin");
+MODULE_FIRMWARE("radeon/TAHITI_ce.bin");
+MODULE_FIRMWARE("radeon/TAHITI_mc.bin");
+MODULE_FIRMWARE("radeon/TAHITI_rlc.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_me.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin");
+MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin");
+MODULE_FIRMWARE("radeon/VERDE_pfp.bin");
+MODULE_FIRMWARE("radeon/VERDE_me.bin");
+MODULE_FIRMWARE("radeon/VERDE_ce.bin");
+MODULE_FIRMWARE("radeon/VERDE_mc.bin");
+MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
+
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
@@ -51,6 +77,135 @@ int si_get_temp(struct radeon_device *rdev)
return actual_temp;
}
+static int si_init_microcode(struct radeon_device *rdev)
+{
+ struct platform_device *pdev;
+ const char *chip_name;
+ const char *rlc_chip_name;
+ size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size,
mc_req_size;
+ char fw_name[30];
+ int err;
+
+ DRM_DEBUG("\n");
+
+ pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
+ err = IS_ERR(pdev);
+ if (err) {
+ printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
+ return -EINVAL;
+ }
+
+ switch (rdev->family) {
+ case CHIP_TAHITI:
+ chip_name = "TAHITI";
+ rlc_chip_name = "TAHITI";
+ pfp_req_size = SI_PFP_UCODE_SIZE * 4;
+ me_req_size = SI_PM4_UCODE_SIZE * 4;
+ ce_req_size = SI_CE_UCODE_SIZE * 4;
+ rlc_req_size = SI_RLC_UCODE_SIZE * 4;
+ mc_req_size = SI_MC_UCODE_SIZE * 4;
+ break;
+ case CHIP_PITCAIRN:
+ chip_name = "PITCAIRN";
+ rlc_chip_name = "PITCAIRN";
+ pfp_req_size = SI_PFP_UCODE_SIZE * 4;
+ me_req_size = SI_PM4_UCODE_SIZE * 4;
+ ce_req_size = SI_CE_UCODE_SIZE * 4;
+ rlc_req_size = SI_RLC_UCODE_SIZE * 4;
+ mc_req_size = SI_MC_UCODE_SIZE * 4;
+ break;
+ case CHIP_VERDE:
+ chip_name = "VERDE";
+ rlc_chip_name = "VERDE";
+ pfp_req_size = SI_PFP_UCODE_SIZE * 4;
+ me_req_size = SI_PM4_UCODE_SIZE * 4;
+ ce_req_size = SI_CE_UCODE_SIZE * 4;
+ rlc_req_size = SI_RLC_UCODE_SIZE * 4;
+ mc_req_size = SI_MC_UCODE_SIZE * 4;
+ break;
+ default: BUG();
+ }
+
+ DRM_INFO("Loading %s Microcode\n", chip_name);
+
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
+ err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->pfp_fw->size != pfp_req_size) {
+ printk(KERN_ERR
+ "si_cp: Bogus length %zu in firmware \"%s\"\n",
+ rdev->pfp_fw->size, fw_name);
+ err = -EINVAL;
+ goto out;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "rad
[PATCH 24/48] drm/radeon/kms: add support for MC ucode loading on SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 195 ++
drivers/gpu/drm/radeon/sid.h | 16
2 files changed, 211 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 0938c21..a8789de 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -77,6 +77,201 @@ int si_get_temp(struct radeon_device *rdev)
return actual_temp;
}
+#define TAHITI_IO_MC_REGS_SIZE 36
+
+static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
+ {0x006f, 0x03044000},
+ {0x0070, 0x0480c018},
+ {0x0071, 0x0040},
+ {0x0072, 0x0100},
+ {0x0074, 0x00ff},
+ {0x0075, 0x00143400},
+ {0x0076, 0x08ec0800},
+ {0x0077, 0x04cc},
+ {0x0079, 0x},
+ {0x007a, 0x21000409},
+ {0x007c, 0x},
+ {0x007d, 0xe800},
+ {0x007e, 0x044408a8},
+ {0x007f, 0x0003},
+ {0x0080, 0x},
+ {0x0081, 0x0100},
+ {0x0082, 0x0200},
+ {0x0083, 0x},
+ {0x0084, 0xe3f3e4f4},
+ {0x0085, 0x00052024},
+ {0x0087, 0x},
+ {0x0088, 0x66036603},
+ {0x0089, 0x0100},
+ {0x008b, 0x1c0a},
+ {0x008c, 0xff01},
+ {0x008e, 0xefff},
+ {0x008f, 0xfff3efff},
+ {0x0090, 0xfff3efbf},
+ {0x0094, 0x00101101},
+ {0x0095, 0x0fff},
+ {0x0096, 0x00116fff},
+ {0x0097, 0x6001},
+ {0x0098, 0x1001},
+ {0x0099, 0x6000},
+ {0x009a, 0x1000},
+ {0x009f, 0x00a77400}
+};
+
+static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
+ {0x006f, 0x03044000},
+ {0x0070, 0x0480c018},
+ {0x0071, 0x0040},
+ {0x0072, 0x0100},
+ {0x0074, 0x00ff},
+ {0x0075, 0x00143400},
+ {0x0076, 0x08ec0800},
+ {0x0077, 0x04cc},
+ {0x0079, 0x},
+ {0x007a, 0x21000409},
+ {0x007c, 0x},
+ {0x007d, 0xe800},
+ {0x007e, 0x044408a8},
+ {0x007f, 0x0003},
+ {0x0080, 0x},
+ {0x0081, 0x0100},
+ {0x0082, 0x0200},
+ {0x0083, 0x},
+ {0x0084, 0xe3f3e4f4},
+ {0x0085, 0x00052024},
+ {0x0087, 0x},
+ {0x0088, 0x66036603},
+ {0x0089, 0x0100},
+ {0x008b, 0x1c0a},
+ {0x008c, 0xff01},
+ {0x008e, 0xefff},
+ {0x008f, 0xfff3efff},
+ {0x0090, 0xfff3efbf},
+ {0x0094, 0x00101101},
+ {0x0095, 0x0fff},
+ {0x0096, 0x00116fff},
+ {0x0097, 0x6001},
+ {0x0098, 0x1001},
+ {0x0099, 0x6000},
+ {0x009a, 0x1000},
+ {0x009f, 0x00a47400}
+};
+
+static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
+ {0x006f, 0x03044000},
+ {0x0070, 0x0480c018},
+ {0x0071, 0x0040},
+ {0x0072, 0x0100},
+ {0x0074, 0x00ff},
+ {0x0075, 0x00143400},
+ {0x0076, 0x08ec0800},
+ {0x0077, 0x04cc},
+ {0x0079, 0x},
+ {0x007a, 0x21000409},
+ {0x007c, 0x},
+ {0x007d, 0xe800},
+ {0x007e, 0x044408a8},
+ {0x007f, 0x0003},
+ {0x0080, 0x},
+ {0x0081, 0x0100},
+ {0x0082, 0x0200},
+ {0x0083, 0x},
+ {0x0084, 0xe3f3e4f4},
+ {0x0085, 0x00052024},
+ {0x0087, 0x},
+ {0x0088, 0x66036603},
+ {0x0089, 0x0100},
+ {0x008b, 0x1c0a},
+ {0x008c, 0xff01},
+ {0x008e, 0xefff},
+ {0x008f, 0xfff3efff},
+ {0x0090, 0xfff3efbf},
+ {0x0094, 0x00101101},
+ {0x0095, 0x0fff},
+ {0x0096, 0x00116fff},
+ {0x0097, 0x6001},
+ {0x0098, 0x1001},
+ {0x0099, 0x6000},
+ {0x009a, 0x1000},
+ {0x009f, 0x00a37400}
+};
+
+/* ucode loading */
+static int si_mc_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ u32 running, blackout = 0;
+ u32 *io_mc_regs;
+ int i, ucode_size, regs_size;
+
+ if (!rdev->mc_fw)
+ return -EINVAL;
+
+ switch (rdev->family) {
+ case CHIP_TAHITI:
+ io_mc_regs = (u32 *)&tahiti_io_mc_regs;
+ ucode_size = SI_MC_UCODE_SIZE;
+ regs_size = TAHITI_IO_MC_REGS_SIZE;
+ break;
+ case CHIP_PITCAIRN:
+ io_mc_regs = (u32 *)&p
[PATCH 25/48] drm/radeon/kms: add support for CP setup on SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/Makefile |2 +-
drivers/gpu/drm/radeon/si.c | 267 ++
drivers/gpu/drm/radeon/si_blit_shaders.c | 252
drivers/gpu/drm/radeon/si_blit_shaders.h | 32
drivers/gpu/drm/radeon/sid.h | 55 ++
5 files changed, 607 insertions(+), 1 deletions(-)
create mode 100644 drivers/gpu/drm/radeon/si_blit_shaders.c
create mode 100644 drivers/gpu/drm/radeon/si_blit_shaders.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index fa3e704..9d83729 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -71,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
evergreen.o evergreen_cs.o evergreen_blit_shaders.o
evergreen_blit_kms.o \
radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \
- radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o
+ radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o si_blit_shaders.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a8789de..a471a80 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -31,6 +31,7 @@
#include "radeon_drm.h"
#include "sid.h"
#include "atom.h"
+#include "si_blit_shaders.h"
#define SI_PFP_UCODE_SIZE 2144
#define SI_PM4_UCODE_SIZE 2144
@@ -1861,6 +1862,272 @@ static void si_gpu_init(struct radeon_device *rdev)
udelay(50);
}
+/*
+ * CP.
+ */
+static void si_cp_enable(struct radeon_device *rdev, bool enable)
+{
+ if (enable)
+ WREG32(CP_ME_CNTL, 0);
+ else {
+ radeon_ttm_set_active_vram_size(rdev,
rdev->mc.visible_vram_size);
+ WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
+ WREG32(SCRATCH_UMSK, 0);
+ }
+ udelay(50);
+}
+
+static int si_cp_load_microcode(struct radeon_device *rdev)
+{
+ const __be32 *fw_data;
+ int i;
+
+ if (!rdev->me_fw || !rdev->pfp_fw)
+ return -EINVAL;
+
+ si_cp_enable(rdev, false);
+
+ /* PFP */
+ fw_data = (const __be32 *)rdev->pfp_fw->data;
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ for (i = 0; i < SI_PFP_UCODE_SIZE; i++)
+ WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+
+ /* CE */
+ fw_data = (const __be32 *)rdev->ce_fw->data;
+ WREG32(CP_CE_UCODE_ADDR, 0);
+ for (i = 0; i < SI_CE_UCODE_SIZE; i++)
+ WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_CE_UCODE_ADDR, 0);
+
+ /* ME */
+ fw_data = (const __be32 *)rdev->me_fw->data;
+ WREG32(CP_ME_RAM_WADDR, 0);
+ for (i = 0; i < SI_PM4_UCODE_SIZE; i++)
+ WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
+ WREG32(CP_ME_RAM_WADDR, 0);
+
+ WREG32(CP_PFP_UCODE_ADDR, 0);
+ WREG32(CP_CE_UCODE_ADDR, 0);
+ WREG32(CP_ME_RAM_WADDR, 0);
+ WREG32(CP_ME_RAM_RADDR, 0);
+ return 0;
+}
+
+static int si_cp_start(struct radeon_device *rdev)
+{
+ struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
+ int r, i;
+
+ r = radeon_ring_lock(rdev, ring, 7 + 4);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ return r;
+ }
+ /* init the CP */
+ radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
+ radeon_ring_write(ring, 0x1);
+ radeon_ring_write(ring, 0x0);
+ radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1);
+ radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 0);
+
+ /* init the CE partitions */
+ radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
+ radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
+ radeon_ring_write(ring, 0xc000);
+ radeon_ring_write(ring, 0xe000);
+ radeon_ring_unlock_commit(rdev, ring);
+
+ si_cp_enable(rdev, true);
+
+ r = radeon_ring_lock(rdev, ring, si_default_size + 10);
+ if (r) {
+ DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+ return r;
+ }
+
+ /* setup clear context state */
+ radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+ radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
+
+ for (i = 0; i < si_default_size; i++)
+ radeon_ring_write(ring, si_default_state[i]);
+
+ radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
+ radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
+
+ /* set clear con
[PATCH 26/48] drm/radeon/kms: add IB and fence dispatch functions for SI
From: Alex Deucher
Support both IBs (DE) and CONST IBs (CE).
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 78 ++
drivers/gpu/drm/radeon/sid.h | 65 +++
2 files changed, 143 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a471a80..408119a 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1863,6 +1863,84 @@ static void si_gpu_init(struct radeon_device *rdev)
}
/*
+ * GPU scratch registers helpers function.
+ */
+static void si_scratch_init(struct radeon_device *rdev)
+{
+ int i;
+
+ rdev->scratch.num_reg = 7;
+ rdev->scratch.reg_base = SCRATCH_REG0;
+ for (i = 0; i < rdev->scratch.num_reg; i++) {
+ rdev->scratch.free[i] = true;
+ rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
+ }
+}
+
+void si_fence_ring_emit(struct radeon_device *rdev,
+ struct radeon_fence *fence)
+{
+ struct radeon_ring *ring = &rdev->ring[fence->ring];
+ u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+
+ /* flush read cache over gart */
+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)
>> 2);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+ radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
+ PACKET3_TC_ACTION_ENA |
+ PACKET3_SH_KCACHE_ACTION_ENA |
+ PACKET3_SH_ICACHE_ACTION_ENA);
+ radeon_ring_write(ring, 0x);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 10); /* poll interval */
+ /* EVENT_WRITE_EOP - flush caches, send int */
+ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+ radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
EVENT_INDEX(5));
+ radeon_ring_write(ring, addr & 0x);
+ radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) |
INT_SEL(2));
+ radeon_ring_write(ring, fence->seq);
+ radeon_ring_write(ring, 0);
+}
+
+/*
+ * IB stuff
+ */
+void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+ struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
+ u32 header;
+
+ if (ib->is_const_ib)
+ header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
+ else
+ header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+
+ radeon_ring_write(ring, header);
+ radeon_ring_write(ring,
+#ifdef __BIG_ENDIAN
+ (2 << 0) |
+#endif
+ (ib->gpu_addr & 0xFFFC));
+ radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0x);
+ radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
+
+ /* flush read cache over gart for this vmid */
+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+ radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START)
>> 2);
+ radeon_ring_write(ring, ib->vm_id);
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+ radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
+ PACKET3_TC_ACTION_ENA |
+ PACKET3_SH_KCACHE_ACTION_ENA |
+ PACKET3_SH_ICACHE_ACTION_ENA);
+ radeon_ring_write(ring, 0x);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 10); /* poll interval */
+}
+
+/*
* CP.
*/
static void si_cp_enable(struct radeon_device *rdev, bool enable)
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 7e08f08..904c4fd 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -294,6 +294,8 @@
#defineCP_PFP_HALT (1 <<
26)
#defineCP_ME_HALT (1 <<
28)
+#defineCP_COHER_CNTL2 0x85E8
+
#defineCP_RB2_RPTR 0x86f8
#defineCP_RB1_RPTR 0x86fc
#defineCP_RB0_RPTR 0x8700
@@ -511,6 +513,45 @@
#defineCP_DEBUG0xC1FC
+#define VGT_EVENT_INITIATOR 0x28a90
+# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
+# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
+# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
+# define CACHE_FLUSH_TS (4 << 0)
+# define CACHE_FLUSH (6 << 0)
+# define CS_PARTIAL_FLUSH (7 << 0)
+# define VGT_STREAMOUT_RESET
[PATCH 27/48] drm/radeon/kms: Add support for RLC init on SI
From: Alex Deucher
RLC handles the interrupt controller and other tasks
on the GPU.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h | 13
drivers/gpu/drm/radeon/si.c | 132 +++
drivers/gpu/drm/radeon/sid.h| 17 +
3 files changed, 162 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f1c2f58..8275b41 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -772,6 +772,18 @@ struct r600_blit {
void r600_blit_suspend(struct radeon_device *rdev);
+/*
+ * SI RLC stuff
+ */
+struct si_rlc {
+ /* for power gating */
+ struct radeon_bo*save_restore_obj;
+ uint64_tsave_restore_gpu_addr;
+ /* for clear state */
+ struct radeon_bo*clear_state_obj;
+ uint64_tclear_state_gpu_addr;
+};
+
int radeon_ib_get(struct radeon_device *rdev, int ring,
struct radeon_ib **ib, unsigned size);
void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
@@ -1532,6 +1544,7 @@ struct radeon_device {
struct r600_vram_scratch vram_scratch;
int msi_enabled; /* msi enabled */
struct r600_ih ih; /* r6/700 interrupt ring */
+ struct si_rlc rlc;
struct work_struct hotplug_work;
int num_crtc; /* number of crtcs */
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 408119a..4252cd0 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2940,3 +2940,135 @@ void si_vm_tlb_flush(struct radeon_device *rdev, struct
radeon_vm *vm)
WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
}
+/*
+ * RLC
+ */
+static void si_rlc_fini(struct radeon_device *rdev)
+{
+ int r;
+
+ /* save restore block */
+ if (rdev->rlc.save_restore_obj) {
+ r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n",
r);
+ radeon_bo_unpin(rdev->rlc.save_restore_obj);
+ radeon_bo_unreserve(rdev->rlc.save_restore_obj);
+
+ radeon_bo_unref(&rdev->rlc.save_restore_obj);
+ rdev->rlc.save_restore_obj = NULL;
+ }
+
+ /* clear state block */
+ if (rdev->rlc.clear_state_obj) {
+ r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
+ if (unlikely(r != 0))
+ dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n",
r);
+ radeon_bo_unpin(rdev->rlc.clear_state_obj);
+ radeon_bo_unreserve(rdev->rlc.clear_state_obj);
+
+ radeon_bo_unref(&rdev->rlc.clear_state_obj);
+ rdev->rlc.clear_state_obj = NULL;
+ }
+}
+
+static int si_rlc_init(struct radeon_device *rdev)
+{
+ int r;
+
+ /* save restore block */
+ if (rdev->rlc.save_restore_obj == NULL) {
+ r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE,
true,
+ RADEON_GEM_DOMAIN_VRAM,
&rdev->rlc.save_restore_obj);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n",
r);
+ return r;
+ }
+ }
+
+ r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
+ if (unlikely(r != 0)) {
+ si_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->rlc.save_restore_gpu_addr);
+ if (r) {
+ radeon_bo_unreserve(rdev->rlc.save_restore_obj);
+ dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r);
+ si_rlc_fini(rdev);
+ return r;
+ }
+
+ /* clear state block */
+ if (rdev->rlc.clear_state_obj == NULL) {
+ r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE,
true,
+ RADEON_GEM_DOMAIN_VRAM,
&rdev->rlc.clear_state_obj);
+ if (r) {
+ dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r);
+ si_rlc_fini(rdev);
+ return r;
+ }
+ }
+ r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
+ if (unlikely(r != 0)) {
+ si_rlc_fini(rdev);
+ return r;
+ }
+ r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
+ &rdev->rlc.clear_state_gpu_addr);
+ if (r) {
+
+ radeon_bo_unreserve(rdev->rlc.clear_state_obj);
+ dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r);
+ si_rlc_fini(rdev);
+ return r;
+ }
+
+ re
[PATCH 28/48] drm/radeon/kms: add support for interrupts on SI
From: Alex Deucher
This is mostly identical to evergreen/ni, however
there are some additional fields in the IV vector
for RINGID and VMID.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/r600.c |4 +-
drivers/gpu/drm/radeon/si.c | 721 +
drivers/gpu/drm/radeon/sid.h | 158 +
3 files changed, 881 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 5eb2382..924b687 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2778,7 +2778,7 @@ void r600_ih_ring_init(struct radeon_device *rdev,
unsigned ring_size)
rdev->ih.rptr = 0;
}
-static int r600_ih_ring_alloc(struct radeon_device *rdev)
+int r600_ih_ring_alloc(struct radeon_device *rdev)
{
int r;
@@ -2814,7 +2814,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev)
return 0;
}
-static void r600_ih_ring_fini(struct radeon_device *rdev)
+void r600_ih_ring_fini(struct radeon_device *rdev)
{
int r;
if (rdev->ih.ring_obj) {
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 4252cd0..6aecbf5 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -55,6 +55,8 @@ MODULE_FIRMWARE("radeon/VERDE_ce.bin");
MODULE_FIRMWARE("radeon/VERDE_mc.bin");
MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
+extern int r600_ih_ring_alloc(struct radeon_device *rdev);
+extern void r600_ih_ring_fini(struct radeon_device *rdev);
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
@@ -3072,3 +3074,722 @@ static int si_rlc_resume(struct radeon_device *rdev)
return 0;
}
+static void si_enable_interrupts(struct radeon_device *rdev)
+{
+ u32 ih_cntl = RREG32(IH_CNTL);
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+
+ ih_cntl |= ENABLE_INTR;
+ ih_rb_cntl |= IH_RB_ENABLE;
+ WREG32(IH_CNTL, ih_cntl);
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ rdev->ih.enabled = true;
+}
+
+static void si_disable_interrupts(struct radeon_device *rdev)
+{
+ u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
+ u32 ih_cntl = RREG32(IH_CNTL);
+
+ ih_rb_cntl &= ~IH_RB_ENABLE;
+ ih_cntl &= ~ENABLE_INTR;
+ WREG32(IH_RB_CNTL, ih_rb_cntl);
+ WREG32(IH_CNTL, ih_cntl);
+ /* set rptr, wptr to 0 */
+ WREG32(IH_RB_RPTR, 0);
+ WREG32(IH_RB_WPTR, 0);
+ rdev->ih.enabled = false;
+ rdev->ih.wptr = 0;
+ rdev->ih.rptr = 0;
+}
+
+static void si_disable_interrupt_state(struct radeon_device *rdev)
+{
+ u32 tmp;
+
+ WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
+ WREG32(CP_INT_CNTL_RING1, 0);
+ WREG32(CP_INT_CNTL_RING2, 0);
+ WREG32(GRBM_INT_CNTL, 0);
+ WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+ WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+ if (rdev->num_crtc >= 4) {
+ WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+ WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+ }
+ if (rdev->num_crtc >= 6) {
+ WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+ WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ }
+
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
+ if (rdev->num_crtc >= 4) {
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
+ }
+ if (rdev->num_crtc >= 6) {
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ }
+
+ WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+
+ tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD1_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD2_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD3_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD4_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD5_INT_CONTROL, tmp);
+ tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD6_INT_CONTROL, tmp);
+
+}
+
+static int si_irq_init(struct radeon_device *rdev)
+{
+ int ret = 0;
+ int rb_bufsz;
+ u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
+
+ /* allocate ring */
+ ret = r600_ih_ring_alloc(rdev);
+ if (ret)
+
[PATCH 29/48] drm/radeon/kms: fill in startup/shutdown callbacks for SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/si.c | 329 +++
1 files changed, 329 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 6aecbf5..4c0d8d2 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3468,6 +3468,12 @@ static void si_irq_suspend(struct radeon_device *rdev)
si_rlc_stop(rdev);
}
+static void si_irq_fini(struct radeon_device *rdev)
+{
+ si_irq_suspend(rdev);
+ r600_ih_ring_fini(rdev);
+}
+
static inline u32 si_get_ih_wptr(struct radeon_device *rdev)
{
u32 wptr, tmp;
@@ -3793,3 +3799,326 @@ restart_ih:
return IRQ_HANDLED;
}
+/*
+ * startup/shutdown callbacks
+ */
+static int si_startup(struct radeon_device *rdev)
+{
+ struct radeon_ring *ring;
+ int r;
+
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
+ !rdev->rlc_fw || !rdev->mc_fw) {
+ r = si_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
+ r = si_mc_load_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load MC firmware!\n");
+ return r;
+ }
+
+ r = r600_vram_scratch_init(rdev);
+ if (r)
+ return r;
+
+ si_mc_program(rdev);
+ r = si_pcie_gart_enable(rdev);
+ if (r)
+ return r;
+ si_gpu_init(rdev);
+
+#if 0
+ r = evergreen_blit_init(rdev);
+ if (r) {
+ r600_blit_fini(rdev);
+ rdev->asic->copy = NULL;
+ dev_warn(rdev->dev, "failed blitter (%d) falling back to
memcpy\n", r);
+ }
+#endif
+ /* allocate rlc buffers */
+ r = si_rlc_init(rdev);
+ if (r) {
+ DRM_ERROR("Failed to init rlc BOs!\n");
+ return r;
+ }
+
+ /* allocate wb buffer */
+ r = radeon_wb_init(rdev);
+ if (r)
+ return r;
+
+ r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
+ return r;
+ }
+
+ r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
+ return r;
+ }
+
+ r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
+ if (r) {
+ dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
+ return r;
+ }
+
+ /* Enable IRQ */
+ r = si_irq_init(rdev);
+ if (r) {
+ DRM_ERROR("radeon: IH init failed (%d).\n", r);
+ radeon_irq_kms_fini(rdev);
+ return r;
+ }
+ si_irq_set(rdev);
+
+ ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
RADEON_WB_CP_RPTR_OFFSET,
+CP_RB0_RPTR, CP_RB0_WPTR,
+0, 0xf, RADEON_CP_PACKET2);
+ if (r)
+ return r;
+
+ ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
RADEON_WB_CP1_RPTR_OFFSET,
+CP_RB1_RPTR, CP_RB1_WPTR,
+0, 0xf, RADEON_CP_PACKET2);
+ if (r)
+ return r;
+
+ ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
+ r = radeon_ring_init(rdev, ring, ring->ring_size,
RADEON_WB_CP2_RPTR_OFFSET,
+CP_RB2_RPTR, CP_RB2_WPTR,
+0, 0xf, RADEON_CP_PACKET2);
+ if (r)
+ return r;
+
+ r = si_cp_load_microcode(rdev);
+ if (r)
+ return r;
+ r = si_cp_resume(rdev);
+ if (r)
+ return r;
+
+ r = radeon_ib_pool_start(rdev);
+ if (r)
+ return r;
+
+ r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX,
&rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
+ if (r) {
+ DRM_ERROR("radeon: failed testing IB (%d) on CP ring 0\n", r);
+ rdev->accel_working = false;
+ return r;
+ }
+
+ r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX,
&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]);
+ if (r) {
+ DRM_ERROR("radeon: failed testing IB (%d) on CP ring 1\n", r);
+ rdev->accel_working = false;
+ return r;
+ }
+
+ r = radeon_ib_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX,
&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]);
+ if (r) {
+ DRM_ERROR("radeon: failed testing IB (%d) on CP ring 2\n", r);
+ rdev->accel_working = false;
+ return r;
+ }
+
+ r = rad
[PATCH 30/48] drm/radeon/kms: add support for compute rings in CS ioctl on SI
From: Alex Deucher
Very basic implementation for picking the ring priority.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_cs.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c
b/drivers/gpu/drm/radeon/radeon_cs.c
index 5e459a3..5cac832 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -103,8 +103,13 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p,
u32 ring, s32 priority
p->ring = RADEON_RING_TYPE_GFX_INDEX;
break;
case RADEON_CS_RING_COMPUTE:
- /* for now */
- p->ring = RADEON_RING_TYPE_GFX_INDEX;
+ if (p->rdev->family >= CHIP_TAHITI) {
+ if (p->priority > 0)
+ p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
+ else
+ p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
+ } else
+ p->ring = RADEON_RING_TYPE_GFX_INDEX;
break;
}
return 0;
--
1.7.7.5
___
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dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 31/48] drm/radeon/kms: add radeon_asic struct for SI
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 110 ++
drivers/gpu/drm/radeon/radeon_asic.h | 22 +++
2 files changed, 132 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index 479c89e..f24e145 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1408,6 +1408,108 @@ static struct radeon_asic cayman_asic = {
},
};
+static const struct radeon_vm_funcs si_vm_funcs = {
+ .init = &si_vm_init,
+ .fini = &si_vm_fini,
+ .bind = &si_vm_bind,
+ .unbind = &si_vm_unbind,
+ .tlb_flush = &si_vm_tlb_flush,
+ .page_flags = &cayman_vm_page_flags,
+ .set_page = &cayman_vm_set_page,
+};
+
+static struct radeon_asic si_asic = {
+ .init = &si_init,
+ .fini = &si_fini,
+ .suspend = &si_suspend,
+ .resume = &si_resume,
+ .gpu_is_lockup = &si_gpu_is_lockup,
+ .asic_reset = &si_asic_reset,
+ .vga_set_state = &r600_vga_set_state,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+ .gart = {
+ .tlb_flush = &si_pcie_gart_tlb_flush,
+ .set_page = &rs600_gart_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = {
+ .ib_execute = &si_ring_ib_execute,
+ .ib_parse = &si_ib_parse,
+ .emit_fence = &si_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ },
+ [CAYMAN_RING_TYPE_CP1_INDEX] = {
+ .ib_execute = &si_ring_ib_execute,
+ .ib_parse = &si_ib_parse,
+ .emit_fence = &si_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ },
+ [CAYMAN_RING_TYPE_CP2_INDEX] = {
+ .ib_execute = &si_ring_ib_execute,
+ .ib_parse = &si_ib_parse,
+ .emit_fence = &si_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = NULL,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ }
+ },
+ .irq = {
+ .set = &si_irq_set,
+ .process = &si_irq_process,
+ },
+ .display = {
+ .bandwidth_update = &dce6_bandwidth_update,
+ .get_vblank_counter = &evergreen_get_vblank_counter,
+ .wait_for_vblank = &dce4_wait_for_vblank,
+ },
+ .copy = {
+ .blit = NULL,
+ .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ .dma = NULL,
+ .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ .copy = NULL,
+ .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ },
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
+ .hpd = {
+ .init = &evergreen_hpd_init,
+ .fini = &evergreen_hpd_fini,
+ .sense = &evergreen_hpd_sense,
+ .set_polarity = &evergreen_hpd_set_polarity,
+ },
+ .pm = {
+ .misc = &evergreen_pm_misc,
+ .prepare = &evergreen_pm_prepare,
+ .finish = &evergreen_pm_finish,
+ .init_profile = &sumo_pm_init_profile,
+ .get_dynpm_state = &r600_pm_get_dynpm_state,
+ .get_engine_clock = &radeon_atom_get_engine_clock,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .get_memory_clock = &radeon_atom_get_memory_clock,
+ .set_memory_clock = &radeon_atom_set_memory_clock,
+ .get_pcie_lanes = NULL,
+ .set_pcie_lanes = NULL,
+ .set_clock_gating = NULL,
+ },
+ .pflip = {
+ .pre_page_flip = &evergreen_pre_page_flip,
+ .page_flip = &evergreen_page_flip,
+ .post_page_flip = &evergreen_post_page_flip,
+ },
+};
+
int radeon_asic_init(struct radeon_device *rdev)
{
radeon_register_accessor_init(rdev);
@@ -1525,6 +1627,14 @@ int radeon_asic_init(struct radeon_device *rdev)
rdev->num_crtc = 6;
rdev->vm_manager.funcs = &cayman_vm_funcs;
break;
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ case
[PATCH 32/48] drm/radeon: Update radeon_info_ioctl for SI. (v2)
From: Michel Dänzer v2: agd5f: add new MAX_PIPES param Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_kms.c | 21 - 1 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 72d70eb..3c2628b 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -171,7 +171,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) value = rdev->accel_working; break; case RADEON_INFO_TILING_CONFIG: - if (rdev->family >= CHIP_CAYMAN) + if (rdev->family >= CHIP_TAHITI) + value = rdev->config.si.tile_config; + else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.tile_config; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.tile_config; @@ -210,7 +212,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) value = rdev->clock.spll.reference_freq * 10; break; case RADEON_INFO_NUM_BACKENDS: - if (rdev->family >= CHIP_CAYMAN) + if (rdev->family >= CHIP_TAHITI) + value = rdev->config.si.max_backends_per_se * + rdev->config.si.max_shader_engines; + else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines; else if (rdev->family >= CHIP_CEDAR) @@ -224,7 +229,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) } break; case RADEON_INFO_NUM_TILE_PIPES: - if (rdev->family >= CHIP_CAYMAN) + if (rdev->family >= CHIP_TAHITI) + value = rdev->config.si.max_tile_pipes; + else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_tile_pipes; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_tile_pipes; @@ -240,7 +247,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) value = 1; break; case RADEON_INFO_BACKEND_MAP: - if (rdev->family >= CHIP_CAYMAN) + if (rdev->family >= CHIP_TAHITI) + value = rdev->config.si.backend_map; + else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.backend_map; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.backend_map; @@ -265,7 +274,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) value = RADEON_IB_VM_MAX_SIZE; break; case RADEON_INFO_MAX_PIPES: - if (rdev->family >= CHIP_CAYMAN) + if (rdev->family >= CHIP_TAHITI) + value = rdev->config.si.max_pipes_per_simd; + else if (rdev->family >= CHIP_CAYMAN) value = rdev->config.cayman.max_pipes_per_simd; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_pipes; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 33/48] drm/radeon/kms: Add SI pci ids
From: Alex Deucher
Signed-off-by: Alex Deucher
---
include/drm/drm_pciids.h | 38 ++
1 files changed, 38 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 14b6cd0..1ab5270 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -202,11 +202,49 @@
{0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x677B, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TAHITI|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6840, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6841, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6842, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6843, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6849, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x684C, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6850, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6858, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_TURKS|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6859, P
[PATCH 34/48] drm/radeon/kms: add trinity (TN) chip family
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon.h|4 +++-
drivers/gpu/drm/radeon/radeon_device.c |1 +
drivers/gpu/drm/radeon/radeon_family.h |1 +
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8275b41..138b952 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1688,7 +1688,9 @@ void r100_pll_errata_after_index(struct radeon_device
*rdev);
#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
(rdev->flags & RADEON_IS_IGP))
#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
-#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_TAHITI))
+#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
+#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
+(rdev->flags & RADEON_IS_IGP))
/*
* BIOS helpers.
diff --git a/drivers/gpu/drm/radeon/radeon_device.c
b/drivers/gpu/drm/radeon/radeon_device.c
index beeefb8..ea7df16 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -89,6 +89,7 @@ static const char radeon_family_name[][16] = {
"TURKS",
"CAICOS",
"CAYMAN",
+ "ARUBA",
"TAHITI",
"PITCAIRN",
"VERDE",
diff --git a/drivers/gpu/drm/radeon/radeon_family.h
b/drivers/gpu/drm/radeon/radeon_family.h
index 71d626a..d1fafea 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -87,6 +87,7 @@ enum radeon_family {
CHIP_TURKS,
CHIP_CAICOS,
CHIP_CAYMAN,
+ CHIP_ARUBA,
CHIP_TAHITI,
CHIP_PITCAIRN,
CHIP_VERDE,
--
1.7.7.5
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[PATCH 35/48] drm/radeon/kms: no support for internal thermal sensor on TN yet
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_pm.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c
b/drivers/gpu/drm/radeon/radeon_pm.c
index a6dbefc..caa55d6 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -518,6 +518,9 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
case THERMAL_TYPE_NI:
case THERMAL_TYPE_SUMO:
case THERMAL_TYPE_SI:
+ /* No support for TN yet */
+ if (rdev->family == CHIP_ARUBA)
+ return err;
rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
if (IS_ERR(rdev->pm.int_hwmon_dev)) {
err = PTR_ERR(rdev->pm.int_hwmon_dev);
--
1.7.7.5
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[PATCH 36/48] drm/radeon/kms: DCE6.1 watermark updates for TN
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c |2 +-
drivers/gpu/drm/radeon/si.c|8 ++--
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 466db41..6c2b666 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -581,7 +581,7 @@ static u32 evergreen_line_buffer_adjust(struct
radeon_device *rdev,
return 0;
}
-static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
+u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
{
u32 tmp = RREG32(MC_SHARED_CHMAP);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 4c0d8d2..d773ea9 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -60,6 +60,7 @@ extern void r600_ih_ring_fini(struct radeon_device *rdev);
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_mc_stop(struct radeon_device *rdev, struct
evergreen_mc_save *save);
extern void evergreen_mc_resume(struct radeon_device *rdev, struct
evergreen_mc_save *save);
+extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
/* get temperature in millidegrees */
int si_get_temp(struct radeon_device *rdev)
@@ -449,7 +450,7 @@ static u32 dce6_line_buffer_adjust(struct radeon_device
*rdev,
return 0;
}
-static u32 dce6_get_number_of_dram_channels(struct radeon_device *rdev)
+static u32 si_get_number_of_dram_channels(struct radeon_device *rdev)
{
u32 tmp = RREG32(MC_SHARED_CHMAP);
@@ -766,7 +767,10 @@ static void dce6_program_watermarks(struct radeon_device
*rdev,
wm.vtaps = 2;
wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
wm.lb_size = lb_size;
- wm.dram_channels = dce6_get_number_of_dram_channels(rdev);
+ if (rdev->family == CHIP_ARUBA)
+ wm.dram_channels =
evergreen_get_number_of_dram_channels(rdev);
+ else
+ wm.dram_channels = si_get_number_of_dram_channels(rdev);
wm.num_heads = num_heads;
/* set for high clocks */
--
1.7.7.5
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[PATCH 37/48] drm/radeon/kms: DCE6.1 disp eng pll updates
From: Alex Deucher DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_crtc.c |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index 6fe4a6d..224775b 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -767,7 +767,9 @@ static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, * SetPixelClock provides the dividers */ args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); - if (ASIC_IS_DCE6(rdev)) + if (ASIC_IS_DCE61(rdev)) + args.v6.ucPpll = ATOM_EXT_PLL1; + else if (ASIC_IS_DCE6(rdev)) args.v6.ucPpll = ATOM_PPLL0; else args.v6.ucPpll = ATOM_DCPLL; -- 1.7.7.5 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[PATCH 38/48] drm/radeon/kms: Adjust pll picker for DCE6.1
From: Alex Deucher
On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F
can use either PPLL1 or PPLL0.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c | 31 ++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 224775b..92263af 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1487,7 +1487,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
struct drm_crtc *test_crtc;
uint32_t pll_in_use = 0;
- if (ASIC_IS_DCE4(rdev)) {
+ if (ASIC_IS_DCE61(rdev)) {
+ list_for_each_entry(test_encoder,
&dev->mode_config.encoder_list, head) {
+ if (test_encoder->crtc && (test_encoder->crtc == crtc))
{
+ struct radeon_encoder *test_radeon_encoder =
+ to_radeon_encoder(test_encoder);
+ struct radeon_encoder_atom_dig *dig =
+ test_radeon_encoder->enc_priv;
+
+ if ((test_radeon_encoder->encoder_id ==
+ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
+ (dig->linkb == false)) /* UNIPHY A uses
PPLL2 */
+ return ATOM_PPLL2;
+ }
+ }
+ /* UNIPHY B/C/D/E/F */
+ list_for_each_entry(test_crtc, &dev->mode_config.crtc_list,
head) {
+ struct radeon_crtc *radeon_test_crtc;
+
+ if (crtc == test_crtc)
+ continue;
+
+ radeon_test_crtc = to_radeon_crtc(test_crtc);
+ if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
+ (radeon_test_crtc->pll_id == ATOM_PPLL1))
+ pll_in_use |= (1 << radeon_test_crtc->pll_id);
+ }
+ if (!(pll_in_use & 4))
+ return ATOM_PPLL0;
+ return ATOM_PPLL1;
+ } else if (ASIC_IS_DCE4(rdev)) {
list_for_each_entry(test_encoder,
&dev->mode_config.encoder_list, head) {
if (test_encoder->crtc && (test_encoder->crtc == crtc))
{
/* in DP mode, the DP ref clock can come from
PPLL, DCPLL, or ext clock,
--
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[PATCH 39/48] drm/radeon/kms: disable PPLL0 on DCE6.1 when not in use
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 92263af..a5c4e3f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1646,6 +1646,8 @@ static void atombios_crtc_commit(struct drm_crtc *crtc)
static void atombios_crtc_disable(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct drm_device *dev = crtc->dev;
+ struct radeon_device *rdev = dev->dev_private;
struct radeon_atom_ss ss;
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
@@ -1657,6 +1659,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id,
radeon_crtc->pll_id,
0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0,
false, &ss);
break;
+ case ATOM_PPLL0:
+ /* disable the ppll */
+ if (ASIC_IS_DCE61(rdev))
+ atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id,
radeon_crtc->pll_id,
+ 0, 0, ATOM_DISABLE, 0, 0, 0,
0, 0, false, &ss);
+ break;
default:
break;
}
--
1.7.7.5
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[PATCH 40/48] drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls
From: Alex Deucher
It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_crtc.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c
b/drivers/gpu/drm/radeon/atombios_crtc.c
index a5c4e3f..083b3ea 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -474,7 +474,7 @@ static void atombios_crtc_program_ss(struct radeon_device
*rdev,
return;
}
args.v3.ucEnable = enable;
- if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
+ if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)
|| ASIC_IS_DCE61(rdev))
args.v3.ucEnable = ATOM_DISABLE;
} else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage =
cpu_to_le16(ss->percentage);
--
1.7.7.5
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[PATCH 41/48] drm/radeon/kms: Add checks for TN in the DP bridge code
From: Alex Deucher
TN (trinity) uses DP bridges for LVDS and VGA just like llano.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/atombios_encoders.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c
b/drivers/gpu/drm/radeon/atombios_encoders.c
index 45bb2fc..468b874 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1438,7 +1438,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
switch (mode) {
case DRM_MODE_DPMS_ON:
default:
- if (ASIC_IS_DCE41(rdev)) {
+ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
atombios_external_encoder_setup(encoder, ext_encoder,
@@ -1449,7 +1449,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
case DRM_MODE_DPMS_STANDBY:
case DRM_MODE_DPMS_SUSPEND:
case DRM_MODE_DPMS_OFF:
- if (ASIC_IS_DCE41(rdev)) {
+ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
atombios_external_encoder_setup(encoder, ext_encoder,
@@ -1822,7 +1822,7 @@ radeon_atom_encoder_init(struct radeon_device *rdev)
break;
}
- if (ext_encoder && ASIC_IS_DCE41(rdev))
+ if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
}
@@ -1911,7 +1911,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
}
if (ext_encoder) {
- if (ASIC_IS_DCE41(rdev))
+ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
else
--
1.7.7.5
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[PATCH 42/48] drm/radeon/kms: cayman gpu init updates for trinity
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen_blit_kms.c |2 +-
drivers/gpu/drm/radeon/ni.c | 52 --
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 4e83fdc..222acd2 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -226,7 +226,7 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
x1 = 1;
if (y2 == 0)
y1 = 1;
- if (rdev->family == CHIP_CAYMAN) {
+ if (rdev->family >= CHIP_CAYMAN) {
if ((x2 == 1) && (y2 == 1))
x2 = 2;
}
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 160799c..833892f 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -478,6 +478,7 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct
radeon_device *rdev,
memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
switch (rdev->family) {
case CHIP_CAYMAN:
+ case CHIP_ARUBA:
force_no_swizzle = true;
break;
default:
@@ -610,7 +611,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
switch (rdev->family) {
case CHIP_CAYMAN:
- default:
rdev->config.cayman.max_shader_engines = 2;
rdev->config.cayman.max_pipes_per_simd = 4;
rdev->config.cayman.max_tile_pipes = 8;
@@ -632,6 +632,43 @@ static void cayman_gpu_init(struct radeon_device *rdev)
rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
break;
+ case CHIP_ARUBA:
+ default:
+ rdev->config.cayman.max_shader_engines = 1;
+ rdev->config.cayman.max_pipes_per_simd = 4;
+ rdev->config.cayman.max_tile_pipes = 2;
+ if ((rdev->pdev->device == 0x9900) ||
+ (rdev->pdev->device == 0x9901)) {
+ rdev->config.cayman.max_simds_per_se = 6;
+ rdev->config.cayman.max_backends_per_se = 2;
+ } else if ((rdev->pdev->device == 0x9903) ||
+ (rdev->pdev->device == 0x9904)) {
+ rdev->config.cayman.max_simds_per_se = 4;
+ rdev->config.cayman.max_backends_per_se = 2;
+ } else if ((rdev->pdev->device == 0x9990) ||
+ (rdev->pdev->device == 0x9991)) {
+ rdev->config.cayman.max_simds_per_se = 3;
+ rdev->config.cayman.max_backends_per_se = 1;
+ } else {
+ rdev->config.cayman.max_simds_per_se = 2;
+ rdev->config.cayman.max_backends_per_se = 1;
+ }
+ rdev->config.cayman.max_texture_channel_caches = 2;
+ rdev->config.cayman.max_gprs = 256;
+ rdev->config.cayman.max_threads = 256;
+ rdev->config.cayman.max_gs_threads = 32;
+ rdev->config.cayman.max_stack_entries = 512;
+ rdev->config.cayman.sx_num_of_sets = 8;
+ rdev->config.cayman.sx_max_export_size = 256;
+ rdev->config.cayman.sx_max_export_pos_size = 64;
+ rdev->config.cayman.sx_max_export_smx_size = 192;
+ rdev->config.cayman.max_hw_contexts = 8;
+ rdev->config.cayman.sq_num_cf_insts = 2;
+
+ rdev->config.cayman.sc_prim_fifo_size = 0x40;
+ rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
+ rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
+ break;
}
/* Initialize HDP */
@@ -652,7 +689,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
- cgts_tcc_disable = 0xff00;
+ cgts_tcc_disable = 0x;
+ for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
+ cgts_tcc_disable &= ~(1 << (16 + i));
gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
@@ -804,8 +843,13 @@ static void cayman_gpu_init(struct radeon_device *rdev)
rdev->config.cayman.tile_config |= (3 << 0);
break;
}
- rdev->config.cayman.tile_config |=
- ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
+
+ /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
+ if (rdev->flags & RADEON_IS_IGP)
+ rdev->config.e
[PATCH 43/48] drm/radeon/kms: Update evergreen functions for trinity
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/evergreen.c | 23 +--
drivers/gpu/drm/radeon/nid.h |1 +
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen.c
b/drivers/gpu/drm/radeon/evergreen.c
index 6c2b666..cfa372c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1328,7 +1328,10 @@ void evergreen_mc_program(struct radeon_device *rdev)
rdev->mc.vram_end >> 12);
}
WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr
>> 12);
- if (rdev->flags & RADEON_IS_IGP) {
+ /* llano/ontario only */
+ if ((rdev->family == CHIP_PALM) ||
+ (rdev->family == CHIP_SUMO) ||
+ (rdev->family == CHIP_SUMO2)) {
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000F;
tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
@@ -1972,7 +1975,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
- if (rdev->flags & RADEON_IS_IGP)
+ if ((rdev->family == CHIP_PALM) ||
+ (rdev->family == CHIP_SUMO) ||
+ (rdev->family == CHIP_SUMO2))
mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
else
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
@@ -2362,7 +2367,9 @@ int evergreen_mc_init(struct radeon_device *rdev)
/* Get VRAM informations */
rdev->mc.vram_is_ddr = true;
- if (rdev->flags & RADEON_IS_IGP)
+ if ((rdev->family == CHIP_PALM) ||
+ (rdev->family == CHIP_SUMO) ||
+ (rdev->family == CHIP_SUMO2))
tmp = RREG32(FUS_MC_ARB_RAMCFG);
else
tmp = RREG32(MC_ARB_RAMCFG);
@@ -2394,12 +2401,14 @@ int evergreen_mc_init(struct radeon_device *rdev)
rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
/* Setup GPU memory space */
- if (rdev->flags & RADEON_IS_IGP) {
+ if ((rdev->family == CHIP_PALM) ||
+ (rdev->family == CHIP_SUMO) ||
+ (rdev->family == CHIP_SUMO2)) {
/* size in bytes on fusion */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
} else {
- /* size in MB on evergreen */
+ /* size in MB on evergreen/cayman/tn */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
}
@@ -2557,7 +2566,9 @@ void evergreen_disable_interrupt_state(struct
radeon_device *rdev)
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
}
- WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+ /* only one DAC on DCE6 */
+ if (!ASIC_IS_DCE6(rdev))
+ WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 9a7f3b6..2aa7046 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -106,6 +106,7 @@
#defineSYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
#defineSYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
#defineENABLE_ADVANCED_DRIVER_MODEL(1 << 6)
+#defineFUS_MC_VM_FB_OFFSET 0x2068
#define MC_SHARED_BLACKOUT_CNTL0x20ac
#defineMC_ARB_RAMCFG 0x2760
--
1.7.7.5
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[PATCH 44/48] drm/radeon/kms/vm: set vram base offset properly for TN
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ni.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 833892f..bae3ec3 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1746,7 +1746,12 @@ int cayman_vm_init(struct radeon_device *rdev)
/* number of VMs */
rdev->vm_manager.nvm = 8;
/* base offset of vram pages */
- rdev->vm_manager.vram_base_offset = 0;
+ if (rdev->flags & RADEON_IS_IGP) {
+ u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
+ tmp <<= 22;
+ rdev->vm_manager.vram_base_offset = tmp;
+ } else
+ rdev->vm_manager.vram_base_offset = 0;
return 0;
}
--
1.7.7.5
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[PATCH 45/48] drm/radeon/kms: add support for ucode loading on trinity (v2)
From: Alex Deucher
v2: fix check for MC ucode from Tom.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/ni.c| 82 +++-
drivers/gpu/drm/radeon/r600.c | 21 --
drivers/gpu/drm/radeon/r600d.h |4 ++
drivers/gpu/drm/radeon/si.c|4 +-
4 files changed, 87 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index bae3ec3..a48ca53 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -42,6 +42,8 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev);
extern int evergreen_mc_init(struct radeon_device *rdev);
extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
+extern void si_rlc_fini(struct radeon_device *rdev);
+extern int si_rlc_init(struct radeon_device *rdev);
#define EVERGREEN_PFP_UCODE_SIZE 1120
#define EVERGREEN_PM4_UCODE_SIZE 1376
@@ -53,6 +55,8 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device
*rdev);
#define CAYMAN_RLC_UCODE_SIZE 1024
#define CAYMAN_MC_UCODE_SIZE 6037
+#define ARUBA_RLC_UCODE_SIZE 1536
+
/* Firmware Names */
MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
MODULE_FIRMWARE("radeon/BARTS_me.bin");
@@ -68,6 +72,9 @@ MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
+MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
+MODULE_FIRMWARE("radeon/ARUBA_me.bin");
+MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
#define BTC_IO_MC_REGS_SIZE 29
@@ -326,6 +333,15 @@ int ni_init_microcode(struct radeon_device *rdev)
rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
break;
+ case CHIP_ARUBA:
+ chip_name = "ARUBA";
+ rlc_chip_name = "ARUBA";
+ /* pfp/me same size as CAYMAN */
+ pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
+ me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
+ rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
+ mc_req_size = 0;
+ break;
default: BUG();
}
@@ -365,15 +381,18 @@ int ni_init_microcode(struct radeon_device *rdev)
err = -EINVAL;
}
- snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
- err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
- if (err)
- goto out;
- if (rdev->mc_fw->size != mc_req_size) {
- printk(KERN_ERR
- "ni_mc: Bogus length %zu in firmware \"%s\"\n",
- rdev->mc_fw->size, fw_name);
- err = -EINVAL;
+ /* no MC ucode on TN */
+ if (!(rdev->flags & RADEON_IS_IGP)) {
+ snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin",
chip_name);
+ err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
+ if (err)
+ goto out;
+ if (rdev->mc_fw->size != mc_req_size) {
+ printk(KERN_ERR
+ "ni_mc: Bogus length %zu in firmware \"%s\"\n",
+ rdev->mc_fw->size, fw_name);
+ err = -EINVAL;
+ }
}
out:
platform_device_unregister(pdev);
@@ -1484,18 +1503,29 @@ static int cayman_startup(struct radeon_device *rdev)
/* enable pcie gen2 link */
evergreen_pcie_gen2_enable(rdev);
- if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
- r = ni_init_microcode(rdev);
+ if (rdev->flags & RADEON_IS_IGP) {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
+ r = ni_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+ } else {
+ if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw ||
!rdev->mc_fw) {
+ r = ni_init_microcode(rdev);
+ if (r) {
+ DRM_ERROR("Failed to load firmware!\n");
+ return r;
+ }
+ }
+
+ r = ni_mc_load_microcode(rdev);
if (r) {
- DRM_ERROR("Failed to load firmware!\n");
+ DRM_ERROR("Failed to load MC firmware!\n");
return r;
}
}
- r = ni_mc_load_microcode(rdev);
- if (r) {
- DRM_ERROR("Failed to load MC firmware!\n");
- return r;
- }
r = r600_vram_scratch_init(rdev);
if (r)
@@ -1514,6 +1544,15 @@ static int cayman_startup(struct radeon_device *rd
[PATCH 46/48] drm/radeon/kms: add radeon_asic struct for trinity
From: Alex Deucher
Trinity (TN) is an APU with:
- Cayman 3D
- DCE6.1 display
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_asic.c | 98 ++
1 files changed, 98 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c
b/drivers/gpu/drm/radeon/radeon_asic.c
index f24e145..be4dc2f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -1408,6 +1408,98 @@ static struct radeon_asic cayman_asic = {
},
};
+static struct radeon_asic trinity_asic = {
+ .init = &cayman_init,
+ .fini = &cayman_fini,
+ .suspend = &cayman_suspend,
+ .resume = &cayman_resume,
+ .gpu_is_lockup = &cayman_gpu_is_lockup,
+ .asic_reset = &cayman_asic_reset,
+ .vga_set_state = &r600_vga_set_state,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
+ .gart = {
+ .tlb_flush = &cayman_pcie_gart_tlb_flush,
+ .set_page = &rs600_gart_set_page,
+ },
+ .ring = {
+ [RADEON_RING_TYPE_GFX_INDEX] = {
+ .ib_execute = &cayman_ring_ib_execute,
+ .ib_parse = &evergreen_ib_parse,
+ .emit_fence = &cayman_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = &evergreen_cs_parse,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ },
+ [CAYMAN_RING_TYPE_CP1_INDEX] = {
+ .ib_execute = &cayman_ring_ib_execute,
+ .ib_parse = &evergreen_ib_parse,
+ .emit_fence = &cayman_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = &evergreen_cs_parse,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ },
+ [CAYMAN_RING_TYPE_CP2_INDEX] = {
+ .ib_execute = &cayman_ring_ib_execute,
+ .ib_parse = &evergreen_ib_parse,
+ .emit_fence = &cayman_fence_ring_emit,
+ .emit_semaphore = &r600_semaphore_ring_emit,
+ .cs_parse = &evergreen_cs_parse,
+ .ring_test = &r600_ring_test,
+ .ib_test = &r600_ib_test,
+ }
+ },
+ .irq = {
+ .set = &evergreen_irq_set,
+ .process = &evergreen_irq_process,
+ },
+ .display = {
+ .bandwidth_update = &dce6_bandwidth_update,
+ .get_vblank_counter = &evergreen_get_vblank_counter,
+ .wait_for_vblank = &dce4_wait_for_vblank,
+ },
+ .copy = {
+ .blit = &r600_copy_blit,
+ .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ .dma = NULL,
+ .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ .copy = &r600_copy_blit,
+ .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
+ },
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
+ .hpd = {
+ .init = &evergreen_hpd_init,
+ .fini = &evergreen_hpd_fini,
+ .sense = &evergreen_hpd_sense,
+ .set_polarity = &evergreen_hpd_set_polarity,
+ },
+ .pm = {
+ .misc = &evergreen_pm_misc,
+ .prepare = &evergreen_pm_prepare,
+ .finish = &evergreen_pm_finish,
+ .init_profile = &sumo_pm_init_profile,
+ .get_dynpm_state = &r600_pm_get_dynpm_state,
+ .get_engine_clock = &radeon_atom_get_engine_clock,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .get_memory_clock = NULL,
+ .set_memory_clock = NULL,
+ .get_pcie_lanes = NULL,
+ .set_pcie_lanes = NULL,
+ .set_clock_gating = NULL,
+ },
+ .pflip = {
+ .pre_page_flip = &evergreen_pre_page_flip,
+ .page_flip = &evergreen_page_flip,
+ .post_page_flip = &evergreen_post_page_flip,
+ },
+};
+
static const struct radeon_vm_funcs si_vm_funcs = {
.init = &si_vm_init,
.fini = &si_vm_fini,
@@ -1627,6 +1719,12 @@ int radeon_asic_init(struct radeon_device *rdev)
rdev->num_crtc = 6;
rdev->vm_manager.funcs = &cayman_vm_funcs;
break;
+ case CHIP_ARUBA:
+ rdev->asic = &trinity_asic;
+ /* set num crtcs */
+ rdev->num_crtc = 4;
+ rdev->vm_manager.funcs = &cayman_vm_funcs;
+ break;
case CHIP_TAH
[PATCH 47/48] drm/radeon/kms: add trinity pci ids
From: Alex Deucher
Signed-off-by: Alex Deucher
---
include/drm/drm_pciids.h | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 1ab5270..58d0bda 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -550,6 +550,22 @@
{0x1002, 0x9807, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9808, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x9809, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9900, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9901, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9903, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9904, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9905, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9906, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9907, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9908, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9909, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x990A, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x990F, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9990, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9991, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9992, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9993, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x9994, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0, 0, 0}
#define r128_PCI_IDS \
--
1.7.7.5
___
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[PATCH 48/48] drm/radeon/kms: update duallink checks for DCE6
From: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/radeon/radeon_connectors.c |2 +-
drivers/gpu/drm/radeon/radeon_encoders.c |6 --
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 64774ac..bd05156 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -1085,7 +1085,7 @@ static int radeon_dvi_mode_valid(struct drm_connector
*connector,
(radeon_connector->connector_object_id ==
CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
return MODE_OK;
else if (radeon_connector->connector_object_id ==
CONNECTOR_OBJECT_ID_HDMI_TYPE_A) {
- if (0) {
+ if (ASIC_IS_DCE6(rdev)) {
/* HDMI 1.3+ supports max clock of 340 Mhz */
if (mode->clock > 34)
return MODE_CLOCK_HIGH;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c
b/drivers/gpu/drm/radeon/radeon_encoders.c
index 26e9270..7467069 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -307,6 +307,8 @@ void radeon_panel_mode_fixup(struct drm_encoder *encoder,
bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
u32 pixel_clock)
{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
struct drm_connector *connector;
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *dig_connector;
@@ -324,7 +326,7 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder
*encoder,
case DRM_MODE_CONNECTOR_HDMIB:
if (radeon_connector->use_digital) {
/* HDMI 1.3 supports up to 340 Mhz over single link */
- if (0 &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
+ if (ASIC_IS_DCE6(rdev) &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
if (pixel_clock > 34)
return true;
else
@@ -346,7 +348,7 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder
*encoder,
return false;
else {
/* HDMI 1.3 supports up to 340 Mhz over single link */
- if (0 &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
+ if (ASIC_IS_DCE6(rdev) &&
drm_detect_hdmi_monitor(radeon_connector->edid)) {
if (pixel_clock > 34)
return true;
else
--
1.7.7.5
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Re: [PATCH] [RFC] dma-buf: mmap support
On Tue, Mar 20, 2012 at 09:53:05PM +0100, Daniel Vetter wrote: > Note taht this dma-buf mmap patch does _not_ support every possible > insanity an existing subsystem could pull of with mmap: Because it > does not allow to intercept pagefaults and shoot down ptes importing > subsystems can't add some magic of their own at these points (e.g. to > automatically synchronize with outstanding rendering or set up some > special resources). I've done a cursory read through a few mmap > implementions of various subsytems and I'm hopeful that we can avoid > this (and the complexity it'd bring with it). To clarify: This concerns the importer. The exporter is of course still free to do whatever it pleases. But the goal of this exercise is that importing subsystems can still offer an identical userspace interfaces for buffers imported through dma-buf and native ones, hence why I've mentioned it. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: [PATCH 17/48] drm/radeon/kms: add gpu init support for SI
On Tue, 2012-03-20 at 17:18 -0400, alexdeuc...@gmail.com wrote:
> From: Alex Deucher
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/radeon.h | 32 ++
> drivers/gpu/drm/radeon/si.c | 1005
> +++
> drivers/gpu/drm/radeon/sid.h| 201
> 3 files changed, 1238 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index c75ccc7..972f167 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -1370,6 +1370,37 @@ struct cayman_asic {
> struct r100_gpu_lockup lockup;
> };
>
> +struct si_asic {
> + unsigned max_shader_engines;
> + unsigned max_pipes_per_simd;
> + unsigned max_tile_pipes;
> + unsigned max_simds_per_se;
> + unsigned max_backends_per_se;
> + unsigned max_texture_channel_caches;
> + unsigned max_gprs;
> + unsigned max_gs_threads;
> + unsigned max_hw_contexts;
> + unsigned sc_prim_fifo_size_frontend;
> + unsigned sc_prim_fifo_size_backend;
> + unsigned sc_hiz_tile_fifo_size;
> + unsigned sc_earlyz_tile_fifo_size;
> +
> + unsigned num_shader_engines;
> + unsigned num_tile_pipes;
> + unsigned num_backends_per_se;
> + unsigned backend_disable_mask_per_asic;
> + unsigned backend_map;
> + unsigned num_texture_channel_caches;
> + unsigned mem_max_burst_length_bytes;
> + unsigned mem_row_size_in_kb;
> + unsigned shader_engine_tile_size;
> + unsigned num_gpus;
> + unsigned multi_gpu_tile_size;
> +
> + unsigned tile_config;
> + struct r100_gpu_lockup lockup;
> +};
> +
> union radeon_asic_config {
> struct r300_asicr300;
> struct r100_asicr100;
> @@ -1377,6 +1408,7 @@ union radeon_asic_config {
> struct rv770_asic rv770;
> struct evergreen_asic evergreen;
> struct cayman_asic cayman;
> + struct si_asic si;
> };
>
> /*
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 3e91429..dd9e7d3 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -28,6 +28,8 @@
> #include "sid.h"
> #include "atom.h"
>
> +extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
> +
> /* get temperature in millidegrees */
> int si_get_temp(struct radeon_device *rdev)
> {
> @@ -503,3 +505,1006 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
> }
> }
>
> +/*
> + * Core functions
> + */
> +static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
> +u32 num_tile_pipes,
> +u32 num_backends_per_asic,
> +u32 *backend_disable_mask_per_asic,
> +u32 num_shader_engines)
> +{
> + u32 backend_map = 0;
> + u32 enabled_backends_mask = 0;
> + u32 enabled_backends_count = 0;
> + u32 num_backends_per_se;
> + u32 cur_pipe;
> + u32 swizzle_pipe[SI_MAX_PIPES];
> + u32 cur_backend = 0;
> + u32 i;
> + bool force_no_swizzle;
> +
> + /* force legal values */
> + if (num_tile_pipes < 1)
> + num_tile_pipes = 1;
> + if (num_tile_pipes > rdev->config.si.max_tile_pipes)
> + num_tile_pipes = rdev->config.si.max_tile_pipes;
> + if (num_shader_engines < 1)
> + num_shader_engines = 1;
> + if (num_shader_engines > rdev->config.si.max_shader_engines)
> + num_shader_engines = rdev->config.si.max_shader_engines;
> + if (num_backends_per_asic < num_shader_engines)
> + num_backends_per_asic = num_shader_engines;
> + if (num_backends_per_asic > (rdev->config.si.max_backends_per_se *
> num_shader_engines))
> + num_backends_per_asic = rdev->config.si.max_backends_per_se *
> num_shader_engines;
> +
> + /* make sure we have the same number of backends per se */
> + num_backends_per_asic = ALIGN(num_backends_per_asic,
> num_shader_engines);
> + /* set up the number of backends per se */
> + num_backends_per_se = num_backends_per_asic / num_shader_engines;
> + if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
> + num_backends_per_se = rdev->config.si.max_backends_per_se;
> + num_backends_per_asic = num_backends_per_se *
> num_shader_engines;
> + }
> +
> + /* create enable mask and count for enabled backends */
> + for (i = 0; i < SI_MAX_BACKENDS; ++i) {
> + if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
> + enabled_backends_mask |= (1 << i);
> + ++enabled_backends_count;
> + }
> + if (enabled_backends_count == num_backends_per_asic)
> + break;
> + }
> +
> + /* force the backends mask to match the current number of backends */
> + if
Re: [PATCH 00/48] Add SI, TN support
On Tue, 2012-03-20 at 17:17 -0400, alexdeuc...@gmail.com wrote: > From: Alex Deucher > > This patch set adds support for SI (Southern Islands discrete > GPUs) and TN (Trinity APU). The patches are available here > as well: > http://people.freedesktop.org/~agd5f/si_tn/ > New ucode for SI (TAHITI, PITCAIRN, VERDE) and TN (ARUBA) is > available here: > http://people.freedesktop.org/~agd5f/radeon_ucode/ > Userspace code to follow. > > I included Tom's patch (0001) since patch 0032 depends on it. > > Alex Deucher (46): > drm/radeon/kms: Upstream ObjectID.h updates > drm/radeon/kms: upstream atombios.h updates > drm/radeon/kms: upstream power table updates > drm/radeon/kms: add SI chip families > drm/radeon/kms: add initial DCE6 display watermark support > drm/radeon/kms: fix up atom HPD gpio parsing for DCE6 > drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bits > drm/radeon/kms/atom: add support for crtc power gating > drm/radeon/kms: DCE6 disp eng pll updates > drm/radeon/kms/atom: add support for DCE6.x dig transmitters > drm/radeon/kms: DP aux updates for DCE6 > drm/radeon/kms: update comments about dig encoders/transmitters > drm/radeon/kms/atom: add support for SI SetVoltage table > drm/radeon/kms: update power table parsing for SI > drm/radeon/kms: add support for internal thermal sensor on SI > drm/radeon/kms: add gpu init support for SI > drm/radeon/kms: Add support for SI GPU reset > drm/radeon/kms: add support for MC/VM setup on SI > drm/radeon/kms: add support for the CONST IB to the CS ioctl > drm/radeon/kms: add VM CS checker for SI > drm/radeon/kms: Only VM CS ioctl is supported on SI (v2) > drm/radeon/kms: add ucode loading for SI > drm/radeon/kms: add support for MC ucode loading on SI > drm/radeon/kms: add support for CP setup on SI > drm/radeon/kms: add IB and fence dispatch functions for SI > drm/radeon/kms: Add support for RLC init on SI > drm/radeon/kms: add support for interrupts on SI > drm/radeon/kms: fill in startup/shutdown callbacks for SI > drm/radeon/kms: add support for compute rings in CS ioctl on SI > drm/radeon/kms: add radeon_asic struct for SI > drm/radeon/kms: Add SI pci ids > drm/radeon/kms: add trinity (TN) chip family > drm/radeon/kms: no support for internal thermal sensor on TN yet > drm/radeon/kms: DCE6.1 watermark updates for TN > drm/radeon/kms: DCE6.1 disp eng pll updates > drm/radeon/kms: Adjust pll picker for DCE6.1 > drm/radeon/kms: disable PPLL0 on DCE6.1 when not in use > drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls > drm/radeon/kms: Add checks for TN in the DP bridge code > drm/radeon/kms: cayman gpu init updates for trinity > drm/radeon/kms: Update evergreen functions for trinity > drm/radeon/kms/vm: set vram base offset properly for TN > drm/radeon/kms: add support for ucode loading on trinity (v2) > drm/radeon/kms: add radeon_asic struct for trinity > drm/radeon/kms: add trinity pci ids > drm/radeon/kms: update duallink checks for DCE6 > > Michel Dänzer (1): > drm/radeon: Update radeon_info_ioctl for SI. (v2) > > Tom Stellard (1): > drm/radeon/kms: add info query for max pipes > > drivers/gpu/drm/radeon/Makefile |2 +- > drivers/gpu/drm/radeon/ObjectID.h |5 + > drivers/gpu/drm/radeon/atombios.h | 1109 +++- > drivers/gpu/drm/radeon/atombios_crtc.c | 100 +- > drivers/gpu/drm/radeon/atombios_dp.c|6 +- > drivers/gpu/drm/radeon/atombios_encoders.c | 71 +- > drivers/gpu/drm/radeon/evergreen.c | 25 +- > drivers/gpu/drm/radeon/evergreen_blit_kms.c |2 +- > drivers/gpu/drm/radeon/ni.c | 141 +- > drivers/gpu/drm/radeon/nid.h|1 + > drivers/gpu/drm/radeon/r600.c | 25 +- > drivers/gpu/drm/radeon/r600d.h |4 + > drivers/gpu/drm/radeon/radeon.h | 55 +- > drivers/gpu/drm/radeon/radeon_asic.c| 208 ++ > drivers/gpu/drm/radeon/radeon_asic.h| 25 + > drivers/gpu/drm/radeon/radeon_atombios.c| 78 +- > drivers/gpu/drm/radeon/radeon_connectors.c |2 +- > drivers/gpu/drm/radeon/radeon_cs.c | 63 +- > drivers/gpu/drm/radeon/radeon_device.c |6 +- > drivers/gpu/drm/radeon/radeon_display.c |2 +- > drivers/gpu/drm/radeon/radeon_drv.c |3 +- > drivers/gpu/drm/radeon/radeon_encoders.c|6 +- > drivers/gpu/drm/radeon/radeon_family.h |4 + > drivers/gpu/drm/radeon/radeon_kms.c | 32 +- > drivers/gpu/drm/radeon/radeon_mode.h|2 +- > drivers/gpu/drm/radeon/radeon_pm.c |7 + > drivers/gpu/drm/radeon/radeon_reg.h |1 + > drivers/gpu/drm/radeon/radeon_ring.c|1 + > drivers/gpu/drm/radeon/si.c | 4128 > +++ > drivers/gpu/drm/radeon/si_blit_shaders.c| 252 ++ > drivers/gpu/drm/radeon/si_blit_shaders.h| 3
Re: [PATCH 06/48] drm/radeon/kms: add initial DCE6 display watermark support
On Tue, 2012-03-20 at 17:18 -0400, alexdeuc...@gmail.com wrote:
> From: Alex Deucher
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/Makefile |2 +-
> drivers/gpu/drm/radeon/radeon_asic.h |3 +
> drivers/gpu/drm/radeon/si.c | 486
> ++
> drivers/gpu/drm/radeon/sid.h | 46
> 4 files changed, 536 insertions(+), 1 deletions(-)
> create mode 100644 drivers/gpu/drm/radeon/si.c
> create mode 100644 drivers/gpu/drm/radeon/sid.h
>
> diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
> index 8410415..fa3e704 100644
> --- a/drivers/gpu/drm/radeon/Makefile
> +++ b/drivers/gpu/drm/radeon/Makefile
> @@ -71,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
> r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
> evergreen.o evergreen_cs.o evergreen_blit_shaders.o
> evergreen_blit_kms.o \
> radeon_trace_points.o ni.o cayman_blit_shaders.o atombios_encoders.o \
> - radeon_semaphore.o radeon_sa.o atombios_i2c.o
> + radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o
>
> radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
> radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h
> b/drivers/gpu/drm/radeon/radeon_asic.h
> index b8f0a16..007f0f6 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -461,4 +461,7 @@ void cayman_vm_set_page(struct radeon_device *rdev,
> struct radeon_vm *vm,
> unsigned pfn, uint64_t addr, uint32_t flags);
> int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
>
> +/* DCE6 - SI */
> +void dce6_bandwidth_update(struct radeon_device *rdev);
> +
> #endif
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> new file mode 100644
> index 000..39c64df
> --- /dev/null
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -0,0 +1,486 @@
> +/*
> + * Copyright 2011 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors: Alex Deucher
> + */
> +#include "drmP.h"
> +#include "radeon.h"
> +#include "radeon_asic.h"
> +#include "radeon_drm.h"
> +#include "sid.h"
> +#include "atom.h"
> +
> +/* watermark setup */
> +static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
> +struct radeon_crtc *radeon_crtc,
> +struct drm_display_mode *mode,
> +struct drm_display_mode *other_mode)
> +{
> + u32 tmp;
> + /*
> + * Line Buffer Setup
> + * There are 3 line buffers, each one shared by 2 display controllers.
> + * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
> + * the display controllers. The paritioning is done via one of four
> + * preset allocations specified in bits 21:20:
> + * 0 - half lb
> + * 2 - whole lb, other crtc must be disabled
> + */
> + /* this can get tricky if we have two large displays on a paired group
> + * of crtcs. Ideally for multiple large displays we'd assign them to
> + * non-linked crtcs for maximum line buffer allocation.
> + */
> + if (radeon_crtc->base.enabled && mode) {
> + if (other_mode)
> + tmp = 0; /* 1/2 */
> + else
> + tmp = 2; /* whole */
> + } else
> + tmp = 0;
> +
> + WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
> +DC_LB_MEMORY_CONFIG(tmp));
> +
> + if (radeon_crtc->base.enabled && mode) {
> + switch (tmp) {
> + case 0:
> + default:
> + return 4096 * 2;
> + case 2:
> + return 8192 * 2;
> + }
> + }
> +
> + /* controller not enabled, so n
Re: [PATCH 19/48] drm/radeon/kms: add support for MC/VM setup on SI
On Tue, 2012-03-20 at 17:18 -0400, alexdeuc...@gmail.com wrote:
> From: Alex Deucher
>
> Sets up the VM and adds support for the new VM ioctls.
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/si.c | 328
> ++
> drivers/gpu/drm/radeon/sid.h | 219
> 2 files changed, 547 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 58ad900..ad91c5f 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -1608,3 +1608,331 @@ int si_asic_reset(struct radeon_device *rdev)
> return si_gpu_soft_reset(rdev);
> }
>
> +/* MC */
> +static void si_mc_program(struct radeon_device *rdev)
> +{
> + struct evergreen_mc_save save;
> + u32 tmp;
> + int i, j;
> +
> + /* Initialize HDP */
> + for (i = 0, j = 0; i < 32; i++, j += 0x18) {
> + WREG32((0x2c14 + j), 0x);
> + WREG32((0x2c18 + j), 0x);
> + WREG32((0x2c1c + j), 0x);
> + WREG32((0x2c20 + j), 0x);
> + WREG32((0x2c24 + j), 0x);
> + }
> + WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
> +
> + evergreen_mc_stop(rdev, &save);
> + if (radeon_mc_wait_for_idle(rdev)) {
> + dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
> + }
> + /* Lockout access through VGA aperture*/
> + WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
> + /* Update configuration */
> + WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
> +rdev->mc.vram_start >> 12);
> + WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> +rdev->mc.vram_end >> 12);
> + WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
> +rdev->vram_scratch.gpu_addr >> 12);
> + tmp = ((rdev->mc.vram_end >> 24) & 0x) << 16;
> + tmp |= ((rdev->mc.vram_start >> 24) & 0x);
> + WREG32(MC_VM_FB_LOCATION, tmp);
> + /* XXX double check these! */
> + WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
> + WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
> + WREG32(HDP_NONSURFACE_SIZE, 0x3FFF);
> + WREG32(MC_VM_AGP_BASE, 0);
> + WREG32(MC_VM_AGP_TOP, 0x0FFF);
> + WREG32(MC_VM_AGP_BOT, 0x0FFF);
> + if (radeon_mc_wait_for_idle(rdev)) {
> + dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
> + }
> + evergreen_mc_resume(rdev, &save);
> + /* we need to own VRAM, so turn off the VGA renderer here
> + * to stop it overwriting our objects */
> + rv515_vga_render_disable(rdev);
> +}
> +
> +/* SI MC address space is 40 bits */
> +static void si_vram_location(struct radeon_device *rdev,
> + struct radeon_mc *mc, u64 base)
> +{
> + mc->vram_start = base;
> + if (mc->mc_vram_size > (0xFFULL - base + 1)) {
Why not ((1ULL << 40ULL) - 1ULL) so i don't have to count the number
of F in 0xFFULL ;)
> + dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
> + mc->real_vram_size = mc->aper_size;
> + mc->mc_vram_size = mc->aper_size;
> + }
> + mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
> + dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
> + mc->mc_vram_size >> 20, mc->vram_start,
> + mc->vram_end, mc->real_vram_size >> 20);
> +}
> +
> +static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
> +{
> + u64 size_af, size_bf;
> +
> + size_af = ((0xFFULL - mc->vram_end) + mc->gtt_base_align) &
> ~mc->gtt_base_align;
> + size_bf = mc->vram_start & ~mc->gtt_base_align;
> + if (size_bf > size_af) {
> + if (mc->gtt_size > size_bf) {
> + dev_warn(rdev->dev, "limiting GTT\n");
> + mc->gtt_size = size_bf;
> + }
> + mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) -
> mc->gtt_size;
> + } else {
> + if (mc->gtt_size > size_af) {
> + dev_warn(rdev->dev, "limiting GTT\n");
> + mc->gtt_size = size_af;
> + }
> + mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) &
> ~mc->gtt_base_align;
> + }
> + mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
> + dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
> + mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
> +}
> +
> +static void si_vram_gtt_location(struct radeon_device *rdev,
> + struct radeon_mc *mc)
> +{
> + if (mc->mc_vram_size > 0xFFC000ULL) {
> + /* leave room for at least 1024M GTT */
> + dev_warn(rdev->dev, "limiting VRAM\n");
> + mc->real_vram_size = 0xFFC000ULL;
> + mc->mc_vram_size = 0xFFC000ULL;
> + }
> + si_vram_location(rdev, &rdev->mc, 0);
> +
Re: Why do flush page cache twice when change TT's cache attribute
yes, flush page twice cause system slow in some CPU.
Meanwhile, set_memory_uc/wc doesn't only do flush page cache, but also
change page table attribute, so your solution seems to have some problem.
2012/3/20 Konrad Rzeszutek Wilk
> On Tue, Mar 20, 2012 at 10:15:02AM +0800, Scott Fang wrote:
> > Can I do the optimization like:
> >
> > if (ttm->caching_state == tt_cached)
> > -drm_clflush_pages(ttm->pages, ttm->num_pages);
> > +for (i = 0; i < ttm->num_pages; ++i)
> > + if (PageHighMem(ttm->pages[i]))
> > +drm_clflush_pages(&ttm->pages[i], 1);
> >
> > only do flush cache when high memory and leave the linear memory flush in
> > function set_memory_uc/wc?
>
> So what are you trying to solve? I mean one way to fix this
> is to do:
> >
> > 2012/3/20 Jerome Glisse
> >
> > > On Mon, 2012-03-19 at 23:11 +0800, Scott Fang wrote:
> > > > In function ttm_tt_set_caching
> > > > ,,,
> > > >
> > > > if (ttm->caching_state == tt_cached)
> > > > drm_clflush_pages(ttm->pages, ttm->num_pages);
> goto out;
> > > >
> > > > for (i = 0; i < ttm->num_pages; ++i) {
> > > > cur_page = ttm->pages[i];
> > > > if (likely(cur_page != NULL)) {
> > > > ret = ttm_tt_set_page_caching(cur_page,
> > > > ttm->caching_state,
> > > > c_state);
> > > > if (unlikely(ret != 0))
> > > > goto out_err;
> > > > }
> > > > }
> > >
> out:
> > > > ttm->caching_state = c_state;
> > > >
> > > > return 0;
>
> Is the problem with calling page change twice making the machine slow?
>
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RE: [PATCH v2 00/14] updated exynos-drm-next.
Hi Dave, > -Original Message- > From: Dave Airlie [mailto:airl...@gmail.com] > Sent: Tuesday, March 20, 2012 6:49 PM > To: Inki Dae > Cc: airl...@linux.ie; dri-devel@lists.freedesktop.org; > kyungmin.p...@samsung.com; sw0312@samsung.com > Subject: Re: [PATCH v2 00/14] updated exynos-drm-next. > > On Fri, Mar 16, 2012 at 9:47 AM, Inki Dae wrote: > > Hi, Dave and all. > > Hi Inki, > > I've taken most of these patches except for the G2D and Virtual drivers, > > If you can make the virtual driver rebase without G2D I don't see an > issue with merging it, it didn't seem to apply cleanly here. > > But I don't think G2D is close enough for this merge window > considering the security issues with exposing DMA engines without a > lot of review. > > Dave. Ok, I will resend rebased Virtual Display Driver and we will consolidate the security part of g2d for next time. Thanks, Inki Dae. ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
[git pull] updated exynos-drm-next
Hi, Dave. as you pointed out, we have removed g2d driver from this patch set and rebased virtual display driver. for g2d driver, we will consolidate the security issue you pointed out for next time. Please pull from git://git.infradead.org/users/kmpark/linux-samsung exynos-drm-next this patch set is based on git repository below: git://people.freedesktop.org/~airlied/linux.git drm-core-next commit-id: 8229c885fe361e521ac64de36b16011e54a30de0 please let me know if there is any problem. Thanks. Eunchul Kim (1): drm/exynos: add default pixel format for plane Inki Dae (4): drm/exynos: added mode_fixup feature and code clean. drm/exynos: update gem and buffer framework. drm/exynos: added new funtion to get/put dma address. drm/exynos: added virtual display driver. Joonyoung Shim (7): drm/exynos: add HDMI version 1.4 support drm/exynos: release pending pageflip events when closed drm/exynos: remove module of exynos drm subdrv drm/exynos: add subdrv open/close functions drm/exynos: add is_local member in exynos_drm_subdrv struct drm/exynos: remove exynos_mixer.h drm/exynos: cleanup exynos_hdmi.h Seung-Woo Kim (1): drm/exynos: enable hdmi audio feature drivers/gpu/drm/exynos/Kconfig| 14 +- drivers/gpu/drm/exynos/Makefile | 11 +- drivers/gpu/drm/exynos/exynos_ddc.c |1 - drivers/gpu/drm/exynos/exynos_drm_buf.c | 191 +++- drivers/gpu/drm/exynos/exynos_drm_buf.h | 22 +- drivers/gpu/drm/exynos/exynos_drm_connector.c | 35 +- drivers/gpu/drm/exynos/exynos_drm_core.c | 140 +-- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 12 +- drivers/gpu/drm/exynos/exynos_drm_drv.c | 94 ++- drivers/gpu/drm/exynos/exynos_drm_drv.h | 38 +- drivers/gpu/drm/exynos/exynos_drm_encoder.c | 24 +- drivers/gpu/drm/exynos/exynos_drm_fb.c|6 - drivers/gpu/drm/exynos/exynos_drm_fbdev.c | 90 +-- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 20 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 363 ++- drivers/gpu/drm/exynos/exynos_drm_gem.h | 29 +- drivers/gpu/drm/exynos/exynos_drm_hdmi.c | 115 +-- drivers/gpu/drm/exynos/exynos_drm_hdmi.h |5 + drivers/gpu/drm/exynos/exynos_drm_plane.c |8 +- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 676 drivers/gpu/drm/exynos/exynos_drm_vidi.h | 36 + drivers/gpu/drm/exynos/exynos_hdmi.c | 1437 +++-- drivers/gpu/drm/exynos/exynos_hdmi.h | 50 - drivers/gpu/drm/exynos/exynos_mixer.c | 57 +- drivers/gpu/drm/exynos/exynos_mixer.h | 92 -- drivers/gpu/drm/exynos/regs-hdmi.h| 488 - include/drm/exynos_drm.h | 26 + 27 files changed, 3365 insertions(+), 715 deletions(-) create mode 100644 drivers/gpu/drm/exynos/exynos_drm_vidi.c create mode 100644 drivers/gpu/drm/exynos/exynos_drm_vidi.h delete mode 100644 drivers/gpu/drm/exynos/exynos_mixer.h -- 1.7.4.1 ___ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Re: Fwd: Brightness on HP EliteBook 8460p
On Saturday 04 February 2012 20:19:16 Joey Lee wrote:
> Add Cc. to dri mail
>
> Hi Pali,
>
> 於 五，2012-02-03 於 16:24 +0100，Pali Rohár 提到：
>
> > On Friday 20 January 2012 17:55:57 Pali Rohár wrote:
> > > On Friday 20 January 2012 11:28:59 joeyli wrote:
> > > > 於 五，2012-01-20 於 11:12 +0800，joeyli 提到：
> > > >
> > > > > Hi Pali,
> > > > >
> > > > > Sorry for I am late reply you.
> > > > >
> > > > > 於 二，2012-01-17 於 19:10 +0100，Pali Rohár 提到：
> > > > >
> > > > > > On Wednesday 21 December 2011 12:45:07 Pali Rohár wrote:
> > > > > > > Hello,
> > > > > > >
> > > > > > > I tried to boot with all 3 strings in acpi_os_name, but
> > > > > > > nothing was
> > > > > > > changed. I'm attaching dmesg outputs, one from BIOS
> > > > > > > mode, one from
> > > > > > > UEFI mode. Both are with "Microsoft Windows NT".
> > > > > >
> > > > > > Did you looked at my logs?
> > > > >
> > > > > I checked your dmesg log, found the acpi_os_name kernel
> > > > > parameter is :
> > > > >
> > > > > [0.00] Command line:
> > > > > BOOT_IMAGE=/vmlinuz-3.2.0-4-generic
> > > > > root=UUIDNc6272a-8551-40f3-a1b1-3e10984f3e69 ro
> > > > > pcie_aspm=force
> > > > > acpi.debug_level=0x2 acpi.debug_layer=0x
> > > > > "acpi_os_name=Microsoft Windows NT" splash vt.handoff=7
> > > > >
> > > > > We still need by-pass the os name check in DSDT when test
> > > > > function key,> > > >
> > > > > please help to feed:
> > > > > acpi_os_name="Windows 2009"
> > > > >
> > > > > And,
> > > > > looks like the acpi debug level not enough, please kindly
> > > > > change acpi> > > >
> > > > > debug parameter to:
> > > > > acpi.debug_level=0xF acpi.debug_layer=0x
> > > > > log_buf_len=5M
> > > > >
> > > > > summary:
> > > > > acpi.debug_level=0xF acpi.debug_layer=0x
> > > > > log_buf_len=5M
> > > > > acpi_os_name="Windows 2009"
> > > >
> > > > Forgot remind,
> > > > please remember press brightness function key a couple of
> > > > times before you dump the dmesg and messages log.
> > > >
> > > >
> > > > Thanks a lot!
> > > > Joey Lee
> > >
> > > Hello,
> > >
> > > there was no acpi log, so I recompiled ubuntu kernel with
> > > CONFIG_ACPI_DEBUG=y and CONFIG_ACPI_DEBUG_FUNC_TRACE. Then I
> > > started kernel with your params.
> > >
> > > Now I'm attaching very long debug output. I belive it will be
> > > now usefull.
> > >
> > > Pressing brightness keys did not show anything in log.
> > >
> > > After writing 0 to /sys/class/backlight/acpi_video0/brightness
> > > in log appear: [ 57.675070] [ACPI Debug] Integer
> > > 0x000B ...
> > >
> > > And after writing 10:
> > > [ 99.865208] [ACPI Debug] Integer 0x0048
> > > [ 99.865295] evmisc-0120 [4294967289]
> > > ev_queue_notify_reques:
> > > Dispatching Notify on [DGFX] Node 880136246c80 Value 0xD0
> > > (**Device Specific**) [ 99.865350]video-1474 [4294967289]
> > > video_bus_notify> >
> > > : Unsupported event [0xd0]
> >
> > Do you need more logs? Or is this enought?
>
> Yes, as you point out, this is a doubt for video bus received 0xD0
> event but nobody take care it.
>
> Traced dsdt of EliteBook 8460p from you, the _BCM like this:
>
> Method (_BCM, 1, Serialized)/* ATI _BCM, per
> log, run this _BCM */ {
> Store (\_SB.BCM (Arg0), Local0) /* set next level,
> normally return 0x1 if XP sp2 or later */ If (Local0)
> /* if XP sp2 or later */ {
> Store (BRID, Local1)
> If (LEqual (SBRV (), 0x00)) /* normally SBRV
> return 1, will not emit SMI */ {
> \_SB.SSMI (0xEA74, 0x04, Local1, 0x00, 0x00)
> }
>
> Signal (\_SB.BEVT) /* emit BEVT event, HKFR
> (HotkeyFunctionResponse) waiting it, but why? */ }
> }
>
> _BCM call SBRV to setup brightness value to variable ABRI:
>
> Method (SBRV, 0, Serialized)/* call by ATI _BCM */
> {
> Store (\_SB.SBRC (), ABRI) /* SBRC() return the
> brightness value, why store to ABRI? only used in PEGP.DGFX.AFN2 */
> Or (PSBR, 0x80, PSBR)
> Notify (^, 0xD0)/* notify method's parent:
> PEGP.DGFX by 0xD0 */ Return (0x01) /*
> normally return 1 */ }The PEGP.DGFX acpi device was binding to
> acpi/video driver, the above ASL code emit a 0xD0 bus event to
> video.c but cann't process it. Even we add a new bus event in
> video.c and generate a acpi event, there still need another acpi
> driver should take care it.
>
> I thought this acpi event might need take care by radeon drm, but I
> am not good for radeon, need more help.
>
> Per your acpi debug log, the brightness value was changed normally
> when you access _BCM:
>
> 83133 Jan 20 17:17:51 Pali-EliteBook kernel: [ 57.674669] ACPI:
> Execute Method [\_SB_.PCI0.PEGP.DGFX.LCD_._BCM] (Node 8
> 801362472a8) # start test _BCM manually 83134 Jan 20 17:17:51
> Pali-EliteBook kernel: [ 57.674736] exregion-0199 [01]
> ex_system_memory_s
Re: Fwd: Brightness on HP EliteBook 8460p
於 二，2012-03-20 於 23:03 +0100，Pali Rohár 提到：
> >
> > Another doubt is the latest statement in _BCM, it emit a BEVT event:
> >
> > Signal (\_SB.BEVT)
> >
> > Only HKFR(HotkeyFunctionResponse) method is waiting this event, it
> > should related to how the HP implement brightness function key on
> > Windows through wmi.
> >
> > Of course this issue really close related to video driver, even
> > more, we might need to know hp wmi for how to implement on Windows.
> >
> > Unfortunately, sorry for I don't have any solution to you, now, I
> > will continue to trace and find any support from other experts.
> >
> >
> > Thanks a lot!
> > Joey Lee
>
> Hi!
>
> now I found that ALS button which enable/disable ambient light sensor
> working with linux and ALS can also decrease/increase brightness.
>
> ALS can be enabled or disabled via WMI (acpi) on linux too. I found
> function which enable ALS in linux kernel. See source code of function
> set_als in hp-wmi.c: http://tomoyo.sourceforge.jp/cgi-
> bin/lxr/source/drivers/platform/x86/hp-wmi.c#L443
>
> This function can enable ALS which can decrease brightness (but only
> to specific one level) via WMI. And WMI is ACPI extension, so maybe it
> is really possible to change brightness via acpi without DRI support.
>
> But I do not WMI, ACPI and DSDT code. Can you try to decode what is
> called in acpi when that set_als function in hp-wmi is called? I think
> here in acpi can be some magic which can manipulate with display
> brightness. At least ACPI must call somewhat to change brightness...
>
> Note: Enabling ALS on my notebook change brightness to some specific
> level and disabling ALS will revert brightness back. From userspace
> ALS can be enabled/disabled via this sysfs entry:
> /sys/devices/platform/hp-wmi/als
>
> --
> Pali Rohár
> pali.ro...@gmail.com
Traced the your dsdt from 8460p.
Let's see "set ALS" first, when set ALS enable, BIOS didn't _eat_ any
input value for brightness level:
Method (WHCM, 2, NotSerialized)
{
CreateDWordField (Arg1, 0x00, SNIN) /* signature */
CreateDWordField (Arg1, 0x04, COMD) /* command = write ? 0x2 : 0x1
*/
CreateDWordField (Arg1, 0x08, CMTP) /* commandtype */
CreateDWordField (Arg1, 0x0C, DASI)
Store ("HandleWMICommand Enter", Debug)
...
If (LEqual (COMD, 0x02))/* command write */
{
Store ("write BIOS command", Debug)
If (LEqual (CMTP, 0x03))/* write HPWMI_ALS_QUERY 0x3 */
{
Store (^WSAL (DDWD), Local2) /* call ^WSAL and feed DDWD */
Store (0x00, RTCD)
}
Method (WSAL, 1, NotSerialized) /* write HPWMI_ALS_QUERY 0x3 */
{
If (LEqual (PRDT, 0x03))
{
Return (Package (0x02)
{
0x04,
0x00
})
}
\_SB.SSMI (0xEA75, 0x02, 0x03, 0x574D4953, 0x00) /* emit SMI,
BIOS code take job but didn't feed Arg0 to BIOS */
Return (WFDA ())
}
Everything handle by BIOS function after emit SMI event, and it didn't
give BIOS any input value of brightness.
So, didn't find any way to change brightness through set ALS.
Then, I found another interesting command for 'write brightness', hp-wmi
doesn't have implementation for this command:
If (LEqual (CMTP, 0x06))/* set brightness? */
{
Store ("write Brightness", Debug)
Store (^SBBC (DDWD), Local2)/* call DDWD */
Store (Local2, Debug)
Store (0x00, RTCD)
}
Method (SBBC, 1, NotSerialized) /* write brighenss? didn't do
anything? */
{
Return (Package (0x02) /* just only return a package */
{
0x04,
0x00
})
}
Unfortunately, the 0x06 command also doesn't do anything for change
brightness on your machine.
Sorry! Didn't find any way can change brightness on your machine unless
we have drm driver support ATI acpi events.
Thanks a lot!
Joey Lee
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[PATCH] dma-buf: add support for kernel cpu access
Big differences to other contenders in the field (like ion) is
that this also supports highmem, so we have to split up the cpu
access from the kernel side into a prepare and a kmap step.
Prepare is allowed to fail and should do everything required so that
the kmap calls can succeed (like swapin/backing storage allocation,
flushing, ...).
More in-depth explanations will follow in the follow-up documentation
patch.
Changes in v2:
- Clear up begin_cpu_access confusion noticed by Sumit Semwal.
- Don't automatically fallback from the _atomic variants to the
non-atomic variants. The _atomic callbacks are not allowed to
sleep, so we want exporters to make this decision explicit. The
function signatures are explicit, so simpler exporters can still
use the same function for both.
- Make the unmap functions optional. Simpler exporters with permanent
mappings don't need to do anything at unmap time.
Changes in v3:
- Adjust the WARN_ON checks for the new ->ops functions as suggested
by Rob Clark and Sumit Semwal.
- Rebased on top of latest dma-buf-next git.
Changes in v4:
- Fixup a missing - in a return -EINVAL; statement.
Signed-Off-by: Daniel Vetter
---
drivers/base/dma-buf.c | 124 ++-
include/linux/dma-buf.h | 59 ++
2 files changed, 182 insertions(+), 1 deletions(-)
diff --git a/drivers/base/dma-buf.c b/drivers/base/dma-buf.c
index 5641b9c..07cbbc6 100644
--- a/drivers/base/dma-buf.c
+++ b/drivers/base/dma-buf.c
@@ -80,7 +80,9 @@ struct dma_buf *dma_buf_export(void *priv, const struct
dma_buf_ops *ops,
if (WARN_ON(!priv || !ops
|| !ops->map_dma_buf
|| !ops->unmap_dma_buf
- || !ops->release)) {
+ || !ops->release
+ || !ops->kmap_atomic
+ || !ops->kmap)) {
return ERR_PTR(-EINVAL);
}
@@ -284,3 +286,123 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment
*attach,
direction);
}
EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment);
+
+
+/**
+ * dma_buf_begin_cpu_access - Must be called before accessing a dma_buf from
the
+ * cpu in the kernel context. Calls begin_cpu_access to allow exporter-specific
+ * preparations. Coherency is only guaranteed in the specified range for the
+ * specified access direction.
+ * @dma_buf: [in]buffer to prepare cpu access for.
+ * @start: [in]start of range for cpu access.
+ * @len: [in]length of range for cpu access.
+ * @direction: [in]length of range for cpu access.
+ *
+ * Can return negative error values, returns 0 on success.
+ */
+int dma_buf_begin_cpu_access(struct dma_buf *dmabuf, size_t start, size_t len,
+enum dma_data_direction direction)
+{
+ int ret = 0;
+
+ if (WARN_ON(!dmabuf))
+ return -EINVAL;
+
+ if (dmabuf->ops->begin_cpu_access)
+ ret = dmabuf->ops->begin_cpu_access(dmabuf, start, len,
direction);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(dma_buf_begin_cpu_access);
+
+/**
+ * dma_buf_end_cpu_access - Must be called after accessing a dma_buf from the
+ * cpu in the kernel context. Calls end_cpu_access to allow exporter-specific
+ * actions. Coherency is only guaranteed in the specified range for the
+ * specified access direction.
+ * @dma_buf: [in]buffer to complete cpu access for.
+ * @start: [in]start of range for cpu access.
+ * @len: [in]length of range for cpu access.
+ * @direction: [in]length of range for cpu access.
+ *
+ * This call must always succeed.
+ */
+void dma_buf_end_cpu_access(struct dma_buf *dmabuf, size_t start, size_t len,
+ enum dma_data_direction direction)
+{
+ WARN_ON(!dmabuf);
+
+ if (dmabuf->ops->end_cpu_access)
+ dmabuf->ops->end_cpu_access(dmabuf, start, len, direction);
+}
+EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access);
+
+/**
+ * dma_buf_kmap_atomic - Map a page of the buffer object into kernel address
+ * space. The same restrictions as for kmap_atomic and friends apply.
+ * @dma_buf: [in]buffer to map page from.
+ * @page_num: [in]page in PAGE_SIZE units to map.
+ *
+ * This call must always succeed, any necessary preparations that might fail
+ * need to be done in begin_cpu_access.
+ */
+void *dma_buf_kmap_atomic(struct dma_buf *dmabuf, unsigned long page_num)
+{
+ WARN_ON(!dmabuf);
+
+ return dmabuf->ops->kmap_atomic(dmabuf, page_num);
+}
+EXPORT_SYMBOL_GPL(dma_buf_kmap_atomic);
+
+/**
+ * dma_buf_kunmap_atomic - Unmap a page obtained by dma_buf_kmap_atomic.
+ * @dma_buf: [in]buffer to unmap page from.
+ * @page_num: [in]page in PAGE_SIZE units to unmap.
+ * @vaddr: [in]kernel space pointer obtained from dma_buf_kmap_atomic.
+ *
+ * This call must always succeed.
+ */
+void dma_buf_kunmap_atomi
[PATCH v2 09/14] drm/exynos: add G2D driver
On 03/19/2012 09:25 PM, Dave Airlie wrote: > On Fri, Mar 16, 2012 at 9:47 AM, Inki Dae wrote: >> From: Joonyoung Shim >> >> The G2D is a 2D graphic accelerator that supports Bit Block Transfer. >> This G2D driver is exynos drm specific and supports only G2D(version >> 4.1) of later Exynos series from Exynos4X12 because supporting DMA. > So just to make sure I understand, userspace generates two command > streams, one containing registers that don't need base addresses > and one containing registers that do contain it. > > Now tell me how this address security wise, since non-root users have > the ability to use this interface. > > can userspace put registers that require a base address into the first > command stream and specify any phy addr in the system? Right, it's possible scenario. I will add codes to check it. > If not, please > explain in comments where this is blocked. Where is the list of > registers the first command stream and second command stream can > access specified? > > I'm not really happy about this appearing so late on the radar for > 3.4, you really want new major userspace security features to turn up > a lot earlier for review. I post the patch to get the review like this and i think time posting patch can be open always. If the patch has serious problem, certainly don't apply it. I don't want it too, but i will try to solve it and resend updated patch. Thanks.
Why do flush page cache twice when change TT's cache attribute
Can I do the optimization like:
if (ttm->caching_state == tt_cached)
-drm_clflush_pages(ttm->pages, ttm->num_pages);
+for (i = 0; i < ttm->num_pages; ++i)
+ if (PageHighMem(ttm->pages[i]))
+drm_clflush_pages(&ttm->pages[i], 1);
only do flush cache when high memory and leave the linear memory flush in
function set_memory_uc/wc?
2012/3/20 Jerome Glisse
> On Mon, 2012-03-19 at 23:11 +0800, Scott Fang wrote:
> > In function ttm_tt_set_caching
> > ,,,
> >
> > if (ttm->caching_state == tt_cached)
> > drm_clflush_pages(ttm->pages, ttm->num_pages);
> >
> > for (i = 0; i < ttm->num_pages; ++i) {
> > cur_page = ttm->pages[i];
> > if (likely(cur_page != NULL)) {
> > ret = ttm_tt_set_page_caching(cur_page,
> > ttm->caching_state,
> > c_state);
> > if (unlikely(ret != 0))
> > goto out_err;
> > }
> > }
> >
> > ttm->caching_state = c_state;
> >
> > return 0;
> >
> >
> > drm_clflush_pages flush cache one time.
> > then in the following function
> > ttm_tt_set_page_caching->set_memory_wc->change_page_attr_set: in this
> > function may flush page cache again.
> >
> > Does the code do some abundant flush, or there is some trick to these
> > codes?
> >
> > Thanks for the answer in advance.
>
> Yes there might be redundant flushing.
>
> Cheers,
> Jerome
>
>
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[PATCH] gpu: schedule gma500 stub driver for feature removal
In v3.3, the gma500 drm driver moved from staging to drm group by Alan Cox's 3abcf41fb patch. the gma500 drm driver should control brightness well and don't need gma500 stub driver anymore. So, my plan is remove gma500 stub driver at Dec. 2012. Signed-off-by: Lee, Chun-Yi --- Documentation/feature-removal-schedule.txt | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index a0ffac0..219d6f1 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -524,3 +524,14 @@ Files: arch/arm/mach-at91/at91cap9.c Why: The code is not actively maintained and platforms are now hard to find. Who: Nicolas Ferre Jean-Christophe PLAGNIOL-VILLARD + + + +What: Intel GMA500 Stub Driver +When: December 2012 +Why: In v3.3, the gma500 drm driver moved from staging to drm group by + Alan Cox's 3abcf41fb patch. the gma500 drm driver should control + brightness well and don't need gma500 stub driver anymore. + + So, my plan is remove gma500 stub driver at Dec. 2012. +Who: Lee, Chun-Yi -- 1.6.0.2
[PATCH v2 00/14] updated exynos-drm-next.
On Fri, Mar 16, 2012 at 9:47 AM, Inki Dae wrote: > Hi, Dave and all. Hi Inki, I've taken most of these patches except for the G2D and Virtual drivers, If you can make the virtual driver rebase without G2D I don't see an issue with merging it, it didn't seem to apply cleanly here. But I don't think G2D is close enough for this merge window considering the security issues with exposing DMA engines without a lot of review. Dave.
[PATCH 1/5] drm: add drm_property_change_is_valid
From: Paulo Zanoni
Move code from drm_mode_connector_property_set_ioctl to a new
function, so we can reuse this code when we add crtc properties.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c | 41 +
1 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6fdaf6f..1cadc11 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2910,6 +2910,26 @@ int drm_mode_connector_update_edid_property(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_mode_connector_update_edid_property);
+static int drm_property_change_is_valid(struct drm_property *property,
+ __u64 value)
+{
+ if (property->flags & DRM_MODE_PROP_IMMUTABLE)
+ return 0;
+ if (property->flags & DRM_MODE_PROP_RANGE) {
+ if (value < property->values[0])
+ return 0;
+ if (value > property->values[1])
+ return 0;
+ return 1;
+ } else {
+ int i;
+ for (i = 0; i < property->num_values; i++)
+ if (property->values[i] == value)
+ return 1;
+ return 0;
+ }
+}
+
int drm_mode_connector_property_set_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
{
@@ -2946,28 +2966,9 @@ int drm_mode_connector_property_set_ioctl(struct
drm_device *dev,
}
property = obj_to_property(obj);
- if (property->flags & DRM_MODE_PROP_IMMUTABLE)
+ if (!drm_property_change_is_valid(property, out_resp->value))
goto out;
- if (property->flags & DRM_MODE_PROP_RANGE) {
- if (out_resp->value < property->values[0])
- goto out;
-
- if (out_resp->value > property->values[1])
- goto out;
- } else {
- int found = 0;
- for (i = 0; i < property->num_values; i++) {
- if (property->values[i] == out_resp->value) {
- found = 1;
- break;
- }
- }
- if (!found) {
- goto out;
- }
- }
-
/* Do DPMS ourselves */
if (property == connector->dev->mode_config.dpms_property) {
if (connector->funcs->dpms)
--
1.7.9.1
[PATCH 2/5] drm: WARN() when drm_connector_attach_property fails
From: Paulo Zanoni
Also return void instead of int. We have more than 100 callers and
no one checks for the return value.
If this function fails the property won't be exposed by the get/set
ioctls, but we should probably survive. If this starts happening,
the solution will be to increase DRM_CONNECTOR_MAX_PROPERTY and
recompile the Kernel.
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c |8 +++-
include/drm/drm_crtc.h |4 ++--
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 1cadc11..6260fc3 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2659,7 +2659,7 @@ void drm_property_destroy(struct drm_device *dev, struct
drm_property *property)
}
EXPORT_SYMBOL(drm_property_destroy);
-int drm_connector_attach_property(struct drm_connector *connector,
+void drm_connector_attach_property(struct drm_connector *connector,
struct drm_property *property, uint64_t init_val)
{
int i;
@@ -2668,13 +2668,11 @@ int drm_connector_attach_property(struct drm_connector
*connector,
if (connector->property_ids[i] == 0) {
connector->property_ids[i] = property->base.id;
connector->property_values[i] = init_val;
- break;
+ return;
}
}
- if (i == DRM_CONNECTOR_MAX_PROPERTY)
- return -EINVAL;
- return 0;
+ WARN(1, "Failed to attach connector property\n");
}
EXPORT_SYMBOL(drm_connector_attach_property);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index 2a0872c..21681fe 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -907,8 +907,8 @@ extern int drmfb_remove(struct drm_device *dev, struct
drm_framebuffer *fb);
extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX,
int maxY);
extern bool drm_crtc_in_use(struct drm_crtc *crtc);
-extern int drm_connector_attach_property(struct drm_connector *connector,
- struct drm_property *property, uint64_t
init_val);
+extern void drm_connector_attach_property(struct drm_connector *connector,
+ struct drm_property *property,
uint64_t init_val);
extern struct drm_property *drm_property_create(struct drm_device *dev, int
flags,
const char *name, int
num_values);
extern struct drm_property *drm_property_create_enum(struct drm_device *dev,
int flags,
--
1.7.9.1
[PATCH 3/5] drm: add CRTC properties
From: Paulo Zanoni
Code based on the connector properties code.
Two new ioctls:
- DRM_IOCTL_MODE_CRTC_GETPROPERTIES
- DRM_IOCTL_MODE_CRTC_SETPROPERTY
The i915 driver needs this for the rotation and overscan compensation
properties. Other drivers might need this too.
v2: replace BUG_ON() for WARN(), fix bugs, add functions to get/set
the value
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/drm_crtc.c | 150
drivers/gpu/drm/drm_drv.c |4 +-
include/drm/drm.h |2 +
include/drm/drm_crtc.h | 28 -
include/drm/drm_mode.h | 13
5 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6260fc3..df00c29 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2712,6 +2712,55 @@ int drm_connector_property_get_value(struct
drm_connector *connector,
}
EXPORT_SYMBOL(drm_connector_property_get_value);
+void drm_crtc_attach_property(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t init_val)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == 0) {
+ crtc->property_ids[i] = property->base.id;
+ crtc->property_values[i] = init_val;
+ return;
+ }
+ }
+
+ WARN(1, "Failed to attach crtc property\n");
+}
+EXPORT_SYMBOL(drm_crtc_attach_property);
+
+int drm_crtc_property_set_value(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t value)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == property->base.id) {
+ crtc->property_values[i] = value;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(drm_crtc_property_set_value);
+
+int drm_crtc_property_get_value(struct drm_crtc *crtc,
+ struct drm_property *property, uint64_t *val)
+{
+ int i;
+
+ for (i = 0; i < DRM_CRTC_MAX_PROPERTY; i++) {
+ if (crtc->property_ids[i] == property->base.id) {
+ *val = crtc->property_values[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+EXPORT_SYMBOL(drm_crtc_property_get_value);
+
int drm_mode_getproperty_ioctl(struct drm_device *dev,
void *data, struct drm_file *file_priv)
{
@@ -2983,6 +3032,107 @@ out:
return ret;
}
+int drm_mode_crtc_get_properties_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
+{
+ struct drm_mode_crtc_get_properties *arg = data;
+ struct drm_mode_object *obj;
+ struct drm_crtc *crtc;
+ int ret = 0;
+ int i;
+ int copied = 0;
+ int props_count = 0;
+ uint32_t __user *props_ptr;
+ uint64_t __user *prop_values_ptr;
+
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ return -EINVAL;
+
+ mutex_lock(&dev->mode_config.mutex);
+
+ obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
+ if (!obj) {
+ ret = -EINVAL;
+ goto out;
+ }
+ crtc = obj_to_crtc(obj);
+
+ for (props_count = 0; props_count < DRM_CRTC_MAX_PROPERTY &&
+crtc->property_ids[props_count] != 0; props_count++)
+ ;
+
+ /* This ioctl is called twice, once to determine how much space is
+* needed, and the 2nd time to fill it. */
+ if ((arg->count_props >= props_count) && props_count) {
+ copied = 0;
+ props_ptr = (uint32_t __user *)(unsigned long)(arg->props_ptr);
+ prop_values_ptr = (uint64_t __user *)(unsigned long)
+ (arg->prop_values_ptr);
+ for (i = 0; i < props_count; i++) {
+ if (put_user(crtc->property_ids[i],
+props_ptr + copied)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ if (put_user(crtc->property_values[i],
+prop_values_ptr + copied)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ copied++;
+ }
+ }
+ arg->count_props = props_count;
+out:
+ mutex_unlock(&dev->mode_config.mutex);
+ return ret;
+}
+
+int drm_mode_crtc_set_property_ioctl(struct drm_device *dev, void *data,
+struct drm_file *file_priv)
+{
+ struct drm_mode_crtc_set_property *arg = data;
+ struct drm_mode_object *obj;
+ struct drm_property *property;
[PATCH 4/5] drm/i915: add 'rotation' CRTC property
From: Paulo Zanoni
This property is needed so we can inform the KVMr feature about our
current rotation: whenever we change the rotation, we should change
that property so that the KVMr knows that the screen is rotated.
How to reproduce the problem:
- on an AMT machine, enable KVM
- boot the machine, use xrandr to rotate the display
- use VNC to connect to the KVM
- try to use the mouse
v2: only create the property once
Signed-off-by: Paulo Zanoni
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h |5 +++
drivers/gpu/drm/i915/intel_display.c | 66 ++
3 files changed, 72 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7a00b7..7994c4f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ typedef struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
+ struct drm_property *rotation_property;
} drm_i915_private_t;
enum hdmi_force_audio {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..79e8b12 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2407,6 +2407,11 @@
#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
+#define PIPECONF_ROTATION_MASK (3 << 14)
+#define PIPECONF_ROTATION_0 (0 << 14)
+#define PIPECONF_ROTATION_90 (1 << 14)
+#define PIPECONF_ROTATION_180(2 << 14)
+#define PIPECONF_ROTATION_270(3 << 14)
#define PIPECONF_BPP_MASK(0x00e0)
#define PIPECONF_BPP_8 (0<<5)
#define PIPECONF_BPP_10 (1<<5)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 683002fb..4842de8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7625,6 +7625,50 @@ static void intel_crtc_reset(struct drm_crtc *crtc)
intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
}
+static void intel_crtc_set_rotation(struct drm_crtc *crtc,
+ uint64_t rotation)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int reg = PIPECONF(intel_crtc->pipe);
+ u32 val = I915_READ(reg);
+
+ val &= ~PIPECONF_ROTATION_MASK;
+
+ switch (rotation) {
+ case 0:
+ val |= PIPECONF_ROTATION_0;
+ break;
+ case 90:
+ val |= PIPECONF_ROTATION_90;
+ break;
+ case 180:
+ val |= PIPECONF_ROTATION_180;
+ break;
+ case 270:
+ val |= PIPECONF_ROTATION_270;
+ break;
+ default:
+ DRM_ERROR("Unsupported rotation: %Lu\n", rotation);
+ val |= PIPECONF_ROTATION_0;
+ }
+
+ I915_WRITE(reg, val);
+}
+
+static int intel_crtc_set_property(struct drm_crtc *crtc,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (property == dev_priv->rotation_property)
+ intel_crtc_set_rotation(crtc, val);
+ return 0;
+}
+
static struct drm_crtc_helper_funcs intel_helper_funcs = {
.dpms = intel_crtc_dpms,
.mode_fixup = intel_crtc_mode_fixup,
@@ -7643,8 +7687,27 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
.set_config = drm_crtc_helper_set_config,
.destroy = intel_crtc_destroy,
.page_flip = intel_crtc_page_flip,
+ .set_property = intel_crtc_set_property,
};
+static void intel_attach_rotation_property(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_property *prop;
+
+ prop = dev_priv->rotation_property;
+ if (prop == NULL) {
+ prop = drm_property_create_range(dev, 0, "rotation", 0, 359);
+ if (prop == NULL)
+ return;
+
+ dev_priv->rotation_property = prop;
+ }
+
+ drm_crtc_attach_property(crtc, prop, 0);
+}
+
static void intel_crtc_init(struct drm_device *dev, int pipe)
{
drm_i915_private_t *dev_priv = dev->dev_private;
@@ -7664,6 +7727,9 @@ static void intel_crtc_init(struct drm_device *dev, int
pipe)
intel_crtc->lut_b[i] = i;
}
+ if (INTEL_INFO(dev)->gen >= 5)
+ intel_attach_rotation_property(&intel_crtc->base);
+
/* Swap pipes & planes for FBC on pre-96
