date:20100525

[patch] drm/nouveau: off by one in init_i2c_device_find()

2010-05-25 Thread Dan Carpenter

dcb->i2c[] has DCB_MAX_NUM_I2C_ENTRIES entries.

Signed-off-by: Dan Carpenter 

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c 
b/drivers/gpu/drm/nouveau/nouveau_bios.c
index e7e69cc..bf92a1e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -814,7 +814,7 @@ init_i2c_device_find(struct drm_device *dev, int i2c_index)
if (i2c_index == 0x81)
i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
 
-   if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) {
+   if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
return NULL;
}
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[PATCH] drm/edid: Allow non-fatal checksum errors in CEA blocks

2010-05-25 Thread Adam Jackson

Switches will try to update the topology address and not correctly fix
up the checksum, so just let it slide.

https://bugs.freedesktop.org/28229

Signed-off-by: Adam Jackson 
---
 drivers/gpu/drm/drm_edid.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f569ae8..c198186 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -147,7 +147,10 @@ drm_edid_block_valid(u8 *raw_edid)
csum += raw_edid[i];
if (csum) {
DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
-   goto bad;
+
+   /* allow CEA to slide through, switches mangle this */
+   if (raw_edid[0] != 0x02)
+   goto bad;
}
 
/* per-block-type checks */
-- 
1.7.0.1

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Re: build warning in radeon/atombios_crtc.c: pll' may be used uninitialized

2010-05-25 Thread Alex Deucher

On Tue, May 25, 2010 at 4:25 PM, Stefan Richter
 wrote:
> Hi,
>
> seen with gcc 4.3.4 in current git (although 2.6.34 should show that
> too):
>
> drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
> drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
> uninitialized in this function
>
> It seems to require a 'make CONFIG_DEBUG_SECTION_MISMATCH=y' to trigger
> this warning; don't know why.
>
> Perhaps add a 'default:' case to the switch block?

Adding a default to the last case should be fine.

Alex

> --
> Stefan Richter
> -=-==-=- -=-= ==--=
> http://arcgraph.de/sr/
>
>
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[Bug 25616] X1600:M56P Second suspend hangs the system

2010-05-25 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=25616

Andrea Iob  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution||WORKSFORME

--- Comment #9 from Andrea Iob  2010-05-25 13:56:35 PDT ---
With Linux 2.6.34 and KMS suspend-to-ram works fine!
I think the bug can be closed.

Thanks guys for your work!

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Re: [PATCH] drm/radeon/kms: suppress a build warning (unused variable)

2010-05-25 Thread Alex Deucher

On Tue, May 25, 2010 at 5:03 PM, Stefan Richter
 wrote:
> At least 'make CONFIG_DEBUG_SECTION_MISMATCH=y' causes
>  drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
>  drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
> uninitialized in this function
> which has the looks of a falso positive.
>
> Add a default: case so that gcc rests assured that all possible pll_id's are 
> covered.
> Keep the present cases that fall through to the default one for 
> self-documentation.
>
> Signed-off-by: Stefan Richter 

looks good.

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/radeon/atombios_crtc.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
> b/drivers/gpu/drm/radeon/atombios_crtc.c
> index 03dd6c4..f3f2827 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -707,6 +707,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, 
> struct drm_display_mode
>                break;
>        case ATOM_DCPLL:
>        case ATOM_PPLL_INVALID:
> +       default:
>                pll = &rdev->clock.dcpll;
>                break;
>        }
> --
> Stefan Richter
> -=-==-=- -=-= ==--=
> http://arcgraph.de/sr/
>
>
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This set of drm patches implements support for 1D and 2D tiling on

2010-05-25 Thread Alex Deucher

First two patches enable scanout from tiled surfaces.
Third patch updates the CS checker to deal properly with tiling.
Fourth patch fixes surface checking for both tiled and non-tiled
pitch, height, and offset alignment.
Fifth patch adds a new info query for the MC tile config which is
required for CPU access to tiled surfaces.

To enable tiling, you need these drm patches as well as ddx and mesa
patches. On r6xx we expose 2 tiling modes 1D and 2D which map to the
MACRO and MICRO tiling flags we used on previous asics.  Unlike
previous asics, you cannot have macro tiled micro linear.

1D tiles are roughly equivalent to MICRO tiles on previous asics.
The 1D tile pattern is not dependant on the MC configuration.  2D
tiling is roughly equivalent to macro tiled micro tiled on previous
asics.  Macro tiles are made up of micro tiles and the macro tile
pattern is based on the MC configuration.

2D tiling should be used for optimal performance, however there are
some cases in the mesa de-tiling algorithm that don't work properly
yet with 2D tiling, so for now when you enable tiling in the ddx, it
will only enable 1D tiling.  To play with 2D tiling, select MACRO
rather then MICRO in radeon_dri2.c in the ddx.

Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
that would require the use of wfb or tiled to untiled blits for CPU
access. Tiled to untiled blits works (I've tested it), but shows an
approximately 40% performance hit for software fallbacks (tested with
non-aa text in x11perf).  I'm not sure what how that compared to sw
detiling with wfb since the algo is pretty complex.  In practice, I
didn't notice any difference in performance on the desktop.

It might also be useful to benchmark using LINEAR_ALGINED rather than
LINEAR_GENERAL for linear surfaces as it is supposedly more efficient.

Alex
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[PATCH 1/5] drm/radeon/kms: Add crtc tiling setup support for r6xx/r7xx

2010-05-25 Thread Alex Deucher

Needed for scanning out of a tiled buffer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_crtc.c |   15 +++
 drivers/gpu/drm/radeon/r500_reg.h  |5 +
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 03dd6c4..171c551 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -978,11 +978,18 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int 
x, int y,
return -EINVAL;
}
 
-   if (tiling_flags & RADEON_TILING_MACRO)
-   fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+   if (rdev->family >= CHIP_R600) {
+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
+   else if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
+   } else {
+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
 
-   if (tiling_flags & RADEON_TILING_MICRO)
-   fb_format |= AVIVO_D1GRPH_TILED;
+   if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= AVIVO_D1GRPH_TILED;
+   }
 
if (radeon_crtc->crtc_id == 0)
WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/r500_reg.h 
b/drivers/gpu/drm/radeon/r500_reg.h
index 93c9a2b..6ac1f60 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -386,6 +386,11 @@
 #   define AVIVO_D1GRPH_TILED   (1 << 20)
 #   define AVIVO_D1GRPH_MACRO_ADDRESS_MODE  (1 << 21)
 
+#   define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL(0 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED(1 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1(2 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1(4 << 20)
+
 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
  * block and vice versa.  This applies to GRPH, CUR, etc.
  */
-- 
1.5.6.3

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[PATCH 2/5] drm/radeon/kms: Add crtc tiling setup support for evergreen

2010-05-25 Thread Alex Deucher

Needed for scanning out of a tiled buffer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_crtc.c |5 +
 drivers/gpu/drm/radeon/evergreen_reg.h |5 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 171c551..ed93d24 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -840,6 +840,11 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, 
int x, int y,
return -EINVAL;
}
 
+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= 
EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
+   else if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= 
EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
+
switch (radeon_crtc->crtc_id) {
case 0:
WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h 
b/drivers/gpu/drm/radeon/evergreen_reg.h
index af86af8..5a1759c 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -61,6 +61,11 @@
 #   define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
 #   define EVERGREEN_GRPH_FORMAT_RGB10  6
 #   define EVERGREEN_GRPH_FORMAT_BGR10  7
+#   define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
+#   define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL  0
+#   define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED  1
+#   define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1  2
+#   define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1  4
 #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
 #   define EVERGREEN_GRPH_ENDIAN_SWAP(x)(((x) & 0x3) << 0)
 #   define EVERGREEN_GRPH_ENDIAN_NONE   0
-- 
1.5.6.3

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[PATCH 3/5] drm/radeon/kms: add tiling support to the cs checker for r6xx/r7xx

2010-05-25 Thread Alex Deucher

Check for relocs for DB_DEPTH_INFO, CB_COLOR*_INFO, and texture
resources.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600_cs.c |   57 ++
 drivers/gpu/drm/radeon/r600d.h   |6 
 2 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c39c1bc..5cab1b4 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -725,7 +725,25 @@ static inline int r600_cs_check_reg(struct 
radeon_cs_parser *p, u32 reg, u32 idx
track->db_depth_control = radeon_get_ib_value(p, idx);
break;
case R_028010_DB_DEPTH_INFO:
-   track->db_depth_info = radeon_get_ib_value(p, idx);
+   if (r600_cs_packet_next_is_pkt3_nop(p)) {
+   r = r600_cs_packet_next_reloc(p, &reloc);
+   if (r) {
+   dev_warn(p->dev, "bad SET_CONTEXT_REG "
+"0x%04X\n", reg);
+   return -EINVAL;
+   }
+   track->db_depth_info = radeon_get_ib_value(p, idx);
+   ib[idx] &= C_028010_ARRAY_MODE;
+   track->db_depth_info &= C_028010_ARRAY_MODE;
+   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+   ib[idx] |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
+   track->db_depth_info |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
+   } else {
+   ib[idx] |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
+   track->db_depth_info |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
+   }
+   } else
+   track->db_depth_info = radeon_get_ib_value(p, idx);
break;
case R_028004_DB_DEPTH_VIEW:
track->db_depth_view = radeon_get_ib_value(p, idx);
@@ -758,8 +776,25 @@ static inline int r600_cs_check_reg(struct 
radeon_cs_parser *p, u32 reg, u32 idx
case R_0280B4_CB_COLOR5_INFO:
case R_0280B8_CB_COLOR6_INFO:
case R_0280BC_CB_COLOR7_INFO:
-   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
-   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   if (r600_cs_packet_next_is_pkt3_nop(p)) {
+   r = r600_cs_packet_next_reloc(p, &reloc);
+   if (r) {
+   dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", 
reg);
+   return -EINVAL;
+   }
+   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
+   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+   ib[idx] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
+   track->cb_color_info[tmp] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
+   } else if (reloc->lobj.tiling_flags & 
RADEON_TILING_MICRO) {
+   ib[idx] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
+   track->cb_color_info[tmp] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
+   }
+   } else {
+   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
+   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   }
break;
case R_028060_CB_COLOR0_SIZE:
case R_028064_CB_COLOR1_SIZE:
@@ -986,8 +1021,9 @@ static void r600_texture_size(unsigned nfaces, unsigned 
blevel, unsigned nlevels
  * the texture and mipmap bo object are big enough to cover this resource.
  */
 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 
idx,
-   struct radeon_bo *texture,
-   struct radeon_bo *mipmap)
+ struct radeon_bo *texture,
+ struct radeon_bo *mipmap,
+ u32 tiling_flags)
 {
u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
u32 word0, word1, l0_size, mipmap_size;
@@ -995,7 +1031,12 @@ static inline int r600_check_texture_resource(struct 
radeon_cs_parser *p,  u32 i
/* on legacy kernel we don't perform advanced check */
if (p->rdev == NULL)
return 0;
+
word0 = radeon_get_ib_value(p, idx + 0);
+   if (tiling_flags & RADEON_TILING_MACRO)
+   word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+   else if (tiling_flags & RAD

[PATCH 4/5] drm/radeon/kms: fix CS alignment checking for tiling

2010-05-25 Thread Alex Deucher

Covers, depth, cb, and textures. Hopefully I got this right.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600_cs.c |  172 ++---
 1 files changed, 139 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 5cab1b4..133f0da 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -25,6 +25,7 @@
  *  Alex Deucher
  *  Jerome Glisse
  */
+#include 
 #include "drmP.h"
 #include "radeon.h"
 #include "r600d.h"
@@ -166,7 +167,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 {
struct r600_cs_track *track = p->track;
-   u32 bpe = 0, pitch, slice_tile_max, size, tmp, height;
+   u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
volatile u32 *ib = p->ib->ptr;
 
if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
@@ -180,56 +181,67 @@ static inline int r600_cs_track_validate_cb(struct 
radeon_cs_parser *p, int i)
i, track->cb_color_info[i]);
return -EINVAL;
}
-   pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
+   /* pitch is the number of 8x8 tiles per row */
+   pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
if (!pitch) {
dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid 
(0x%08X)\n",
__func__, __LINE__, pitch, i, track->cb_color_size[i]);
return -EINVAL;
}
-   height = size / (pitch * bpe);
+   height = size / (pitch * 8 * bpe);
if (height > 8192)
height = 8192;
+   height &= ~0x7;
+   if (!height)
+   height = 8;
switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
case V_0280A0_ARRAY_LINEAR_GENERAL:
-   case V_0280A0_ARRAY_LINEAR_ALIGNED:
-   if (pitch & 0x3f) {
-   dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) 
invalid\n",
-   __func__, __LINE__, pitch, bpe, pitch * bpe);
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
-   if ((pitch * bpe) & (track->group_size - 1)) {
+   break;
+   case V_0280A0_ARRAY_LINEAR_ALIGNED:
+   pitch_align = (max((u32)64, (u32)(track->group_size / bpe)) / 
8) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+__func__, __LINE__, pitch);
+   return -EINVAL;
+   }
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
break;
case V_0280A0_ARRAY_1D_TILED_THIN1:
-   if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 
1)) {
+   pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe * 
track->nsamples))) / 8) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+__func__, __LINE__, pitch);
+   return -EINVAL;
+   }
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
-   height &= ~0x7;
-   if (!height)
-   height = 8;
break;
case V_0280A0_ARRAY_2D_TILED_THIN1:
-   if (pitch & ((8 * track->nbanks) - 1)) {
+   pitch_align = max((u32)track->nbanks,
+ (u32)(((track->group_size / 8) / (bpe * 
track->nsamples)) * track->nbanks)) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
__func__, __LINE__, pitch);
return -EINVAL;
}
-   tmp = pitch * 8 * bpe * track->nsamples;
-   tmp = tmp / track->nbanks;
-   if (tmp & (track->group_size - 1)) {
-   dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+   if ((height / 8) & (tr

[PATCH 5/5] drm/radeon/kms/r6xx+: add query for tile config

2010-05-25 Thread Alex Deucher

Userspace needs this information to access tiled
buffers via the CPU.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/evergreen.c  |1 +
 drivers/gpu/drm/radeon/r600.c   |2 +-
 drivers/gpu/drm/radeon/radeon.h |3 +++
 drivers/gpu/drm/radeon/radeon_drv.c |3 ++-
 drivers/gpu/drm/radeon/radeon_kms.c |   12 
 drivers/gpu/drm/radeon/rv770.c  |3 ++-
 include/drm/radeon_drm.h|1 +
 7 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 8c8e4d3..e220c7e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1104,6 +1104,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
rdev->config.evergreen.max_backends) &

EVERGREEN_MAX_BACKENDS_MASK));
 
+   rdev->config.evergreen.tile_config = gb_addr_config;
WREG32(GB_BACKEND_MAP, gb_backend_map);
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 44e96a2..dac2534 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1508,7 +1508,7 @@ void r600_gpu_init(struct radeon_device *rdev)
 
r600_count_pipe_bits((cc_rb_backend_disable &
   
R6XX_MAX_BACKENDS_MASK) >> 16)),
(cc_rb_backend_disable 
>> 16));
-
+   rdev->config.r600.tile_config = tiling_config;
tiling_config |= BACKEND_MAP(backend_map);
WREG32(GB_TILING_CONFIG, tiling_config);
WREG32(DCP_TILING_CONFIG, tiling_config & 0x);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5c9ce2b..78b59a7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -892,6 +892,7 @@ struct r600_asic {
unsignedtiling_nbanks;
unsignedtiling_npipes;
unsignedtiling_group_size;
+   unsignedtile_config;
struct r100_gpu_lockup  lockup;
 };
 
@@ -916,6 +917,7 @@ struct rv770_asic {
unsignedtiling_nbanks;
unsignedtiling_npipes;
unsignedtiling_group_size;
+   unsignedtile_config;
struct r100_gpu_lockup  lockup;
 };
 
@@ -941,6 +943,7 @@ struct evergreen_asic {
unsigned tiling_nbanks;
unsigned tiling_npipes;
unsigned tiling_group_size;
+   unsigned tile_config;
 };
 
 union radeon_asic_config {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 902d173..ece06a6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -45,9 +45,10 @@
  * - 2.2.0 - add r6xx/r7xx const buffer support
  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  * - 2.4.0 - add crtc id query
+ * - 2.5.0 - add tiling config query (r6xx+)
  */
 #define KMS_DRIVER_MAJOR   2
-#define KMS_DRIVER_MINOR   4
+#define KMS_DRIVER_MINOR   5
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c 
b/drivers/gpu/drm/radeon/radeon_kms.c
index 021572a..977447e 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -134,6 +134,18 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
return -EINVAL;
}
break;
+   case RADEON_INFO_TILING_CONFIG:
+   if (rdev->family >= CHIP_CEDAR)
+   value = rdev->config.evergreen.tile_config;
+   else if (rdev->family >= CHIP_RV770)
+   value = rdev->config.rv770.tile_config;
+   else if (rdev->family >= CHIP_R600)
+   value = rdev->config.r600.tile_config;
+   else {
+   DRM_DEBUG("tiling config is r6xx+ only!\n");
+   return -EINVAL;
+   }
+   break;
default:
DRM_DEBUG("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 253f24a..d285ca8 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -648,8 +648,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
r600_count_pipe_bits((cc_rb_backend_disable &

[PATCH 0/5] Add tiling support for r6xx/r7xx

2010-05-25 Thread Alex Deucher

This set of drm patches implements support for 1D and 2D tiling on
r6xx/r7xx chips and lays the groundwork for evergreen tiling
support.

First two patches enable scanout from tiled surfaces.
Third patch updates the CS checker to deal properly with tiling.
Fourth patch fixes surface checking for both tiled and non-tiled
pitch, height, and offset alignment.
Fifth patch adds a new info query for the MC tile config which is
required for CPU access to tiled surfaces.

To enable tiling, you need these drm patches as well as ddx and mesa
patches. On r6xx we expose 2 tiling modes 1D and 2D which map to the
MACRO and MICRO tiling flags we used on previous asics.  Unlike
previous asics, you cannot have macro tiled micro linear.

1D tiles are roughly equivalent to MICRO tiles on previous asics.
The 1D tile pattern is not dependant on the MC configuration.  2D
tiling is roughly equivalent to macro tiled micro tiled on previous
asics.  Macro tiles are made up of micro tiles and the macro tile
pattern is based on the MC configuration.

2D tiling should be used for optimal performance, however there are
some cases in the mesa de-tiling algorithm that don't work properly
yet with 2D tiling, so for now when you enable tiling in the ddx, it
will only enable 1D tiling.  To play with 2D tiling, select MACRO
rather then MICRO in radeon_dri2.c in the ddx.

Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
that would require the use of wfb or tiled to untiled blits for CPU
access. Tiled to untiled blits works (I've tested it), but shows an
approximately 40% performance hit for software fallbacks (tested with
non-aa text in x11perf).  I'm not sure what how that compared to sw
detiling with wfb since the algo is pretty complex.  In practice, I
didn't notice any difference in performance on the desktop.

It might also be useful to benchmark using LINEAR_ALGINED rather than
LINEAR_GENERAL for linear surfaces as it is supposedly more efficient.

Alex
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[PATCH 0/3] Add r6xx/r7xx tiling support to mesa

2010-05-25 Thread Alex Deucher

These patches along with the drm and ddx patches enable tiling
on r6xx/r7xx hardware.

Alex

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[PATCH 1/3] r600: add span support for 2D tiling

2010-05-25 Thread Alex Deucher

Requires tiling config ioctl support from the drm to use.
kms only.

Signed-off-by: Alex Deucher 
---
 .../drivers/dri/radeon/radeon_common_context.c |9 +-
 .../drivers/dri/radeon/radeon_common_context.h |7 +
 src/mesa/drivers/dri/radeon/radeon_screen.h|7 +
 src/mesa/drivers/dri/radeon/radeon_span.c  |  192 +++-
 4 files changed, 210 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c 
b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 94f4766..1cce032 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -650,6 +650,13 @@ radeon_update_renderbuffers(__DRIcontext *context, 
__DRIdrawable *drawable,
rb->base.Height = drawable->h;
rb->has_surface = 0;
 
+   /* r6xx+ tiling */
+   rb->tile_config = radeon->radeonScreen->tile_config;
+   rb->group_bytes = radeon->radeonScreen->group_bytes;
+   rb->num_channels = radeon->radeonScreen->num_channels;
+   rb->num_banks = radeon->radeonScreen->num_banks;
+   rb->r7xx_bank_op = radeon->radeonScreen->r7xx_bank_op;
+
if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
if (RADEON_DEBUG & RADEON_DRI)
fprintf(stderr, "(reusing depth buffer as 
stencil)\n");
@@ -678,7 +685,7 @@ radeon_update_renderbuffers(__DRIcontext *context, 
__DRIdrawable *drawable,
bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
if (tiling_flags & RADEON_TILING_MICRO)
bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
-   
+
}
 
if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h 
b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 5156c5d..3fd00eb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -93,6 +93,13 @@ struct radeon_renderbuffer
GLuint pf_pending;  /**< sequence number of pending flip */
GLuint vbl_pending;   /**< vblank sequence number of pending flip */
__DRIdrawable *dPriv;
+
+   /* r6xx+ tiling */
+   GLuint tile_config;
+   GLint group_bytes;
+   GLint num_channels;
+   GLint num_banks;
+   GLint r7xx_bank_op;
 };
 
 struct radeon_framebuffer
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 0d7e335..2b33201 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -112,6 +112,13 @@ typedef struct radeon_screen {
int kernel_mm;
drm_radeon_sarea_t *sarea;  /* Private SAREA data */
struct radeon_bo_manager *bom;
+
+   /* r6xx+ tiling */
+   GLuint tile_config;
+   GLint group_bytes;
+   GLint num_channels;
+   GLint num_banks;
+   GLint r7xx_bank_op;
 } radeonScreenRec, *radeonScreenPtr;
 
 #define IS_R100_CLASS(screen) \
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c 
b/src/mesa/drivers/dri/radeon/radeon_span.c
index 1adb609..9dfe2dd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -111,7 +111,6 @@ static GLubyte *r200_depth_4byte(const struct 
radeon_renderbuffer * rrb,
  * two main types:
  * - 1D (akin to macro-linear/micro-tiled on older asics)
  * - 2D (akin to macro-tiled/micro-tiled on older asics)
- * only 1D tiling is implemented below
  */
 #if defined(RADEON_R600)
 static inline GLint r600_1d_tile_helper(const struct radeon_renderbuffer * rrb,
@@ -208,12 +207,190 @@ static inline GLint r600_1d_tile_helper(const struct 
radeon_renderbuffer * rrb,
 return offset;
 }
 
+static inline GLint r600_log2(GLint n)
+{
+   GLint log2 = 0;
+
+   while (n >>= 1)
+   ++log2;
+   return log2;
+}
+
+static inline GLint r600_2d_tile_helper(const struct radeon_renderbuffer * rrb,
+   GLint x, GLint y, GLint is_depth, GLint 
is_stencil)
+{
+   GLint group_bytes = rrb->group_bytes;
+   GLint num_channels = rrb->num_channels;
+   GLint num_banks = rrb->num_banks;
+   GLint r7xx_bank_op = rrb->r7xx_bank_op;
+   /* */
+   GLint group_bits = r600_log2(group_bytes);
+   GLint channel_bits = r600_log2(num_channels);
+   GLint bank_bits = r600_log2(num_banks);
+   GLint element_bytes = rrb->cpp;
+   GLint num_samples = 1;
+   GLint tile_width = 8;
+   GLint tile_height = 8;
+   GLint tile_thickness = 1;
+   GLint macro_tile_width = num_banks;
+   GLint macro_tile_height = num_channels;
+   GLint pitch_elements = (rrb->pitch / element_bytes) / tile_width;
+   GLint height = rrb->base.Height / tile_height;
+   GL

[PATCH 2/3] r600: add new relocs for tiling support

2010-05-25 Thread Alex Deucher

Signed-off-by: Alex Deucher 
---
 src/mesa/drivers/dri/r600/r600_blit.c |   20 +++--
 src/mesa/drivers/dri/r600/r700_chip.c |   37 +++-
 2 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/r600/r600_blit.c 
b/src/mesa/drivers/dri/r600/r600_blit.c
index 172f85e..6196782 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -390,13 +390,20 @@ set_render_target(context_t *context, struct radeon_bo 
*bo, gl_format mesa_forma
 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 END_BATCH();
 
-BEGIN_BATCH_NO_AUTOSTATE(12);
+BEGIN_BATCH_NO_AUTOSTATE(9);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
-R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 END_BATCH();
 
+BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
+R600_OUT_BATCH_RELOC(0,
+bo,
+0,
+0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+END_BATCH();
+
 COMMIT_BATCH();
 
 }
@@ -1447,7 +1454,7 @@ set_default_state(context_t *context)
SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
 }
 
-BEGIN_BATCH_NO_AUTOSTATE(117);
+BEGIN_BATCH_NO_AUTOSTATE(114);
 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
 R600_OUT_BATCH(sq_config);
 R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
@@ -1477,7 +1484,6 @@ set_default_state(context_t *context)
  (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
 R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
 R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
-R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
 R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
 R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
@@ -1607,7 +1613,7 @@ unsigned r600_blit(GLcontext *ctx,
 /* Flush is needed to make sure that source buffer has correct data */
 radeonFlush(ctx);
 
-rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__);
+rcommonEnsureCmdBufSpace(&context->radeon, 305, __FUNCTION__);
 
 /* load shaders */
 load_shaders(context->radeon.glCtx);
@@ -1616,7 +1622,7 @@ unsigned r600_blit(GLcontext *ctx,
 return GL_FALSE;
 
 /* set clear state */
-/* 117 */
+/* 114 */
 set_default_state(context);
 
 /* shaders */
@@ -1632,7 +1638,7 @@ unsigned r600_blit(GLcontext *ctx,
 set_tex_sampler(context);
 
 /* dst */
-/* 27 */
+/* 31 */
 set_render_target(context, dst_bo, dst_mesaformat,
  dst_pitch, dst_width, dst_height, dst_offset);
 /* scissors */
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c 
b/src/mesa/drivers/dri/r600/r700_chip.c
index cefda3a..1e955b9 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -617,18 +617,25 @@ static void r700SendDepthTargetState(GLcontext *ctx, 
struct radeon_state_atom *a
 
r700SetDepthTarget(context);
 
-BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
+BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
-   R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
+   R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
-   R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 rrb->bo,
 r700->DB_DEPTH_BASE.u32All,
 0, RADEON_GEM_DOMAIN_VRAM, 0);
 END_BATCH();
+BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+   R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
+   R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
+   R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
+rrb->bo,
+r700->DB_DEPTH_INFO.u32All,
+0, RADEON_GEM_DOMAIN_VRAM, 0);
+END_BATCH();
 
if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
(context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
@@ -687,27 +694,35 @@ static void r700SendRenderTargetState(GLcontext *ctx, 
struct radeon_state_atom *
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
-   R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
+   R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
 rrb->bo,
-

[PATCH 3/3] r600: add support for getting the tiling config via drm ioctl

2010-05-25 Thread Alex Deucher

Needed for the the 2D tiling span functions.

Signed-off-by: Alex Deucher 
---
 src/mesa/drivers/dri/radeon/radeon_screen.c |   53 +++
 1 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 4f59511..175ef71 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -233,6 +233,9 @@ radeonGetParam(__DRIscreen *sPriv, int param, void *value)
   case RADEON_PARAM_NUM_Z_PIPES:
   info.request = RADEON_INFO_NUM_Z_PIPES;
   break;
+  case 0x05: /* RADEON_INFO_TILE_CONFIG */
+  info.request = 0x05;
+  break;
   default:
   return -EINVAL;
   }
@@ -1316,6 +1319,56 @@ radeonCreateScreen2(__DRIscreen *sPriv)
else
   screen->chip_flags |= RADEON_CLASS_R600;
 
+   /* r6xx+ tiling */
+   if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 5)) {
+  ret = radeonGetParam(sPriv, 0x05, &temp);
+  if (ret)
+  fprintf(stderr, "failed to get tiling info\n");
+  else {
+  screen->tile_config = temp;
+  screen->r7xx_bank_op = 0;
+  switch((screen->tile_config & 0xe) >> 1) {
+  case 0:
+  screen->num_channels = 1;
+  break;
+  case 1:
+  screen->num_channels = 2;
+  break;
+  case 2:
+  screen->num_channels = 4;
+  break;
+  case 3:
+  screen->num_channels = 8;
+  break;
+  default:
+  fprintf(stderr, "bad channels\n");
+  break;
+  }
+  switch((screen->tile_config & 0x30) >> 4) {
+  case 0:
+  screen->num_banks = 4;
+  break;
+  case 1:
+  screen->num_banks = 8;
+  break;
+  default:
+  fprintf(stderr, "bad banks\n");
+  break;
+  }
+  switch((screen->tile_config & 0xc0) >> 6) {
+  case 0:
+  screen->group_bytes = 256;
+  break;
+  case 1:
+  screen->group_bytes = 512;
+  break;
+  default:
+  fprintf(stderr, "bad group_bytes\n");
+  break;
+  }
+  }
+   }
+
if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {
-- 
1.5.6.3

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[PATCH 0/2] Add r6xx/r7xx tiling support to the ddx

2010-05-25 Thread Alex Deucher

These patches along with the drm and mesa patches enable tiling
on r6xx/r7xx hardware.

Alex

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[PATCH 1/2] r6xx/r7xx: add support for tiling with kms

2010-05-25 Thread Alex Deucher

Requires radeon drm 2.5.0 and updated mesa.

Signed-off-by: Alex Deucher 
---
 src/drmmode_display.c |7 ++-
 src/r600_exa.c|3 +
 src/r600_state.h  |3 +
 src/r6xx_accel.c  |   12 --
 src/radeon.h  |6 +++
 src/radeon_dri2.c |   10 -
 src/radeon_exa.c  |   26 ++--
 src/radeon_kms.c  |   99 ++--
 8 files changed, 140 insertions(+), 26 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 686de5e..c251110 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1099,8 +1099,11 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
if (!info->front_bo)
goto fail;
 
-   if (info->allowColorTiling)
-   tiling_flags |= RADEON_TILING_MACRO;
+   /* no tiled scanout on r6xx+ yet */
+   if (info->allowColorTiling) {
+   if (info->ChipFamily < CHIP_FAMILY_R600)
+   tiling_flags |= RADEON_TILING_MACRO;
+   }
 #if X_BYTE_ORDER == X_BIG_ENDIAN
switch (cpp) {
case 4:
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 26b59d8..6b6c897 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2305,6 +2305,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
info->accel_state->exa->UploadToScreen = R600UploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
+#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5)
+info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
+#endif
 } else
 #endif
 #endif
diff --git a/src/r600_state.h b/src/r600_state.h
index e9bfa10..c1e1ad3 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -339,6 +339,9 @@ R600SetAccelState(ScrnInfoPtr pScrn,
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
 extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
+extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
+   int depth, int usage_hint, int bitsPerPixel,
+   int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
 extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index a835d71..cc82115 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -282,16 +282,21 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, 
cb_config_t *cb_conf, uint32_
 EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8));  // 
FMASK per-tile data base/256
 RELOC_BATCH(cb_conf->bo, 0, domain);
 END_BATCH();
-BEGIN_BATCH(12);
+BEGIN_BATCH(9);
 // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
 EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << 
PITCH_TILE_MAX_shift)|
(slice << 
SLICE_TILE_MAX_shift)));
 EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0<< 
SLICE_START_shift)|
(0<< SLICE_MAX_shift)));
-EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
 EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0<< 
CMASK_BLOCK_MAX_shift)|
(0<< 
FMASK_TILE_MAX_shift)));
 END_BATCH();
+
+BEGIN_BATCH(3 + 2);
+EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
+RELOC_BATCH(cb_conf->bo, 0, domain);
+END_BATCH();
+
 }
 
 void
@@ -905,7 +910,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 
 sq_setup(pScrn, ib, &sq_conf);
 
-BEGIN_BATCH(59);
+BEGIN_BATCH(56);
 EREG(ib, SQ_VTX_BASE_VTX_LOC, 0);
 EREG(ib, SQ_VTX_START_INST_LOC,   0);
 
@@ -921,7 +926,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 E32(ib, 0);// 
SQ_GS_VERT_ITEMSIZE
 
 // DB
-EREG(ib, DB_DEPTH_INFO,   0);
 EREG(ib, DB_STENCIL_CLEAR,0);
 EREG(ib, DB_DEPTH_CLEAR,  0);
 EREG(ib, DB_STENCILREFMASK,   0);
diff --git a/src/radeon.h b/src/radeon.h
index 56bc076..9ba3173 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1036,6 +1036,12 @@ typedef struct {
 uint64_t vram_size;
 uint64_t gart_size;
 drmmode_rec drmmode;
+/* r6xx+ tile config */
+uint32_t tile_config;
+int group_bytes;
+int num_channels;
+int num_banks;
+int r7xx_bank_op;
 #else
 /* fake bool */
 Bool cs;
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 7d5205e..d10d9a8 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -101,7 +101

[PATCH 2/2] r6xx/r7xx: default to micro (1D) tiling for now

2010-05-25 Thread Alex Deucher

SW de-tiling used in the r600c 3D driver has issues with
certain configurations.

Signed-off-by: Alex Deucher 
---
 src/radeon_dri2.c |   32 +---
 1 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index d10d9a8..0811bb1 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -102,7 +102,10 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
if (info->ChipFamily >= CHIP_FAMILY_R600)
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
@@ -110,7 +113,13 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
@@ -186,16 +195,25 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
switch(attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
-   if (info->ChipFamily >= CHIP_FAMILY_R600)
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
-   else
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
+   /* macro is the preferred setting, but the 2D detiling for software
+* fallbacks in mesa still has issues on some configurations
+*/
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
-- 
1.5.6.3

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[git pull] drm fixes

2010-05-25 Thread Dave Airlie


Hi Linus,

just some minor drm/agp fixes, nothing too serious, AGP s/r regression, 
HDMI EDID regression fix.

Dave.

The following changes since commit b486787ee4797d6e42a9bd3a6f079385ad0f4472:
  Alex Deucher (1):
drm/radeon/kms/pm/r600: select the mid clock mode for single head low 
profile

are available in the git repository at:

  ssh://master.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git drm-linus

Adam Jackson (1):
  drm/edid: Allow non-fatal checksum errors in CEA blocks

Jerome Glisse (1):
  drm/radeon/kms: release AGP bridge at suspend

Jiri Slaby (1):
  agp: amd64, fix pci reference leaks

Prarit Bhargava (1):
  drm: Fixes linux-next & linux-2.6 checkstack warnings:

Randy Dunlap (1):
  nouveau: fix acpi_lid_open undefined

Stefan Richter (1):
  drm/radeon/kms: suppress a build warning (unused variable)

 drivers/char/agp/amd64-agp.c|   28 +-
 drivers/gpu/drm/drm_edid.c  |5 +++-
 drivers/gpu/drm/nouveau/nouveau_connector.c |3 +-
 drivers/gpu/drm/nouveau/nv40_graph.c|8 ++-
 drivers/gpu/drm/radeon/atombios_crtc.c  |1 +
 drivers/gpu/drm/radeon/radeon.h |1 +
 drivers/gpu/drm/radeon/radeon_agp.c |5 
 drivers/gpu/drm/radeon/radeon_atombios.c|   13 ++-
 drivers/gpu/drm/radeon/radeon_device.c  |2 +
 9 files changed, 51 insertions(+), 15 deletions(-)
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[Bug 28229] Radeon driver not detecting HDMI monitor correctly when using KMS

2010-05-25 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=28229

Alex Deucher  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution||FIXED

--- Comment #13 from Alex Deucher  2010-05-25 21:55:03 PDT ---
fixed here:
http://git.kernel.org/?p=linux/kernel/git/airlied/drm-2.6.git;a=commitdiff;h=4a638b4e38234233f5c7e6705662fbc0b58d80c2

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[Bug 26852] Build libkms against in-tree xf86drm.h

2010-05-25 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=26852

--- Comment #3 from Christopher James Halse Rogers  
2010-05-25 23:35:04 PDT ---
So, until there's an actual kernel incompatibility introduced for which runtime
detection in libkms is necessary, is there any reason not to apply this patch?  

Building against the headers shipped in the source alongside it makes much more
sense to me.

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[PATCH -next] nouveau: fix acpi_lid_open undefined

2010-05-25 Thread Dave Airlie

On Mon, 2010-05-24 at 07:17 -0700, Randy Dunlap wrote:
> On 05/24/10 06:59, Matthew Garrett wrote:
> > On Mon, May 24, 2010 at 06:53:51AM -0700, Randy Dunlap wrote:
> >> On 05/24/10 05:56, Matthew Garrett wrote:
> >>> Won't this result in a behavioural difference? The desirable outcome is 
> >>
> >> It could, yes.
> >>
> >>> that that configuration be impossible, not for that configuration to 
> >>> build but be buggy.
> >>
> >> so nouveau should depend on (or select, if ACPI is enabled) ACPI_BUTTON?
> > 
> > There's an argument that it doesn't need to depend on it, but if button 
> > is a module then nouveau has to be. Except the inverse isn't true. 
> > Kconfig is hard, let's weep gently.
> 
> Maybe Dave can weep with us when he is back at work...

Yeah I've had problems like this a few times lately with the drm, I'm
torn between just adding select all over the place, or assuming someone
sane is configuring the kernel.

I'm sort of erring on the someone sane is configuring the kernel just
because Linus's objects to "default y" things seems to point at that we
can't really give pointers to the people who haven't done it before. So
I'm quite happy to leave it having different behaviour depending on the
configuration and simply ignoring bug reports from incompetents.

Dave.

[PATCH -next] nouveau: fix acpi_lid_open undefined

2010-05-25 Thread Nigel Cunningham

Hi.

On 25/05/10 08:47, Dave Airlie wrote:
> On Mon, 2010-05-24 at 07:17 -0700, Randy Dunlap wrote:
>> On 05/24/10 06:59, Matthew Garrett wrote:
>>> On Mon, May 24, 2010 at 06:53:51AM -0700, Randy Dunlap wrote:
 On 05/24/10 05:56, Matthew Garrett wrote:
> Won't this result in a behavioural difference? The desirable outcome is

 It could, yes.

> that that configuration be impossible, not for that configuration to
> build but be buggy.

 so nouveau should depend on (or select, if ACPI is enabled) ACPI_BUTTON?
>>>
>>> There's an argument that it doesn't need to depend on it, but if button
>>> is a module then nouveau has to be. Except the inverse isn't true.
>>> Kconfig is hard, let's weep gently.
>>
>> Maybe Dave can weep with us when he is back at work...
>
> Yeah I've had problems like this a few times lately with the drm, I'm
> torn between just adding select all over the place, or assuming someone
> sane is configuring the kernel.
>
> I'm sort of erring on the someone sane is configuring the kernel just
> because Linus's objects to "default y" things seems to point at that we
> can't really give pointers to the people who haven't done it before. So
> I'm quite happy to leave it having different behaviour depending on the
> configuration and simply ignoring bug reports from incompetents.

'scuse me for butting in, but would you at least consider adding 
something to the help for the Nouveau and/or ACPI button options? You 
might have a sane person configuring the kernel, but that doesn't mean a 
dependency like this would necessarily be obvious to them.

Personally, I'd argue for the select.

Regards,

Nigel

[patch] drm/nouveau: off by one in init_i2c_device_find()

2010-05-25 Thread Dan Carpenter

dcb->i2c[] has DCB_MAX_NUM_I2C_ENTRIES entries.

Signed-off-by: Dan Carpenter 

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c 
b/drivers/gpu/drm/nouveau/nouveau_bios.c
index e7e69cc..bf92a1e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -814,7 +814,7 @@ init_i2c_device_find(struct drm_device *dev, int i2c_index)
if (i2c_index == 0x81)
i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;

-   if (i2c_index > DCB_MAX_NUM_I2C_ENTRIES) {
+   if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
return NULL;
}

[PATCH] drm/edid: Allow non-fatal checksum errors in CEA blocks

2010-05-25 Thread Adam Jackson

Switches will try to update the topology address and not correctly fix
up the checksum, so just let it slide.

https://bugs.freedesktop.org/28229

Signed-off-by: Adam Jackson 
---
 drivers/gpu/drm/drm_edid.c |5 -
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f569ae8..c198186 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -147,7 +147,10 @@ drm_edid_block_valid(u8 *raw_edid)
csum += raw_edid[i];
if (csum) {
DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
-   goto bad;
+
+   /* allow CEA to slide through, switches mangle this */
+   if (raw_edid[0] != 0x02)
+   goto bad;
}

/* per-block-type checks */
-- 
1.7.0.1

build warning in radeon/atombios_crtc.c: pll' may be used uninitialized

2010-05-25 Thread Alex Deucher

On Tue, May 25, 2010 at 4:25 PM, Stefan Richter
 wrote:
> Hi,
>
> seen with gcc 4.3.4 in current git (although 2.6.34 should show that
> too):
>
> drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
> drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
> uninitialized in this function
>
> It seems to require a 'make CONFIG_DEBUG_SECTION_MISMATCH=y' to trigger
> this warning; don't know why.
>
> Perhaps add a 'default:' case to the switch block?

Adding a default to the last case should be fine.

Alex

> --
> Stefan Richter
> -=-==-=- -=-= ==--=
> http://arcgraph.de/sr/
>
>

[Bug 25616] X1600:M56P Second suspend hangs the system

2010-05-25 Thread bugzilla-dae...@freedesktop.org

https://bugs.freedesktop.org/show_bug.cgi?id=25616

Andrea Iob  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution||WORKSFORME

--- Comment #9 from Andrea Iob  2010-05-25 13:56:35 PDT 
---
With Linux 2.6.34 and KMS suspend-to-ram works fine!
I think the bug can be closed.

Thanks guys for your work!

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[PATCH] drm/radeon/kms: suppress a build warning (unused variable)

2010-05-25 Thread Alex Deucher

On Tue, May 25, 2010 at 5:03 PM, Stefan Richter
 wrote:
> At least 'make CONFIG_DEBUG_SECTION_MISMATCH=y' causes
> ?drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
> ?drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
> uninitialized in this function
> which has the looks of a falso positive.
>
> Add a default: case so that gcc rests assured that all possible pll_id's are 
> covered.
> Keep the present cases that fall through to the default one for 
> self-documentation.
>
> Signed-off-by: Stefan Richter 

looks good.

Reviewed-by: Alex Deucher 

> ---
> ?drivers/gpu/drm/radeon/atombios_crtc.c | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
> b/drivers/gpu/drm/radeon/atombios_crtc.c
> index 03dd6c4..f3f2827 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -707,6 +707,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, 
> struct drm_display_mode
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case ATOM_DCPLL:
> ? ? ? ?case ATOM_PPLL_INVALID:
> + ? ? ? default:
> ? ? ? ? ? ? ? ?pll = &rdev->clock.dcpll;
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?}
> --
> Stefan Richter
> -=-==-=- -=-= ==--=
> http://arcgraph.de/sr/
>
>

This set of drm patches implements support for 1D and 2D tiling on

2010-05-25 Thread Alex Deucher

First two patches enable scanout from tiled surfaces.
Third patch updates the CS checker to deal properly with tiling.
Fourth patch fixes surface checking for both tiled and non-tiled
pitch, height, and offset alignment.
Fifth patch adds a new info query for the MC tile config which is
required for CPU access to tiled surfaces.

To enable tiling, you need these drm patches as well as ddx and mesa
patches. On r6xx we expose 2 tiling modes 1D and 2D which map to the
MACRO and MICRO tiling flags we used on previous asics.  Unlike
previous asics, you cannot have macro tiled micro linear.

1D tiles are roughly equivalent to MICRO tiles on previous asics.
The 1D tile pattern is not dependant on the MC configuration.  2D
tiling is roughly equivalent to macro tiled micro tiled on previous
asics.  Macro tiles are made up of micro tiles and the macro tile
pattern is based on the MC configuration.

2D tiling should be used for optimal performance, however there are
some cases in the mesa de-tiling algorithm that don't work properly
yet with 2D tiling, so for now when you enable tiling in the ddx, it
will only enable 1D tiling.  To play with 2D tiling, select MACRO
rather then MICRO in radeon_dri2.c in the ddx.

Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
that would require the use of wfb or tiled to untiled blits for CPU
access. Tiled to untiled blits works (I've tested it), but shows an
approximately 40% performance hit for software fallbacks (tested with
non-aa text in x11perf).  I'm not sure what how that compared to sw
detiling with wfb since the algo is pretty complex.  In practice, I
didn't notice any difference in performance on the desktop.

It might also be useful to benchmark using LINEAR_ALGINED rather than
LINEAR_GENERAL for linear surfaces as it is supposedly more efficient.

Alex

[PATCH 1/5] drm/radeon/kms: Add crtc tiling setup support for r6xx/r7xx

2010-05-25 Thread Alex Deucher

Needed for scanning out of a tiled buffer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_crtc.c |   15 +++
 drivers/gpu/drm/radeon/r500_reg.h  |5 +
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 03dd6c4..171c551 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -978,11 +978,18 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int 
x, int y,
return -EINVAL;
}

-   if (tiling_flags & RADEON_TILING_MACRO)
-   fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+   if (rdev->family >= CHIP_R600) {
+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
+   else if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
+   } else {
+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;

-   if (tiling_flags & RADEON_TILING_MICRO)
-   fb_format |= AVIVO_D1GRPH_TILED;
+   if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= AVIVO_D1GRPH_TILED;
+   }

if (radeon_crtc->crtc_id == 0)
WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/r500_reg.h 
b/drivers/gpu/drm/radeon/r500_reg.h
index 93c9a2b..6ac1f60 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -386,6 +386,11 @@
 #   define AVIVO_D1GRPH_TILED   (1 << 20)
 #   define AVIVO_D1GRPH_MACRO_ADDRESS_MODE  (1 << 21)

+#   define R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL(0 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED(1 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1(2 << 20)
+#   define R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1(4 << 20)
+
 /* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
  * block and vice versa.  This applies to GRPH, CUR, etc.
  */
-- 
1.5.6.3

[PATCH 2/5] drm/radeon/kms: Add crtc tiling setup support for evergreen

2010-05-25 Thread Alex Deucher

Needed for scanning out of a tiled buffer.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/atombios_crtc.c |5 +
 drivers/gpu/drm/radeon/evergreen_reg.h |5 +
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 171c551..ed93d24 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -840,6 +840,11 @@ static int evergreen_crtc_set_base(struct drm_crtc *crtc, 
int x, int y,
return -EINVAL;
}

+   if (tiling_flags & RADEON_TILING_MACRO)
+   fb_format |= 
EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
+   else if (tiling_flags & RADEON_TILING_MICRO)
+   fb_format |= 
EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
+
switch (radeon_crtc->crtc_id) {
case 0:
WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h 
b/drivers/gpu/drm/radeon/evergreen_reg.h
index af86af8..5a1759c 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -61,6 +61,11 @@
 #   define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
 #   define EVERGREEN_GRPH_FORMAT_RGB10  6
 #   define EVERGREEN_GRPH_FORMAT_BGR10  7
+#   define EVERGREEN_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
+#   define EVERGREEN_GRPH_ARRAY_LINEAR_GENERAL  0
+#   define EVERGREEN_GRPH_ARRAY_LINEAR_ALIGNED  1
+#   define EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1  2
+#   define EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1  4
 #define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
 #   define EVERGREEN_GRPH_ENDIAN_SWAP(x)(((x) & 0x3) << 0)
 #   define EVERGREEN_GRPH_ENDIAN_NONE   0
-- 
1.5.6.3

[PATCH 3/5] drm/radeon/kms: add tiling support to the cs checker for r6xx/r7xx

2010-05-25 Thread Alex Deucher

Check for relocs for DB_DEPTH_INFO, CB_COLOR*_INFO, and texture
resources.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600_cs.c |   57 ++
 drivers/gpu/drm/radeon/r600d.h   |6 
 2 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c39c1bc..5cab1b4 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -725,7 +725,25 @@ static inline int r600_cs_check_reg(struct 
radeon_cs_parser *p, u32 reg, u32 idx
track->db_depth_control = radeon_get_ib_value(p, idx);
break;
case R_028010_DB_DEPTH_INFO:
-   track->db_depth_info = radeon_get_ib_value(p, idx);
+   if (r600_cs_packet_next_is_pkt3_nop(p)) {
+   r = r600_cs_packet_next_reloc(p, &reloc);
+   if (r) {
+   dev_warn(p->dev, "bad SET_CONTEXT_REG "
+"0x%04X\n", reg);
+   return -EINVAL;
+   }
+   track->db_depth_info = radeon_get_ib_value(p, idx);
+   ib[idx] &= C_028010_ARRAY_MODE;
+   track->db_depth_info &= C_028010_ARRAY_MODE;
+   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+   ib[idx] |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
+   track->db_depth_info |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
+   } else {
+   ib[idx] |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
+   track->db_depth_info |= 
S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
+   }
+   } else
+   track->db_depth_info = radeon_get_ib_value(p, idx);
break;
case R_028004_DB_DEPTH_VIEW:
track->db_depth_view = radeon_get_ib_value(p, idx);
@@ -758,8 +776,25 @@ static inline int r600_cs_check_reg(struct 
radeon_cs_parser *p, u32 reg, u32 idx
case R_0280B4_CB_COLOR5_INFO:
case R_0280B8_CB_COLOR6_INFO:
case R_0280BC_CB_COLOR7_INFO:
-   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
-   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   if (r600_cs_packet_next_is_pkt3_nop(p)) {
+   r = r600_cs_packet_next_reloc(p, &reloc);
+   if (r) {
+   dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", 
reg);
+   return -EINVAL;
+   }
+   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
+   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
+   ib[idx] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
+   track->cb_color_info[tmp] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
+   } else if (reloc->lobj.tiling_flags & 
RADEON_TILING_MICRO) {
+   ib[idx] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
+   track->cb_color_info[tmp] |= 
S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
+   }
+   } else {
+   tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
+   track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
+   }
break;
case R_028060_CB_COLOR0_SIZE:
case R_028064_CB_COLOR1_SIZE:
@@ -986,8 +1021,9 @@ static void r600_texture_size(unsigned nfaces, unsigned 
blevel, unsigned nlevels
  * the texture and mipmap bo object are big enough to cover this resource.
  */
 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 
idx,
-   struct radeon_bo *texture,
-   struct radeon_bo *mipmap)
+ struct radeon_bo *texture,
+ struct radeon_bo *mipmap,
+ u32 tiling_flags)
 {
u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
u32 word0, word1, l0_size, mipmap_size;
@@ -995,7 +1031,12 @@ static inline int r600_check_texture_resource(struct 
radeon_cs_parser *p,  u32 i
/* on legacy kernel we don't perform advanced check */
if (p->rdev == NULL)
return 0;
+
word0 = radeon_get_ib_value(p, idx + 0);
+   if (tiling_flags & RADEON_TILING_MACRO)
+   word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
+   else if (tiling_flags & RAD

[PATCH 4/5] drm/radeon/kms: fix CS alignment checking for tiling

2010-05-25 Thread Alex Deucher

Covers, depth, cb, and textures. Hopefully I got this right.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/r600_cs.c |  172 ++---
 1 files changed, 139 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 5cab1b4..133f0da 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -25,6 +25,7 @@
  *  Alex Deucher
  *  Jerome Glisse
  */
+#include 
 #include "drmP.h"
 #include "radeon.h"
 #include "r600d.h"
@@ -166,7 +167,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 {
struct r600_cs_track *track = p->track;
-   u32 bpe = 0, pitch, slice_tile_max, size, tmp, height;
+   u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
volatile u32 *ib = p->ib->ptr;

if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
@@ -180,56 +181,67 @@ static inline int r600_cs_track_validate_cb(struct 
radeon_cs_parser *p, int i)
i, track->cb_color_info[i]);
return -EINVAL;
}
-   pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) << 3;
+   /* pitch is the number of 8x8 tiles per row */
+   pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
if (!pitch) {
dev_warn(p->dev, "%s:%d cb pitch (%d) for %d invalid 
(0x%08X)\n",
__func__, __LINE__, pitch, i, track->cb_color_size[i]);
return -EINVAL;
}
-   height = size / (pitch * bpe);
+   height = size / (pitch * 8 * bpe);
if (height > 8192)
height = 8192;
+   height &= ~0x7;
+   if (!height)
+   height = 8;
switch (G_0280A0_ARRAY_MODE(track->cb_color_info[i])) {
case V_0280A0_ARRAY_LINEAR_GENERAL:
-   case V_0280A0_ARRAY_LINEAR_ALIGNED:
-   if (pitch & 0x3f) {
-   dev_warn(p->dev, "%s:%d cb pitch (%d x %d = %d) 
invalid\n",
-   __func__, __LINE__, pitch, bpe, pitch * bpe);
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
-   if ((pitch * bpe) & (track->group_size - 1)) {
+   break;
+   case V_0280A0_ARRAY_LINEAR_ALIGNED:
+   pitch_align = (max((u32)64, (u32)(track->group_size / bpe)) / 
8) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+__func__, __LINE__, pitch);
+   return -EINVAL;
+   }
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
break;
case V_0280A0_ARRAY_1D_TILED_THIN1:
-   if ((pitch * 8 * bpe * track->nsamples) & (track->group_size - 
1)) {
+   pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe * 
track->nsamples))) / 8) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+__func__, __LINE__, pitch);
+   return -EINVAL;
+   }
+   if (height & 0x7) {
+   dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+__func__, __LINE__, height);
return -EINVAL;
}
-   height &= ~0x7;
-   if (!height)
-   height = 8;
break;
case V_0280A0_ARRAY_2D_TILED_THIN1:
-   if (pitch & ((8 * track->nbanks) - 1)) {
+   pitch_align = max((u32)track->nbanks,
+ (u32)(((track->group_size / 8) / (bpe * 
track->nsamples)) * track->nbanks)) - 1;
+   if (pitch & pitch_align) {
dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
__func__, __LINE__, pitch);
return -EINVAL;
}
-   tmp = pitch * 8 * bpe * track->nsamples;
-   tmp = tmp / track->nbanks;
-   if (tmp & (track->group_size - 1)) {
-   dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-   __func__, __LINE__, pitch);
+   if ((height / 8) & (tra

[PATCH 5/5] drm/radeon/kms/r6xx+: add query for tile config

2010-05-25 Thread Alex Deucher

Userspace needs this information to access tiled
buffers via the CPU.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/radeon/evergreen.c  |1 +
 drivers/gpu/drm/radeon/r600.c   |2 +-
 drivers/gpu/drm/radeon/radeon.h |3 +++
 drivers/gpu/drm/radeon/radeon_drv.c |3 ++-
 drivers/gpu/drm/radeon/radeon_kms.c |   12 
 drivers/gpu/drm/radeon/rv770.c  |3 ++-
 include/drm/radeon_drm.h|1 +
 7 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/evergreen.c 
b/drivers/gpu/drm/radeon/evergreen.c
index 8c8e4d3..e220c7e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1104,6 +1104,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
rdev->config.evergreen.max_backends) &

EVERGREEN_MAX_BACKENDS_MASK));

+   rdev->config.evergreen.tile_config = gb_addr_config;
WREG32(GB_BACKEND_MAP, gb_backend_map);
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 44e96a2..dac2534 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1508,7 +1508,7 @@ void r600_gpu_init(struct radeon_device *rdev)
 
r600_count_pipe_bits((cc_rb_backend_disable &
   
R6XX_MAX_BACKENDS_MASK) >> 16)),
(cc_rb_backend_disable 
>> 16));
-
+   rdev->config.r600.tile_config = tiling_config;
tiling_config |= BACKEND_MAP(backend_map);
WREG32(GB_TILING_CONFIG, tiling_config);
WREG32(DCP_TILING_CONFIG, tiling_config & 0x);
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5c9ce2b..78b59a7 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -892,6 +892,7 @@ struct r600_asic {
unsignedtiling_nbanks;
unsignedtiling_npipes;
unsignedtiling_group_size;
+   unsignedtile_config;
struct r100_gpu_lockup  lockup;
 };

@@ -916,6 +917,7 @@ struct rv770_asic {
unsignedtiling_nbanks;
unsignedtiling_npipes;
unsignedtiling_group_size;
+   unsignedtile_config;
struct r100_gpu_lockup  lockup;
 };

@@ -941,6 +943,7 @@ struct evergreen_asic {
unsigned tiling_nbanks;
unsigned tiling_npipes;
unsigned tiling_group_size;
+   unsigned tile_config;
 };

 union radeon_asic_config {
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index 902d173..ece06a6 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -45,9 +45,10 @@
  * - 2.2.0 - add r6xx/r7xx const buffer support
  * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  * - 2.4.0 - add crtc id query
+ * - 2.5.0 - add tiling config query (r6xx+)
  */
 #define KMS_DRIVER_MAJOR   2
-#define KMS_DRIVER_MINOR   4
+#define KMS_DRIVER_MINOR   5
 #define KMS_DRIVER_PATCHLEVEL  0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c 
b/drivers/gpu/drm/radeon/radeon_kms.c
index 021572a..977447e 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -134,6 +134,18 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
return -EINVAL;
}
break;
+   case RADEON_INFO_TILING_CONFIG:
+   if (rdev->family >= CHIP_CEDAR)
+   value = rdev->config.evergreen.tile_config;
+   else if (rdev->family >= CHIP_RV770)
+   value = rdev->config.rv770.tile_config;
+   else if (rdev->family >= CHIP_R600)
+   value = rdev->config.r600.tile_config;
+   else {
+   DRM_DEBUG("tiling config is r6xx+ only!\n");
+   return -EINVAL;
+   }
+   break;
default:
DRM_DEBUG("Invalid request %d\n", info->request);
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 253f24a..d285ca8 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -648,8 +648,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
r600_count_pipe_bits((cc_rb_backend_disable &

[PATCH 0/5] Add tiling support for r6xx/r7xx

2010-05-25 Thread Alex Deucher

This set of drm patches implements support for 1D and 2D tiling on
r6xx/r7xx chips and lays the groundwork for evergreen tiling
support.

First two patches enable scanout from tiled surfaces.
Third patch updates the CS checker to deal properly with tiling.
Fourth patch fixes surface checking for both tiled and non-tiled
pitch, height, and offset alignment.
Fifth patch adds a new info query for the MC tile config which is
required for CPU access to tiled surfaces.

To enable tiling, you need these drm patches as well as ddx and mesa
patches. On r6xx we expose 2 tiling modes 1D and 2D which map to the
MACRO and MICRO tiling flags we used on previous asics.  Unlike
previous asics, you cannot have macro tiled micro linear.

1D tiles are roughly equivalent to MICRO tiles on previous asics.
The 1D tile pattern is not dependant on the MC configuration.  2D
tiling is roughly equivalent to macro tiled micro tiled on previous
asics.  Macro tiles are made up of micro tiles and the macro tile
pattern is based on the MC configuration.

2D tiling should be used for optimal performance, however there are
some cases in the mesa de-tiling algorithm that don't work properly
yet with 2D tiling, so for now when you enable tiling in the ddx, it
will only enable 1D tiling.  To play with 2D tiling, select MACRO
rather then MICRO in radeon_dri2.c in the ddx.

Also, on r6xx/r7xx, we don't enable tiling of the front buffer as
that would require the use of wfb or tiled to untiled blits for CPU
access. Tiled to untiled blits works (I've tested it), but shows an
approximately 40% performance hit for software fallbacks (tested with
non-aa text in x11perf).  I'm not sure what how that compared to sw
detiling with wfb since the algo is pretty complex.  In practice, I
didn't notice any difference in performance on the desktop.

It might also be useful to benchmark using LINEAR_ALGINED rather than
LINEAR_GENERAL for linear surfaces as it is supposedly more efficient.

Alex

[PATCH 0/3] Add r6xx/r7xx tiling support to mesa

2010-05-25 Thread Alex Deucher

These patches along with the drm and ddx patches enable tiling
on r6xx/r7xx hardware.

Alex

[PATCH 1/3] r600: add span support for 2D tiling

2010-05-25 Thread Alex Deucher

Requires tiling config ioctl support from the drm to use.
kms only.

Signed-off-by: Alex Deucher 
---
 .../drivers/dri/radeon/radeon_common_context.c |9 +-
 .../drivers/dri/radeon/radeon_common_context.h |7 +
 src/mesa/drivers/dri/radeon/radeon_screen.h|7 +
 src/mesa/drivers/dri/radeon/radeon_span.c  |  192 +++-
 4 files changed, 210 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c 
b/src/mesa/drivers/dri/radeon/radeon_common_context.c
index 94f4766..1cce032 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c
@@ -650,6 +650,13 @@ radeon_update_renderbuffers(__DRIcontext *context, 
__DRIdrawable *drawable,
rb->base.Height = drawable->h;
rb->has_surface = 0;

+   /* r6xx+ tiling */
+   rb->tile_config = radeon->radeonScreen->tile_config;
+   rb->group_bytes = radeon->radeonScreen->group_bytes;
+   rb->num_channels = radeon->radeonScreen->num_channels;
+   rb->num_banks = radeon->radeonScreen->num_banks;
+   rb->r7xx_bank_op = radeon->radeonScreen->r7xx_bank_op;
+
if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
if (RADEON_DEBUG & RADEON_DRI)
fprintf(stderr, "(reusing depth buffer as 
stencil)\n");
@@ -678,7 +685,7 @@ radeon_update_renderbuffers(__DRIcontext *context, 
__DRIdrawable *drawable,
bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
if (tiling_flags & RADEON_TILING_MICRO)
bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
-   
+
}

if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h 
b/src/mesa/drivers/dri/radeon/radeon_common_context.h
index 5156c5d..3fd00eb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common_context.h
+++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h
@@ -93,6 +93,13 @@ struct radeon_renderbuffer
GLuint pf_pending;  /**< sequence number of pending flip */
GLuint vbl_pending;   /**< vblank sequence number of pending flip */
__DRIdrawable *dPriv;
+
+   /* r6xx+ tiling */
+   GLuint tile_config;
+   GLint group_bytes;
+   GLint num_channels;
+   GLint num_banks;
+   GLint r7xx_bank_op;
 };

 struct radeon_framebuffer
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h 
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 0d7e335..2b33201 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -112,6 +112,13 @@ typedef struct radeon_screen {
int kernel_mm;
drm_radeon_sarea_t *sarea;  /* Private SAREA data */
struct radeon_bo_manager *bom;
+
+   /* r6xx+ tiling */
+   GLuint tile_config;
+   GLint group_bytes;
+   GLint num_channels;
+   GLint num_banks;
+   GLint r7xx_bank_op;
 } radeonScreenRec, *radeonScreenPtr;

 #define IS_R100_CLASS(screen) \
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c 
b/src/mesa/drivers/dri/radeon/radeon_span.c
index 1adb609..9dfe2dd 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -111,7 +111,6 @@ static GLubyte *r200_depth_4byte(const struct 
radeon_renderbuffer * rrb,
  * two main types:
  * - 1D (akin to macro-linear/micro-tiled on older asics)
  * - 2D (akin to macro-tiled/micro-tiled on older asics)
- * only 1D tiling is implemented below
  */
 #if defined(RADEON_R600)
 static inline GLint r600_1d_tile_helper(const struct radeon_renderbuffer * rrb,
@@ -208,12 +207,190 @@ static inline GLint r600_1d_tile_helper(const struct 
radeon_renderbuffer * rrb,
 return offset;
 }

+static inline GLint r600_log2(GLint n)
+{
+   GLint log2 = 0;
+
+   while (n >>= 1)
+   ++log2;
+   return log2;
+}
+
+static inline GLint r600_2d_tile_helper(const struct radeon_renderbuffer * rrb,
+   GLint x, GLint y, GLint is_depth, GLint 
is_stencil)
+{
+   GLint group_bytes = rrb->group_bytes;
+   GLint num_channels = rrb->num_channels;
+   GLint num_banks = rrb->num_banks;
+   GLint r7xx_bank_op = rrb->r7xx_bank_op;
+   /* */
+   GLint group_bits = r600_log2(group_bytes);
+   GLint channel_bits = r600_log2(num_channels);
+   GLint bank_bits = r600_log2(num_banks);
+   GLint element_bytes = rrb->cpp;
+   GLint num_samples = 1;
+   GLint tile_width = 8;
+   GLint tile_height = 8;
+   GLint tile_thickness = 1;
+   GLint macro_tile_width = num_banks;
+   GLint macro_tile_height = num_channels;
+   GLint pitch_elements = (rrb->pitch / element_bytes) / tile_width;
+   GLint height = rrb->base.Height / tile_height;
+   GLint z

[PATCH 2/3] r600: add new relocs for tiling support

2010-05-25 Thread Alex Deucher

Signed-off-by: Alex Deucher 
---
 src/mesa/drivers/dri/r600/r600_blit.c |   20 +++--
 src/mesa/drivers/dri/r600/r700_chip.c |   37 +++-
 2 files changed, 39 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/r600/r600_blit.c 
b/src/mesa/drivers/dri/r600/r600_blit.c
index 172f85e..6196782 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -390,13 +390,20 @@ set_render_target(context_t *context, struct radeon_bo 
*bo, gl_format mesa_forma
 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 END_BATCH();

-BEGIN_BATCH_NO_AUTOSTATE(12);
+BEGIN_BATCH_NO_AUTOSTATE(9);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), cb_color0_size);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), cb_color0_view);
-R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
 R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), 0);
 END_BATCH();

+BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), cb_color0_info);
+R600_OUT_BATCH_RELOC(0,
+bo,
+0,
+0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+END_BATCH();
+
 COMMIT_BATCH();

 }
@@ -1447,7 +1454,7 @@ set_default_state(context_t *context)
SETbit(sq_dyn_gpr_cntl_ps_flush_req, VS_PC_LIMIT_ENABLE_bit);
 }

-BEGIN_BATCH_NO_AUTOSTATE(117);
+BEGIN_BATCH_NO_AUTOSTATE(114);
 R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
 R600_OUT_BATCH(sq_config);
 R600_OUT_BATCH(sq_gpr_resource_mgmt_1);
@@ -1477,7 +1484,6 @@ set_default_state(context_t *context)
  (CLRCMP_SEL_SRC << CLRCMP_FCN_SEL_shift));
 R600_OUT_BATCH_REGVAL(SQ_VTX_BASE_VTX_LOC, 0);
 R600_OUT_BATCH_REGVAL(SQ_VTX_START_INST_LOC, 0);
-R600_OUT_BATCH_REGVAL(DB_DEPTH_INFO, 0);
 R600_OUT_BATCH_REGVAL(DB_DEPTH_CONTROL, 0);
 R600_OUT_BATCH_REGVAL(CB_SHADER_MASK, (OUTPUT0_ENABLE_mask));
 R600_OUT_BATCH_REGVAL(CB_TARGET_MASK, (TARGET0_ENABLE_mask));
@@ -1607,7 +1613,7 @@ unsigned r600_blit(GLcontext *ctx,
 /* Flush is needed to make sure that source buffer has correct data */
 radeonFlush(ctx);

-rcommonEnsureCmdBufSpace(&context->radeon, 304, __FUNCTION__);
+rcommonEnsureCmdBufSpace(&context->radeon, 305, __FUNCTION__);

 /* load shaders */
 load_shaders(context->radeon.glCtx);
@@ -1616,7 +1622,7 @@ unsigned r600_blit(GLcontext *ctx,
 return GL_FALSE;

 /* set clear state */
-/* 117 */
+/* 114 */
 set_default_state(context);

 /* shaders */
@@ -1632,7 +1638,7 @@ unsigned r600_blit(GLcontext *ctx,
 set_tex_sampler(context);

 /* dst */
-/* 27 */
+/* 31 */
 set_render_target(context, dst_bo, dst_mesaformat,
  dst_pitch, dst_width, dst_height, dst_offset);
 /* scissors */
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c 
b/src/mesa/drivers/dri/r600/r700_chip.c
index cefda3a..1e955b9 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -617,18 +617,25 @@ static void r700SendDepthTargetState(GLcontext *ctx, 
struct radeon_state_atom *a

r700SetDepthTarget(context);

-BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
+BEGIN_BATCH_NO_AUTOSTATE(7 + 2);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
R600_OUT_BATCH(r700->DB_DEPTH_VIEW.u32All);
-   R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 2);
+   R600_OUT_BATCH_REGSEQ(DB_DEPTH_BASE, 1);
R600_OUT_BATCH(r700->DB_DEPTH_BASE.u32All);
-   R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All,
 rrb->bo,
 r700->DB_DEPTH_BASE.u32All,
 0, RADEON_GEM_DOMAIN_VRAM, 0);
 END_BATCH();
+BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
+   R600_OUT_BATCH_REGSEQ(DB_DEPTH_INFO, 1);
+   R600_OUT_BATCH(r700->DB_DEPTH_INFO.u32All);
+   R600_OUT_BATCH_RELOC(r700->DB_DEPTH_INFO.u32All,
+rrb->bo,
+r700->DB_DEPTH_INFO.u32All,
+0, RADEON_GEM_DOMAIN_VRAM, 0);
+END_BATCH();

if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) &&
(context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) {
@@ -687,27 +694,35 @@ static void r700SendRenderTargetState(GLcontext *ctx, 
struct radeon_state_atom *
BEGIN_BATCH_NO_AUTOSTATE(3 + 2);
R600_OUT_BATCH_REGSEQ(CB_COLOR0_TILE + (4 * id), 1);
R600_OUT_BATCH(r700->render_target[id].CB_COLOR0_TILE.u32All);
-   R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All,
+   R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_TILE.u32All,
 rrb->bo,
-

[PATCH 3/3] r600: add support for getting the tiling config via drm ioctl

2010-05-25 Thread Alex Deucher

Needed for the the 2D tiling span functions.

Signed-off-by: Alex Deucher 
---
 src/mesa/drivers/dri/radeon/radeon_screen.c |   53 +++
 1 files changed, 53 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c 
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 4f59511..175ef71 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -233,6 +233,9 @@ radeonGetParam(__DRIscreen *sPriv, int param, void *value)
   case RADEON_PARAM_NUM_Z_PIPES:
   info.request = RADEON_INFO_NUM_Z_PIPES;
   break;
+  case 0x05: /* RADEON_INFO_TILE_CONFIG */
+  info.request = 0x05;
+  break;
   default:
   return -EINVAL;
   }
@@ -1316,6 +1319,56 @@ radeonCreateScreen2(__DRIscreen *sPriv)
else
   screen->chip_flags |= RADEON_CLASS_R600;

+   /* r6xx+ tiling */
+   if (IS_R600_CLASS(screen) && (sPriv->drm_version.minor >= 5)) {
+  ret = radeonGetParam(sPriv, 0x05, &temp);
+  if (ret)
+  fprintf(stderr, "failed to get tiling info\n");
+  else {
+  screen->tile_config = temp;
+  screen->r7xx_bank_op = 0;
+  switch((screen->tile_config & 0xe) >> 1) {
+  case 0:
+  screen->num_channels = 1;
+  break;
+  case 1:
+  screen->num_channels = 2;
+  break;
+  case 2:
+  screen->num_channels = 4;
+  break;
+  case 3:
+  screen->num_channels = 8;
+  break;
+  default:
+  fprintf(stderr, "bad channels\n");
+  break;
+  }
+  switch((screen->tile_config & 0x30) >> 4) {
+  case 0:
+  screen->num_banks = 4;
+  break;
+  case 1:
+  screen->num_banks = 8;
+  break;
+  default:
+  fprintf(stderr, "bad banks\n");
+  break;
+  }
+  switch((screen->tile_config & 0xc0) >> 6) {
+  case 0:
+  screen->group_bytes = 256;
+  break;
+  case 1:
+  screen->group_bytes = 512;
+  break;
+  default:
+  fprintf(stderr, "bad group_bytes\n");
+  break;
+  }
+  }
+   }
+
if (IS_R300_CLASS(screen)) {
ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
if (ret) {
-- 
1.5.6.3

[PATCH 0/2] Add r6xx/r7xx tiling support to the ddx

2010-05-25 Thread Alex Deucher

These patches along with the drm and mesa patches enable tiling
on r6xx/r7xx hardware.

Alex

[PATCH 1/2] r6xx/r7xx: add support for tiling with kms

2010-05-25 Thread Alex Deucher

Requires radeon drm 2.5.0 and updated mesa.

Signed-off-by: Alex Deucher 
---
 src/drmmode_display.c |7 ++-
 src/r600_exa.c|3 +
 src/r600_state.h  |3 +
 src/r6xx_accel.c  |   12 --
 src/radeon.h  |6 +++
 src/radeon_dri2.c |   10 -
 src/radeon_exa.c  |   26 ++--
 src/radeon_kms.c  |   99 ++--
 8 files changed, 140 insertions(+), 26 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 686de5e..c251110 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1099,8 +1099,11 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
if (!info->front_bo)
goto fail;

-   if (info->allowColorTiling)
-   tiling_flags |= RADEON_TILING_MACRO;
+   /* no tiled scanout on r6xx+ yet */
+   if (info->allowColorTiling) {
+   if (info->ChipFamily < CHIP_FAMILY_R600)
+   tiling_flags |= RADEON_TILING_MACRO;
+   }
 #if X_BYTE_ORDER == X_BIG_ENDIAN
switch (cpp) {
case 4:
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 26b59d8..6b6c897 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2305,6 +2305,9 @@ R600DrawInit(ScreenPtr pScreen)
info->accel_state->exa->FinishAccess = RADEONFinishAccess_CS;
info->accel_state->exa->UploadToScreen = R600UploadToScreenCS;
info->accel_state->exa->DownloadFromScreen = R600DownloadFromScreenCS;
+#if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 5)
+info->accel_state->exa->CreatePixmap2 = RADEONEXACreatePixmap2;
+#endif
 } else
 #endif
 #endif
diff --git a/src/r600_state.h b/src/r600_state.h
index e9bfa10..c1e1ad3 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -339,6 +339,9 @@ R600SetAccelState(ScrnInfoPtr pScrn,
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
 extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
+extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
+   int depth, int usage_hint, int bitsPerPixel,
+   int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
 extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index a835d71..cc82115 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -282,16 +282,21 @@ set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, 
cb_config_t *cb_conf, uint32_
 EREG(ib, (CB_COLOR0_FRAG + (4 * cb_conf->id)), (0 >> 8));  // 
FMASK per-tile data base/256
 RELOC_BATCH(cb_conf->bo, 0, domain);
 END_BATCH();
-BEGIN_BATCH(12);
+BEGIN_BATCH(9);
 // pitch only for ARRAY_LINEAR_GENERAL, other tiling modes require addrlib
 EREG(ib, (CB_COLOR0_SIZE + (4 * cb_conf->id)), ((pitch << 
PITCH_TILE_MAX_shift)|
(slice << 
SLICE_TILE_MAX_shift)));
 EREG(ib, (CB_COLOR0_VIEW + (4 * cb_conf->id)), ((0<< 
SLICE_START_shift)|
(0<< SLICE_MAX_shift)));
-EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
 EREG(ib, (CB_COLOR0_MASK + (4 * cb_conf->id)), ((0<< 
CMASK_BLOCK_MAX_shift)|
(0<< 
FMASK_TILE_MAX_shift)));
 END_BATCH();
+
+BEGIN_BATCH(3 + 2);
+EREG(ib, (CB_COLOR0_INFO + (4 * cb_conf->id)), cb_color_info);
+RELOC_BATCH(cb_conf->bo, 0, domain);
+END_BATCH();
+
 }

 void
@@ -905,7 +910,7 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)

 sq_setup(pScrn, ib, &sq_conf);

-BEGIN_BATCH(59);
+BEGIN_BATCH(56);
 EREG(ib, SQ_VTX_BASE_VTX_LOC, 0);
 EREG(ib, SQ_VTX_START_INST_LOC,   0);

@@ -921,7 +926,6 @@ set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib)
 E32(ib, 0);// 
SQ_GS_VERT_ITEMSIZE

 // DB
-EREG(ib, DB_DEPTH_INFO,   0);
 EREG(ib, DB_STENCIL_CLEAR,0);
 EREG(ib, DB_DEPTH_CLEAR,  0);
 EREG(ib, DB_STENCILREFMASK,   0);
diff --git a/src/radeon.h b/src/radeon.h
index 56bc076..9ba3173 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1036,6 +1036,12 @@ typedef struct {
 uint64_t vram_size;
 uint64_t gart_size;
 drmmode_rec drmmode;
+/* r6xx+ tile config */
+uint32_t tile_config;
+int group_bytes;
+int num_channels;
+int num_banks;
+int r7xx_bank_op;
 #else
 /* fake bool */
 Bool cs;
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 7d5205e..d10d9a8 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -101,7 +101,10 @@

[PATCH 2/2] r6xx/r7xx: default to micro (1D) tiling for now

2010-05-25 Thread Alex Deucher

SW de-tiling used in the r600c 3D driver has issues with
certain configurations.

Signed-off-by: Alex Deucher 
---
 src/radeon_dri2.c |   32 +---
 1 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index d10d9a8..0811bb1 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -102,7 +102,10 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
if (info->ChipFamily >= CHIP_FAMILY_R600)
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
else
flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
@@ -110,7 +113,13 @@ radeon_dri2_create_buffers(DrawablePtr drawable,
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
@@ -186,16 +195,25 @@ radeon_dri2_create_buffer(DrawablePtr drawable,
switch(attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:
-   if (info->ChipFamily >= CHIP_FAMILY_R600)
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
-   else
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
+   /* macro is the preferred setting, but the 2D detiling for software
+* fallbacks in mesa still has issues on some configurations
+*/
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO | 
RADEON_CREATE_PIXMAP_TILING_MICRO;
break;
case DRI2BufferBackLeft:
case DRI2BufferBackRight:
case DRI2BufferFakeFrontLeft:
case DRI2BufferFakeFrontRight:
-   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
+   if (info->ChipFamily >= CHIP_FAMILY_R600)
+   /* macro is the preferred setting, but the 2D detiling for 
software
+* fallbacks in mesa still has issues on some configurations
+*/
+   flags = RADEON_CREATE_PIXMAP_TILING_MICRO;
+   else
+   flags = RADEON_CREATE_PIXMAP_TILING_MACRO;
break;
default:
flags = 0;
-- 
1.5.6.3

[Bug 28229] Radeon driver not detecting HDMI monitor correctly when using KMS

2010-05-25 Thread bugzilla-dae...@freedesktop.org

https://bugs.freedesktop.org/show_bug.cgi?id=28229

Alex Deucher  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution||FIXED

--- Comment #13 from Alex Deucher  2010-05-25 21:55:03 PDT 
---
fixed here:
http://git.kernel.org/?p=linux/kernel/git/airlied/drm-2.6.git;a=commitdiff;h=4a638b4e38234233f5c7e6705662fbc0b58d80c2

-- 
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--- You are receiving this mail because: ---
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[Bug 26852] Build libkms against in-tree xf86drm.h

2010-05-25 Thread bugzilla-dae...@freedesktop.org

https://bugs.freedesktop.org/show_bug.cgi?id=26852

--- Comment #3 from Christopher James Halse Rogers  
2010-05-25 23:35:04 PDT ---
So, until there's an actual kernel incompatibility introduced for which runtime
detection in libkms is necessary, is there any reason not to apply this patch?  

Building against the headers shipped in the source alongside it makes much more
sense to me.

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build warning in radeon/atombios_crtc.c: pll' may be used uninitialized

2010-05-25 Thread Stefan Richter

Hi,

seen with gcc 4.3.4 in current git (although 2.6.34 should show that
too):

drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
   
drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
uninitialized in this function  
 

It seems to require a 'make CONFIG_DEBUG_SECTION_MISMATCH=y' to trigger
this warning; don't know why.

Perhaps add a 'default:' case to the switch block?
-- 
Stefan Richter
-=-==-=- -=-= ==--=
http://arcgraph.de/sr/

[PATCH] drm/radeon/kms: suppress a build warning (unused variable)

2010-05-25 Thread Stefan Richter

At least 'make CONFIG_DEBUG_SECTION_MISMATCH=y' causes
  drivers/gpu/drm/radeon/atombios_crtc.c: In function 'atombios_crtc_set_pll':
  drivers/gpu/drm/radeon/atombios_crtc.c:684: warning: 'pll' may be used 
uninitialized in this function
which has the looks of a falso positive.

Add a default: case so that gcc rests assured that all possible pll_id's are 
covered.
Keep the present cases that fall through to the default one for 
self-documentation.

Signed-off-by: Stefan Richter 
---
 drivers/gpu/drm/radeon/atombios_crtc.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 03dd6c4..f3f2827 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -707,6 +707,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, 
struct drm_display_mode
break;
case ATOM_DCPLL:
case ATOM_PPLL_INVALID:
+   default:
pll = &rdev->clock.dcpll;
break;
}
-- 
Stefan Richter
-=-==-=- -=-= ==--=
http://arcgraph.de/sr/

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