git: 63f7a383434a - main - vmm: Only link the arm64 hyp code in vmm.ko once

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=63f7a383434ae81cdccc6250045f637f8ae9615a

commit 63f7a383434ae81cdccc6250045f637f8ae9615a
Author: Andrew Turner 
AuthorDate: 2024-06-10 14:58:15 +
Commit: Andrew Turner 
CommitDate: 2024-06-10 15:16:10 +

vmm: Only link the arm64 hyp code in vmm.ko once

This code runs at EL2 while the kernel runs at EL1. We build these
files for EL2 through a dependency in vmm_hyp_blob.elf.full so there
is no need to include them in SRCS.

Reviewed by:imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45467
---
 sys/modules/vmm/Makefile | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/sys/modules/vmm/Makefile b/sys/modules/vmm/Makefile
index 6737d868f2ea..8f6eb915290a 100644
--- a/sys/modules/vmm/Makefile
+++ b/sys/modules/vmm/Makefile
@@ -34,8 +34,7 @@ SRCS+=vgic.c \
vgic_v3.c \
vtimer.c
 
-SRCS+= vmm_hyp_exception.S vmm_hyp.c
-
+CLEANFILES+=   vmm_hyp_exception.o vmm_hyp.o
 CLEANFILES+=   vmm_hyp_blob.elf.full
 CLEANFILES+=   vmm_hyp_blob.elf vmm_hyp_blob.bin
 

git: 86bafddd61ab - main - arm64: Fix indentation to be consistent

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=86bafddd61aba115bc46bcf1d7e0afb125850b5f

commit 86bafddd61aba115bc46bcf1d7e0afb125850b5f
Author: Andrew Turner 
AuthorDate: 2024-06-10 14:58:22 +
Commit: Andrew Turner 
CommitDate: 2024-06-10 15:16:10 +

arm64: Fix indentation to be consistent

Adjust the mair_el1 macro indentation to be consistent with the
surrounding macros.

Reviewed by:emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45524
---
 sys/arm64/include/armreg.h | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 7bdb28aad1e5..194731c98902 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1505,13 +1505,13 @@
 #define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
 
 /* MAIR_EL1 - Memory Attribute Indirection Register */
-#defineMAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8))
-#defineMAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
-#define MAIR_DEVICE_nGnRnE UL(0x00)
-#define MAIR_DEVICE_nGnRE  UL(0x04)
-#define MAIR_NORMAL_NC UL(0x44)
-#define MAIR_NORMAL_WT UL(0xbb)
-#define MAIR_NORMAL_WB UL(0xff)
+#defineMAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8))
+#defineMAIR_ATTR(attr, idx)((attr) << ((idx) * 8))
+#define MAIR_DEVICE_nGnRnE UL(0x00)
+#define MAIR_DEVICE_nGnRE  UL(0x04)
+#define MAIR_NORMAL_NC UL(0x44)
+#define MAIR_NORMAL_WT UL(0xbb)
+#define MAIR_NORMAL_WB UL(0xff)
 
 /* MDCCINT_EL1 */
 #defineMDCCINT_EL1 MRS_REG(MDCCINT_EL1)

git: 6abad5b6062d - main - Remove the arm FIQ support

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=6abad5b6062d9e8f7e6dd08eaa4033a5358b952e

commit 6abad5b6062d9e8f7e6dd08eaa4033a5358b952e
Author: Andrew Turner 
AuthorDate: 2024-06-10 14:58:47 +
Commit: Andrew Turner 
CommitDate: 2024-06-10 15:16:10 +

Remove the arm FIQ support

It isn't used, and only masks/unmasks FIQs on the local CPU so will be
broken on SMP.

Reviewed by:mmel
Differential Revision:  https://reviews.freebsd.org/D33804
---
 sys/arm/arm/autoconf.c  |   2 +-
 sys/arm/arm/exception.S |  37 +--
 sys/arm/arm/fiq.c   | 163 
 sys/arm/arm/fiq_subr.S  |  92 ---
 sys/arm/arm/machdep.c   |   2 +-
 sys/arm/arm/pmap-v6.c   |   4 +-
 sys/arm/arm/syscall.c   |   2 -
 sys/arm/arm/trap-v6.c   |   4 +-
 sys/arm/arm/undefined.c |   2 -
 sys/arm/include/cpu.h   |   2 +-
 sys/arm/include/fiq.h   |  71 -
 sys/conf/files.arm  |   2 -
 12 files changed, 9 insertions(+), 374 deletions(-)

diff --git a/sys/arm/arm/autoconf.c b/sys/arm/arm/autoconf.c
index 23289db9c19a..fe2882dc6d9f 100644
--- a/sys/arm/arm/autoconf.c
+++ b/sys/arm/arm/autoconf.c
@@ -90,7 +90,7 @@ static void
 configure_final(void *dummy)
 {
 
-   enable_interrupts(PSR_I | PSR_F);
+   enable_interrupts(PSR_I);
cninit_finish();
cold = 0;
 }
diff --git a/sys/arm/arm/exception.S b/sys/arm/arm/exception.S
index d2e55bd7d84d..d0be3bd9c90a 100644
--- a/sys/arm/arm/exception.S
+++ b/sys/arm/arm/exception.S
@@ -165,12 +165,12 @@ _C_LABEL(dtrace_invop_jump_addr):
 #defineDO_AST  
   \
ldr r0, [sp];   /* Get the SPSR from stack */  \
mrs r4, cpsr;   /* save CPSR */\
-   orr r1, r4, #(PSR_I|PSR_F);\
+   orr r1, r4, #(PSR_I);  \
msr cpsr_c, r1; /* Disable interrupts */   \
and r0, r0, #(PSR_MODE);/* Returning to USR mode? */   \
teq r0, #(PSR_USR32_MODE); \
bne 2f; /* Nope, get out now */\
-   bic r4, r4, #(PSR_I|PSR_F);\
+   bic r4, r4, #(PSR_I);  \
 1: GET_CURTHREAD_PTR(r5); \
ldr r1, [r5, #(TD_AST)];   \
teq r1, #0;\
@@ -178,7 +178,7 @@ _C_LABEL(dtrace_invop_jump_addr):
msr cpsr_c, r4; /* Restore interrupts */   \
mov r0, sp;\
bl  _C_LABEL(ast);  /* ast(frame) */   \
-   orr r0, r4, #(PSR_I|PSR_F);\
+   orr r0, r4, #(PSR_I);  \
msr cpsr_c, r0;\
b   1b;\
 2:
@@ -315,21 +315,6 @@ ASENTRY_NP(irq_entry)
b   _C_LABEL(intr_irq_handler)/* trapframe to the handler. */
 END(irq_entry)
 
-/*
- * Entry point for an FIQ interrupt.
- *
- * We don't currently support FIQ handlers very much.  Something can
- * install itself in the FIQ vector using code (that may or may not work
- * these days) in fiq.c.  If nobody does that and an FIQ happens, this
- * default handler just disables FIQs and otherwise ignores it.
- */
-ASENTRY_NP(fiq_entry)
-   mrs r8, cpsr/* FIQ handling isn't supported, */
-   bic r8, #(PSR_F)/* just disable FIQ and return.  */
-   msr cpsr_c, r8  /* The r8 we trash here is the  */
-   subspc, lr, #4  /* banked FIQ-mode r8. */
-END(fiq_entry)
-
 /*
  * Entry point for an Address Exception exception.
  * This is an arm26 exception that should never happen.
@@ -378,8 +363,6 @@ _C_LABEL(page0):
ldr pc, .Ldata_abort_entry
ldr pc, .Laddr_exception_entry
ldr pc, .Lirq_entry
-.fiqv: ldr pc, .Lfiq_entry
-   .space 256  /* room for some fiq handler code */
 
 _C_LABEL(page0_data):
 .Lreset_entry: .word   reset_entry
@@ -389,18 +372,4 @@ _C_LABEL(page0_data):
 .Ldata_abort_entry:.word   data_abort_entry
 .Laddr_exception_entry:.word   addr_exception_entry
 .Lirq_entry:   .word   irq_entry
-.Lfiq_entry:   .word   fiq_entry
-
-/*
- * These items are used by the code in fiq.c to install what it calls the
- * "null" handler.  It's actually our default vector entry that just ju

git: abf239cf097b - main - arm64/vmm: Add braces to fix the gcc build

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=abf239cf097b7a16defb9857027165427341c38c

commit abf239cf097b7a16defb9857027165427341c38c
Author: Andrew Turner 
AuthorDate: 2024-06-11 08:49:14 +
Commit: Andrew Turner 
CommitDate: 2024-06-11 13:12:43 +

arm64/vmm: Add braces to fix the gcc build

Reviewed by:markj, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45548
---
 sys/arm64/vmm/vmm_arm64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index e0547bcef914..6b058a993cdd 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -1352,7 +1352,7 @@ vmmops_setcap(void *vcpui, int num, int val)
 
switch (num) {
case VM_CAP_BRK_EXIT:
-   if ((val != 0) == (hypctx->setcaps & (1ul << num)) != 0)
+   if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
break;
if (val != 0)
hypctx->mdcr_el2 |= MDCR_EL2_TDE;
@@ -1360,7 +1360,7 @@ vmmops_setcap(void *vcpui, int num, int val)
hypctx->mdcr_el2 &= ~MDCR_EL2_TDE;
break;
case VM_CAP_SS_EXIT:
-   if ((val != 0) == (hypctx->setcaps & (1ul << num)) != 0)
+   if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
break;
 
if (val != 0) {
@@ -1382,7 +1382,7 @@ vmmops_setcap(void *vcpui, int num, int val)
}
break;
case VM_CAP_MASK_HWINTR:
-   if ((val != 0) == (hypctx->setcaps & (1ul << num)) != 0)
+   if ((val != 0) == ((hypctx->setcaps & (1ul << num)) != 0))
break;
 
if (val != 0) {

git: 9a4813e1dc17 - main - bhyve: Fix the build with gcc

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=9a4813e1dc1781d952d8db017fc7cc005095c6a0

commit 9a4813e1dc1781d952d8db017fc7cc005095c6a0
Author: Andrew Turner 
AuthorDate: 2024-06-11 08:49:32 +
Commit: Andrew Turner 
CommitDate: 2024-06-11 13:12:43 +

bhyve: Fix the build with gcc

gcc doesn't like const and static to not be at the start of a variable
declaration. Update the gdb_regset arrays to make it more obvious they
are arrays of struct gdb_reg and to fix the gcc build.

Reviewed by:corvink, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45550
---
 usr.sbin/bhyve/gdb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/usr.sbin/bhyve/gdb.c b/usr.sbin/bhyve/gdb.c
index 6df8026a0245..a13166e1e2c8 100644
--- a/usr.sbin/bhyve/gdb.c
+++ b/usr.sbin/bhyve/gdb.c
@@ -166,10 +166,10 @@ static bool gdb_active = false;
 struct gdb_reg {
enum vm_reg_name id;
int size;
-}
+};
 
 #ifdef __amd64__
-static const gdb_regset[] = {
+static const struct gdb_reg gdb_regset[] = {
{ .id = VM_REG_GUEST_RAX, .size = 8 },
{ .id = VM_REG_GUEST_RBX, .size = 8 },
{ .id = VM_REG_GUEST_RCX, .size = 8 },
@@ -212,7 +212,7 @@ static const gdb_regset[] = {
{ .id = VM_REG_GUEST_EFER, .size = 8 },
 };
 #else /* __aarch64__ */
-static const gdb_regset[] = {
+static const struct gdb_reg gdb_regset[] = {
{ .id = VM_REG_GUEST_X0, .size = 8 },
{ .id = VM_REG_GUEST_X1, .size = 8 },
{ .id = VM_REG_GUEST_X2, .size = 8 },

git: b8a496dfb6df - main - lib: Remove __ARM_ARCH checks that are always true

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=b8a496dfb6df7b86e014d0d4476cd75850e060c1

commit b8a496dfb6df7b86e014d0d4476cd75850e060c1
Author: Andrew Turner 
AuthorDate: 2024-06-12 11:49:05 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 11:49:05 +

lib: Remove __ARM_ARCH checks that are always true

Reviewed by:imp
Differential Revision:  https://reviews.freebsd.org/D45559
---
 lib/libc/arm/aeabi/aeabi_vfp.h | 2 +-
 lib/libc/arm/gen/_setjmp.S | 8 
 lib/libc/arm/gen/setjmp.S  | 4 ++--
 lib/libsys/arm/__vdso_gettc.c  | 7 ---
 lib/msun/arm/fenv.c| 6 +-
 5 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/lib/libc/arm/aeabi/aeabi_vfp.h b/lib/libc/arm/aeabi/aeabi_vfp.h
index f87f9acfd0a2..3b70fe06fab3 100644
--- a/lib/libc/arm/aeabi/aeabi_vfp.h
+++ b/lib/libc/arm/aeabi/aeabi_vfp.h
@@ -65,7 +65,7 @@
  * C Helper macros
  */
 
-#if __ARM_ARCH >= 6 && !defined(SOFTFLOAT_FOR_GCC)
+#if !defined(SOFTFLOAT_FOR_GCC)
 /*
  * Generate a function that will either call into the VFP implementation,
  * or the soft float version for a given __aeabi_* helper. The function
diff --git a/lib/libc/arm/gen/_setjmp.S b/lib/libc/arm/gen/_setjmp.S
index 19b8b6b07059..9e655d2e9e2e 100644
--- a/lib/libc/arm/gen/_setjmp.S
+++ b/lib/libc/arm/gen/_setjmp.S
@@ -58,12 +58,12 @@
 ENTRY(_setjmp)
ldr r1, .L_setjmp_magic
 
-#if !defined(_STANDALONE) && __ARM_ARCH >= 6 && !defined(SOFTFLOAT_FOR_GCC)
+#if !defined(_STANDALONE) && !defined(SOFTFLOAT_FOR_GCC)
add r2, r0, #(_JB_REG_D8 * 4)
vstmia  r2, {d8-d15}
vmrsr2, fpscr
str r2, [r0, #(_JB_REG_FPSCR * 4)]
-#endif /* !_STANDALONE && __ARM_ARCH >= 6 */
+#endif /* !_STANDALONE && !SOFTFLOAT_FOR_GCC */
 
str r1, [r0]
 
@@ -91,12 +91,12 @@ ENTRY(_longjmp)
teq ip, r2  /* magic correct? */
bne botch   /*   no, botch */
 
-#if !defined(_STANDALONE) && __ARM_ARCH >= 6 && !defined(SOFTFLOAT_FOR_GCC)
+#if !defined(_STANDALONE) && !defined(SOFTFLOAT_FOR_GCC)
add ip, r0, #(_JB_REG_D8 * 4)
vldmia  ip, {d8-d15}
ldr ip, [r0, #(_JB_REG_FPSCR * 4)]
vmsrfpscr, ip
-#endif /* !_STANDALONE && __ARM_ARCH >= 6 */
+#endif /* !_STANDALONE && !SOFTFLOAT_FOR_GCC */
 
add r0, r0, #(_JB_REG_R4 * 4)
/* Restore integer registers */
diff --git a/lib/libc/arm/gen/setjmp.S b/lib/libc/arm/gen/setjmp.S
index 5a6c899e2b23..e7f8b788e878 100644
--- a/lib/libc/arm/gen/setjmp.S
+++ b/lib/libc/arm/gen/setjmp.S
@@ -61,7 +61,7 @@ ENTRY(setjmp)
 
ldr r1, .Lsetjmp_magic
 
-#if __ARM_ARCH >= 6 && !defined(SOFTFLOAT_FOR_GCC)
+#if !defined(SOFTFLOAT_FOR_GCC)
add r2, r0, #(_JB_REG_D8 * 4)
vstmia  r2, {d8-d15}
vmrsr2, fpscr
@@ -102,7 +102,7 @@ ENTRY(__longjmp)
bl  PIC_SYM(_C_LABEL(sigprocmask), PLT)
ldmfd   sp!, {r0-r2, r14}
 
-#if __ARM_ARCH >= 6 && !defined(SOFTFLOAT_FOR_GCC)
+#if !defined(SOFTFLOAT_FOR_GCC)
add ip, r0, #(_JB_REG_D8 * 4)
vldmia  ip, {d8-d15}
ldr ip, [r0, #(_JB_REG_FPSCR * 4)]
diff --git a/lib/libsys/arm/__vdso_gettc.c b/lib/libsys/arm/__vdso_gettc.c
index ea70dec35cd8..cb4bdec1e8ef 100644
--- a/lib/libsys/arm/__vdso_gettc.c
+++ b/lib/libsys/arm/__vdso_gettc.c
@@ -37,7 +37,6 @@
 #include 
 #include "libc_private.h"
 
-#if __ARM_ARCH >= 6
 static inline uint64_t
 cp15_cntvct_get(void)
 {
@@ -55,7 +54,6 @@ cp15_cntpct_get(void)
__asm __volatile("mrrc\tp15, 0, %Q0, %R0, c14" : "=r" (reg));
return (reg);
 }
-#endif
 
 #pragma weak __vdso_gettc
 int
@@ -64,7 +62,6 @@ __vdso_gettc(const struct vdso_timehands *th, u_int *tc)
 
if (th->th_algo != VDSO_TH_ALGO_ARM_GENTIM)
return (ENOSYS);
-#if __ARM_ARCH >= 6
/*
 * Userspace gettimeofday() is only enabled on ARMv7 CPUs, but
 * libc is compiled for ARMv6.  Due to clang issues, .arch
@@ -73,10 +70,6 @@ __vdso_gettc(const struct vdso_timehands *th, u_int *tc)
__asm __volatile(".word\t0xf57ff06f" : : : "memory"); /* isb */
*tc = th->th_physical == 0 ? cp15_cntvct_get() : cp15_cntpct_get();
return (0);
-#else
-   *tc = 0;
-   return (ENOSYS);
-#endif
 }
 
 #pragma weak __vdso_gettimekeep
diff --git a/lib/msun/arm/fenv.c b/lib/msun/arm/fenv.c
index 9f172d5fd7c9..05b3adb05f81 100644
--- a/lib/msun/arm/fenv.c
+++ b/lib/msun/arm/fenv.c
@@ -32,10 +32,6 @@
 
 #include 
 
-#if __ARM_ARCH >= 6
-#define FENV_ARMv6
-#endif
-
 /* When SOFTFP_ABI is defined we are using the softfp ABI. */
 #if defined(__VFP_FP__) && !defined(__ARM_PCS_VFP)
 #define SOFTFP_ABI
@@ -52,7 +48,7 @@ c

git: bbdf32d94c2f - main - nanobsd: Remove pre-armv6 support

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=bbdf32d94c2f746b914aa87b1104b579426d8100

commit bbdf32d94c2f746b914aa87b1104b579426d8100
Author: Andrew Turner 
AuthorDate: 2024-06-12 11:49:13 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 11:49:13 +

nanobsd: Remove pre-armv6 support

Remove support for pre-armv6 from nanobsd. It was removed from FreeBSD
in 2020.

Reviewed by:imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45560
---
 tools/tools/nanobsd/embedded/common | 4 
 1 file changed, 4 deletions(-)

diff --git a/tools/tools/nanobsd/embedded/common 
b/tools/tools/nanobsd/embedded/common
index bcb1061df629..4f5eac7806f2 100644
--- a/tools/tools/nanobsd/embedded/common
+++ b/tools/tools/nanobsd/embedded/common
@@ -51,7 +51,6 @@
 # o documentation for how to run the qemu images
 # o msdos mtools fallback
 # o special boot for !x86 !arm platforms
-# o qemu image for arm
 # o qemu image for aarch64
 # o qemu image for armv6/armv7
 # o easy support for different image / vm formats
@@ -503,9 +502,6 @@ std_amd64 ( ) {
std_i386
 }
 
-std_arm ( ) {
-}
-
 std_armv6 ( ) {
 }
 

git: a7ae78caaa17 - main - cdefs: Add __writeonly to mark write only vars

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a7ae78caaa17ff840da844c1dcaa780d194c9e20

commit a7ae78caaa17ff840da844c1dcaa780d194c9e20
Author: Andrew Turner 
AuthorDate: 2024-06-12 13:04:13 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 13:04:13 +

cdefs: Add __writeonly to mark write only vars

When a variable in write only and can't be removed, e.g. for API
reasons, it is useful to document this fact similar to __diagused
and __witness_used.

Add __writeonly to tell the compiler and anyone looking at the code
that this variable is expected to only be written to, and to not
raise and error.

Reviewed by:imp, kib
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45561
---
 sys/sys/cdefs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/sys/cdefs.h b/sys/sys/cdefs.h
index 037dfa55f923..c3268791787f 100644
--- a/sys/sys/cdefs.h
+++ b/sys/sys/cdefs.h
@@ -180,6 +180,7 @@
 #define__aligned(x)__attribute__((__aligned__(x)))
 #define__section(x)__attribute__((__section__(x)))
 #endif
+#define__writeonly __unused
 #if __GNUC_PREREQ__(4, 3) || __has_attribute(__alloc_size__)
 #define__alloc_size(x) __attribute__((__alloc_size__(x)))
 #define__alloc_size2(n, x) __attribute__((__alloc_size__(n, x)))

git: 19782e5bef34 - main - ibcore: Mark write-only variables

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=19782e5bef3403a6ed65d46653f2e70f81dced37

commit 19782e5bef3403a6ed65d46653f2e70f81dced37
Author: Andrew Turner 
AuthorDate: 2024-06-12 13:04:45 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 13:04:45 +

ibcore: Mark write-only variables

Some LinuxKPI lock macros pass need a flags field passed in. This is
written to but never read from so gcc complains.

Fix this by marking the flags variables as unused to quieten the
compiler.

Reviewed by:brooks (earlier version), kib
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45303
---
 sys/ofed/drivers/infiniband/core/ib_cache.c | 16 
 sys/ofed/drivers/infiniband/core/ib_cm.c|  4 ++--
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/sys/ofed/drivers/infiniband/core/ib_cache.c 
b/sys/ofed/drivers/infiniband/core/ib_cache.c
index b170f2b637f9..d2cc680796ef 100644
--- a/sys/ofed/drivers/infiniband/core/ib_cache.c
+++ b/sys/ofed/drivers/infiniband/core/ib_cache.c
@@ -465,7 +465,7 @@ static int _ib_cache_gid_table_find(struct ib_device 
*ib_dev,
struct ib_gid_table *table;
u8 p;
int local_index;
-   unsigned long flags;
+   unsigned long flags __writeonly;
 
for (p = 0; p < ib_dev->phys_port_cnt; p++) {
table = ports_table[p];
@@ -514,7 +514,7 @@ int ib_find_cached_gid_by_port(struct ib_device *ib_dev,
unsigned long mask = GID_ATTR_FIND_MASK_GID |
 GID_ATTR_FIND_MASK_GID_TYPE;
struct ib_gid_attr val = {.ndev = ndev, .gid_type = gid_type};
-   unsigned long flags;
+   unsigned long flags __writeonly;
 
if (!rdma_is_port_valid(ib_dev, port))
return -ENOENT;
@@ -570,7 +570,7 @@ static int ib_cache_gid_find_by_filter(struct ib_device 
*ib_dev,
struct ib_gid_table **ports_table = ib_dev->cache.gid_cache;
struct ib_gid_table *table;
unsigned int i;
-   unsigned long flags;
+   unsigned long flags __writeonly;
bool found = false;
 
if (!ports_table)
@@ -879,7 +879,7 @@ int ib_get_cached_gid(struct ib_device *device,
  struct ib_gid_attr *gid_attr)
 {
int res;
-   unsigned long flags;
+   unsigned long flags __writeonly;
struct ib_gid_table **ports_table = device->cache.gid_cache;
struct ib_gid_table *table = ports_table[port_num - 
rdma_start_port(device)];
 
@@ -929,7 +929,7 @@ int ib_get_cached_pkey(struct ib_device *device,
   u16  *pkey)
 {
struct ib_pkey_cache *cache;
-   unsigned long flags;
+   unsigned long flags __writeonly;
int ret = 0;
 
if (!rdma_is_port_valid(device, port_num))
@@ -956,7 +956,7 @@ int ib_find_cached_pkey(struct ib_device *device,
u16  *index)
 {
struct ib_pkey_cache *cache;
-   unsigned long flags;
+   unsigned long flags __writeonly;
int i;
int ret = -ENOENT;
int partial_ix = -1;
@@ -997,7 +997,7 @@ int ib_find_exact_cached_pkey(struct ib_device *device,
  u16  *index)
 {
struct ib_pkey_cache *cache;
-   unsigned long flags;
+   unsigned long flags __writeonly;
int i;
int ret = -ENOENT;
 
@@ -1027,7 +1027,7 @@ int ib_get_cached_lmc(struct ib_device *device,
  u8port_num,
  u8*lmc)
 {
-   unsigned long flags;
+   unsigned long flags __writeonly;
int ret = 0;
 
if (!rdma_is_port_valid(device, port_num))
diff --git a/sys/ofed/drivers/infiniband/core/ib_cm.c 
b/sys/ofed/drivers/infiniband/core/ib_cm.c
index 3ee17a847720..7ace287b1c88 100644
--- a/sys/ofed/drivers/infiniband/core/ib_cm.c
+++ b/sys/ofed/drivers/infiniband/core/ib_cm.c
@@ -4057,7 +4057,7 @@ static void cm_add_one(struct ib_device *ib_device)
struct ib_port_modify port_modify = {
.set_port_cap_mask = IB_PORT_CM_SUP
};
-   unsigned long flags;
+   unsigned long flags __writeonly;
int ret;
int count = 0;
u8 i;
@@ -4150,7 +4150,7 @@ static void cm_remove_one(struct ib_device *ib_device, 
void *client_data)
struct ib_port_modify port_modify = {
.clr_port_cap_mask = IB_PORT_CM_SUP
};
-   unsigned long flags;
+   unsigned long flags __writeonly;
int i;
 
if (!cm_dev)

git: 4eec584d79c1 - main - arm64: Clear td_frame when returning to userspace

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=4eec584d79c1e8375d863c7eec7229ac7ec3f13b

commit 4eec584d79c1e8375d863c7eec7229ac7ec3f13b
Author: Andrew Turner 
AuthorDate: 2024-06-12 13:08:13 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 13:08:13 +

arm64: Clear td_frame when returning to userspace

When returning from an exception to userspace clear the saved td_frame.
On the next exception this should point to the frame, however this is
not guaranteed.

To ensure the trap frame pointer is either valid or NULL clear it
before returning to userspace in the EL0 synchronous exception handler.

Reviewed by:kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D44807
---
 sys/arm64/arm64/exception.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S
index 662684588e0c..3dff834e27a2 100644
--- a/sys/arm64/arm64/exception.S
+++ b/sys/arm64/arm64/exception.S
@@ -252,9 +252,11 @@ ENTRY(handle_el0_sync)
KMSAN_ENTER
ldr x0, [x18, #PC_CURTHREAD]
mov x1, sp
+   mov x22, x0
str x1, [x0, #TD_FRAME]
bl  do_el0_sync
do_ast
+   str xzr, [x22, #TD_FRAME]
KMSAN_LEAVE
restore_registers 0
ERET

git: a30149b2a9c6 - main - arm64: Create a version of vfp_save_state for cpu_switch

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a30149b2a9c6ac5280523eea9570e5b5e5f1fdf8

commit a30149b2a9c6ac5280523eea9570e5b5e5f1fdf8
Author: Andrew Turner 
AuthorDate: 2024-06-12 13:09:14 +
Commit: Andrew Turner 
CommitDate: 2024-06-12 13:09:14 +

arm64: Create a version of vfp_save_state for cpu_switch

This will be used when we add SVE support to reduce the registers
needed to be saved on context switch.

Reviewed by:imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43305
---
 sys/arm64/arm64/swtch.S | 4 +---
 sys/arm64/arm64/vfp.c   | 8 
 sys/arm64/include/vfp.h | 1 +
 3 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/arm64/swtch.S b/sys/arm64/arm64/swtch.S
index ca00d473fd47..6af70ca839a0 100644
--- a/sys/arm64/arm64/swtch.S
+++ b/sys/arm64/arm64/swtch.S
@@ -148,9 +148,7 @@ ENTRY(cpu_switch)
mov x21, x2
 
 #ifdef VFP
-   /* Load the pcb address */
-   mov x1, x4
-   bl  vfp_save_state
+   bl  vfp_save_state_switch
mov x0, x20
 #else
mov x0, x1
diff --git a/sys/arm64/arm64/vfp.c b/sys/arm64/arm64/vfp.c
index f35cd960702b..c65108a83399 100644
--- a/sys/arm64/arm64/vfp.c
+++ b/sys/arm64/arm64/vfp.c
@@ -216,6 +216,14 @@ vfp_save_state_savectx(struct pcb *pcb)
vfp_save_state_common(curthread, pcb);
 }
 
+void
+vfp_save_state_switch(struct thread *td)
+{
+   KASSERT(td != NULL, ("NULL vfp thread"));
+
+   vfp_save_state_common(td, td->td_pcb);
+}
+
 /*
  * Update the VFP state for a forked process or new thread. The PCB will
  * have been copied from the old thread.
diff --git a/sys/arm64/include/vfp.h b/sys/arm64/include/vfp.h
index 7f4c86e7737d..47d068d6050c 100644
--- a/sys/arm64/include/vfp.h
+++ b/sys/arm64/include/vfp.h
@@ -79,6 +79,7 @@ void  vfp_reset_state(struct thread *, struct pcb *);
 void   vfp_restore_state(void);
 void   vfp_save_state(struct thread *, struct pcb *);
 void   vfp_save_state_savectx(struct pcb *);
+void   vfp_save_state_switch(struct thread *);
 
 struct fpu_kern_ctx;
 

git: a67a0a6a2088 - main - nanobsd: Remove armv6 support

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a67a0a6a20886eef5f74db57e349c5c9cc465e58

commit a67a0a6a20886eef5f74db57e349c5c9cc465e58
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:06 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:06 +

nanobsd: Remove armv6 support

In preparation for removing armv6 remove it from nanobsd.

Reviewed by:imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45635
---
 tools/tools/nanobsd/embedded/common  |  5 +
 tools/tools/nanobsd/embedded/rpi.cfg | 35 ---
 2 files changed, 1 insertion(+), 39 deletions(-)

diff --git a/tools/tools/nanobsd/embedded/common 
b/tools/tools/nanobsd/embedded/common
index 4f5eac7806f2..4aecd3602f6f 100644
--- a/tools/tools/nanobsd/embedded/common
+++ b/tools/tools/nanobsd/embedded/common
@@ -52,7 +52,7 @@
 # o msdos mtools fallback
 # o special boot for !x86 !arm platforms
 # o qemu image for aarch64
-# o qemu image for armv6/armv7
+# o qemu image for armv7
 # o easy support for different image / vm formats
 # o need to promote much of this to nanobsd.sh and friends
 # o uses old kludge to build image w/o ownership being right
@@ -502,9 +502,6 @@ std_amd64 ( ) {
std_i386
 }
 
-std_armv6 ( ) {
-}
-
 std_armv7 ( ) {
 }
 
diff --git a/tools/tools/nanobsd/embedded/rpi.cfg 
b/tools/tools/nanobsd/embedded/rpi.cfg
deleted file mode 100644
index 54d2b559290b..
--- a/tools/tools/nanobsd/embedded/rpi.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-
-#-
-# Copyright (c) 2015 M. Warner Losh 
-# Copyright (c) 2010-2011 iXsystems, Inc.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-# 1. Redistributions of source code must retain the above copyright
-#notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#notice, this list of conditions and the following disclaimer in the
-#documentation and/or other materials provided with the distribution.
-#
-# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-# ARE DISCLAIMED.  IN NO EVENT SHALL iXsystems, Inc. OR CONTRIBUTORS BE LIABLE
-# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-# SUCH DAMAGE.
-#
-
-NANO_ARCH=armv6
-NANO_KERNEL=RPI-B
-NANO_DRIVE=mmcsd0
-NANO_NAME=rpi-b
-NANO_BOOT_PKG=u-boot-rpi
-NANO_CPUTYPE=arm1176jzf-s
-
-. common   # Pull in common definitions, keep last

git: eda7eff0d266 - main - share/examples/etc/make.conf: Remove old arm archs

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=eda7eff0d266b9644f047469ce7c739a4ef2681a

commit eda7eff0d266b9644f047469ce7c739a4ef2681a
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:10 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:10 +

share/examples/etc/make.conf: Remove old arm archs

Remove the pre-armv7 architecture options from the example make.conf.
These have either been removed, or will soon be removed from the build.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45636
---
 share/examples/etc/make.conf | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/share/examples/etc/make.conf b/share/examples/etc/make.conf
index 0cf156371aec..93c611557cb6 100644
--- a/share/examples/etc/make.conf
+++ b/share/examples/etc/make.conf
@@ -43,8 +43,7 @@
 #  pentium3m, pentium3, pentium-m, pentium2, pentiumpro,
 #  pentium-mmx, pentium, i486
 #   (VIA CPUs) c7, c3-2, c3
-#   ARM architecture:  armv5, armv5te, armv6, armv6t2, arm1176jzf-s, armv7,
-#  armv7-a, armv7ve, generic-armv7-a, cortex-a5,
+#   ARM architecture:  armv7, armv7-a, armv7ve, generic-armv7-a, cortex-a5,
 #  cortex-a7, cortex-a8, cortex-a9, cortex-a12,
 #  cortex-a15, cortex-a17
 #   ARM64 architecture:cortex-a53, cortex-a57, cortex-a72,
@@ -78,7 +77,7 @@
 #
 # CFLAGS+= -msse3
 # CXXFLAGS+=   -msse3
-# CFLAGS.armv6+= -mfloat-abi=softfp
+# CFLAGS.armv7+= -mfloat-abi=softfp
 #
 # MAKE_SHELL controls the shell used internally by make(1) to process the
 # command scripts in makefiles.  Three shells are supported, sh, ksh, and

git: 8203cf1c53f0 - main - md.4: Remove armv6 as it is being removed

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=8203cf1c53f05ddb92075480cdf30c066b37ee4d

commit 8203cf1c53f05ddb92075480cdf30c066b37ee4d
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:12 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:12 +

md.4: Remove armv6 as it is being removed

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45637
---
 share/man/man4/md.4 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/share/man/man4/md.4 b/share/man/man4/md.4
index acd52aecb675..0c99d61f8392 100644
--- a/share/man/man4/md.4
+++ b/share/man/man4/md.4
@@ -98,7 +98,7 @@ disk found in the
 man page.
 Other tools will also create these images, such as NanoBSD.
 .Sh ARM KERNEL OPTIONS
-On armv6 and armv7 architectures, an MD_ROOT image larger than
+On the armv7 architecture, an MD_ROOT image larger than
 approximately 55 MiB may require building a custom kernel using
 several tuning options related to kernel memory usage.
 .Bl -tag -width indent

git: e726eed75d87 - main - share/mk: Remove pre-armv7 example architectures

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=e726eed75d87c7306c179e17c671e92e9fe61937

commit e726eed75d87c7306c179e17c671e92e9fe61937
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:14 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:14 +

share/mk: Remove pre-armv7 example architectures

These are already removed from the tree, or are in the process of being
removed.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45638
---
 share/mk/bsd.cpu.mk | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk
index 730e4b4aa152..793c01b76dca 100644
--- a/share/mk/bsd.cpu.mk
+++ b/share/mk/bsd.cpu.mk
@@ -108,16 +108,11 @@ _CPUCFLAGS = -mfloat-abi=softfp
 _CPUCFLAGS = -march=armv7 -mfpu=vfp
 .  elif ${CPUTYPE:Marmv[67]*} != ""
 # Handle all the armvX types that FreeBSD runs:
-#  armv6, armv6t2, armv7, armv7-a, armv7ve
+#  armv7, armv7-a, armv7ve
 # they require -march=. All the others require -mcpu=.
 _CPUCFLAGS = -march=${CPUTYPE}
 .  else
 # Common values for FreeBSD
-# arm: (any arm v4 or v5 processor you are targeting)
-#  arm920t, arm926ej-s, marvell-pj4, fa526, fa626,
-#  fa606te, fa626te, fa726te
-# armv6:
-#  arm1176jzf-s
 # armv7: generic-armv7-a, cortex-a5, cortex-a7, cortex-a8, cortex-a9,
 #   cortex-a12, cortex-a15, cortex-a17
 #   cortex-a53, cortex-a57, cortex-a72,

git: a2054786c255 - main - uefi.8: Remove a reference to armv6

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a2054786c255a79ed5ab25630013c868aca19480

commit a2054786c255a79ed5ab25630013c868aca19480
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:16 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:16 +

uefi.8: Remove a reference to armv6

It is in the process of being removed from the tree.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45640
---
 share/man/man8/uefi.8 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/share/man/man8/uefi.8 b/share/man/man8/uefi.8
index 7a684f6b092b..fa4770188d61 100644
--- a/share/man/man8/uefi.8
+++ b/share/man/man8/uefi.8
@@ -126,7 +126,7 @@ boot support for amd64 first appeared in
 .Fx 10.1 ;
 for arm64 in
 .Fx 11.0 ;
-for armv6 and armv7 in
+for armv7 in
 .Fx 12.0 ;
 and for riscv in
 .Fx 13.0 .

git: 68f044de29b3 - main - binmiscctl.8: Change the example to armv7

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=68f044de29b3867c2e0d282b86395f777f95b034

commit 68f044de29b3867c2e0d282b86395f777f95b034
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:18 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:18 +

binmiscctl.8: Change the example to armv7

armv6 is in the process of being removed.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45641
---
 usr.sbin/binmiscctl/binmiscctl.8 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/usr.sbin/binmiscctl/binmiscctl.8 b/usr.sbin/binmiscctl/binmiscctl.8
index 178389920448..4a4890146b57 100644
--- a/usr.sbin/binmiscctl/binmiscctl.8
+++ b/usr.sbin/binmiscctl/binmiscctl.8
@@ -288,15 +288,15 @@ Add QEMU bsd-user program as an image activator for 
64-bit RISC-V binaries:
\exff\exff\exff\exff\exff\exff\exfe\exff\exff\exff" \e
   --size 20 --set-enabled
 .Ed
-.Ss "Create and use an ARMv6 chroot on an AMD64 host"
+.Ss "Create and use an ARMv7 chroot on an AMD64 host"
 Use an existing source tree to build a chroot host with architecture
 overrides:
 .Bd -literal -offset ident
 D=/path/to/chroot
 cd /usr/src
 mkdir -p $D
-make world TARGET=arm TARGET_ARCH=armv6 DESTDIR=$D
-make distribution TARGET=arm TARGET_ARCH=armv6 DESTDIR=$D
+make world TARGET=arm TARGET_ARCH=armv7 DESTDIR=$D
+make distribution TARGET=arm TARGET_ARCH=armv7 DESTDIR=$D
 .Ed
 .Pp
 With

git: 4f351c1ddcfb - main - tools/boot/universe.sh: Remove armv6 from a comment

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=4f351c1ddcfbd74a93e9969ab7b99f09e785de55

commit 4f351c1ddcfbd74a93e9969ab7b99f09e785de55
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:20 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:20 +

tools/boot/universe.sh: Remove armv6 from a comment

It is in the process of being removed.

Reviewed by:manu, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45642
---
 tools/boot/universe.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/boot/universe.sh b/tools/boot/universe.sh
index 3e033ce26ae2..e97858ff2bcb 100755
--- a/tools/boot/universe.sh
+++ b/tools/boot/universe.sh
@@ -3,7 +3,7 @@
 #
 # Full list of all arches we don't build.
 #
-#  powerpc/powerpcspe arm/armv6
+#  powerpc/powerpcspe
 #
 # This script is expected to be run in stand (though you could run it anywhere
 # in the tree). It does a full clean build. For stand you can do all the archs 
in

git: 6eeedf35c3ec - main - libc: Replace armv6 with armv7 in a comment

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=6eeedf35c3ecf50cc3def1eaa40a37b2257b85ac

commit 6eeedf35c3ecf50cc3def1eaa40a37b2257b85ac
Author: Andrew Turner 
AuthorDate: 2024-06-20 09:26:22 +
Commit: Andrew Turner 
CommitDate: 2024-06-20 09:26:22 +

libc: Replace armv6 with armv7 in a comment

Armv6 is being removed from the treem and the comment applies to armv7.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45645
---
 lib/libc/arm/aeabi/aeabi_double.c | 2 +-
 lib/libc/arm/aeabi/aeabi_float.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/libc/arm/aeabi/aeabi_double.c 
b/lib/libc/arm/aeabi/aeabi_double.c
index 190354e5c6eb..61f64678e795 100644
--- a/lib/libc/arm/aeabi/aeabi_double.c
+++ b/lib/libc/arm/aeabi/aeabi_double.c
@@ -54,7 +54,7 @@ float64 __aeabi_dsub_vfp(float64, float64);
 
 /*
  * Depending on the target these will:
- *  On armv6 with a vfp call the above function, or
+ *  On armv7 with a vfp call the above function, or
  *  Call the softfloat function in the 3rd argument.
  */
 int AEABI_FUNC2(dcmpeq, float64, float64_eq)
diff --git a/lib/libc/arm/aeabi/aeabi_float.c b/lib/libc/arm/aeabi/aeabi_float.c
index ac6b11ae9dfe..0e465754ecf0 100644
--- a/lib/libc/arm/aeabi/aeabi_float.c
+++ b/lib/libc/arm/aeabi/aeabi_float.c
@@ -54,7 +54,7 @@ float32 __aeabi_fsub_vfp(float32, float32);
 
 /*
  * Depending on the target these will:
- *  On armv6 with a vfp call the above function, or
+ *  On armv7 with a vfp call the above function, or
  *  Call the softfloat function in the 3rd argument.
  */
 int AEABI_FUNC2(fcmpeq, float32, float32_eq)

git: 915161b3d35e - main - hwpmc/arm64: fix the type for pm_arm64_evsel

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=915161b3d35ed5a742e3a8d90d215a2d930dd199

commit 915161b3d35ed5a742e3a8d90d215a2d930dd199
Author: Andrew Turner 
AuthorDate: 2024-06-25 08:41:37 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:07:19 +

hwpmc/arm64: fix the type for pm_arm64_evsel

It holds a 64-bit register, use a uint64_t.

Reviewed by:mhorne
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45526
---
 sys/dev/hwpmc/hwpmc_arm64.c | 7 ---
 sys/dev/hwpmc/hwpmc_arm64.h | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c
index af8d25b098c4..4b2fd5cc746f 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.c
+++ b/sys/dev/hwpmc/hwpmc_arm64.c
@@ -163,7 +163,7 @@ static int
 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
   const struct pmc_op_pmcallocate *a)
 {
-   uint32_t config;
+   uint64_t config;
enum pmc_event pe;
 
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
@@ -201,7 +201,8 @@ arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
}
 
pm->pm_md.pm_arm64.pm_arm64_evsel = config;
-   PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
+   PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%lx", ri,
+   config);
 
return (0);
 }
@@ -299,7 +300,7 @@ arm64_config_pmc(int cpu, int ri, struct pmc *pm)
 static int
 arm64_start_pmc(int cpu, int ri, struct pmc *pm)
 {
-   uint32_t config;
+   uint64_t config;
 
config = pm->pm_md.pm_arm64.pm_arm64_evsel;
 
diff --git a/sys/dev/hwpmc/hwpmc_arm64.h b/sys/dev/hwpmc/hwpmc_arm64.h
index e1f605a0371b..97909d8e7c92 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.h
+++ b/sys/dev/hwpmc/hwpmc_arm64.h
@@ -42,7 +42,7 @@
 #ifdef _KERNEL
 /* MD extension for 'struct pmc' */
 struct pmc_md_arm64_pmc {
-   uint32_tpm_arm64_evsel;
+   uint64_tpm_arm64_evsel;
 };
 #endif /* _KERNEL */
 #endif /* _DEV_HWPMC_ARMV8_H_ */

git: c36fa8d5022d - main - hwpmc/arm64: Support the kernel booting to VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=c36fa8d5022db8b4cca01b391d9d82f26c632234

commit c36fa8d5022db8b4cca01b391d9d82f26c632234
Author: Andrew Turner 
AuthorDate: 2024-06-25 08:41:50 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:07:19 +

hwpmc/arm64: Support the kernel booting to VHE

When booting to VHE we need to handle using the PMU at either EL1 or
EL2. WE already support EL1 so add support for EL2.

Reviewed by:mhorne
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45527
---
 sys/dev/hwpmc/hwpmc_arm64.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c
index 4b2fd5cc746f..5d221c738c2f 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.c
+++ b/sys/dev/hwpmc/hwpmc_arm64.c
@@ -34,6 +34,7 @@
 
 #include 
 #include 
+#include 
 
 #include "opt_acpi.h"
 
@@ -186,10 +187,18 @@ arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
 
switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) {
case PMC_CAP_SYSTEM:
+   /* Exclude EL0 */
config |= PMEVTYPER_U;
+   if (in_vhe()) {
+   /* If in VHE we need to include EL2 and exclude EL1 */
+   config |= PMEVTYPER_NSH | PMEVTYPER_P;
+   }
break;
case PMC_CAP_USER:
+   /* Exclude EL1 */
config |= PMEVTYPER_P;
+   /* Exclude EL2 */
+   config &= ~PMEVTYPER_NSH;
break;
default:
/*
@@ -197,6 +206,10 @@ arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
 * (default setting) or if both flags are specified
 * (user explicitly requested both qualifiers).
 */
+   if (in_vhe()) {
+   /* If in VHE we need to include EL2 */
+   config |= PMEVTYPER_NSH;
+   }
break;
}
 

git: 0cdd0032a769 - main - arm64/vmm: Fix the SPAN check

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=0cdd0032a769a727b0e41298e388853ff59007e8

commit 0cdd0032a769a727b0e41298e388853ff59007e8
Author: Andrew Turner 
AuthorDate: 2024-06-25 08:41:57 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:07:19 +

arm64/vmm: Fix the SPAN check

When raising an exception we may need to set the SPSR_EL1.PAN field.
The check for this was incorrect meaning it would be set when it
shouldn't be.

Reviewed by:markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45717
---
 sys/arm64/vmm/vmm_arm64.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index 1b61871014a7..e5eee47b405b 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -1108,7 +1108,7 @@ vmmops_run(void *vcpui, register_t pc, pmap_t pmap, 
struct vm_eventinfo *evinfo)
 * Update fields that may change on exeption entry
 * based on how sctlr_el1 is configured.
 */
-   if ((hypctx->sctlr_el1 & SCTLR_SPAN) != 0)
+   if ((hypctx->sctlr_el1 & SCTLR_SPAN) == 0)
hypctx->tf.tf_spsr |= PSR_PAN;
if ((hypctx->sctlr_el1 & SCTLR_DSSBS) == 0)
hypctx->tf.tf_spsr &= ~PSR_SSBS;

git: 940cf92c0786 - main - WIP: Switch to compiler-rt sync on armv7

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=940cf92c07867bcfb1cd5648cffc5df25fd0b92a

commit 940cf92c07867bcfb1cd5648cffc5df25fd0b92a
Author: Andrew Turner 
AuthorDate: 2024-06-24 08:11:27 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:07:19 +

WIP: Switch to compiler-rt sync on armv7
---
 lib/libcompiler_rt/Makefile.inc | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/lib/libcompiler_rt/Makefile.inc b/lib/libcompiler_rt/Makefile.inc
index bdb6b93e6fda..7b4de36f87e2 100644
--- a/lib/libcompiler_rt/Makefile.inc
+++ b/lib/libcompiler_rt/Makefile.inc
@@ -270,6 +270,13 @@ SRCF+= truncsfbf2
 
 SRCF+= stdatomic
 CFLAGS+=   -DEMIT_SYNC_ATOMICS
+
+#.for op in add and max min nand or sub umax umin xor
+#. for size in 4 8
+#SRCF+=sync_fetch_and_${op}_${size}
+#. endfor
+#.endfor
+
 .endif
 
 .for file in ${SRCF}

git: 3d02fe6c59dc - main - arm: Start to remove the now unneeded acle-compat.h

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=3d02fe6c59dc87b265f268233cd574f7f04edb5d

commit 3d02fe6c59dc87b265f268233cd574f7f04edb5d
Author: Andrew Turner 
AuthorDate: 2024-06-25 08:59:42 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:07:19 +

arm: Start to remove the now unneeded acle-compat.h

All supported compilers provide the acle macros so we don't need the
backup versions.

Sponsored by:   Arm Ltd
---
 sys/arm/include/acle-compat.h | 158 +-
 1 file changed, 3 insertions(+), 155 deletions(-)

diff --git a/sys/arm/include/acle-compat.h b/sys/arm/include/acle-compat.h
index 0d5726b7846c..75e7e3774491 100644
--- a/sys/arm/include/acle-compat.h
+++ b/sys/arm/include/acle-compat.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 ARM Ltd
+ * Copyright (c) 2024 Arm Ltd
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,157 +27,5 @@
  */
 
 #ifndef __ARM_ARCH
-
-/* ACLE standardises a set of pre-defines that describe the ARM architecture.
-   These were mostly implemented in GCC around GCC-4.8; older versions
-   have no, or only partial support.  To provide a level of backwards
-   compatibility we try to work out what the definitions should be, given
-   the older pre-defines that GCC did produce.  This isn't complete, but
-   it should be enough for use by routines that depend on this header.  */
-
-/* No need to handle ARMv8, GCC had ACLE support before that.  */
-
-#define __ARM_ACLE 101
-
-# ifdef __ARM_ARCH_7__
-/* The common subset of ARMv7 in all profiles.  */
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-# endif
-
-# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 15
-#  define __ARM_FEATURE_UNALIGNED
-#  ifdef __ARM_ARCH_7A__
-#   define __ARM_ARCH_PROFILE 'A'
-#  else
-#   define __ARM_ARCH_PROFILE 'R'
-#  endif
-# endif
-
-# ifdef __ARM_ARCH_7EM__
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# ifdef __ARM_ARCH_7M__
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# ifdef __ARM_ARCH_6T2__
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 4
-#  define __ARM_FEATURE_UNALIGNED
-# endif
-
-# ifdef __ARM_ARCH_6M__
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 1
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
-  || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
-  || defined (__ARM_ARCH_6ZK__)
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 1
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_UNALIGNED
-#  ifndef __thumb__
-#   if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
-#define __ARM_FEATURE_LDREX 15
-#   else
-#define __ARM_FEATURE_LDREX 4
-#   endif
-#  endif
-# endif
-
-# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
-#  define __ARM_ARCH 5
-#  define __ARM_ARCH_ISA_ARM
-#  ifdef __ARM_ARCH_5TE__
-#   define __ARM_ARCH_ISA_THUMB 1
-#  endif
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_DSP
-# endif
-
-# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
-#  define __ARM_ARCH 5
-#  define __ARM_ARCH_ISA_ARM
-#  ifdef __ARM_ARCH_5TE__
-#   define __ARM_ARCH_ISA_THUMB 1
-#  endif
-#  define __ARM_FEATURE_CLZ
-# endif
-
-# ifdef __ARM_ARCH_4T__
-#  define __ARM_ARCH 4
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_ARCH_ISA_THUMB 1
-# endif
-
-# ifdef __ARM_ARCH_4__
-#  define __ARM_ARCH 4
-#  define __ARM_ARCH_ISA_ARM
-# endif
-
-# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
-#  define __ARM_ARCH 3
-#  define __ARM_ARCH_ISA_ARM
-# endif
-
-# ifdef __ARM_ARCH_2__
-#  define __ARM_ARCH 2

git: 8521ea135f5b - main - Revert "WIP: Switch to compiler-rt sync on armv7"

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=8521ea135f5b1a24c2ce631777d4e497d43d0278

commit 8521ea135f5b1a24c2ce631777d4e497d43d0278
Author: Andrew Turner 
AuthorDate: 2024-06-25 09:37:38 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:37:38 +

Revert "WIP: Switch to compiler-rt sync on armv7"

This reverts commit 940cf92c07867bcfb1cd5648cffc5df25fd0b92a.

This wasn't ready to be committed
---
 lib/libcompiler_rt/Makefile.inc | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/lib/libcompiler_rt/Makefile.inc b/lib/libcompiler_rt/Makefile.inc
index 7b4de36f87e2..bdb6b93e6fda 100644
--- a/lib/libcompiler_rt/Makefile.inc
+++ b/lib/libcompiler_rt/Makefile.inc
@@ -270,13 +270,6 @@ SRCF+= truncsfbf2
 
 SRCF+= stdatomic
 CFLAGS+=   -DEMIT_SYNC_ATOMICS
-
-#.for op in add and max min nand or sub umax umin xor
-#. for size in 4 8
-#SRCF+=sync_fetch_and_${op}_${size}
-#. endfor
-#.endfor
-
 .endif
 
 .for file in ${SRCF}

git: 36e0db4916c5 - main - Revert "arm: Start to remove the now unneeded acle-compat.h"

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=36e0db4916c5957dbea4e8451b15bd7b846ed272

commit 36e0db4916c5957dbea4e8451b15bd7b846ed272
Author: Andrew Turner 
AuthorDate: 2024-06-25 09:37:14 +
Commit: Andrew Turner 
CommitDate: 2024-06-25 09:37:14 +

Revert "arm: Start to remove the now unneeded acle-compat.h"

This reverts commit 3d02fe6c59dc87b265f268233cd574f7f04edb5d.

This wasn't ready to be committed
---
 sys/arm/include/acle-compat.h | 158 +-
 1 file changed, 155 insertions(+), 3 deletions(-)

diff --git a/sys/arm/include/acle-compat.h b/sys/arm/include/acle-compat.h
index 75e7e3774491..0d5726b7846c 100644
--- a/sys/arm/include/acle-compat.h
+++ b/sys/arm/include/acle-compat.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Arm Ltd
+ * Copyright (c) 2014 ARM Ltd
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,5 +27,157 @@
  */
 
 #ifndef __ARM_ARCH
-#error You compiler is too old
-#endif
+
+/* ACLE standardises a set of pre-defines that describe the ARM architecture.
+   These were mostly implemented in GCC around GCC-4.8; older versions
+   have no, or only partial support.  To provide a level of backwards
+   compatibility we try to work out what the definitions should be, given
+   the older pre-defines that GCC did produce.  This isn't complete, but
+   it should be enough for use by routines that depend on this header.  */
+
+/* No need to handle ARMv8, GCC had ACLE support before that.  */
+
+#define __ARM_ACLE 101
+
+# ifdef __ARM_ARCH_7__
+/* The common subset of ARMv7 in all profiles.  */
+#  define __ARM_ARCH 7
+#  define __ARM_ARCH_ISA_THUMB 2
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_LDREX 7
+#  define __ARM_FEATURE_UNALIGNED
+# endif
+
+# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
+#  define __ARM_ARCH 7
+#  define __ARM_ARCH_ISA_THUMB 2
+#  define __ARM_ARCH_ISA_ARM
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_SIMD32
+#  define __ARM_FEATURE_DSP
+#  define __ARM_FEATURE_QBIT
+#  define __ARM_FEATURE_SAT
+#  define __ARM_FEATURE_LDREX 15
+#  define __ARM_FEATURE_UNALIGNED
+#  ifdef __ARM_ARCH_7A__
+#   define __ARM_ARCH_PROFILE 'A'
+#  else
+#   define __ARM_ARCH_PROFILE 'R'
+#  endif
+# endif
+
+# ifdef __ARM_ARCH_7EM__
+#  define __ARM_ARCH 7
+#  define __ARM_ARCH_ISA_THUMB 2
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_SIMD32
+#  define __ARM_FEATURE_DSP
+#  define __ARM_FEATURE_QBIT
+#  define __ARM_FEATURE_SAT
+#  define __ARM_FEATURE_LDREX 7
+#  define __ARM_FEATURE_UNALIGNED
+#  define __ARM_ARCH_PROFILE 'M'
+# endif
+
+# ifdef __ARM_ARCH_7M__
+#  define __ARM_ARCH 7
+#  define __ARM_ARCH_ISA_THUMB 2
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_QBIT
+#  define __ARM_FEATURE_SAT
+#  define __ARM_FEATURE_LDREX 7
+#  define __ARM_FEATURE_UNALIGNED
+#  define __ARM_ARCH_PROFILE 'M'
+# endif
+
+# ifdef __ARM_ARCH_6T2__
+#  define __ARM_ARCH 6
+#  define __ARM_ARCH_ISA_THUMB 2
+#  define __ARM_ARCH_ISA_ARM
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_SIMD32
+#  define __ARM_FEATURE_DSP
+#  define __ARM_FEATURE_QBIT
+#  define __ARM_FEATURE_SAT
+#  define __ARM_FEATURE_LDREX 4
+#  define __ARM_FEATURE_UNALIGNED
+# endif
+
+# ifdef __ARM_ARCH_6M__
+#  define __ARM_ARCH 6
+#  define __ARM_ARCH_ISA_THUMB 1
+#  define __ARM_ARCH_PROFILE 'M'
+# endif
+
+# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
+  || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
+  || defined (__ARM_ARCH_6ZK__)
+#  define __ARM_ARCH 6
+#  define __ARM_ARCH_ISA_THUMB 1
+#  define __ARM_ARCH_ISA_ARM
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_SIMD32
+#  define __ARM_FEATURE_DSP
+#  define __ARM_FEATURE_QBIT
+#  define __ARM_FEATURE_SAT
+#  define __ARM_FEATURE_UNALIGNED
+#  ifndef __thumb__
+#   if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
+#define __ARM_FEATURE_LDREX 15
+#   else
+#define __ARM_FEATURE_LDREX 4
+#   endif
+#  endif
+# endif
+
+# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
+#  define __ARM_ARCH 5
+#  define __ARM_ARCH_ISA_ARM
+#  ifdef __ARM_ARCH_5TE__
+#   define __ARM_ARCH_ISA_THUMB 1
+#  endif
+#  define __ARM_FEATURE_CLZ
+#  define __ARM_FEATURE_DSP
+# endif
+
+# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
+#  define __ARM_ARCH 5
+#  define __ARM_ARCH_ISA_ARM
+#  ifdef __ARM_ARCH_5TE__
+#   define __ARM_ARCH_ISA_THUMB 1
+#  endif
+#  define __ARM_FEATURE_CLZ
+# endif
+
+# ifdef __ARM_ARCH_4T__
+#  define __ARM_ARCH 4
+#  define __ARM_ARCH_ISA_ARM
+#  define __ARM_ARCH_ISA_THUMB 1
+# endif
+
+# ifdef __ARM_ARCH_4__
+#  define __ARM_ARCH 4
+#  define __ARM_ARCH_ISA_ARM
+# endif
+
+# if defined (__ARM_ARCH_3__) || defined (__ARM_ARCH_3M__)
+#  define __ARM_ARCH 3
+#  define __ARM_ARCH_ISA_ARM
+# endif
+
+# ifde

git: 5afc347944e7 - main - arm: Start to remove the now unneeded acle-compat.h

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=5afc347944e760774797b3275124591d69228fc1

commit 5afc347944e760774797b3275124591d69228fc1
Author: Andrew Turner 
AuthorDate: 2024-06-25 08:59:42 +
Commit: Andrew Turner 
CommitDate: 2024-06-26 08:52:08 +

arm: Start to remove the now unneeded acle-compat.h

All supported compilers provide the acle macros so we don't need the
backup versions.

Keep the file around for anything that included it directly, but make
it an error to not support the acle macros.

Reviewed by:imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45726
---
 sys/arm/include/acle-compat.h | 158 +-
 1 file changed, 3 insertions(+), 155 deletions(-)

diff --git a/sys/arm/include/acle-compat.h b/sys/arm/include/acle-compat.h
index 0d5726b7846c..6ab48ac16669 100644
--- a/sys/arm/include/acle-compat.h
+++ b/sys/arm/include/acle-compat.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014 ARM Ltd
+ * Copyright (c) 2024 Arm Ltd
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,157 +27,5 @@
  */
 
 #ifndef __ARM_ARCH
-
-/* ACLE standardises a set of pre-defines that describe the ARM architecture.
-   These were mostly implemented in GCC around GCC-4.8; older versions
-   have no, or only partial support.  To provide a level of backwards
-   compatibility we try to work out what the definitions should be, given
-   the older pre-defines that GCC did produce.  This isn't complete, but
-   it should be enough for use by routines that depend on this header.  */
-
-/* No need to handle ARMv8, GCC had ACLE support before that.  */
-
-#define __ARM_ACLE 101
-
-# ifdef __ARM_ARCH_7__
-/* The common subset of ARMv7 in all profiles.  */
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-# endif
-
-# if defined (__ARM_ARCH_7A__) || defined (__ARM_ARCH_7R__)
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 15
-#  define __ARM_FEATURE_UNALIGNED
-#  ifdef __ARM_ARCH_7A__
-#   define __ARM_ARCH_PROFILE 'A'
-#  else
-#   define __ARM_ARCH_PROFILE 'R'
-#  endif
-# endif
-
-# ifdef __ARM_ARCH_7EM__
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# ifdef __ARM_ARCH_7M__
-#  define __ARM_ARCH 7
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 7
-#  define __ARM_FEATURE_UNALIGNED
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# ifdef __ARM_ARCH_6T2__
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 2
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_LDREX 4
-#  define __ARM_FEATURE_UNALIGNED
-# endif
-
-# ifdef __ARM_ARCH_6M__
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 1
-#  define __ARM_ARCH_PROFILE 'M'
-# endif
-
-# if defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) \
-  || defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) \
-  || defined (__ARM_ARCH_6ZK__)
-#  define __ARM_ARCH 6
-#  define __ARM_ARCH_ISA_THUMB 1
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_SIMD32
-#  define __ARM_FEATURE_DSP
-#  define __ARM_FEATURE_QBIT
-#  define __ARM_FEATURE_SAT
-#  define __ARM_FEATURE_UNALIGNED
-#  ifndef __thumb__
-#   if defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6ZK__)
-#define __ARM_FEATURE_LDREX 15
-#   else
-#define __ARM_FEATURE_LDREX 4
-#   endif
-#  endif
-# endif
-
-# if defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5E__)
-#  define __ARM_ARCH 5
-#  define __ARM_ARCH_ISA_ARM
-#  ifdef __ARM_ARCH_5TE__
-#   define __ARM_ARCH_ISA_THUMB 1
-#  endif
-#  define __ARM_FEATURE_CLZ
-#  define __ARM_FEATURE_DSP
-# endif
-
-# if defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5__)
-#  define __ARM_ARCH 5
-#  define __ARM_ARCH_ISA_ARM
-#  ifdef __ARM_ARCH_5TE__
-#   define __ARM_ARCH_ISA_THUMB 1
-#  endif
-#  define __ARM_FEATURE_CLZ
-# endif
-
-# ifdef __ARM_ARCH_4T__
-#  define __ARM_ARCH 4
-#  define __ARM_ARCH_ISA_ARM
-#  define __ARM_ARCH_ISA_THUMB 1
-# endif
-
-# ifdef __ARM_ARCH_4__
-#  define __ARM_A

git: 7818c2d37c2c - main - armv6: Remove support for building armv6

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7818c2d37c2c600fc9ad6f2a0951e50dd21b17c8

commit 7818c2d37c2c600fc9ad6f2a0951e50dd21b17c8
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:28:35 +
Commit: Andrew Turner 
CommitDate: 2024-07-12 11:31:53 +

armv6: Remove support for building armv6

With it planned that armv7 will be the only 32-bit kernel when 15.0 is
released remove support for armv6.

Remove the top level build infrastructure. It was already removed from
universe, this just stops it from being built directly.

Reviewed by:mmel, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45634
---
 Makefile| 6 +-
 Makefile.inc1   | 1 -
 UPDATING| 3 +++
 sys/sys/param.h | 2 +-
 4 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index b2613b68b645..5c113d5b83cc 100644
--- a/Makefile
+++ b/Makefile
@@ -521,9 +521,6 @@ worlds: .PHONY
 # Don't build rarely used, semi-supported architectures unless requested.
 #
 .if defined(EXTRA_TARGETS)
-# armv6's importance has waned enough to make building it the exception rather
-# than the rule.
-EXTRA_ARCHES_arm=  armv6
 # powerpcspe excluded from main list until clang fixed
 EXTRA_ARCHES_powerpc=  powerpcspe
 .endif
@@ -535,8 +532,7 @@ TARGET_ARCHES_${target}= ${MACHINE_ARCH_LIST_${target}}
 
 .if defined(USE_GCC_TOOLCHAINS)
 TOOLCHAINS_amd64=  amd64-gcc12
-TOOLCHAINS_arm=armv6-gcc12 armv7-gcc12
-TOOLCHAIN_armv7=   armv7-gcc12
+TOOLCHAINS_arm=armv7-gcc12
 TOOLCHAINS_arm64=  aarch64-gcc12
 TOOLCHAINS_i386=   i386-gcc12
 TOOLCHAINS_powerpc=powerpc-gcc12 powerpc64-gcc12
diff --git a/Makefile.inc1 b/Makefile.inc1
index 2f442bc9a394..19ed923702b1 100644
--- a/Makefile.inc1
+++ b/Makefile.inc1
@@ -146,7 +146,6 @@ TARGET_TRIPLE_ABI?= unknown
 TARGET_TRIPLE?=
${TARGET_ARCH:S/amd64/x86_64/}-${TARGET_TRIPLE_ABI}-freebsd${OS_REVISION}
 KNOWN_ARCHES?= aarch64/arm64 \
amd64 \
-   armv6/arm \
armv7/arm \
i386 \
powerpc \
diff --git a/UPDATING b/UPDATING
index 2b6f9cb0d956..fc3abb285039 100644
--- a/UPDATING
+++ b/UPDATING
@@ -27,6 +27,9 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 15.x IS SLOW:
world, or to merely disable the most expensive debugging functionality
at runtime, run "ln -s 'abort:false,junk:false' /etc/malloc.conf".)
 
+20240712:
+   Support for armv6 has been disconnected and is being removed.
+
 20240617:
ifconfig now treats IPv4 addresses without a width or mask as an error.
Specify the desired mask or width along with the IP address on the
diff --git a/sys/sys/param.h b/sys/sys/param.h
index 75370d5998fb..887c595a1de5 100644
--- a/sys/sys/param.h
+++ b/sys/sys/param.h
@@ -73,7 +73,7 @@
  * cannot include sys/param.h and should only be updated here.
  */
 #undef __FreeBSD_version
-#define __FreeBSD_version 1500019
+#define __FreeBSD_version 1500020
 
 /*
  * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,

git: 06999c8a3a3c - main - share/mk: Remove armv6 support

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=06999c8a3a3cbd254b8e52b25549e5f5222dafa6

commit 06999c8a3a3cbd254b8e52b25549e5f5222dafa6
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:28:44 +
Commit: Andrew Turner 
CommitDate: 2024-07-12 11:31:54 +

share/mk: Remove armv6 support

It is being removed from the tree. Remove the build infrastructure to
configure armv6 builds.

Reviewed by:manu, imp, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45643
---
 share/mk/bsd.cpu.mk  | 5 +
 share/mk/bsd.opts.mk | 2 +-
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk
index 793c01b76dca..29eb4662dcdd 100644
--- a/share/mk/bsd.cpu.mk
+++ b/share/mk/bsd.cpu.mk
@@ -315,13 +315,10 @@ MACHINE_CPU = riscv
 ## arm
 .if ${MACHINE_CPUARCH} == "arm"
 MACHINE_CPU += arm
-. if ${MACHINE_ARCH:Marmv6*} != ""
-MACHINE_CPU += armv6
-. endif
 . if ${MACHINE_ARCH:Marmv7*} != ""
 MACHINE_CPU += armv7
 . endif
-# Normally armv6 and armv7 are hard float ABI from FreeBSD 11 onwards. However
+# Normally armv7 is hard float ABI from FreeBSD 11 onwards. However
 # when CPUTYPE has 'soft' in it, we use the soft-float ABI to allow building of
 # soft-float ABI libraries. In this case, we have to add the -mfloat-abi=softfp
 # to force that.
diff --git a/share/mk/bsd.opts.mk b/share/mk/bsd.opts.mk
index 18098c93605c..136215a2db47 100644
--- a/share/mk/bsd.opts.mk
+++ b/share/mk/bsd.opts.mk
@@ -95,7 +95,7 @@ __DEFAULT_DEPENDENT_OPTIONS = \
 # means that ASLR is of limited effectiveness, and it may cause issues with
 # some memory-hungry workloads.
 #
-.if ${MACHINE_ARCH} == "armv6" || ${MACHINE_ARCH} == "armv7" \
+.if ${MACHINE_ARCH} == "armv7" \
 || ${MACHINE_ARCH} == "i386" || ${MACHINE_ARCH} == "powerpc" \
 || ${MACHINE_ARCH} == "powerpcspe"
 __DEFAULT_NO_OPTIONS+= PIE

git: 97dbe3e7ace2 - main - libclang_rt: Simplify the arm check

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=97dbe3e7ace2c222b18f4eb787de91ee44192e76

commit 97dbe3e7ace2c222b18f4eb787de91ee44192e76
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:28:50 +
Commit: Andrew Turner 
CommitDate: 2024-07-12 11:31:54 +

libclang_rt: Simplify the arm check

We just need to check we are building for arm.

Reviewed by:manu, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45644
---
 lib/libclang_rt/compiler-rt-vars.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/libclang_rt/compiler-rt-vars.mk 
b/lib/libclang_rt/compiler-rt-vars.mk
index 5a9f115697d9..c4a33309bc89 100644
--- a/lib/libclang_rt/compiler-rt-vars.mk
+++ b/lib/libclang_rt/compiler-rt-vars.mk
@@ -5,7 +5,7 @@ SANITIZER_SHAREDIR= ${CLANGDIR}/share
 
 # armv[67] is a bit special since we allow a soft-floating version via
 # CPUTYPE matching *soft*. This variant may not actually work though.
-.if ${MACHINE_ARCH:Marmv[67]*} != "" && \
+.if ${MACHINE_CPUARCH} == "arm" && \
 (!defined(CPUTYPE) || ${CPUTYPE:M*soft*} == "")
 CRTARCH?=  armhf
 .else

git: f5c7644378f8 - main - sys/arm: Remove armv6 kernel configs

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=f5c7644378f884dad473011a1f9350fed6fe4e4e

commit f5c7644378f884dad473011a1f9350fed6fe4e4e
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:28:57 +
Commit: Andrew Turner 
CommitDate: 2024-07-12 11:31:54 +

sys/arm: Remove armv6 kernel configs

Only the Raspberry Pi config was supported on armv6. Remove it in
preparation for removing armv6 support from the kernel.

Reviewed by:manu, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45646
---
 sys/arm/conf/RPI-B | 109 -
 sys/arm/conf/std.armv6 |  81 
 2 files changed, 190 deletions(-)

diff --git a/sys/arm/conf/RPI-B b/sys/arm/conf/RPI-B
deleted file mode 100644
index d0a3ee13c367..
--- a/sys/arm/conf/RPI-B
+++ /dev/null
@@ -1,109 +0,0 @@
-#
-# RPI-B -- Custom configuration for the Raspberry Pi
-#
-# For more information on this file, please read the config(5) manual page,
-# and/or the handbook section on Kernel Configuration Files:
-#
-#
https://docs.freebsd.org/en/books/handbook/kernelconfig/#kernelconfig-config
-#
-# The handbook is also available locally in /usr/share/doc/handbook
-# if you've installed the doc distribution, otherwise always see the
-# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
-# latest information.
-#
-# An exhaustive list of options and more detailed explanations of the
-# device lines is also present in the ../../conf/NOTES and NOTES files.
-# If you are in doubt as to the purpose or necessity of a line, check first
-# in NOTES.
-#
-
-ident  RPI-B
-
-include"std.armv6"
-include"../broadcom/bcm2835/std.rpi"
-include"../broadcom/bcm2835/std.bcm2835"
-
-optionsSCHED_4BSD  # 4BSD scheduler
-optionsPLATFORM
-
-# NFS root from boopt/dhcp
-#options   BOOTP
-#options   BOOTP_NFSROOT
-#options   BOOTP_COMPAT
-#options   BOOTP_NFSV3
-#options   BOOTP_WIRED_TO=ue0
-
-#options   ROOTDEVNAME=\"ufs:mmcsd0s2\"
-
-# pseudo devices
-device clk
-device phy
-device hwreset
-device nvmem
-device regulator
-device syscon
-
-device bpf
-device loop
-device ether
-device uart
-device pty
-device snp
-device pl011
-
-# Device mode support
-device usb_template# Control of the gadget
-
-# Comment following lines for boot console on serial port
-device vt
-device kbdmux
-device hkbd
-device ukbd
-
-device sdhci
-device mmc
-device mmcsd
-
-device gpio
-device gpioled
-
-# I2C
-device iic
-device iicbus
-device bcm2835_bsc
-
-device md
-
-# USB support
-device usb
-device dwcotg  # DWC OTG controller
-
-# USB storage support
-device scbus
-device da
-device umass
-
-# USB ethernet support
-device smscphy
-device mii
-device smsc
-
-# SPI
-device spibus
-device bcm2835_spi
-
-device vchiq
-device sound
-
-device fdt_pinctrl
-
-# HID support
-device hid # Generic HID support
-
-# Flattened Device Tree
-optionsFDT # Configure using FDT/DTB data
-# Note:  DTB is normally loaded and modified by RPi boot loader, then
-# handed to kernel via U-Boot and ubldr.
-#options   FDT_DTB_STATIC
-#makeoptions   FDT_DTS_FILE=rpi.dts
-makeoptionsMODULES_EXTRA="dtb/rpi rpi_ft5406"
diff --git a/sys/arm/conf/std.armv6 b/sys/arm/conf/std.armv6
deleted file mode 100644
index a24227fc838f..
--- a/sys/arm/conf/std.armv6
+++ /dev/null
@@ -1,81 +0,0 @@
-# Standard kernel config items for all ARMv6 systems.
-#
-
-optionsHZ=1000
-optionsPREEMPTION  # Enable kernel thread preemption
-optionsVIMAGE  # Subsystem virtualization, e.g. VNET
-optionsINET# InterNETworking
-optionsINET6   # IPv6 communications protocols
-optionsCC_CUBIC# include CUBIC congestion control
-optionsTCP_HHOOK   # hhook(9) framework for TCP
-device crypto  # core crypto support
-optionsIPSEC_SUPPORT   # Allow kldload of ipsec and tcpmd5
-optionsNETLINK # netlink(4) support
-optionsSCTP_SUPPORT# Allow kldload of SCTP
-optionsFFS # Berkeley Fast Filesystem
-optionsSOFTUPDATES # Enable FFS soft updates support
-optionsUFS_ACL # Support for access control lists
-options 

git: 47361851bc2e - main - arm64: Add EL1 and EL12 register alt names

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=47361851bc2e292bd7c723ba5f57792a7794f1b4

commit 47361851bc2e292bd7c723ba5f57792a7794f1b4
Author: Andrew Turner 
AuthorDate: 2024-07-23 09:17:52 +
Commit: Andrew Turner 
CommitDate: 2024-07-23 09:25:05 +

arm64: Add EL1 and EL12 register alt names

When adding VHE support we may need to access these registers using
the _EL12 or _EL1 name depending on if VHE is enabled or not.

Add the registers we will likely need to access from VHE so these can
be updated in the guest switcher code.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45525
---
 sys/arm64/include/armreg.h | 222 +
 1 file changed, 222 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 194731c98902..b2ab472dad0d 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -77,6 +77,54 @@
 
 #defineUL(x)   UINT64_C(x)
 
+/* AFSR0_EL1 - Auxiliary Fault Status Register 0 */
+#defineAFSR0_EL1_REG   MRS_REG_ALT_NAME(AFSR0_EL1)
+#defineAFSR0_EL1_op0   3
+#defineAFSR0_EL1_op1   0
+#defineAFSR0_EL1_CRn   5
+#defineAFSR0_EL1_CRm   1
+#defineAFSR0_EL1_op2   0
+
+/* AFSR0_EL12 */
+#defineAFSR0_EL12_REG  MRS_REG_ALT_NAME(AFSR0_EL12)
+#defineAFSR0_EL12_op0  3
+#defineAFSR0_EL12_op1  5
+#defineAFSR0_EL12_CRn  5
+#defineAFSR0_EL12_CRm  1
+#defineAFSR0_EL12_op2  0
+
+/* AFSR1_EL1 - Auxiliary Fault Status Register 1 */
+#defineAFSR1_EL1_REG   MRS_REG_ALT_NAME(AFSR1_EL1)
+#defineAFSR1_EL1_op0   3
+#defineAFSR1_EL1_op1   0
+#defineAFSR1_EL1_CRn   5
+#defineAFSR1_EL1_CRm   1
+#defineAFSR1_EL1_op2   1
+
+/* AFSR1_EL12 */
+#defineAFSR1_EL12_REG  MRS_REG_ALT_NAME(AFSR1_EL12)
+#defineAFSR1_EL12_op0  3
+#defineAFSR1_EL12_op1  5
+#defineAFSR1_EL12_CRn  5
+#defineAFSR1_EL12_CRm  1
+#defineAFSR1_EL12_op2  1
+
+/* AMAIR_EL1 - Auxiliary Memory Attribute Indirection Register */
+#defineAMAIR_EL1_REG   MRS_REG_ALT_NAME(AMAIR_EL1)
+#defineAMAIR_EL1_op0   3
+#defineAMAIR_EL1_op1   0
+#defineAMAIR_EL1_CRn   10
+#defineAMAIR_EL1_CRm   3
+#defineAMAIR_EL1_op2   0
+
+/* AMAIR_EL12 */
+#defineAMAIR_EL12_REG  MRS_REG_ALT_NAME(AMAIR_EL12)
+#defineAMAIR_EL12_op0  3
+#defineAMAIR_EL12_op1  5
+#defineAMAIR_EL12_CRn  10
+#defineAMAIR_EL12_CRm  3
+#defineAMAIR_EL12_op2  0
+
 /* APDAKeyHi_EL1 */
 #defineAPDAKeyHi_EL1_REG   MRS_REG_ALT_NAME(APDAKeyHi_EL1)
 #defineAPDAKeyHi_EL1_op0   3
@@ -227,7 +275,21 @@
 #defineCONTEXTIDR_EL1_CRm  0
 #defineCONTEXTIDR_EL1_op2  1
 
+/* CONTEXTIDR_EL12 */
+#defineCONTEXTIDR_EL12_REG MRS_REG_ALT_NAME(CONTEXTIDR_EL12)
+#defineCONTEXTIDR_EL12_op0 3
+#defineCONTEXTIDR_EL12_op1 5
+#defineCONTEXTIDR_EL12_CRn 13
+#defineCONTEXTIDR_EL12_CRm 0
+#defineCONTEXTIDR_EL12_op2 1
+
 /* CPACR_EL1 */
+#defineCPACR_EL1_REG   MRS_REG_ALT_NAME(CPACR_EL1)
+#defineCPACR_EL1_op0   3
+#defineCPACR_EL1_op1   0
+#defineCPACR_EL1_CRn   1
+#defineCPACR_EL1_CRm   0
+#defineCPACR_EL1_op2   2
 #defineCPACR_ZEN_MASK  (0x3 << 16)
 #define CPACR_ZEN_TRAP_ALL1(0x0 << 16) /* Traps from EL0 and EL1 */
 #define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */
@@ -240,6 +302,14 @@
 #define CPACR_FPEN_TRAP_NONE   (0x3 << 20) /* No traps */
 #defineCPACR_TTA   (0x1 << 28)
 
+/* CPACR_EL12 */
+#defineCPACR_EL12_REG  MRS_REG_ALT_NAME(CPACR_EL12)
+#defineCPACR_EL12_op0  3
+#defineCPACR_EL12_op1  5
+#defineCPACR_EL12_CRn  1
+#defineCPACR_EL12_CRm  0
+#defineCPACR_EL12_op2  2
+
 /* CSSELR_EL1 - Cache size selection register */
 #defineCSSELR_Level(i) (i << 1)
 #defineCSSELR_InD  0x0001
@@ -396,6 +466,22 @@
 #defineDBGPRC

git: 997511dffe65 - main - arm64: Support counter access with E2H

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=997511dffe651e1d2d708f37f2ced430a6ab3349

commit 997511dffe651e1d2d708f37f2ced430a6ab3349
Author: Andrew Turner 
AuthorDate: 2024-07-23 09:18:00 +
Commit: Andrew Turner 
CommitDate: 2024-07-23 09:25:05 +

arm64: Support counter access with E2H

When entering the kernel with the E2H field set the layout of the
cnthctl_el2 register changes. Use the correct field locations to enable
access to the counter and timer registers from EL1.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45529
---
 sys/arm64/arm64/locore.S   | 6 --
 sys/arm64/include/hypervisor.h | 9 +++--
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index d1120e0476a2..2680669c61f8 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -365,8 +365,10 @@ LENTRY(enter_kernel_el)
msr hstr_el2, xzr
 
/* Enable access to the physical timers at EL1 */
-   mrs x2, cnthctl_el2
-   orr x2, x2, #(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
+   tst x4, #HCR_E2H
+   ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
+   ldr x5, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
+   cselx2, x3, x5, eq
msr cnthctl_el2, x2
 
/* Set the counter offset to a known value */
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 85ac5cda7037..418047cb22f2 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -37,10 +37,15 @@
 
 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
 #defineCNTHCTL_EVNTI_MASK  (0xf << 4) /* Bit to trigger event 
stream */
+/* Valid if HCR_EL2.E2H == 0 */
+#defineCNTHCTL_EL1PCTEN(1 << 0) /* Allow physical counter 
access */
+#defineCNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access 
*/
+/* Valid if HCR_EL2.E2H == 1 */
+#defineCNTHCTL_E2H_EL1PCTEN(1 << 10) /* Allow physical counter 
access */
+#defineCNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer 
access */
+/* Unconditionally valid */
 #defineCNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger 
bit */
 #defineCNTHCTL_EVNTEN  (1 << 2) /* Enable event stream */
-#defineCNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer 
access */
-#defineCNTHCTL_EL1PCTEN(1 << 0) /*Allow EL0/1 physical counter 
access*/
 
 /* CPTR_EL2 - Architecture feature trap register */
 /* Valid if HCR_EL2.E2H == 0 */

git: 57ef7935eb11 - main - arm64: Fix the gicv3 check in locore.S

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=57ef7935eb114e98e7e554c5ffbded68fd038c04

commit 57ef7935eb114e98e7e554c5ffbded68fd038c04
Author: Andrew Turner 
AuthorDate: 2024-07-23 09:18:08 +
Commit: Andrew Turner 
CommitDate: 2024-07-23 09:25:05 +

arm64: Fix the gicv3 check in locore.S

In locore.S we need to configure access to the GICv3. To check if it's
available we read the id_aa64pfr0_el1 register, however we then only
check if a GICv3.0 or 4.0 is present. If the system has a GICv4.1 this
check would fail.

Move to checking if the GICV3+ is not absent so this will still work if
the field is updated again.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45530
---
 sys/arm64/arm64/locore.S | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 2680669c61f8..3dcb01fd2a6e 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -389,9 +389,8 @@ LENTRY(enter_kernel_el)
mrs x2, id_aa64pfr0_el1
/* Extract GIC bits from the register */
ubfxx2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
-   /* GIC[3:0] == 0001 - GIC CPU interface via special regs. supported */
-   cmp x2, #(ID_AA64PFR0_GIC_CPUIF_EN >> ID_AA64PFR0_GIC_SHIFT)
-   b.ne2f
+   /* GIC[3:0] !=  - GIC CPU interface via special regs. supported */
+   cbz x2, 2f
 
mrs x2, icc_sre_el2
orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */

git: 034c83fd7d85 - main - arm64: Ensure sctlr and pstate are in known states

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=034c83fd7d85f57193850a73cc0ac957a211f725

commit 034c83fd7d85f57193850a73cc0ac957a211f725
Author: Andrew Turner 
AuthorDate: 2024-07-23 09:18:24 +
Commit: Andrew Turner 
CommitDate: 2024-07-23 09:25:05 +

arm64: Ensure sctlr and pstate are in known states

Before entering the kernel exception level ensure sctlr_el2 and
sctlr_el1 are in a known state. The EOS flag needs to be set to ensure
an eret instruction is a context synchronization event.

Set spcr_el1 when entering the kernel from EL1 and use an eret
instruction to return to the caller. This ensures the CPU pstate is
consistent with the value in spcr_el1 as it is the only way to set it
directly.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45528
---
 sys/arm64/arm64/locore.S   | 52 ++
 sys/arm64/include/hypervisor.h |  4 
 2 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 3dcb01fd2a6e..4252ea3f59f8 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -67,19 +67,6 @@ ENTRY(_start)
/* Enter the kernel exception level */
bl  enter_kernel_el
 
-   /*
-* Disable the MMU. We may have entered the kernel with it on and
-* will need to update the tables later. If this has been set up
-* with anything other than a VA == PA map then this will fail,
-* but in this case the code to find where we are running from
-* would have also failed.
-*/
-   dsb sy
-   mrs x2, sctlr_el1
-   bic x2, x2, SCTLR_M
-   msr sctlr_el1, x2
-   isb
-
/* Set the context id */
msr contextidr_el1, xzr
 
@@ -314,19 +301,37 @@ LEND(mpentry_common)
  * registers and drop to EL1.
  */
 LENTRY(enter_kernel_el)
+#defineINIT_SCTLR_EL1  (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \
+SCTLR_TSCXT | SCTLR_EOS)
mrs x23, CurrentEL
and x23, x23, #(CURRENTEL_EL_MASK)
cmp x23, #(CURRENTEL_EL_EL2)
b.eq1f
-   ret
+
+   ldr x2, =INIT_SCTLR_EL1
+   msr sctlr_el1, x2
+   /* SCTLR_EOS is set so eret is a context synchronizing event so we
+* need an isb here to ensure it's observed by later instructions,
+* but don't need it in the eret below.
+*/
+   isb
+
+   /* Ensure SPSR_EL1 and pstate are in sync. The only wat to set the
+* latter is to set the former and return from an exception with eret.
+*/
+   mov x2, #(PSR_DAIF | PSR_M_EL1h)
+   msr spsr_el1, x2
+   msr elr_el1, lr
+   eret
+
 1:
+   dsb sy
/*
-* Disable the MMU. If the HCR_EL2.E2H field is set we will clear it
-* which may break address translation.
+* Set just the reserved bits in sctlr_el2. This will disable the
+* MMU which may have broken the kernel if we enter the kernel in
+* EL2, e.g. when using VHE.
 */
-   dsb sy
-   mrs x2, sctlr_el2
-   bic x2, x2, SCTLR_M
+   ldr x2, =(SCTLR_EL2_RES1 | SCTLR_EL2_EIS | SCTLR_EL2_EOS)
msr sctlr_el2, x2
isb
 
@@ -346,8 +351,8 @@ LENTRY(enter_kernel_el)
mrs x2, mpidr_el1
msr vmpidr_el2, x2
 
-   /* Set the bits that need to be 1 in sctlr_el1 */
-   ldr x2, .Lsctlr_res1
+   /* Set the initial sctlr_el1 */
+   ldr x2, =INIT_SCTLR_EL1
msr sctlr_el1, x2
 
/*
@@ -403,10 +408,7 @@ LENTRY(enter_kernel_el)
isb
 
eret
-
-   .align 3
-.Lsctlr_res1:
-   .quad SCTLR_RES1
+#undef INIT_SCTLR_EL1
 LEND(enter_kernel_el)
 
 /*
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 418047cb22f2..011f86e83fdf 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -148,10 +148,14 @@
 #defineSCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT)
 #defineSCTLR_EL2_SA_SHIFT  3
 #defineSCTLR_EL2_SA(0x1UL << SCTLR_EL2_SA_SHIFT)
+#defineSCTLR_EL2_EOS_SHIFT 11
+#defineSCTLR_EL2_EOS   (0x1UL << SCTLR_EL2_EOS_SHIFT)
 #defineSCTLR_EL2_I_SHIFT   12
 #defineSCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT)
 #defineSCTLR_EL2_WXN_SHIFT 19
 #defineSCTLR_EL2_WXN   (0x1UL << SCTLR_EL2_WXN_SHIFT)
+#defineSCTLR_EL2_EIS_SHIFT 22
+#defineSCTLR_EL2_EIS   (0x1UL << SCTLR_EL2_EIS_SHIFT)
 #defineSCTLR_EL2_EE_SHIFT  25
 #defineSCTLR_EL2_EE(0x1UL << SCTLR_EL2_EE_SHIFT)
 

git: 9840598aa31f - main - dev/uart: Add APMC0D08 as found in the Intel E2100

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=9840598aa31f2a89272f5bef6545e316f254f0c6

commit 9840598aa31f2a89272f5bef6545e316f254f0c6
Author: Andrew Turner 
AuthorDate: 2024-07-23 09:18:36 +
Commit: Andrew Turner 
CommitDate: 2024-07-23 09:25:05 +

dev/uart: Add APMC0D08 as found in the Intel E2100

This uart has the requirement for 32-bit sized and aligned memory
accesses. It is also described in the Serial Port Console Redirection
Table (SPCR) with a different interface type value.

Reviewed by:imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45834
---
 sys/dev/uart/uart_dev_ns8250.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c
index 16c3cb2fc5a9..1a58600c8039 100644
--- a/sys/dev/uart/uart_dev_ns8250.c
+++ b/sys/dev/uart/uart_dev_ns8250.c
@@ -460,6 +460,7 @@ UART_CLASS(uart_ns8250_class);
 static struct acpi_uart_compat_data acpi_compat_data[] = {
{"AMD0020", &uart_ns8250_class, 0, 2, 0, 4800, 
UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"},
{"AMDI0020", &uart_ns8250_class, 0, 2, 0, 4800, UART_F_BUSY_DETECT, 
"AMD / Synopsys Designware UART"},
+   {"APMC0D08", &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE, 2, 4, 0, 
0, "APM compatible UART"},
{"MRVL0001", &uart_ns8250_class, ACPI_DBG2_16550_SUBSET, 2, 0, 
2, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"},
{"SCX0006",  &uart_ns8250_class, 0, 2, 0, 6250, UART_F_BUSY_DETECT, 
"SynQuacer / Synopsys Designware UART"},
{"HISI0031", &uart_ns8250_class, 0, 2, 0, 2, 
UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"},

git: 5048308bdb76 - main - buf_ring: Remove PREFETCH_DEFINED

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=5048308bdb76f40e88c9133658fc61d82158ded2

commit 5048308bdb76f40e88c9133658fc61d82158ded2
Author: Andrew Turner 
AuthorDate: 2024-07-29 10:28:15 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 09:04:24 +

buf_ring: Remove PREFETCH_DEFINED

I'm not able to find anything in the tree that ever defined it. Remove
as it's unused so is untested.

Reviewed by:alc, imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46148
---
 sys/sys/buf_ring.h | 13 -
 1 file changed, 13 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index cb18175c3a75..6bd3b91dcd04 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -165,9 +165,6 @@ static __inline void *
 buf_ring_dequeue_sc(struct buf_ring *br)
 {
uint32_t cons_head, cons_next;
-#ifdef PREFETCH_DEFINED
-   uint32_t cons_next_next;
-#endif
uint32_t prod_tail;
void *buf;
 
@@ -204,20 +201,10 @@ buf_ring_dequeue_sc(struct buf_ring *br)
prod_tail = atomic_load_acq_32(&br->br_prod_tail);
 
cons_next = (cons_head + 1) & br->br_cons_mask;
-#ifdef PREFETCH_DEFINED
-   cons_next_next = (cons_head + 2) & br->br_cons_mask;
-#endif
 
if (cons_head == prod_tail) 
return (NULL);
 
-#ifdef PREFETCH_DEFINED
-   if (cons_next != prod_tail) {   
-   prefetch(br->br_ring[cons_next]);
-   if (cons_next_next != prod_tail) 
-   prefetch(br->br_ring[cons_next_next]);
-   }
-#endif
br->br_cons_head = cons_next;
buf = br->br_ring[cons_head];
 

git: 17a597bc13aa - main - buf_ring: Consistently use atomic_*_32

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=17a597bc13aa59ee90facaf9b8dada80f32eb52d

commit 17a597bc13aa59ee90facaf9b8dada80f32eb52d
Author: Andrew Turner 
AuthorDate: 2024-07-29 10:28:33 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 09:04:25 +

buf_ring: Consistently use atomic_*_32

We are operating on uint32_t values, use uint32_t atomic functions.

Reviewed by:alc, imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46150
---
 sys/sys/buf_ring.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 2d61f393712d..47ed04f570c1 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -94,7 +94,7 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
}
continue;
}
-   } while (!atomic_cmpset_acq_int(&br->br_prod_head, prod_head, 
prod_next));
+   } while (!atomic_cmpset_acq_32(&br->br_prod_head, prod_head, 
prod_next));
 #ifdef DEBUG_BUFRING
if (br->br_ring[prod_head] != NULL)
panic("dangling value in enqueue");
@@ -108,7 +108,7 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
 */   
while (br->br_prod_tail != prod_head)
cpu_spinwait();
-   atomic_store_rel_int(&br->br_prod_tail, prod_next);
+   atomic_store_rel_32(&br->br_prod_tail, prod_next);
critical_exit();
return (0);
 }
@@ -132,7 +132,7 @@ buf_ring_dequeue_mc(struct buf_ring *br)
critical_exit();
return (NULL);
}
-   } while (!atomic_cmpset_acq_int(&br->br_cons_head, cons_head, 
cons_next));
+   } while (!atomic_cmpset_acq_32(&br->br_cons_head, cons_head, 
cons_next));
 
buf = br->br_ring[cons_head];
 #ifdef DEBUG_BUFRING
@@ -146,7 +146,7 @@ buf_ring_dequeue_mc(struct buf_ring *br)
while (br->br_cons_tail != cons_head)
cpu_spinwait();
 
-   atomic_store_rel_int(&br->br_cons_tail, cons_next);
+   atomic_store_rel_32(&br->br_cons_tail, cons_next);
critical_exit();
 
return (buf);

git: 3cc603909e09 - main - buf_ring: Keep the full head and tail values

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=3cc603909e09c958e20dd5a8a341f62f29e33a07

commit 3cc603909e09c958e20dd5a8a341f62f29e33a07
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:06:44 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:11 +

buf_ring: Keep the full head and tail values

If a thread reads the head but then sleeps for long enough that
another thread fills the ring and leaves the new head with the
expected value then the cmpset can pass when it should have failed.

To work around this keep the full head and tail value and use the
upper bits as a generation count.

Reviewed by:kib
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46151
---
 sys/sys/buf_ring.h | 87 +++---
 1 file changed, 56 insertions(+), 31 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 47ed04f570c1..dec0f971ae44 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -40,6 +40,15 @@
 #include 
 #endif
 
+/*
+ * We only apply the mask to the head and tail values when calculating the
+ * index into br_ring to access. This means the upper bits can be used as
+ * epoch to reduce the chance the atomic_cmpset succeedes when it should
+ * fail, e.g. when the head wraps while the CPU is in an interrupt. This
+ * is a probablistic fix as there is still a very unlikely chance the
+ * value wraps back to the expected value.
+ *
+ */
 struct buf_ring {
volatile uint32_t   br_prod_head;
volatile uint32_t   br_prod_tail;   
@@ -63,28 +72,28 @@ struct buf_ring {
 static __inline int
 buf_ring_enqueue(struct buf_ring *br, void *buf)
 {
-   uint32_t prod_head, prod_next, cons_tail;
-#ifdef DEBUG_BUFRING
-   int i;
+   uint32_t prod_head, prod_next, prod_idx;
+   uint32_t cons_tail, mask;
 
+   mask = br->br_prod_mask;
+#ifdef DEBUG_BUFRING
/*
 * Note: It is possible to encounter an mbuf that was removed
 * via drbr_peek(), and then re-added via drbr_putback() and
 * trigger a spurious panic.
 */
-   for (i = br->br_cons_head; i != br->br_prod_head;
-i = ((i + 1) & br->br_cons_mask))
-   if (br->br_ring[i] == buf)
+   for (uint32_t i = br->br_cons_head; i != br->br_prod_head; i++)
+   if (br->br_ring[i & mask] == buf)
panic("buf=%p already enqueue at %d prod=%d cons=%d",
buf, i, br->br_prod_tail, br->br_cons_tail);
 #endif 
critical_enter();
do {
prod_head = br->br_prod_head;
-   prod_next = (prod_head + 1) & br->br_prod_mask;
+   prod_next = prod_head + 1;
cons_tail = br->br_cons_tail;
 
-   if (prod_next == cons_tail) {
+   if ((int32_t)(cons_tail + br->br_prod_size - prod_next) < 1) {
rmb();
if (prod_head == br->br_prod_head &&
cons_tail == br->br_cons_tail) {
@@ -95,11 +104,12 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
continue;
}
} while (!atomic_cmpset_acq_32(&br->br_prod_head, prod_head, 
prod_next));
+   prod_idx = prod_head & mask;
 #ifdef DEBUG_BUFRING
-   if (br->br_ring[prod_head] != NULL)
+   if (br->br_ring[prod_idx] != NULL)
panic("dangling value in enqueue");
 #endif 
-   br->br_ring[prod_head] = buf;
+   br->br_ring[prod_idx] = buf;
 
/*
 * If there are other enqueues in progress
@@ -120,23 +130,26 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
 static __inline void *
 buf_ring_dequeue_mc(struct buf_ring *br)
 {
-   uint32_t cons_head, cons_next;
+   uint32_t cons_head, cons_next, cons_idx;
+   uint32_t mask;
void *buf;
 
critical_enter();
+   mask = br->br_cons_mask;
do {
cons_head = br->br_cons_head;
-   cons_next = (cons_head + 1) & br->br_cons_mask;
+   cons_next = cons_head + 1;
 
if (cons_head == br->br_prod_tail) {
critical_exit();
return (NULL);
}
} while (!atomic_cmpset_acq_32(&br->br_cons_head, cons_head, 
cons_next));
+   cons_idx = cons_head & mask;
 
-   buf = br->br_ring[cons_head];
+   buf = br->br_ring[cons_idx];
 #ifdef DEBUG_BUFRING
-   br->br_ring[cons_head] = NULL;
+   br->br_ring[cons_idx] = NULL;
 #endif
/*
 * If there are other dequeues in progress
@@ -160,8 +173,8 @@ buf_ring_dequeue_mc(struct buf_ring *br)
 static __inline void *
 buf_ring_dequeue_sc(struct buf_ring *br

git: d3d34d56bee4 - main - buf_ring: Support DEBUG_BUFRING in userspace

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d3d34d56bee4222b3bf3ec26d7877998405115a3

commit d3d34d56bee4222b3bf3ec26d7877998405115a3
Author: Andrew Turner 
AuthorDate: 2024-07-29 10:28:24 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 09:04:25 +

buf_ring: Support DEBUG_BUFRING in userspace

The only part of DEBUG_BUFRING we don't support in userspace is the
mutex checks. Add _KERNEL checks around these so we can enable the
extra debugging.

Reviewed by:alc, imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46149
---
 sys/sys/buf_ring.h | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 6bd3b91dcd04..2d61f393712d 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -35,13 +35,9 @@
 #include 
 #include 
 
-#ifdef DEBUG_BUFRING
-#ifdef _KERNEL
+#if defined(DEBUG_BUFRING) && defined(_KERNEL)
 #include 
 #include 
-#else
-#error "DEBUG_BUFRING is only supported in kernel"
-#endif
 #endif
 
 struct buf_ring {
@@ -54,7 +50,7 @@ struct buf_ring {
volatile uint32_t   br_cons_tail;
int br_cons_size;
int br_cons_mask;
-#ifdef DEBUG_BUFRING
+#if defined(DEBUG_BUFRING) && defined(_KERNEL)
struct mtx  *br_lock;
 #endif 
void*br_ring[0] __aligned(CACHE_LINE_SIZE);
@@ -210,8 +206,10 @@ buf_ring_dequeue_sc(struct buf_ring *br)
 
 #ifdef DEBUG_BUFRING
br->br_ring[cons_head] = NULL;
+#ifdef _KERNEL
if (!mtx_owned(br->br_lock))
panic("lock not held on single consumer dequeue");
+#endif
if (br->br_cons_tail != cons_head)
panic("inconsistent list cons_tail=%d cons_head=%d",
br->br_cons_tail, cons_head);
@@ -277,7 +275,7 @@ static __inline void *
 buf_ring_peek(struct buf_ring *br)
 {
 
-#ifdef DEBUG_BUFRING
+#if defined(DEBUG_BUFRING) && defined(_KERNEL)
if ((br->br_lock != NULL) && !mtx_owned(br->br_lock))
panic("lock not held on single consumer dequeue");
 #endif 
@@ -296,9 +294,9 @@ buf_ring_peek(struct buf_ring *br)
 static __inline void *
 buf_ring_peek_clear_sc(struct buf_ring *br)
 {
-#ifdef DEBUG_BUFRING
void *ret;
 
+#if defined(DEBUG_BUFRING) && defined(_KERNEL)
if (!mtx_owned(br->br_lock))
panic("lock not held on single consumer dequeue");
 #endif 
@@ -320,17 +318,15 @@ buf_ring_peek_clear_sc(struct buf_ring *br)
atomic_thread_fence_acq();
 #endif
 
+   ret = br->br_ring[br->br_cons_head];
 #ifdef DEBUG_BUFRING
/*
 * Single consumer, i.e. cons_head will not move while we are
 * running, so atomic_swap_ptr() is not necessary here.
 */
-   ret = br->br_ring[br->br_cons_head];
br->br_ring[br->br_cons_head] = NULL;
-   return (ret);
-#else
-   return (br->br_ring[br->br_cons_head]);
 #endif
+   return (ret);
 }
 
 static __inline int

git: 44e1cfca417c - main - buf_ring: Use atomic operations with br_cons_tail

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=44e1cfca417c5ef0db908f3836ec3ba704ef1de2

commit 44e1cfca417c5ef0db908f3836ec3ba704ef1de2
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:06:52 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:11 +

buf_ring: Use atomic operations with br_cons_tail

Use an atomic operation with a memory barrier loading br_cons_tail
from the producer thread and storing to it in the consumer thread.

On dequeue we need to read the pointer value from the buf_ring before
moving the consumer tail as that indicates the entry is available to be
used. The store release atomic operation guarantees this.

In the enqueueing thread we then need to use a load acquire atomic
operation to ensure writing to this entry can only happen after the
tail has been read and checked.

Reported by:Ali Saidi 
Co-developed by: Ali Saidi 
Reviewed by:markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46152
---
 sys/sys/buf_ring.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index dec0f971ae44..9aeb5aa19fa8 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -91,7 +91,7 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
do {
prod_head = br->br_prod_head;
prod_next = prod_head + 1;
-   cons_tail = br->br_cons_tail;
+   cons_tail = atomic_load_acq_32(&br->br_cons_tail);
 
if ((int32_t)(cons_tail + br->br_prod_size - prod_next) < 1) {
rmb();
@@ -229,7 +229,7 @@ buf_ring_dequeue_sc(struct buf_ring *br)
panic("inconsistent list cons_tail=%d cons_head=%d",
br->br_cons_tail, cons_head);
 #endif
-   br->br_cons_tail = cons_next;
+   atomic_store_rel_32(&br->br_cons_tail, cons_next);
return (buf);
 }
 
@@ -257,7 +257,7 @@ buf_ring_advance_sc(struct buf_ring *br)
 #ifdef DEBUG_BUFRING
br->br_ring[cons_head & mask] = NULL;
 #endif
-   br->br_cons_tail = cons_next;
+   atomic_store_rel_32(&br->br_cons_tail, cons_next);
 }
 
 /*

git: 7eb0fffc7792 - main - buf_ring: Remove old arm-only dequeue code

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7eb0fffc7792bc294d6b86546a3923e2e2f83f8a

commit 7eb0fffc7792bc294d6b86546a3923e2e2f83f8a
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:07:10 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:11 +

buf_ring: Remove old arm-only dequeue code

In the single consumer dequeue the consumer thread controls
br_cons_head. As such no ordering between this and other data are
required.

Reviewed by:alc, imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46153
---
 sys/sys/buf_ring.h | 29 -
 1 file changed, 29 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 9aeb5aa19fa8..ad463fba27cb 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -177,37 +177,8 @@ buf_ring_dequeue_sc(struct buf_ring *br)
uint32_t prod_tail, mask;
void *buf;
 
-   /*
-* This is a workaround to allow using buf_ring on ARM and ARM64.
-* ARM64TODO: Fix buf_ring in a generic way.
-* REMARKS: It is suspected that br_cons_head does not require
-*   load_acq operation, but this change was extensively tested
-*   and confirmed it's working. To be reviewed once again in
-*   FreeBSD-12.
-*
-* Preventing following situation:
-
-* Core(0) - buf_ring_enqueue()   
Core(1) - buf_ring_dequeue_sc()
-* -
   --
-*
-*  
  cons_head = br->br_cons_head;
-* atomic_cmpset_acq_32(&br->br_prod_head, ...));
-*  
  buf = br->br_ring[cons_head]; >
-* br->br_ring[prod_head] = buf;
-* atomic_store_rel_32(&br->br_prod_tail, ...);
-*  
  prod_tail = br->br_prod_tail;
-*  
  if (cons_head == prod_tail) 
-*  
  return (NULL);
-*  
  `  
-*
-* <1> Load (on core 1) from br->br_ring[cons_head] can be reordered 
(speculative readed) by CPU.
-*/ 
mask = br->br_cons_mask;
-#if defined(__arm__) || defined(__aarch64__)
-   cons_head = atomic_load_acq_32(&br->br_cons_head);
-#else
cons_head = br->br_cons_head;
-#endif
prod_tail = atomic_load_acq_32(&br->br_prod_tail);
 
cons_next = cons_head + 1;

git: 947754af55ed - main - buf_ring: Use atomic operations with br_prod_tail

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=947754af55edc217c10e3456d97558c4eb6d0f99

commit 947754af55edc217c10e3456d97558c4eb6d0f99
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:07:19 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:11 +

buf_ring: Use atomic operations with br_prod_tail

As with br_cons_tail use an atomic load acquire to read br_prod_tail
in buf_ring_dequeue_mc and buf_ring_peek*.

On dequeue we need to ensure we don't read the entry from the buf_ring
until it is available and prod_tail has updated. There is already an
appropriate store in the enqueue path and an appropriate load in the
single consumer dequeue, we just need one in the other functions that
read from the buf_ring.

Reviewed by:imp, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46154
---
 sys/sys/buf_ring.h | 45 -
 1 file changed, 16 insertions(+), 29 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index ad463fba27cb..66e1e55bc5e9 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -131,7 +131,7 @@ static __inline void *
 buf_ring_dequeue_mc(struct buf_ring *br)
 {
uint32_t cons_head, cons_next, cons_idx;
-   uint32_t mask;
+   uint32_t prod_tail, mask;
void *buf;
 
critical_enter();
@@ -139,8 +139,9 @@ buf_ring_dequeue_mc(struct buf_ring *br)
do {
cons_head = br->br_cons_head;
cons_next = cons_head + 1;
+   prod_tail = atomic_load_acq_32(&br->br_prod_tail);
 
-   if (cons_head == br->br_prod_tail) {
+   if (cons_head == prod_tail) {
critical_exit();
return (NULL);
}
@@ -266,29 +267,26 @@ buf_ring_putback_sc(struct buf_ring *br, void *new)
 static __inline void *
 buf_ring_peek(struct buf_ring *br)
 {
-   uint32_t mask;
+   uint32_t cons_head, prod_tail, mask;
 
 #if defined(DEBUG_BUFRING) && defined(_KERNEL)
if ((br->br_lock != NULL) && !mtx_owned(br->br_lock))
panic("lock not held on single consumer dequeue");
 #endif 
mask = br->br_cons_mask;
-   /*
-* I believe it is safe to not have a memory barrier
-* here because we control cons and tail is worst case
-* a lagging indicator so we worst case we might
-* return NULL immediately after a buffer has been enqueued
-*/
-   if (br->br_cons_head == br->br_prod_tail)
+   prod_tail = atomic_load_acq_32(&br->br_prod_tail);
+   cons_head = br->br_cons_head;
+
+   if (cons_head == prod_tail)
return (NULL);
 
-   return (br->br_ring[br->br_cons_head & mask]);
+   return (br->br_ring[cons_head & mask]);
 }
 
 static __inline void *
 buf_ring_peek_clear_sc(struct buf_ring *br)
 {
-   uint32_t mask;
+   uint32_t cons_head, prod_tail, mask;
void *ret;
 
 #if defined(DEBUG_BUFRING) && defined(_KERNEL)
@@ -297,30 +295,19 @@ buf_ring_peek_clear_sc(struct buf_ring *br)
 #endif 
 
mask = br->br_cons_mask;
-   if (br->br_cons_head == br->br_prod_tail)
-   return (NULL);
+   prod_tail = atomic_load_acq_32(&br->br_prod_tail);
+   cons_head = br->br_cons_head;
 
-#if defined(__arm__) || defined(__aarch64__)
-   /*
-* The barrier is required there on ARM and ARM64 to ensure, that
-* br->br_ring[br->br_cons_head] will not be fetched before the above
-* condition is checked.
-* Without the barrier, it is possible, that buffer will be fetched
-* before the enqueue will put mbuf into br, then, in the meantime, the
-* enqueue will update the array and the br_prod_tail, and the
-* conditional check will be true, so we will return previously fetched
-* (and invalid) buffer.
-*/
-   atomic_thread_fence_acq();
-#endif
+   if (cons_head == prod_tail)
+   return (NULL);
 
-   ret = br->br_ring[br->br_cons_head & mask];
+   ret = br->br_ring[cons_head & mask];
 #ifdef DEBUG_BUFRING
/*
 * Single consumer, i.e. cons_head will not move while we are
 * running, so atomic_swap_ptr() is not necessary here.
 */
-   br->br_ring[br->br_cons_head & mask] = NULL;
+   br->br_ring[cons_head & mask] = NULL;
 #endif
return (ret);
 }

git: fe2445f47d02 - main - buf_ring: Ensure correct ordering of loads

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=fe2445f47d027c73aa729e7d94b70d3949a4

commit fe2445f47d027c73aa729e7d94b70d3949a4
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:07:26 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:11 +

buf_ring: Ensure correct ordering of loads

When enqueueing on an architecture with a weak memory model ensure
loading br->br_prod_head and br->br_cons_tail are ordered correctly.

If br_cons_tail is loaded first then other threads may perform a
dequeue and enqueue before br_prod_head is loaded. This will mean the
tail is one less than it should be and the code under the
prod_next == cons_tail check could incorrectly be skipped.

buf_ring_dequeue_mc has the same issue with br->br_prod_tail and
br->br_cons_head so needs the same fix.

Reported by:Ali Saidi 
Co-developed by: Ali Saidi 
Reviewed by:imp, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46155
---
 sys/sys/buf_ring.h | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 66e1e55bc5e9..512f20dc13e2 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -89,7 +89,17 @@ buf_ring_enqueue(struct buf_ring *br, void *buf)
 #endif 
critical_enter();
do {
-   prod_head = br->br_prod_head;
+   /*
+* br->br_prod_head needs to be read before br->br_cons_tail.
+* If not then we could perform the dequeue and enqueue
+* between reading br_cons_tail and reading br_prod_head. This
+* could give us values where br_cons_head == br_prod_tail
+* (after masking).
+*
+* To work around this us a load acquire. This is just to
+* ensure ordering within this thread.
+*/
+   prod_head = atomic_load_acq_32(&br->br_prod_head);
prod_next = prod_head + 1;
cons_tail = atomic_load_acq_32(&br->br_cons_tail);
 
@@ -137,7 +147,12 @@ buf_ring_dequeue_mc(struct buf_ring *br)
critical_enter();
mask = br->br_cons_mask;
do {
-   cons_head = br->br_cons_head;
+   /*
+* As with buf_ring_enqueue ensure we read the head before
+* the tail. If we read them in the wrong order we may
+* think the bug_ring is full when it is empty.
+*/
+   cons_head = atomic_load_acq_32(&br->br_cons_head);
cons_next = cons_head + 1;
prod_tail = atomic_load_acq_32(&br->br_prod_tail);
 

git: 87940d2b331c - main - buf_ring: Add an Arm copyright

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=87940d2b331c2575f96fbff2600d8da35191157b

commit 87940d2b331c2575f96fbff2600d8da35191157b
Author: Andrew Turner 
AuthorDate: 2024-08-19 09:08:20 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:12 +

buf_ring: Add an Arm copyright

I've change enough of this file to add Arm as a copyright holder.
Add it after the "All rights reserved" line as that's not needed.

Reviewed by:imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46157
---
 sys/sys/buf_ring.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/sys/buf_ring.h b/sys/sys/buf_ring.h
index 512f20dc13e2..c99cf81d8b6d 100644
--- a/sys/sys/buf_ring.h
+++ b/sys/sys/buf_ring.h
@@ -3,6 +3,7 @@
  *
  * Copyright (c) 2007-2009 Kip Macy 
  * All rights reserved.
+ * Copyright (c) 2024 Arm Ltd
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions

git: 7a345763f96d - main - arm64: Expand the use of Armv8.1-A atomics

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7a345763f96d86eee9ab578e64311bf452e58900

commit 7a345763f96d86eee9ab578e64311bf452e58900
Author: Andrew Turner 
AuthorDate: 2024-07-30 09:26:21 +
Commit: Andrew Turner 
CommitDate: 2024-08-19 10:53:12 +

arm64: Expand the use of Armv8.1-A atomics

When targeting Armv8.1 we can assume FEAT_LSE is available and can use
the atomic instructions this provides without needing to check for
support first.

Reviewed by:imp, markj, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46159
---
 sys/arm64/include/atomic.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/include/atomic.h b/sys/arm64/include/atomic.h
index 76ca951678d4..c7aaa76d9de9 100644
--- a/sys/arm64/include/atomic.h
+++ b/sys/arm64/include/atomic.h
@@ -65,8 +65,9 @@ extern _Bool lse_supported;
 
 #include 
 
-#ifdef _KERNEL
-
+#if defined(__ARM_FEATURE_ATOMICS)
+#define_ATOMIC_LSE_SUPPORTED   1
+#elif defined(_KERNEL)
 #ifdef LSE_ATOMICS
 #define_ATOMIC_LSE_SUPPORTED   1
 #else

git: 12a6257a9600 - main - sys/conf: Introduce NOSAN_CFLAGS and NOSAN_C

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=12a6257a96007222e5441d883709fca2a28febb5

commit 12a6257a96007222e5441d883709fca2a28febb5
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:53:27 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

sys/conf: Introduce NOSAN_CFLAGS and NOSAN_C

To simplify disabling the kernel sanitizers in some files add
NOSAN_CFLAGS and NOSAN_C variables. These are CFLAGS and NORMAL_C with
the sanitizer flags removed.

While here add MSAN_CFLAGS to simplify keeping KMSAN in kern_kcov.c

Reviewed by:khng, brooks, imp, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45498
---
 sys/conf/files   | 10 +-
 sys/conf/files.arm64 |  6 +++---
 sys/conf/kern.mk |  2 ++
 sys/conf/kern.post.mk|  6 +++---
 sys/conf/kern.pre.mk |  9 +++--
 sys/conf/kmod.mk |  4 ++--
 sys/modules/linux64/Makefile |  3 +--
 sys/modules/vmm/Makefile | 15 ++-
 8 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/sys/conf/files b/sys/conf/files
index df4c702540ae..6445f00e2801 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -3811,7 +3811,7 @@ kern/kern_idle.c  standard
 kern/kern_intr.c   standard
 kern/kern_jail.c   standard
 kern/kern_kcov.c   optional kcov   \
-   compile-with "${NORMAL_C:N-fsanitize*} 
${NORMAL_C:M-fsanitize=kernel-memory}"
+   compile-with "${NOSAN_C} ${MSAN_CFLAGS}"
 kern/kern_khelp.c  standard
 kern/kern_kthread.cstandard
 kern/kern_ktr.coptional ktr
@@ -3879,7 +3879,7 @@ kern/stack_protector.cstandard \
 kern/subr_acl_nfs4.c   optional ufs_acl | zfs
 kern/subr_acl_posix1e.coptional ufs_acl
 kern/subr_asan.c   optional kasan \
-   compile-with "${NORMAL_C:N-fsanitize*:N-fstack-protector*}"
+   compile-with "${NOSAN_C:N-fstack-protector*}"
 kern/subr_autoconf.c   standard
 kern/subr_blist.c  standard
 kern/subr_boot.c   standard
@@ -3891,10 +3891,10 @@ kern/subr_clock.c   standard
 kern/subr_compressor.c standard \
compile-with "${NORMAL_C} -I$S/contrib/zstd/lib/freebsd"
 kern/subr_coverage.c   optional coverage \
-   compile-with "${NORMAL_C:N-fsanitize*:N-fno-sanitize*}"
+   compile-with "${NOSAN_C}"
 kern/subr_counter.cstandard
 kern/subr_csan.c   optional kcsan \
-   compile-with "${NORMAL_C:N-fsanitize*:N-fstack-protector*}"
+   compile-with "${NOSAN_C:N-fstack-protector*}"
 kern/subr_devstat.cstandard
 kern/subr_disk.c   standard
 kern/subr_early.c  standard
@@ -3914,7 +3914,7 @@ kern/subr_mchain.coptional libmchain
 kern/subr_memdesc.cstandard
 kern/subr_module.c standard
 kern/subr_msan.c   optional kmsan \
-   compile-with 
"${NORMAL_C:N-fsanitize*:N-fno-sanitize*:N-fstack-protector*}"
+   compile-with "${NOSAN_C:N-fstack-protector*}"
 kern/subr_msgbuf.c standard
 kern/subr_param.c  standard
 kern/subr_pcpu.c   standard
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 0ff18cc6dd99..0688aabb562b 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -81,7 +81,7 @@ arm64/arm64/trap.cstandard
 arm64/arm64/uio_machdep.c  standard
 arm64/arm64/undefined.cstandard
 arm64/arm64/unwind.c   optional ddb | kdtrace_hooks | 
stack \
-   compile-with "${NORMAL_C:N-fsanitize*:N-fno-sanitize*}"
+   compile-with "${NOSAN_C}"
 arm64/arm64/vfp.c  standard
 arm64/arm64/vm_machdep.c   standard
 
@@ -124,10 +124,10 @@ arm64/vmm/vmm_arm64.c 
optional vmm
 arm64/vmm/vmm_reset.c  optional vmm
 arm64/vmm/vmm_call.S   optional vmm
 arm64/vmm/vmm_hyp_exception.S  optional vmm\
-   compile-with
"${NORMAL_C:N-fsanitize*:N-fno-sanitize*:N-mbranch-protection*} -fpie"  
\
+   compile-with "${NOSAN_C:N-mbranch-protection*} -fpie" \
no-obj
 arm64/vmm/vmm_hyp.coptional vmm\
-   compile-with
"${NORMAL_C:N-fsanitize*:N-fno-sanitize*:N-mbranch-protection*} -fpie"  
\
+   compile-with "${NOSAN_C:N-mbranch-protection*} -fpie" \
no-obj
 vmm_hyp_blob.elf.full  optional vmm\
depende

git: 43e8849bc294 - main - conf: Enable BTI checking in the arm64 kernel

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=43e8849bc29414036ccaef7788de95a07ad32ab5

commit 43e8849bc29414036ccaef7788de95a07ad32ab5
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:59:49 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

conf: Enable BTI checking in the arm64 kernel

To ensure new code has BTI support make it an error to not have the
BTI ELF note when linking the kernel and kernel modules.

Reviewed by:kib, emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45469
---
 sys/conf/kern.mk | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk
index 93187d93ac63..079bd1173fad 100644
--- a/sys/conf/kern.mk
+++ b/sys/conf/kern.mk
@@ -143,6 +143,9 @@ CFLAGS += -mgeneral-regs-only
 CFLAGS += -ffixed-x18
 # Build with BTI+PAC
 CFLAGS += -mbranch-protection=standard
+.if ${LINKER_TYPE} == "lld"
+LDFLAGS += -Wl,-zbti-report=error
+.endif
 # TODO: support outline atomics
 CFLAGS += -mno-outline-atomics
 INLINE_LIMIT?= 8000

git: 4db15ab2c65e - main - arm64: Add counter timer registers to armreg.h

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=4db15ab2c65e60f4d49d40ad6922ca301b184510

commit 4db15ab2c65e60f4d49d40ad6922ca301b184510
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:05 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64: Add counter timer registers to armreg.h

Reviewed by:imp
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46071
---
 sys/arm64/include/armreg.h | 48 ++
 1 file changed, 48 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index b2ab472dad0d..ce21bf4de0a9 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -231,6 +231,22 @@
 #defineCLIDR_CTYPE_ID  0x3 /* Split instruction and data */
 #defineCLIDR_CTYPE_UNIFIED 0x4 /* Unified */
 
+/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */
+#defineCNTKCTL_EL1 MRS_REG(CNTKCTL_EL0)
+#defineCNTKCTL_EL1_op0 3
+#defineCNTKCTL_EL1_op1 0
+#defineCNTKCTL_EL1_CRn 14
+#defineCNTKCTL_EL1_CRm 1
+#defineCNTKCTL_EL1_op2 0
+
+/* CNTKCTL_EL12 - Counter-timer Kernel Control Register */
+#defineCNTKCTL_EL12MRS_REG(CNTKCTL_EL0)
+#defineCNTKCTL_EL12_op03
+#defineCNTKCTL_EL12_op15
+#defineCNTKCTL_EL12_CRn14
+#defineCNTKCTL_EL12_CRm1
+#defineCNTKCTL_EL12_op20
+
 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
 #defineCNTP_CTL_EL0MRS_REG(CNTP_CTL_EL0)
 #defineCNTP_CTL_EL0_op03
@@ -266,6 +282,38 @@
 #defineCNTPCT_EL0_CRm  0
 #defineCNTPCT_EL0_op2  1
 
+/* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */
+#defineCNTV_CTL_EL0MRS_REG(CNTV_CTL_EL0)
+#defineCNTV_CTL_EL0_op03
+#defineCNTV_CTL_EL0_op13
+#defineCNTV_CTL_EL0_CRn14
+#defineCNTV_CTL_EL0_CRm3
+#defineCNTV_CTL_EL0_op21
+
+/* CNTV_CTL_EL02 - Counter-timer Virtual Timer Control register */
+#defineCNTV_CTL_EL02   MRS_REG(CNTV_CTL_EL02)
+#defineCNTV_CTL_EL02_op0   3
+#defineCNTV_CTL_EL02_op1   5
+#defineCNTV_CTL_EL02_CRn   14
+#defineCNTV_CTL_EL02_CRm   3
+#defineCNTV_CTL_EL02_op2   1
+
+/* CNTV_CVAL_EL0 - Counter-timer Virtual Timer CompareValue register */
+#defineCNTV_CVAL_EL0   MRS_REG(CNTV_CVAL_EL0)
+#defineCNTV_CVAL_EL0_op0   3
+#defineCNTV_CVAL_EL0_op1   3
+#defineCNTV_CVAL_EL0_CRn   14
+#defineCNTV_CVAL_EL0_CRm   3
+#defineCNTV_CVAL_EL0_op2   2
+
+/* CNTV_CVAL_EL02 - Counter-timer Virtual Timer CompareValue register */
+#defineCNTV_CVAL_EL02  MRS_REG(CNTV_CVAL_EL02)
+#defineCNTV_CVAL_EL02_op0  3
+#defineCNTV_CVAL_EL02_op1  5
+#defineCNTV_CVAL_EL02_CRn  14
+#defineCNTV_CVAL_EL02_CRm  3
+#defineCNTV_CVAL_EL02_op2  2
+
 /* CONTEXTIDR_EL1 - Context ID register */
 #defineCONTEXTIDR_EL1  MRS_REG(CONTEXTIDR_EL1)
 #defineCONTEXTIDR_EL1_REG  MRS_REG_ALT_NAME(CONTEXTIDR_EL1)

git: 3d61bcf1eb84 - main - arm64/vmm: Start to extract code not needed by VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=3d61bcf1eb8403780418096e4f520573acad6c0d

commit 3d61bcf1eb8403780418096e4f520573acad6c0d
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:22 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Start to extract code not needed by VHE

We can share some of the vmm code between VHE and non-VHE modes. To
support this create new files that include the common code and create
macros to name what will be the common functions.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46072
---
 sys/arm64/vmm/vmm_hyp.c| 58 --
 sys/arm64/vmm/vmm_hyp_exception.S  |  6 ++--
 sys/arm64/vmm/vmm_nvhe.c   | 31 
 sys/arm64/vmm/vmm_nvhe_exception.S | 30 
 sys/conf/files.arm64   |  6 ++--
 sys/modules/vmm/Makefile   |  9 +++---
 6 files changed, 103 insertions(+), 37 deletions(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 9ff250e798e7..1226876aa642 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -41,7 +41,7 @@ struct hypctx;
 
 uint64_t vmm_hyp_enter(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t,
 uint64_t, uint64_t, uint64_t);
-uint64_t vmm_enter_guest(struct hypctx *);
+uint64_t VMM_HYP_FUNC(do_call_guest)(struct hypctx *);
 
 static void
 vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, bool guest)
@@ -496,7 +496,7 @@ vmm_hyp_call_guest(struct hyp *hyp, struct hypctx *hypctx)
WRITE_SPECIALREG(mdcr_el2, hypctx->mdcr_el2);
 
/* Call into the guest */
-   ret = vmm_enter_guest(hypctx);
+   ret = VMM_HYP_FUNC(do_call_guest)(hypctx);
 
WRITE_SPECIALREG(mdcr_el2, host_hypctx.mdcr_el2);
isb();
@@ -566,8 +566,20 @@ vmm_hyp_call_guest(struct hyp *hyp, struct hypctx *hypctx)
return (ret);
 }
 
-static uint64_t
-vmm_hyp_read_reg(uint64_t reg)
+VMM_STATIC uint64_t
+VMM_HYP_FUNC(enter_guest)(struct hyp *hyp, struct hypctx *hypctx)
+{
+   uint64_t ret;
+
+   do {
+   ret = vmm_hyp_call_guest(hyp, hypctx);
+   } while (ret == EXCP_TYPE_REENTER);
+
+   return (ret);
+}
+
+VMM_STATIC uint64_t
+VMM_HYP_FUNC(read_reg)(uint64_t reg)
 {
switch (reg) {
case HYP_REG_ICH_VTR:
@@ -579,18 +591,16 @@ vmm_hyp_read_reg(uint64_t reg)
return (0);
 }
 
-static int
-vmm_clean_s2_tlbi(void)
+VMM_STATIC void
+VMM_HYP_FUNC(clean_s2_tlbi)(void)
 {
dsb(ishst);
__asm __volatile("tlbi alle1is");
dsb(ish);
-
-   return (0);
 }
 
-static int
-vm_s2_tlbi_range(uint64_t vttbr, vm_offset_t sva, vm_size_t eva,
+VMM_STATIC void
+VMM_HYP_FUNC(s2_tlbi_range)(uint64_t vttbr, vm_offset_t sva, vm_offset_t eva,
 bool final_only)
 {
uint64_t end, r, start;
@@ -634,12 +644,10 @@ vm_s2_tlbi_range(uint64_t vttbr, vm_offset_t sva, 
vm_size_t eva,
/* Switch back t othe host vttbr */
WRITE_SPECIALREG(vttbr_el2, host_vttbr);
isb();
-
-   return (0);
 }
 
-static int
-vm_s2_tlbi_all(uint64_t vttbr)
+VMM_STATIC void
+VMM_HYP_FUNC(s2_tlbi_all)(uint64_t vttbr)
 {
uint64_t host_vttbr;
 
@@ -656,8 +664,6 @@ vm_s2_tlbi_all(uint64_t vttbr)
/* Switch back t othe host vttbr */
WRITE_SPECIALREG(vttbr_el2, host_vttbr);
isb();
-
-   return (0);
 }
 
 static int
@@ -705,27 +711,25 @@ uint64_t
 vmm_hyp_enter(uint64_t handle, uint64_t x1, uint64_t x2, uint64_t x3,
 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7)
 {
-   uint64_t ret;
-
switch (handle) {
case HYP_ENTER_GUEST:
-   do {
-   ret = vmm_hyp_call_guest((struct hyp *)x1,
-   (struct hypctx *)x2);
-   } while (ret == EXCP_TYPE_REENTER);
-   return (ret);
+   return (VMM_HYP_FUNC(enter_guest)((struct hyp *)x1,
+   (struct hypctx *)x2));
case HYP_READ_REGISTER:
-   return (vmm_hyp_read_reg(x1));
+   return (VMM_HYP_FUNC(read_reg)(x1));
case HYP_CLEAN_S2_TLBI:
-   return (vmm_clean_s2_tlbi());
+   VMM_HYP_FUNC(clean_s2_tlbi());
+   return (0);
case HYP_DC_CIVAC:
return (vmm_dc_civac(x1, x2));
case HYP_EL2_TLBI:
return (vmm_el2_tlbi(x1, x2, x3));
case HYP_S2_TLBI_RANGE:
-   return (vm_s2_tlbi_range(x1, x2, x3, x4));
+   VMM_HYP_FUNC(s2_tlbi_range)(x1, x2, x3, x4);
+   return (0);
case HYP_S2_TLBI_ALL:
-   return (vm_s2_tlbi_all(x1));
+   VMM_HYP_FUNC(s2_tlbi_all)(x1);
+   return (0);
case HYP_CLEANUP:   /* Handled in vmm_hyp_exception.S */
default:
break;
diff --git a/sys/arm64/vmm/vmm_hyp_excep

git: 4b6c9f84deb5 - main - arm64/vmm: Move nVHE-only code to the new file

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=4b6c9f84deb53b111ccbcbea595b2cdd347ca7f9

commit 4b6c9f84deb53b111ccbcbea595b2cdd347ca7f9
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:31 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Move nVHE-only code to the new file

There are some functions that are only needed in non-VHE mode. These
are used to handle hypervisor calls from the kernel, and to manage the
page tables in EL2. As these won't be used by the VHE code we can move
them to the non-VHE specific files.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46073
---
 sys/arm64/vmm/vmm_hyp.c| 74 ---
 sys/arm64/vmm/vmm_hyp_exception.S  | 88 -
 sys/arm64/vmm/vmm_nvhe.c   | 83 +++
 sys/arm64/vmm/vmm_nvhe_exception.S | 90 ++
 4 files changed, 173 insertions(+), 162 deletions(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 1226876aa642..92f8cd25251d 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -39,8 +39,6 @@
 
 struct hypctx;
 
-uint64_t vmm_hyp_enter(uint64_t, uint64_t, uint64_t, uint64_t, uint64_t,
-uint64_t, uint64_t, uint64_t);
 uint64_t VMM_HYP_FUNC(do_call_guest)(struct hypctx *);
 
 static void
@@ -665,75 +663,3 @@ VMM_HYP_FUNC(s2_tlbi_all)(uint64_t vttbr)
WRITE_SPECIALREG(vttbr_el2, host_vttbr);
isb();
 }
-
-static int
-vmm_dc_civac(uint64_t start, uint64_t len)
-{
-   size_t line_size, end;
-   uint64_t ctr;
-
-   ctr = READ_SPECIALREG(ctr_el0);
-   line_size = sizeof(int) << CTR_DLINE_SIZE(ctr);
-   end = start + len;
-   dsb(ishst);
-   /* Clean and Invalidate the D-cache */
-   for (; start < end; start += line_size)
-   __asm __volatile("dccivac, %0" :: "r" (start) : "memory");
-   dsb(ish);
-   return (0);
-}
-
-static int
-vmm_el2_tlbi(uint64_t type, uint64_t start, uint64_t len)
-{
-   uint64_t end, r;
-
-   dsb(ishst);
-   switch (type) {
-   default:
-   case HYP_EL2_TLBI_ALL:
-   __asm __volatile("tlbi  alle2" ::: "memory");
-   break;
-   case HYP_EL2_TLBI_VA:
-   end = TLBI_VA(start + len);
-   start = TLBI_VA(start);
-   for (r = start; r < end; r += TLBI_VA_L3_INCR) {
-   __asm __volatile("tlbi  vae2is, %0" :: "r"(r));
-   }
-   break;
-   }
-   dsb(ish);
-
-   return (0);
-}
-
-uint64_t
-vmm_hyp_enter(uint64_t handle, uint64_t x1, uint64_t x2, uint64_t x3,
-uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7)
-{
-   switch (handle) {
-   case HYP_ENTER_GUEST:
-   return (VMM_HYP_FUNC(enter_guest)((struct hyp *)x1,
-   (struct hypctx *)x2));
-   case HYP_READ_REGISTER:
-   return (VMM_HYP_FUNC(read_reg)(x1));
-   case HYP_CLEAN_S2_TLBI:
-   VMM_HYP_FUNC(clean_s2_tlbi());
-   return (0);
-   case HYP_DC_CIVAC:
-   return (vmm_dc_civac(x1, x2));
-   case HYP_EL2_TLBI:
-   return (vmm_el2_tlbi(x1, x2, x3));
-   case HYP_S2_TLBI_RANGE:
-   VMM_HYP_FUNC(s2_tlbi_range)(x1, x2, x3, x4);
-   return (0);
-   case HYP_S2_TLBI_ALL:
-   VMM_HYP_FUNC(s2_tlbi_all)(x1);
-   return (0);
-   case HYP_CLEANUP:   /* Handled in vmm_hyp_exception.S */
-   default:
-   break;
-   }
-
-   return (0);
-}
diff --git a/sys/arm64/vmm/vmm_hyp_exception.S 
b/sys/arm64/vmm/vmm_hyp_exception.S
index 3b9c08af97ac..9a1648130f49 100644
--- a/sys/arm64/vmm/vmm_hyp_exception.S
+++ b/sys/arm64/vmm/vmm_hyp_exception.S
@@ -145,29 +145,6 @@
b   handle_\name
 .endm
 
-   .section ".vmm_vectors","ax"
-   .align 11
-hyp_init_vectors:
-   vempty  /* Synchronous EL2t */
-   vempty  /* IRQ EL2t */
-   vempty  /* FIQ EL2t */
-   vempty  /* Error EL2t */
-
-   vempty  /* Synchronous EL2h */
-   vempty  /* IRQ EL2h */
-   vempty  /* FIQ EL2h */
-   vempty  /* Error EL2h */
-
-   vector hyp_init /* Synchronous 64-bit EL1 */
-   vempty  /* IRQ 64-bit EL1 */
-   vempty  /* FIQ 64-bit EL1 */
-   vempty  /* Error 64-bit EL1 */
-
-   vempty  /* Synchronous 32-bit EL1 */
-   vempty  /* IRQ 32-bit EL1 */
-   vempty  /* FIQ 32-bit EL1 */
-   vempty  /* Error 32-bit EL1 */
-
.text
.align 11
 hyp_vectors:
@@ -191,50 +168,6 @@ hyp_vectors:
vempty   

git: a745cdc19b7f - main - arm64/vmm: Teach the vtimer about VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a745cdc19b7f92b490f7c332abad82945f3b06cb

commit a745cdc19b7f92b490f7c332abad82945f3b06cb
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:37 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Teach the vtimer about VHE

Teach the virtual timer about the cnthctl_el2 field layout under VHE.
As with non-VHE we need to trap the physical timer and not trap the
virtual timer.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46074
---
 sys/arm64/include/hypervisor.h |  4 
 sys/arm64/vmm/io/vtimer.c  | 38 +-
 2 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 011f86e83fdf..4c501e2722a9 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -41,6 +41,10 @@
 #defineCNTHCTL_EL1PCTEN(1 << 0) /* Allow physical counter 
access */
 #defineCNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access 
*/
 /* Valid if HCR_EL2.E2H == 1 */
+#defineCNTHCTL_E2H_EL0PCTEN(1 << 0) /* Allow EL0 physical counter 
access */
+#defineCNTHCTL_E2H_EL0VCTEN(1 << 1) /* Allow EL0 virtual counter 
access */
+#defineCNTHCTL_E2H_EL0VTEN (1 << 8)
+#defineCNTHCTL_E2H_EL0PTEN (1 << 9)
 #defineCNTHCTL_E2H_EL1PCTEN(1 << 10) /* Allow physical counter 
access */
 #defineCNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer 
access */
 /* Unconditionally valid */
diff --git a/sys/arm64/vmm/io/vtimer.c b/sys/arm64/vmm/io/vtimer.c
index aa0b3ff1588e..f59d7ebc1ad4 100644
--- a/sys/arm64/vmm/io/vtimer.c
+++ b/sys/arm64/vmm/io/vtimer.c
@@ -129,14 +129,42 @@ vtimer_vminit(struct hyp *hyp)
 {
uint64_t now;
 
+   hyp->vtimer.cnthctl_el2 = cnthctl_el2_reg;
+
/*
 * Configure the Counter-timer Hypervisor Control Register for the VM.
-*
-* CNTHCTL_EL1PCEN: trap access to CNTP_{CTL, CVAL, TVAL}_EL0 from EL1
-* CNTHCTL_EL1PCTEN: trap access to CNTPCT_EL0
 */
-   hyp->vtimer.cnthctl_el2 = cnthctl_el2_reg & ~CNTHCTL_EL1PCEN;
-   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_EL1PCTEN;
+   if (in_vhe()) {
+   /*
+* CNTHCTL_E2H_EL0PCTEN: trap EL0 access to CNTP{CT,CTSS}_EL0
+* CNTHCTL_E2H_EL1VCTEN: don't trap EL0 access to
+*   CNTV{CT,CTSS}_EL0
+* CNTHCTL_E2H_EL0VTEN: don't trap EL0 access to
+*  CNTV_{CTL,CVAL,TVAL}_EL0
+* CNTHCTL_E2H_EL0PTEN: trap EL0 access to
+*  CNTP_{CTL,CVAL,TVAL}_EL0
+* CNTHCTL_E2H_EL1PCEN: trap EL1 access to
+   CNTP_{CTL,CVAL,TVAL}_EL0
+* CNTHCTL_E2H_EL1PCTEN: trap access to CNTPCT_EL0
+*
+* TODO: Don't trap when FEAT_ECV is present
+*/
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL0PCTEN;
+   hyp->vtimer.cnthctl_el2 |= CNTHCTL_E2H_EL0VCTEN;
+   hyp->vtimer.cnthctl_el2 |= CNTHCTL_E2H_EL0VTEN;
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL0PTEN;
+
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL1PTEN;
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_E2H_EL1PCTEN;
+   } else {
+   /*
+* CNTHCTL_EL1PCEN: trap access to CNTP_{CTL, CVAL, TVAL}_EL0
+*  from EL1
+* CNTHCTL_EL1PCTEN: trap access to CNTPCT_EL0
+*/
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_EL1PCEN;
+   hyp->vtimer.cnthctl_el2 &= ~CNTHCTL_EL1PCTEN;
+   }
 
now = READ_SPECIALREG(cntpct_el0);
hyp->vtimer.cntvoff_el2 = now;

git: 55aa31480ced - main - arm64/vmm: Create functions to call into EL2

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=55aa31480ced477610b7cb0a948af6e99fefe864

commit 55aa31480ced477610b7cb0a948af6e99fefe864
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:42 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Create functions to call into EL2

These will become ifuncs to enable VHE in a later change.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46075
---
 sys/arm64/vmm/io/vgic_v3.c   |  3 +-
 sys/arm64/vmm/vmm_arm64.c| 38 --
 sys/arm64/vmm/vmm_handlers.c | 65 
 sys/arm64/vmm/vmm_handlers.h | 48 
 sys/conf/files.arm64 |  1 +
 sys/modules/vmm/Makefile |  1 +
 6 files changed, 123 insertions(+), 33 deletions(-)

diff --git a/sys/arm64/vmm/io/vgic_v3.c b/sys/arm64/vmm/io/vgic_v3.c
index 7ed591c409ba..67afb3374815 100644
--- a/sys/arm64/vmm/io/vgic_v3.c
+++ b/sys/arm64/vmm/io/vgic_v3.c
@@ -68,6 +68,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "vgic.h"
 #include "vgic_v3.h"
@@ -2252,7 +2253,7 @@ vgic_v3_init(device_t dev)
uint64_t ich_vtr_el2;
uint32_t pribits, prebits;
 
-   ich_vtr_el2 = vmm_call_hyp(HYP_READ_REGISTER, HYP_REG_ICH_VTR);
+   ich_vtr_el2 = vmm_read_reg(HYP_REG_ICH_VTR);
 
/* TODO: These fields are common with the vgicv2 driver */
pribits = ICH_VTR_EL2_PRIBITS(ich_vtr_el2);
diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index e5eee47b405b..1b73ed019fad 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -65,6 +65,7 @@
 #include "io/vgic.h"
 #include "io/vgic_v3.h"
 #include "io/vtimer.h"
+#include "vmm_handlers.h"
 #include "vmm_stat.h"
 
 #defineHANDLED 1
@@ -101,9 +102,6 @@ static vm_offset_t stack_hyp_va[MAXCPU];
 static vmem_t *el2_mem_alloc;
 
 static void arm_setup_vectors(void *arg);
-static void vmm_pmap_clean_stage2_tlbi(void);
-static void vmm_pmap_invalidate_range(uint64_t, vm_offset_t, vm_offset_t, 
bool);
-static void vmm_pmap_invalidate_all(uint64_t);
 
 DPCPU_DEFINE_STATIC(struct hypctx *, vcpu);
 
@@ -235,7 +233,6 @@ vmmops_modinit(int ipinum)
vm_paddr_t vmm_base;
uint64_t id_aa64mmfr0_el1, pa_range_bits, pa_range_field;
uint64_t cnthctl_el2;
-   register_t daif;
int cpu, i;
bool rv __diagused;
 
@@ -291,9 +288,9 @@ vmmops_modinit(int ipinum)
 
/* Set up the stage 2 pmap callbacks */
MPASS(pmap_clean_stage2_tlbi == NULL);
-   pmap_clean_stage2_tlbi = vmm_pmap_clean_stage2_tlbi;
-   pmap_stage2_invalidate_range = vmm_pmap_invalidate_range;
-   pmap_stage2_invalidate_all = vmm_pmap_invalidate_all;
+   pmap_clean_stage2_tlbi = vmm_clean_s2_tlbi;
+   pmap_stage2_invalidate_range = vmm_s2_tlbi_range;
+   pmap_stage2_invalidate_all = vmm_s2_tlbi_all;
 
/*
 * Create an allocator for the virtual address space used by EL2.
@@ -429,9 +426,7 @@ vmmops_modinit(int ipinum)
vmem_add(el2_mem_alloc, next_hyp_va,
HYP_VM_MAX_ADDRESS - next_hyp_va, M_WAITOK);
 
-   daif = intr_disable();
-   cnthctl_el2 = vmm_call_hyp(HYP_READ_REGISTER, HYP_REG_CNTHCTL);
-   intr_restore(daif);
+   cnthctl_el2 = vmm_read_reg(HYP_REG_CNTHCTL);
 
vgic_init();
vtimer_init(cnthctl_el2);
@@ -567,26 +562,6 @@ vmmops_vmspace_free(struct vmspace *vmspace)
vmspace_free(vmspace);
 }
 
-static void
-vmm_pmap_clean_stage2_tlbi(void)
-{
-   vmm_call_hyp(HYP_CLEAN_S2_TLBI);
-}
-
-static void
-vmm_pmap_invalidate_range(uint64_t vttbr, vm_offset_t sva, vm_offset_t eva,
-bool final_only)
-{
-   MPASS(eva > sva);
-   vmm_call_hyp(HYP_S2_TLBI_RANGE, vttbr, sva, eva, final_only);
-}
-
-static void
-vmm_pmap_invalidate_all(uint64_t vttbr)
-{
-   vmm_call_hyp(HYP_S2_TLBI_ALL, vttbr);
-}
-
 static inline void
 arm64_print_hyp_regs(struct vm_exit *vme)
 {
@@ -1143,8 +1118,7 @@ vmmops_run(void *vcpui, register_t pc, pmap_t pmap, 
struct vm_eventinfo *evinfo)
vgic_flush_hwstate(hypctx);
 
/* Call into EL2 to switch to the guest */
-   excp_type = vmm_call_hyp(HYP_ENTER_GUEST,
-   hyp->el2_addr, hypctx->el2_addr);
+   excp_type = vmm_enter_guest(hyp, hypctx);
 
vgic_sync_hwstate(hypctx);
vtimer_sync_hwstate(hypctx);
diff --git a/sys/arm64/vmm/vmm_handlers.c b/sys/arm64/vmm/vmm_handlers.c
new file mode 100644
index ..2ce674d5ba46
--- /dev/null
+++ b/sys/arm64/vmm/vmm_handlers.c
@@ -0,0 +1,65 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2024 Arm Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modifi

git: 387f878aa7af - main - arm64/vmm: Teach vmm_arm.c about VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=387f878aa7afdc48cdd304a9c2f5e6806639f6f0

commit 387f878aa7afdc48cdd304a9c2f5e6806639f6f0
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:46 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Teach vmm_arm.c about VHE

Most of the code is identical however some, e.g. managing EL2 memory
or setting EL2 registers, are unneeded under VHE as the kernel is in
EL2 so can manage these directly.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46076
---
 sys/arm64/vmm/vmm_arm64.c | 224 +-
 sys/arm64/vmm/vmm_reset.c |   8 +-
 2 files changed, 127 insertions(+), 105 deletions(-)

diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index 1b73ed019fad..3079353668e3 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -128,20 +128,6 @@ arm_setup_vectors(void *arg)
el2_regs = arg;
arm64_set_active_vcpu(NULL);
 
-   daif = intr_disable();
-
-   /*
-* Install the temporary vectors which will be responsible for
-* initializing the VMM when we next trap into EL2.
-*
-* x0: the exception vector table responsible for hypervisor
-* initialization on the next call.
-*/
-   vmm_call_hyp(vtophys(&vmm_hyp_code));
-
-   /* Create and map the hypervisor stack */
-   stack_top = stack_hyp_va[PCPU_GET(cpuid)] + VMM_STACK_SIZE;
-
/*
 * Configure the system control register for EL2:
 *
@@ -159,9 +145,27 @@ arm_setup_vectors(void *arg)
sctlr_el2 |= SCTLR_EL2_WXN;
sctlr_el2 &= ~SCTLR_EL2_EE;
 
-   /* Special call to initialize EL2 */
-   vmm_call_hyp(vmmpmap_to_ttbr0(), stack_top, el2_regs->tcr_el2,
-   sctlr_el2, el2_regs->vtcr_el2);
+   daif = intr_disable();
+
+   if (in_vhe()) {
+   WRITE_SPECIALREG(vtcr_el2, el2_regs->vtcr_el2);
+   } else {
+   /*
+* Install the temporary vectors which will be responsible for
+* initializing the VMM when we next trap into EL2.
+*
+* x0: the exception vector table responsible for hypervisor
+* initialization on the next call.
+*/
+   vmm_call_hyp(vtophys(&vmm_hyp_code));
+
+   /* Create and map the hypervisor stack */
+   stack_top = stack_hyp_va[PCPU_GET(cpuid)] + VMM_STACK_SIZE;
+
+   /* Special call to initialize EL2 */
+   vmm_call_hyp(vmmpmap_to_ttbr0(), stack_top, el2_regs->tcr_el2,
+   sctlr_el2, el2_regs->vtcr_el2);
+   }
 
intr_restore(daif);
 }
@@ -280,10 +284,12 @@ vmmops_modinit(int ipinum)
}
pa_range_bits = pa_range_field >> ID_AA64MMFR0_PARange_SHIFT;
 
-   /* Initialise the EL2 MMU */
-   if (!vmmpmap_init()) {
-   printf("vmm: Failed to init the EL2 MMU\n");
-   return (ENOMEM);
+   if (!in_vhe()) {
+   /* Initialise the EL2 MMU */
+   if (!vmmpmap_init()) {
+   printf("vmm: Failed to init the EL2 MMU\n");
+   return (ENOMEM);
+   }
}
 
/* Set up the stage 2 pmap callbacks */
@@ -292,55 +298,58 @@ vmmops_modinit(int ipinum)
pmap_stage2_invalidate_range = vmm_s2_tlbi_range;
pmap_stage2_invalidate_all = vmm_s2_tlbi_all;
 
-   /*
-* Create an allocator for the virtual address space used by EL2.
-* EL2 code is identity-mapped; the allocator is used to find space for
-* VM structures.
-*/
-   el2_mem_alloc = vmem_create("VMM EL2", 0, 0, PAGE_SIZE, 0, M_WAITOK);
-
-   /* Create the mappings for the hypervisor translation table. */
-   hyp_code_len = round_page(&vmm_hyp_code_end - &vmm_hyp_code);
-
-   /* We need an physical identity mapping for when we activate the MMU */
-   hyp_code_base = vmm_base = vtophys(&vmm_hyp_code);
-   rv = vmmpmap_enter(vmm_base, hyp_code_len, vmm_base,
-   VM_PROT_READ | VM_PROT_EXECUTE);
-   MPASS(rv);
-
-   next_hyp_va = roundup2(vmm_base + hyp_code_len, L2_SIZE);
-
-   /* Create a per-CPU hypervisor stack */
-   CPU_FOREACH(cpu) {
-   stack[cpu] = malloc(VMM_STACK_SIZE, M_HYP, M_WAITOK | M_ZERO);
-   stack_hyp_va[cpu] = next_hyp_va;
-
-   for (i = 0; i < VMM_STACK_PAGES; i++) {
-   rv = vmmpmap_enter(stack_hyp_va[cpu] + ptoa(i),
-   PAGE_SIZE, vtophys(stack[cpu] + ptoa(i)),
-   VM_PROT_READ | VM_PROT_WRITE);
-   MPASS(rv);
+   if (!in_vhe()) {
+   /*
+* Create an alloc

git: 6b17f49da0a2 - main - arm64/vmm: Restore hcr_el2 earlier

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=6b17f49da0a2c4cba05e6a1994fb10d16f11fe0a

commit 6b17f49da0a2c4cba05e6a1994fb10d16f11fe0a
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:51 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Restore hcr_el2 earlier

It may cause fields in other registers to change meaning.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46077
---
 sys/arm64/vmm/vmm_hyp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 92f8cd25251d..9341f42daef6 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -262,6 +262,9 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
uint64_t dfr0;
 
/* Restore the special registers */
+   WRITE_SPECIALREG(hcr_el2, hypctx->hcr_el2);
+   isb();
+
WRITE_SPECIALREG(elr_el1, hypctx->elr_el1);
WRITE_SPECIALREG(sp_el0, hypctx->sp_el0);
WRITE_SPECIALREG(tpidr_el0, hypctx->tpidr_el0);
@@ -290,7 +293,6 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
WRITE_SPECIALREG(spsr_el1, hypctx->spsr_el1);
 
WRITE_SPECIALREG(cptr_el2, hypctx->cptr_el2);
-   WRITE_SPECIALREG(hcr_el2, hypctx->hcr_el2);
WRITE_SPECIALREG(vpidr_el2, hypctx->vpidr_el2);
WRITE_SPECIALREG(vmpidr_el2, hypctx->vmpidr_el2);
 

git: 7861ecd18b6f - main - arm64/vmm: Teach the switcher about new registers

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7861ecd18b6f15cfe37fc6f51f6ba89b92398648

commit 7861ecd18b6f15cfe37fc6f51f6ba89b92398648
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:43:59 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Teach the switcher about new registers

To support booting the kernel in EL2 some of the EL0 and EL1 registers
are changed to point to an EL2 version. To get access to the EL0/EL1
version of these registers we need to use the new EL02 and EL12
registers, e.g. to access elr_el1 from the host we would use elr_el12.

Add macros that can be different on VHE vs non-VHE code so these
registers can be accessed in the correct way.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46078
---
 sys/arm64/vmm/vmm_hyp.c  | 89 +++-
 sys/arm64/vmm/vmm_nvhe.c |  4 +++
 2 files changed, 54 insertions(+), 39 deletions(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 9341f42daef6..ae0c46331382 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -49,11 +49,12 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
/* Store the guest VFP registers */
if (guest) {
/* Store the timer registers */
-   hypctx->vtimer_cpu.cntkctl_el1 = READ_SPECIALREG(cntkctl_el1);
+   hypctx->vtimer_cpu.cntkctl_el1 =
+   READ_SPECIALREG(EL1_REG(CNTKCTL));
hypctx->vtimer_cpu.virt_timer.cntx_cval_el0 =
-   READ_SPECIALREG(cntv_cval_el0);
+   READ_SPECIALREG(EL0_REG(CNTV_CVAL));
hypctx->vtimer_cpu.virt_timer.cntx_ctl_el0 =
-   READ_SPECIALREG(cntv_ctl_el0);
+   READ_SPECIALREG(EL0_REG(CNTV_CTL));
 
/* Store the GICv3 registers */
hypctx->vgic_v3_regs.ich_eisr_el2 =
@@ -222,33 +223,37 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
}
 
/* Store the guest special registers */
-   hypctx->elr_el1 = READ_SPECIALREG(elr_el1);
hypctx->sp_el0 = READ_SPECIALREG(sp_el0);
hypctx->tpidr_el0 = READ_SPECIALREG(tpidr_el0);
hypctx->tpidrro_el0 = READ_SPECIALREG(tpidrro_el0);
hypctx->tpidr_el1 = READ_SPECIALREG(tpidr_el1);
-   hypctx->vbar_el1 = READ_SPECIALREG(vbar_el1);
 
hypctx->actlr_el1 = READ_SPECIALREG(actlr_el1);
-   hypctx->afsr0_el1 = READ_SPECIALREG(afsr0_el1);
-   hypctx->afsr1_el1 = READ_SPECIALREG(afsr1_el1);
-   hypctx->amair_el1 = READ_SPECIALREG(amair_el1);
-   hypctx->contextidr_el1 = READ_SPECIALREG(contextidr_el1);
-   hypctx->cpacr_el1 = READ_SPECIALREG(cpacr_el1);
hypctx->csselr_el1 = READ_SPECIALREG(csselr_el1);
-   hypctx->esr_el1 = READ_SPECIALREG(esr_el1);
-   hypctx->far_el1 = READ_SPECIALREG(far_el1);
-   hypctx->mair_el1 = READ_SPECIALREG(mair_el1);
hypctx->mdccint_el1 = READ_SPECIALREG(mdccint_el1);
hypctx->mdscr_el1 = READ_SPECIALREG(mdscr_el1);
hypctx->par_el1 = READ_SPECIALREG(par_el1);
-   hypctx->sctlr_el1 = READ_SPECIALREG(sctlr_el1);
-   hypctx->spsr_el1 = READ_SPECIALREG(spsr_el1);
-   hypctx->tcr_el1 = READ_SPECIALREG(tcr_el1);
-   /* TODO: Support when this is not res0 */
-   hypctx->tcr2_el1 = 0;
-   hypctx->ttbr0_el1 = READ_SPECIALREG(ttbr0_el1);
-   hypctx->ttbr1_el1 = READ_SPECIALREG(ttbr1_el1);
+
+   if (guest_or_nonvhe(guest)) {
+   hypctx->elr_el1 = READ_SPECIALREG(EL1_REG(ELR));
+   hypctx->vbar_el1 = READ_SPECIALREG(EL1_REG(VBAR));
+
+   hypctx->afsr0_el1 = READ_SPECIALREG(EL1_REG(AFSR0));
+   hypctx->afsr1_el1 = READ_SPECIALREG(EL1_REG(AFSR1));
+   hypctx->amair_el1 = READ_SPECIALREG(EL1_REG(AMAIR));
+   hypctx->contextidr_el1 = READ_SPECIALREG(EL1_REG(CONTEXTIDR));
+   hypctx->cpacr_el1 = READ_SPECIALREG(EL1_REG(CPACR));
+   hypctx->esr_el1 = READ_SPECIALREG(EL1_REG(ESR));
+   hypctx->far_el1 = READ_SPECIALREG(EL1_REG(FAR));
+   hypctx->mair_el1 = READ_SPECIALREG(EL1_REG(MAIR));
+   hypctx->sctlr_el1 = READ_SPECIALREG(EL1_REG(SCTLR));
+   hypctx->spsr_el1 = READ_SPECIALREG(EL1_REG(SPSR));
+   hypctx->tcr_el1 = READ_SPECIALREG(EL1_REG(TCR));
+   /* TODO: Support when this is not res0 */
+   hypctx->tcr2_el1 = 0;
+   hypctx->ttbr0_el1 = READ_SPECIALREG(EL1_REG(TTBR0));
+   hypctx->ttbr1_el1 = READ_SPECIALREG(EL1_REG(TTBR1));
+   }
 
hypctx->cptr_el2 = READ_SPECIALREG(cptr_el2);

git: 5577bb2f67ff - main - arm64/vmm: Support tlbi from VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=5577bb2f67ff442a92a3c0edb133e03bc28bb9d6

commit 5577bb2f67ff442a92a3c0edb133e03bc28bb9d6
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:44:11 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Support tlbi from VHE

When invalidating the stage 2 TLB we need to ensure page tables updates
have completed and for tlbi vmalle1is the HCR_EL2 TGE flag needs to be
clear.

To fix the former add a data barrier before the tlbi instructions. On
non-VHE this will happen as part of the exception entry, so is only
needed for VHE.

The tlbi vmalle1is instruction operates on the EL2 & 0 regime when
HCR_EL2 E2H and TGE flags are both set. By clearing the TGE flag it
will stop this and operate on the EL1 & 0 regime we are expecting.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46080
---
 sys/arm64/vmm/vmm_hyp.c | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index 9c84bb4b294e..bd119c80139b 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -619,6 +619,13 @@ VMM_HYP_FUNC(s2_tlbi_range)(uint64_t vttbr, vm_offset_t 
sva, vm_offset_t eva,
 {
uint64_t end, r, start;
uint64_t host_vttbr;
+#ifdef VMM_VHE
+   uint64_t host_tcr;
+#endif
+
+#ifdef VMM_VHE
+   dsb(ishst);
+#endif
 
 #defineTLBI_VA_SHIFT   12
 #defineTLBI_VA_MASK((1ul << 44) - 1)
@@ -631,6 +638,12 @@ VMM_HYP_FUNC(s2_tlbi_range)(uint64_t vttbr, vm_offset_t 
sva, vm_offset_t eva,
WRITE_SPECIALREG(vttbr_el2, vttbr);
isb();
 
+#ifdef VMM_VHE
+   host_tcr = READ_SPECIALREG(tcr_el2);
+   WRITE_SPECIALREG(tcr_el2, host_tcr & ~HCR_TGE);
+   isb();
+#endif
+
/*
 * The CPU can cache the stage 1 + 2 combination so we need to ensure
 * the stage 2 is invalidated first, then when this has completed we
@@ -655,7 +668,12 @@ VMM_HYP_FUNC(s2_tlbi_range)(uint64_t vttbr, vm_offset_t 
sva, vm_offset_t eva,
dsb(ish);
isb();
 
-   /* Switch back t othe host vttbr */
+#ifdef VMM_VHE
+   WRITE_SPECIALREG(tcr_el2, host_tcr);
+   isb();
+#endif
+
+   /* Switch back to the host vttbr */
WRITE_SPECIALREG(vttbr_el2, host_vttbr);
isb();
 }
@@ -665,6 +683,10 @@ VMM_HYP_FUNC(s2_tlbi_all)(uint64_t vttbr)
 {
uint64_t host_vttbr;
 
+#ifdef VMM_VHE
+   dsb(ishst);
+#endif
+
/* Switch to the guest vttbr */
/* TODO: Handle Cortex-A57/A72 erratum 131936 */
host_vttbr = READ_SPECIALREG(vttbr_el2);

git: 20eabb33b464 - main - arm64/vmm: Only store the guest par_el1

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=20eabb33b4645bc088c40d6475d5fa628b39031f

commit 20eabb33b4645bc088c40d6475d5fa628b39031f
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:44:05 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:15 +

arm64/vmm: Only store the guest par_el1

There is no need to store the host par_el1. We don't depend on it not
changing across calls into a guest.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46079
---
 sys/arm64/vmm/vmm_hyp.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/vmm/vmm_hyp.c b/sys/arm64/vmm/vmm_hyp.c
index ae0c46331382..9c84bb4b294e 100644
--- a/sys/arm64/vmm/vmm_hyp.c
+++ b/sys/arm64/vmm/vmm_hyp.c
@@ -220,6 +220,7 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
hypctx->tf.tf_spsr = READ_SPECIALREG(spsr_el2);
if (guest) {
hypctx->tf.tf_esr = READ_SPECIALREG(esr_el2);
+   hypctx->par_el1 = READ_SPECIALREG(par_el1);
}
 
/* Store the guest special registers */
@@ -232,7 +233,6 @@ vmm_hyp_reg_store(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
hypctx->csselr_el1 = READ_SPECIALREG(csselr_el1);
hypctx->mdccint_el1 = READ_SPECIALREG(mdccint_el1);
hypctx->mdscr_el1 = READ_SPECIALREG(mdscr_el1);
-   hypctx->par_el1 = READ_SPECIALREG(par_el1);
 
if (guest_or_nonvhe(guest)) {
hypctx->elr_el1 = READ_SPECIALREG(EL1_REG(ELR));
@@ -279,7 +279,6 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp *hyp, 
bool guest)
WRITE_SPECIALREG(csselr_el1, hypctx->csselr_el1);
WRITE_SPECIALREG(mdccint_el1, hypctx->mdccint_el1);
WRITE_SPECIALREG(mdscr_el1, hypctx->mdscr_el1);
-   WRITE_SPECIALREG(par_el1, hypctx->par_el1);
 
if (guest_or_nonvhe(guest)) {
WRITE_SPECIALREG(EL1_REG(ELR), hypctx->elr_el1);
@@ -302,6 +301,10 @@ vmm_hyp_reg_restore(struct hypctx *hypctx, struct hyp 
*hyp, bool guest)
WRITE_SPECIALREG(EL1_REG(TTBR1), hypctx->ttbr1_el1);
}
 
+   if (guest) {
+   WRITE_SPECIALREG(par_el1, hypctx->par_el1);
+   }
+
WRITE_SPECIALREG(cptr_el2, hypctx->cptr_el2);
WRITE_SPECIALREG(vpidr_el2, hypctx->vpidr_el2);
WRITE_SPECIALREG(vmpidr_el2, hypctx->vmpidr_el2);

git: f83a0f38d14e - main - arm64/vmm: Update exception vectors around a guest

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=f83a0f38d14e26f5f7f31050786e9190cd131902

commit f83a0f38d14e26f5f7f31050786e9190cd131902
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:44:18 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Update exception vectors around a guest

When entering into a guest with VHE we need to switch from the kernel
exception vectors to the vmm exception vectors. The latter understands
an exception will be from a guest and can switch back to a kernel
context.

Rather than encoding the location of the kernel vectors we can just
read the value from vbar_el2 and restore it later.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46081
---
 sys/arm64/vmm/vmm_hyp_exception.S | 12 
 1 file changed, 12 insertions(+)

diff --git a/sys/arm64/vmm/vmm_hyp_exception.S 
b/sys/arm64/vmm/vmm_hyp_exception.S
index 9a1648130f49..cd2b94f1ff0b 100644
--- a/sys/arm64/vmm/vmm_hyp_exception.S
+++ b/sys/arm64/vmm/vmm_hyp_exception.S
@@ -175,6 +175,10 @@ hyp_vectors:
/* Restore host VTTBR */
mov x9, #VTTBR_HOST
msr vttbr_el2, x9
+
+#ifdef VMM_VHE
+   msr vbar_el1, x1
+#endif
 .endm
 
 
@@ -288,6 +292,14 @@ LEND(handle_el2_el1_error64)
  * x0 - hypctx address
  */
 ENTRY(VMM_HYP_FUNC(do_call_guest))
+#ifdef VMM_VHE
+   mrs x1, vbar_el1
+   adrpx2, hyp_vectors
+   add x2, x2, :lo12:hyp_vectors
+   msr vbar_el1, x2
+   isb
+#endif
+
/* Save hypctx address */
msr tpidr_el2, x0
 

git: 79a19e0e8d8d - main - arm64/vmm: Hide non-VHE exception code from VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=79a19e0e8d8d1fa71092e542671213bfe99b024e

commit 79a19e0e8d8d1fa71092e542671213bfe99b024e
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:44:24 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Hide non-VHE exception code from VHE

Remove the non-VHE exception code from the VHE code path. As we replace
the exception vectors when entering the guest we don't need to check
which context we are in so can skip parts of the exception vectors.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46082
---
 sys/arm64/vmm/vmm_hyp_exception.S | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/vmm/vmm_hyp_exception.S 
b/sys/arm64/vmm/vmm_hyp_exception.S
index cd2b94f1ff0b..95b0e20f37ed 100644
--- a/sys/arm64/vmm/vmm_hyp_exception.S
+++ b/sys/arm64/vmm/vmm_hyp_exception.S
@@ -183,6 +183,7 @@ hyp_vectors:
 
 
 .macro handle_el2_excp type
+#ifndef VMM_VHE
/* Save registers before modifying so we can restore them */
str x9, [sp, #-16]!
 
@@ -193,15 +194,18 @@ hyp_vectors:
 
/* We got the exception while the guest was running */
ldr x9, [sp], #16
+#endif /* !VMM_VHE */
do_world_switch_to_host
mov x0, \type
ret
 
+#ifndef VMM_VHE
 1:
/* We got the exception while the host was running */
ldr x9, [sp], #16
mov x0, \type
ERET
+#endif /* !VMM_VHE */
 .endm
 
 
@@ -223,6 +227,7 @@ LEND(handle_el2_el2h_error)
 
 
 LENTRY(handle_el2_el1_sync64)
+#ifndef VMM_VHE
/* Save registers before modifying so we can restore them */
str x9, [sp, #-16]!
 
@@ -245,7 +250,9 @@ LENTRY(handle_el2_el1_sync64)
ldr lr, [sp], #16
ERET
 
-1: /* Guest exception taken to EL2 */
+1:
+#endif
+   /* Guest exception taken to EL2 */
do_world_switch_to_host
mov x0, #EXCP_TYPE_EL1_SYNC
ret

git: b87952e837ec - main - arm64/vmm: Mark asm files as supporting BTI

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=b87952e837ec1e42a573557a8e938693d8952705

commit b87952e837ec1e42a573557a8e938693d8952705
Author: Andrew Turner 
AuthorDate: 2024-08-19 13:28:39 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Mark asm files as supporting BTI

These already support BTI as they use the ENTRY macro. While the
non-VHE code doesn't need this the new VHE code will need it as it is
linked into either the kernel or the vmm module so will be included in
the BTI check.

Sponsored by:   Arm Ltd
---
 sys/arm64/vmm/vmm_hyp_exception.S | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sys/arm64/vmm/vmm_hyp_exception.S 
b/sys/arm64/vmm/vmm_hyp_exception.S
index 95b0e20f37ed..50c2490f37bf 100644
--- a/sys/arm64/vmm/vmm_hyp_exception.S
+++ b/sys/arm64/vmm/vmm_hyp_exception.S
@@ -30,6 +30,7 @@
  */
 
 
+#include 
 #include 
 #include 
 
@@ -316,3 +317,5 @@ ENTRY(VMM_HYP_FUNC(do_call_guest))
/* Enter guest */
ERET
 END(VMM_HYP_FUNC(do_call_guest))
+
+GNU_PROPERTY_AARCH64_FEATURE_1_NOTE(GNU_PROPERTY_AARCH64_FEATURE_1_VAL)

git: bbe97db3c211 - main - arm64/vmm: Add the VHE exception and switcher files

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=bbe97db3c211bd0a89a5b9c1a58857625b763475

commit bbe97db3c211bd0a89a5b9c1a58857625b763475
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:44:31 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Add the VHE exception and switcher files

These just need to include the common code with macros to ensure it is
built correctly.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46083
---
 sys/arm64/vmm/vmm_vhe.c   | 39 +++
 sys/arm64/vmm/vmm_vhe_exception.S | 31 +++
 sys/conf/files.arm64  |  2 ++
 sys/modules/vmm/Makefile  |  2 ++
 4 files changed, 74 insertions(+)

diff --git a/sys/arm64/vmm/vmm_vhe.c b/sys/arm64/vmm/vmm_vhe.c
new file mode 100644
index ..8a12852e2a7a
--- /dev/null
+++ b/sys/arm64/vmm/vmm_vhe.c
@@ -0,0 +1,39 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2024 Arm Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "vmm_handlers.h"
+
+#defineVMM_VHE
+
+#defineVMM_STATIC
+#defineVMM_HYP_FUNC(func)  vmm_vhe_ ## func
+
+#defineguest_or_nonvhe(guest)  (guest)
+#defineEL1_REG(reg)MRS_REG_ALT_NAME(reg ## _EL12)
+#defineEL0_REG(reg)MRS_REG_ALT_NAME(reg ## _EL02)
+
+#include "vmm_hyp.c"
diff --git a/sys/arm64/vmm/vmm_vhe_exception.S 
b/sys/arm64/vmm/vmm_vhe_exception.S
new file mode 100644
index ..286f5df03707
--- /dev/null
+++ b/sys/arm64/vmm/vmm_vhe_exception.S
@@ -0,0 +1,31 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2024 Arm Ltd
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#define VMM_VHE
+#defineVMM_HYP_FUNC(func)  vmm_vhe_ ## func
+
+#include "vmm_hyp_exception.S"
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index b522177221e5..b105ce873d24 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -145,6 +145,8 @@ vmm_hyp_blob.binoptional vmm
\
 arm64/vmm/vmm_hyp_el2.Soptional vmm
\
dependency  vmm_hyp_blob.bin
 arm64/vmm/vmm_mmu.coptional vmm
+arm64/vmm/vmm_vhe.c 

git: 7279fa6af13d - main - arm64/vmm: Convert the handlers into ifuncs

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7279fa6af13d1c370f9bcb293562c694090d849d

commit 7279fa6af13d1c370f9bcb293562c694090d849d
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:45:54 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Convert the handlers into ifuncs

Now we have support for both VHE and non-VHE update the handlers to
use an ifunc to decide which version to use.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46084
---
 sys/arm64/vmm/vmm_handlers.c | 68 +---
 1 file changed, 58 insertions(+), 10 deletions(-)

diff --git a/sys/arm64/vmm/vmm_handlers.c b/sys/arm64/vmm/vmm_handlers.c
index 2ce674d5ba46..c567b585eb06 100644
--- a/sys/arm64/vmm/vmm_handlers.c
+++ b/sys/arm64/vmm/vmm_handlers.c
@@ -33,33 +33,81 @@
 #include "arm64.h"
 #include "vmm_handlers.h"
 
-uint64_t
-vmm_read_reg(uint64_t reg)
+/* Read an EL2 register */
+static uint64_t
+vmm_nvhe_read_reg(uint64_t reg)
 {
return (vmm_call_hyp(HYP_READ_REGISTER, reg));
 }
 
-uint64_t
-vmm_enter_guest(struct hyp *hyp, struct hypctx *hypctx)
+DEFINE_IFUNC(, uint64_t, vmm_read_reg, (uint64_t reg))
+{
+   if (in_vhe())
+   return (vmm_vhe_read_reg);
+   return (vmm_nvhe_read_reg);
+}
+
+/* Enter the guest */
+static uint64_t
+vmm_nvhe_enter_guest(struct hyp *hyp, struct hypctx *hypctx)
 {
return (vmm_call_hyp(HYP_ENTER_GUEST, hyp->el2_addr, hypctx->el2_addr));
 }
 
-void
-vmm_clean_s2_tlbi(void)
+DEFINE_IFUNC(, uint64_t, vmm_enter_guest,
+(struct hyp *hyp, struct hypctx *hypctx))
+{
+   if (in_vhe())
+   return (vmm_vhe_enter_guest);
+   return (vmm_nvhe_enter_guest);
+}
+
+/* Clean the TLB for all guests */
+static void
+vmm_nvhe_clean_s2_tlbi(void)
 {
vmm_call_hyp(HYP_CLEAN_S2_TLBI);
 }
 
-void
-vmm_s2_tlbi_range(uint64_t vttbr, vm_offset_t sva, vm_offset_t eva,
+DEFINE_IFUNC(, void, vmm_clean_s2_tlbi, (void))
+{
+   if (in_vhe())
+   return (vmm_vhe_clean_s2_tlbi);
+   return (vmm_nvhe_clean_s2_tlbi);
+}
+
+/*
+ * Switch to a guest vttbr and clean the TLB for a range of guest
+ * virtual address space.
+ */
+static void
+vmm_nvhe_s2_tlbi_range(uint64_t vttbr, vm_offset_t sva, vm_offset_t eva,
 bool final_only)
 {
vmm_call_hyp(HYP_S2_TLBI_RANGE, vttbr, sva, eva, final_only);
 }
 
-void
-vmm_s2_tlbi_all(uint64_t vttbr)
+DEFINE_IFUNC(, void, vmm_s2_tlbi_range,
+(uint64_t vttbr, vm_offset_t sva, vm_offset_t eva, bool final_only))
+{
+   if (in_vhe())
+   return (vmm_vhe_s2_tlbi_range);
+   return (vmm_nvhe_s2_tlbi_range);
+}
+
+/*
+ * Switch to a guest vttbr and clean the TLB for all the guest
+ * virtual address space.
+ */
+static void
+vmm_nvhe_s2_tlbi_all(uint64_t vttbr)
 {
vmm_call_hyp(HYP_S2_TLBI_ALL, vttbr);
 }
+
+DEFINE_IFUNC(, void, vmm_s2_tlbi_all, (uint64_t vttbr))
+{
+   if (in_vhe())
+   return (vmm_vhe_s2_tlbi_all);
+   return (vmm_nvhe_s2_tlbi_all);
+}

git: 53b8812c9a99 - main - arm64/vmm: Allow vmm when in VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=53b8812c9a997ef7e8879484890ef688bca4acdf

commit 53b8812c9a997ef7e8879484890ef688bca4acdf
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:46:00 +
Commit: Andrew Turner 
CommitDate: 2024-08-20 08:49:16 +

arm64/vmm: Allow vmm when in VHE

We now support VHE in byve so there is no reason to block it.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46085
---
 sys/arm64/vmm/vmm_arm64.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/sys/arm64/vmm/vmm_arm64.c b/sys/arm64/vmm/vmm_arm64.c
index 3079353668e3..164ff65cfe2c 100644
--- a/sys/arm64/vmm/vmm_arm64.c
+++ b/sys/arm64/vmm/vmm_arm64.c
@@ -246,12 +246,6 @@ vmmops_modinit(int ipinum)
return (ENXIO);
}
 
-   /* TODO: Support VHE */
-   if (in_vhe()) {
-   printf("vmm: VHE is unsupported\n");
-   return (ENXIO);
-   }
-
if (!vgic_present()) {
printf("vmm: No vgic found\n");
return (ENODEV);

git: db6e3260a8b9 - main - arm64: Remove the E2H check from has_hyp

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=db6e3260a8b9257aa4f1991867e46973e4f0dce8

commit db6e3260a8b9257aa4f1991867e46973e4f0dce8
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:46:05 +
Commit: Andrew Turner 
CommitDate: 2024-08-21 08:46:59 +

arm64: Remove the E2H check from has_hyp

This was added to not use the physical timer when E2H was set. As we
now use the correct timer in this case we can remove this extra check.

Tested by:  kevans
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46086
---
 sys/arm64/arm64/genassym.c  | 1 -
 sys/arm64/arm64/locore.S| 1 -
 sys/arm64/arm64/machdep.c   | 9 +
 sys/arm64/include/machdep.h | 1 -
 4 files changed, 1 insertion(+), 11 deletions(-)

diff --git a/sys/arm64/arm64/genassym.c b/sys/arm64/arm64/genassym.c
index c4f52ae61a77..a4db825e976c 100644
--- a/sys/arm64/arm64/genassym.c
+++ b/sys/arm64/arm64/genassym.c
@@ -42,7 +42,6 @@ ASSYM(BP_MODULEP, offsetof(struct arm64_bootparams, modulep));
 ASSYM(BP_KERN_STACK, offsetof(struct arm64_bootparams, kern_stack));
 ASSYM(BP_KERN_TTBR0, offsetof(struct arm64_bootparams, kern_ttbr0));
 ASSYM(BP_BOOT_EL, offsetof(struct arm64_bootparams, boot_el));
-ASSYM(BP_HCR_EL2, offsetof(struct arm64_bootparams, hcr_el2));
 
 ASSYM(PCPU_SIZE, sizeof(struct pcpu));
 ASSYM(PC_CURPCB, offsetof(struct pcpu, pc_curpcb));
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 4252ea3f59f8..ab1fea0c4716 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -134,7 +134,6 @@ virtdone:
str x25, [x0, #BP_KERN_STACK]
str x27, [x0, #BP_KERN_TTBR0]
str x23, [x0, #BP_BOOT_EL]
-   str x4,  [x0, #BP_HCR_EL2]
 
 #ifdef KASAN
/* Save bootparams */
diff --git a/sys/arm64/arm64/machdep.c b/sys/arm64/arm64/machdep.c
index 090ea2c10853..c73c6d205c1a 100644
--- a/sys/arm64/arm64/machdep.c
+++ b/sys/arm64/arm64/machdep.c
@@ -131,7 +131,6 @@ static struct trapframe proc0_tf;
 int early_boot = 1;
 int cold = 1;
 static int boot_el;
-static uint64_t hcr_el2;
 
 struct kva_md_info kmi;
 
@@ -207,12 +206,7 @@ pan_enable(void)
 bool
 has_hyp(void)
 {
-
-   /*
-* XXX The E2H check is wrong, but it's close enough for now.  Needs to
-* be re-evaluated once we're running regularly in EL2.
-*/
-   return (boot_el == CURRENTEL_EL_EL2 && (hcr_el2 & HCR_E2H) == 0);
+   return (boot_el == CURRENTEL_EL_EL2);
 }
 
 bool
@@ -905,7 +899,6 @@ initarm(struct arm64_bootparams *abp)
TSRAW(&thread0, TS_ENTER, __func__, NULL);
 
boot_el = abp->boot_el;
-   hcr_el2 = abp->hcr_el2;
 
/* Parse loader or FDT boot parametes. Determine last used address. */
lastaddr = parse_boot_param(abp);
diff --git a/sys/arm64/include/machdep.h b/sys/arm64/include/machdep.h
index 2f2960ae39f2..4fa80219da42 100644
--- a/sys/arm64/include/machdep.h
+++ b/sys/arm64/include/machdep.h
@@ -33,7 +33,6 @@ struct arm64_bootparams {
vm_offset_t modulep;
vm_offset_t kern_stack;
vm_paddr_t  kern_ttbr0;
-   uint64_thcr_el2;
int boot_el;/* EL the kernel booted from */
int pad;
 };

git: 0054693392f0 - main - arm64: Boot into VHE mode when able

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=0054693392f094c035fd396db339b8ceb16f17dd

commit 0054693392f094c035fd396db339b8ceb16f17dd
Author: Andrew Turner 
AuthorDate: 2024-08-19 12:46:10 +
Commit: Andrew Turner 
CommitDate: 2024-08-21 08:46:59 +

arm64: Boot into VHE mode when able

When FEAT_VHE is present the HCR_EL2 E2H field will be implemented. Try
setting this and checking if it's still set to decide if we can boot
into VHE mode or not.

When it is implemented the kernel will boot into EL2 rather than EL1
it currently boots to. The parts of the kernel that need to know if
they are in EL1 or EL2 have been updated other than the CoreSight
driver as there doesn't appear to be any way to currently use it and
it will be updated soon with the new HWT framework.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46087
---
 sys/arm64/arm64/locore.S | 65 +---
 1 file changed, 40 insertions(+), 25 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index ab1fea0c4716..b71e02538716 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -296,8 +296,12 @@ LEND(mpentry_common)
 #endif
 
 /*
- * If we are started in EL2, configure the required hypervisor
- * registers and drop to EL1.
+ * Enter the exception level the kernel will use:
+ *
+ *  - If in EL1 continue in EL1
+ *  - If the CPU supports FEAT_VHE then set HCR_E2H and HCR_TGE and continue
+ *in EL2
+ *  - Configure EL2 to support running the kernel at EL1 and exit to that
  */
 LENTRY(enter_kernel_el)
 #defineINIT_SCTLR_EL1  (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_EIS | \
@@ -335,13 +339,14 @@ LENTRY(enter_kernel_el)
isb
 
/* Configure the Hypervisor */
-   ldr x2, =(HCR_RW | HCR_APK | HCR_API)
+   ldr x2, =(HCR_RW | HCR_APK | HCR_API | HCR_E2H)
msr hcr_el2, x2
 
/* Stash value of HCR_EL2 for later */
isb
mrs x4, hcr_el2
 
+
/* Load the Virtualization Process ID Register */
mrs x2, midr_el1
msr vpidr_el2, x2
@@ -354,41 +359,51 @@ LENTRY(enter_kernel_el)
ldr x2, =INIT_SCTLR_EL1
msr sctlr_el1, x2
 
+   /* Check if the E2H flag is set */
+   tst x4, #HCR_E2H
+   b.eq.Lno_vhe
+
/*
-* On some hardware, e.g., Apple M1, we can't clear E2H, so make sure we
-* don't trap to EL2 for SIMD register usage to have at least a
-* minimally usable system.
+* The kernel will be running in EL2, route exceptions here rather
+* than EL1.
 */
-   tst x4, #HCR_E2H
-   mov x3, #CPTR_RES1  /* HCR_E2H == 0 */
-   mov x5, #CPTR_FPEN  /* HCR_E2H == 1 */
-   cselx2, x3, x5, eq
+   orr x4, x4, #(HCR_TGE)
+   msr hcr_el2, x4
+   isb
+
+   msr SCTLR_EL12_REG, x2
+   ldr x2, =(CPTR_FPEN)
+   ldr x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
+   ldr x5, =(PSR_DAIF | PSR_M_EL2h)
+   b   .Ldone_vhe
+
+.Lno_vhe:
+   /* Hypervisor trap functions */
+   adrpx2, hyp_stub_vectors
+   add x2, x2, :lo12:hyp_stub_vectors
+   msr vbar_el2, x2
+
+   ldr x2, =(CPTR_RES1)
+   ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
+   ldr x5, =(PSR_DAIF | PSR_M_EL1h)
+
+.Ldone_vhe:
+
msr cptr_el2, x2
+   /* Enable access to the physical timers at EL1 */
+   msr cnthctl_el2, x3
+   /* Set the return PSTATE */
+   msr spsr_el2, x5
 
/* Don't trap to EL2 for CP15 traps */
msr hstr_el2, xzr
 
-   /* Enable access to the physical timers at EL1 */
-   tst x4, #HCR_E2H
-   ldr x3, =(CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN)
-   ldr x5, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
-   cselx2, x3, x5, eq
-   msr cnthctl_el2, x2
-
/* Set the counter offset to a known value */
msr cntvoff_el2, xzr
 
-   /* Hypervisor trap functions */
-   adrpx2, hyp_stub_vectors
-   add x2, x2, :lo12:hyp_stub_vectors
-   msr vbar_el2, x2
-
/* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */
msr vttbr_el2, xzr
 
-   mov x2, #(PSR_DAIF | PSR_M_EL1h)
-   msr spsr_el2, x2
-
/* Configure GICv3 CPU interface */
mrs x2, id_aa64pfr0_el1
/* Extract GIC bits from the register */

git: 78d69d0a3c7f - main - arm64: Fix the kernel with options VMM

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=78d69d0a3c7f17944a7ecb84509fca6d0aa8545e

commit 78d69d0a3c7f17944a7ecb84509fca6d0aa8545e
Author: Andrew Turner 
AuthorDate: 2024-08-21 09:06:57 +
Commit: Andrew Turner 
CommitDate: 2024-08-21 10:16:10 +

arm64: Fix the kernel with options VMM

 * We can build the non-VHE code with branch protection, it is already
   build as such in the module.
 * Use the correct file name for the non-VHE exception .o file.
---
 sys/conf/files.arm64 | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index b105ce873d24..1c863ff98998 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -125,13 +125,13 @@ arm64/vmm/vmm_reset.c 
optional vmm
 arm64/vmm/vmm_handlers.c   optional vmm
 arm64/vmm/vmm_call.S   optional vmm
 arm64/vmm/vmm_nvhe_exception.S optional vmm\
-   compile-with "${NOSAN_C:N-mbranch-protection*} -fpie" \
+   compile-with "${NOSAN_C} -fpie" \
no-obj
 arm64/vmm/vmm_nvhe.c   optional vmm\
-   compile-with "${NOSAN_C:N-mbranch-protection*} -fpie" \
+   compile-with "${NOSAN_C} -fpie" \
no-obj
 vmm_hyp_blob.elf.full  optional vmm\
-   dependency  "vmm_nvhe.o vmm_hyp_exception.o"
\
+   dependency  "vmm_nvhe.o vmm_nvhe_exception.o"   
\
compile-with"${SYSTEM_LD_BASECMD} -o ${.TARGET} ${.ALLSRC} 
--defsym=_start='0x0' --defsym=text_start='0x0'" \
no-obj no-implicit-rule
 vmm_hyp_blob.elf   optional vmm\

git: f1bc3750cf9a - main - arm64: Use store-pair to zero the kernel bss

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=f1bc3750cf9a6623b0c0861984ef2a8ac966a4e3

commit f1bc3750cf9a6623b0c0861984ef2a8ac966a4e3
Author: Andrew Turner 
AuthorDate: 2024-08-20 17:14:28 +
Commit: Andrew Turner 
CommitDate: 2024-08-21 10:16:10 +

arm64: Use store-pair to zero the kernel bss

While this won't be noticed by most users the time to zero the bss
while using instruction tracing in the Arm FVP models (simulators) is
noticeable.

Reduce this time by using a store-pair instruction to double the size
of memory we zero on each iteration of the loop.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D42733
---
 sys/arm64/arm64/locore.S | 2 +-
 sys/conf/ldscript.arm64  | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index b71e02538716..ae1a005fd68f 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -111,7 +111,7 @@ virtdone:
ldr x15, .Lbss
ldr x14, .Lend
 1:
-   str xzr, [x15], #8
+   stp xzr, xzr, [x15], #16
cmp x15, x14
b.lo1b
 
diff --git a/sys/conf/ldscript.arm64 b/sys/conf/ldscript.arm64
index ea52a3128527..32af035105d0 100644
--- a/sys/conf/ldscript.arm64
+++ b/sys/conf/ldscript.arm64
@@ -121,6 +121,7 @@ SECTIONS
   .sdata : { *(.sdata) }
   _edata  =  .;
   PROVIDE (edata = .);
+  . = ALIGN(16);
   __bss_start = .;
   .sbss  : { *(.sbss) *(.scommon) }
   .bss   :
@@ -128,7 +129,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
-   . = ALIGN(8);
+   . = ALIGN(16);
__bss_end = .;
/* A section for the initial page table, it doesn't need to be in the
   kernel file, however unlike normal .bss entries should not be zeroed

git: 024248c933c5 - main - libc/aarch64: Remove an unneeded weak symbol

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=024248c933c5741a21c17eda63092f330dd98337

commit 024248c933c5741a21c17eda63092f330dd98337
Author: Andrew Turner 
AuthorDate: 2024-01-02 16:32:08 +
Commit: Andrew Turner 
CommitDate: 2024-08-21 10:16:10 +

libc/aarch64: Remove an unneeded weak symbol

The index symbol doesn't belong in memcpy.S as it is already in
strchr.S where it belongs.

Sponsored by:   Arm Ltd
---
 lib/libc/aarch64/string/memcpy.S | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/lib/libc/aarch64/string/memcpy.S b/lib/libc/aarch64/string/memcpy.S
index ac4fbe8d6175..f403dd2e42a8 100644
--- a/lib/libc/aarch64/string/memcpy.S
+++ b/lib/libc/aarch64/string/memcpy.S
@@ -1,6 +1,3 @@
 #define__memcpy_aarch64memcpy
 #define__memmove_aarch64   memmove
 #include "aarch64/memcpy.S"
-
-.weak index
-.equ index, strchr

git: 8b017284319c - main - arm64: Fix the ESR_EL1_op2 value

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=8b017284319c46d349abee5573d4656bb377b0fd

commit 8b017284319c46d349abee5573d4656bb377b0fd
Author: Andrew Turner 
AuthorDate: 2024-08-29 08:51:30 +
Commit: Andrew Turner 
CommitDate: 2024-08-29 10:42:34 +

arm64: Fix the ESR_EL1_op2 value

This leads to an unallocated register. Fix the value to point to
ESR_EL1.

Sponsored by:   Arm Ltd
---
 sys/arm64/include/armreg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index ce21bf4de0a9..a04afd57585c 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -676,7 +676,7 @@
 #defineESR_EL1_op1 0
 #defineESR_EL1_CRn 5
 #defineESR_EL1_CRm 2
-#defineESR_EL1_op2 1
+#defineESR_EL1_op2 0
 
 /* ESR_EL12 */
 #defineESR_EL12_REGMRS_REG_ALT_NAME(ESR_EL12)

Re: git: 43e8849bc294 - main - conf: Enable BTI checking in the arm64 kernel

[Andrew Turner]

> On 29 Aug 2024, at 17:02, Jessica Clarke  wrote:
> 
> On 21 Aug 2024, at 15:28, John Baldwin  wrote:
>> 
>> On 8/20/24 05:02, Andrew Turner wrote:
>>> The branch main has been updated by andrew:
>>> URL: 
>>> https://cgit.FreeBSD.org/src/commit/?id=43e8849bc29414036ccaef7788de95a07ad32ab5
>>> commit 43e8849bc29414036ccaef7788de95a07ad32ab5
>>> Author: Andrew Turner 
>>> AuthorDate: 2024-08-19 12:59:49 +
>>> Commit: Andrew Turner 
>>> CommitDate: 2024-08-20 08:49:15 +
>>>conf: Enable BTI checking in the arm64 kernel
>>> To ensure new code has BTI support make it an error to not have the
>>>BTI ELF note when linking the kernel and kernel modules.
>>> Reviewed by:kib, emaste
>>>Sponsored by:   Arm Ltd
>>>Differential Revision:  https://reviews.freebsd.org/D45469
>> 
>> This has broken two of the GitHub CI actions using clang 12 and clang 13.
>> Please fix this to be conditional on a supported linker version (or perhaps
>> add a new linker feature to bsd.linker.mk).
> 
> This is still broken. If it’s not fixed promptly I will just revert
> this change; we can’t leave CI broken, especially when it gets used to
> test GitHub PRs. Please stop breaking building with older toolchains,
> this isn’t the first time it’s happened.

See https://github.com/freebsd/freebsd-src/pull/1393 and 
https://github.com/freebsd/freebsd-src/pull/1399

Andrew

git: 973bbdab4703 - main - mk: Add a BTI-report linker feature

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=973bbdab47035ebd16200c63d095904924dc44d9

commit 973bbdab47035ebd16200c63d095904924dc44d9
Author: Jose Luis Duran 
AuthorDate: 2024-08-22 03:23:59 +
Commit: Andrew Turner 
CommitDate: 2024-08-30 16:03:17 +

mk: Add a BTI-report linker feature

Add support for specifying how to report the missing Branch Target
Identification (BTI) linker feature on AArch64.

For:

Kernel:bti-report on when the linker supports it
Userspace: bti-report on when the linker supports it and
   BTI_REPORT_ERROR is defined

Fixes:  43e8849bc294 ("conf: Enable BTI checking in the arm64 kernel")
Pull Request:   https://github.com/freebsd/freebsd-src/pull/1393
---
 share/mk/bsd.lib.mk|  2 +-
 share/mk/bsd.linker.mk | 11 ---
 share/mk/bsd.prog.mk   |  2 +-
 sys/conf/kern.mk   |  2 +-
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/share/mk/bsd.lib.mk b/share/mk/bsd.lib.mk
index 575b521bea55..6e288b9cd4ce 100644
--- a/share/mk/bsd.lib.mk
+++ b/share/mk/bsd.lib.mk
@@ -99,7 +99,7 @@ LDFLAGS+= -Wl,-zretpolineplt
 LDFLAGS.bfd+= -Wl,-znoexecstack
 .if ${MK_BRANCH_PROTECTION} != "no"
 CFLAGS+=  -mbranch-protection=standard
-.if ${MACHINE_ARCH} == "aarch64" && defined(BTI_REPORT_ERROR)
+.if ${LINKER_FEATURES:Mbti-report} && defined(BTI_REPORT_ERROR)
 LDFLAGS+= -Wl,-zbti-report=error
 .endif
 .endif
diff --git a/share/mk/bsd.linker.mk b/share/mk/bsd.linker.mk
index 0e9477284ea3..cceeadd05b94 100644
--- a/share/mk/bsd.linker.mk
+++ b/share/mk/bsd.linker.mk
@@ -11,9 +11,11 @@
 # LINKER_FEATURES may contain one or more of the following, based on
 # linker support for that feature:
 #
-# - build-id:  support for generating a Build-ID note
-# - retpoline: support for generating PLT with retpoline speculative
-#  execution vulnerability mitigation
+# - build-id:   support for generating a Build-ID note
+# - retpoline:  support for generating PLT with retpoline speculative
+#   execution vulnerability mitigation
+# - bti-report: support for specifying how to report the missing
+#   Branch Target Identification (BTI) property (AArch64)
 #
 # LINKER_FREEBSD_VERSION is the linker's internal source version.
 #
@@ -112,6 +114,9 @@ ${X_}LINKER_FEATURES+=  retpoline
 .if ${${X_}LINKER_TYPE} == "lld" && ${${X_}LINKER_VERSION} >= 9
 ${X_}LINKER_FEATURES+= ifunc-noplt
 .endif
+.if ${${X_}LINKER_TYPE} == "lld" && ${${X_}LINKER_VERSION} >= 14
+${X_}LINKER_FEATURES+= bti-report
+.endif
 .endif
 .else
 # Use LD's values
diff --git a/share/mk/bsd.prog.mk b/share/mk/bsd.prog.mk
index 74a653057bda..89534b21d0e7 100644
--- a/share/mk/bsd.prog.mk
+++ b/share/mk/bsd.prog.mk
@@ -71,7 +71,7 @@ LDFLAGS+= -Wl,-zretpolineplt
 LDFLAGS.bfd+= -Wl,-znoexecstack
 .if ${MK_BRANCH_PROTECTION} != "no"
 CFLAGS+=  -mbranch-protection=standard
-.if ${MACHINE_ARCH} == "aarch64" && defined(BTI_REPORT_ERROR)
+.if ${LINKER_FEATURES:Mbti-report} && defined(BTI_REPORT_ERROR)
 LDFLAGS+= -Wl,-zbti-report=error
 .endif
 .endif
diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk
index 079bd1173fad..00492584921b 100644
--- a/sys/conf/kern.mk
+++ b/sys/conf/kern.mk
@@ -143,7 +143,7 @@ CFLAGS += -mgeneral-regs-only
 CFLAGS += -ffixed-x18
 # Build with BTI+PAC
 CFLAGS += -mbranch-protection=standard
-.if ${LINKER_TYPE} == "lld"
+.if ${LINKER_FEATURES:Mbti-report}
 LDFLAGS += -Wl,-zbti-report=error
 .endif
 # TODO: support outline atomics

git: 7be11454edd4 - main - arm64: Add the tcr_el2 ds field

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7be11454edd4eca6cbd299cb5b486294f912ffbd

commit 7be11454edd4eca6cbd299cb5b486294f912ffbd
Author: Andrew Turner 
AuthorDate: 2024-09-05 12:11:42 +
Commit: Andrew Turner 
CommitDate: 2024-09-05 12:12:16 +

arm64: Add the tcr_el2 ds field

This will be used to support FEAT_LPA2 to allow more than 48 bits of
physical address space.

Reviewed by:alc, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46392
---
 sys/arm64/include/armreg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index a04afd57585c..b4adc3d2c254 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2444,6 +2444,8 @@
 #defineTCR_EL1_CRm 0
 #defineTCR_EL1_op2 2
 /* Bits 63:59 are reserved */
+#defineTCR_DS_SHIFT59
+#defineTCR_DS  (UL(1) << TCR_DS_SHIFT)
 #defineTCR_TCMA1_SHIFT 58
 #defineTCR_TCMA1   (UL(1) << TCR_TCMA1_SHIFT)
 #defineTCR_TCMA0_SHIFT 57

git: 3a3aa2cc0756 - main - arm64: Remove TCR_CACHE_ATTRS and TCR_SMP_ATTRS

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=3a3aa2cc07563e288950affbda6b743487e9d49d

commit 3a3aa2cc07563e288950affbda6b743487e9d49d
Author: Andrew Turner 
AuthorDate: 2024-09-05 12:11:48 +
Commit: Andrew Turner 
CommitDate: 2024-09-05 12:12:16 +

arm64: Remove TCR_CACHE_ATTRS and TCR_SMP_ATTRS

These are only used in one place so expand them there.

While here always set TCR_SH0_IS and TCR_SH1_IS. There is no advantage
to not set them in a UP kernel.

Reviewed by:alc, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46393
---
 sys/arm64/arm64/locore.S   | 5 +++--
 sys/arm64/include/armreg.h | 8 
 2 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index ae1a005fd68f..daf8a936eda2 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -945,8 +945,9 @@ tcr:
 #error Unsupported page size
 #endif
 
-   .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG | \
-   TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
+   .quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_TG |  \
+   TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA |  \
+   TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA)
 sctlr_set:
/* Bits to set */
.quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index b4adc3d2c254..54600d63891e 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -2543,14 +2543,6 @@
 #defineTCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
 #defineTCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
 
-#defineTCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
-   (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
-#ifdef SMP
-#defineTCR_SMP_ATTRS   (TCR_SH0_IS | TCR_SH1_IS)
-#else
-#defineTCR_SMP_ATTRS   0
-#endif
-
 /* TCR_EL12 */
 #defineTCR_EL12_REGMRS_REG_ALT_NAME(TCR_EL12)
 #defineTCR_EL12_op03

git: e2990a9ee479 - main - arm64: Remove ATTR_DEFAULT from pte.h

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=e2990a9ee479b7d31bceb75310c0f290cdfb8504

commit e2990a9ee479b7d31bceb75310c0f290cdfb8504
Author: Andrew Turner 
AuthorDate: 2024-09-05 12:11:55 +
Commit: Andrew Turner 
CommitDate: 2024-09-05 12:12:17 +

arm64: Remove ATTR_DEFAULT from pte.h

ATTR_SH(ATTR_SH_IS) will soon be dynamic as the field is moved out of
the page tables in FEAT_LPA2. When this happens ATTR_DEFAULT will just
be ATTR_AF.

Rather than keeping ATTR_DEFAULT with one attribute remove it.

Reviewed by:alc, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46466
---
 sys/arm64/arm64/efirt_machdep.c|  2 +-
 sys/arm64/arm64/locore.S   |  4 +--
 sys/arm64/arm64/minidump_machdep.c |  6 ++---
 sys/arm64/arm64/pmap.c | 53 --
 sys/arm64/include/pte.h|  2 --
 sys/arm64/iommu/iommu_pmap.c   |  2 +-
 sys/arm64/vmm/vmm_mmu.c|  2 +-
 7 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/sys/arm64/arm64/efirt_machdep.c b/sys/arm64/arm64/efirt_machdep.c
index 0c46d2e6dcc6..7c1d12b0b9b4 100644
--- a/sys/arm64/arm64/efirt_machdep.c
+++ b/sys/arm64/arm64/efirt_machdep.c
@@ -214,7 +214,7 @@ efi_create_1t1_map(struct efi_md *map, int ndesc, int 
descsz)
p->md_phys, mode, p->md_pages);
}
 
-   l3_attr = ATTR_DEFAULT | ATTR_S1_IDX(mode) |
+   l3_attr = ATTR_AF | ATTR_SH(ATTR_SH_IS) | ATTR_S1_IDX(mode) |
ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_nG | L3_PAGE;
if (mode == VM_MEMATTR_DEVICE || p->md_attr & EFI_MD_ATTR_XP)
l3_attr |= ATTR_S1_XN;
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index daf8a936eda2..e37ea5aa3b48 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -747,7 +747,7 @@ LENTRY(build_l2_block_pagetable)
 
/* Build the L2 block entry */
orr x12, x7, #L2_BLOCK
-   orr x12, x12, #(ATTR_DEFAULT)
+   orr x12, x12, #(ATTR_AF | ATTR_SH(ATTR_SH_IS))
orr x12, x12, #(ATTR_S1_UXN)
 #ifdef __ARM_FEATURE_BTI_DEFAULT
orr x12, x12, #(ATTR_S1_GP)
@@ -823,7 +823,7 @@ LENTRY(build_l3_page_pagetable)
 
/* Build the L3 page entry */
orr x12, x7, #L3_PAGE
-   orr x12, x12, #(ATTR_DEFAULT)
+   orr x12, x12, #(ATTR_AF | ATTR_SH(ATTR_SH_IS))
orr x12, x12, #(ATTR_S1_UXN)
 #ifdef __ARM_FEATURE_BTI_DEFAULT
orr x12, x12, #(ATTR_S1_GP)
diff --git a/sys/arm64/arm64/minidump_machdep.c 
b/sys/arm64/arm64/minidump_machdep.c
index 8ee626953aef..ac0a2c2dc96e 100644
--- a/sys/arm64/arm64/minidump_machdep.c
+++ b/sys/arm64/arm64/minidump_machdep.c
@@ -310,8 +310,8 @@ cpu_minidumpsys(struct dumperinfo *di, const struct 
minidumpstate *state)
for (i = 0; i < Ln_ENTRIES; i++) {
for (j = 0; j < Ln_ENTRIES; j++) {
tmpbuffer[j] = (pa + i * L2_SIZE +
-   j * PAGE_SIZE) | ATTR_DEFAULT |
-   L3_PAGE;
+   j * PAGE_SIZE) | ATTR_AF |
+   ATTR_SH(ATTR_SH_IS) | L3_PAGE;
}
error = blk_write(di, (char *)&tmpbuffer, 0,
PAGE_SIZE);
@@ -330,7 +330,7 @@ cpu_minidumpsys(struct dumperinfo *di, const struct 
minidumpstate *state)
/* Generate fake l3 entries based upon the l1 entry */
for (i = 0; i < Ln_ENTRIES; i++) {
tmpbuffer[i] = (pa + i * PAGE_SIZE) |
-   ATTR_DEFAULT | L3_PAGE;
+   ATTR_AF | ATTR_SH(ATTR_SH_IS) | L3_PAGE;
}
error = blk_write(di, (char *)&tmpbuffer, 0, PAGE_SIZE);
if (error)
diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
index 224ecbdc4577..5f09f4cbcf1b 100644
--- a/sys/arm64/arm64/pmap.c
+++ b/sys/arm64/arm64/pmap.c
@@ -185,8 +185,8 @@
 #else
 #defineATTR_KERN_GP0
 #endif
-#definePMAP_SAN_PTE_BITS   (ATTR_DEFAULT | ATTR_S1_XN | 
ATTR_KERN_GP | \
-   ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | ATTR_S1_AP(ATTR_S1_AP_RW))
+#definePMAP_SAN_PTE_BITS   (ATTR_AF | ATTR_SH(ATTR_SH_IS) | 
ATTR_S1_XN | \
+  ATTR_KERN_GP | ATTR_S1_IDX(VM_MEMATTR_WRITE_BACK) | 
ATTR_S1_AP(ATTR_S1_AP_RW))
 
 struct pmap_large_md_page {
struct rwlock   pv_lock;
@@ -1150,7 +1150,7 @@ pmap_bootstrap_l2_block(struct pmap_bootstrap_state 
*state, int i)
MPASS((state->pa & L2

git: d52c31904218 - main - arm64: Make shareability attributes dynamic

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d52c31904218c79424435b69b9ec4098885d800f

commit d52c31904218c79424435b69b9ec4098885d800f
Author: Andrew Turner 
AuthorDate: 2024-09-05 12:12:04 +
Commit: Andrew Turner 
CommitDate: 2024-09-05 12:12:17 +

arm64: Make shareability attributes dynamic

When LPA2 is enabled the shareability attribute in the page table are
replaces with output address bits. To support a larger physical address
space make this attribute dynamic so we only set it when appropriate.

Reviewed by:alc, kib
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46394
---
 sys/arm64/arm64/efirt_machdep.c|  2 +-
 sys/arm64/arm64/locore.S   | 44 --
 sys/arm64/arm64/minidump_machdep.c |  4 ++--
 sys/arm64/arm64/pmap.c | 24 +++--
 sys/arm64/include/hypervisor.h |  2 ++
 sys/arm64/include/pmap.h   |  2 ++
 sys/arm64/vmm/vmm_arm64.c  |  8 +++
 7 files changed, 70 insertions(+), 16 deletions(-)

diff --git a/sys/arm64/arm64/efirt_machdep.c b/sys/arm64/arm64/efirt_machdep.c
index 7c1d12b0b9b4..47e0a209d8b1 100644
--- a/sys/arm64/arm64/efirt_machdep.c
+++ b/sys/arm64/arm64/efirt_machdep.c
@@ -214,7 +214,7 @@ efi_create_1t1_map(struct efi_md *map, int ndesc, int 
descsz)
p->md_phys, mode, p->md_pages);
}
 
-   l3_attr = ATTR_AF | ATTR_SH(ATTR_SH_IS) | ATTR_S1_IDX(mode) |
+   l3_attr = ATTR_AF | pmap_sh_attr | ATTR_S1_IDX(mode) |
ATTR_S1_AP(ATTR_S1_AP_RW) | ATTR_S1_nG | L3_PAGE;
if (mode == VM_MEMATTR_DEVICE || p->md_attr & EFI_MD_ATTR_XP)
l3_attr |= ATTR_S1_XN;
diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index e37ea5aa3b48..7c60a2c5bf0a 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -86,6 +86,7 @@ ENTRY(_start)
 * x27 = TTBR0 table
 * x26 = Kernel L1 table
 * x24 = TTBR1 table
+* x22 = PTE shareability attributes
 */
 
/* Enable the mmu */
@@ -135,6 +136,10 @@ virtdone:
str x27, [x0, #BP_KERN_TTBR0]
str x23, [x0, #BP_BOOT_EL]
 
+   /* Set this before it's used in kasan_init_early */
+   adrpx1, pmap_sh_attr
+   str x22, [x1, :lo12:pmap_sh_attr]
+
 #ifdef KASAN
/* Save bootparams */
mov x19, x0
@@ -476,6 +481,30 @@ LENTRY(create_pagetables)
cmp x6, x27
b.lo1b
 
+   /*
+* Find the shareability attribute we should use. If FEAT_LPA2 is
+* enabled then the shareability field is moved from the page table
+* to tcr_el1 and the bits in the page table are reused by the
+* address field.
+*/
+#if PAGE_SIZE == PAGE_SIZE_4K
+#defineLPA2_MASK   ID_AA64MMFR0_TGran4_MASK
+#defineLPA2_VALID_AA64MMFR0_TGran4_LPA2
+#elif PAGE_SIZE == PAGE_SIZE_16K
+#defineLPA2_MASK   ID_AA64MMFR0_TGran16_MASK
+#defineLPA2_VALID_AA64MMFR0_TGran16_LPA2
+#else
+#error Unsupported page size
+#endif
+   mrs x6, id_aa64mmfr0_el1
+   mov x7, LPA2_VAL
+   and x6, x6, LPA2_MASK
+   cmp x6, x7
+   ldr x22, =(ATTR_SH(ATTR_SH_IS))
+   cselx22, xzr, x22, eq
+#undef LPA2_MASK
+#undef LPA2_VAL
+
/*
 * Build the TTBR1 maps.
 */
@@ -747,11 +776,13 @@ LENTRY(build_l2_block_pagetable)
 
/* Build the L2 block entry */
orr x12, x7, #L2_BLOCK
-   orr x12, x12, #(ATTR_AF | ATTR_SH(ATTR_SH_IS))
+   orr x12, x12, #(ATTR_AF)
orr x12, x12, #(ATTR_S1_UXN)
 #ifdef __ARM_FEATURE_BTI_DEFAULT
orr x12, x12, #(ATTR_S1_GP)
 #endif
+   /* Set the shareability attribute */
+   orr x12, x12, x22
 
/* Only use the output address bits */
lsr x9, x9, #L2_SHIFT
@@ -823,11 +854,13 @@ LENTRY(build_l3_page_pagetable)
 
/* Build the L3 page entry */
orr x12, x7, #L3_PAGE
-   orr x12, x12, #(ATTR_AF | ATTR_SH(ATTR_SH_IS))
+   orr x12, x12, #(ATTR_AF)
orr x12, x12, #(ATTR_S1_UXN)
 #ifdef __ARM_FEATURE_BTI_DEFAULT
orr x12, x12, #(ATTR_S1_GP)
 #endif
+   /* Set the shareability attribute */
+   orr x12, x12, x22
 
/* Only use the output address bits */
lsr x9, x9, #L3_SHIFT
@@ -886,6 +919,13 @@ LENTRY(start_mmu)
 * to 1 only if the ASIDBits field equals 0b0010.
 */
ldr x2, tcr
+
+   /* If x22 contains a non-zero value then LPA2 is not implemented */
+   cbnzx22, .Lno_lpa2
+   ldr x3, =(TCR_DS)
+   orr x2, x2, x3
+.Lno_lpa2:
+
mrs x3, id_aa64mmfr0_el1
 
/* Copy the bottom 3 bits from id_aa64mmfr0_el1 into TCR.IPS *

git: 31ca046e2250 - main - arm: Only define get_cntxct_a64_unstable when used

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=31ca046e2250e30cb92a546ecad7ec07e4b016ca

commit 31ca046e2250e30cb92a546ecad7ec07e4b016ca
Author: Andrew Turner 
AuthorDate: 2024-09-09 13:15:39 +
Commit: Andrew Turner 
CommitDate: 2024-09-09 13:15:39 +

arm: Only define get_cntxct_a64_unstable when used

When building an ACPI only kernel get_cntxct_a64_unstable in the Arm
generic tiner driver is unused. Add an #ifdef FDT check around it.

Sponsored by:   Arm Ltd
---
 sys/arm/arm/generic_timer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/arm/arm/generic_timer.c b/sys/arm/arm/generic_timer.c
index d3e264527a7f..9b5f0f52368b 100644
--- a/sys/arm/arm/generic_timer.c
+++ b/sys/arm/arm/generic_timer.c
@@ -187,6 +187,7 @@ get_freq(void)
return (get_el0(cntfrq));
 }
 
+#ifdef FDT
 static uint64_t
 get_cntxct_a64_unstable(bool physical)
 {
@@ -208,6 +209,7 @@ get_cntxct_a64_unstable(bool physical)
 
return (val);
 }
+#endif
 
 static uint64_t
 get_cntxct(bool physical)

git: ecde7bb28567 - main - arm64/vmm: Fix when VMM is built into the kernel

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=ecde7bb2856722e493a3799e8498fe83b3b1ac2b

commit ecde7bb2856722e493a3799e8498fe83b3b1ac2b
Author: Andrew Turner 
AuthorDate: 2024-09-09 13:15:42 +
Commit: Andrew Turner 
CommitDate: 2024-09-09 13:15:42 +

arm64/vmm: Fix when VMM is built into the kernel

Sponsored by:   Arm Ltd
---
 sys/conf/files.arm64 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 4cfe87f5a508..fc7c770683fe 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -117,7 +117,7 @@ dev/iommu/busdma_iommu.coptional iommu
 dev/iommu/iommu_gas.c  optional iommu
 
 arm64/vmm/vmm.coptional vmm
-arm64/vmm/vmm_dev.coptional vmm
+arm64/vmm/vmm_dev_machdep.coptional vmm
 arm64/vmm/vmm_instruction_emul.c   optional vmm
 arm64/vmm/vmm_arm64.c  optional vmm
 arm64/vmm/vmm_reset.c  optional vmm

git: 33ba37525b1d - main - sys/conf: Check for FDT in FDT only files

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=33ba37525b1d3f6ef21e6aadc089e67e30e06264

commit 33ba37525b1d3f6ef21e6aadc089e67e30e06264
Author: Andrew Turner 
AuthorDate: 2024-09-09 13:15:44 +
Commit: Andrew Turner 
CommitDate: 2024-09-09 13:15:44 +

sys/conf: Check for FDT in FDT only files

Fix the arm64 ACPI only build by adding FDT checks to files.arm64.

Sponsored by:   Arm Ltd
---
 sys/conf/files.arm64 | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index fc7c770683fe..cd161a18500f 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -599,10 +599,10 @@ arm64/freescale/imx/clk/imx_clk_frac_pll.c
optional fdt soc_freescale_imx8
 
 # iMX drivers
 arm/freescale/imx/imx_gpio.c   optional gpio 
soc_freescale_imx8 fdt
-arm/freescale/imx/imx_i2c.coptional fsliic
+arm/freescale/imx/imx_i2c.coptional fdt fsliic
 arm/freescale/imx/imx_machdep.coptional fdt 
soc_freescale_imx8
 arm64/freescale/imx/imx7gpc.c  optional fdt soc_freescale_imx8
-dev/ffec/if_ffec.c optional ffec
+dev/ffec/if_ffec.c optional fdt ffec
 
 # Marvell
 arm/mv/a37x0_gpio.coptional a37x0_gpio gpio fdt

git: f05795e3f65f - main - arm64: write PID in CONTEXTIDR_EL1 on ctx switch

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=f05795e3f65f305cb770ae91d8e9c8f05d267e0d

commit f05795e3f65f305cb770ae91d8e9c8f05d267e0d
Author: Zachary Leaf 
AuthorDate: 2024-07-31 08:23:24 +
Commit: Andrew Turner 
CommitDate: 2024-09-09 16:03:19 +

arm64: write PID in CONTEXTIDR_EL1 on ctx switch

Debug and trace features such as Statistical Profiling Extension (SPE)
use the CONTEXTIDR_EL1 register to get the PID of the current process.

Add a sysctl switch to toggle writing the current PID into this register
in the thread switcher.

To make use of the feature, the following sysctl switch must be set:

sysctl machdep.pid_in_contextidr=1

Kernel code can also toggle the sysctl by writing directly to the global
var behind the sysctl arm64_pid_in_contextidr:

extern bool arm64_pid_in_contextidr;

Reviewed by:andrew
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46192
---
 sys/arm64/arm64/genassym.c|  2 ++
 sys/arm64/arm64/swtch.S   | 17 +
 sys/arm64/arm64/sys_machdep.c |  6 ++
 3 files changed, 25 insertions(+)

diff --git a/sys/arm64/arm64/genassym.c b/sys/arm64/arm64/genassym.c
index a4db825e976c..5a20169d51c3 100644
--- a/sys/arm64/arm64/genassym.c
+++ b/sys/arm64/arm64/genassym.c
@@ -58,6 +58,8 @@ ASSYM(PCB_TPIDRRO, offsetof(struct pcb, pcb_tpidrro_el0));
 ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
 ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
 
+ASSYM(PR_PID, offsetof(struct proc, p_pid));
+
 ASSYM(SF_UC, offsetof(struct sigframe, sf_uc));
 
 ASSYM(TD_PROC, offsetof(struct thread, td_proc));
diff --git a/sys/arm64/arm64/swtch.S b/sys/arm64/arm64/swtch.S
index 6af70ca839a0..3a2bf2cb5a7f 100644
--- a/sys/arm64/arm64/swtch.S
+++ b/sys/arm64/arm64/swtch.S
@@ -55,6 +55,15 @@
 999:
 .endm
 
+.macro pid_in_context_idr label
+   adrpx9, arm64_pid_in_contextidr
+   ldr x10, [x9, :lo12:arm64_pid_in_contextidr]
+   cbz x10, \label
+   ldr x9, [x1, #TD_PROC]
+   ldr x10, [x9, #PR_PID]
+   msr contextidr_el1, x10
+.endm
+
 /*
  * void cpu_throw(struct thread *old, struct thread *new)
  */
@@ -66,8 +75,12 @@ ENTRY(cpu_throw)
ldr x4, [x0, #TD_PCB]
ldr w5, [x4, #PCB_FLAGS]
clear_step_flag w5, x6
+
 1:
+   /* debug/trace: set CONTEXTIDR_EL1 to current PID, if enabled */
+   pid_in_context_idr 2f
 
+2:
 #ifdef VFP
/* Backup the new thread pointer around a call to C code */
mov x19, x1
@@ -147,6 +160,10 @@ ENTRY(cpu_switch)
mov x20, x1
mov x21, x2
 
+   /* debug/trace: set CONTEXTIDR_EL1 to current PID, if enabled */
+   pid_in_context_idr 0f
+
+0:
 #ifdef VFP
bl  vfp_save_state_switch
mov x0, x20
diff --git a/sys/arm64/arm64/sys_machdep.c b/sys/arm64/arm64/sys_machdep.c
index eedc57f7c572..eedee1d27015 100644
--- a/sys/arm64/arm64/sys_machdep.c
+++ b/sys/arm64/arm64/sys_machdep.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -80,3 +81,8 @@ sysarch(struct thread *td, struct sysarch_args *uap)
 
return (error);
 }
+
+bool arm64_pid_in_contextidr = false;
+SYSCTL_BOOL(_machdep, OID_AUTO, pid_in_contextidr, CTLFLAG_RW,
+&arm64_pid_in_contextidr, false,
+"Save PID into CONTEXTIDR_EL1 register on context switch");

git: 610348a90467 - main - arm64: add additional MDCR_EL2 fields

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=610348a90467980de0498fab8dfdddf221d7a604

commit 610348a90467980de0498fab8dfdddf221d7a604
Author: Zachary Leaf 
AuthorDate: 2024-07-03 07:26:34 +
Commit: Andrew Turner 
CommitDate: 2024-09-09 15:56:53 +

arm64: add additional MDCR_EL2 fields

Monitor Debug Configuration Register provides EL2 configuration options
for self-hosted debug and the Performance Monitors Extension.

Reviewed by:andrew
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46191
---
 sys/arm64/include/hypervisor.h | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 1a27a8dd919b..499dba9092fc 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -267,5 +267,35 @@
 #defineMDCR_EL2_TDOSA  (0x1UL << MDCR_EL2_TDOSA_SHIFT)
 #defineMDCR_EL2_TDRA_SHIFT 11
 #defineMDCR_EL2_TDRA   (0x1UL << MDCR_EL2_TDRA_SHIFT)
+#defineMDCR_E2PB_SHIFT 12
+#defineMDCR_E2PB_MASK  (0x3UL << MDCR_E2PB_SHIFT)
+#defineMDCR_TPMS_SHIFT 14
+#defineMDCR_TPMS   (0x1UL << MDCR_TPMS_SHIFT)
+#defineMDCR_EnSPM_SHIFT15
+#defineMDCR_EnSPM  (0x1UL << MDCR_EnSPM_SHIFT)
+#defineMDCR_HPMD_SHIFT 17
+#defineMDCR_HPMD   (0x1UL << MDCR_HPMD_SHIFT)
+#defineMDCR_TTRF_SHIFT 19
+#defineMDCR_TTRF   (0x1UL << MDCR_TTRF_SHIFT)
+#defineMDCR_HCCD_SHIFT 23
+#defineMDCR_HCCD   (0x1UL << MDCR_HCCD_SHIFT)
+#defineMDCR_E2TB_SHIFT 24
+#defineMDCR_E2TB_MASK  (0x3UL << MDCR_E2TB_SHIFT)
+#defineMDCR_HLP_SHIFT  26
+#defineMDCR_HLP(0x1UL << MDCR_HLP_SHIFT)
+#defineMDCR_TDCC_SHIFT 27
+#defineMDCR_TDCC   (0x1UL << MDCR_TDCC_SHIFT)
+#defineMDCR_MTPME_SHIFT28
+#defineMDCR_MTPME  (0x1UL << MDCR_MTPME_SHIFT)
+#defineMDCR_HPMFZO_SHIFT   29
+#defineMDCR_HPMFZO (0x1UL << MDCR_HPMFZO_SHIFT)
+#defineMDCR_PMSSE_SHIFT30
+#defineMDCR_PMSSE_MASK (0x3UL << MDCR_PMSSE_SHIFT)
+#defineMDCR_HPMFZS_SHIFT   36
+#defineMDCR_HPMFZS (0x1UL << MDCR_HPMFZS_SHIFT)
+#defineMDCR_PMEE_SHIFT 40
+#defineMDCR_PMEE_MASK  (0x3UL << MDCR_PMEE_SHIFT)
+#defineMDCR_EBWE_SHIFT 43
+#defineMDCR_EBWE   (0x1UL << MDCR_EBWE_SHIFT)
 
 #endif /* !_MACHINE_HYPERVISOR_H_ */

git: d99e6b22c01f - main - arm64: Make L1_BLOCKS_SUPPORTED dynamic

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d99e6b22c01f335ea1b4ba3bc7311ed194b17086

commit d99e6b22c01f335ea1b4ba3bc7311ed194b17086
Author: Andrew Turner 
AuthorDate: 2024-09-11 09:36:39 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:08 +

arm64: Make L1_BLOCKS_SUPPORTED dynamic

When FEAT_LPA2 is implemented and the TCR_EL1.DS field is set we can
create blocks at level 1 with a 16kB page size. Add a variable to
tell the kernel this is enabled.

This will be used by other parts of pmap.c with a 4k page kernel so
make it visible there.

Reviewed by:alc, kib, markj
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46395
---
 sys/arm64/arm64/pmap.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c
index 2fd45bdb6b95..6f758b7ff10c 100644
--- a/sys/arm64/arm64/pmap.c
+++ b/sys/arm64/arm64/pmap.c
@@ -355,17 +355,19 @@ static u_int physmap_idx;
 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 "VM/pmap parameters");
 
+static bool pmap_lpa_enabled __read_mostly = false;
 pt_entry_t pmap_sh_attr __read_mostly = ATTR_SH(ATTR_SH_IS);
 
 #if PAGE_SIZE == PAGE_SIZE_4K
 #defineL1_BLOCKS_SUPPORTED 1
 #else
-/* TODO: Make this dynamic when we support FEAT_LPA2 (TCR_EL1.DS == 1) */
-#defineL1_BLOCKS_SUPPORTED 0
+#defineL1_BLOCKS_SUPPORTED (pmap_lpa_enabled)
 #endif
 
 #definePMAP_ASSERT_L1_BLOCKS_SUPPORTED MPASS(L1_BLOCKS_SUPPORTED)
 
+static bool pmap_l1_supported __read_mostly = false;
+
 /*
  * This ASID allocator uses a bit vector ("asid_set") to remember which ASIDs
  * that it has currently allocated to a pmap, a cursor ("asid_next") to
@@ -1306,10 +1308,17 @@ pmap_bootstrap(vm_size_t kernlen)
 {
vm_offset_t dpcpu, msgbufpv;
vm_paddr_t start_pa, pa;
+   uint64_t tcr;
+
+   tcr = READ_SPECIALREG(tcr_el1);
 
/* Verify that the ASID is set through TTBR0. */
-   KASSERT((READ_SPECIALREG(tcr_el1) & TCR_A1) == 0,
-   ("pmap_bootstrap: TCR_EL1.A1 != 0"));
+   KASSERT((tcr & TCR_A1) == 0, ("pmap_bootstrap: TCR_EL1.A1 != 0"));
+
+   if ((tcr & TCR_DS) != 0)
+   pmap_lpa_enabled = true;
+
+   pmap_l1_supported = L1_BLOCKS_SUPPORTED;
 
/* Set this early so we can use the pagetable walking functions */
kernel_pmap_store.pm_l0 = pagetable_l0_ttbr1;
@@ -1681,6 +1690,9 @@ static COUNTER_U64_DEFINE_EARLY(pmap_l1_demotions);
 SYSCTL_COUNTER_U64(_vm_pmap_l1, OID_AUTO, demotions, CTLFLAG_RD,
 &pmap_l1_demotions, "L1 (1GB/64GB) page demotions");
 
+SYSCTL_BOOL(_vm_pmap_l1, OID_AUTO, supported, CTLFLAG_RD, &pmap_l1_supported,
+0, "L1 blocks are supported");
+
 static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2c, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
 "L2C (32MB/1GB) page mapping counters");
 

git: 16e661921a9b - main - arm64: Add E2H to CPTR_EL2 register values

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=16e661921a9bbc6aab455c59da055b6f4ff75627

commit 16e661921a9bbc6aab455c59da055b6f4ff75627
Author: Andrew Turner 
AuthorDate: 2024-09-11 09:38:15 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:09 +

arm64: Add E2H to CPTR_EL2 register values

Rename register fields that are only valid when HCR_EL2.E2H == 1. Some
fields move around depending on the value of the E2H field.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46514
---
 sys/arm64/include/hypervisor.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 9f53c8255e49..ba18f8077467 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -57,7 +57,7 @@
 #defineCPTR_RES1   0x33ff
 #defineCPTR_TFP0x0400
 /* Valid if HCR_EL2.E2H == 1 */
-#defineCPTR_FPEN   0x0030
+#defineCPTR_E2H_FPEN   0x0030
 /* Unconditionally valid */
 #defineCPTR_TTA0x0010
 #defineCPTR_TCPAC  0x8000

git: 769eeb093254 - main - arm64: Trap floating-point registers with VHE

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=769eeb09325419ccbc7fbd1c22afc9b1e1e191f3

commit 769eeb09325419ccbc7fbd1c22afc9b1e1e191f3
Author: Andrew Turner 
AuthorDate: 2024-09-02 15:36:13 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:08 +

arm64: Trap floating-point registers with VHE

When VHE is enabled we disabled trapping floating-point instructions to
EL2 in locore.S. As the kernel is running in EL2 then vfp.c will manage
enabling floating-point instructions as needed.

Sponsored by:   Arm Ltd
---
 sys/arm64/arm64/locore.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 7c60a2c5bf0a..f9a179931d7d 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -377,7 +377,7 @@ LENTRY(enter_kernel_el)
isb
 
msr SCTLR_EL12_REG, x2
-   ldr x2, =(CPTR_FPEN)
+   mov x2, xzr /* CPTR_EL2 is managed by vfp.c */
ldr x3, =(CNTHCTL_E2H_EL1PCTEN | CNTHCTL_E2H_EL1PTEN)
ldr x5, =(PSR_DAIF | PSR_M_EL2h)
b   .Ldone_vhe

git: 9f3d15fda29a - main - arm64: Add CPTR_E2H_TTA

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=9f3d15fda29a9d510754daed8e6158c637108b42

commit 9f3d15fda29a9d510754daed8e6158c637108b42
Author: Andrew Turner 
AuthorDate: 2024-09-11 09:38:22 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:09 +

arm64: Add CPTR_E2H_TTA

The TTA field moves depending on the HCR_EL2.E2H field. Add a macro to
hold the E2H == 1 case.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46515
---
 sys/arm64/include/hypervisor.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index ba18f8077467..738eeca66ffe 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -56,10 +56,11 @@
 #defineCPTR_RES0   0x7fefc800
 #defineCPTR_RES1   0x33ff
 #defineCPTR_TFP0x0400
+#defineCPTR_TTA0x0010
 /* Valid if HCR_EL2.E2H == 1 */
 #defineCPTR_E2H_FPEN   0x0030
+#defineCPTR_E2H_TTA0x1000
 /* Unconditionally valid */
-#defineCPTR_TTA0x0010
 #defineCPTR_TCPAC  0x8000
 
 /* HCR_EL2 - Hypervisor Config Register */

git: 7a488d83b3af - main - arm64: Adjust the indentation of CPTR_EL2 values

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=7a488d83b3af4d59946319b251a3a2060f18df40

commit 7a488d83b3af4d59946319b251a3a2060f18df40
Author: Andrew Turner 
AuthorDate: 2024-09-11 09:38:08 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:08 +

arm64: Adjust the indentation of CPTR_EL2 values

Reviewed by:emaste
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46513
---
 sys/arm64/include/hypervisor.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 499dba9092fc..9f53c8255e49 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -53,14 +53,14 @@
 
 /* CPTR_EL2 - Architecture feature trap register */
 /* Valid if HCR_EL2.E2H == 0 */
-#defineCPTR_RES0   0x7fefc800
-#defineCPTR_RES1   0x33ff
-#defineCPTR_TFP0x0400
+#defineCPTR_RES0   0x7fefc800
+#defineCPTR_RES1   0x33ff
+#defineCPTR_TFP0x0400
 /* Valid if HCR_EL2.E2H == 1 */
-#defineCPTR_FPEN   0x0030
+#defineCPTR_FPEN   0x0030
 /* Unconditionally valid */
-#defineCPTR_TTA0x0010
-#defineCPTR_TCPAC  0x8000
+#defineCPTR_TTA0x0010
+#defineCPTR_TCPAC  0x8000
 
 /* HCR_EL2 - Hypervisor Config Register */
 #defineHCR_VM  (UL(0x1) << 0)

git: 4ec5fbddeda4 - main - sys/conf: Remove LD_EMULATION_armv6

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=4ec5fbddeda4d5cc550fa26346d04bd26eea8fed

commit 4ec5fbddeda4d5cc550fa26346d04bd26eea8fed
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:51:28 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:41:04 +

sys/conf: Remove LD_EMULATION_armv6

Armv6 support has been removed, we can remove LD_EMULATION for it.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45959
---
 sys/conf/kern.mk | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk
index 00492584921b..4c3014f2abb6 100644
--- a/sys/conf/kern.mk
+++ b/sys/conf/kern.mk
@@ -324,7 +324,6 @@ CCLDFLAGS+= -fuse-ld=${LD:[1]:S/^ld.//1W}
 LD_EMULATION_aarch64=aarch64elf
 LD_EMULATION_amd64=elf_x86_64_fbsd
 LD_EMULATION_arm=armelf_fbsd
-LD_EMULATION_armv6=armelf_fbsd
 LD_EMULATION_armv7=armelf_fbsd
 LD_EMULATION_i386=elf_i386_fbsd
 LD_EMULATION_powerpc= elf32ppc_fbsd

git: d54631360276 - main - arm64: Add CPTR_TRAP_ALL and use it in vmm

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d54631360276d3fdbaa9a7872f8af82f1f4287da

commit d54631360276d3fdbaa9a7872f8af82f1f4287da
Author: Andrew Turner 
AuthorDate: 2024-09-11 09:38:27 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:25:09 +

arm64: Add CPTR_TRAP_ALL and use it in vmm

Add a new macro that enables all CPTR_EL2 traps. This helps ensure we
trap all extensions we don't support.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D46516
---
 sys/arm64/include/hypervisor.h | 2 ++
 sys/arm64/vmm/vmm_reset.c  | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index 738eeca66ffe..0a138006b108 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -53,11 +53,13 @@
 
 /* CPTR_EL2 - Architecture feature trap register */
 /* Valid if HCR_EL2.E2H == 0 */
+#defineCPTR_TRAP_ALL   0xc01037ff /* Enable all traps */
 #defineCPTR_RES0   0x7fefc800
 #defineCPTR_RES1   0x33ff
 #defineCPTR_TFP0x0400
 #defineCPTR_TTA0x0010
 /* Valid if HCR_EL2.E2H == 1 */
+#defineCPTR_E2H_TRAP_ALL   0xd000
 #defineCPTR_E2H_FPEN   0x0030
 #defineCPTR_E2H_TTA0x1000
 /* Unconditionally valid */
diff --git a/sys/arm64/vmm/vmm_reset.c b/sys/arm64/vmm/vmm_reset.c
index 3195bc10dedd..8ccb83e7a0ea 100644
--- a/sys/arm64/vmm/vmm_reset.c
+++ b/sys/arm64/vmm/vmm_reset.c
@@ -170,9 +170,10 @@ reset_vm_el2_regs(void *vcpu)
 * and floating point functionality to EL2.
 */
if (in_vhe())
-   el2ctx->cptr_el2 = CPACR_FPEN_TRAP_NONE;
+   el2ctx->cptr_el2 = CPTR_E2H_TRAP_ALL | CPTR_E2H_FPEN;
else
-   el2ctx->cptr_el2 = CPTR_RES1;
+   el2ctx->cptr_el2 = CPTR_TRAP_ALL & ~CPTR_TFP;
+   el2ctx->cptr_el2 &= ~CPTR_TCPAC;
/*
 * Disable interrupts in the guest. The guest OS will re-enable
 * them.

git: d29771a722ac - main - arm: Assume __ARM_ARCH == 7

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d29771a722acf17b3d2693e237c0da7ce866997f

commit d29771a722acf17b3d2693e237c0da7ce866997f
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:44:50 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:40:13 +

arm: Assume __ARM_ARCH == 7

The only supported 32-bit Arm architecture is Armv7. Remove old checks
for earlier architecture revisions.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45957
---
 sys/arm/arm/cpu_asm-v6.S  | 18 ---
 sys/arm/arm/exception.S   |  4 
 sys/arm/arm/exec_machdep.c|  2 --
 sys/arm/arm/hypervisor-stub.S |  2 --
 sys/arm/arm/locore.S  |  6 -
 sys/arm/arm/mp_machdep.c  |  2 --
 sys/arm/arm/pmu.c |  8 +++
 sys/arm/arm/trap-v6.c |  4 
 sys/arm/arm/undefined.c   | 13 ---
 sys/arm/arm/vm_machdep.c  |  2 --
 sys/arm/include/asm.h |  8 ---
 sys/arm/include/atomic.h  |  6 -
 sys/arm/include/cpu.h | 54 ---
 sys/arm/include/param.h   |  4 
 sys/arm/include/sysreg.h  | 38 ++
 sys/kern/imgact_elf.c |  2 +-
 16 files changed, 17 insertions(+), 156 deletions(-)

diff --git a/sys/arm/arm/cpu_asm-v6.S b/sys/arm/arm/cpu_asm-v6.S
index 6942c5ce4420..5e8b5e80a436 100644
--- a/sys/arm/arm/cpu_asm-v6.S
+++ b/sys/arm/arm/cpu_asm-v6.S
@@ -47,11 +47,6 @@
 
 /* Invalidate D cache to PoC. (aka all cache levels)*/
 ASENTRY_NP(dcache_inv_poc_all)
-#if __ARM_ARCH == 6
-   mcr CP15_DCIALL
-   DSB
-   bx  lr
-#else
mrc CP15_CLIDR(r0)
andsr0, r0, #0x0700
mov r0, r0, lsr #23 /* Get LoC 'naturally' aligned for */
@@ -97,16 +92,10 @@ ASENTRY_NP(dcache_inv_poc_all)
mcr CP15_CSSELR(r0)
isb
bx  lr
-#endif /* __ARM_ARCH == 6 */
 END(dcache_inv_poc_all)
 
 /* Invalidate D cache to PoU. (aka L1 cache only)*/
 ASENTRY_NP(dcache_inv_pou_all)
-#if __ARM_ARCH == 6
-   mcr CP15_DCIALL
-   DSB
-   bx  lr
-#else
mrc CP15_CLIDR(r0)
andsr0, r0, #0x3800
mov r0, r0, lsr #26 /* Get LoUU (naturally aligned) */
@@ -151,16 +140,10 @@ ASENTRY_NP(dcache_inv_pou_all)
mov r0, #0
mcr CP15_CSSELR(r0)
bx  lr
-#endif
 END(dcache_inv_pou_all)
 
 /* Write back and Invalidate D cache to PoC. */
 ASENTRY_NP(dcache_wbinv_poc_all)
-#if __ARM_ARCH == 6
-   mcr CP15_DCCIALL
-   DSB
-   bx  lr
-#else
mrc CP15_CLIDR(r0)
andsr0, r0, #0x0700
beq 4f
@@ -208,7 +191,6 @@ ASENTRY_NP(dcache_wbinv_poc_all)
mov r0, #0
mcr CP15_CSSELR(r0)
bx  lr
-#endif /* __ARM_ARCH == 6 */
 END(dcache_wbinv_poc_all)
 
 ASENTRY_NP(dcache_wb_pou_checked)
diff --git a/sys/arm/arm/exception.S b/sys/arm/arm/exception.S
index d0be3bd9c90a..7230830f78cb 100644
--- a/sys/arm/arm/exception.S
+++ b/sys/arm/arm/exception.S
@@ -270,13 +270,9 @@ ASENTRY_NP(undefined_entry)
mov r0, sp  /* exception exit routine. pass frame */
 
ldr r2, [sp, #(TF_PC)]  /* load pc */
-#if __ARM_ARCH >= 7
tst r4, #(PSR_T)/* test if PSR_T */
subne   r2, r2, #(THUMB_INSN_SIZE)
subeq   r2, r2, #(INSN_SIZE)
-#else
-   sub r2, r2, #(INSN_SIZE)/* fix pc */
-#endif
str r2, [sp, #TF_PC]/* store pc */
 
 #ifdef KDTRACE_HOOKS
diff --git a/sys/arm/arm/exec_machdep.c b/sys/arm/arm/exec_machdep.c
index 0e66dbddb9ef..0b9468c756a9 100644
--- a/sys/arm/arm/exec_machdep.c
+++ b/sys/arm/arm/exec_machdep.c
@@ -353,12 +353,10 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
tf->tf_usr_lr = (register_t)(PROC_PS_STRINGS(p) -
*(sysent->sv_szsigcode));
/* Set the mode to enter in the signal handler */
-#if __ARM_ARCH >= 7
if ((register_t)catcher & 1)
tf->tf_spsr |= PSR_T;
else
tf->tf_spsr &= ~PSR_T;
-#endif
 
CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr,
tf->tf_usr_sp);
diff --git a/sys/arm/arm/hypervisor-stub.S b/sys/arm/arm/hypervisor-stub.S
index edf538b2b4e5..68ad1f1c1b1b 100644
--- a/sys/arm/arm/hypervisor-stub.S
+++ b/sys/arm/arm/hypervisor-stub.S
@@ -30,7 +30,6 @@
 #include 
 #include 
 #include 
-#if __ARM_ARCH >= 7
 #if defined(__ARM_ARCH_7VE__) || defined(__clang__)
 .arch_extension virt
 #endif
@@ -81,5 +80,4 @@ _C_LABEL(hypervisor_stub_vect):
b   hypervisor_stub_trap /* HYP-Mode */
.word 0 /* FIQ */
.word 0 /* IRQ */
-#endif /* __ARM_ARCH >= 7 */
 
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index ce2bf678b648

git: 66a6e1d61380 - main - arm: Remove support for Armv6 CPU cores

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=66a6e1d61380cd265a4d7dfbc996aebce112db2c

commit 66a6e1d61380cd265a4d7dfbc996aebce112db2c
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:48:25 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:40:35 +

arm: Remove support for Armv6 CPU cores

The ARM1176 is an Armv6 CPU. As Armv6 support has been removed we can
also remove ARM1176 support.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45958
---
 sys/arm/arm/cpufunc.c | 66 +--
 sys/arm/include/cpufunc.h |  3 ---
 2 files changed, 1 insertion(+), 68 deletions(-)

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 05dd521f8221..ba63f82ee597 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -67,9 +67,6 @@ unsigned int  arm_dcache_align_mask;
 #ifdef CPU_MV_PJ4B
 static void pj4bv7_setup(void);
 #endif
-#if defined(CPU_ARM1176)
-static void arm11x6_setup(void);
-#endif
 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 static void cortexa_setup(void);
 #endif
@@ -91,22 +88,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
 };
 #endif /* CPU_MV_PJ4B */
 
-#if defined(CPU_ARM1176)
-struct cpu_functions arm1176_cpufuncs = {
-   /* Cache operations */
-   .cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
-   .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
-   .cf_l2cache_inv_range = (void *)cpufunc_nullop,
-   .cf_l2cache_wb_range = (void *)cpufunc_nullop,
-   .cf_l2cache_drain_writebuf = (void *)cpufunc_nullop,
-
-   /* Other functions */
-   .cf_sleep = arm11x6_sleep, 
-
-   /* Soft functions */
-   .cf_setup = arm11x6_setup
-};
-#endif /*CPU_ARM1176 */
 
 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 struct cpu_functions cortexa_cpufuncs = {
@@ -210,13 +191,6 @@ set_cpufuncs(void)
cputype = cp15_midr_get();
cputype &= CPU_ID_CPU_MASK;
 
-#if defined(CPU_ARM1176)
-   if (cputype == CPU_ID_ARM1176JZS) {
-   cpufuncs = arm1176_cpufuncs;
-   get_cachetype_cp15();
-   goto out;
-   }
-#endif /* CPU_ARM1176 */
 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
switch(cputype & CPU_ID_SCHEME_MASK) {
case CPU_ID_CORTEXA5:
@@ -262,9 +236,7 @@ out:
  */
 
 
-#if defined(CPU_ARM1176) \
- || defined(CPU_MV_PJ4B) \
- || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+#if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
 static __inline void
 cpu_scc_setup_ccnt(void)
 {
@@ -277,10 +249,6 @@ cpu_scc_setup_ccnt(void)
/* Set PMUSERENR[0] to allow userland access */
cp15_pmuserenr_set(1);
 #endif
-#if defined(CPU_ARM1176)
-   /* Set PMCR[2,0] to enable counters and reset CCNT */
-   cp15_pmcr_set(5);
-#else
/* Set up the PMCCNTR register as a cyclecounter:
 * Set PMINTENCLR to 0x to block interrupts
 * Set PMCR[2,0] to enable counters and reset CCNT
@@ -288,41 +256,9 @@ cpu_scc_setup_ccnt(void)
cp15_pminten_clr(0x);
cp15_pmcr_set(5);
cp15_pmcnten_set(0x8000);
-#endif
 }
 #endif
 
-#if defined(CPU_ARM1176)
-static void
-arm11x6_setup(void)
-{
-   uint32_t auxctrl, auxctrl_wax;
-   uint32_t tmp, tmp2;
-   uint32_t cpuid;
-
-   cpuid = cp15_midr_get();
-
-   auxctrl = 0;
-   auxctrl_wax = ~0;
-
-   /*
-* Enable an errata workaround
-*/
-   if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1176JZS) { /* ARM1176JZSr0 */
-   auxctrl = ARM1176_AUXCTL_PHD;
-   auxctrl_wax = ~ARM1176_AUXCTL_PHD;
-   }
-
-   tmp = cp15_actlr_get();
-   tmp2 = tmp;
-   tmp &= auxctrl_wax;
-   tmp |= auxctrl;
-   if (tmp != tmp2)
-   cp15_actlr_set(tmp);
-
-   cpu_scc_setup_ccnt();
-}
-#endif  /* CPU_ARM1176 */
 
 #ifdef CPU_MV_PJ4B
 static void
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 6562042dac0c..15fbabcc109d 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -97,9 +97,6 @@ void  armv7_cpu_sleep (int);
 void   pj4b_config (void);
 #endif
 
-#if defined(CPU_ARM1176)
-voidarm11x6_sleep   (int);  /* no ref. for errata */
-#endif
 
 
 /*

git: bf18be5ab707 - main - bcm2835: Remove support for SoCs with an Armv6 CPU

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=bf18be5ab707c46035239e281f6a1fe458f373a8

commit bf18be5ab707c46035239e281f6a1fe458f373a8
Author: Andrew Turner 
AuthorDate: 2024-07-12 11:39:45 +
Commit: Andrew Turner 
CommitDate: 2024-09-11 10:39:42 +

bcm2835: Remove support for SoCs with an Armv6 CPU

Armv6 has been removed, there is no need to keep this in the tree.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D45956
---
 sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c  |  22 --
 sys/arm/broadcom/bcm2835/bcm2835_machdep.c  |  28 ---
 sys/arm/broadcom/bcm2835/bcm2835_systimer.c | 309 
 sys/arm/broadcom/bcm2835/files.bcm2835  |   2 -
 sys/arm/broadcom/bcm2835/std.bcm2835|   9 -
 5 files changed, 370 deletions(-)

diff --git a/sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c 
b/sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c
index 56227f948e98..3ef564c6ae13 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_cpufreq.c
@@ -61,17 +61,10 @@
 #defineHZ2MHZ(freq) ((freq) / (1000 * 1000))
 #defineMHZ2HZ(freq) ((freq) * (1000 * 1000))
 
-#ifdef SOC_BCM2835
-#defineOFFSET2MVOLT(val) (1200 + ((val) * 25))
-#defineMVOLT2OFFSET(val) (((val) - 1200) / 25)
-#defineDEFAULT_ARM_FREQUENCY700
-#defineDEFAULT_LOWEST_FREQ  300
-#else
 #defineOFFSET2MVOLT(val) (((val) / 1000))
 #defineMVOLT2OFFSET(val) (((val) * 1000))
 #defineDEFAULT_ARM_FREQUENCY600
 #defineDEFAULT_LOWEST_FREQ  600
-#endif
 #defineDEFAULT_CORE_FREQUENCY   250
 #defineDEFAULT_SDRAM_FREQUENCY  400
 #defineTRANSITION_LATENCY  1000
@@ -1507,20 +1500,6 @@ bcm2835_cpufreq_make_freq_list(device_t dev, struct 
cf_setting *sets,
if (min_freq > cpufreq_lowest_freq)
min_freq = cpufreq_lowest_freq;
 
-#ifdef SOC_BCM2835
-   /* from freq to min_freq */
-   for (idx = 0; idx < *count && freq >= min_freq; idx++) {
-   if (freq > sc->arm_min_freq)
-   volts = sc->max_voltage_core;
-   else
-   volts = sc->min_voltage_core;
-   sets[idx].freq = freq;
-   sets[idx].volts = volts;
-   sets[idx].lat = TRANSITION_LATENCY;
-   sets[idx].dev = dev;
-   freq -= MHZSTEP;
-   }
-#else
/* XXX RPi2 have only 900/600MHz */
idx = 0;
volts = sc->min_voltage_core;
@@ -1536,7 +1515,6 @@ bcm2835_cpufreq_make_freq_list(device_t dev, struct 
cf_setting *sets,
sets[idx].dev = dev;
idx++;
}
-#endif
*count = idx;
 
return (0);
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c 
b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
index eabbc371bb19..be6b8971437d 100644
--- a/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
+++ b/sys/arm/broadcom/bcm2835/bcm2835_machdep.c
@@ -61,9 +61,6 @@
 
 #include "platform_if.h"
 
-#ifdef SOC_BCM2835
-static platform_devmap_init_t bcm2835_devmap_init;
-#endif
 #ifdef SOC_BCM2836
 static platform_devmap_init_t bcm2836_devmap_init;
 #endif
@@ -91,20 +88,6 @@ bcm2835_late_init(platform_t plat)
}
 }
 
-#ifdef SOC_BCM2835
-/*
- * Set up static device mappings.
- * All on-chip peripherals exist in a 16MB range starting at 0x2000.
- * Map the entire range using 1MB section mappings.
- */
-static int
-bcm2835_devmap_init(platform_t plat)
-{
-
-   devmap_add_entry(0x2000, 0x0100);
-   return (0);
-}
-#endif
 
 #ifdef SOC_BCM2836
 static int
@@ -122,17 +105,6 @@ bcm2835_cpu_reset(platform_t plat)
bcmwd_watchdog_reset();
 }
 
-#ifdef SOC_BCM2835
-static platform_method_t bcm2835_methods[] = {
-   PLATFORMMETHOD(platform_devmap_init,bcm2835_devmap_init),
-   PLATFORMMETHOD(platform_late_init,  bcm2835_late_init),
-   PLATFORMMETHOD(platform_cpu_reset,  bcm2835_cpu_reset),
-
-   PLATFORMMETHOD_END,
-};
-FDT_PLATFORM_DEF2(bcm2835, bcm2835_legacy, "bcm2835 (legacy)", 0, 
"raspberrypi,model-b", 100);
-FDT_PLATFORM_DEF2(bcm2835, bcm2835, "bcm2835", 0, "brcm,bcm2835", 100);
-#endif
 
 #if defined(SOC_BCM2836) || defined(SOC_BRCM_BCM2837)
 static platform_method_t bcm2836_methods[] = {
diff --git a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c 
b/sys/arm/broadcom/bcm2835/bcm2835_systimer.c
deleted file mode 100644
index 33775d0a2935..
--- a/sys/arm/broadcom/bcm2835/bcm2835_systimer.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * SPDX-License-Identifier: BSD-2-Clause
- *
- * Copyright (c) 2012 Oleksandr Tymoshenko 
- * Copyright (c) 2012 Damjan Marion 
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted pr

git: ecd8cc84dcee - main - scmi: Implement scmi_clknode_recalc_freq method

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=ecd8cc84dcee7d08be8663f721f0502dc5b65808

commit ecd8cc84dcee7d08be8663f721f0502dc5b65808
Author: Cristian Marussi 
AuthorDate: 2023-12-10 22:14:21 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Implement scmi_clknode_recalc_freq method

Allow the SCMI clock frequency to be queried back, useful for testing
the IRQ path via sysctl access.

Reviewed by:andrew
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43038
---
 sys/dev/firmware/arm/scmi_clk.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi_clk.c b/sys/dev/firmware/arm/scmi_clk.c
index da7a8d37b465..b9ab2145ed76 100644
--- a/sys/dev/firmware/arm/scmi_clk.c
+++ b/sys/dev/firmware/arm/scmi_clk.c
@@ -55,7 +55,7 @@ struct scmi_clknode_softc {
int clock_id;
 };
 
-static int __unused
+static int
 scmi_clk_get_rate(struct scmi_clk_softc *sc, int clk_id, uint64_t *rate)
 {
struct scmi_clk_rate_get_out out;
@@ -154,8 +154,18 @@ scmi_clknode_init(struct clknode *clk, device_t dev)
 static int
 scmi_clknode_recalc_freq(struct clknode *clk, uint64_t *freq)
 {
+   struct scmi_clknode_softc *clk_sc;
+   struct scmi_clk_softc *sc;
+   uint64_t rate;
+   int ret;
 
-   return (0);
+   clk_sc = clknode_get_softc(clk);
+   sc = device_get_softc(clk_sc->dev);
+   ret = scmi_clk_get_rate(sc, clk_sc->clock_id, &rate);
+   if (ret == 0)
+   *freq = rate;
+
+   return (ret);
 }
 
 static int

git: d46f01fd590e - main - scmi: Split out the SCMI mailbox to a new file

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d46f01fd590eab5b7c25c7b218d390704a5bcb81

commit d46f01fd590eab5b7c25c7b218d390704a5bcb81
Author: Andrew Turner 
AuthorDate: 2023-10-04 09:32:29 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Split out the SCMI mailbox to a new file

Add a new SCMI interface file to allow for multiple kind of transports
and move the mailbox transport to its own file, using the new interface.

Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43039
---
 sys/conf/files.arm64|   2 +
 sys/dev/firmware/arm/scmi.c |  82 ++---
 sys/dev/firmware/arm/scmi.h |  13 +++
 sys/dev/firmware/arm/scmi_if.m  |  32 +++
 sys/dev/firmware/arm/scmi_mailbox.c | 178 
 5 files changed, 232 insertions(+), 75 deletions(-)

diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 293a0ae1c0f9..5541a18af659 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -272,6 +272,8 @@ dev/etherswitch/felix/felix.c   
optional enetc etherswitch fdt felix pci soc_nxp
 
 dev/firmware/arm/scmi.coptional fdt scmi
 dev/firmware/arm/scmi_clk.coptional fdt scmi
+dev/firmware/arm/scmi_if.m optional fdt scmi
+dev/firmware/arm/scmi_mailbox.coptional fdt scmi
 dev/firmware/arm/scmi_shmem.c  optional fdt scmi
 
 dev/gpio/pl061.c   optional pl061 gpio
diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index 3101be245ee1..fae4ec676a17 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -47,15 +47,6 @@
 #include "scmi.h"
 #include "scmi_protocols.h"
 
-struct scmi_softc {
-   struct simplebus_softc  simplebus_sc;
-   device_tdev;
-   device_ttx_shmem;
-   struct arm_doorbell *db;
-   struct mtx  mtx;
-   int req_done;
-};
-
 static device_t
 scmi_get_shmem(struct scmi_softc *sc, int index)
 {
@@ -90,26 +81,11 @@ scmi_get_shmem(struct scmi_softc *sc, int index)
return (dev);
 }
 
-static void
-scmi_callback(void *arg)
-{
-   struct scmi_softc *sc;
-
-   sc = arg;
-
-   dprintf("%s sc %p\n", __func__, sc);
-
-   SCMI_LOCK(sc);
-   sc->req_done = 1;
-   wakeup(sc);
-   SCMI_UNLOCK(sc);
-}
-
 static int
 scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req)
 {
struct scmi_smt_header hdr;
-   int timeout;
+   int ret;
 
bzero(&hdr, sizeof(struct scmi_smt_header));
 
@@ -125,6 +101,7 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req 
*req)
hdr.channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
hdr.msg_header = req->protocol_id << SMT_HEADER_PROTOCOL_ID_S;
hdr.msg_header |= req->message_id << SMT_HEADER_MESSAGE_ID_S;
+   /* TODO: Allocate a token */
hdr.length = sizeof(hdr.msg_header) + req->in_size;
hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
 
@@ -135,31 +112,9 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req 
*req)
scmi_shmem_write(sc->tx_shmem, SMT_HEADER_SIZE, req->in_buf,
req->in_size);
 
-   sc->req_done = 0;
-
-   /* Interrupt SCP firmware. */
-   arm_doorbell_set(sc->db);
-
-   timeout = 200;
-
-   dprintf("%s: request\n", __func__);
-
-   do {
-   if (cold) {
-   if (arm_doorbell_get(sc->db))
-   break;
-   DELAY(1);
-   } else {
-   msleep(sc, &sc->mtx, 0, "scmi", hz / 10);
-   if (sc->req_done)
-   break;
-   }
-   } while (timeout--);
-
-   if (timeout <= 0)
-   return (-1);
-
-   dprintf("%s: got reply, timeout %d\n", __func__, timeout);
+   ret = SCMI_XFER_MSG(sc->dev);
+   if (ret != 0)
+   return (ret);
 
/* Read header. */
scmi_shmem_read(sc->tx_shmem, 0, &hdr, SMT_HEADER_SIZE);
@@ -186,22 +141,7 @@ scmi_request(device_t dev, struct scmi_req *req)
return (error);
 }
 
-static int
-scmi_probe(device_t dev)
-{
-
-   if (!ofw_bus_is_compatible(dev, "arm,scmi"))
-   return (ENXIO);
-
-   if (!ofw_bus_status_okay(dev))
-   return (ENXIO);
-
-   device_set_desc(dev, "ARM SCMI interface driver");
-
-   return (BUS_PROBE_DEFAULT);
-}
-
-static int
+int
 scmi_attach(device_t dev)
 {
struct scmi_softc *sc;
@@ -221,16 +161,8 @@ scmi_attach(device_t dev)
return (ENXIO)

git: 5ea251c4ed6e - main - scmi: Add an SCMI SMC transport driver

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=5ea251c4ed6e511050037db62600ddf815b623d2

commit 5ea251c4ed6e511050037db62600ddf815b623d2
Author: Andrew Turner 
AuthorDate: 2023-10-04 13:00:50 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Add an SCMI SMC transport driver

Using the SCMI transport interface add a new SMC transport to the
SCMI stack.

Sponsored by: Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43040
---
 sys/conf/files.arm64|   1 +
 sys/dev/firmware/arm/scmi_smc.c | 131 
 2 files changed, 132 insertions(+)

diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 5541a18af659..a22ffa2b7f0c 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -274,6 +274,7 @@ dev/firmware/arm/scmi.c 
optional fdt scmi
 dev/firmware/arm/scmi_clk.coptional fdt scmi
 dev/firmware/arm/scmi_if.m optional fdt scmi
 dev/firmware/arm/scmi_mailbox.coptional fdt scmi
+dev/firmware/arm/scmi_smc.coptional fdt scmi
 dev/firmware/arm/scmi_shmem.c  optional fdt scmi
 
 dev/gpio/pl061.c   optional pl061 gpio
diff --git a/sys/dev/firmware/arm/scmi_smc.c b/sys/dev/firmware/arm/scmi_smc.c
new file mode 100644
index ..ff5f4a2d1491
--- /dev/null
+++ b/sys/dev/firmware/arm/scmi_smc.c
@@ -0,0 +1,131 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2022 Ruslan Bukin 
+ * Copyright (c) 2023 Arm Ltd
+ *
+ * This work was supported by Innovate UK project 105694, "Digital Security
+ * by Design (DSbD) Technology Platform Prototype".
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "scmi.h"
+#include "scmi_protocols.h"
+
+struct scmi_smc_softc {
+   struct scmi_softc   base;
+   uint32_tsmc_id;
+};
+
+static int
+scmi_smc_xfer_msg(device_t dev)
+{
+   struct scmi_smc_softc *sc;
+
+   sc = device_get_softc(dev);
+   SCMI_ASSERT_LOCKED(&sc->base);
+
+   arm_smccc_smc(sc->smc_id, 0, 0, 0, 0, 0, 0, 0, NULL);
+
+   return (0);
+}
+
+static int
+scmi_smc_probe(device_t dev)
+{
+
+   if (!ofw_bus_is_compatible(dev, "arm,scmi-smc"))
+   return (ENXIO);
+
+   if (!ofw_bus_status_okay(dev))
+   return (ENXIO);
+
+   device_set_desc(dev, "ARM SCMI SCM interface driver");
+
+   return (BUS_PROBE_DEFAULT);
+}
+
+static int
+scmi_smc_attach(device_t dev)
+{
+   struct scmi_smc_softc *sc;
+   phandle_t node;
+   ssize_t len;
+
+   sc = device_get_softc(dev);
+
+   node = ofw_bus_get_node(dev);
+   len = OF_getencprop(node, "arm,smc-id", &sc->smc_id,
+   sizeof(sc->smc_id));
+   if (len <= 0) {
+   device_printf(dev, "No SMC ID found\n");
+   return (EINVAL);
+   }
+
+   device_printf(dev, "smc id %x\n", sc->smc_id);
+
+   return (scmi_attach(dev));
+}
+
+static int
+scmi_smc_detach(device_t dev)
+{
+
+   return (0);
+}
+
+static device_method_t scmi_smc_methods[] = {
+   DEVMETHOD(device_probe, scmi_smc_probe),
+   DEVMETHOD(device_attach,scmi_smc_attach),
+   DEVMETHOD(device_detach,scmi_smc_detach),
+
+   /* SCMI interface */
+   DEVMETHOD(scmi_xfer_msg, 

git: d220b1cf02ce - main - scmi: Extend and refactor SCMI shmem support

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=d220b1cf02ce5e7cc0c39052b4e8bffa408d9ed3

commit d220b1cf02ce5e7cc0c39052b4e8bffa408d9ed3
Author: Cristian Marussi 
AuthorDate: 2023-12-06 19:36:02 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Extend and refactor SCMI shmem support

Add a few new common public scmi_shmem methods to be used to handle SCMI
shared memory areas from multiple transports; while doing that review
the shared memory accesses to read only the SMT header fields strictly
relevant to the SCMI message processing.

Move all the SCMI shmem related code to the existing scmi_shmem.c file
and add a new dedicated scmi_shmem.h header.

Introduce some commonly needed message header manipulation macros.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43041
---
 sys/dev/firmware/arm/scmi.c   |  95 ---
 sys/dev/firmware/arm/scmi.h   |  42 --
 sys/dev/firmware/arm/scmi_shmem.c | 115 +-
 sys/dev/firmware/arm/scmi_shmem.h |  70 +++
 4 files changed, 231 insertions(+), 91 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index fae4ec676a17..8428d17cecec 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -2,6 +2,7 @@
  * SPDX-License-Identifier: BSD-2-Clause
  *
  * Copyright (c) 2022 Ruslan Bukin 
+ * Copyright (c) 2023 Arm Ltd
  *
  * This work was supported by Innovate UK project 105694, "Digital Security
  * by Design (DSbD) Technology Platform Prototype".
@@ -46,84 +47,62 @@
 
 #include "scmi.h"
 #include "scmi_protocols.h"
+#include "scmi_shmem.h"
 
-static device_t
-scmi_get_shmem(struct scmi_softc *sc, int index)
-{
-   phandle_t *shmems;
-   phandle_t node;
-   device_t dev;
-   size_t len;
-
-   node = ofw_bus_get_node(sc->dev);
-   if (node <= 0)
-   return (NULL);
-
-   len = OF_getencprop_alloc_multi(node, "shmem", sizeof(*shmems),
-   (void **)&shmems);
-   if (len <= 0) {
-   device_printf(sc->dev, "%s: Can't get shmem node.\n", __func__);
-   return (NULL);
-   }
+#defineSCMI_HDR_TOKEN_S18
+#define SCMI_HDR_TOKEN_BF  (0x3fff)
+#defineSCMI_HDR_TOKEN_M(SCMI_HDR_TOKEN_BF << 
SCMI_HDR_TOKEN_S)
 
-   if (index >= len) {
-   OF_prop_free(shmems);
-   return (NULL);
-   }
+#defineSCMI_HDR_PROTOCOL_ID_S  10
+#defineSCMI_HDR_PROTOCOL_ID_BF (0xff)
+#defineSCMI_HDR_PROTOCOL_ID_M  \
+(SCMI_HDR_PROTOCOL_ID_BF << SCMI_HDR_PROTOCOL_ID_S)
 
-   dev = OF_device_from_xref(shmems[index]);
-   if (dev == NULL)
-   device_printf(sc->dev, "%s: Can't get shmem device.\n",
-   __func__);
+#defineSCMI_HDR_MESSAGE_TYPE_S 8
+#defineSCMI_HDR_MESSAGE_TYPE_BF(0x3)
+#defineSCMI_HDR_MESSAGE_TYPE_M \
+(SCMI_HDR_MESSAGE_TYPE_BF << SCMI_HDR_MESSAGE_TYPE_S)
 
-   OF_prop_free(shmems);
+#defineSCMI_HDR_MESSAGE_ID_S   0
+#defineSCMI_HDR_MESSAGE_ID_BF  (0xff)
+#defineSCMI_HDR_MESSAGE_ID_M   \
+(SCMI_HDR_MESSAGE_ID_BF << SCMI_HDR_MESSAGE_ID_S)
 
-   return (dev);
-}
+#define SCMI_MSG_TYPE_CMD  0
+#define SCMI_MSG_TYPE_DRESP2
+#define SCMI_MSG_TYPE_NOTIF3
 
 static int
 scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req)
 {
-   struct scmi_smt_header hdr;
+   uint32_t reply_header;
int ret;
 
-   bzero(&hdr, sizeof(struct scmi_smt_header));
-
SCMI_ASSERT_LOCKED(sc);
 
-   /* Read header */
-   scmi_shmem_read(sc->tx_shmem, 0, &hdr, SMT_HEADER_SIZE);
-
-   if ((hdr.channel_status & SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE) == 0)
-   return (1);
-
-   /* Update header */
-   hdr.channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
-   hdr.msg_header = req->protocol_id << SMT_HEADER_PROTOCOL_ID_S;
-   hdr.msg_header |= req->message_id << SMT_HEADER_MESSAGE_ID_S;
+   req->msg_header = req->message_id << SCMI_HDR_MESSAGE_ID_S;
/* TODO: Allocate a token */
-   hdr.length = sizeof(hdr.msg_header) + req->in_size;
-   hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
-
-   /* Write header */
-   scmi_shmem_write(sc->tx_shmem, 0, &hdr, SMT_HEADER_SIZE);
+   req->msg_header |= SCMI_MSG_TYPE_CMD << SCMI_HDR_MESSAGE_TYPE_S;
+   req->msg_header |= req->protocol_id <&l

git: cbcfdff05678 - main - scmi: Fix SCMI mailbox polling mechanism

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=cbcfdff05678b143436f81e09f21b3c727efd805

commit cbcfdff05678b143436f81e09f21b3c727efd805
Author: Cristian Marussi 
AuthorDate: 2023-12-07 07:06:10 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Fix SCMI mailbox polling mechanism

When the system is cold, the SCMI stack processes commands in polling
mode with the current polling mechanism being a check of the status
register in the mailbox controller to see if there is any pending
doorbell request.

Anyway, the completion interrupt is optional by the SCMI specification
and a system could have been simply designed without it: for this
reason polling on the mailbox controller status registers is not going
to work in all situations.

Moreover even alternative SCMI transports based on shared memory, like
SMC, will not have at all a mailbox controller to poll for.

On the other side, the associated SCMI Shared Memory Transport defines
dedicated channel flags and status bits that can be used by the agent to
explicitly request a polling-based transaction, even if the completion
interrupt was available, and to check afterwards when the platform has
completed its processing on the outstanding command.

Use SCMI/SMT specific mechanism to process transactions in polling mode.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43042
---
 sys/dev/firmware/arm/scmi.c |  2 +-
 sys/dev/firmware/arm/scmi_mailbox.c |  3 ++-
 sys/dev/firmware/arm/scmi_shmem.c   | 18 --
 sys/dev/firmware/arm/scmi_shmem.h   |  4 +++-
 4 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index 8428d17cecec..ee41ad4383c0 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -85,7 +85,7 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req 
*req)
req->msg_header |= SCMI_MSG_TYPE_CMD << SCMI_HDR_MESSAGE_TYPE_S;
req->msg_header |= req->protocol_id << SCMI_HDR_PROTOCOL_ID_S;
 
-   ret = scmi_shmem_prepare_msg(sc->a2p_dev, req);
+   ret = scmi_shmem_prepare_msg(sc->a2p_dev, req, cold);
if (ret != 0)
return (ret);
 
diff --git a/sys/dev/firmware/arm/scmi_mailbox.c 
b/sys/dev/firmware/arm/scmi_mailbox.c
index bebdc7348b98..c7f4fda4d5c4 100644
--- a/sys/dev/firmware/arm/scmi_mailbox.c
+++ b/sys/dev/firmware/arm/scmi_mailbox.c
@@ -49,6 +49,7 @@
 
 #include "scmi.h"
 #include "scmi_protocols.h"
+#include "scmi_shmem.h"
 
 struct scmi_mailbox_softc {
struct scmi_softc   base;
@@ -91,7 +92,7 @@ scmi_mailbox_xfer_msg(device_t dev)
 
do {
if (cold) {
-   if (arm_doorbell_get(sc->db))
+   if (scmi_shmem_poll_msg(sc->base.a2p_dev))
break;
DELAY(1);
} else {
diff --git a/sys/dev/firmware/arm/scmi_shmem.c 
b/sys/dev/firmware/arm/scmi_shmem.c
index efb6b77c6e4b..066f28777cb7 100644
--- a/sys/dev/firmware/arm/scmi_shmem.c
+++ b/sys/dev/firmware/arm/scmi_shmem.c
@@ -168,7 +168,7 @@ scmi_shmem_get(device_t dev, phandle_t node, int index)
 }
 
 int
-scmi_shmem_prepare_msg(device_t dev, struct scmi_req *req)
+scmi_shmem_prepare_msg(device_t dev, struct scmi_req *req, bool polling)
 {
struct scmi_smt_header hdr = {};
uint32_t channel_status;
@@ -185,7 +185,10 @@ scmi_shmem_prepare_msg(device_t dev, struct scmi_req *req)
hdr.channel_status &= ~SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE;
hdr.msg_header = htole32(req->msg_header);
hdr.length = htole32(sizeof(req->msg_header) + req->in_size);
-   hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+   if (!polling)
+   hdr.flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+   else
+   hdr.flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
 
/* Write header */
scmi_shmem_write(dev, 0, &hdr, SMT_SIZE_HEADER);
@@ -239,6 +242,17 @@ scmi_shmem_read_msg_payload(device_t dev, uint8_t *buf, 
uint32_t buf_len)
return (0);
 }
 
+bool scmi_shmem_poll_msg(device_t dev)
+{
+   uint32_t status;
+
+   scmi_shmem_read(dev, SMT_OFFSET_CHAN_STATUS, &status,
+   SMT_SIZE_CHAN_STATUS);
+
+   return (status & (SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR |
+   SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE));
+}
+
 static device_method_t shmem_methods[] = {
DEVMETHOD(device_probe, shmem_probe),
DEVMETHOD(device_attach,shmem_attach),
diff --git a/sys/dev/firmware/arm/scmi_shmem.h 
b/sys/dev/firmware/arm/scmi_shmem.h
index ce82a3c90d87..d46493dc0342 100644
--- a/sys/de

git: a0ba2a97fd19 - main - scmi: Protect SCMI/SMT channels from concurrent transmissions

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=a0ba2a97fd19e233ee4ab34c2ca7b1aecbe6d651

commit a0ba2a97fd19e233ee4ab34c2ca7b1aecbe6d651
Author: Cristian Marussi 
AuthorDate: 2023-12-07 07:58:28 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Protect SCMI/SMT channels from concurrent transmissions

The SCMI/SMT memory areas are used from the agent and the platform as
channels to exchage commands and replies.

Once the platform has completed its processing and a reply is ready to
be read from the agent, the platform will relinquish the channel to the
agent by setting the CHANNEL_FREE bits in the related SMT area.

When this happens, though, the agent has still to effectively read back
the reply message and any other concurrent request happened to have been
issued in the meantime will have been to be hold back until the reply
is processed or risk to be overwritten by the new request.

The base->mtx lock that currently guards the whole scmi_request()
operation is released when sleeping waiting for a reply, so the above
mentioned race can still happen or, in a slightly different scenario,
the concurrent transmission could just fail, finding the channel busy,
after having sneaked through the mutex.

Adding a new mechanism to let the agent explicitly acquire/release the
channel paves the way, in the future, to remove such central commmon
lock in favour of new dedicated per-transport locking mechanisms, since
not all transports will necessarily need the same level of protection.

Add a flag, controlled by the agent, to mark when the channel has an
inflight command transaction still pending to be completed and make the
agent spin on it when queueing multiple concurrent messages on the same
SMT channel.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43043
---
 sys/dev/firmware/arm/scmi.c   | 19 --
 sys/dev/firmware/arm/scmi_shmem.c | 41 +++
 sys/dev/firmware/arm/scmi_shmem.h |  1 +
 3 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index ee41ad4383c0..a797e52d74b1 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -91,18 +91,25 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req 
*req)
 
ret = SCMI_XFER_MSG(sc->dev);
if (ret != 0)
-   return (ret);
+   goto out;
 
/* Read header. */
ret = scmi_shmem_read_msg_header(sc->a2p_dev, &reply_header);
if (ret != 0)
-   return (ret);
+   goto out;
+
+   if (reply_header != req->msg_header) {
+   ret = EPROTO;
+   goto out;
+   }
+
+   ret = scmi_shmem_read_msg_payload(sc->a2p_dev, req->out_buf,
+   req->out_size);
 
-   if (reply_header != req->msg_header)
-   return (EPROTO);
+out:
+   scmi_shmem_tx_complete(sc->a2p_dev);
 
-   return (scmi_shmem_read_msg_payload(sc->a2p_dev, req->out_buf,
-   req->out_size));
+   return (ret);
 }
 
 int
diff --git a/sys/dev/firmware/arm/scmi_shmem.c 
b/sys/dev/firmware/arm/scmi_shmem.c
index 066f28777cb7..5fb41af05246 100644
--- a/sys/dev/firmware/arm/scmi_shmem.c
+++ b/sys/dev/firmware/arm/scmi_shmem.c
@@ -36,6 +36,8 @@
 #include 
 #include 
 
+#include 
+
 #include 
 #include 
 #include 
@@ -45,15 +47,21 @@
 #include "scmi_shmem.h"
 #include "scmi.h"
 
+#define INFLIGHT_NONE  0
+#define INFLIGHT_REQ   1
+
 struct shmem_softc {
device_tdev;
device_tparent;
int reg;
+   int inflight;
 };
 
 static voidscmi_shmem_read(device_t, bus_size_t, void *, bus_size_t);
 static voidscmi_shmem_write(device_t, bus_size_t, const void *,
 bus_size_t);
+static voidscmi_shmem_acquire_channel(struct shmem_softc *);
+static voidscmi_shmem_release_channel(struct shmem_softc *);
 
 static int shmem_probe(device_t);
 static int shmem_attach(device_t);
@@ -94,6 +102,7 @@ shmem_attach(device_t dev)
dprintf("%s: reg %x\n", __func__, reg);
 
sc->reg = reg;
+   atomic_store_rel_int(&sc->inflight, INFLIGHT_NONE);
 
OF_device_register_xref(OF_xref_from_node(node), dev);
 
@@ -167,16 +176,39 @@ scmi_shmem_get(device_t dev, phandle_t node, int index)
return (shmem_dev);
 }
 
+static void
+scmi_shmem_acquire_channel(struct shmem_softc *sc)
+{
+
+while ((atomic_cmpset_acq_int(&sc->inflight, INFLIGHT_NONE,
+INFLIGHT_REQ)) == 0)
+  

git: 403ca28c28bd - main - scmi: Add new SCMI interfaces for init and message processing

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=403ca28c28bdd34849b7e621b5e0acb4a864111c

commit 403ca28c28bdd34849b7e621b5e0acb4a864111c
Author: Cristian Marussi 
AuthorDate: 2023-12-07 14:06:36 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Add new SCMI interfaces for init and message processing

Introduce a couple of new SCMI interface methods to allow centralized
initialization of transport-specific features and a couple of methods
to handle message reception from the SCMI core.

Move SCMI SMT related calls out of the core common SCMI code into the
transport specific layers Mailbox/SMC.

Make SCMI Mailbox/SMC transports use the new interface methods for
initialization and message reception.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43044
---
 sys/dev/firmware/arm/scmi.c |  42 +++-
 sys/dev/firmware/arm/scmi.h |   1 -
 sys/dev/firmware/arm/scmi_if.m  |  23 +++
 sys/dev/firmware/arm/scmi_mailbox.c | 127 +---
 sys/dev/firmware/arm/scmi_shmem.c   |   2 +-
 sys/dev/firmware/arm/scmi_smc.c |  78 +++---
 6 files changed, 192 insertions(+), 81 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index a797e52d74b1..5a69dc1daa7b 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -43,11 +43,8 @@
 #include 
 #include 
 
-#include "dev/mailbox/arm/arm_doorbell.h"
-
 #include "scmi.h"
 #include "scmi_protocols.h"
-#include "scmi_shmem.h"
 
 #defineSCMI_HDR_TOKEN_S18
 #define SCMI_HDR_TOKEN_BF  (0x3fff)
@@ -75,7 +72,6 @@
 static int
 scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req)
 {
-   uint32_t reply_header;
int ret;
 
SCMI_ASSERT_LOCKED(sc);
@@ -85,29 +81,12 @@ scmi_request_locked(struct scmi_softc *sc, struct scmi_req 
*req)
req->msg_header |= SCMI_MSG_TYPE_CMD << SCMI_HDR_MESSAGE_TYPE_S;
req->msg_header |= req->protocol_id << SCMI_HDR_PROTOCOL_ID_S;
 
-   ret = scmi_shmem_prepare_msg(sc->a2p_dev, req, cold);
-   if (ret != 0)
-   return (ret);
-
-   ret = SCMI_XFER_MSG(sc->dev);
-   if (ret != 0)
-   goto out;
-
-   /* Read header. */
-   ret = scmi_shmem_read_msg_header(sc->a2p_dev, &reply_header);
-   if (ret != 0)
-   goto out;
-
-   if (reply_header != req->msg_header) {
-   ret = EPROTO;
-   goto out;
-   }
+   ret = SCMI_XFER_MSG(sc->dev, req);
+   if (ret == 0)
+   ret = SCMI_COLLECT_REPLY(sc->dev, req);
 
-   ret = scmi_shmem_read_msg_payload(sc->a2p_dev, req->out_buf,
-   req->out_size);
-
-out:
-   scmi_shmem_tx_complete(sc->a2p_dev);
+   if (ret == 0  || ret != EBUSY)
+   SCMI_TX_COMPLETE(sc->dev, NULL);
 
return (ret);
 }
@@ -141,16 +120,14 @@ scmi_attach(device_t dev)
if (node == -1)
return (ENXIO);
 
-   sc->a2p_dev = scmi_shmem_get(dev, node, SCMI_CHAN_A2P);
-   if (sc->a2p_dev == NULL) {
-   device_printf(dev, "A2P shmem dev not found.\n");
-   return (ENXIO);
-   }
-
mtx_init(&sc->mtx, device_get_nameunit(dev), "SCMI", MTX_DEF);
 
simplebus_init(dev, node);
 
+   error = SCMI_TRANSPORT_INIT(dev);
+   if (error != 0)
+   return (error);
+
/*
 * Allow devices to identify.
 */
@@ -171,6 +148,7 @@ static int
 scmi_detach(device_t dev)
 {
 
+   SCMI_TRANSPORT_CLEANUP(dev);
return (0);
 }
 
diff --git a/sys/dev/firmware/arm/scmi.h b/sys/dev/firmware/arm/scmi.h
index bebebff50429..2647db9d9e90 100644
--- a/sys/dev/firmware/arm/scmi.h
+++ b/sys/dev/firmware/arm/scmi.h
@@ -51,7 +51,6 @@ enum scmi_chan {
 struct scmi_softc {
struct simplebus_softc  simplebus_sc;
device_tdev;
-   device_ta2p_dev;
struct mtx  mtx;
 };
 
diff --git a/sys/dev/firmware/arm/scmi_if.m b/sys/dev/firmware/arm/scmi_if.m
index 524cf0fb0d66..5cacf99edc47 100644
--- a/sys/dev/firmware/arm/scmi_if.m
+++ b/sys/dev/firmware/arm/scmi_if.m
@@ -27,6 +27,29 @@
 
 INTERFACE scmi;
 
+HEADER {
+   struct scmi_req;
+};
+
+METHOD int transport_init {
+   device_t dev;
+};
+
+METHOD void transport_cleanup {
+   device_t dev;
+};
+
 METHOD int xfer_msg {
device_t dev;
+   struct scmi_req *req;
+};
+
+METHOD int collect_reply {
+   device_t dev;
+   struct scmi_req *req;
+};
+
+METHOD void tx_complete {
+   device_t dev;
+   void *chan;
 };
diff --git a/sys/dev/fi

git: 3595f18fc78b - main - scmi: Add SCMI message tracking and centralize tx/rx logic

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=3595f18fc78b9f799010a1a45fb890e3b087394d

commit 3595f18fc78b9f799010a1a45fb890e3b087394d
Author: Cristian Marussi 
AuthorDate: 2023-12-07 18:32:29 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Add SCMI message tracking and centralize tx/rx logic

In order to be able to support also new, more parallel, SCMI transports
that by nature can allow multiple concurrent commands to be in-flight,
pending a reply, we must be able to use the sequence number provided in
the SCMI messages to track the message status, matching commands and
replies while keeping track of timeouts and duplicates.

Add the needed message tracking machinery in the core SCMI stack and
move the residual common tx/rx logic from the specific transports to
the core SCMI stack, while adding one more interface to let the
transports customize ther behaviour.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43045
---
 sys/dev/firmware/arm/scmi.c | 298 
 sys/dev/firmware/arm/scmi.h |  40 +++--
 sys/dev/firmware/arm/scmi_if.m  |  11 ++
 sys/dev/firmware/arm/scmi_mailbox.c |  73 +
 sys/dev/firmware/arm/scmi_shmem.c   |  23 ++-
 sys/dev/firmware/arm/scmi_shmem.h   |   3 +-
 sys/dev/firmware/arm/scmi_smc.c |  52 +++
 7 files changed, 391 insertions(+), 109 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index 5a69dc1daa7b..620b40ba32aa 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -31,12 +31,17 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -46,6 +51,8 @@
 #include "scmi.h"
 #include "scmi_protocols.h"
 
+#define SCMI_MAX_TOKEN 1024
+
 #defineSCMI_HDR_TOKEN_S18
 #define SCMI_HDR_TOKEN_BF  (0x3fff)
 #defineSCMI_HDR_TOKEN_M(SCMI_HDR_TOKEN_BF << 
SCMI_HDR_TOKEN_S)
@@ -69,42 +76,43 @@
 #define SCMI_MSG_TYPE_DRESP2
 #define SCMI_MSG_TYPE_NOTIF3
 
-static int
-scmi_request_locked(struct scmi_softc *sc, struct scmi_req *req)
-{
-   int ret;
-
-   SCMI_ASSERT_LOCKED(sc);
-
-   req->msg_header = req->message_id << SCMI_HDR_MESSAGE_ID_S;
-   /* TODO: Allocate a token */
-   req->msg_header |= SCMI_MSG_TYPE_CMD << SCMI_HDR_MESSAGE_TYPE_S;
-   req->msg_header |= req->protocol_id << SCMI_HDR_PROTOCOL_ID_S;
-
-   ret = SCMI_XFER_MSG(sc->dev, req);
-   if (ret == 0)
-   ret = SCMI_COLLECT_REPLY(sc->dev, req);
+#define SCMI_MSG_TYPE_CHECK(_h, _t)\
+_h) & SCMI_HDR_MESSAGE_TYPE_M) >> SCMI_HDR_MESSAGE_TYPE_S) == (_t))
 
-   if (ret == 0  || ret != EBUSY)
-   SCMI_TX_COMPLETE(sc->dev, NULL);
+#define SCMI_IS_MSG_TYPE_NOTIF(h)  \
+SCMI_MSG_TYPE_CHECK((h), SCMI_MSG_TYPE_NOTIF)
+#define SCMI_IS_MSG_TYPE_DRESP(h)  \
+SCMI_MSG_TYPE_CHECK((h), SCMI_MSG_TYPE_DRESP)
 
-   return (ret);
-}
+#define SCMI_MSG_TOKEN(_hdr)   \
+(((_hdr) & SCMI_HDR_TOKEN_M) >> SCMI_HDR_TOKEN_S)
 
-int
-scmi_request(device_t dev, struct scmi_req *req)
-{
-   struct scmi_softc *sc;
-   int error;
+BITSET_DEFINE(_scmi_tokens, SCMI_MAX_TOKEN);
+LIST_HEAD(inflight_head, scmi_req);
+#defineREQHASH(_sc, _tk)   \
+(&((_sc)->trs->inflight_ht[(_tk) & (_sc)->trs->inflight_mask]))
 
-   sc = device_get_softc(dev);
+struct scmi_transport {
+   unsigned long   next_id;
+   struct _scmi_tokens avail_tokens;
+   struct inflight_head*inflight_ht;
+   unsigned long   inflight_mask;
+   struct mtx  mtx;
+};
 
-   SCMI_LOCK(sc);
-   error = scmi_request_locked(sc, req);
-   SCMI_UNLOCK(sc);
+static int scmi_transport_init(struct scmi_softc *);
+static voidscmi_transport_cleanup(struct scmi_softc *);
+static int scmi_token_pick(struct scmi_softc *);
+static voidscmi_token_release_unlocked(struct scmi_softc *, int);
+static int scmi_req_track_inflight(struct scmi_softc *,
+   struct scmi_req *);
+static int scmi_req_drop_inflight(struct scmi_softc *,
+   struct scmi_req *);
+static struct scmi_req *scmi_req_lookup_inflight(struct scmi_softc *, 
uint32_t);
 
-   return (error);
-}
+static int scmi_wait_for_response(struct scmi_softc *,
+struct scmi_req *);
+static void  

git: 35f93203963f - main - scmi: Introduce a new SCMI API and port CLK SCMI driver to it

[Andrew Turner]

The branch main has been updated by andrew:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=35f93203963f83161012cd731e858a56548c2ef9

commit 35f93203963f83161012cd731e858a56548c2ef9
Author: Cristian Marussi 
AuthorDate: 2023-12-11 08:33:01 +
Commit: Andrew Turner 
CommitDate: 2024-04-11 09:58:56 +

scmi: Introduce a new SCMI API and port CLK SCMI driver to it

Expose new scmi_buf_get/put API methods to build and send messages;
command request descriptors are now pre-allocated when the SCMI core is
initialized and kept in a free list, instead of being allocated on the
stack of the caller of the SCMI request.

Dynamically allocated descriptors enable the SCMI core to keep around
and track outstanding transactions for as long as needed, outliving the
lifetime of the caller stack: this allows tracking of late or missing
replies and it will be needed when adding support for SCMI transports
that allows for more messages to be inflight concurrently.

Move the existing CLK SCMI driver to the new API.

Reviewed by:andrew
Tested on:  Arm Morello Board
Sponsored by:   Arm Ltd
Differential Revision:  https://reviews.freebsd.org/D43046
---
 sys/dev/firmware/arm/scmi.c | 282 +---
 sys/dev/firmware/arm/scmi.h |  32 ++--
 sys/dev/firmware/arm/scmi_clk.c | 232 +
 sys/dev/firmware/arm/scmi_clk.h |  13 +-
 sys/dev/firmware/arm/scmi_if.m  |   8 +-
 sys/dev/firmware/arm/scmi_mailbox.c |  36 ++---
 sys/dev/firmware/arm/scmi_shmem.c   |  39 ++---
 sys/dev/firmware/arm/scmi_shmem.h   |  10 +-
 sys/dev/firmware/arm/scmi_smc.c |  30 ++--
 9 files changed, 433 insertions(+), 249 deletions(-)

diff --git a/sys/dev/firmware/arm/scmi.c b/sys/dev/firmware/arm/scmi.c
index 620b40ba32aa..945c2b2e9f6e 100644
--- a/sys/dev/firmware/arm/scmi.c
+++ b/sys/dev/firmware/arm/scmi.c
@@ -42,6 +42,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -87,6 +88,31 @@
 #define SCMI_MSG_TOKEN(_hdr)   \
 (((_hdr) & SCMI_HDR_TOKEN_M) >> SCMI_HDR_TOKEN_S)
 
+struct scmi_req {
+   int cnt;
+   booltimed_out;
+   booluse_polling;
+   booldone;
+   struct mtx  mtx;
+   LIST_ENTRY(scmi_req)next;
+   int protocol_id;
+   int message_id;
+   int token;
+   uint32_theader;
+   struct scmi_msg msg;
+};
+
+#define buf_to_msg(b)  __containerof((b), struct scmi_msg, payld)
+#define msg_to_req(m)  __containerof((m), struct scmi_req, msg)
+#define buf_to_req(b)  msg_to_req(buf_to_msg(b))
+
+LIST_HEAD(reqs_head, scmi_req);
+
+struct scmi_reqs_pool {
+   struct mtx  mtx;
+   struct reqs_headhead;
+};
+
 BITSET_DEFINE(_scmi_tokens, SCMI_MAX_TOKEN);
 LIST_HEAD(inflight_head, scmi_req);
 #defineREQHASH(_sc, _tk)   \
@@ -97,11 +123,19 @@ struct scmi_transport {
struct _scmi_tokens avail_tokens;
struct inflight_head*inflight_ht;
unsigned long   inflight_mask;
+   struct scmi_reqs_pool   *chans[SCMI_CHAN_MAX];
struct mtx  mtx;
 };
 
 static int scmi_transport_init(struct scmi_softc *);
 static voidscmi_transport_cleanup(struct scmi_softc *);
+static struct scmi_reqs_pool *scmi_reqs_pool_allocate(const int, const int);
+static voidscmi_reqs_pool_free(struct scmi_reqs_pool *);
+static struct scmi_req *scmi_req_alloc(struct scmi_softc *, enum scmi_chan);
+static voidscmi_req_free_unlocked(struct scmi_softc *,
+enum scmi_chan, struct scmi_req *);
+static voidscmi_req_get(struct scmi_softc *, struct scmi_req *);
+static voidscmi_req_put(struct scmi_softc *, struct scmi_req *);
 static int scmi_token_pick(struct scmi_softc *);
 static voidscmi_token_release_unlocked(struct scmi_softc *, int);
 static int scmi_req_track_inflight(struct scmi_softc *,
@@ -111,7 +145,7 @@ static int  scmi_req_drop_inflight(struct 
scmi_softc *,
 static struct scmi_req *scmi_req_lookup_inflight(struct scmi_softc *, 
uint32_t);
 
 static int scmi_wait_for_response(struct scmi_softc *,
-struct scmi_req *);
+   struct scmi_req *, void **);
 static voidscmi_process_response(struct scmi_softc *, uint32_t);
 
 int
@@ -177,6 +211,42 @@ DEFINE_CLASS_1(scmi, scmi_driver, scmi_methods, 
sizeof(struct scmi_softc),
 DRIVER_MODULE(scmi, simplebus, scmi_driver, 0, 0);
 MODULE_VERSION(scmi, 1);
 
+static struct scmi_reqs_pool *
+scmi_reqs_pool_allocate(const int max_msg, const int max_payld_sz)
+{
+   struct scmi_reqs_pool *rp;
+   struct scmi_req *req;
+
+   rp = malloc(sizeof(*rp), M_DEVBUF, M_ZERO | M_WAITOK);
+
+   LIST_INIT(&rp->head);
+