[dpdk-dev] [PATCH v1] raw/ptdma: introduce ptdma driver
From: Selwin Sebastian
Add support for PTDMA driver
Signed-off-by: Selwin Sebastian
---
MAINTAINERS | 5 +
doc/guides/rawdevs/ptdma.rst | 220 +
drivers/raw/meson.build | 1 +
drivers/raw/ptdma/meson.build| 16 +
drivers/raw/ptdma/ptdma_dev.c| 136
drivers/raw/ptdma/ptdma_pmd_private.h| 41 +++
drivers/raw/ptdma/ptdma_rawdev.c | 294 ++
drivers/raw/ptdma/ptdma_rawdev_spec.h| 379 +++
drivers/raw/ptdma/ptdma_rawdev_test.c| 273
drivers/raw/ptdma/rte_ptdma_rawdev.h | 124
drivers/raw/ptdma/rte_ptdma_rawdev_fns.h | 261
drivers/raw/ptdma/version.map| 5 +
usertools/dpdk-devbind.py| 4 +-
13 files changed, 1758 insertions(+), 1 deletion(-)
create mode 100644 doc/guides/rawdevs/ptdma.rst
create mode 100644 drivers/raw/ptdma/meson.build
create mode 100644 drivers/raw/ptdma/ptdma_dev.c
create mode 100644 drivers/raw/ptdma/ptdma_pmd_private.h
create mode 100644 drivers/raw/ptdma/ptdma_rawdev.c
create mode 100644 drivers/raw/ptdma/ptdma_rawdev_spec.h
create mode 100644 drivers/raw/ptdma/ptdma_rawdev_test.c
create mode 100644 drivers/raw/ptdma/rte_ptdma_rawdev.h
create mode 100644 drivers/raw/ptdma/rte_ptdma_rawdev_fns.h
create mode 100644 drivers/raw/ptdma/version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index 44f3d322e..96005da54 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1272,6 +1272,11 @@ F: doc/guides/rawdevs/ioat.rst
F: examples/ioat/
F: doc/guides/sample_app_ug/ioat.rst
+PTDMA Rawdev
+M: Selwin Sebastian
+F: drivers/raw/ptdma/
+F: doc/guides/rawdevs/ptdma.rst
+
NXP DPAA2 QDMA
M: Nipun Gupta
F: drivers/raw/dpaa2_qdma/
diff --git a/doc/guides/rawdevs/ptdma.rst b/doc/guides/rawdevs/ptdma.rst
new file mode 100644
index 0..50772f9f3
--- /dev/null
+++ b/doc/guides/rawdevs/ptdma.rst
@@ -0,0 +1,220 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+PTDMA Rawdev Driver
+===
+
+The ``ptdma`` rawdev driver provides a poll-mode driver (PMD) for AMD PTDMA
device.
+
+Hardware Requirements
+--
+
+The ``dpdk-devbind.py`` script, included with DPDK,
+can be used to show the presence of supported hardware.
+Running ``dpdk-devbind.py --status-dev misc`` will show all the miscellaneous,
+or rawdev-based devices on the system.
+
+Sample output from a system with PTDMA is shown below
+
+Misc (rawdev) devices using DPDK-compatible driver
+==
+:01:00.2 'Starship/Matisse PTDMA 1498' drv=igb_uio unused=vfio-pci
+:02:00.2 'Starship/Matisse PTDMA 1498' drv=igb_uio unused=vfio-pci
+
+Devices using UIO drivers
+~~~
+
+The HW devices to be used will need to be bound to a user-space IO driver for
use.
+The ``dpdk-devbind.py`` script can be used to view the state of the PTDMA
devices
+and to bind them to a suitable DPDK-supported driver, such as ``igb_uio``.
+For example::
+
+$ sudo ./usertools/dpdk-devbind.py --force --bind=igb_uio
:01:00.2 :02:00.2
+
+Compilation
+
+
+For builds using ``meson`` and ``ninja``, the driver will be built when the
target platform is x86-based.
+No additional compilation steps are necessary.
+
+
+Using PTDMA Rawdev Devices
+--
+
+To use the devices from an application, the rawdev API can be used, along
+with definitions taken from the device-specific header file
+``rte_ptdma_rawdev.h``. This header is needed to get the definition of
+structure parameters used by some of the rawdev APIs for PTDMA rawdev
+devices, as well as providing key functions for using the device for memory
+copies.
+
+Getting Device Information
+~~~
+
+Basic information about each rawdev device can be queried using the
+``rte_rawdev_info_get()`` API. For most applications, this API will be
+needed to verify that the rawdev in question is of the expected type. For
+example, the following code snippet can be used to identify an PTDMA
+rawdev device for use by an application:
+
+.. code-block:: C
+
+for (i = 0; i < count && !found; i++) {
+struct rte_rawdev_info info = { .dev_private = NULL };
+found = (rte_rawdev_info_get(i, &info, 0) == 0 &&
+strcmp(info.driver_name,
+PTDMA_PMD_RAWDEV_NAME) == 0);
+}
+
+When calling the ``rte_rawdev_info_get()`` API for an PTDMA rawdev device,
+the ``dev_private`` field in the ``rte_rawdev_info`` struct should either
+be NULL, or else be set to point to a structure of type
+``rte_ptdma_rawdev_config``, in which case the size of the configured device
+input ring will be returned in that structure.
+
+Device Configuration
+
[dpdk-dev] [RFC PATCH] raw/ptdma: introduce ptdma driver
From: Selwin Sebastian
Add support for PTDMA driver
Signed-off-by: Selwin Sebastian
---
MAINTAINERS | 5 +
doc/guides/rawdevs/ptdma.rst | 220 +
drivers/raw/meson.build | 1 +
drivers/raw/ptdma/meson.build| 16 +
drivers/raw/ptdma/ptdma_dev.c| 136
drivers/raw/ptdma/ptdma_pmd_private.h| 41 +++
drivers/raw/ptdma/ptdma_rawdev.c | 294 ++
drivers/raw/ptdma/ptdma_rawdev_spec.h| 379 +++
drivers/raw/ptdma/ptdma_rawdev_test.c| 273
drivers/raw/ptdma/rte_ptdma_rawdev.h | 124
drivers/raw/ptdma/rte_ptdma_rawdev_fns.h | 261
drivers/raw/ptdma/version.map| 5 +
usertools/dpdk-devbind.py| 4 +-
13 files changed, 1758 insertions(+), 1 deletion(-)
create mode 100644 doc/guides/rawdevs/ptdma.rst
create mode 100644 drivers/raw/ptdma/meson.build
create mode 100644 drivers/raw/ptdma/ptdma_dev.c
create mode 100644 drivers/raw/ptdma/ptdma_pmd_private.h
create mode 100644 drivers/raw/ptdma/ptdma_rawdev.c
create mode 100644 drivers/raw/ptdma/ptdma_rawdev_spec.h
create mode 100644 drivers/raw/ptdma/ptdma_rawdev_test.c
create mode 100644 drivers/raw/ptdma/rte_ptdma_rawdev.h
create mode 100644 drivers/raw/ptdma/rte_ptdma_rawdev_fns.h
create mode 100644 drivers/raw/ptdma/version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index 44f3d322e..96005da54 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1272,6 +1272,11 @@ F: doc/guides/rawdevs/ioat.rst
F: examples/ioat/
F: doc/guides/sample_app_ug/ioat.rst
+PTDMA Rawdev
+M: Selwin Sebastian
+F: drivers/raw/ptdma/
+F: doc/guides/rawdevs/ptdma.rst
+
NXP DPAA2 QDMA
M: Nipun Gupta
F: drivers/raw/dpaa2_qdma/
diff --git a/doc/guides/rawdevs/ptdma.rst b/doc/guides/rawdevs/ptdma.rst
new file mode 100644
index 0..50772f9f3
--- /dev/null
+++ b/doc/guides/rawdevs/ptdma.rst
@@ -0,0 +1,220 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
+
+PTDMA Rawdev Driver
+===
+
+The ``ptdma`` rawdev driver provides a poll-mode driver (PMD) for AMD PTDMA
device.
+
+Hardware Requirements
+--
+
+The ``dpdk-devbind.py`` script, included with DPDK,
+can be used to show the presence of supported hardware.
+Running ``dpdk-devbind.py --status-dev misc`` will show all the miscellaneous,
+or rawdev-based devices on the system.
+
+Sample output from a system with PTDMA is shown below
+
+Misc (rawdev) devices using DPDK-compatible driver
+==
+:01:00.2 'Starship/Matisse PTDMA 1498' drv=igb_uio unused=vfio-pci
+:02:00.2 'Starship/Matisse PTDMA 1498' drv=igb_uio unused=vfio-pci
+
+Devices using UIO drivers
+~~~
+
+The HW devices to be used will need to be bound to a user-space IO driver for
use.
+The ``dpdk-devbind.py`` script can be used to view the state of the PTDMA
devices
+and to bind them to a suitable DPDK-supported driver, such as ``igb_uio``.
+For example::
+
+$ sudo ./usertools/dpdk-devbind.py --force --bind=igb_uio
:01:00.2 :02:00.2
+
+Compilation
+
+
+For builds using ``meson`` and ``ninja``, the driver will be built when the
target platform is x86-based.
+No additional compilation steps are necessary.
+
+
+Using PTDMA Rawdev Devices
+--
+
+To use the devices from an application, the rawdev API can be used, along
+with definitions taken from the device-specific header file
+``rte_ptdma_rawdev.h``. This header is needed to get the definition of
+structure parameters used by some of the rawdev APIs for PTDMA rawdev
+devices, as well as providing key functions for using the device for memory
+copies.
+
+Getting Device Information
+~~~
+
+Basic information about each rawdev device can be queried using the
+``rte_rawdev_info_get()`` API. For most applications, this API will be
+needed to verify that the rawdev in question is of the expected type. For
+example, the following code snippet can be used to identify an PTDMA
+rawdev device for use by an application:
+
+.. code-block:: C
+
+for (i = 0; i < count && !found; i++) {
+struct rte_rawdev_info info = { .dev_private = NULL };
+found = (rte_rawdev_info_get(i, &info, 0) == 0 &&
+strcmp(info.driver_name,
+PTDMA_PMD_RAWDEV_NAME) == 0);
+}
+
+When calling the ``rte_rawdev_info_get()`` API for an PTDMA rawdev device,
+the ``dev_private`` field in the ``rte_rawdev_info`` struct should either
+be NULL, or else be set to point to a structure of type
+``rte_ptdma_rawdev_config``, in which case the size of the configured device
+input ring will be returned in that structure.
+
+Device Configuration
+
axgbe PMD fixes and updates
Updates to axgbe pmd driver >From sseba...@amd.com # This line is ignored. From: sseba...@amd.com Reply-To: Subject: axgbe PMD fixes and updates In-Reply-To:
[PATCH v1 1/6] net/axgbe: always attempt link training in KR mode
From: Selwin Sebastian
Link training is always attempted when in KR mode, but the code is
structured to check if link training has been enabled before attempting
to perform it.Since that check will always be true, simplify the code
to always enable and start link training during KR auto-negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_mdio.c | 62 --
1 file changed, 15 insertions(+), 47 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c
index 32d8c666f9..913ceada0d 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -80,31 +80,10 @@ static void axgbe_an_clear_interrupts_all(struct axgbe_port
*pdata)
axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata)
{
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1);
@@ -114,9 +93,6 @@ static void axgbe_kr_mode(struct axgbe_port *pdata)
static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
@@ -126,9 +102,6 @@ static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
static void axgbe_kx_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -142,8 +115,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1);
@@ -154,8 +125,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
static void axgbe_x_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -166,8 +135,6 @@ static void axgbe_x_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -178,8 +145,6 @@ static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -284,6 +249,12 @@ static void axgbe_an73_set(struct axgbe_port *pdata, bool
enable,
{
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
@@ -379,20 +350,17 @@ static enum axgbe_an axgbe_an73_tx_training(struct
axgbe_port *pdata,
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg |= AXGBE_KR_TRAINING_ENABLE;
+ reg |= AXGBE_KR_TRAINING_START;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
- if (p
[PATCH v1 2/6] net/axgbe: toggle PLL settings during rate change
From: Selwin Sebastian
For each rate change command submission, the FW has to do a phy
power off sequence internally. For this to happen correctly, the
PLL re-initialization control setting has to be turned off before
sending mailbox commands and re-enabled once the command submission
is complete. Without the PLL control setting, the link up takes
longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 9 +
drivers/net/axgbe/axgbe_phy_impl.c | 22 --
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR0x
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 02236ec192..dc9489f0aa 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
+{
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
{
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
@@ -1213,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+/* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
}
--
2.25.1
[PATCH v1 3/6] net/axgbe: simplify mailbox interface rate change code
From: Selwin Sebastian
Simplify and centralize the mailbox command rate change interface by
having a single function perform the writes to the mailbox registers
to issue the request.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 --
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index dc9489f0aa..0894dbf74b 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port
*pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
-{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata)
{
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
}
@@ -1263,13 +1257,9 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n");
@@ -1278,31 +1268,21 @@ static void axgbe_phy_power_off(struct axgbe_port
*pdata)
static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
@@ -1311,22 +1291,11 @@ static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int
[PATCH v1 6/6] net/axgbe: alter the port speed bit range
From: Selwin Sebastian Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware. The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.: Before: PORT_PROPERTY_0[22:21] - Reserved PORT_PROPERTY_0[26:23] - Supported Speeds After: PORT_PROPERTY_0[21] - Reserved PORT_PROPERTY_0[26:22] - Supported Speeds To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/axgbe/axgbe_phy_impl.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index a5431dd998..5310ac54f5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1032,8 +1032,8 @@ #define XP_PROP_0_PORT_ID_WIDTH8 #define XP_PROP_0_PORT_MODE_INDEX 8 #define XP_PROP_0_PORT_MODE_WIDTH 4 -#define XP_PROP_0_PORT_SPEEDS_INDEX23 -#define XP_PROP_0_PORT_SPEEDS_WIDTH4 +#define XP_PROP_0_PORT_SPEEDS_INDEX22 +#define XP_PROP_0_PORT_SPEEDS_WIDTH5 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c index 2aad8babd2..776144696a 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -7,10 +7,10 @@ #include "axgbe_common.h" #include "axgbe_phy.h" -#define AXGBE_PHY_PORT_SPEED_100 BIT(0) -#define AXGBE_PHY_PORT_SPEED_1000 BIT(1) -#define AXGBE_PHY_PORT_SPEED_2500 BIT(2) -#define AXGBE_PHY_PORT_SPEED_1 BIT(3) +#define AXGBE_PHY_PORT_SPEED_100 BIT(1) +#define AXGBE_PHY_PORT_SPEED_1000 BIT(2) +#define AXGBE_PHY_PORT_SPEED_2500 BIT(3) +#define AXGBE_PHY_PORT_SPEED_1 BIT(4) #define AXGBE_MUTEX_RELEASE0x8000 -- 2.25.1
[PATCH v1 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
From: Selwin Sebastian
Sometimes mailbox commands timeout when the RX data path becomes
unresponsive. This prevents the submission of new mailbox commands
to DXIO. This patch identifies the timeout and resets the RX data
path so that the next message can be submitted properly.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 14 ++
drivers/net/axgbe/axgbe_phy_impl.c | 29 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLTBIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR0x
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 0894dbf74b..e52dbb9585 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
+{
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+* This can be done by asseting the reset bit and wait for
+* its compeletion.
+*/
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
{
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
@@ -1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct
axgbe_port *pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
@@ -1235,6 +1259,9 @@ static void axgbe_phy_perform_ratechange(struct
axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
[PATCH v1 5/6] net/axgbe: add support for new port mode
From: Selwin Sebastian
Add support for a new port mode that is abackplane
connection without support for auto negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index e52dbb9585..2aad8babd2 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_1baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct
axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata,
enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode);
@@ -1806,6 +1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /*fallthrough;*/
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
[PATCH v2 0/6] axgbe pmd updates
From: Selwin Sebastian some updates to axgbe pmd driver Selwin Sebastian (6): net/axgbe: always attempt link training in KR mode net/axgbe: toggle PLL settings during rate change net/axgbe: simplify mailbox interface rate change code net/axgbe: reset PHY Rx when mailbox command timeout net/axgbe: add support for new port mode net/axgbe: alter the port speed bit range drivers/net/axgbe/axgbe_common.h | 27 - drivers/net/axgbe/axgbe_mdio.c | 62 +++ drivers/net/axgbe/axgbe_phy_impl.c | 164 +++-- 3 files changed, 126 insertions(+), 127 deletions(-) -- 2.25.1
[PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
From: Selwin Sebastian
Link training is always attempted when in KR mode, but the code is
structured to check if link training has been enabled before attempting
to perform it.Since that check will always be true, simplify the code
to always enable and start link training during KR auto-negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_mdio.c | 62 --
1 file changed, 15 insertions(+), 47 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c
index 32d8c666f9..913ceada0d 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -80,31 +80,10 @@ static void axgbe_an_clear_interrupts_all(struct axgbe_port
*pdata)
axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata)
-{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata)
{
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1);
@@ -114,9 +93,6 @@ static void axgbe_kr_mode(struct axgbe_port *pdata)
static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
@@ -126,9 +102,6 @@ static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
static void axgbe_kx_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -142,8 +115,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1);
@@ -154,8 +125,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
static void axgbe_x_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -166,8 +135,6 @@ static void axgbe_x_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -178,8 +145,6 @@ static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata)
{
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -284,6 +249,12 @@ static void axgbe_an73_set(struct axgbe_port *pdata, bool
enable,
{
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
@@ -379,20 +350,17 @@ static enum axgbe_an axgbe_an73_tx_training(struct
axgbe_port *pdata,
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg |= AXGBE_KR_TRAINING_ENABLE;
+ reg |= AXGBE_KR_TRAINING_START;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
- if (p
[PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
From: Selwin Sebastian
Simplify and centralize the mailbox command rate change interface by
having a single function perform the writes to the mailbox registers
to issue the request.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 --
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 08d3484a11..2ed94868b8 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port
*pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
-{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata)
{
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n");
}
@@ -1263,13 +1257,9 @@ static void axgbe_phy_power_off(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n");
@@ -1278,31 +1268,21 @@ static void axgbe_phy_power_off(struct axgbe_port
*pdata)
static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n");
@@ -1311,22 +1291,11 @@ static void axgbe_phy_sfi_mode(struct axgbe_port *pdata)
static void axgbe_phy_kr_mode(struct axgbe_port *pdata)
{
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int
[PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
From: Selwin Sebastian
For each rate change command submission, the FW has to do a phy
power off sequence internally. For this to happen correctly, the
PLL re-initialization control setting has to be turned off before
sending mailbox commands and re-enabled once the command submission
is complete. Without the PLL control setting, the link up takes
longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 9 +
drivers/net/axgbe/axgbe_phy_impl.c | 22 --
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR0x
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 72104f8a3f..08d3484a11 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
+{
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
{
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
@@ -1213,10 +1227,14 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+/* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
}
--
2.25.1
[PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
From: Selwin Sebastian
Sometimes mailbox commands timeout when the RX data path becomes
unresponsive. This prevents the submission of new mailbox commands
to DXIO. This patch identifies the timeout and resets the RX data
path so that the next message can be submitted properly.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 14 ++
drivers/net/axgbe/axgbe_phy_impl.c | 29 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLTBIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR0x
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 2ed94868b8..eefb03e94e 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
+{
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+* This can be done by asseting the reset bit and wait for
+* its compeletion.
+*/
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
{
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
@@ -1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct
axgbe_port *pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
@@ -1235,6 +1259,9 @@ static void axgbe_phy_perform_ratechange(struct
axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
[PATCH v2 5/6] net/axgbe: add support for new port mode
From: Selwin Sebastian
Add support for a new port mode that is a backplane
connection without support for auto negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index eefb03e94e..b0e1c267b1 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_1baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct
axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata,
enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode);
@@ -1806,6 +1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /* Fallthrough */
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
[PATCH v2 6/6] net/axgbe: alter the port speed bit range
From: Selwin Sebastian Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware. The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.: Before: PORT_PROPERTY_0[22:21] - Reserved PORT_PROPERTY_0[26:23] - Supported Speeds After: PORT_PROPERTY_0[21] - Reserved PORT_PROPERTY_0[26:22] - Supported Speeds To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/axgbe/axgbe_phy_impl.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index a5431dd998..5310ac54f5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1032,8 +1032,8 @@ #define XP_PROP_0_PORT_ID_WIDTH8 #define XP_PROP_0_PORT_MODE_INDEX 8 #define XP_PROP_0_PORT_MODE_WIDTH 4 -#define XP_PROP_0_PORT_SPEEDS_INDEX23 -#define XP_PROP_0_PORT_SPEEDS_WIDTH4 +#define XP_PROP_0_PORT_SPEEDS_INDEX22 +#define XP_PROP_0_PORT_SPEEDS_WIDTH5 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c index b0e1c267b1..d97fbbfddd 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -7,10 +7,10 @@ #include "axgbe_common.h" #include "axgbe_phy.h" -#define AXGBE_PHY_PORT_SPEED_100 BIT(0) -#define AXGBE_PHY_PORT_SPEED_1000 BIT(1) -#define AXGBE_PHY_PORT_SPEED_2500 BIT(2) -#define AXGBE_PHY_PORT_SPEED_1 BIT(3) +#define AXGBE_PHY_PORT_SPEED_100 BIT(1) +#define AXGBE_PHY_PORT_SPEED_1000 BIT(2) +#define AXGBE_PHY_PORT_SPEED_2500 BIT(3) +#define AXGBE_PHY_PORT_SPEED_1 BIT(4) #define AXGBE_MUTEX_RELEASE0x8000 -- 2.25.1
[PATCH v1 1/2] net/axgbe: add support for Yellow Carp ethernet device
From: Selwin Sebastian
Yellow Carp ethernet devices (V3xxx) use the existing PCI ID but
the window settings for the indirect PCS access have been
altered. Add the check for Yellow Carp Ethernet devices to
use the new register values.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 2 ++
drivers/net/axgbe/axgbe_ethdev.c | 34 +---
2 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5310ac54f5..b9ebf64fb8 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -901,6 +901,8 @@
#define PCS_V2_WINDOW_SELECT 0x9064
#define PCS_V2_RV_WINDOW_DEF 0x1060
#define PCS_V2_RV_WINDOW_SELECT0x1064
+#define PCS_V2_YC_WINDOW_DEF 0x18060
+#define PCS_V2_YC_WINDOW_SELECT0x18064
/* PCS register entry bit positions and sizes */
#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index e9546469f3..2be9387f98 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -173,6 +173,8 @@ static const struct axgbe_xstats axgbe_xstats_strings[] = {
/* The set of PCI devices this driver supports */
#define AMD_PCI_VENDOR_ID 0x1022
#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
+#define AMD_PCI_YC_ROOT_COMPLEX_ID 0x14b5
+#define AMD_PCI_SNOWY_ROOT_COMPLEX_ID 0x1450
#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458
#define AMD_PCI_AXGBE_DEVICE_V2B 0x1459
@@ -2178,17 +2180,6 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
pdata->pci_dev = pci_dev;
- /*
-* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
-*/
- if ((get_pci_rc_devid()) == AMD_PCI_RV_ROOT_COMPLEX_ID) {
- pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
- pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
- } else {
- pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
- pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
- }
-
pdata->xgmac_regs =
(void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs
@@ -2203,6 +2194,27 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
else
pdata->vdata = &axgbe_v2b;
+ /*
+* Use PCI root complex device ID to identify the CPU
+*/
+ switch (get_pci_rc_devid()) {
+ case AMD_PCI_RV_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
+ break;
+ case AMD_PCI_YC_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
+ break;
+ case AMD_PCI_SNOWY_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "No supported devices found\n");
+ return -ENODEV;
+ }
+
/* Configure the PCS indirect addressing support */
reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
--
2.25.1
[PATCH v1 0/2] net/axgbe: Add support for Yellow Carp ethernet
From: Selwin Sebastian Adding support for Yellow Carp ethernet device Selwin Sebastian (2): net/axgbe: add support for Yellow Carp ethernet device net/axgbe: disable the CDR wa for Yellow Carp devices drivers/net/axgbe/axgbe_common.h | 2 ++ drivers/net/axgbe/axgbe_ethdev.c | 36 ++-- 2 files changed, 27 insertions(+), 11 deletions(-) -- 2.25.1
[PATCH v1 2/2] net/axgbe: disable the CDR wa for Yellow Carp devices
From: Selwin Sebastian Yellow Carp ethernet devices (V3xxx) do not require autonegotiation CDR workaround, hence disable the same. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index 2be9387f98..951da5cc26 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -2205,6 +2205,8 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) case AMD_PCI_YC_ROOT_COMPLEX_ID: pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; + /* Yellow Carp devices do not need cdr workaround */ + pdata->vdata->an_cdr_workaround = 0; break; case AMD_PCI_SNOWY_ROOT_COMPLEX_ID: pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; -- 2.25.1
[dpdk-dev] [PATCH v1] net/axgbe: add support for Scattered Rx
From: Selwin Sebastian
Enable scattered rx support and add jumbo packet transmit capability
Signed-off-by: Selwin Sebastian
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_ethdev.c | 18 +++-
drivers/net/axgbe/axgbe_rxtx.c | 146 +
drivers/net/axgbe/axgbe_rxtx.h | 2 +
5 files changed, 168 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index ab4da559f..0becaa097 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -7,6 +7,7 @@
Speed capabilities = Y
Link status = Y
Jumbo frame = Y
+Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index fdb037dd5..fbd46150c 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1135,6 +1135,8 @@
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
+#define RX_NORMAL_DESC3_LD_INDEX 28
+#define RX_NORMAL_DESC3_LD_WIDTH 1
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index d0b6f091f..eb2f51f89 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -789,11 +789,17 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_SCATTER|
DEV_RX_OFFLOAD_KEEP_CRC;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_UDP_TSO |
+ DEV_TX_OFFLOAD_SCTP_CKSUM |
+ DEV_TX_OFFLOAD_MULTI_SEGS |
DEV_TX_OFFLOAD_TCP_CKSUM;
if (pdata->hw_feat.rss) {
@@ -1018,9 +1024,19 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
struct rte_pci_device *pci_dev;
uint32_t reg, mac_lo, mac_hi;
int ret;
+ struct rte_eth_dev_info dev_info = { 0 };
eth_dev->dev_ops = &axgbe_eth_dev_ops;
- eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
+ eth_dev->dev_ops->dev_infos_get(eth_dev, &dev_info);
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_SCATTER)
+ eth_dev->data->scattered_rx = 1;
+
+ /* Scatter Rx handling */
+ if (eth_dev->data->scattered_rx)
+ eth_dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
+ else
+ eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
/*
* For secondary processes, we don't initialise any further as primary
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 96055c25b..57e2bbb34 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -307,6 +307,152 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
return nb_rx;
}
+
+uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
+ struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+ PMD_INIT_FUNC_TRACE();
+ uint16_t nb_rx = 0;
+ struct axgbe_rx_queue *rxq = rx_queue;
+ volatile union axgbe_rx_desc *desc;
+
+ uint64_t old_dirty = rxq->dirty;
+ struct rte_mbuf *first_seg = NULL;
+ struct rte_mbuf *mbuf, *tmbuf;
+ unsigned int err;
+ uint32_t error_status;
+ uint16_t idx, pidx, data_len = 0, pkt_len = 0;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ while (nb_rx < nb_pkts) {
+ bool eop = 0;
+next_desc:
+ if (unlikely(idx == rxq->nb_desc))
+ idx = 0;
+
+ desc = &rxq->desc[idx];
+
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ break;
+
+ tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
+ if (unlikely(!tmbuf)) {
+ PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
+ " queue_id = %u\n",
+ (unsigned int)rxq->port_id,
+ (unsigned int)rxq->queue_id);
+
rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
+ break;
+ }
+
+ pidx = idx + 1;
+ if (unlikely(pidx == rxq->nb_desc))
+ pidx = 0;
+
+ rte_prefetch0(rxq->sw_
[dpdk-dev] [PATCH v1] net/axgbe: add support for Scattered Rx
From: Selwin Sebastian
Enable scattered rx support and add jumbo packet transmit capability
Signed-off-by: Selwin Sebastian
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_ethdev.c | 18 +++-
drivers/net/axgbe/axgbe_rxtx.c | 146 +
drivers/net/axgbe/axgbe_rxtx.h | 2 +
5 files changed, 168 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index ab4da559f..0becaa097 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -7,6 +7,7 @@
Speed capabilities = Y
Link status = Y
Jumbo frame = Y
+Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index fdb037dd5..fbd46150c 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1135,6 +1135,8 @@
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
+#define RX_NORMAL_DESC3_LD_INDEX 28
+#define RX_NORMAL_DESC3_LD_WIDTH 1
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index d0b6f091f..eb2f51f89 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -789,11 +789,17 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_SCATTER|
DEV_RX_OFFLOAD_KEEP_CRC;
dev_info->tx_offload_capa =
DEV_TX_OFFLOAD_IPV4_CKSUM |
DEV_TX_OFFLOAD_UDP_CKSUM |
+ DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_TX_OFFLOAD_UDP_TSO |
+ DEV_TX_OFFLOAD_SCTP_CKSUM |
+ DEV_TX_OFFLOAD_MULTI_SEGS |
DEV_TX_OFFLOAD_TCP_CKSUM;
if (pdata->hw_feat.rss) {
@@ -1018,9 +1024,19 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
struct rte_pci_device *pci_dev;
uint32_t reg, mac_lo, mac_hi;
int ret;
+ struct rte_eth_dev_info dev_info = { 0 };
eth_dev->dev_ops = &axgbe_eth_dev_ops;
- eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
+ eth_dev->dev_ops->dev_infos_get(eth_dev, &dev_info);
+
+ if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_SCATTER)
+ eth_dev->data->scattered_rx = 1;
+
+ /* Scatter Rx handling */
+ if (eth_dev->data->scattered_rx)
+ eth_dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
+ else
+ eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
/*
* For secondary processes, we don't initialise any further as primary
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 96055c25b..57e2bbb34 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -307,6 +307,152 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
return nb_rx;
}
+
+uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
+ struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+ PMD_INIT_FUNC_TRACE();
+ uint16_t nb_rx = 0;
+ struct axgbe_rx_queue *rxq = rx_queue;
+ volatile union axgbe_rx_desc *desc;
+
+ uint64_t old_dirty = rxq->dirty;
+ struct rte_mbuf *first_seg = NULL;
+ struct rte_mbuf *mbuf, *tmbuf;
+ unsigned int err;
+ uint32_t error_status;
+ uint16_t idx, pidx, data_len = 0, pkt_len = 0;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ while (nb_rx < nb_pkts) {
+ bool eop = 0;
+next_desc:
+ if (unlikely(idx == rxq->nb_desc))
+ idx = 0;
+
+ desc = &rxq->desc[idx];
+
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ break;
+
+ tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
+ if (unlikely(!tmbuf)) {
+ PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
+ " queue_id = %u\n",
+ (unsigned int)rxq->port_id,
+ (unsigned int)rxq->queue_id);
+
rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
+ break;
+ }
+
+ pidx = idx + 1;
+ if (unlikely(pidx == rxq->nb_desc))
+ pidx = 0;
+
+ rte_prefetch0(rxq->sw_
[dpdk-dev] [PATCH v2] net/axgbe: add support for Scattered Rx
From: Selwin Sebastian
Enable scattered rx support and add jumbo packet receive capability
Signed-off-by: Selwin Sebastian
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_ethdev.c | 17 +++-
drivers/net/axgbe/axgbe_rxtx.c | 146 +
drivers/net/axgbe/axgbe_rxtx.h | 2 +
5 files changed, 167 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index ab4da559f..0becaa097 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -7,6 +7,7 @@
Speed capabilities = Y
Link status = Y
Jumbo frame = Y
+Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index fdb037dd5..fbd46150c 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1135,6 +1135,8 @@
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
+#define RX_NORMAL_DESC3_LD_INDEX 28
+#define RX_NORMAL_DESC3_LD_WIDTH 1
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index d0b6f091f..542003bda 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -249,6 +249,10 @@ axgbe_dev_start(struct rte_eth_dev *dev)
{
struct axgbe_port *pdata = dev->data->dev_private;
int ret;
+ struct rte_eth_dev_data *dev_data = dev->data;
+ uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len;
+
+ dev->dev_ops = &axgbe_eth_dev_ops;
PMD_INIT_FUNC_TRACE();
@@ -279,6 +283,16 @@ axgbe_dev_start(struct rte_eth_dev *dev)
axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
+ if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
+ max_pkt_len > pdata->rx_buf_size)
+ dev_data->scattered_rx = 1;
+
+ /* Scatter Rx handling */
+ if (dev_data->scattered_rx)
+ dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
+ else
+ dev->rx_pkt_burst = &axgbe_recv_pkts;
+
return 0;
}
@@ -789,6 +803,8 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_SCATTER|
DEV_RX_OFFLOAD_KEEP_CRC;
dev_info->tx_offload_capa =
@@ -1020,7 +1036,6 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
int ret;
eth_dev->dev_ops = &axgbe_eth_dev_ops;
- eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
/*
* For secondary processes, we don't initialise any further as primary
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 96055c25b..57e2bbb34 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -307,6 +307,152 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
return nb_rx;
}
+
+uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
+ struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+ PMD_INIT_FUNC_TRACE();
+ uint16_t nb_rx = 0;
+ struct axgbe_rx_queue *rxq = rx_queue;
+ volatile union axgbe_rx_desc *desc;
+
+ uint64_t old_dirty = rxq->dirty;
+ struct rte_mbuf *first_seg = NULL;
+ struct rte_mbuf *mbuf, *tmbuf;
+ unsigned int err;
+ uint32_t error_status;
+ uint16_t idx, pidx, data_len = 0, pkt_len = 0;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ while (nb_rx < nb_pkts) {
+ bool eop = 0;
+next_desc:
+ if (unlikely(idx == rxq->nb_desc))
+ idx = 0;
+
+ desc = &rxq->desc[idx];
+
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ break;
+
+ tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
+ if (unlikely(!tmbuf)) {
+ PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
+ " queue_id = %u\n",
+ (unsigned int)rxq->port_id,
+ (unsigned int)rxq->queue_id);
+
rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
+ break;
+ }
+
+ pidx = idx + 1;
+ if (unlikely(pidx == rxq->nb_desc))
+
[dpdk-dev] [PATCH v3] net/axgbe: add support for Scattered Rx
From: Selwin Sebastian
Enable scattered rx support and add jumbo packet receive capability
Signed-off-by: Selwin Sebastian
---
doc/guides/nics/features/axgbe.ini | 1 +
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_ethdev.c | 16 +++-
drivers/net/axgbe/axgbe_rxtx.c | 145 +
drivers/net/axgbe/axgbe_rxtx.h | 2 +
5 files changed, 165 insertions(+), 1 deletion(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index ab4da559f..0becaa097 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -7,6 +7,7 @@
Speed capabilities = Y
Link status = Y
Jumbo frame = Y
+Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index fdb037dd5..fbd46150c 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1135,6 +1135,8 @@
#define RX_NORMAL_DESC3_PL_WIDTH 14
#define RX_NORMAL_DESC3_RSV_INDEX 26
#define RX_NORMAL_DESC3_RSV_WIDTH 1
+#define RX_NORMAL_DESC3_LD_INDEX 28
+#define RX_NORMAL_DESC3_LD_WIDTH 1
#define RX_DESC3_L34T_IPV4_TCP 1
#define RX_DESC3_L34T_IPV4_UDP 2
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index d0b6f091f..013c6330d 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -249,6 +249,8 @@ axgbe_dev_start(struct rte_eth_dev *dev)
{
struct axgbe_port *pdata = dev->data->dev_private;
int ret;
+ struct rte_eth_dev_data *dev_data = dev->data;
+ uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len;
PMD_INIT_FUNC_TRACE();
@@ -279,6 +281,17 @@ axgbe_dev_start(struct rte_eth_dev *dev)
axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state);
axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state);
+
+ if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) ||
+ max_pkt_len > pdata->rx_buf_size)
+ dev_data->scattered_rx = 1;
+
+ /* Scatter Rx handling */
+ if (dev_data->scattered_rx)
+ dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts;
+ else
+ dev->rx_pkt_burst = &axgbe_recv_pkts;
+
return 0;
}
@@ -789,6 +802,8 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
DEV_RX_OFFLOAD_IPV4_CKSUM |
DEV_RX_OFFLOAD_UDP_CKSUM |
DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_SCATTER|
DEV_RX_OFFLOAD_KEEP_CRC;
dev_info->tx_offload_capa =
@@ -1020,7 +1035,6 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
int ret;
eth_dev->dev_ops = &axgbe_eth_dev_ops;
- eth_dev->rx_pkt_burst = &axgbe_recv_pkts;
/*
* For secondary processes, we don't initialise any further as primary
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 96055c25b..8f818eb89 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -307,6 +307,151 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
return nb_rx;
}
+uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
+ struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
+{
+ PMD_INIT_FUNC_TRACE();
+ uint16_t nb_rx = 0;
+ struct axgbe_rx_queue *rxq = rx_queue;
+ volatile union axgbe_rx_desc *desc;
+
+ uint64_t old_dirty = rxq->dirty;
+ struct rte_mbuf *first_seg = NULL;
+ struct rte_mbuf *mbuf, *tmbuf;
+ unsigned int err;
+ uint32_t error_status;
+ uint16_t idx, pidx, data_len = 0, pkt_len = 0;
+
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+ while (nb_rx < nb_pkts) {
+ bool eop = 0;
+next_desc:
+ if (unlikely(idx == rxq->nb_desc))
+ idx = 0;
+
+ desc = &rxq->desc[idx];
+
+ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN))
+ break;
+
+ tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
+ if (unlikely(!tmbuf)) {
+ PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u"
+ " queue_id = %u\n",
+ (unsigned int)rxq->port_id,
+ (unsigned int)rxq->queue_id);
+
rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
+ break;
+ }
+
+ pidx = idx + 1;
+ if (unlikely(pidx == rxq->nb_desc))
+ pidx = 0;
+
+ rte_prefetch0(rx
