[dpdk-dev] [PATCH v2] net/axgbe: add RSS reta/hash query and update
From: Chandu Babu N
add support for RSS reta/hash query and update function
v2:
modification as per Andrew Rybchenko review comments
Signed-off-by: Chandu Babu N
---
doc/guides/nics/features/axgbe.ini | 2 +
drivers/net/axgbe/axgbe_dev.c | 5 +-
drivers/net/axgbe/axgbe_ethdev.c | 144 +
drivers/net/axgbe/axgbe_ethdev.h | 3 +
4 files changed, 152 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index 0becaa097..34df0d1ee 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -11,6 +11,8 @@ Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
+RSS key update = Y
+RSS reta update = Y
CRC offload = Y
L3 checksum offload = Y
L4 checksum offload = Y
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 5f0f19592..af62eae3b 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -614,7 +614,7 @@ static int axgbe_write_rss_reg(struct axgbe_port *pdata,
unsigned int type,
return -EBUSY;
}
-static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
+int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
{
struct rte_eth_rss_conf *rss_conf;
unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
@@ -638,7 +638,7 @@ static int axgbe_write_rss_hash_key(struct axgbe_port
*pdata)
return 0;
}
-static int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
+int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
{
unsigned int i;
int ret;
@@ -683,6 +683,7 @@ static void axgbe_rss_options(struct axgbe_port *pdata)
uint64_t rss_hf;
rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
+ pdata->rss_hf = rss_conf->rss_hf;
rss_hf = rss_conf->rss_hf;
if (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6))
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867058845..619250fb0 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -60,6 +60,16 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
const uint64_t *ids,
unsigned int size);
static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
+static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
+struct rte_eth_rss_reta_entry64 *reta_conf,
+uint16_t reta_size);
+static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
+struct rte_eth_rss_conf *rss_conf);
+static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf);
static int axgbe_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
@@ -201,6 +211,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.xstats_get_names = axgbe_dev_xstats_get_names,
.xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
.xstats_get_by_id = axgbe_dev_xstats_get_by_id,
+ .reta_update = axgbe_dev_rss_reta_update,
+ .reta_query = axgbe_dev_rss_reta_query,
+ .rss_hash_update = axgbe_dev_rss_hash_update,
+ .rss_hash_conf_get= axgbe_dev_rss_hash_conf_get,
.dev_infos_get= axgbe_dev_info_get,
.rx_queue_setup = axgbe_dev_rx_queue_setup,
.rx_queue_release = axgbe_dev_rx_queue_release,
@@ -450,6 +464,136 @@ axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct
rte_ether_addr *mac_addr,
return 0;
}
+static int
+axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int i, idx, shift;
+ int ret;
+
+ if (!pdata->rss_enable) {
+ PMD_DRV_LOG(ERR, "RSS not enabled\n");
+ return -ENOTSUP;
+ }
+
+ if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
+ PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ shift = i % RTE_RETA_GROUP_SIZE;
+ if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
+
[dpdk-dev] [PATCH v2] net/axgbe: add RSS reta/hash query and update
From: Chandu Babu N
add support for RSS reta/hash query and update function
v2:
modification as per Andrew Rybchenko review comments
Signed-off-by: Chandu Babu N
---
doc/guides/nics/features/axgbe.ini | 2 +
drivers/net/axgbe/axgbe_dev.c | 5 +-
drivers/net/axgbe/axgbe_ethdev.c | 144 +
drivers/net/axgbe/axgbe_ethdev.h | 3 +
4 files changed, 152 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/features/axgbe.ini
b/doc/guides/nics/features/axgbe.ini
index 0becaa097..34df0d1ee 100644
--- a/doc/guides/nics/features/axgbe.ini
+++ b/doc/guides/nics/features/axgbe.ini
@@ -11,6 +11,8 @@ Scattered Rx = Y
Promiscuous mode = Y
Allmulticast mode= Y
RSS hash = Y
+RSS key update = Y
+RSS reta update = Y
CRC offload = Y
L3 checksum offload = Y
L4 checksum offload = Y
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 5f0f19592..af62eae3b 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -614,7 +614,7 @@ static int axgbe_write_rss_reg(struct axgbe_port *pdata,
unsigned int type,
return -EBUSY;
}
-static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
+int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
{
struct rte_eth_rss_conf *rss_conf;
unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
@@ -638,7 +638,7 @@ static int axgbe_write_rss_hash_key(struct axgbe_port
*pdata)
return 0;
}
-static int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
+int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
{
unsigned int i;
int ret;
@@ -683,6 +683,7 @@ static void axgbe_rss_options(struct axgbe_port *pdata)
uint64_t rss_hf;
rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
+ pdata->rss_hf = rss_conf->rss_hf;
rss_hf = rss_conf->rss_hf;
if (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6))
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867058845..619250fb0 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -60,6 +60,16 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
const uint64_t *ids,
unsigned int size);
static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
+static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
+struct rte_eth_rss_reta_entry64 *reta_conf,
+uint16_t reta_size);
+static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
+struct rte_eth_rss_conf *rss_conf);
+static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf);
static int axgbe_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
@@ -201,6 +211,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.xstats_get_names = axgbe_dev_xstats_get_names,
.xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
.xstats_get_by_id = axgbe_dev_xstats_get_by_id,
+ .reta_update = axgbe_dev_rss_reta_update,
+ .reta_query = axgbe_dev_rss_reta_query,
+ .rss_hash_update = axgbe_dev_rss_hash_update,
+ .rss_hash_conf_get= axgbe_dev_rss_hash_conf_get,
.dev_infos_get= axgbe_dev_info_get,
.rx_queue_setup = axgbe_dev_rx_queue_setup,
.rx_queue_release = axgbe_dev_rx_queue_release,
@@ -450,6 +464,136 @@ axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct
rte_ether_addr *mac_addr,
return 0;
}
+static int
+axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int i, idx, shift;
+ int ret;
+
+ if (!pdata->rss_enable) {
+ PMD_DRV_LOG(ERR, "RSS not enabled\n");
+ return -ENOTSUP;
+ }
+
+ if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
+ PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ shift = i % RTE_RETA_GROUP_SIZE;
+ if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
+
[dpdk-dev] [PATCH v1] net/axgbe: add register dump support
From: Chandu Babu N
Implement "get_reg" eth_dev_ops for axgbe
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_common.h | 3 +
drivers/net/axgbe/axgbe_ethdev.c | 25
drivers/net/axgbe/axgbe_regs.h | 229 +++
3 files changed, 257 insertions(+)
create mode 100644 drivers/net/axgbe/axgbe_regs.h
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index fdb037dd5..2ac4d8946 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -289,6 +289,9 @@
#define MAC_RQC2_INC 4
#define MAC_RQC2_Q_PER_REG 4
+#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
+#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
+
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7445c544d..00974e737 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -7,6 +7,7 @@
#include "axgbe_ethdev.h"
#include "axgbe_common.h"
#include "axgbe_phy.h"
+#include "axgbe_regs.h"
static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev);
static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev);
@@ -21,6 +22,8 @@ static int axgbe_dev_allmulticast_enable(struct rte_eth_dev
*dev);
static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
static int axgbe_dev_link_update(struct rte_eth_dev *dev,
int wait_to_complete);
+static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
+ struct rte_dev_reg_info *regs);
static int axgbe_dev_stats_get(struct rte_eth_dev *dev,
struct rte_eth_stats *stats);
static int axgbe_dev_stats_reset(struct rte_eth_dev *dev);
@@ -158,6 +161,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.allmulticast_enable = axgbe_dev_allmulticast_enable,
.allmulticast_disable = axgbe_dev_allmulticast_disable,
.link_update = axgbe_dev_link_update,
+ .get_reg = axgbe_dev_get_regs,
.stats_get= axgbe_dev_stats_get,
.stats_reset = axgbe_dev_stats_reset,
.xstats_get = axgbe_dev_xstats_get,
@@ -393,6 +397,27 @@ axgbe_dev_link_update(struct rte_eth_dev *dev,
return ret;
}
+static int
+axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ if (regs->data == NULL) {
+ regs->length = axgbe_regs_get_count(pdata);
+ regs->width = sizeof(uint32_t);
+ return 0;
+ }
+
+ /* Only full register dump is supported */
+ if (regs->length &&
+ regs->length != (uint32_t)axgbe_regs_get_count(pdata))
+ return -ENOTSUP;
+
+ regs->version = pdata->pci_dev->id.vendor_id << 16 |
+ pdata->pci_dev->id.device_id;
+ axgbe_regs_dump(pdata, regs->data);
+ return 0;
+}
static void axgbe_read_mmc_stats(struct axgbe_port *pdata)
{
struct axgbe_mmc_stats *stats = &pdata->mmc_stats;
diff --git a/drivers/net/axgbe/axgbe_regs.h b/drivers/net/axgbe/axgbe_regs.h
new file mode 100644
index 0..c7e032620
--- /dev/null
+++ b/drivers/net/axgbe/axgbe_regs.h
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Advanced Micro Devices, Inc. All rights reserved.
+ */
+#ifndef RTE_ETH_AXGBE_REGS_H_
+#define RTE_ETH_AXGBE_REGS_H_
+
+#include "axgbe_common.h"
+
+static const uint32_t dma_reg_tbl[] = {
+ DMA_MR, /* DMA Mode */
+ DMA_SBMR, /* DMA Sys Bus Mode */
+ DMA_ISR,/* DMA Interrupt Status */
+ DMA_AXIARCR,/* DMA AXI Tx AR ACE Ctrl */
+ DMA_AXIAWCR,/* DMA AXI Rx AW ACE Ctrl */
+ DMA_AXIAWRCR, /* DMA AXI TxRx AWR ACE Ctrl */
+ DMA_DSR0, /* DMA Debug Status0 */
+ DMA_DSR1, /* DMA Debug Status1 */
+ EDMA_TX_CONTROL,/* DMA Tx EDMA Ctrl */
+ EDMA_RX_CONTROL,/* DMA Rx EDMA Ctrl */
+};
+
+static const uint32_t dma_txch_reg_tbl[] = {
+ DMA_CH_CR, /* DMA Channel Ctrl */
+ DMA_CH_TCR, /* DMA Tx Ctrl */
+ DMA_CH_TDLR_HI, /* DMA TxDescList HAddr */
+ DMA_CH_TDLR_LO, /* DMA TxDescList LAddr */
+ DMA_CH_TDTR_LO, /* DMA TxDescTail LAddr */
+ DMA_CH_TDRLR, /* DMA TxDescRing Length */
+ DMA_CH_IER, /* DMA Interrupt Enable */
+ DMA_CH_CATDR_LO,/* DMA CurrApp TxDesc LAddr */
+ DMA_CH_CATBR_HI,/* DMA CurrApp TxBuf HAddr */
+ DMA_CH_CATBR_LO,/* DMA CurrApp TxBuf LAddr */
+ DMA_CH_SR, /* DMA Channel Status */
+};
+
+static const uint32_t dma_rxch_reg_tbl[] = {
+
[dpdk-dev] [PATCH v1 1/2] net/axgbe: add additional MAC address support
From: Chandu Babu N
Supports adding MAC addresses to enable whitelist filtering to
accept packets
implement eth_dev_ops mac_addr_set, mac_addr_add, mac_addr_remove and
set_mc_addr_list
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_dev.c| 29 ++
drivers/net/axgbe/axgbe_ethdev.c | 94 ++--
drivers/net/axgbe/axgbe_ethdev.h | 4 +-
3 files changed, 121 insertions(+), 6 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 2e796c0b3..f830b7230 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,35 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
+{
+ unsigned int mac_addr_hi, mac_addr_lo;
+ u8 *mac_addr;
+
+ mac_addr_lo = 0;
+ mac_addr_hi = 0;
+
+ if (addr) {
+ mac_addr = (u8 *)&mac_addr_lo;
+ mac_addr[0] = addr[0];
+ mac_addr[1] = addr[1];
+ mac_addr[2] = addr[2];
+ mac_addr[3] = addr[3];
+ mac_addr = (u8 *)&mac_addr_hi;
+ mac_addr[0] = addr[4];
+ mac_addr[1] = addr[5];
+
+ /*Address Enable: Use this Addr for Perfect Filtering */
+ AXGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
+ }
+
+ PMD_DRV_LOG(DEBUG, "%s mac address at %#x\n",
+ addr ? "set" : "clear", index);
+
+ AXGMAC_IOWRITE(pdata, MAC_MACAHR(index), mac_addr_hi);
+ AXGMAC_IOWRITE(pdata, MAC_MACALR(index), mac_addr_lo);
+}
+
static int axgbe_set_mac_address(struct axgbe_port *pdata, u8 *addr)
{
unsigned int mac_addr_hi, mac_addr_lo;
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 00974e737..34cc0fbb8 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -20,6 +20,16 @@ static int axgbe_dev_promiscuous_enable(struct rte_eth_dev
*dev);
static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
+static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr);
+static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint32_t index,
+ uint32_t vmdq);
+static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
+static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr);
static int axgbe_dev_link_update(struct rte_eth_dev *dev,
int wait_to_complete);
static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
@@ -160,6 +170,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.promiscuous_disable = axgbe_dev_promiscuous_disable,
.allmulticast_enable = axgbe_dev_allmulticast_enable,
.allmulticast_disable = axgbe_dev_allmulticast_disable,
+ .mac_addr_set = axgbe_dev_mac_addr_set,
+ .mac_addr_add = axgbe_dev_mac_addr_add,
+ .mac_addr_remove = axgbe_dev_mac_addr_remove,
+ .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
.link_update = axgbe_dev_link_update,
.get_reg = axgbe_dev_get_regs,
.stats_get= axgbe_dev_stats_get,
@@ -370,6 +384,74 @@ axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
return 0;
}
+static int
+axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ /* Set Default MAC Addr */
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
+
+ return 0;
+}
+
+static int
+axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr,
+ uint32_t index, uint32_t pool __rte_unused)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_mac) {
+ PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
+ return -EINVAL;
+ }
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
+ return 0;
+}
+
+static void
+axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_
[dpdk-dev] [PATCH v1 2/2] net/axgbe: add unicast hash table for mac address
From: Chandu Babu N
implement eth_dev_ops uc_hash_table_set and uc_all_hash_table_set
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_dev.c| 60
drivers/net/axgbe/axgbe_ethdev.c | 79
drivers/net/axgbe/axgbe_ethdev.h | 10 +++-
4 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 2ac4d8946..72683aa65 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -292,6 +292,8 @@
#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
+#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
+
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index f830b7230..5f0f19592 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,50 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+static uint32_t bitrev32(uint32_t x)
+{
+ x = (x >> 16) | (x << 16);
+ x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
+ x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
+ x = (((x & 0x) >> 2) | ((x & 0x) << 2));
+ x = (((x & 0x) >> 1) | ((x & 0x) << 1));
+ return x;
+}
+
+static uint32_t crc32_le(uint32_t crc, uint8_t *p, uint32_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ }
+ return crc;
+}
+
+void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add)
+{
+ uint32_t crc, htable_index, htable_bitmask;
+
+ crc = bitrev32(~crc32_le(~0, addr, RTE_ETHER_ADDR_LEN));
+ crc >>= pdata->hash_table_shift;
+ htable_index = crc >> 5;
+ htable_bitmask = 1 << (crc & 0x1f);
+
+ if (add) {
+ pdata->uc_hash_table[htable_index] |= htable_bitmask;
+ pdata->uc_hash_mac_addr++;
+ } else {
+ pdata->uc_hash_table[htable_index] &= ~htable_bitmask;
+ pdata->uc_hash_mac_addr--;
+ }
+ PMD_DRV_LOG(DEBUG, "%s MAC hash table Bit %d at Index %#x\n",
+ add ? "set" : "clear", (crc & 0x1f), htable_index);
+
+ AXGMAC_IOWRITE(pdata, MAC_HTR(htable_index),
+ pdata->uc_hash_table[htable_index]);
+}
+
void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
{
unsigned int mac_addr_hi, mac_addr_lo;
@@ -1051,6 +1095,21 @@ static int axgbe_set_mac_address(struct axgbe_port
*pdata, u8 *addr)
return 0;
}
+static void axgbe_config_mac_hash_table(struct axgbe_port *pdata)
+{
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ pdata->hash_table_shift = 0;
+ pdata->hash_table_count = 0;
+ pdata->uc_hash_mac_addr = 0;
+ memset(pdata->uc_hash_table, 0, sizeof(pdata->uc_hash_table));
+
+ if (hw_feat->hash_table_size) {
+ pdata->hash_table_shift = 26 - (hw_feat->hash_table_size >> 7);
+ pdata->hash_table_count = hw_feat->hash_table_size / 32;
+ }
+}
+
static void axgbe_config_mac_address(struct axgbe_port *pdata)
{
axgbe_set_mac_address(pdata, pdata->mac_addr.addr_bytes);
@@ -1129,6 +1188,7 @@ static int axgbe_init(struct axgbe_port *pdata)
axgbe_enable_mtl_interrupts(pdata);
/* Initialize MAC related features */
+ axgbe_config_mac_hash_table(pdata);
axgbe_config_mac_address(pdata);
axgbe_config_jumbo_enable(pdata);
axgbe_config_flow_control(pdata);
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 34cc0fbb8..a1d048a9d 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -30,6 +30,11 @@ static void axgbe_dev_mac_addr_remove(struct rte_eth_dev
*dev, uint32_t index);
static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addr_set,
uint32_t nb_mc_addr);
+static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint8_t add);
+static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
+ uint8_t add);
static int
[dpdk-dev] [PATCH v1 2/2] net/axgbe: add unicast hash table for mac address
From: Chandu Babu N
implement eth_dev_ops uc_hash_table_set and uc_all_hash_table_set
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_dev.c| 60
drivers/net/axgbe/axgbe_ethdev.c | 79
drivers/net/axgbe/axgbe_ethdev.h | 10 +++-
4 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 2ac4d8946..72683aa65 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -292,6 +292,8 @@
#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
+#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
+
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index f830b7230..5f0f19592 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,50 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+static uint32_t bitrev32(uint32_t x)
+{
+ x = (x >> 16) | (x << 16);
+ x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
+ x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
+ x = (((x & 0x) >> 2) | ((x & 0x) << 2));
+ x = (((x & 0x) >> 1) | ((x & 0x) << 1));
+ return x;
+}
+
+static uint32_t crc32_le(uint32_t crc, uint8_t *p, uint32_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ }
+ return crc;
+}
+
+void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add)
+{
+ uint32_t crc, htable_index, htable_bitmask;
+
+ crc = bitrev32(~crc32_le(~0, addr, RTE_ETHER_ADDR_LEN));
+ crc >>= pdata->hash_table_shift;
+ htable_index = crc >> 5;
+ htable_bitmask = 1 << (crc & 0x1f);
+
+ if (add) {
+ pdata->uc_hash_table[htable_index] |= htable_bitmask;
+ pdata->uc_hash_mac_addr++;
+ } else {
+ pdata->uc_hash_table[htable_index] &= ~htable_bitmask;
+ pdata->uc_hash_mac_addr--;
+ }
+ PMD_DRV_LOG(DEBUG, "%s MAC hash table Bit %d at Index %#x\n",
+ add ? "set" : "clear", (crc & 0x1f), htable_index);
+
+ AXGMAC_IOWRITE(pdata, MAC_HTR(htable_index),
+ pdata->uc_hash_table[htable_index]);
+}
+
void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
{
unsigned int mac_addr_hi, mac_addr_lo;
@@ -1051,6 +1095,21 @@ static int axgbe_set_mac_address(struct axgbe_port
*pdata, u8 *addr)
return 0;
}
+static void axgbe_config_mac_hash_table(struct axgbe_port *pdata)
+{
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ pdata->hash_table_shift = 0;
+ pdata->hash_table_count = 0;
+ pdata->uc_hash_mac_addr = 0;
+ memset(pdata->uc_hash_table, 0, sizeof(pdata->uc_hash_table));
+
+ if (hw_feat->hash_table_size) {
+ pdata->hash_table_shift = 26 - (hw_feat->hash_table_size >> 7);
+ pdata->hash_table_count = hw_feat->hash_table_size / 32;
+ }
+}
+
static void axgbe_config_mac_address(struct axgbe_port *pdata)
{
axgbe_set_mac_address(pdata, pdata->mac_addr.addr_bytes);
@@ -1129,6 +1188,7 @@ static int axgbe_init(struct axgbe_port *pdata)
axgbe_enable_mtl_interrupts(pdata);
/* Initialize MAC related features */
+ axgbe_config_mac_hash_table(pdata);
axgbe_config_mac_address(pdata);
axgbe_config_jumbo_enable(pdata);
axgbe_config_flow_control(pdata);
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 34cc0fbb8..a1d048a9d 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -30,6 +30,11 @@ static void axgbe_dev_mac_addr_remove(struct rte_eth_dev
*dev, uint32_t index);
static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addr_set,
uint32_t nb_mc_addr);
+static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint8_t add);
+static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
+ uint8_t add);
static int
[dpdk-dev] [PATCH v1 1/2] net/axgbe: add additional MAC address support
From: Chandu Babu N
Supports adding MAC addresses to enable whitelist filtering to
accept packets
implement eth_dev_ops mac_addr_set, mac_addr_add, mac_addr_remove and
set_mc_addr_list
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_dev.c| 29 ++
drivers/net/axgbe/axgbe_ethdev.c | 94 ++--
drivers/net/axgbe/axgbe_ethdev.h | 4 +-
3 files changed, 121 insertions(+), 6 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 2e796c0b3..f830b7230 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,35 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
+{
+ unsigned int mac_addr_hi, mac_addr_lo;
+ u8 *mac_addr;
+
+ mac_addr_lo = 0;
+ mac_addr_hi = 0;
+
+ if (addr) {
+ mac_addr = (u8 *)&mac_addr_lo;
+ mac_addr[0] = addr[0];
+ mac_addr[1] = addr[1];
+ mac_addr[2] = addr[2];
+ mac_addr[3] = addr[3];
+ mac_addr = (u8 *)&mac_addr_hi;
+ mac_addr[0] = addr[4];
+ mac_addr[1] = addr[5];
+
+ /*Address Enable: Use this Addr for Perfect Filtering */
+ AXGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
+ }
+
+ PMD_DRV_LOG(DEBUG, "%s mac address at %#x\n",
+ addr ? "set" : "clear", index);
+
+ AXGMAC_IOWRITE(pdata, MAC_MACAHR(index), mac_addr_hi);
+ AXGMAC_IOWRITE(pdata, MAC_MACALR(index), mac_addr_lo);
+}
+
static int axgbe_set_mac_address(struct axgbe_port *pdata, u8 *addr)
{
unsigned int mac_addr_hi, mac_addr_lo;
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 00974e737..34cc0fbb8 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -20,6 +20,16 @@ static int axgbe_dev_promiscuous_enable(struct rte_eth_dev
*dev);
static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
+static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr);
+static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint32_t index,
+ uint32_t vmdq);
+static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
+static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr);
static int axgbe_dev_link_update(struct rte_eth_dev *dev,
int wait_to_complete);
static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
@@ -160,6 +170,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.promiscuous_disable = axgbe_dev_promiscuous_disable,
.allmulticast_enable = axgbe_dev_allmulticast_enable,
.allmulticast_disable = axgbe_dev_allmulticast_disable,
+ .mac_addr_set = axgbe_dev_mac_addr_set,
+ .mac_addr_add = axgbe_dev_mac_addr_add,
+ .mac_addr_remove = axgbe_dev_mac_addr_remove,
+ .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
.link_update = axgbe_dev_link_update,
.get_reg = axgbe_dev_get_regs,
.stats_get= axgbe_dev_stats_get,
@@ -370,6 +384,74 @@ axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
return 0;
}
+static int
+axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ /* Set Default MAC Addr */
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
+
+ return 0;
+}
+
+static int
+axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr,
+ uint32_t index, uint32_t pool __rte_unused)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_mac) {
+ PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
+ return -EINVAL;
+ }
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
+ return 0;
+}
+
+static void
+axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_
[dpdk-dev] [PATCH v1 2/2] net/axgbe: add unicast hash table for mac address
From: Chandu Babu N
implement eth_dev_ops uc_hash_table_set and uc_all_hash_table_set
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_common.h | 2 +
drivers/net/axgbe/axgbe_dev.c| 60
drivers/net/axgbe/axgbe_ethdev.c | 79
drivers/net/axgbe/axgbe_ethdev.h | 10 +++-
4 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 2ac4d8946..72683aa65 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -292,6 +292,8 @@
#define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8))
#define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8))
+#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC))
+
/* MAC register entry bit positions and sizes */
#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index f830b7230..5f0f19592 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,50 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+static uint32_t bitrev32(uint32_t x)
+{
+ x = (x >> 16) | (x << 16);
+ x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
+ x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
+ x = (((x & 0x) >> 2) | ((x & 0x) << 2));
+ x = (((x & 0x) >> 1) | ((x & 0x) << 1));
+ return x;
+}
+
+static uint32_t crc32_le(uint32_t crc, uint8_t *p, uint32_t len)
+{
+ int i;
+ while (len--) {
+ crc ^= *p++;
+ for (i = 0; i < 8; i++)
+ crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
+ }
+ return crc;
+}
+
+void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add)
+{
+ uint32_t crc, htable_index, htable_bitmask;
+
+ crc = bitrev32(~crc32_le(~0, addr, RTE_ETHER_ADDR_LEN));
+ crc >>= pdata->hash_table_shift;
+ htable_index = crc >> 5;
+ htable_bitmask = 1 << (crc & 0x1f);
+
+ if (add) {
+ pdata->uc_hash_table[htable_index] |= htable_bitmask;
+ pdata->uc_hash_mac_addr++;
+ } else {
+ pdata->uc_hash_table[htable_index] &= ~htable_bitmask;
+ pdata->uc_hash_mac_addr--;
+ }
+ PMD_DRV_LOG(DEBUG, "%s MAC hash table Bit %d at Index %#x\n",
+ add ? "set" : "clear", (crc & 0x1f), htable_index);
+
+ AXGMAC_IOWRITE(pdata, MAC_HTR(htable_index),
+ pdata->uc_hash_table[htable_index]);
+}
+
void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
{
unsigned int mac_addr_hi, mac_addr_lo;
@@ -1051,6 +1095,21 @@ static int axgbe_set_mac_address(struct axgbe_port
*pdata, u8 *addr)
return 0;
}
+static void axgbe_config_mac_hash_table(struct axgbe_port *pdata)
+{
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ pdata->hash_table_shift = 0;
+ pdata->hash_table_count = 0;
+ pdata->uc_hash_mac_addr = 0;
+ memset(pdata->uc_hash_table, 0, sizeof(pdata->uc_hash_table));
+
+ if (hw_feat->hash_table_size) {
+ pdata->hash_table_shift = 26 - (hw_feat->hash_table_size >> 7);
+ pdata->hash_table_count = hw_feat->hash_table_size / 32;
+ }
+}
+
static void axgbe_config_mac_address(struct axgbe_port *pdata)
{
axgbe_set_mac_address(pdata, pdata->mac_addr.addr_bytes);
@@ -1129,6 +1188,7 @@ static int axgbe_init(struct axgbe_port *pdata)
axgbe_enable_mtl_interrupts(pdata);
/* Initialize MAC related features */
+ axgbe_config_mac_hash_table(pdata);
axgbe_config_mac_address(pdata);
axgbe_config_jumbo_enable(pdata);
axgbe_config_flow_control(pdata);
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 34cc0fbb8..a1d048a9d 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -30,6 +30,11 @@ static void axgbe_dev_mac_addr_remove(struct rte_eth_dev
*dev, uint32_t index);
static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
struct rte_ether_addr *mc_addr_set,
uint32_t nb_mc_addr);
+static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint8_t add);
+static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev,
+ uint8_t add);
static int
[dpdk-dev] [PATCH v1 1/2] net/axgbe: add additional MAC address support
From: Chandu Babu N
Supports adding MAC addresses to enable whitelist filtering to
accept packets
implement eth_dev_ops mac_addr_set, mac_addr_add, mac_addr_remove and
set_mc_addr_list
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_dev.c| 29 ++
drivers/net/axgbe/axgbe_ethdev.c | 94 ++--
drivers/net/axgbe/axgbe_ethdev.h | 4 +-
3 files changed, 121 insertions(+), 6 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 2e796c0b3..f830b7230 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -1008,6 +1008,35 @@ static void axgbe_enable_mtl_interrupts(struct
axgbe_port *pdata)
}
}
+void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t
index)
+{
+ unsigned int mac_addr_hi, mac_addr_lo;
+ u8 *mac_addr;
+
+ mac_addr_lo = 0;
+ mac_addr_hi = 0;
+
+ if (addr) {
+ mac_addr = (u8 *)&mac_addr_lo;
+ mac_addr[0] = addr[0];
+ mac_addr[1] = addr[1];
+ mac_addr[2] = addr[2];
+ mac_addr[3] = addr[3];
+ mac_addr = (u8 *)&mac_addr_hi;
+ mac_addr[0] = addr[4];
+ mac_addr[1] = addr[5];
+
+ /*Address Enable: Use this Addr for Perfect Filtering */
+ AXGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
+ }
+
+ PMD_DRV_LOG(DEBUG, "%s mac address at %#x\n",
+ addr ? "set" : "clear", index);
+
+ AXGMAC_IOWRITE(pdata, MAC_MACAHR(index), mac_addr_hi);
+ AXGMAC_IOWRITE(pdata, MAC_MACALR(index), mac_addr_lo);
+}
+
static int axgbe_set_mac_address(struct axgbe_port *pdata, u8 *addr)
{
unsigned int mac_addr_hi, mac_addr_lo;
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 00974e737..34cc0fbb8 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -20,6 +20,16 @@ static int axgbe_dev_promiscuous_enable(struct rte_eth_dev
*dev);
static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
+static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr);
+static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mac_addr,
+ uint32_t index,
+ uint32_t vmdq);
+static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
+static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
+ struct rte_ether_addr *mc_addr_set,
+ uint32_t nb_mc_addr);
static int axgbe_dev_link_update(struct rte_eth_dev *dev,
int wait_to_complete);
static int axgbe_dev_get_regs(struct rte_eth_dev *dev,
@@ -160,6 +170,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.promiscuous_disable = axgbe_dev_promiscuous_disable,
.allmulticast_enable = axgbe_dev_allmulticast_enable,
.allmulticast_disable = axgbe_dev_allmulticast_disable,
+ .mac_addr_set = axgbe_dev_mac_addr_set,
+ .mac_addr_add = axgbe_dev_mac_addr_add,
+ .mac_addr_remove = axgbe_dev_mac_addr_remove,
+ .set_mc_addr_list = axgbe_dev_set_mc_addr_list,
.link_update = axgbe_dev_link_update,
.get_reg = axgbe_dev_get_regs,
.stats_get= axgbe_dev_stats_get,
@@ -370,6 +384,74 @@ axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
return 0;
}
+static int
+axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+
+ /* Set Default MAC Addr */
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0);
+
+ return 0;
+}
+
+static int
+axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr
*mac_addr,
+ uint32_t index, uint32_t pool __rte_unused)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_mac) {
+ PMD_DRV_LOG(ERR, "Invalid Index %d\n", index);
+ return -EINVAL;
+ }
+ axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index);
+ return 0;
+}
+
+static void
+axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ struct axgbe_hw_features *hw_feat = &pdata->hw_feat;
+
+ if (index > hw_feat->addn_
[dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query and update
From: Chandu Babu N
add support for RSS ethdev_ops reta_update, reta_query
rss_hash_update, rss_hash_conf_get
Signed-off-by: Chandu Babu N
---
drivers/net/axgbe/axgbe_dev.c| 5 +-
drivers/net/axgbe/axgbe_ethdev.c | 146 +++
drivers/net/axgbe/axgbe_ethdev.h | 3 +
3 files changed, 152 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
index 5f0f19592..af62eae3b 100644
--- a/drivers/net/axgbe/axgbe_dev.c
+++ b/drivers/net/axgbe/axgbe_dev.c
@@ -614,7 +614,7 @@ static int axgbe_write_rss_reg(struct axgbe_port *pdata,
unsigned int type,
return -EBUSY;
}
-static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
+int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
{
struct rte_eth_rss_conf *rss_conf;
unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
@@ -638,7 +638,7 @@ static int axgbe_write_rss_hash_key(struct axgbe_port
*pdata)
return 0;
}
-static int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
+int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
{
unsigned int i;
int ret;
@@ -683,6 +683,7 @@ static void axgbe_rss_options(struct axgbe_port *pdata)
uint64_t rss_hf;
rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
+ pdata->rss_hf = rss_conf->rss_hf;
rss_hf = rss_conf->rss_hf;
if (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6))
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 867058845..f42bb7a0d 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -60,6 +60,18 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
const uint64_t *ids,
unsigned int size);
static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
+static int
+axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size);
+static int
+axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
+struct rte_eth_rss_reta_entry64 *reta_conf,
+uint16_t reta_size);
+static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
+struct rte_eth_rss_conf *rss_conf);
+static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
+ struct rte_eth_rss_conf *rss_conf);
static int axgbe_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev,
@@ -201,6 +213,10 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = {
.xstats_get_names = axgbe_dev_xstats_get_names,
.xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
.xstats_get_by_id = axgbe_dev_xstats_get_by_id,
+ .reta_update = axgbe_dev_rss_reta_update,
+ .reta_query = axgbe_dev_rss_reta_query,
+ .rss_hash_update = axgbe_dev_rss_hash_update,
+ .rss_hash_conf_get= axgbe_dev_rss_hash_conf_get,
.dev_infos_get= axgbe_dev_info_get,
.rx_queue_setup = axgbe_dev_rx_queue_setup,
.rx_queue_release = axgbe_dev_rx_queue_release,
@@ -450,6 +466,136 @@ axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct
rte_ether_addr *mac_addr,
return 0;
}
+static int
+axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
+ struct rte_eth_rss_reta_entry64 *reta_conf,
+ uint16_t reta_size)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int i, idx, shift;
+ int ret;
+
+ if (!pdata->rss_enable) {
+ PMD_DRV_LOG(ERR, "RSS not enabled\n");
+ return -ENOTSUP;
+ }
+
+ if (!reta_size || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) {
+ PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ shift = i % RTE_RETA_GROUP_SIZE;
+ if ((reta_conf[idx].mask & (1ULL << shift)) == 0)
+ continue;
+ pdata->rss_table[i] = reta_conf[idx].reta[shift];
+ }
+
+ /* Program the lookup table */
+ ret = axgbe_write_rss_lookup_table(pdata);
+ return ret;
+}
+
+static int
+axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
+struct rte_eth_rss_reta_entry64 *reta_conf,
+uint16_t reta_size)
+{
+ struct axgbe_port *pdata = dev->data->dev_private;
+ unsigned int i, idx, shift;
+
+ if (!pdata->rss_enable) {
RE: [PATCH v2] net/axgbe: use PCI root complex device to distinguish AMD hardware
[Public]
Hi,
Gentle reminder.
This is patch is required to submit changes for new AMD products. Please review
and let us know if any modification are required.
Regards,
Chandu
-Original Message-
From: Namburu, Chandu-babu
Sent: Wednesday, December 22, 2021 2:58 PM
To: dev@dpdk.org; david.march...@redhat.com; ferruh.yi...@intel.com
Cc: Sebastian, Selwin ; arsalan_a...@mentor.com;
sta...@dpdk.org
Subject: RE: [PATCH v2] net/axgbe: use PCI root complex device to distinguish
AMD hardware
[Public]
Hi David Marchand,
I have submitted v2 patch with your suggestion in git log. Please review
changes.
Regards,
Chandu
-Original Message-
From: Namburu, Chandu-babu
Sent: Thursday, December 2, 2021 9:41 PM
To: dev@dpdk.org; david.march...@redhat.com
Cc: Sebastian, Selwin ; arsalan_a...@mentor.com;
ferruh.yi...@intel.com; Namburu, Chandu-babu ; sta...@dpdk.org
Subject: [PATCH v2] net/axgbe: use PCI root complex device to distinguish AMD
hardware
"bus/pci: optimize bus scan" broke axgbe on V1000/R1000.
RV root complex pci device does not have any kernel driver assigned so it is
removed from pci scan list which is used in
"net/axgbe: add a HW quirk for register definitions".
Get root complex device id directly from pci sysfs instead of pci scan list.
Fixes: 991e0b1dbc4a (net/axgbe: add a HW quirk for register definitions)
Cc: sta...@dpdk.org
Signed-off-by: Chandubabu Namburu
---
drivers/net/axgbe/axgbe_ethdev.c | 39
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7d40c18a86..7b8d94ca3c 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -10,6 +10,8 @@
#include "axgbe_regs.h"
#include "rte_time.h"
+#include "eal_filesystem.h"
+
static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static int
axgbe_dev_configure(struct rte_eth_dev *dev); static int
axgbe_dev_start(struct rte_eth_dev *dev); @@ -2117,28 +2119,27 @@ static void
axgbe_default_config(struct axgbe_port *pdata)
pdata->power_down = 0;
}
-static int
-pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
+/*
+ * Return PCI root complex device id on success else 0 */ static
+uint16_t
+get_pci_rc_devid(void)
{
- const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
- const struct rte_pci_id *pcid = _pci_id;
+ char pci_sysfs[PATH_MAX];
+ const struct rte_pci_addr pci_rc_addr = {0, 0, 0, 0};
+ unsigned long device_id;
- if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
- pdev->id.device_id == pcid->device_id)
- return 0;
- return 1;
-}
+ snprintf(pci_sysfs, sizeof(pci_sysfs), "%s/" PCI_PRI_FMT "/device",
+rte_pci_get_sysfs_path(), pci_rc_addr.domain,
+pci_rc_addr.bus, pci_rc_addr.devid, pci_rc_addr.function);
-static bool
-pci_search_device(int device_id)
-{
- struct rte_bus *pci_bus;
- struct rte_pci_id dev_id;
+ /* get device id */
+ if (eal_parse_sysfs_value(pci_sysfs, &device_id) < 0) {
+ PMD_INIT_LOG(ERR, "Error in reading PCI sysfs\n");
+ return 0;
+ }
- dev_id.device_id = device_id;
- pci_bus = rte_bus_find_by_name("pci");
- return (pci_bus != NULL) &&
- (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
+ return (uint16_t)device_id;
}
/*
@@ -2180,7 +2181,7 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
/*
* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
*/
- if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
+ if ((get_pci_rc_devid()) == AMD_PCI_RV_ROOT_COMPLEX_ID) {
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
} else {
--
2.25.1
RE: [PATCH v1 2/6] net/axgbe: toggle PLL settings during rate change
[Public]
For series,
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Monday, January 10, 2022 5:05 PM
To: dev@dpdk.org
Subject: [PATCH v1 2/6] net/axgbe: toggle PLL settings during rate change
From: Selwin Sebastian
For each rate change command submission, the FW has to do a phy power off
sequence internally. For this to happen correctly, the PLL re-initialization
control setting has to be turned off before sending mailbox commands and
re-enabled once the command submission is complete. Without the PLL control
setting, the link up takes longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 9 +
drivers/net/axgbe/axgbe_phy_impl.c | 22 --
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR0x
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 02236ec192..dc9489f0aa 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) {
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for
command\n"); @@ -1213,10 +1227,14 @@ static void
axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+/* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); }
--
2.25.1
RE: [PATCH v1 3/6] net/axgbe: simplify mailbox interface rate change code
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Monday, January 10, 2022 5:05 PM
To: dev@dpdk.org
Subject: [PATCH v1 3/6] net/axgbe: simplify mailbox interface rate change code
From: Selwin Sebastian
Simplify and centralize the mailbox command rate change interface by having a
single function perform the writes to the mailbox registers to issue the
request.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 --
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index dc9489f0aa..0894dbf74b 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port
*pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) -{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata) {
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); } @@ -1263,13 +1257,9
@@ static void axgbe_phy_power_off(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n"); @@ -1278,31 +1268,21 @@ static
void axgbe_phy_power_off(struct axgbe_port *pdata) static void
axgbe_phy_sfi_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI m
RE: [PATCH v1 6/6] net/axgbe: alter the port speed bit range
[Public] Acked-by: Chandubabu Namburu -Original Message- From: sseba...@amd.com Sent: Monday, January 10, 2022 5:05 PM To: dev@dpdk.org Subject: [PATCH v1 6/6] net/axgbe: alter the port speed bit range From: Selwin Sebastian Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware. The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.: Before: PORT_PROPERTY_0[22:21] - Reserved PORT_PROPERTY_0[26:23] - Supported Speeds After: PORT_PROPERTY_0[21] - Reserved PORT_PROPERTY_0[26:22] - Supported Speeds To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/axgbe/axgbe_phy_impl.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index a5431dd998..5310ac54f5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1032,8 +1032,8 @@ #define XP_PROP_0_PORT_ID_WIDTH8 #define XP_PROP_0_PORT_MODE_INDEX 8 #define XP_PROP_0_PORT_MODE_WIDTH 4 -#define XP_PROP_0_PORT_SPEEDS_INDEX23 -#define XP_PROP_0_PORT_SPEEDS_WIDTH4 +#define XP_PROP_0_PORT_SPEEDS_INDEX22 +#define XP_PROP_0_PORT_SPEEDS_WIDTH5 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c index 2aad8babd2..776144696a 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -7,10 +7,10 @@ #include "axgbe_common.h" #include "axgbe_phy.h" -#define AXGBE_PHY_PORT_SPEED_100 BIT(0) -#define AXGBE_PHY_PORT_SPEED_1000 BIT(1) -#define AXGBE_PHY_PORT_SPEED_2500 BIT(2) -#define AXGBE_PHY_PORT_SPEED_1 BIT(3) +#define AXGBE_PHY_PORT_SPEED_100 BIT(1) +#define AXGBE_PHY_PORT_SPEED_1000 BIT(2) +#define AXGBE_PHY_PORT_SPEED_2500 BIT(3) +#define AXGBE_PHY_PORT_SPEED_1 BIT(4) #define AXGBE_MUTEX_RELEASE0x8000 -- 2.25.1
RE: [PATCH v1 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Monday, January 10, 2022 5:05 PM
To: dev@dpdk.org
Subject: [PATCH v1 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
From: Selwin Sebastian
Sometimes mailbox commands timeout when the RX data path becomes unresponsive.
This prevents the submission of new mailbox commands to DXIO. This patch
identifies the timeout and resets the RX data path so that the next message can
be submitted properly.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 14 ++
drivers/net/axgbe/axgbe_phy_impl.c | 29 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLTBIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR0x
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 0894dbf74b..e52dbb9585 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata) {
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+* This can be done by asseting the reset bit and wait for
+* its compeletion.
+*/
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, @@
-1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port
*pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); @@ -1235,6 +1259,9
@@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
RE: [PATCH v1 5/6] net/axgbe: add support for new port mode
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Monday, January 10, 2022 5:05 PM
To: dev@dpdk.org
Subject: [PATCH v1 5/6] net/axgbe: add support for new port mode
From: Selwin Sebastian
Add support for a new port mode that is abackplane connection without support
for auto negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index e52dbb9585..2aad8babd2 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_1baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct
axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata,
enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode); @@ -1806,6
+1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /*fallthrough;*/
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
RE: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
[Public] For series, Acked-by: Chandubabu Namburu -Original Message- From: sseba...@amd.com Sent: Tuesday, January 25, 2022 5:48 PM To: dev@dpdk.org Subject: [PATCH v2 6/6] net/axgbe: alter the port speed bit range From: Selwin Sebastian Newer generation Hardware uses the slightly different port speed bit widths, so alter the existing port speed bit range to extend support to the newer generation hardware while maintaining the backward compatibility with older generation hardware. The previously reserved bits are now being used which then requires the adjustment to the BIT values, e.g.: Before: PORT_PROPERTY_0[22:21] - Reserved PORT_PROPERTY_0[26:23] - Supported Speeds After: PORT_PROPERTY_0[21] - Reserved PORT_PROPERTY_0[26:22] - Supported Speeds To make this backwards compatible, the existing BIT definitions for the port speeds are incremented by one to maintain the original position. Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 4 ++-- drivers/net/axgbe/axgbe_phy_impl.c | 8 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index a5431dd998..5310ac54f5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -1032,8 +1032,8 @@ #define XP_PROP_0_PORT_ID_WIDTH8 #define XP_PROP_0_PORT_MODE_INDEX 8 #define XP_PROP_0_PORT_MODE_WIDTH 4 -#define XP_PROP_0_PORT_SPEEDS_INDEX23 -#define XP_PROP_0_PORT_SPEEDS_WIDTH4 +#define XP_PROP_0_PORT_SPEEDS_INDEX22 +#define XP_PROP_0_PORT_SPEEDS_WIDTH5 #define XP_PROP_1_MAX_RX_DMA_INDEX 24 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8 diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c index b0e1c267b1..d97fbbfddd 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -7,10 +7,10 @@ #include "axgbe_common.h" #include "axgbe_phy.h" -#define AXGBE_PHY_PORT_SPEED_100 BIT(0) -#define AXGBE_PHY_PORT_SPEED_1000 BIT(1) -#define AXGBE_PHY_PORT_SPEED_2500 BIT(2) -#define AXGBE_PHY_PORT_SPEED_1 BIT(3) +#define AXGBE_PHY_PORT_SPEED_100 BIT(1) +#define AXGBE_PHY_PORT_SPEED_1000 BIT(2) +#define AXGBE_PHY_PORT_SPEED_2500 BIT(3) +#define AXGBE_PHY_PORT_SPEED_1 BIT(4) #define AXGBE_MUTEX_RELEASE0x8000 -- 2.25.1
RE: [PATCH v2 5/6] net/axgbe: add support for new port mode
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 5/6] net/axgbe: add support for new port mode
From: Selwin Sebastian
Add support for a new port mode that is a backplane connection without support
for auto negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index eefb03e94e..b0e1c267b1 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -46,6 +46,7 @@ enum axgbe_port_mode {
AXGBE_PORT_MODE_10GBASE_T,
AXGBE_PORT_MODE_10GBASE_R,
AXGBE_PORT_MODE_SFP,
+ AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG,
AXGBE_PORT_MODE_MAX,
};
@@ -885,6 +886,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
if (ad_reg & 0x80) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KR;
break;
default:
@@ -894,6 +896,7 @@ static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct
axgbe_port *pdata)
} else if (ad_reg & 0x20) {
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
mode = AXGBE_MODE_KX_1000;
break;
case AXGBE_PORT_MODE_1000BASE_X:
@@ -1052,6 +1055,7 @@ static unsigned int axgbe_phy_an_advertising(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
advertising |= ADVERTISED_1baseKR_Full;
break;
case AXGBE_PORT_MODE_BACKPLANE_2500:
@@ -1122,6 +1126,7 @@ static enum axgbe_an_mode axgbe_phy_an_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
return AXGBE_AN_MODE_CL73;
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
return AXGBE_AN_MODE_NONE;
case AXGBE_PORT_MODE_1000BASE_T:
@@ -1400,6 +1405,7 @@ static enum axgbe_mode axgbe_phy_switch_mode(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_switch_bp_mode(pdata);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_switch_bp_2500_mode(pdata);
@@ -1495,6 +1501,7 @@ static enum axgbe_mode axgbe_phy_get_mode(struct
axgbe_port *pdata,
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_get_bp_mode(speed);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_get_bp_2500_mode(speed);
@@ -1644,6 +1651,7 @@ static bool axgbe_phy_use_mode(struct axgbe_port *pdata,
enum axgbe_mode mode)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
return axgbe_phy_use_bp_mode(pdata, mode);
case AXGBE_PORT_MODE_BACKPLANE_2500:
return axgbe_phy_use_bp_2500_mode(pdata, mode); @@ -1806,6
+1814,7 @@ static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) ||
(phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1))
return false;
@@ -1858,6 +1867,7 @@ static bool axgbe_phy_conn_type_mismatch(struct
axgbe_port *pdata)
switch (phy_data->port_mode) {
case AXGBE_PORT_MODE_BACKPLANE:
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
case AXGBE_PORT_MODE_BACKPLANE_2500:
if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE)
return false;
@@ -2122,6 +2132,8 @@ static int axgbe_phy_init(struct axgbe_port *pdata)
/* Backplane support */
case AXGBE_PORT_MODE_BACKPLANE:
pdata->phy.supported |= SUPPORTED_Autoneg;
+ /* Fallthrough */
+ case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG:
pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
pdata->phy.supported |= SUPPORTED_Backplane;
if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) {
--
2.25.1
RE: [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout
From: Selwin Sebastian
Sometimes mailbox commands timeout when the RX data path becomes unresponsive.
This prevents the submission of new mailbox commands to DXIO. This patch
identifies the timeout and resets the RX data path so that the next message can
be submitted properly.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 14 ++
drivers/net/axgbe/axgbe_phy_impl.c | 29 -
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5a7ac35b6a..a5431dd998 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1270,10 +1270,18 @@
#define MDIO_PMA_10GBR_FECCTRL 0x00ab
#endif
+#ifndef MDIO_PMA_RX_CTRL1
+#define MDIO_PMA_RX_CTRL1 0x8051
+#endif
+
#ifndef MDIO_PCS_DIG_CTRL
#define MDIO_PCS_DIG_CTRL 0x8000
#endif
+#ifndef MDIO_PCS_DIGITAL_STAT
+#define MDIO_PCS_DIGITAL_STAT 0x8010
+#endif
+
#ifndef MDIO_AN_XNP
#define MDIO_AN_XNP0x0016
#endif
@@ -1354,6 +1362,8 @@
#define AXGBE_KR_TRAINING_ENABLE BIT(1)
#define AXGBE_PCS_CL37_BP BIT(12)
+#define XGBE_PCS_PSEQ_STATE_MASK 0x1c
+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD 0x10
#define AXGBE_AN_CL37_INT_CMPLTBIT(0)
#define AXGBE_AN_CL37_INT_MASK 0x01
@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)
#define XGBE_PMA_PLL_CTRL_SET BIT(15)
#define XGBE_PMA_PLL_CTRL_CLEAR0x
+#define XGBE_PMA_RX_RST_0_MASK BIT(4)
+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10
+#define XGBE_PMA_RX_RST_0_RESET_OFF0x00
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 2ed94868b8..eefb03e94e 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_rx_reset(struct axgbe_port *pdata) {
+ int reg;
+
+ reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,
+ XGBE_PCS_PSEQ_STATE_MASK);
+ if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {
+ /* Mailbox command timed out, reset of RX block is required.
+* This can be done by asseting the reset bit and wait for
+* its compeletion.
+*/
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_ON);
+ rte_delay_us(20);
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,
+XGBE_PMA_RX_RST_0_MASK,
XGBE_PMA_RX_RST_0_RESET_OFF);
+ rte_delay_us(45);
+ PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n");
+ }
+}
+
+
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, @@
-1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port
*pdata,
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
- if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
+ if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
+ axgbe_phy_rx_reset(pdata);
+ }
/* Construct the command */
XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); @@ -1235,6 +1259,9
@@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
goto reenable_pll;
rte_delay_us(1500);
}
+ PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
+ /* Reset on error */
+ axgbe_phy_rx_reset(pdata);
reenable_pll:
/* Re-enable the PLL control */
--
2.25.1
RE: [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code
From: Selwin Sebastian
Simplify and centralize the mailbox command rate change interface by having a
single function perform the writes to the mailbox registers to issue the
request.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_phy_impl.c | 95 --
1 file changed, 23 insertions(+), 72 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 08d3484a11..2ed94868b8 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1207,21 +1207,26 @@ static void axgbe_phy_pll_ctrl(struct axgbe_port
*pdata, bool enable)
rte_delay_us(150);
}
-static void axgbe_phy_start_ratechange(struct axgbe_port *pdata)
+static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
+ unsigned int cmd, unsigned int sub_cmd)
{
+ unsigned int s0 = 0;
+ unsigned int wait;
/* Clear the PLL so that it helps in power down sequence */
axgbe_phy_pll_ctrl(pdata, false);
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n");
- else
- return;
-}
-static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) -{
- unsigned int wait;
+ /* Construct the command */
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
+ XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
+
+ /* Issue the command */
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
+ XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
+ XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
/* Wait for command to complete */
wait = AXGBE_RATECHANGE_COUNT;
@@ -1240,21 +1245,10 @@ static void axgbe_phy_complete_ratechange(struct
axgbe_port *pdata)
static void axgbe_phy_rrc(struct axgbe_port *pdata) {
- unsigned int s0;
- axgbe_phy_start_ratechange(pdata);
/* Receiver Reset Cycle */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5);
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
-
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
-
- axgbe_phy_complete_ratechange(pdata);
+ axgbe_phy_perform_ratechange(pdata, 5, 0);
PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); } @@ -1263,13 +1257,9
@@ static void axgbe_phy_power_off(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- axgbe_phy_start_ratechange(pdata);
+ /* Power off */
+ axgbe_phy_perform_ratechange(pdata, 0, 0);
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_UNKNOWN;
PMD_DRV_LOG(DEBUG, "phy powered off\n"); @@ -1278,31 +1268,21 @@ static
void axgbe_phy_power_off(struct axgbe_port *pdata) static void
axgbe_phy_sfi_mode(struct axgbe_port *pdata) {
struct axgbe_phy_data *phy_data = pdata->phy_data;
- unsigned int s0;
axgbe_phy_set_redrv_mode(pdata);
- axgbe_phy_start_ratechange(pdata);
-
/* 10G/SFI */
- s0 = 0;
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3);
if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) {
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0);
+ axgbe_phy_perform_ratechange(pdata, 3, 0);
} else {
if (phy_data->sfp_cable_len <= 1)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1);
+ axgbe_phy_perform_ratechange(pdata, 3, 1);
else if (phy_data->sfp_cable_len <= 3)
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2);
+ axgbe_phy_perform_ratechange(pdata, 3, 2);
else
- XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3);
+ axgbe_phy_perform_ratechange(pdata, 3, 3);
}
- /* Call FW to make the change */
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
- XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
- XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
- axgbe_phy_complete_ratechange(pdata);
phy_data->cur_mode = AXGBE_MODE_SFI;
PMD_DRV_LOG(DEBUG, "10GbE SFI
RE: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change
From: Selwin Sebastian
For each rate change command submission, the FW has to do a phy power off
sequence internally. For this to happen correctly, the PLL re-initialization
control setting has to be turned off before sending mailbox commands and
re-enabled once the command submission is complete. Without the PLL control
setting, the link up takes longer time in a fixed phy configuration.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 9 +
drivers/net/axgbe/axgbe_phy_impl.c | 22 --
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index df0aa21a9b..5a7ac35b6a 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1314,6 +1314,11 @@
#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
#endif
+#ifndef MDIO_VEND2_PMA_MISC_CTRL0
+#define MDIO_VEND2_PMA_MISC_CTRL0 0x8090
+#endif
+
+
#ifndef MDIO_CTRL1_SPEED1G
#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
#endif
@@ -1392,6 +1397,10 @@ static inline uint32_t high32_value(uint64_t addr)
return (addr >> 32) & 0x0;
}
+#define XGBE_PMA_PLL_CTRL_MASK BIT(15)
+#define XGBE_PMA_PLL_CTRL_SET BIT(15)
+#define XGBE_PMA_PLL_CTRL_CLEAR0x
+
/*END*/
/* Bit setting and getting macros
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c
b/drivers/net/axgbe/axgbe_phy_impl.c
index 72104f8a3f..08d3484a11 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1196,8 +1196,22 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port
*pdata)
axgbe_phy_put_comm_ownership(pdata);
}
+static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) {
+ XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
+ XGBE_PMA_PLL_CTRL_MASK,
+ enable ? XGBE_PMA_PLL_CTRL_SET
+ : XGBE_PMA_PLL_CTRL_CLEAR);
+
+ /* Wait for command to complete */
+ rte_delay_us(150);
+}
+
static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) {
+ /* Clear the PLL so that it helps in power down sequence */
+ axgbe_phy_pll_ctrl(pdata, false);
+
/* Log if a previous command did not complete */
if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for
command\n"); @@ -1213,10 +1227,14 @@ static void
axgbe_phy_complete_ratechange(struct axgbe_port *pdata)
wait = AXGBE_RATECHANGE_COUNT;
while (wait--) {
if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
- return;
-
+ goto reenable_pll;
rte_delay_us(1500);
}
+
+reenable_pll:
+/* Re-enable the PLL control */
+ axgbe_phy_pll_ctrl(pdata, true);
+
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); }
--
2.25.1
RE: [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: sseba...@amd.com
Sent: Tuesday, January 25, 2022 5:48 PM
To: dev@dpdk.org
Subject: [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode
From: Selwin Sebastian
Link training is always attempted when in KR mode, but the code is structured
to check if link training has been enabled before attempting to perform
it.Since that check will always be true, simplify the code to always enable and
start link training during KR auto-negotiation.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_mdio.c | 62 --
1 file changed, 15 insertions(+), 47 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_mdio.c b/drivers/net/axgbe/axgbe_mdio.c
index 32d8c666f9..913ceada0d 100644
--- a/drivers/net/axgbe/axgbe_mdio.c
+++ b/drivers/net/axgbe/axgbe_mdio.c
@@ -80,31 +80,10 @@ static void axgbe_an_clear_interrupts_all(struct axgbe_port
*pdata)
axgbe_an37_clear_interrupts(pdata);
}
-static void axgbe_an73_enable_kr_training(struct axgbe_port *pdata) -{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- reg |= AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
-
-static void axgbe_an73_disable_kr_training(struct axgbe_port *pdata) -{
- unsigned int reg;
-
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
-
- reg &= ~AXGBE_KR_TRAINING_ENABLE;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
-}
static void axgbe_kr_mode(struct axgbe_port *pdata) {
- /* Enable KR training */
- axgbe_an73_enable_kr_training(pdata);
-
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1);
@@ -114,9 +93,6 @@ static void axgbe_kr_mode(struct axgbe_port *pdata)
static void axgbe_kx_2500_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 2.5G speed */
pdata->hw_if.set_speed(pdata, SPEED_2500);
@@ -126,9 +102,6 @@ static void axgbe_kx_2500_mode(struct axgbe_port *pdata)
static void axgbe_kx_1000_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
-
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000);
@@ -142,8 +115,6 @@ static void axgbe_sfi_mode(struct axgbe_port *pdata)
if (pdata->kr_redrv)
return axgbe_kr_mode(pdata);
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 10G speed */
pdata->hw_if.set_speed(pdata, SPEED_1); @@ -154,8 +125,6 @@ static
void axgbe_sfi_mode(struct axgbe_port *pdata)
static void axgbe_x_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -166,8 +135,6 @@ static
void axgbe_x_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_1000_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -178,8 +145,6 @@ static
void axgbe_sgmii_1000_mode(struct axgbe_port *pdata)
static void axgbe_sgmii_100_mode(struct axgbe_port *pdata) {
- /* Disable KR training */
- axgbe_an73_disable_kr_training(pdata);
/* Set MAC to 1G speed */
pdata->hw_if.set_speed(pdata, SPEED_1000); @@ -284,6 +249,12 @@ static
void axgbe_an73_set(struct axgbe_port *pdata, bool enable, {
unsigned int reg;
+ /* Disable KR training for now */
+ reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
+ reg &= ~AXGBE_KR_TRAINING_ENABLE;
+ XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
+
+ /* Update AN settings */
reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
reg &= ~MDIO_AN_CTRL1_ENABLE;
@@ -379,20 +350,17 @@ static enum axgbe_an axgbe_an73_tx_training(struct
axgbe_port *pdata,
XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
/* Start KR training */
- reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
- if (reg & AXGBE_KR_TRAINING_ENABLE) {
- if (pdata->phy_if.phy_impl.kr_training_pre)
- pdata->phy_if.phy_impl.kr_training_pre(pdata);
+ if (pdata->phy_if.phy_impl.kr_training_pre)
+ pdata->phy_if.phy_impl.kr_training_pre(pdata);
- reg |= AXGBE_KR_TRAINING_START;
- XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
- reg);
-
- PMD_DRV_LOG(DEBUG, "KR training initiated\n");
+ reg = XMDIO_R
RE: [PATCH v1 1/2] net/axgbe: add support for Yellow Carp ethernet device
[Public]
-Original Message-
From: Sebastian, Selwin
Sent: Monday, January 31, 2022 11:09 AM
To: dev@dpdk.org
Cc: Namburu, Chandu-babu ; ferruh.yi...@intel.com
Subject: [PATCH v1 1/2] net/axgbe: add support for Yellow Carp ethernet device
From: Selwin Sebastian
Yellow Carp ethernet devices (V3xxx) use the existing PCI ID but the window
settings for the indirect PCS access have been altered. Add the check for
Yellow Carp Ethernet devices to use the new register values.
Signed-off-by: Selwin Sebastian
---
drivers/net/axgbe/axgbe_common.h | 2 ++ drivers/net/axgbe/axgbe_ethdev.c |
34 +---
2 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index 5310ac54f5..b9ebf64fb8 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -901,6 +901,8 @@
#define PCS_V2_WINDOW_SELECT 0x9064
#define PCS_V2_RV_WINDOW_DEF 0x1060
#define PCS_V2_RV_WINDOW_SELECT0x1064
+#define PCS_V2_YC_WINDOW_DEF 0x18060
+#define PCS_V2_YC_WINDOW_SELECT0x18064
/* PCS register entry bit positions and sizes */
#define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index e9546469f3..2be9387f98 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -173,6 +173,8 @@ static const struct axgbe_xstats axgbe_xstats_strings[] = {
/* The set of PCI devices this driver supports */
#define AMD_PCI_VENDOR_ID 0x1022
#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
+#define AMD_PCI_YC_ROOT_COMPLEX_ID 0x14b5
+#define AMD_PCI_SNOWY_ROOT_COMPLEX_ID 0x1450
#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 #define AMD_PCI_AXGBE_DEVICE_V2B
0x1459
@@ -2178,17 +2180,6 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
pdata->pci_dev = pci_dev;
- /*
-* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
-*/
- if ((get_pci_rc_devid()) == AMD_PCI_RV_ROOT_COMPLEX_ID) {
- pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
- pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
- } else {
- pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
- pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
- }
-
pdata->xgmac_regs =
(void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr;
pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs @@ -2203,6
+2194,27 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
else
pdata->vdata = &axgbe_v2b;
+ /*
+* Use PCI root complex device ID to identify the CPU
+*/
+ switch (get_pci_rc_devid()) {
+ case AMD_PCI_RV_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
+ break;
+ case AMD_PCI_YC_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT;
+ break;
+ case AMD_PCI_SNOWY_ROOT_COMPLEX_ID:
+ pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
+ pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "No supported devices found\n");
+ return -ENODEV;
+ }
+
/* Configure the PCS indirect addressing support */
reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
--
2.25.1
For series,
Acked-by: Chandubabu Namburu
RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[AMD Official Use Only]
Hi Arsalan Awan,
Thank you for sharing the patch. DPDK not working on V1000 is regression due to
"bus/pci: optimize bus scan" patch. As RV Root Complex device does not have any
Linux kernel driver assigned, this device is removed from PCI scan list and not
found using pcie_search_device() routine.
Patch submitted is potential fix for the issue, but we are checking if this is
the best way to fix regression. Will update you soon on the fix shared.
Regards,
Chandu
-Original Message-
From: Arsalan H. Awan
Sent: Wednesday, November 10, 2021 5:15 PM
To: dev@dpdk.org
Cc: Namburu, Chandu-babu ; Somalapuram, Amaranath
; Sebastian, Selwin ;
Giriyapura, Maheshwaramurthy ; Arsalan H.
Awan
Subject: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
The RV PCI Root Complex Device is not visible to DPDK on the PCI bus via
pci_search_device on some OSs including Ubuntu and Yocto. This makes it
impossible to determine which machine DPDK/axgbe is running on. As a result,
DPDK/axgbe does not work on v1000.
Let's use the Raven Internal PCIe GPP Bridge ID that DPDK can see on the PCI
bus that exists on the v1000 to differentiate between RV AXGBE and SNOWY AXGBE,
and set the registers accordingly. This fixes DPDK not working on v1000
platform.
Signed-off-by: Arsalan H. Awan
---
drivers/net/axgbe/axgbe_ethdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7d40c18a86..7b1b46990f 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -170,7 +170,7 @@ static const struct axgbe_xstats axgbe_xstats_strings[] = {
/* The set of PCI devices this driver supports */
#define AMD_PCI_VENDOR_ID 0x1022
-#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
+#define AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID 0x15db
#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 #define AMD_PCI_AXGBE_DEVICE_V2B
0x1459
@@ -2178,9 +2178,9 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pdata->pci_dev = pci_dev;
/*
-* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
+* Use Raven Internal PCIe GPP Bridge device ID to differentiate RV
+AXGBE vs SNOWY AXGBE
*/
- if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
+ if (pci_search_device(AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID)) {
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
} else {
--
2.17.1
RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[Public]
Hi Arsalan,
We have identified fix for this issue and will submit the patch for community
review asap.
Thanks,
Chandu
-Original Message-
From: Awan, Arsalan
Sent: Thursday, November 25, 2021 1:42 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Somalapuram, Amaranath ; Sebastian, Selwin
; Giriyapura, Maheshwaramurthy
Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
Hi Chandu,
Do we have an update on this?
Can we go ahead with this patch for now as it does not break anything else, but
fixes the problem.
DPDK will be working fine as is on the e3000.
This patch only adjusts the code for the v1000 and it works fine and there
isn't a difference in the approach of fixing the problem compared to that being
done currently to distinguish between the two platforms i.e. e3000 & v1000.
Hoping to hear from you soon.
Thanks,
Arsalan
From: Awan, Arsalan
Sent: Monday, November 15, 2021 3:15 PM
To: Namburu, Chandu-babu; dev@dpdk.org
Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy
Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
Thanks, Chandu!
Appreciate you guys looking into this!
Looking forward to hear from you soon.
Thanks and regards,
Arsalan
From: Namburu, Chandu-babu
Sent: Friday, November 12, 2021 7:48 PM
To: Awan, Arsalan; dev@dpdk.org
Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy
Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[AMD Official Use Only]
Hi Arsalan Awan,
Thank you for sharing the patch. DPDK not working on V1000 is regression due to
"bus/pci: optimize bus scan" patch. As RV Root Complex device does not have any
Linux kernel driver assigned, this device is removed from PCI scan list and not
found using pcie_search_device() routine.
Patch submitted is potential fix for the issue, but we are checking if this is
the best way to fix regression. Will update you soon on the fix shared.
Regards,
Chandu
-Original Message-
From: Arsalan H. Awan
Sent: Wednesday, November 10, 2021 5:15 PM
To: dev@dpdk.org
Cc: Namburu, Chandu-babu ; Somalapuram, Amaranath
; Sebastian, Selwin ;
Giriyapura, Maheshwaramurthy ; Arsalan H.
Awan
Subject: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
The RV PCI Root Complex Device is not visible to DPDK on the PCI bus via
pci_search_device on some OSs including Ubuntu and Yocto. This makes it
impossible to determine which machine DPDK/axgbe is running on. As a result,
DPDK/axgbe does not work on v1000.
Let's use the Raven Internal PCIe GPP Bridge ID that DPDK can see on the PCI
bus that exists on the v1000 to differentiate between RV AXGBE and SNOWY AXGBE,
and set the registers accordingly. This fixes DPDK not working on v1000
platform.
Signed-off-by: Arsalan H. Awan
---
drivers/net/axgbe/axgbe_ethdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7d40c18a86..7b1b46990f 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -170,7 +170,7 @@ static const struct axgbe_xstats axgbe_xstats_strings[] = {
/* The set of PCI devices this driver supports */
#define AMD_PCI_VENDOR_ID 0x1022
-#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
+#define AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID 0x15db
#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 #define AMD_PCI_AXGBE_DEVICE_V2B
0x1459
@@ -2178,9 +2178,9 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pdata->pci_dev = pci_dev;
/*
-* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
+* Use Raven Internal PCIe GPP Bridge device ID to differentiate
+RV AXGBE vs SNOWY AXGBE
*/
- if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
+ if (pci_search_device(AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID)) {
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
} else {
--
2.17.1
RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[Public]
Hi Arsalan,
I have submitted new patch to community review and looped you in. Please share
your comments.
https://patches.dpdk.org/project/dpdk/list/?series=20788
Regards,
Chandu
-Original Message-
From: Awan, Arsalan
Sent: Thursday, November 25, 2021 2:37 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Somalapuram, Amaranath ; Sebastian, Selwin
; Giriyapura, Maheshwaramurthy
Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
Thanks, Chandu!
This will help a lot!
Regards,
Arsalan
From: Namburu, Chandu-babu
Sent: Thursday, November 25, 2021 1:23 PM
To: Awan, Arsalan; dev@dpdk.org
Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy
Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[Public]
Hi Arsalan,
We have identified fix for this issue and will submit the patch for community
review asap.
Thanks,
Chandu
-Original Message-
From: Awan, Arsalan
Sent: Thursday, November 25, 2021 1:42 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Somalapuram, Amaranath ; Sebastian, Selwin
; Giriyapura, Maheshwaramurthy
Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
Hi Chandu,
Do we have an update on this?
Can we go ahead with this patch for now as it does not break anything else, but
fixes the problem.
DPDK will be working fine as is on the e3000.
This patch only adjusts the code for the v1000 and it works fine and there
isn't a difference in the approach of fixing the problem compared to that being
done currently to distinguish between the two platforms i.e. e3000 & v1000.
Hoping to hear from you soon.
Thanks,
Arsalan
From: Awan, Arsalan
Sent: Monday, November 15, 2021 3:15 PM
To: Namburu, Chandu-babu; dev@dpdk.org
Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy
Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
Thanks, Chandu!
Appreciate you guys looking into this!
Looking forward to hear from you soon.
Thanks and regards,
Arsalan
From: Namburu, Chandu-babu
Sent: Friday, November 12, 2021 7:48 PM
To: Awan, Arsalan; dev@dpdk.org
Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy
Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[AMD Official Use Only]
Hi Arsalan Awan,
Thank you for sharing the patch. DPDK not working on V1000 is regression due to
"bus/pci: optimize bus scan" patch. As RV Root Complex device does not have any
Linux kernel driver assigned, this device is removed from PCI scan list and not
found using pcie_search_device() routine.
Patch submitted is potential fix for the issue, but we are checking if this is
the best way to fix regression. Will update you soon on the fix shared.
Regards,
Chandu
-Original Message-
From: Arsalan H. Awan
Sent: Wednesday, November 10, 2021 5:15 PM
To: dev@dpdk.org
Cc: Namburu, Chandu-babu ; Somalapuram, Amaranath
; Sebastian, Selwin ;
Giriyapura, Maheshwaramurthy ; Arsalan H.
Awan
Subject: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
The RV PCI Root Complex Device is not visible to DPDK on the PCI bus via
pci_search_device on some OSs including Ubuntu and Yocto. This makes it
impossible to determine which machine DPDK/axgbe is running on. As a result,
DPDK/axgbe does not work on v1000.
Let's use the Raven Internal PCIe GPP Bridge ID that DPDK can see on the PCI
bus that exists on the v1000 to differentiate between RV AXGBE and SNOWY AXGBE,
and set the registers accordingly. This fixes DPDK not working on v1000
platform.
Signed-off-by: Arsalan H. Awan
---
drivers/net/axgbe/axgbe_ethdev.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7d40c18a86..7b1b46990f 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -170,7 +170,7 @@ static const struct axgbe_xstats axgbe_xstats_strings[] = {
/* The set of PCI devices this driver supports */
#define AMD_PCI_VENDOR_ID 0x1022
-#define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0
+#define AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID 0x15db
#define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 #define AMD_PCI_AXGBE_DEVICE_V2B
0x1459
@@ -2178,9 +2178,9 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
pdata->pci_dev = pci_dev;
/*
-* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
+* Use Raven Internal PCIe GPP Bridge device ID to differentiate
+RV AXGBE vs SNOWY AXGBE
*/
- if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
+ if (pci_search_device(AMD_PCI_RV_INTERNAL_PCIE_GPP_BRIDGE_ID)) {
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
pdata->xpcs_window_
RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000
[Public] Hi Arsalan, Thank you for your comments. Regards, Chandu -Original Message- From: Awan, Arsalan Sent: Wednesday, December 1, 2021 2:19 PM To: Namburu, Chandu-babu ; dev@dpdk.org Cc: Somalapuram, Amaranath ; Sebastian, Selwin ; Giriyapura, Maheshwaramurthy Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 Hi Chandu, I have provided my comments on your patch acknowledging your solution as a better approach than this one. Thanks and regards, Arsalan From: Namburu, Chandu-babu Sent: Friday, November 26, 2021 3:35 PM To: Awan, Arsalan; dev@dpdk.org Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 [Public] Hi Arsalan, I have submitted new patch to community review and looped you in. Please share your comments. https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.dpdk.org%2Fproject%2Fdpdk%2Flist%2F%3Fseries%3D20788&data=04%7C01%7Cchandu%40amd.com%7C6355ab7462c44e390bcc08d9b4a75e16%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637739453199074315%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=I9m0teM9abhf21%2BHn90dJCLNKS28D%2BY%2BCya%2FADdS5nI%3D&reserved=0 Regards, Chandu -Original Message- From: Awan, Arsalan Sent: Thursday, November 25, 2021 2:37 PM To: Namburu, Chandu-babu ; dev@dpdk.org Cc: Somalapuram, Amaranath ; Sebastian, Selwin ; Giriyapura, Maheshwaramurthy Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 Thanks, Chandu! This will help a lot! Regards, Arsalan From: Namburu, Chandu-babu Sent: Thursday, November 25, 2021 1:23 PM To: Awan, Arsalan; dev@dpdk.org Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 [Public] Hi Arsalan, We have identified fix for this issue and will submit the patch for community review asap. Thanks, Chandu -Original Message- From: Awan, Arsalan Sent: Thursday, November 25, 2021 1:42 PM To: Namburu, Chandu-babu ; dev@dpdk.org Cc: Somalapuram, Amaranath ; Sebastian, Selwin ; Giriyapura, Maheshwaramurthy Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 Hi Chandu, Do we have an update on this? Can we go ahead with this patch for now as it does not break anything else, but fixes the problem. DPDK will be working fine as is on the e3000. This patch only adjusts the code for the v1000 and it works fine and there isn't a difference in the approach of fixing the problem compared to that being done currently to distinguish between the two platforms i.e. e3000 & v1000. Hoping to hear from you soon. Thanks, Arsalan From: Awan, Arsalan Sent: Monday, November 15, 2021 3:15 PM To: Namburu, Chandu-babu; dev@dpdk.org Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy Subject: Re: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 Thanks, Chandu! Appreciate you guys looking into this! Looking forward to hear from you soon. Thanks and regards, Arsalan ____ From: Namburu, Chandu-babu Sent: Friday, November 12, 2021 7:48 PM To: Awan, Arsalan; dev@dpdk.org Cc: Somalapuram, Amaranath; Sebastian, Selwin; Giriyapura, Maheshwaramurthy Subject: RE: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 [AMD Official Use Only] Hi Arsalan Awan, Thank you for sharing the patch. DPDK not working on V1000 is regression due to "bus/pci: optimize bus scan" patch. As RV Root Complex device does not have any Linux kernel driver assigned, this device is removed from PCI scan list and not found using pcie_search_device() routine. Patch submitted is potential fix for the issue, but we are checking if this is the best way to fix regression. Will update you soon on the fix shared. Regards, Chandu -Original Message- From: Arsalan H. Awan Sent: Wednesday, November 10, 2021 5:15 PM To: dev@dpdk.org Cc: Namburu, Chandu-babu ; Somalapuram, Amaranath ; Sebastian, Selwin ; Giriyapura, Maheshwaramurthy ; Arsalan H. Awan Subject: [PATCH] net/axgbe: fix PCI ID to distinguish v1000 vs e3000 The RV PCI Root Complex Device is not visible to DPDK on the PCI bus via pci_search_device on some OSs including Ubuntu and Yocto. This makes it impossible to determine which machine DPDK/axgbe is running on. As a result, DPDK/axgbe does not work on v1000. Let's use the Raven Internal PCIe GPP Bridge ID that DPDK can see on the PCI bus that exists on the v1000 to differentiate between RV AXGBE and SNOWY AXGBE, and set the registers accordingly. This fixes DPDK not working on v1000 platform. Signed-off-by: Arsalan H. Awan --- drivers/net/axgbe/axgbe_et
RE: [PATCH v1] net/axgbe: use PCI root complex device to distinguish AMD hardware
[Public]
Hi David Marchand,
Thank you for your comments. Will change patch and submit v2 for review
Regards,
Chandu
-Original Message-
From: David Marchand
Sent: Wednesday, December 1, 2021 2:31 PM
To: Namburu, Chandu-babu
Cc: dev ; Sebastian, Selwin ;
arsalan_a...@mentor.com; Yigit, Ferruh
Subject: Re: [PATCH v1] net/axgbe: use PCI root complex device to distinguish
AMD hardware
On Fri, Nov 26, 2021 at 11:24 AM Chandubabu Namburu wrote:
>
> "bus/pci: optimize bus scan" broke axgbe on V1000/R1000.
> RV root complex pci device does not have any kernel driver assigned so
> it is removed from pci scan list which is used in
> "net/axgbe: add a HW quirk for register definitions"
>
> Get root complex device id directly from pci sysfs instead of pci scan
> list
Please end the sentences with a '.'.
As you described, this change is a fix.
Please add a Fixes: tag and Cc: sta...@dpdk.org in the commitlog if you think
it should be backported to LTS releases.
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdoc.dpdk.org%2Fguides%2Fcontributing%2Fpatches.html%23patch-for-stable-releases&data=04%7C01%7Cchandu%40amd.com%7C6618c303ecb146be0b5908d9b4a91c01%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637739460691977618%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=piC1U%2BPcPP2A0xwM3%2FA5qDUFXNLAj2SrLBywTFc3DFM%3D&reserved=0
>
> Signed-off-by: Chandubabu Namburu
> ---
> drivers/net/axgbe/axgbe_ethdev.c | 39
>
> 1 file changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/net/axgbe/axgbe_ethdev.c
> b/drivers/net/axgbe/axgbe_ethdev.c
> index 9cd056d04a..26babde354 100644
> --- a/drivers/net/axgbe/axgbe_ethdev.c
> +++ b/drivers/net/axgbe/axgbe_ethdev.c
> @@ -10,6 +10,8 @@
> #include "axgbe_regs.h"
> #include "rte_time.h"
>
> +#include "eal_filesystem.h"
> +
> static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static
> int axgbe_dev_configure(struct rte_eth_dev *dev); static int
> axgbe_dev_start(struct rte_eth_dev *dev); @@ -1923,28 +1925,27 @@
> static void axgbe_default_config(struct axgbe_port *pdata)
> pdata->power_down = 0;
> }
>
> -static int
> -pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
> +/*
> + * Return PCI root complex device id on success else 0 */ static
> +uint16_t
> +get_pci_rc_devid(void)
> {
> - const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
> - const struct rte_pci_id *pcid = _pci_id;
> + char pci_sysfs[PATH_MAX];
> + const struct rte_pci_addr pci_rc_addr = {0, 0, 0, 0};
> + unsigned long device_id;
>
> - if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
> - pdev->id.device_id == pcid->device_id)
> - return 0;
> - return 1;
> -}
> + snprintf(pci_sysfs, sizeof(pci_sysfs), "%s/" PCI_PRI_FMT "/device",
> +rte_pci_get_sysfs_path(), pci_rc_addr.domain,
> +pci_rc_addr.bus, pci_rc_addr.devid,
> + pci_rc_addr.function);
The use of rte_pci_get_sysfs_path() and in general is ugly because it only
works for Linux.
We could come up with a better API in the pci bus, but I don't think it is
worth it atm.
We can live with your implementation since this driver is only compiled on
Linux.
--
David Marchand
RE: [PATCH v2] net/axgbe: use PCI root complex device to distinguish AMD hardware
[Public]
Hi David Marchand,
I have submitted v2 patch with your suggestion in git log. Please review
changes.
Regards,
Chandu
-Original Message-
From: Namburu, Chandu-babu
Sent: Thursday, December 2, 2021 9:41 PM
To: dev@dpdk.org; david.march...@redhat.com
Cc: Sebastian, Selwin ; arsalan_a...@mentor.com;
ferruh.yi...@intel.com; Namburu, Chandu-babu ; sta...@dpdk.org
Subject: [PATCH v2] net/axgbe: use PCI root complex device to distinguish AMD
hardware
"bus/pci: optimize bus scan" broke axgbe on V1000/R1000.
RV root complex pci device does not have any kernel driver assigned so it is
removed from pci scan list which is used in
"net/axgbe: add a HW quirk for register definitions".
Get root complex device id directly from pci sysfs instead of pci scan list.
Fixes: 991e0b1dbc4a (net/axgbe: add a HW quirk for register definitions)
Cc: sta...@dpdk.org
Signed-off-by: Chandubabu Namburu
---
drivers/net/axgbe/axgbe_ethdev.c | 39
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index 7d40c18a86..7b8d94ca3c 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -10,6 +10,8 @@
#include "axgbe_regs.h"
#include "rte_time.h"
+#include "eal_filesystem.h"
+
static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static int
axgbe_dev_configure(struct rte_eth_dev *dev); static int
axgbe_dev_start(struct rte_eth_dev *dev); @@ -2117,28 +2119,27 @@ static void
axgbe_default_config(struct axgbe_port *pdata)
pdata->power_down = 0;
}
-static int
-pci_device_cmp(const struct rte_device *dev, const void *_pci_id)
+/*
+ * Return PCI root complex device id on success else 0 */ static
+uint16_t
+get_pci_rc_devid(void)
{
- const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev);
- const struct rte_pci_id *pcid = _pci_id;
+ char pci_sysfs[PATH_MAX];
+ const struct rte_pci_addr pci_rc_addr = {0, 0, 0, 0};
+ unsigned long device_id;
- if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID &&
- pdev->id.device_id == pcid->device_id)
- return 0;
- return 1;
-}
+ snprintf(pci_sysfs, sizeof(pci_sysfs), "%s/" PCI_PRI_FMT "/device",
+rte_pci_get_sysfs_path(), pci_rc_addr.domain,
+pci_rc_addr.bus, pci_rc_addr.devid, pci_rc_addr.function);
-static bool
-pci_search_device(int device_id)
-{
- struct rte_bus *pci_bus;
- struct rte_pci_id dev_id;
+ /* get device id */
+ if (eal_parse_sysfs_value(pci_sysfs, &device_id) < 0) {
+ PMD_INIT_LOG(ERR, "Error in reading PCI sysfs\n");
+ return 0;
+ }
- dev_id.device_id = device_id;
- pci_bus = rte_bus_find_by_name("pci");
- return (pci_bus != NULL) &&
- (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL);
+ return (uint16_t)device_id;
}
/*
@@ -2180,7 +2181,7 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)
/*
* Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE
*/
- if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) {
+ if ((get_pci_rc_devid()) == AMD_PCI_RV_ROOT_COMPLEX_ID) {
pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
} else {
--
2.25.1
RE: [PATCH v1] maintainers: take maintainership of AMD axgbe driver
[Public] -Original Message- From: Selwin Sebastian Sent: Wednesday, August 30, 2023 2:32 PM To: dev@dpdk.org Cc: Sebastian, Selwin Subject: [PATCH v1] maintainers: take maintainership of AMD axgbe driver Chandu is not working on dpdk axgbe driver anymore. Signed-off-by: Selwin Sebastian --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6b95da9ae3..1c40ad5665 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -644,7 +644,7 @@ F: doc/guides/nics/ena.rst F: doc/guides/nics/features/ena.ini AMD axgbe -M: Chandubabu Namburu +M: Selwin Sebastian F: drivers/net/axgbe/ F: doc/guides/nics/axgbe.rst F: doc/guides/nics/features/axgbe.ini -- 2.34.1 Acked-by: Chandubabu Namburu
RE: [PATCH v3 1/4] net/axgbe: fix scattered Rx
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: Modali, Bhagyada
Sent: Friday, September 2, 2022 2:18 PM
To: Namburu, Chandu-babu ; Yigit, Ferruh
Cc: dev@dpdk.org; sta...@dpdk.org; Modali, Bhagyada
Subject: [PATCH v3 1/4] net/axgbe: fix scattered Rx
Error check needs to be done only for last segment of Jumbo packet.
Freed first_seg and reset eop to 0 in error case
Fixes: 965b3127d425 ("net/axgbe: support scattered Rx")
Cc: sta...@dpdk.org
Signed-off-by: Bhagyada Modali
---
v2:
* removed the extra paranthesis
* initialised the variables
* updated the commit logs
---
drivers/net/axgbe/axgbe_rxtx.c | 35 +++---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index f38bb64fab..89ed6fd74a 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -343,8 +343,8 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
uint64_t old_dirty = rxq->dirty;
struct rte_mbuf *first_seg = NULL;
struct rte_mbuf *mbuf, *tmbuf;
- unsigned int err, etlt;
- uint32_t error_status;
+ unsigned int err = 0, etlt;
+ uint32_t error_status = 0;
uint16_t idx, pidx, data_len = 0, pkt_len = 0;
uint64_t offloads;
@@ -381,19 +381,6 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
}
mbuf = rxq->sw_ring[idx];
- /* Check for any errors and free mbuf*/
- err = AXGMAC_GET_BITS_LE(desc->write.desc3,
-RX_NORMAL_DESC3, ES);
- error_status = 0;
- if (unlikely(err)) {
- error_status = desc->write.desc3 & AXGBE_ERR_STATUS;
- if ((error_status != AXGBE_L3_CSUM_ERR)
- && (error_status != AXGBE_L4_CSUM_ERR))
{
- rxq->errors++;
- rte_pktmbuf_free(mbuf);
- goto err_set;
- }
- }
rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *));
if (!AXGMAC_GET_BITS_LE(desc->write.desc3,
@@ -406,6 +393,24 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3,
RX_NORMAL_DESC3, PL);
data_len = pkt_len - rxq->crc_len;
+ /* Check for any errors and free mbuf*/
+ err = AXGMAC_GET_BITS_LE(desc->write.desc3,
+ RX_NORMAL_DESC3, ES);
+ error_status = 0;
+ if (unlikely(err)) {
+ error_status = desc->write.desc3 &
+ AXGBE_ERR_STATUS;
+ if (error_status != AXGBE_L3_CSUM_ERR &&
+ error_status !=
AXGBE_L4_CSUM_ERR) {
+ rxq->errors++;
+ rte_pktmbuf_free(mbuf);
+ rte_pktmbuf_free(first_seg);
+ first_seg = NULL;
+ eop = 0;
+ goto err_set;
+ }
+ }
+
}
if (first_seg != NULL) {
--
2.25.1
RE: [PATCH v2] net/axgbe: optimise scattered rx
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: Modali, Bhagyada
Sent: Tuesday, September 6, 2022 5:29 PM
To: Namburu, Chandu-babu ; Yigit, Ferruh
Cc: dev@dpdk.org; sta...@dpdk.org; Modali, Bhagyada
Subject: [PATCH v2] net/axgbe: optimise scattered rx
Updated the logic to remove the extra increments of the variables.
Fixes: 965b3127d425 ("net/axgbe: support scattered Rx")
Cc: sta...@dpdk.org
Signed-off-by: Bhagyada Modali
---
v2:
* rebased to the latest changes and submitting the patch again
---
---
drivers/net/axgbe/axgbe_rxtx.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 2bad638f79..8b43e8160b 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -340,7 +340,6 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
struct axgbe_rx_queue *rxq = rx_queue;
volatile union axgbe_rx_desc *desc;
- uint64_t old_dirty = rxq->dirty;
struct rte_mbuf *first_seg = NULL;
struct rte_mbuf *mbuf, *tmbuf;
unsigned int err = 0, etlt;
@@ -352,8 +351,7 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
while (nb_rx < nb_pkts) {
bool eop = 0;
next_desc:
- if (unlikely(idx == rxq->nb_desc))
- idx = 0;
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
desc = &rxq->desc[idx];
@@ -446,19 +444,19 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
~RTE_MBUF_F_RX_VLAN_STRIPPED;
} else {
first_seg->ol_flags &=
- ~(RTE_MBUF_F_RX_VLAN |
RTE_MBUF_F_RX_VLAN_STRIPPED);
+ ~(RTE_MBUF_F_RX_VLAN |
+
RTE_MBUF_F_RX_VLAN_STRIPPED);
first_seg->vlan_tci = 0;
}
}
err_set:
rxq->cur++;
- rxq->sw_ring[idx++] = tmbuf;
+ rxq->sw_ring[idx] = tmbuf;
desc->read.baddr =
rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf));
memset((void *)(&desc->read.desc2), 0, 8);
AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
- rxq->dirty++;
if (!eop) {
rte_pktmbuf_free(mbuf);
@@ -501,12 +499,13 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
/* Save receive context.*/
rxq->pkts += nb_rx;
- if (rxq->dirty != old_dirty) {
+ if (rxq->dirty != rxq->cur) {
rte_wmb();
- idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1);
+ idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur - 1);
AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO,
low32_value(rxq->ring_phys_addr +
(idx * sizeof(union axgbe_rx_desc;
+ rxq->dirty = rxq->cur;
}
return nb_rx;
}
--
2.25.1
RE: [PATCH v2 1/3] net/axgbe: reset the end of packet in scattered rx
[Public]
For the series,
Acked-by: Chandubabu Namburu
-Original Message-
From: Modali, Bhagyada
Sent: Thursday, September 8, 2022 9:01 AM
To: Namburu, Chandu-babu ; Yigit, Ferruh
Cc: dev@dpdk.org; sta...@dpdk.org; Modali, Bhagyada
Subject: [PATCH v2 1/3] net/axgbe: reset the end of packet in scattered rx
Reset the eop in the failure scenario and also after the last segment.
Removed the packet length updation explicitly as it is done in Chaining.
Fixes: 965b3127d425 ("net/axgbe: support scattered Rx")
Cc: sta...@dpdk.org
Signed-off-by: Bhagyada Modali
---
drivers/net/axgbe/axgbe_rxtx.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 8b43e8160b..e1488483bc 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -346,10 +346,11 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
uint32_t error_status = 0;
uint16_t idx, pidx, data_len = 0, pkt_len = 0;
uint64_t offloads;
+ bool eop = 0;
idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
+
while (nb_rx < nb_pkts) {
- bool eop = 0;
next_desc:
idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur);
@@ -416,9 +417,12 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
mbuf->pkt_len = data_len;
if (first_seg != NULL) {
- if (rte_pktmbuf_chain(first_seg, mbuf) != 0)
+ if (rte_pktmbuf_chain(first_seg, mbuf) != 0) {
rte_mempool_put(rxq->mb_pool,
first_seg);
+ eop = 0;
+ break;
+ }
} else {
first_seg = mbuf;
}
@@ -462,8 +466,8 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
rte_pktmbuf_free(mbuf);
goto next_desc;
}
+ eop = 0;
- first_seg->pkt_len = pkt_len;
rxq->bytes += pkt_len;
mbuf->next = NULL;
--
2.25.1
RE: [PATCH] net/axgbe: remove freeing buffer in scattered rx
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: Modali, Bhagyada
Sent: Thursday, September 8, 2022 6:12 PM
To: Namburu, Chandu-babu ; Yigit, Ferruh
Cc: dev@dpdk.org; sta...@dpdk.org; Modali, Bhagyada
Subject: [PATCH] net/axgbe: remove freeing buffer in scattered rx
Removed freeing of mbuf in scattered Rx as it should not be freed in rx.
Fixes: 965b3127d425 ("net/axgbe: support scattered Rx")
Cc: sta...@dpdk.org
Signed-off-by: Bhagyada Modali
---
drivers/net/axgbe/axgbe_rxtx.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 8b43e8160b..d4224992ee 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -458,14 +458,11 @@ uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue,
memset((void *)(&desc->read.desc2), 0, 8);
AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1);
- if (!eop) {
- rte_pktmbuf_free(mbuf);
+ if (!eop)
goto next_desc;
- }
first_seg->pkt_len = pkt_len;
rxq->bytes += pkt_len;
- mbuf->next = NULL;
first_seg->port = rxq->port_id;
if (rxq->pdata->rx_csum_enable) {
--
2.25.1
RE: [PATCH v2] net/axgbe: support segmented Tx
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: Modali, Bhagyada
Sent: Thursday, September 8, 2022 11:45 PM
To: Namburu, Chandu-babu ; Yigit, Ferruh
Cc: dev@dpdk.org; sta...@dpdk.org; Modali, Bhagyada
Subject: [PATCH v2] net/axgbe: support segmented Tx
Enable segmented tx support and add jumbo packet transmit capability
Signed-off-by: Bhagyada Modali
---
drivers/net/axgbe/axgbe_ethdev.c | 1 +
drivers/net/axgbe/axgbe_ethdev.h | 1 +
drivers/net/axgbe/axgbe_rxtx.c | 213 ++-
drivers/net/axgbe/axgbe_rxtx.h | 4 +
4 files changed, 218 insertions(+), 1 deletion(-)
diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
index e6822fa711..b071e4e460 100644
--- a/drivers/net/axgbe/axgbe_ethdev.c
+++ b/drivers/net/axgbe/axgbe_ethdev.c
@@ -1228,6 +1228,7 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
+ RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
RTE_ETH_TX_OFFLOAD_TCP_CKSUM;
diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h
index e06d40f9eb..7f19321d88 100644
--- a/drivers/net/axgbe/axgbe_ethdev.h
+++ b/drivers/net/axgbe/axgbe_ethdev.h
@@ -582,6 +582,7 @@ struct axgbe_port {
unsigned int tx_pbl;
unsigned int tx_osp_mode;
unsigned int tx_max_fifo_size;
+ unsigned int multi_segs_tx;
/* Rx settings */
unsigned int rx_sf_mode;
diff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c
index 8b43e8160b..881ffa01db 100644
--- a/drivers/net/axgbe/axgbe_rxtx.c
+++ b/drivers/net/axgbe/axgbe_rxtx.c
@@ -544,6 +544,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx,
unsigned int tsize;
const struct rte_memzone *tz;
uint64_t offloads;
+ struct rte_eth_dev_data *dev_data = dev->data;
tx_desc = nb_desc;
pdata = dev->data->dev_private;
@@ -611,7 +612,13 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx,
if (!pdata->tx_queues)
pdata->tx_queues = dev->data->tx_queues;
- if (txq->vector_disable ||
+ if ((dev_data->dev_conf.txmode.offloads &
+ RTE_ETH_TX_OFFLOAD_MULTI_SEGS))
+ pdata->multi_segs_tx = true;
+
+ if (pdata->multi_segs_tx)
+ dev->tx_pkt_burst = &axgbe_xmit_pkts_seg;
+ else if (txq->vector_disable ||
rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)
dev->tx_pkt_burst = &axgbe_xmit_pkts;
else
@@ -762,6 +769,29 @@ void axgbe_dev_enable_tx(struct rte_eth_dev *dev)
AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); }
+/* Free Tx conformed mbufs segments */
+static void
+axgbe_xmit_cleanup_seg(struct axgbe_tx_queue *txq) {
+ volatile struct axgbe_tx_desc *desc;
+ uint16_t idx;
+
+ idx = AXGBE_GET_DESC_IDX(txq, txq->dirty);
+ while (txq->cur != txq->dirty) {
+ if (unlikely(idx == txq->nb_desc))
+ idx = 0;
+ desc = &txq->desc[idx];
+ /* Check for ownership */
+ if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))
+ return;
+ memset((void *)&desc->desc2, 0, 8);
+ /* Free mbuf */
+ rte_pktmbuf_free_seg(txq->sw_ring[idx]);
+ txq->sw_ring[idx++] = NULL;
+ txq->dirty++;
+ }
+}
+
/* Free Tx conformed mbufs */
static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq) { @@ -854,6
+884,187 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
return 0;
}
+/* Tx Descriptor formation for segmented mbuf
+ * Each mbuf will require multiple descriptors */
+
+static int
+axgbe_xmit_hw_seg(struct axgbe_tx_queue *txq,
+ struct rte_mbuf *mbuf)
+{
+ volatile struct axgbe_tx_desc *desc;
+ uint16_t idx;
+ uint64_t mask;
+ int start_index;
+ uint32_t pkt_len = 0;
+ int nb_desc_free;
+ struct rte_mbuf *tx_pkt;
+
+ nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
+
+ if (mbuf->nb_segs > nb_desc_free) {
+ axgbe_xmit_cleanup_seg(txq);
+ nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);
+ if (unlikely(mbuf->nb_segs > nb_desc_free))
+ return RTE_ETH_TX_DESC_UNAVAIL;
+ }
+
+ idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
+ desc = &txq->desc[idx];
+ /* Saving the start index for setting the OWN bit finally */
+ start_index = idx;
+
+
RE: [PATCH] crypto/ccp: Check for the NULL pointer after calling rte_malloc
[Public]
Acked-by: Chandubabu Namburu
-Original Message-
From: 835703...@qq.com <835703...@qq.com>
Sent: Saturday, July 9, 2022 4:31 PM
To: Namburu, Chandu-babu
Cc: dev@dpdk.org; Shiqi Liu <835703...@qq.com>
Subject: [PATCH] crypto/ccp: Check for the NULL pointer after calling rte_malloc
From: Shiqi Liu <835703...@qq.com>
As the possible failure of the rte_malloc(), the not_checked and checked could
be NULL pointer.
Therefore, it should be better to check it in order to avoid the dereference of
the NULL pointer.
Fixes: 09a0fd736a0 ("crypto/ccp: enable IOMMU")
Signed-off-by: Shiqi Liu <835703...@qq.com>
---
drivers/crypto/ccp/rte_ccp_pmd.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/crypto/ccp/rte_ccp_pmd.c b/drivers/crypto/ccp/rte_ccp_pmd.c
index a35a8cd775..776f928864 100644
--- a/drivers/crypto/ccp/rte_ccp_pmd.c
+++ b/drivers/crypto/ccp/rte_ccp_pmd.c
@@ -301,6 +301,9 @@ cryptodev_ccp_probe(struct rte_pci_driver *pci_drv
__rte_unused,
};
sha_ctx = (void *)rte_malloc(NULL, SHA512_DIGEST_SIZE, 64);
+ if (sha_ctx == NULL) {
+ return -ENOMEM;
+ }
if (ccp_pmd_init_done) {
RTE_LOG(INFO, PMD, "CCP PMD already initialized\n");
return -EFAULT;
--
2.35.1.windows.2
RE: [EXT] Re: [PATCH] crypto/ccp: Check for the NULL pointer after calling rte_malloc
[Public]
+ sunil
-Original Message-
From: Akhil Goyal
Sent: Tuesday, August 16, 2022 9:31 PM
To: Namburu, Chandu-babu ; 835703...@qq.com
Cc: dev@dpdk.org; David Marchand
Subject: RE: [EXT] Re: [PATCH] crypto/ccp: Check for the NULL pointer after
calling rte_malloc
Hi,
Could you please reply to David and Stephen's comments?
Regards,
Akhil
> On Wed, Jul 20, 2022 at 8:29 AM Namburu, Chandu-babu
> wrote:
> > From: Shiqi Liu <835703...@qq.com>
> >
> > As the possible failure of the rte_malloc(), the not_checked and
> > checked could
> be NULL pointer.
> > Therefore, it should be better to check it in order to avoid the
> > dereference of
> the NULL pointer.
> >
> > Fixes: 09a0fd736a0 ("crypto/ccp: enable IOMMU")
> > Signed-off-by: Shiqi Liu <835703...@qq.com>
>
> This sha_ctx variable and its accesses are suspicious.
>
> It seems to be used as some kind of intermediate buffer, but I fail to
> see the need.
> Can't the existing code rely on sess->auth.ctx ?
>
> There is also a suspicious mention (in ccp_perform_sha) of sha_ctx but
> with no calling rte_mem_virt2iova().
>
>
> --
> David Marchand
RE: [EXT] [dpdk-dev v5] crypto/openssl: openssl 3.0 support on sym crypto routine
[Public] Hi Roy Fan, -Original Message- From: Zhang, Roy Fan Sent: Friday, February 25, 2022 7:21 PM To: Akhil Goyal ; Ji, Kai ; dev@dpdk.org Cc: Namburu, Chandu-babu Subject: RE: [EXT] [dpdk-dev v5] crypto/openssl: openssl 3.0 support on sym crypto routine Hi Akhil, > -Original Message- > From: Akhil Goyal > Sent: Friday, February 25, 2022 10:40 AM > To: Ji, Kai ; dev@dpdk.org > Cc: Zhang, Roy Fan > Subject: RE: [EXT] [dpdk-dev v5] crypto/openssl: openssl 3.0 support > on sym crypto routine > > Hi Kai, > > > > The warning messages are deprecated APIs warnings from openssl , not > > compiler warnings from gcc, the integrity of DPDK remain the same. > > Alongside openssl pmd, the ccp and qat pmd also raise the same type > > of warnings once openssl 3.0 installed. > > > > In the current intel roadmap, we will try to support 3.0 API fully > > for openssl > and > > qat pmds by the end of year, so this patch is the first step. > > I think the warning messages are safe to stay, Unfortunately the fix > > ccp > pmd > > driver is out of our reach. > > > > When DPDK is compiled with openssl 3.0. I am seeing these errors in > compilation. > So, compilation is broken and we cannot take this patch as is. > We have few options, > - fix all of these errors, > - add exception in meson.build for ignoring these errors. > - disable/skip compilation of PMDs if openssl version is >3.0 > > Adding only one type of APIs does not make sense, if the driver is not > compiled. > > In file included from ../drivers/crypto/openssl/openssl_pmd_private.h:12, > from ../drivers/crypto/openssl/rte_openssl_pmd.c:16: > /usr/local/include/openssl/dh.h:223:27: note: declared here > 223 | OSSL_DEPRECATEDIN_3_0 int DH_generate_key(DH *dh); > | ^~~ > ../drivers/crypto/openssl/rte_openssl_pmd.c: In function > 'process_openssl_rsa_op': > ../drivers/crypto/openssl/rte_openssl_pmd.c:2068:3: error: > 'RSA_public_encrypt' is deprecated: Since OpenSSL 3.0 [- > Werror=deprecated-declarations] > 2068 | ret = RSA_public_encrypt(op->rsa.message.length, You are right. We will defer the change to next release so we can send along with the asym openssl change Kai is working on. But since we have your attention I would want to drag Chandubabu's attention too as there are three PMDs uses deprecated openssl lib APIs: openssl, qat, and ccp. Adding a suppress flag to meson build file won't resolve the problem - we need to resolve them before the APIs are gone for good. Thank you for bringing this to our attention, we will work on CCP changes to support 3.0 API's. > > Also, avoid top posting of comments!
Re: [dpdk-dev] [PATCH v1 1/2] net/axgbe: add additional MAC address support
[AMD Official Use Only - Internal Distribution Only] Hi Ferruh, Thank you for pointing it out, I will correct them. Regards, Chandu -Original Message- From: Ferruh Yigit Sent: Friday, February 28, 2020 7:33 PM To: Namburu, Chandu-babu ; dev@dpdk.org; Somalapuram, Amaranath Cc: Kumar, Ravi1 Subject: Re: [dpdk-dev] [PATCH v1 1/2] net/axgbe: add additional MAC address support On 2/28/2020 1:59 PM, cha...@amd.com wrote: > From: Chandu Babu N > > Supports adding MAC addresses to enable whitelist filtering to accept > packets implement eth_dev_ops mac_addr_set, mac_addr_add, > mac_addr_remove and set_mc_addr_list > > Signed-off-by: Chandu Babu N Hi Chandu, Amaranath, Same comment with previous patchset, Please check the "Contributing Code to DPDK" before sending patch: https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdoc.dpdk.org%2Fguides%2Fcontributing%2Fpatches.html&data=02%7C01%7Cchandu%40amd.com%7Cdaf59805e48d4384dc8708d7bc570ff4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C63718495477587&sdata=PLWzmriaCP0%2FS51xJomCQWlT7EJ5bwz95ZOsJAP5fX0%3D&reserved=0 And prefer threading for series instead of sending them one by one, as noted in above document: ''Shallow threading (--thread --no-chain-reply-to) is preferred for a patch series.''
Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query and update
[AMD Official Use Only - Internal Distribution Only]
RSS functionality is already supported by AXGBE and it is updated in
doc/guides/nics/features/axgbe.ini accordingly.
This patch adds support to update RSS Hash key and RETA.
Regards,
Chandu
-Original Message-
From: Andrew Rybchenko
Sent: Tuesday, March 24, 2020 3:25 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Kumar, Ravi1 ; Somalapuram, Amaranath
Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query and update
On 3/20/20 2:29 PM, cha...@amd.com wrote:
> From: Chandu Babu N
>
> add support for RSS ethdev_ops reta_update, reta_query
> rss_hash_update, rss_hash_conf_get
The patch should update doc/guides/nics/features/axgbe.ini to advertise
corresponding features.
>
> Signed-off-by: Chandu Babu N
> ---
> drivers/net/axgbe/axgbe_dev.c| 5 +-
> drivers/net/axgbe/axgbe_ethdev.c | 146 +++
> drivers/net/axgbe/axgbe_ethdev.h | 3 +
> 3 files changed, 152 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/axgbe/axgbe_dev.c
> b/drivers/net/axgbe/axgbe_dev.c index 5f0f19592..af62eae3b 100644
> --- a/drivers/net/axgbe/axgbe_dev.c
> +++ b/drivers/net/axgbe/axgbe_dev.c
> @@ -614,7 +614,7 @@ static int axgbe_write_rss_reg(struct axgbe_port *pdata,
> unsigned int type,
> return -EBUSY;
> }
>
> -static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
> +int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
> {
> struct rte_eth_rss_conf *rss_conf;
> unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); @@
> -638,7 +638,7 @@ static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
> return 0;
> }
>
> -static int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
> +int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
> {
> unsigned int i;
> int ret;
> @@ -683,6 +683,7 @@ static void axgbe_rss_options(struct axgbe_port *pdata)
> uint64_t rss_hf;
>
> rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
> + pdata->rss_hf = rss_conf->rss_hf;
> rss_hf = rss_conf->rss_hf;
>
> if (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6)) diff --git
> a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
> index 867058845..f42bb7a0d 100644
> --- a/drivers/net/axgbe/axgbe_ethdev.c
> +++ b/drivers/net/axgbe/axgbe_ethdev.c
> @@ -60,6 +60,18 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
>const uint64_t *ids,
>unsigned int size);
> static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
> +static int
> +axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
> + struct rte_eth_rss_reta_entry64 *reta_conf,
> + uint16_t reta_size);
> +static int
> +axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
> + struct rte_eth_rss_reta_entry64 *reta_conf,
> + uint16_t reta_size);
It looks like style is inconsistent for above to declarations vs declarations
around.
> +static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
> + struct rte_eth_rss_conf *rss_conf); static
> int
> +axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
> +struct rte_eth_rss_conf *rss_conf);
> static int axgbe_dev_info_get(struct rte_eth_dev *dev,
> struct rte_eth_dev_info *dev_info); static int
> axgbe_flow_ctrl_get(struct rte_eth_dev *dev, @@ -201,6 +213,10 @@
> static const struct eth_dev_ops axgbe_eth_dev_ops = {
> .xstats_get_names = axgbe_dev_xstats_get_names,
> .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
> .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
> + .reta_update = axgbe_dev_rss_reta_update,
> + .reta_query = axgbe_dev_rss_reta_query,
> + .rss_hash_update = axgbe_dev_rss_hash_update,
> + .rss_hash_conf_get= axgbe_dev_rss_hash_conf_get,
> .dev_infos_get= axgbe_dev_info_get,
> .rx_queue_setup = axgbe_dev_rx_queue_setup,
> .rx_queue_release = axgbe_dev_rx_queue_release,
> @@ -450,6 +466,136 @@ axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct
> rte_ether_addr *mac_addr,
> return 0;
> }
>
> +static int
> +axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
> + struct rte_eth_rss_reta_entry64 *reta_conf,
> + uint16_t reta_size)
> +{
> + struct axgbe_port *pdata = dev->data->dev_private;
> + unsigned int i, idx, shift;
> + int ret;
> +
>
Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query and update
[AMD Public Use]
Thank you Andrew, will update these in v2 patch.
-Original Message-
From: Andrew Rybchenko
Sent: Tuesday, March 24, 2020 3:55 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Kumar, Ravi1 ; Somalapuram, Amaranath
Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query and update
On 3/24/20 1:17 PM, Namburu, Chandu-babu wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> RSS functionality is already supported by AXGBE and it is updated in
> doc/guides/nics/features/axgbe.ini accordingly.
> This patch adds support to update RSS Hash key and RETA.
What about (see doc/guides/nics/features/default.ini)
RSS key update =
RSS reta update =
> Regards,
> Chandu
> -Original Message-
> From: Andrew Rybchenko
> Sent: Tuesday, March 24, 2020 3:25 PM
> To: Namburu, Chandu-babu ; dev@dpdk.org
> Cc: Kumar, Ravi1 ; Somalapuram, Amaranath
>
> Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS reta/hash query
> and update
>
> On 3/20/20 2:29 PM, cha...@amd.com wrote:
>> From: Chandu Babu N
>>
>> add support for RSS ethdev_ops reta_update, reta_query
>> rss_hash_update, rss_hash_conf_get
>
> The patch should update doc/guides/nics/features/axgbe.ini to advertise
> corresponding features.
>
>>
>> Signed-off-by: Chandu Babu N
>> ---
>> drivers/net/axgbe/axgbe_dev.c| 5 +-
>> drivers/net/axgbe/axgbe_ethdev.c | 146 +++
>> drivers/net/axgbe/axgbe_ethdev.h | 3 +
>> 3 files changed, 152 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/axgbe/axgbe_dev.c
>> b/drivers/net/axgbe/axgbe_dev.c index 5f0f19592..af62eae3b 100644
>> --- a/drivers/net/axgbe/axgbe_dev.c
>> +++ b/drivers/net/axgbe/axgbe_dev.c
>> @@ -614,7 +614,7 @@ static int axgbe_write_rss_reg(struct axgbe_port *pdata,
>> unsigned int type,
>> return -EBUSY;
>> }
>>
>> -static int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
>> +int axgbe_write_rss_hash_key(struct axgbe_port *pdata)
>> {
>> struct rte_eth_rss_conf *rss_conf;
>> unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); @@
>> -638,7 +638,7 @@ static int axgbe_write_rss_hash_key(struct axgbe_port
>> *pdata)
>> return 0;
>> }
>>
>> -static int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
>> +int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
>> {
>> unsigned int i;
>> int ret;
>> @@ -683,6 +683,7 @@ static void axgbe_rss_options(struct axgbe_port *pdata)
>> uint64_t rss_hf;
>>
>> rss_conf = &pdata->eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
>> +pdata->rss_hf = rss_conf->rss_hf;
>> rss_hf = rss_conf->rss_hf;
>>
>> if (rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6)) diff --git
>> a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c
>> index 867058845..f42bb7a0d 100644
>> --- a/drivers/net/axgbe/axgbe_ethdev.c
>> +++ b/drivers/net/axgbe/axgbe_ethdev.c
>> @@ -60,6 +60,18 @@ axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
>> const uint64_t *ids,
>> unsigned int size);
>> static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev);
>> +static int
>> +axgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
>> + struct rte_eth_rss_reta_entry64 *reta_conf,
>> + uint16_t reta_size);
>> +static int
>> +axgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
>> + struct rte_eth_rss_reta_entry64 *reta_conf,
>> + uint16_t reta_size);
>
> It looks like style is inconsistent for above to declarations vs declarations
> around.
>
>> +static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
>> + struct rte_eth_rss_conf *rss_conf); static
>> int
>> +axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
>> + struct rte_eth_rss_conf *rss_conf);
>> static int axgbe_dev_info_get(struct rte_eth_dev *dev,
>> struct rte_eth_dev_info *dev_info); static int
>> axgbe_flow_ctrl_get(struct rte_eth_dev *dev, @@ -201,6 +213,10 @@
>> static const struct eth_dev_ops axgbe_eth_dev_ops = {
>> .xstats_get_names = axgbe_dev_xstats_get_names,
>> .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id,
>> .xstats_get_by_id = axgbe_dev_xstats_get_by_id,
>> +.reta_update = axgbe_dev_rss_re
