[dpdk-dev] [RFC PATCH] test/distributor: fix burst flush on worker quit
While working on RISC-V port I have encountered a situation where worker
threads get stuck in the rte_distributor_return_pkt() function in the
burst test.
After investigation some of the threads enter this function with
flag RTE_DISTRIB_GET_BUF set in the d->retptr64[0]. At the same time
main thread has already passed rte_distributor_process() so nobody will
clear this flag and hence workers can't return.
What I've noticed is that adding a flush just after the last _process(),
similarly to how quit_workers() function is written in the
test_distributor.c fixes the issue.
Additionally the issue disappears when I remove the rdtsc delay code
inside the rte_distributor_request_pkt().
However I can't get this to reproduce on x86 (even with SIMD forced
off) and with artificial delays, which is why I wonder whether I'm not
actually hiding some other issue.
Looking at the implementation of the distributor, it is based on
__atomic_* builtins and the only platform related bit in the fast-path
is the rte_rdtsc() and rte_pause(). There may be some issues in the
toolchain (I've tried so far with the Ubuntu one - 10.2.0-8ubuntu1).
I should add that all unit tests for distributor are passing so either
there's some coverage corner case or the implementation works on RISC-V.
As for RDTSC I'm using a sleep-stable time counter with 1MHz frequency
and switching to high resolution cycle counter also removes the issue
but that's the same as removing the rdtsc delay as mentioned above.
I'd love to hear from You if this fix makes any sense.
While modifying this test, I've also pulled in a fix from
test_distributor.c which ensures that each thread gets his own wakeup
packet as it's possible that when sending a burst of packets, they won't
be spread over all the workers.
Signed-off-by: Stanislaw Kardach
Fixes: 7c3287a10535 ("test/distributor: add performance test for burst mode")
Cc: david.h...@intel.com
Cc: l.wojciec...@partner.samsung.com
Cc: David Marchand
---
app/test/test_distributor_perf.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/app/test/test_distributor_perf.c b/app/test/test_distributor_perf.c
index b25f79a34..fdbeae6d2 100644
--- a/app/test/test_distributor_perf.c
+++ b/app/test/test_distributor_perf.c
@@ -188,13 +188,15 @@ quit_workers(struct rte_distributor *d, struct
rte_mempool *p)
rte_mempool_get_bulk(p, (void *)bufs, num_workers);
quit = 1;
- for (i = 0; i < num_workers; i++)
+ for (i = 0; i < num_workers; i++) {
bufs[i]->hash.usr = i << 1;
- rte_distributor_process(d, bufs, num_workers);
+ rte_distributor_process(d, &bufs[i], 1);
+ }
rte_mempool_put_bulk(p, (void *)bufs, num_workers);
rte_distributor_process(d, NULL, 0);
+ rte_distributor_flush(d);
rte_eal_mp_wait_lcore();
quit = 0;
worker_idx = 0;
--
2.27.0
[dpdk-dev] [PATCH v2 0/2] test/distributor: perf burst mode quit fixes
This series addresses two issues: 1. Worker threads hang when finishing the burst-mode distributor perf test. This was observed on a RISC-V platform as well as reproduced on x86. 2. Potential lack of fairness in final wakeup notification distribution in burst mode. Though this issue was not observed, the change is in line with the functional tests. --- RFC -> V2 - Split 2 fixes into separate patches. - Added review/test/ack tags from the RFC discussion. --- Stanislaw Kardach (2): test/distributor: fix worker notification in burst test/distributor: fix burst flush on worker quit app/test/test_distributor_perf.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.27.0
[dpdk-dev] [PATCH v2 1/2] test/distributor: fix worker notification in burst
Because a single worker can process more than one packet from the
distributor, the final set of notifications in burst mode should be
sent one-by-one to ensure that each worker has a chance to wake up.
This fix mirrors the change done in the functional test by
commit f72bff0ec272 ("test/distributor: fix quitting workers in burst
mode").
Fixes: c3eabff124e6 ("distributor: add unit tests")
Cc: bruce.richard...@intel.com
Signed-off-by: Stanislaw Kardach
Acked-by: David Hunt
Tested-by: Lukasz Wojciechowski
Reviewed-by: Lukasz Wojciechowski
---
app/test/test_distributor_perf.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/app/test/test_distributor_perf.c b/app/test/test_distributor_perf.c
index b25f79a34..371a14ba4 100644
--- a/app/test/test_distributor_perf.c
+++ b/app/test/test_distributor_perf.c
@@ -188,9 +188,10 @@ quit_workers(struct rte_distributor *d, struct rte_mempool
*p)
rte_mempool_get_bulk(p, (void *)bufs, num_workers);
quit = 1;
- for (i = 0; i < num_workers; i++)
+ for (i = 0; i < num_workers; i++) {
bufs[i]->hash.usr = i << 1;
- rte_distributor_process(d, bufs, num_workers);
+ rte_distributor_process(d, &bufs[i], 1);
+ }
rte_mempool_put_bulk(p, (void *)bufs, num_workers);
--
2.27.0
[dpdk-dev] [PATCH v2 2/2] test/distributor: fix burst flush on worker quit
While working on RISC-V port I have encountered a situation where worker
threads get stuck in the rte_distributor_return_pkt() function in the
burst test.
Investigation showed some of the threads enter this function with
flag RTE_DISTRIB_GET_BUF set in the d->retptr64[0]. At the same time the
main thread has already passed rte_distributor_process() so nobody will
clear this flag and hence workers can't return.
What I've noticed is that adding a flush just after the last _process(),
similarly to how quit_workers() function is written in the
test_distributor.c fixes the issue.
Lukasz Wojciechowski reproduced the same issue on x86 using a VM with 32
emulated CPU cores to force some lcores not to be woken up.
Fixes: 7c3287a10535 ("test/distributor: add performance test for burst mode")
Cc: David Marchand
Signed-off-by: Stanislaw Kardach
Acked-by: David Hunt
Tested-by: Lukasz Wojciechowski
Reviewed-by: Lukasz Wojciechowski
---
app/test/test_distributor_perf.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/app/test/test_distributor_perf.c b/app/test/test_distributor_perf.c
index 371a14ba4..fdbeae6d2 100644
--- a/app/test/test_distributor_perf.c
+++ b/app/test/test_distributor_perf.c
@@ -196,6 +196,7 @@ quit_workers(struct rte_distributor *d, struct rte_mempool
*p)
rte_mempool_put_bulk(p, (void *)bufs, num_workers);
rte_distributor_process(d, NULL, 0);
+ rte_distributor_flush(d);
rte_eal_mp_wait_lcore();
quit = 0;
worker_idx = 0;
--
2.27.0
Re: [dpdk-dev] L3fwd mode in testpmd
On Wed, Apr 28, 2021 at 09:44:54PM +, Honnappa Nagarahalli wrote: > [Honnappa] Sorry, I do not understand this. I see that vector code is under > compile time flag as below > > #if defined RTE_ARCH_X86 || defined __ARM_NEON > l3fwd_em_send_packets(nb_rx, pkts_burst, > portid, qconf); > #else >l3fwd_em_no_opt_send_packets(nb_rx, pkts_burst, > portid, qconf); > #endif Take a look at the ifdef tree at the top of l3fwd_em.c, here: http://git.dpdk.org/dpdk/tree/examples/l3fwd/l3fwd_em.c#n218 #if defined(__SSE2__) ... #else #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain #endif -- Best Regards, Stanislaw Kardach
Re: [dpdk-dev] L3fwd mode in testpmd
On Thu, Apr 29, 2021 at 08:31:03AM +, Ananyev, Konstantin wrote: > Hi Stanislaw, > > > > > On Wed, Apr 28, 2021 at 09:44:54PM +, Honnappa Nagarahalli wrote: > > > > > [Honnappa] Sorry, I do not understand this. I see that vector code is > > > under compile time flag as below > > > > > > #if defined RTE_ARCH_X86 || defined __ARM_NEON > > > l3fwd_em_send_packets(nb_rx, pkts_burst, > > > portid, qconf); > > > #else > > >l3fwd_em_no_opt_send_packets(nb_rx, pkts_burst, > > > portid, qconf); > > > #endif > > Take a look at the ifdef tree at the top of l3fwd_em.c, here: > > http://git.dpdk.org/dpdk/tree/examples/l3fwd/l3fwd_em.c#n218 > > > > #if defined(__SSE2__) > > ... > > #else > > #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain > > #endif > > > > I think it is just a flaw and needs to be fixed. > Patch would help here 😊 > Konstantin It looks as if implementing em_mask_key() is enough to get l3fwd working. However to me this ifdef seems tricky. How should a scalar implementation handle the xmm_t type? rte_xmm_t looks like an API type/union, but both are not mentioned in documentation and are in platform dependent rte_vect.h only. So either I add another case for RISC-V or (what seems more proper) add an else clause implementation. However then should I change this function to take rte_xmm_t? If not is casting xmm_t to i.e. int32_t[] always valid? Even if I change to rte_xmm_t, it's not a stable API type, is it? So what guarantee do I have that it maps to int32_t bit-wise on every platform? I think the semantic requirements of xmm_t typedef are a bit undefined as well as the vector handling across the architectures (being something rather arch specific). I don't have a clear idea on how to solve this yet and I would not like to hijack this discussion with vector stuff. Though I may be missing some obvious solution here. Any idea is welcome. :) -- Best Regards, Stanislaw Kardach
Re: [dpdk-dev] L3fwd mode in testpmd
On Thu, Apr 29, 2021 at 11:47:30AM +, Ananyev, Konstantin wrote: > > > > It looks as if implementing em_mask_key() is enough to get l3fwd > > working. However to me this ifdef seems tricky. How should a scalar > > implementation handle the xmm_t type? rte_xmm_t looks like an API > > type/union, but both are not mentioned in documentation and are in > > platform dependent rte_vect.h only. > > So either I add another case for RISC-V or (what seems more proper) add > > an else clause implementation. However then should I change this function > > to take rte_xmm_t? If not is casting xmm_t to i.e. int32_t[] always > > valid? Even if I change to rte_xmm_t, it's not a stable API type, is it? > > So what guarantee do I have that it maps to int32_t bit-wise on every > > platform? > > > > I think the semantic requirements of xmm_t typedef are a bit undefined as > > well as the vector handling across the architectures (being something > > rather arch specific). I don't have a clear idea on how to solve this > > yet and I would not like to hijack this discussion with vector stuff. > > > > Though I may be missing some obvious solution here. Any idea is welcome. > > :) > > I think it should be possible to replace xmm_t with rte_xmm_t in > ipv(4|6)_5tuple_host > and make em_mask_key to take 'rte_xmm_t *' as a parameter/return value > instead of xmm_t. > With that in place scalar version seems straightforward. > Of course perf regression test would be needed after such changes, > but I think with '-O3' it should be no difference. > I did that and it works in practice. I'm more asking about the lack of definition in rte_xmm_t semantics. Because once it's in an example, people may start assuming it's OK to use it this way. If it is OK, then I'll just post a patch, otherwise we need a separate discussion. -- Best Regards, Stanislaw Kardach
Re: [dpdk-dev] [PATCH v5 3/5] test/hash: add additional thash tests
On Thu, Apr 29, 2021 at 12:17:08PM +0300, Medvedkin, Vladimir wrote: > > Test Failed > > RTE>> > > --- stderr --- > > EAL: Detected 2 lcore(s) > > EAL: Detected 1 NUMA nodes > > EAL: Detected shared linkage of DPDK > > EAL: Multi-process socket /var/run/dpdk/thash_autotest/mp_socket > > EAL: Selected IOVA mode 'PA' > > EAL: No available 1048576 kB hugepages reported > > EAL: VFIO support initialized > > APP: HPET is not enabled, using TSC as default timer > > HASH: Can't add helper due to conflict with existing helper second_range > > HASH: Can't generate m-sequence due to period overflow > > EAL: Test assert test_adjust_tuple line 559 failed: can not adjust > > tuple, ret -17 > > I can see the same issue on my side. Happening randomly, more often on a RISC-V target than on my laptop (i5-10210U). Though the reproduction seems to be a lot of patience and the following: meson test --repeat 10 DPDK:fast-tests / thash_autotest I wonder if it can be related to the desired_value in test_adjust_tuple being a randomized value without setting the seed prior to the test? I haven't analyzed the code in-depth but it seems that the rte_thash_add_helper() also uses a random lfsr which is then used in the subkey generation. Could this contribute to the randomness of the issue? -- Best Regards, Stanislaw Kardach
Re: [dpdk-dev] [PATCH v2] hash: fix tuple adjustment
);
> +
> for (i = 0; i < attempts; i++) {
> for (j = 0; j < (tuple_len / 4); j++)
> tmp_tuple[j] =
> @@ -651,14 +730,12 @@ rte_thash_adjust_tuple(struct rte_thash_ctx *ctx,
>
> /*
>* Hint: LSB of adj_bits corresponds to
> - * offset + len bit of tuple
> + * offset + len bit of the subtuple
>*/
> - for (j = 0; j < sizeof(uint32_t) * CHAR_BIT; j++) {
> - bit = (adj_bits >> j) & 0x1;
> - if (bit)
> - xor_bit(tuple, bit, h->tuple_offset +
> - h->tuple_len - 1 - j);
> - }
> + offset = h->tuple_offset + h->tuple_len - ctx->reta_sz_log;
> + tmp = read_unaligned_bits(tuple, ctx->reta_sz_log, offset);
> + tmp ^= adj_bits;
> + write_unaligned_bits(tuple, ctx->reta_sz_log, offset, tmp);
>
> if (fn != NULL) {
> ret = (fn(userdata, tuple)) ? 0 : -EEXIST;
> @@ -666,13 +743,15 @@ rte_thash_adjust_tuple(struct rte_thash_ctx *ctx,
> return 0;
> else if (i < (attempts - 1)) {
Small nit. This comment should be updated as the bits aren't random
anymore, just incremented.
> /* Update tuple with random bits */
> - for (j = 0; j < h->tuple_len; j++) {
> - bit = rte_rand() & 0x1;
> - if (bit)
> - xor_bit(tuple, bit,
> - h->tuple_offset +
> - h->tuple_len - 1 - j);
> - }
> + tmp_len = RTE_MIN(sizeof(uint32_t) * CHAR_BIT,
> + h->tuple_len - ctx->reta_sz_log);
> + offset -= tmp_len;
> + tmp = read_unaligned_bits(tuple, tmp_len,
> + offset);
> + tmp++;
> + tmp &= (1 << tmp_len) - 1;
> + write_unaligned_bits(tuple, tmp_len, offset,
> + tmp);
> }
> } else
> return 0;
> --
> 2.7.4
>
Makes the issue not visible on both x86 and RISC-V.
Tested-by: Stanislaw Kardach
Reviewed-by: Stanislaw Kardach
--
Best Regards,
Stanislaw Kardach
[PATCH RESEND v4 0/8] Introduce support for RISC-V architecture
RESEND: To trigger CI as all dependent patches have been merged already. This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v4: - Update RISC-V cross-compilation docs to remove vendor-specific instructions and better match the Ubuntu environment. - Remove optional "fence" removal in the CYCLE and TIME counter reads as those are irrelevant compared to the cost of a firmware call that allowed such removal. The per-platform build-configuration is left in meson files for setting '-mtune' and reference for future platforms. - Update cross-files to specify PKG_CONFIG_LIBDIR instead of relying on the riscv64-linux-gnu-pkg-config wrapper which was removed from Ubuntu anyway. Also use sys_root properly instead of using c_args directly. - Note: rte_rdtsc handling is left as it was in v3: TIME counter default, CYCLE via compile-time option. This is mostly due to CYCLE being core-local with values differing among cores which causes timer_autotest to run overly long if it so happens that CYCLE on core 0 is ahead of other cores' CYCLEs. This makes TIME counter more stable for general usage. Since CYCLE read in userspace can be disabled by the kernel-mode (it isn't currently), the compile-time approach is taken, same as with Aarch64. - Added details on --no-huge tests failing in the known_issues.rst. - Additional notes on tests: - link_bonding_mode4_autotest succeeds and then dpdk-test fails with segmentation fault randomly when run directly (via DPDK_TEST env variable) with MALLOC_PERTURB_. This was not noticed in any other test suggesting that there is a race condition somewhere in the link_bonding PMD that leads to use-after-free (since MALLOC_PERTURB_ causes free() to re-initialize freed memory to a given value). - ipsec_perf_autotest currently does not check whether there is any crypto device available (as ipsec_autotest does) and therefore fails. v3: - Limit test-meson-builds.sh testing to a generic rv64gc configuration. Previous version was missing this change by mistake. v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. [1] http://lists.infradead.org/pipermail/opensbi/2021-June/001219.html Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job .ci/linux-build.sh| 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 +++ app/test/test_xmmt_ops.h | 16 +++ config/meson.build| 2 + config/riscv/meson.build | 131 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 20 +++ devtools/test-meson-builds.sh | 4 + doc/guides/contributing/design.rst
[PATCH RESEND v4 1/8] eal: add initial support for RISC-V architecture
From: Michal Mazurek Add all necessary elements for DPDK to compile and run EAL on SiFive Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc) core complex. This includes: - EAL library implementation for rv64imafdc ISA. - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the U74 core. Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain. Clang compilation currently not supported due to issues with missing relocation relaxation. Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime (default) and unstable high-resolution using rdcycle. User can override the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of both DPDK and the application. The reasoning for this is as follows. The RISC-V ISA mandates that clock read by rdtime has to be of constant period and synchronized between all hardware threads within 1 tick (chapter 10.1 in version 20191213 of RISC-V spec). However this clock may not be of high-enough frequency for dataplane uses. I.e. on HiFive Unmatched (FU740) it is 1MHz. There is a high-resolution alternative in form of rdcycle which is clocked at the core clock frequency. The drawbacks are that it may be disabled during sleep (WFI), its frequency might change due to DVFS and it is core-local and therefore cannot be used as a wall-clock. It can however be used for micro-benchmarking user applications, similarly to Aarch64's PMCCNTR PMU counter. The platform is currently marked as linux-only because rte_cycles implementation uses the timebase-frequency device-tree node read through the proc file system. Such approach was chosen because Linux kernel depends on the presence of this device-tree node. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. The compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Known checkpatch errors/warnings: - ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline assembly declarations. - vector_size compiler attribute used in rte_vect.h directly. - rte_*mb() used directly in rte_atomic.h to reduce code duplication. - __atomic_thread_fence() used to implement rte_atomic_thread_fence(). Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach --- MAINTAINERS | 6 + app/test/test_xmmt_ops.h | 16 +++ config/meson.build| 2 + config/riscv/meson.build | 131 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 20 +++ doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 115 +++ doc/guides/linux_gsg/index.rst| 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/rel_notes/known_issues.rst | 10 +- doc/guides/rel_notes/release_22_07.rst| 8 ++ drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/meson.build | 6 + drivers/net/memif/meson.build | 5 + drivers/net/tap/meson.build | 5 + examples/l3fwd/meson.build| 6 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h| 52 +++ lib/eal/riscv/include/rte_byteorder.h | 44 ++ lib/eal/riscv/include/rte_cpuflags.h | 55 lib/eal/riscv/include/rte_cycles.h| 101 ++ lib/eal/riscv/include/rte_io.h| 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h| 63 + lib/eal/riscv/include/rte_pause.h | 31 + lib/eal/riscv/include/rte_pflock.h| 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 +++ lib/eal/riscv/include/rte_rwlock.h| 44 ++ lib/eal/riscv/include/rte_spinlock.h | 67 + lib/eal/riscv/include/rte_ticketlock.h| 21 +++ lib/eal/riscv/include/rte_vect.h | 55 lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 lib/eal/riscv/rte_cycles.c| 77 ++ lib/eal/riscv/rte_hypervisor.c| 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 meson.build | 2 + 40 files changed, 1323 insertions(+), 4 deletions(-) create mod
[PATCH RESEND v4 2/8] net/ixgbe: enable vector stubs for RISC-V
Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++--
drivers/net/ixgbe/meson.build | 6 --
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini
b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows = Y
ARMv8= Y
x86-32 = Y
x86-64 = Y
+rv64 = Y
[rte_flow items]
eth = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.30.2
[PATCH RESEND v4 4/8] net/tap: set BPF syscall ID for RISC-V
Define the missing __NR_bpf syscall id to enable the tap PMD.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
drivers/net/tap/meson.build | 5 -
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
build = false
reason = 'only supported on Linux'
endif
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
sources = files(
'rte_eth_tap.c',
'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
# define __NR_bpf 351
# elif defined(__powerpc__)
# define __NR_bpf 361
+# elif defined(__riscv)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.30.2
[PATCH RESEND v4 3/8] net/memif: set memfd syscall ID on RISC-V
Define the missing __NR_memfd_create syscall id to enable the memif PMD. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 - drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.30.2
[PATCH RESEND v4 5/8] examples/l3fwd: enable RISC-V operation
Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
examples/l3fwd/l3fwd_em.c | 8
examples/l3fwd/l3fwd_fib.c | 2 ++
examples/l3fwd/meson.build | 6 --
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 6f8d94f120..10be24c61d 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
return vec_and(data, mask);
}
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 26d0767ae2..e02e4b3f5a 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
#include "l3fwd_neon.h"
#elif defined RTE_ARCH_PPC_64
#include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
#endif
#include "l3fwd_event.h"
#include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if dpdk_conf.has('RTE_ARCH_RISCV')
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.30.2
[PATCH RESEND v4 6/8] test/cpuflags: add test for RISC-V cpu flag
From: Michal Mazurek
Add checks for all flag values defined in the RISC-V misa CSR register.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
app/test/test_cpuflags.c | 81
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
[PATCH RESEND v4 7/8] devtools: add RISC-V to test-meson-builds.sh
Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- devtools/test-meson-builds.sh | 4 1 file changed, 4 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..f732dccf6c 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,10 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configuration +build build-riscv64-linux-gcc $srcdir/config/riscv/riscv64_linux_gcc ABI \ + $use_shared + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc -- 2.30.2
[PATCH RESEND v4 8/8] ci: add RISCV64 cross compilation job
Checks cross-compilation using Ubuntu 20.04 x86.
Signed-off-by: David Marchand
Signed-off-by: Stanislaw Kardach
---
.ci/linux-build.sh | 4
.github/workflows/build.yml | 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 1de8962f0e..06104eca22 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
fi
+if [ "$RISCV64" = "true" ]; then
+cross_file=config/riscv/riscv64_linux_gcc
+fi
+
if [ -n "$cross_file" ]; then
OPTS="$OPTS --cross-file $cross_file"
fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ad8ad1a187..7c8528cb04 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -26,6 +26,7 @@ jobs:
MINI: ${{ matrix.config.mini != '' }}
PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
REF_GIT_TAG: v22.03
+ RISCV64: ${{ matrix.config.cross == 'riscv64' }}
RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
strategy:
@@ -74,6 +75,10 @@ jobs:
compiler: gcc
library: shared
cross: ppc64le
+ - os: ubuntu-20.04
+compiler: gcc
+library: shared
+cross: riscv64
steps:
- name: Checkout sources
@@ -132,8 +137,12 @@ jobs:
if: env.PPC64LE == 'true'
run: sudo apt install -y gcc-powerpc64le-linux-gnu
libc6-dev-ppc64el-cross
pkg-config-powerpc-linux-gnu
+- name: Install riscv64 cross compiling packages
+ if: env.RISCV64 == 'true'
+ run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+pkg-config-riscv64-linux-gnu
- name: Install test tools packages
- if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS ==
'true'
+ if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 !=
'true' || env.RUN_TESTS == 'true'
run: sudo apt install -y gdb
- name: Install doc generation packages
if: env.BUILD_DOCS == 'true'
--
2.30.2
[PATCH 0/3] Fix xmm_t to rte_xmm_t scalar conversion
As David noticed in [1] there is an issue with C++ compilation of the rte_vect.h header in RISC-V. Upon closer inspection, the problem appears on all architectures due to the type conversion rules in C++. More precisely a union type rte_xmm_t requires a conversion constructor from xmm_t type. The most obvious fix is to use a structure initializer for such copies (since rte_xmm_t union contains xmm_t anyway). The generated assembly at -O2 is exactly the same, so there's no real impact. The bigger question is whether accessing bits of the architecture specific xmm_t type in an array fashion is always correct? All current architectures define rte_xmm_t in the same manner implying that. Additionally change RISC-V CI settings to use crossbuild-essential-riscv64 package which provides tools that enable C++ checks. [1] http://mails.dpdk.org/archives/dev/2022-June/243683.html Stanislaw Kardach (3): eal/riscv: fix xmm_t casting for C++ lpm: fix xmm_t casting for C++ in scalar version ci: use crossbuild-essential-riscv64 for compiling .github/workflows/build.yml | 3 +-- lib/eal/riscv/include/rte_vect.h | 4 ++-- lib/lpm/rte_lpm_scalar.h | 11 ++- 3 files changed, 9 insertions(+), 9 deletions(-) -- 2.30.2
[PATCH 2/3] lpm: fix xmm_t casting for C++ in scalar version
rte_xmm_t is a union type which wraps around xmm_t and maps its contents
to scalar structures. Since C++ has stricter type conversion rules than
C, the rte_xmm_t::x has to be used instead of C-casting.
The generated assembly is identical to the code without the fix (checked
both on x86 and RISC-V).
Signed-off-by: Stanislaw Kardach
---
lib/lpm/rte_lpm_scalar.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
index f0d9f37894..161b40ff80 100644
--- a/lib/lpm/rte_lpm_scalar.h
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -15,18 +15,19 @@ extern "C" {
static inline void
rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
- uint32_t defv)
+uint32_t defv)
{
+ rte_xmm_t xip = { .x = ip };
uint32_t nh;
int ret;
- ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[0], &nh);
+ ret = rte_lpm_lookup(lpm, xip.u32[0], &nh);
hop[0] = (ret == 0) ? nh : defv;
- ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[1], &nh);
+ ret = rte_lpm_lookup(lpm, xip.u32[1], &nh);
hop[1] = (ret == 0) ? nh : defv;
- ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[2], &nh);
+ ret = rte_lpm_lookup(lpm, xip.u32[2], &nh);
hop[2] = (ret == 0) ? nh : defv;
- ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[3], &nh);
+ ret = rte_lpm_lookup(lpm, xip.u32[3], &nh);
hop[3] = (ret == 0) ? nh : defv;
}
--
2.30.2
[PATCH 1/3] eal/riscv: fix xmm_t casting for C++
rte_xmm_t is a union type which wraps around xmm_t and maps its contents
to scalar structures. Since C++ has stricter type conversion rules than
C, the rte_xmm_t::x has to be used instead of C-casting.
Signed-off-by: Stanislaw Kardach
---
lib/eal/riscv/include/rte_vect.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
index 4600521c20..2f97f437a2 100644
--- a/lib/eal/riscv/include/rte_vect.h
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -41,8 +41,8 @@ vect_load_128(void *p)
static inline xmm_t
vect_and(xmm_t data, xmm_t mask)
{
- rte_xmm_t ret = (rte_xmm_t)data;
- rte_xmm_t m = (rte_xmm_t)mask;
+ rte_xmm_t ret = {.x = data };
+ rte_xmm_t m = {.x = mask };
ret.u64[0] &= m.u64[0];
ret.u64[1] &= m.u64[1];
return ret.x;
--
2.30.2
[PATCH 3/3] ci: use crossbuild-essential-riscv64 for compiling
The current packages installed for RISC-V build check do not contain a C++ compiler, which hid an issue with C++ type conversion in the rte_vect.h header on RISC-V or in the scalar implementation of the LPM x4 lookup. Now that this issue is fixed, use the full toolchain install to enable the C++ test. Besides, the user's guide for RISC-V cross-compilation recommends the use of crossbuild-essential-riscv64. Signed-off-by: Stanislaw Kardach --- .github/workflows/build.yml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 7c8528cb04..c0d2829d0e 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -139,8 +139,7 @@ jobs: pkg-config-powerpc-linux-gnu - name: Install riscv64 cross compiling packages if: env.RISCV64 == 'true' - run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross -pkg-config-riscv64-linux-gnu + run: sudo apt install -y crossbuild-essential-riscv64 - name: Install test tools packages if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true' run: sudo apt install -y gdb -- 2.30.2
[PATCH] doc: fix formatting in RISC-V release notes entry
There was an extra * in the title of the RISC-V entry. It gets rendered in the documentation output giving an impression that there will be a footnote for this entry, which is not the case. Signed-off-by: Stanislaw Kardach --- doc/guides/rel_notes/release_22_07.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst index faddcef667..0172a6b82f 100644 --- a/doc/guides/rel_notes/release_22_07.rst +++ b/doc/guides/rel_notes/release_22_07.rst @@ -55,7 +55,7 @@ New Features Also, make sure to start the actual text at the margin. === -* **Added initial RISC-V architecture support.*** +* **Added initial RISC-V architecture support.** Added EAL implementation for RISC-V architecture. The initial device the porting was tested on is -- 2.30.2
[PATCH 1/1] doc: expand description of no-huge and PMD issue
Add more details to the description of a known issue of PMDs not being usable when --no-huge EAL command line parameter is used. The issue actually happens whenever there is a need for physical addresses, even when there is no PMD attached. Signed-off-by: Stanislaw Kardach --- doc/guides/rel_notes/known_issues.rst | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/doc/guides/rel_notes/known_issues.rst b/doc/guides/rel_notes/known_issues.rst index 570550843a..2e0ffbdd93 100644 --- a/doc/guides/rel_notes/known_issues.rst +++ b/doc/guides/rel_notes/known_issues.rst @@ -249,11 +249,15 @@ PMD does not work with --no-huge EAL command line parameter --- **Description**: - Currently, the DPDK does not store any information about memory allocated by ``malloc()` (for example, NUMA node, - physical address), hence PMDs do not work when the ``--no-huge`` command line parameter is supplied to EAL. + Currently, the DPDK does not store any information about memory allocated by ``malloc()`` (for example, NUMA node, + physical address), hence PMDs do not work when the ``--no-huge`` command line parameter is supplied to EAL. This + happens when using non-IOMMU based UIO drivers (i.e. ``igb_uio`` or ``uio_pci_generic``) or when IOVA mode is + explicitly set to use physical addresses (via the ``--iova-mode=pa`` EAL parameter). **Implication**: - Sending and receiving data with PMD will not work. + Sending and receiving data with PMD will not work. Unit tests checking ``--no-huge`` operation will fail if + there is a device bound to the PMD (eal_flags_n_opt_autotest, eal_flags_no_huge_autotest, + eal_flags_vdev_opt_autotest, eal_flags_misc_autotest). **Resolution/Workaround**: Use huge page memory or use VFIO to map devices. -- 2.30.2
[PATCH 0/2] fix C++ include checks in cross-compilation
Meson detects the C++ cross-compiler during configuration and based on that reports whether C++ language is available or not. The C++ include check target (buildtools/chkincs/chkincs-cpp) is only built when C++ language is available. There are 2 issues that currently prevent those checks to be run in cross-compiled environments: * PowerPC and ARM cross-files define cpp instead of g++ as C++ compiler. That's wrong because cpp is a C Preprocessor binary. * The CI workflow file does not install a g++ cross-compiler. This patchset fixes both issues. Stanislaw Kardach (2): config: Use G++ as C++ compiler ci: use crossbuild-essential packages .github/workflows/build.yml| 6 ++ config/arm/arm32_armv8_linux_gcc | 2 +- config/arm/arm64_armada_linux_gcc | 2 +- config/arm/arm64_armv8_linux_gcc | 2 +- config/arm/arm64_bluefield_linux_gcc | 2 +- config/arm/arm64_centriq2400_linux_gcc | 2 +- config/arm/arm64_cn10k_linux_gcc | 2 +- config/arm/arm64_cn9k_linux_gcc| 2 +- config/arm/arm64_dpaa_linux_gcc| 2 +- config/arm/arm64_emag_linux_gcc| 2 +- config/arm/arm64_graviton2_linux_gcc | 2 +- config/arm/arm64_kunpeng920_linux_gcc | 2 +- config/arm/arm64_kunpeng930_linux_gcc | 2 +- config/arm/arm64_n1sdp_linux_gcc | 2 +- config/arm/arm64_n2_linux_gcc | 2 +- config/arm/arm64_stingray_linux_gcc| 2 +- config/arm/arm64_thunderx2_linux_gcc | 2 +- config/arm/arm64_thunderxt83_linux_gcc | 2 +- config/arm/arm64_thunderxt88_linux_gcc | 2 +- config/ppc/ppc64le-power8-linux-gcc| 2 +- config/ppc/ppc64le-power8-linux-gcc-ubuntu | 2 +- 21 files changed, 22 insertions(+), 24 deletions(-) -- 2.30.2
[PATCH 1/2] config: Use G++ as C++ compiler
Through some mixup all cross-files for PowerPC and ARM platforms were using C Preprocessor (cpp) instead of GCC (g++). This caused meson to fail detecting the C++ compiler presence and therefore disabling some targets (i.e. C++ include file checks). Signed-off-by: Stanislaw Kardach --- config/arm/arm32_armv8_linux_gcc | 2 +- config/arm/arm64_armada_linux_gcc | 2 +- config/arm/arm64_armv8_linux_gcc | 2 +- config/arm/arm64_bluefield_linux_gcc | 2 +- config/arm/arm64_centriq2400_linux_gcc | 2 +- config/arm/arm64_cn10k_linux_gcc | 2 +- config/arm/arm64_cn9k_linux_gcc| 2 +- config/arm/arm64_dpaa_linux_gcc| 2 +- config/arm/arm64_emag_linux_gcc| 2 +- config/arm/arm64_graviton2_linux_gcc | 2 +- config/arm/arm64_kunpeng920_linux_gcc | 2 +- config/arm/arm64_kunpeng930_linux_gcc | 2 +- config/arm/arm64_n1sdp_linux_gcc | 2 +- config/arm/arm64_n2_linux_gcc | 2 +- config/arm/arm64_stingray_linux_gcc| 2 +- config/arm/arm64_thunderx2_linux_gcc | 2 +- config/arm/arm64_thunderxt83_linux_gcc | 2 +- config/arm/arm64_thunderxt88_linux_gcc | 2 +- config/ppc/ppc64le-power8-linux-gcc| 2 +- config/ppc/ppc64le-power8-linux-gcc-ubuntu | 2 +- 20 files changed, 20 insertions(+), 20 deletions(-) diff --git a/config/arm/arm32_armv8_linux_gcc b/config/arm/arm32_armv8_linux_gcc index 7f2977e49d..269a60ba19 100644 --- a/config/arm/arm32_armv8_linux_gcc +++ b/config/arm/arm32_armv8_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'arm-linux-gnueabihf-gcc'] -cpp = ['ccache', 'arm-linux-gnueabihf-cpp'] +cpp = ['ccache', 'arm-linux-gnueabihf-g++'] ar = 'arm-linux-gnueabihf-gcc-ar' strip = 'arm-linux-gnueabihf-strip' pkgconfig = 'arm-linux-gnueabihf-pkg-config' diff --git a/config/arm/arm64_armada_linux_gcc b/config/arm/arm64_armada_linux_gcc index 1566999101..635b4946a3 100644 --- a/config/arm/arm64_armada_linux_gcc +++ b/config/arm/arm64_armada_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'] -cpp = ['ccache', 'aarch64-linux-gnu-cpp'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] ar = 'aarch64-linux-gnu-ar' as = 'aarch64-linux-gnu-as' strip = 'aarch64-linux-gnu-strip' diff --git a/config/arm/arm64_armv8_linux_gcc b/config/arm/arm64_armv8_linux_gcc index 048c2d9f29..529694b49d 100644 --- a/config/arm/arm64_armv8_linux_gcc +++ b/config/arm/arm64_armv8_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'] -cpp = ['ccache', 'aarch64-linux-gnu-cpp'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] ar = 'aarch64-linux-gnu-gcc-ar' strip = 'aarch64-linux-gnu-strip' pkgconfig = 'aarch64-linux-gnu-pkg-config' diff --git a/config/arm/arm64_bluefield_linux_gcc b/config/arm/arm64_bluefield_linux_gcc index 38df3c198b..1286227915 100644 --- a/config/arm/arm64_bluefield_linux_gcc +++ b/config/arm/arm64_bluefield_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'] -cpp = ['ccache', 'aarch64-linux-gnu-cpp'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] ar = 'aarch64-linux-gnu-gcc-ar' strip = 'aarch64-linux-gnu-strip' pkgconfig = 'aarch64-linux-gnu-pkg-config' diff --git a/config/arm/arm64_centriq2400_linux_gcc b/config/arm/arm64_centriq2400_linux_gcc index 0966eef2c5..bc8737e072 100644 --- a/config/arm/arm64_centriq2400_linux_gcc +++ b/config/arm/arm64_centriq2400_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'] -cpp = ['ccache', 'aarch64-linux-gnu-cpp'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] ar = 'aarch64-linux-gnu-gcc-ar' strip = 'aarch64-linux-gnu-strip' pkgconfig = 'aarch64-linux-gnu-pkg-config' diff --git a/config/arm/arm64_cn10k_linux_gcc b/config/arm/arm64_cn10k_linux_gcc index 201e0ccd59..05d2d64cf2 100644 --- a/config/arm/arm64_cn10k_linux_gcc +++ b/config/arm/arm64_cn10k_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'] -cpp = ['ccache', 'aarch64-linux-gnu-cpp'] +cpp = ['ccache', 'aarch64-linux-gnu-g++'] ar = 'aarch64-linux-gnu-gcc-ar' strip = 'aarch64-linux-gnu-strip' pkgconfig = 'aarch64-linux-gnu-pkg-config' diff --git a/config/arm/arm64_cn9k_linux_gcc b/config/arm/arm64_cn9k_linux_gcc index a9b4d51958..7416454de0 100644 --- a/config/arm/arm64_cn9k_linux_gcc +++ b/config/arm/arm64_cn9k_linux_gcc @@ -1,6 +1,6 @@ [binaries] c = ['ccache', 'aarch64-linux-gnu-gcc'
[PATCH 2/2] ci: use crossbuild-essential packages
The crossbuild-essential- packages contain all necessary dependencies to cross-compile binaries for a given architecture including C and C++ compilers. Therefore use those instead of listing packages directly. This way C++ compiler is also installed and C++ include checks will be checked in CI for PowerPC and ARM. Signed-off-by: Stanislaw Kardach --- .github/workflows/build.yml | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c0d2829d0e..1106256539 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -128,15 +128,13 @@ jobs: run: sudo apt install -y gcc-multilib g++-multilib - name: Install aarch64 cross compiling packages if: env.AARCH64 == 'true' - run: sudo apt install -y gcc-aarch64-linux-gnu libc6-dev-arm64-cross -pkg-config-aarch64-linux-gnu + run: sudo apt install -y crossbuild-essential-arm64 - name: Install mingw cross compiling packages if: env.MINGW == 'true' run: sudo apt install -y mingw-w64 mingw-w64-tools - name: Install ppc64le cross compiling packages if: env.PPC64LE == 'true' - run: sudo apt install -y gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross -pkg-config-powerpc-linux-gnu + run: sudo apt install -y crossbuild-essential-ppc64el - name: Install riscv64 cross compiling packages if: env.RISCV64 == 'true' run: sudo apt install -y crossbuild-essential-riscv64 -- 2.30.2
[PATCH] config/riscv: name the cross file properly
Since the riscv64_linux_gcc was in fact a Ubuntu-specific cross-file,
rename it.
Signed-off-by: Stanislaw Kardach
---
.ci/linux-build.sh | 2 +-
config/riscv/{riscv64_linux_gcc => riscv64_linux_gcc_ubuntu} | 0
devtools/test-meson-builds.sh| 2 +-
doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst | 4 ++--
4 files changed, 4 insertions(+), 4 deletions(-)
rename config/riscv/{riscv64_linux_gcc => riscv64_linux_gcc_ubuntu} (100%)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 06104eca22..dcf4d4ccb3 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -75,7 +75,7 @@ if [ "$PPC64LE" = "true" ]; then
fi
if [ "$RISCV64" = "true" ]; then
-cross_file=config/riscv/riscv64_linux_gcc
+cross_file=config/riscv/riscv64_linux_gcc_ubuntu
fi
if [ -n "$cross_file" ]; then
diff --git a/config/riscv/riscv64_linux_gcc
b/config/riscv/riscv64_linux_gcc_ubuntu
similarity index 100%
rename from config/riscv/riscv64_linux_gcc
rename to config/riscv/riscv64_linux_gcc_ubuntu
diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index 04a85fe987..00b97a3e50 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -265,7 +265,7 @@ f=$srcdir/config/ppc/ppc64le-power8-linux-gcc
build build-ppc64-power8-gcc $f ABI $use_shared
# generic RISC-V
-f=$srcdir/config/riscv/riscv64_linux_gcc
+f=$srcdir/config/riscv/riscv64_linux_gcc_ubuntu
build build-riscv64-generic-gcc $f ABI $use_shared
# Test installation of the x86-generic target, to be used for checking
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
index 9e121645a8..84d1ea3aa6 100644
--- a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
@@ -74,7 +74,7 @@ To cross-compile DPDK for a desired target machine use the
following command::
For example if the target machine is a generic rv64gc RISC-V, use the following
command::
- meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
+ meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc_ubuntu
ninja -C riscv64-build-gcc
If riscv-gnu-toolchain is used, binary names should be updated to match. Update
@@ -106,7 +106,7 @@ Supported cross-compilation targets
Currently the following targets are supported:
-* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
+* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc_ubuntu``
* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
--
2.30.2
[dpdk-dev] [PATCH 0/3] add lock-free stack support discovery
The lock-free stack implementation (RTE_STACK_F_LF) is supported only on a subset of platforms, namely x86_64 and arm64. Platforms supporting 128b atomics have to opt-in to a generic or C11 implementations. All other platforms use a stubbed implementation for push/pop operations which are basically NOPs. However rte_stack_create() will not fail and application can proceed assuming it has a working lock-free stack. This means that among other things the stack_lf fast and perf tests will fail as if implementation is wrong (which one can argue is). Therefore this patchset tries to give user a way to check whether a lock_free is supported or not both at compile time (build flag) and at runtime (ENOTSUP errno in rte_stack_create). I have added cc to sta...@dpdk.org because check-git-log.sh suggested it. I'm not sure if adding a binary compatible change to API is worth sta...@dpdk.org. Cc: sta...@dpdk.org Stanislaw Kardach (3): stack: update lock-free supported archs stack: add compile flag for lock-free support test: run lock-free stack tests when supported app/test/test_stack.c | 4 app/test/test_stack_perf.c | 4 doc/guides/rel_notes/release_21_05.rst | 4 lib/librte_stack/rte_stack.c | 4 +++- lib/librte_stack/rte_stack.h | 3 ++- lib/librte_stack/rte_stack_lf.h| 5 + 6 files changed, 22 insertions(+), 2 deletions(-) -- 2.27.0
[dpdk-dev] [PATCH 1/3] stack: update lock-free supported archs
Since 7911ba047 lock-free stack is supported on arm64 but this
description was missing from the doxygen for the flag.
Signed-off-by: Stanislaw Kardach
Fixes: 7911ba0473e0 ("stack: enable lock-free implementation for aarch64")
Cc: phil.y...@arm.com
Cc: sta...@dpdk.org
---
lib/librte_stack/rte_stack.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/librte_stack/rte_stack.h b/lib/librte_stack/rte_stack.h
index 395b9ef83..b82c74e72 100644
--- a/lib/librte_stack/rte_stack.h
+++ b/lib/librte_stack/rte_stack.h
@@ -89,7 +89,7 @@ struct rte_stack {
/**
* The stack uses lock-free push and pop functions. This flag is only
- * supported on x86_64 platforms, currently.
+ * supported on x86_64 or arm64 platforms, currently.
*/
#define RTE_STACK_F_LF 0x0001
--
2.27.0
[dpdk-dev] [PATCH 2/3] stack: add lock-free support indication
Currently it is impossible to detect programatically whether lock-free
implementation of rte_stack is supported. One could check whether the
header guard for lock-free stubs is defined (_RTE_STACK_LF_STUBS_H_) but
that's an unstable implementation detail. Because of that currently all
lock-free ring creations silently succeed (as long as the stack header
is 16B long) which later leads to push and pop operations being NOPs.
The observable effect is that stack_lf_autotest fails on platforms not
supporting the lock-free. Instead it should just skip the lock-free test
altogether.
This commit adds a new errno value (ENOTSUP) that may be returned by
rte_stack_create() to indicate that a given combination of flags is not
supported on a current platform.
This is detected by checking a compile-time flag in the include logic in
rte_stack_lf.h which may be used by applications to check the lock-free
support at compile time.
Signed-off-by: Stanislaw Kardach
Fixes: 7911ba0473e0 ("stack: enable lock-free implementation for aarch64")
Cc: phil.y...@arm.com
Cc: sta...@dpdk.org
---
doc/guides/rel_notes/release_21_05.rst | 4
lib/librte_stack/rte_stack.c | 4 +++-
lib/librte_stack/rte_stack.h | 1 +
lib/librte_stack/rte_stack_lf.h| 5 +
4 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/doc/guides/rel_notes/release_21_05.rst
b/doc/guides/rel_notes/release_21_05.rst
index 6f5858c8f..42ed60da8 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -166,6 +166,10 @@ API Changes
* pci: The value ``PCI_ANY_ID`` is marked as deprecated
and can be replaced with ``RTE_PCI_ANY_ID``.
+* Lock-free ``rte_stack`` no longer silently ignores push and pop when it's not
+ supported on the current platform. Instead ``rte_stack_create()`` fails and
+ ``rte_errno`` is set to ``ENOTSUP``.
+
ABI Changes
---
diff --git a/lib/librte_stack/rte_stack.c b/lib/librte_stack/rte_stack.c
index 8a51fba17..10d3b2eeb 100644
--- a/lib/librte_stack/rte_stack.c
+++ b/lib/librte_stack/rte_stack.c
@@ -64,9 +64,11 @@ rte_stack_create(const char *name, unsigned int count, int
socket_id,
#ifdef RTE_ARCH_64
RTE_BUILD_BUG_ON(sizeof(struct rte_stack_lf_head) != 16);
-#else
+#endif
+#if !defined(RTE_STACK_LF_SUPPORTED)
if (flags & RTE_STACK_F_LF) {
STACK_LOG_ERR("Lock-free stack is not supported on your
platform\n");
+ rte_errno = ENOTSUP;
return NULL;
}
#endif
diff --git a/lib/librte_stack/rte_stack.h b/lib/librte_stack/rte_stack.h
index b82c74e72..27640f87b 100644
--- a/lib/librte_stack/rte_stack.h
+++ b/lib/librte_stack/rte_stack.h
@@ -205,6 +205,7 @@ rte_stack_free_count(struct rte_stack *s)
*- EEXIST - a stack with the same name already exists
*- ENOMEM - insufficient memory to create the stack
*- ENAMETOOLONG - name size exceeds RTE_STACK_NAMESIZE
+ *- ENOTSUP - platform does not support given flags combination.
*/
struct rte_stack *
rte_stack_create(const char *name, unsigned int count, int socket_id,
diff --git a/lib/librte_stack/rte_stack_lf.h b/lib/librte_stack/rte_stack_lf.h
index eb106e64e..f2b012cd0 100644
--- a/lib/librte_stack/rte_stack_lf.h
+++ b/lib/librte_stack/rte_stack_lf.h
@@ -13,6 +13,11 @@
#else
#include "rte_stack_lf_generic.h"
#endif
+
+/**
+ * Indicates that RTE_STACK_F_LF is supported.
+ */
+#define RTE_STACK_LF_SUPPORTED
#endif
/**
--
2.27.0
[dpdk-dev] [PATCH 3/3] test: run lock-free stack tests when supported
Use the recently added RTE_STACK_LF_SUPPORTED flag to disable the
lock-free stack tests at the compile time.
Perf test doesn't fail because rte_ring_create() succeeds, however
marking this test as skipped gives a better indication of what actually
was tested.
Signed-off-by: Stanislaw Kardach
Cc: sta...@dpdk.org
---
app/test/test_stack.c | 4
app/test/test_stack_perf.c | 4
2 files changed, 8 insertions(+)
diff --git a/app/test/test_stack.c b/app/test/test_stack.c
index 02422a32d..00efb38e2 100644
--- a/app/test/test_stack.c
+++ b/app/test/test_stack.c
@@ -373,7 +373,11 @@ test_stack(void)
static int
test_lf_stack(void)
{
+#if defined(RTE_STACK_LF_SUPPORTED)
return __test_stack(RTE_STACK_F_LF);
+#else
+ return TEST_SKIPPED;
+#endif
}
REGISTER_TEST_COMMAND(stack_autotest, test_stack);
diff --git a/app/test/test_stack_perf.c b/app/test/test_stack_perf.c
index 3590625c4..4ee40d5d1 100644
--- a/app/test/test_stack_perf.c
+++ b/app/test/test_stack_perf.c
@@ -349,7 +349,11 @@ test_stack_perf(void)
static int
test_lf_stack_perf(void)
{
+#if defined(RTE_STACK_LF_SUPPORTED)
return __test_stack_perf(RTE_STACK_F_LF);
+#else
+ return TEST_SKIPPED;
+#endif
}
REGISTER_TEST_COMMAND(stack_perf_autotest, test_stack_perf);
--
2.27.0
[dpdk-dev] [PATCH 1/3] test: disable no-huge test with PA IOVA
On linux systems without IOMMU support available (be it lack of
supported IOMMU or lack of IOMMU support in kernel), the IOVA mapping
will default to DMA with physical addresses. This implicitly requires
hugepage support (most prominently for performance reasons).
Therefore trying to run the eal_flags_no_huge_autotest in such scenario
is not a valid requirement.
To verify this even on x86 do (output from i5-10210U):
$ ./app/test/dpdk-test -m 18 --iova-mode=pa --no-huge
EAL: Detected 8 lcore(s)
EAL: Detected 1 NUMA nodes
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: FATAL: Cannot use IOVA as 'PA' since physical addresses are not available
EAL: Cannot use IOVA as 'PA' since physical addresses are not available
While doing:
$ sudo ./app/test/dpdk-test --iova-mode=pa
EAL: Detected 8 lcore(s)
EAL: Detected 1 NUMA nodes
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'PA'
EAL: No available 1048576 kB hugepages reported
EAL: Probing VFIO support...
EAL: VFIO support initialized
TELEMETRY: No legacy callbacks, legacy socket not created
APP: HPET is not enabled, using TSC as default timer
RTE>>
This commit finishes the above test early with SKIP status to signify
that no-huge support is simply not available.
Signed-off-by: Stanislaw Kardach
Cc: sta...@dpdk.org
---
app/test/test_eal_flags.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/app/test/test_eal_flags.c b/app/test/test_eal_flags.c
index 932fbe3d0..462dc6384 100644
--- a/app/test/test_eal_flags.c
+++ b/app/test/test_eal_flags.c
@@ -756,6 +756,15 @@ test_no_huge_flag(void)
#else
const char * prefix = "--file-prefix=nohuge";
#endif
+#ifdef RTE_EXEC_ENV_LINUX
+ /* EAL requires hugepages for RTE_IOVA_PA operation on linux.
+* The test application is run with RTE_IOVA_DC, so if at this point we
+* get RTE_IOVA_PA, it means that newly spawned process will also get
+* it.
+*/
+ if (rte_eal_iova_mode() == RTE_IOVA_PA)
+ return TEST_SKIPPED;
+#endif
/* With --no-huge */
const char *argv1[] = {prgname, prefix, no_huge};
--
2.27.0
[dpdk-dev] [PATCH 0/3] Increase test compatibility with PA IOVA
While working in some scenarios where only RTE_IOVA_PA is available I've noticed that some of the EAL tests are failing because of a totally different reason than the test itself. Namely the --no-huge flag and PA IOVA can't be used together and EAL init fails warning about this. This patchset tries to cleanup the --no-huge usage so that it doesn't hide the real state of tests when RTE_IOVA_PA is used (i.e. on platforms without IOMMU). This means skipping the no-huge test as it is not supported by design and removing no-huge usage on linux as it seems that it was previously used with --no-shconf to increase the compatibility with FreeBSD. That is if I'm not missing a bigger picture of using the --no-huge with --no-shconf on non-FreeBSD platforms. Stanislaw Kardach (3): test: disable no-huge test with PA IOVA test: disable no-huge where it's not necessary test: fix the -n unit test description app/test/test_eal_flags.c | 45 --- 1 file changed, 32 insertions(+), 13 deletions(-) -- 2.27.0
[dpdk-dev] [PATCH 2/3] test: disable no-huge where it's not necessary
In tests where no-shconf flag is used, no-huge is also passed due to
compatibility with FreeBSD system, as described in: b5d878e6d.
However on Linux systems with RTE_IOVA_PA (lack of or an incompatible
IOMMU) this causes issues since hugepages are required by EAL.
Therefore replace all occurrences of no_huge which don't actually test
the no-huge logic with a execution environment conditional
no_huge_compat to indicate that it is passed as a compatibility flag,
not as a requirement for a test itself.
Note that checkpatch is complaining about argvX arrays not being static
const. This patch doesn't change that to not add confusion.
Signed-off-by: Stanislaw Kardach
Fixes: b5d878e6db56 ("test: fix EAL flags autotest on FreeBSD")
Cc: sta...@dpdk.org
---
app/test/test_eal_flags.c | 33 ++---
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/app/test/test_eal_flags.c b/app/test/test_eal_flags.c
index 462dc6384..cfc54684a 100644
--- a/app/test/test_eal_flags.c
+++ b/app/test/test_eal_flags.c
@@ -29,6 +29,17 @@
#define mp_flag "--proc-type=secondary"
#define no_hpet "--no-hpet"
#define no_huge "--no-huge"
+/* FreeBSD does not support running multiple primary processes, hence for tests
+ * requiring no-shconf, no-huge is also required.
+ * On Linux on the other hand no-huge is not needed so don't pass it as it
+ * would break cases when IOMMU is not able to provide IOVA translation
+ * (rte_eal_iova_mode() == RTE_IOVA_PA).
+ */
+#ifdef RTE_EXEC_ENV_LINUX
+#define no_huge_compat ""
+#else
+#define no_huge_compat no_huge
+#endif
#define no_shconf "--no-shconf"
#define allow "--allow"
#define vdev "--vdev"
@@ -354,17 +365,17 @@ test_invalid_vdev_flag(void)
#endif
/* Test with invalid vdev option */
- const char *vdevinval[] = {prgname, prefix, no_huge,
+ const char *vdevinval[] = {prgname, prefix, no_huge_compat,
vdev, "eth_dummy"};
/* Test with valid vdev option */
- const char *vdevval1[] = {prgname, prefix, no_huge,
+ const char *vdevval1[] = {prgname, prefix, no_huge_compat,
vdev, "net_ring0"};
- const char *vdevval2[] = {prgname, prefix, no_huge,
+ const char *vdevval2[] = {prgname, prefix, no_huge_compat,
vdev, "net_ring0,args=test"};
- const char *vdevval3[] = {prgname, prefix, no_huge,
+ const char *vdevval3[] = {prgname, prefix, no_huge_compat,
vdev, "net_ring0,nodeaction=r1:0:CREATE"};
if (launch_proc(vdevinval) == 0) {
@@ -674,19 +685,19 @@ test_invalid_n_flag(void)
#endif
/* -n flag but no value */
- const char *argv1[] = { prgname, prefix, no_huge, no_shconf,
+ const char *argv1[] = { prgname, prefix, no_huge_compat, no_shconf,
"-n"};
/* bad numeric value */
- const char *argv2[] = { prgname, prefix, no_huge, no_shconf,
+ const char *argv2[] = { prgname, prefix, no_huge_compat, no_shconf,
"-n", "e" };
/* zero is invalid */
- const char *argv3[] = { prgname, prefix, no_huge, no_shconf,
+ const char *argv3[] = { prgname, prefix, no_huge_compat, no_shconf,
"-n", "0" };
/* sanity test - check with good value */
- const char *argv4[] = { prgname, prefix, no_huge, no_shconf,
+ const char *argv4[] = { prgname, prefix, no_huge_compat, no_shconf,
"-n", "2" };
/* sanity test - check with no -n flag */
- const char *argv5[] = { prgname, prefix, no_huge, no_shconf};
+ const char *argv5[] = { prgname, prefix, no_huge_compat, no_shconf};
if (launch_proc(argv1) == 0
|| launch_proc(argv2) == 0
@@ -878,7 +889,7 @@ test_misc_flags(void)
const char *argv5[] = {prgname, prefix, mp_flag, "--syslog", "error"};
/* With no-sh-conf, also use no-huge to ensure this test runs on BSD */
const char *argv6[] = {prgname, "-m", DEFAULT_MEM_SIZE,
- no_shconf, nosh_prefix, no_huge};
+ no_shconf, nosh_prefix, no_huge_compat};
/* With --huge-dir */
const char *argv7[] = {prgname, "-m", DEFAULT_MEM_SIZE,
@@ -920,7 +931,7 @@ test_misc_flags(void)
/* With process type as auto-detect with no-shconf */
const char * const argv17[] = {prgname, "--proc-type=auto",
- no_shconf, nosh_prefix, no_huge};
+ no_shconf, nosh_prefix, no_huge_compat};
/* With process type as --create-uio-dev flag */
const char * const argv18[] = {prgname, "--file-prefix=uiodev",
--
2.27.0
[dpdk-dev] [PATCH 3/3] test: fix the -n unit test description
When -n argument became optional, the test logic was fixed (by
1e0b51fd4) but the comment indicating why --no-huge and --no-shconf are
used was not changed.
Today those flags are used for compatibility with FreeBSD (see
b5d878e6d), so change the comment to reflect that.
Signed-off-by: Stanislaw Kardach
Fixes: b5d878e6db56 ("test: fix EAL flags autotest on FreeBSD")
Cc: sta...@dpdk.org
---
app/test/test_eal_flags.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/app/test/test_eal_flags.c b/app/test/test_eal_flags.c
index cfc54684a..894e2e90c 100644
--- a/app/test/test_eal_flags.c
+++ b/app/test/test_eal_flags.c
@@ -666,8 +666,8 @@ test_main_lcore_flag(void)
/*
* Test that the app doesn't run with invalid -n flag option.
* Final test ensures it does run with valid options as sanity check
- * Since -n is not compulsory for MP, we instead use --no-huge and --no-shconf
- * flags.
+ * For compatibility with BSD use --no-huge and --no-shconf flags as we need to
+ * run a primary process.
*/
static int
test_invalid_n_flag(void)
--
2.27.0
[PATCH 00/11] Introduce support for RISC-V architecture
This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Commits 1-2 fix small issues which are encountered if a given platform does not support any vector operations (which is the case with U740). Commit 3 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 4-7 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 8 adds RISC-V specific cpuflags test. Commit 9 works around a bug in the current GCC in test_ring compiled with -O0 or -Og. Commit 10 adds RISC-V testing to test-meson-builds.sh automatically iterating over cross-compile config files (currently present for generic rv64gc and SiFive U740). Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM measurements. This is an extraneous commit which is not directly needed for RISC-V support but was noticed when we have started gathering test results. If needed, I can submit it separately. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach NOTE: This work was sponsored by StarFive and SiFive which is signified by "Sponsored-by:" sign-offs in each commit message. After discussing it with Thomas Monjalon it seemed a better choice than "Suggested-by" which does not fully convey the nature of involvement. However it makes Linux checkpatch unhappy so I'm not sure if I shouldn't change the sign-offs. NOTE2: I have added maintainers for each commit based on MAINTAINERS file. However some modules (l3fwd, net/tap and cpuflags unit tests) do not have any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as if it was a commit adding new files. Michal Mazurek (3): lpm: add a scalar version of lookupx4 function eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (8): examples/l3fwd: fix scalar LPM compilation net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation test/ring: disable problematic tests for RISC-V devtools: add RISC-V to test-meson-builds.sh test/hash: report non HTM numbers for single r/w MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 ++ app/test/test_hash_readwrite.c| 8 +- app/test/test_ring.c | 8 + app/test/test_xmmt_ops.h | 16 ++ config/meson.build| 2 + config/riscv/meson.build | 148 ++ config/riscv/riscv64_linux_gcc| 17 ++ config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++ devtools/test-meson-builds.sh | 6 + doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++ doc/guides/linux_gsg/index.rst| 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini| 1 + doc/guides/rel_notes/release_22_07.rst| 29 drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c| 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_fib.c| 2 + examples/l3fwd/l3fwd_lpm.c| 2 +- lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h| 52 ++ lib/eal/riscv/include/rte_byteorder.h | 44 ++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++ lib/eal/riscv/include/rte_cycles.h| 103 lib/eal/riscv/include/rte_io.h| 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h| 63 lib/eal/riscv/include/rte_pause.h | 31 lib/eal/riscv/include/rte_pflock.h| 17 ++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++ lib/eal/riscv/include/rte_rwlock.h| 44 ++ lib/eal/riscv/include/rte_spinlock.h
[PATCH 01/11] lpm: add a scalar version of lookupx4 function
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
doc/guides/rel_notes/release_22_07.rst | 5 +
lib/lpm/meson.build| 1 +
lib/lpm/rte_lpm.h | 4 +-
lib/lpm/rte_lpm_scalar.h | 122 +
4 files changed, 131 insertions(+), 1 deletion(-)
create mode 100644 lib/lpm/rte_lpm_scalar.h
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index 88d6e96cc1..067118174b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -65,6 +65,11 @@ New Features
* Added support for promiscuous mode on Windows.
* Added support for MTU on Windows.
+* **Added scalar version of the LPM library.**
+
+ * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
Removed Items
-
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
indirect_headers += files(
'rte_lpm_altivec.h',
'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..b5db6a353a 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
#endif
#ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..991b94e687
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ rte_xmm_t i24;
+ rte_xmm_t i8;
+ uint32_t tbl[4];
+ uint64_t pt, pt2;
+ const uint32_t *ptbl;
+
+ const rte_xmm_t mask8 = {
+ .u32 = {UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX}};
+
+ /*
+* RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
+* as one 64-bit value (0x03000300).
+*/
+ const uint64_t mask_xv =
+ ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
+ (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
+
+ /*
+* RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
+* as one 64-bit value (0x01000100).
+*/
+ const uint64_t mask_v =
+ ((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
+ (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
+
+ /* get 4 indexes for tbl24[]. */
+ i24.x = ip;
+ i24.u32[0] >>= CHAR_BIT;
+ i24.u32[1] >>= CHAR_BIT;
+ i24.u32[2] >>= CHAR_BIT;
+ i24.u32[3] >>= CHAR_BIT;
+
+ /* extract values from tbl24[] */
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[0]];
+ tbl[0] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[1]];
+ tbl[1] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[2]];
+ tbl[2] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[3]];
+ tbl[3] = *ptbl;
+
+ /* get 4 indexes for tbl8[]. */
+ i8.x = ip;
+ i8.u64[0] &= mask8.u64[0];
+ i8.u64[1] &= mask8.u64[1];
+
+ pt = (uint64_t)tbl[0] |
+ (uint64_t)tbl[1] << 32;
+ pt2 = (uint64_t)tbl[2] |
+ (uint64_t)tbl[3] << 32;
+
+ /* search successfully finished for all 4 IP addresses. */
+ if (likely((pt & mask_xv) == mask_v) &&
+ likely((pt2 & mask_xv) == mask_v)) {
+ *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
+ *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
+ return;
+ }
+
+ if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+ i8.u32[0] = i8.u32[0] +
+
[PATCH 02/11] examples/l3fwd: fix scalar LPM compilation
The lpm_process_event_pkt() can either process a packet using an
architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
path or a scalar one. The choice is however done using an ifdef
pre-processor macro. Because of that the scalar version was apparently
not widely excersized/compiled.
Due to some copy/paste errors, the scalar logic in
lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
should be returned after refactoring of the LPM logic in the l3fwd
example.
Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
Cc: pbhagavat...@marvell.com
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
examples/l3fwd/l3fwd_lpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c
index bec22c44cd..6e1defbf7f 100644
--- a/examples/l3fwd/l3fwd_lpm.c
+++ b/examples/l3fwd/l3fwd_lpm.c
@@ -248,7 +248,7 @@ lpm_process_event_pkt(const struct lcore_conf *lconf,
struct rte_mbuf *mbuf)
if (is_valid_ipv4_pkt(ipv4_hdr, mbuf->pkt_len)
< 0) {
mbuf->port = BAD_PORT;
- continue;
+ return mbuf->port;
}
/* Update time to live and header checksum */
--(ipv4_hdr->time_to_live);
--
2.30.2
[PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V
Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++--
drivers/net/ixgbe/meson.build | 6 --
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini
b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows = Y
ARMv8= Y
x86-32 = Y
x86-64 = Y
+rv64 = Y
[rte_flow items]
eth = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.30.2
[PATCH 03/11] eal: add initial support for RISC-V architecture
From: Michal Mazurek Add all necessary elements for DPDK to compile and run EAL on SiFive Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc) core complex. This includes: - EAL library implementation for rv64imafdc ISA. - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define is added for architecture identification. - xmm_t structure operation stubs as there is no vector support in the U74 core. Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain. Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime (default) and unstable high-resolution using rdcycle. User can override the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of both DPDK and the application. The reasoning for this is as follows. The RISC-V ISA mandates that clock read by rdtime has to be of constant period and synchronized between all hardware threads within 1 tick (chapter 10.1 in version 20191213 of RISC-V spec). However this clock may not be of high-enough frequency for dataplane uses. I.e. on HiFive Unmatched (FU740) it is 1MHz. There is a high-resolution alternative in form of rdcycle which is clocked at the core clock frequency. The drawbacks are that it may be disabled during sleep (WFI) and its frequency might change due to DVFS. The platform is currently marked as linux-only because rte_cycles implementation uses the timebase-frequency device-tree node read through the proc file system. Such approach was chosen because Linux kernel depends on the presence of this device-tree node. The compilation of following modules has been disabled by this commit and will be re-enabled in later commits as fixes are introduced: net/ixgbe, net/memif, net/tap, example/l3fwd. Known checkpatch errors/warnings: - ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline assembly declarations. - vector_size compiler attribute used in rte_vect.h directly. - rte_*mb() used directly in rte_atomic.h to reduce code duplication. - __atomic_thread_fence() used to implement rte_atomic_thread_fence(). Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- MAINTAINERS | 6 + app/test/test_xmmt_ops.h | 16 ++ config/meson.build| 2 + config/riscv/meson.build | 143 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++ doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++ doc/guides/linux_gsg/index.rst| 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/rel_notes/release_22_07.rst| 23 +++ drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/meson.build | 6 + drivers/net/memif/meson.build | 5 + drivers/net/tap/meson.build | 5 + examples/l3fwd/meson.build| 6 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h| 52 +++ lib/eal/riscv/include/rte_byteorder.h | 44 ++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++ lib/eal/riscv/include/rte_cycles.h| 103 + lib/eal/riscv/include/rte_io.h| 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h| 63 lib/eal/riscv/include/rte_pause.h | 31 lib/eal/riscv/include/rte_pflock.h| 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++ lib/eal/riscv/include/rte_rwlock.h| 44 ++ lib/eal/riscv/include/rte_spinlock.h | 67 lib/eal/riscv/include/rte_ticketlock.h| 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 +++ lib/eal/riscv/rte_cycles.c| 77 ++ lib/eal/riscv/rte_hypervisor.c| 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 +++ meson.build | 2 + 39 files changed, 1354 insertions(+), 1 deletion(-) create mode 100644 config/riscv/meson.build create mode 100644 config/riscv/riscv64_linux_gcc create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst create mode 100644 lib/eal/riscv/include/meson.build create mode 100644 lib/eal/riscv/include/rte_atomic.h create mode 100644 lib/eal/riscv/include/rte_byteorder.h create mode 100644 lib/eal/ris
[PATCH 05/11] net/memif: set memfd syscall ID on RISC-V
Define the missing __NR_memfd_create syscall id to enable the memif PMD. Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 - drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.30.2
[PATCH 06/11] net/tap: set BPF syscall ID for RISC-V
Define the missing __NR_bpf syscall id to enable the tap PMD.
Signed-off-by: Stanislaw Kardach
---
drivers/net/tap/meson.build | 5 -
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
build = false
reason = 'only supported on Linux'
endif
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
sources = files(
'rte_eth_tap.c',
'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
# define __NR_bpf 351
# elif defined(__powerpc__)
# define __NR_bpf 361
+# elif defined(__riscv)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.30.2
[PATCH 07/11] examples/l3fwd: enable RISC-V operation
Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
examples/l3fwd/l3fwd_em.c | 8
examples/l3fwd/l3fwd_fib.c | 2 ++
examples/l3fwd/meson.build | 6 --
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
return vec_and(data, mask);
}
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
#include "l3fwd_neon.h"
#elif defined RTE_ARCH_PPC_64
#include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
#endif
#include "l3fwd_event.h"
#include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if dpdk_conf.has('RTE_ARCH_RISCV')
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.30.2
[PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag
From: Michal Mazurek
Add checks for all flag values defined in the RISC-V misa CSR register.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
app/test/test_cpuflags.c | 81
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
[PATCH 09/11] test/ring: disable problematic tests for RISC-V
When compiling for RISC-V in debug mode the large amount of inlining in
test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
leads to large loop bodies. This causes 'goto' and 'for' loop
PC-relative jumps generated by the compiler to go beyond the architecture
limitation of +/-1MB offset (the 'j ' instruction). This
instruction should not be generated by the compiler since C language does
not limit the maximum distance for 'goto' or 'for' loop jumps.
This only happens in the unit test for ring which tries to perform long
loops with ring enqueue/dequeue and it seems to be caused by excessive
__rte_always_inline usage. ring perf test compiles just fine under
debug.
To work around this, disable the offending tests in debug mode.
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
app/test/test_ring.c | 8
config/riscv/meson.build | 5 +
doc/guides/rel_notes/release_22_07.rst | 3 ++-
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index bde33ab4a1..7d809c147b 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx)
return -1;
}
+#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
/*
* Test default, single element, bulk and burst APIs
*/
@@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void)
rte_ring_free(exact_sz_r);
return -1;
}
+#endif
static int
test_ring(void)
@@ -1200,12 +1202,18 @@ test_ring(void)
if (test_ring_negative_tests() < 0)
goto test_fail;
+/* Disable the following tests on RISC-V in debug mode. This is a work-around
+ * GCC bug for RISC-V which fails to generate proper jumps for loops with large
+ * bodies.
+ */
+#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
/* Some basic operations */
if (test_ring_basic_ex() < 0)
goto test_fail;
if (test_ring_with_exact_size() < 0)
goto test_fail;
+#endif
/* Burst and bulk operations with sp/sc, mp/mc and default.
* The test cases are split into smaller test cases to
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 0c16c31fc2..50d0b513bf 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -141,3 +141,8 @@ foreach flag: dpdk_flags
endforeach
message('Using machine args: @0@'.format(machine_args))
+# Enable work-around for ring unit tests in debug mode which fail to link
+# properly due to bad code generation by GCC.
+if get_option('optimization') == '0' or get_option('optimization') == 'g'
+add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS', language: 'c')
+endif
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index 453591e568..4d64b68dfd 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -76,7 +76,8 @@ New Features
* Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
seemingly invalid loop and goto jump code generation by GCC in
``test_ring.c`` where extensive inlining increases the code size beyond the
-capability of the generated instruction (JAL: +/-1MB PC-relative).
+capability of the generated instruction (JAL: +/-1MB PC-relative). The
+workaround is to disable ``test_ring_basic_ex()`` and
``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``.
* **Updated Intel iavf driver.**
--
2.30.2
[PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh
Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Signed-off-by: Stanislaw Kardach Sponsored-by: Frank Zhao Sponsored-by: Sam Grove --- devtools/test-meson-builds.sh | 6 ++ 1 file changed, 6 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..12513e9d7f 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configurations +for f in $srcdir/config/riscv/riscv* ; do + targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2) + build $targetdir $f ABI $use_shared +done + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc -- 2.30.2
[PATCH 11/11] test/hash: report non HTM numbers for single r/w
In hash_readwrite_perf_autotest a single read and write operation is
benchmarked for both HTM and non HTM cases. However the result summary
only shows the HTM value. Therefore add the non HTM value for
completeness.
Fixes: 0eb3726ebcf1 ("test/hash: add test for read/write concurrency")
Cc: yipeng1.w...@intel.com
Signed-off-by: Stanislaw Kardach
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
---
app/test/test_hash_readwrite.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/app/test/test_hash_readwrite.c b/app/test/test_hash_readwrite.c
index 9b192f2b5e..6373e62d33 100644
--- a/app/test/test_hash_readwrite.c
+++ b/app/test/test_hash_readwrite.c
@@ -664,8 +664,12 @@ test_hash_rw_perf_main(void)
printf("Results summary:\n");
printf("\n");
- printf("single read: %u\n", htm_results.single_read);
- printf("single write: %u\n", htm_results.single_write);
+ printf("HTM:\n");
+ printf(" single read: %u\n", htm_results.single_read);
+ printf(" single write: %u\n", htm_results.single_write);
+ printf("non HTM:\n");
+ printf(" single read: %u\n", non_htm_results.single_read);
+ printf(" single write: %u\n", non_htm_results.single_write);
for (i = 0; i < NUM_TEST; i++) {
printf("+++ core_cnt: %u +++\n", core_cnt[i]);
printf("HTM:\n");
--
2.30.2
[PATCH 1/1] test/hash: report non HTM numbers for single r/w
In hash_readwrite_perf_autotest a single read and write operation is
benchmarked for both HTM and non HTM cases. However the result summary
only shows the HTM value. Therefore add the non HTM value for
completeness.
Fixes: 0eb3726ebcf1 ("test/hash: add test for read/write concurrency")
Signed-off-by: Stanislaw Kardach
---
app/test/test_hash_readwrite.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/app/test/test_hash_readwrite.c b/app/test/test_hash_readwrite.c
index 9b192f2b5e..6373e62d33 100644
--- a/app/test/test_hash_readwrite.c
+++ b/app/test/test_hash_readwrite.c
@@ -664,8 +664,12 @@ test_hash_rw_perf_main(void)
printf("Results summary:\n");
printf("\n");
- printf("single read: %u\n", htm_results.single_read);
- printf("single write: %u\n", htm_results.single_write);
+ printf("HTM:\n");
+ printf(" single read: %u\n", htm_results.single_read);
+ printf(" single write: %u\n", htm_results.single_write);
+ printf("non HTM:\n");
+ printf(" single read: %u\n", non_htm_results.single_read);
+ printf(" single write: %u\n", non_htm_results.single_write);
for (i = 0; i < NUM_TEST; i++) {
printf("+++ core_cnt: %u +++\n", core_cnt[i]);
printf("HTM:\n");
--
2.30.2
[PATCH 1/1] test/ring: remove excessive inlining
Forcing inlining in test_ring_enqueue and test_ring_dequeue can cause
the compiled code to grow extensively when compiled with no optimization
(-O0 or -Og). This is default in the meson's debug configuration. This
can collide with compiler bugs and cause issues during linking of unit
tests where the api_type or esize are non-const variables causing
inlining cascade. In perf tests this is not the case in perf-tests as
esize and api_type are const values.
One such case was discovered when porting DPDK to RISC-V. GCC 11.2 (and
no fix still in 12.1) is generating a short relative jump instruction
(J ) for goto and for loops. When loop body grows extensively in
ring test, the target offset goes beyond supported offfset of +/- 1MB
from PC. This is an obvious bug in the GCC as RISC-V has a
two-instruction construct to jump to any absolute address (AUIPC+JALR).
However there is no reason to force inlining as the test code works
perfectly fine without it.
Fixes: a9fe152363 test/ring: add custom element size functional tests
Signed-off-by: Stanislaw Kardach
---
app/test/test_ring.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/app/test/test_ring.h b/app/test/test_ring.h
index c8bfec8399..45c263f3ff 100644
--- a/app/test/test_ring.h
+++ b/app/test/test_ring.h
@@ -97,7 +97,7 @@ test_ring_copy_from(struct rte_ring_zc_data *zcd, void *dst,
int esize,
}
}
-static __rte_always_inline unsigned int
+static inline unsigned int
test_ring_enqueue(struct rte_ring *r, void **obj, int esize, unsigned int n,
unsigned int api_type)
{
@@ -158,7 +158,7 @@ test_ring_enqueue(struct rte_ring *r, void **obj, int
esize, unsigned int n,
}
}
-static __rte_always_inline unsigned int
+static inline unsigned int
test_ring_dequeue(struct rte_ring *r, void **obj, int esize, unsigned int n,
unsigned int api_type)
{
@@ -222,7 +222,7 @@ test_ring_dequeue(struct rte_ring *r, void **obj, int
esize, unsigned int n,
/* This function is placed here as it is required for both
* performance and functional tests.
*/
-static __rte_always_inline void *
+static inline void *
test_ring_calloc(unsigned int rsize, int esize)
{
unsigned int sz;
--
2.30.2
[PATCH 1/1] lpm: add a scalar version of lookupx4 function
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with a basic level of LPM support.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
doc/guides/rel_notes/release_22_07.rst | 5 +
lib/lpm/meson.build| 1 +
lib/lpm/rte_lpm.h | 4 +-
lib/lpm/rte_lpm_scalar.h | 122 +
4 files changed, 131 insertions(+), 1 deletion(-)
create mode 100644 lib/lpm/rte_lpm_scalar.h
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index 4ae91dd94d..73e8d632f2 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -70,6 +70,11 @@ New Features
* Added AH mode support in lookaside protocol (IPsec) for CN9K & CN10K.
* Added AES-GMAC support in lookaside protocol (IPsec) for CN9K & CN10K.
+* **Added scalar version of the LPM library.**
+
+ * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
Removed Items
-
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
indirect_headers += files(
'rte_lpm_altivec.h',
'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..b5db6a353a 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
#endif
#ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..991b94e687
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ rte_xmm_t i24;
+ rte_xmm_t i8;
+ uint32_t tbl[4];
+ uint64_t pt, pt2;
+ const uint32_t *ptbl;
+
+ const rte_xmm_t mask8 = {
+ .u32 = {UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX}};
+
+ /*
+* RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
+* as one 64-bit value (0x03000300).
+*/
+ const uint64_t mask_xv =
+ ((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
+ (uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
+
+ /*
+* RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
+* as one 64-bit value (0x01000100).
+*/
+ const uint64_t mask_v =
+ ((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
+ (uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
+
+ /* get 4 indexes for tbl24[]. */
+ i24.x = ip;
+ i24.u32[0] >>= CHAR_BIT;
+ i24.u32[1] >>= CHAR_BIT;
+ i24.u32[2] >>= CHAR_BIT;
+ i24.u32[3] >>= CHAR_BIT;
+
+ /* extract values from tbl24[] */
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[0]];
+ tbl[0] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[1]];
+ tbl[1] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[2]];
+ tbl[2] = *ptbl;
+ ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[3]];
+ tbl[3] = *ptbl;
+
+ /* get 4 indexes for tbl8[]. */
+ i8.x = ip;
+ i8.u64[0] &= mask8.u64[0];
+ i8.u64[1] &= mask8.u64[1];
+
+ pt = (uint64_t)tbl[0] |
+ (uint64_t)tbl[1] << 32;
+ pt2 = (uint64_t)tbl[2] |
+ (uint64_t)tbl[3] << 32;
+
+ /* search successfully finished for all 4 IP addresses. */
+ if (likely((pt & mask_xv) == mask_v) &&
+ likely((pt2 & mask_xv) == mask_v)) {
+ *(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
+ *(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
+ return;
+ }
+
+ if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+ RTE_LP
[PATCH 1/1] examples/l3fwd: fix scalar LPM compilation
The lpm_process_event_pkt() can either process a packet using an
architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
path or a scalar one. The choice is however done using an ifdef
pre-processor macro. Because of that the scalar version was apparently
not widely excersized/compiled.
Due to some copy/paste errors, the scalar logic in
lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
should be returned after refactoring of the LPM logic in the l3fwd
example.
Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
Cc: pbhagavat...@marvell.com
Signed-off-by: Stanislaw Kardach
---
examples/l3fwd/l3fwd_lpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c
index bec22c44cd..6e1defbf7f 100644
--- a/examples/l3fwd/l3fwd_lpm.c
+++ b/examples/l3fwd/l3fwd_lpm.c
@@ -248,7 +248,7 @@ lpm_process_event_pkt(const struct lcore_conf *lconf,
struct rte_mbuf *mbuf)
if (is_valid_ipv4_pkt(ipv4_hdr, mbuf->pkt_len)
< 0) {
mbuf->port = BAD_PORT;
- continue;
+ return mbuf->port;
}
/* Update time to live and header checksum */
--(ipv4_hdr->time_to_live);
--
2.30.2
[PATCH v2 0/8] Introduce support for RISC-V architecture
This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job --- NOTE: I have added maintainers for each commit based on MAINTAINERS file. However some modules (l3fwd, net/tap and cpuflags unit tests) do not have any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as if it was a commit adding new files. .ci/linux-build.sh| 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 ++ app/test/test_xmmt_ops.h | 16 ++ config/meson.build| 2 + config/riscv/meson.build | 143 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++ devtools/test-meson-builds.sh | 6 + doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++ doc/guides/linux_gsg/index.rst| 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini| 1 + doc/guides/rel_notes/release_22_07.rst| 8 + drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c| 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_fib.c| 2 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h| 52 +++ lib/eal/riscv/include/rte_byteorder.h | 44 ++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++ lib/eal/riscv/include/rte_cycles.h| 105 + lib/eal/riscv/include/rte_io.h| 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h| 63 lib/eal/riscv/include/rte_pause.h | 31 lib/eal/riscv/include/rte_pflock.h| 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++ lib/eal/riscv/include/rte_rwlock.h| 44 ++ lib/eal/riscv/include/rte_spinlock.h | 67 lib/eal/riscv/include/rte_ticketlock.h| 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 +++ lib/eal/riscv/rte_cycles.c| 77 ++ lib/eal/riscv/rte_hypervisor.c| 13 +
[PATCH v2 1/8] eal: add initial support for RISC-V architecture
From: Michal Mazurek
Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.
This includes:
- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
U74 core.
Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.
Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI) and its frequency might change due to DVFS.
The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.
The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.
The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Known checkpatch errors/warnings:
- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
Depends-on: series-22867 ("test/ring: remove excessive inlining")
Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
---
MAINTAINERS | 6 +
app/test/test_xmmt_ops.h | 16 ++
config/meson.build| 2 +
config/riscv/meson.build | 143 ++
config/riscv/riscv64_linux_gcc| 17 +++
config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++
doc/guides/contributing/design.rst| 2 +-
.../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++
doc/guides/linux_gsg/index.rst| 1 +
doc/guides/nics/features.rst | 5 +
doc/guides/nics/features/default.ini | 1 +
doc/guides/rel_notes/release_22_07.rst| 8 +
drivers/net/i40e/meson.build | 6 +
drivers/net/ixgbe/meson.build | 6 +
drivers/net/memif/meson.build | 5 +
drivers/net/tap/meson.build | 5 +
examples/l3fwd/meson.build| 6 +
lib/eal/riscv/include/meson.build | 23 +++
lib/eal/riscv/include/rte_atomic.h| 52 +++
lib/eal/riscv/include/rte_byteorder.h | 44 ++
lib/eal/riscv/include/rte_cpuflags.h | 55 +++
lib/eal/riscv/include/rte_cycles.h| 105 +
lib/eal/riscv/include/rte_io.h| 21 +++
lib/eal/riscv/include/rte_mcslock.h | 18 +++
lib/eal/riscv/include/rte_memcpy.h| 63
lib/eal/riscv/include/rte_pause.h | 31
lib/eal/riscv/include/rte_pflock.h| 17 +++
lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++
lib/eal/riscv/include/rte_prefetch.h | 50 ++
lib/eal/riscv/include/rte_rwlock.h| 44 ++
lib/eal/riscv/include/rte_spinlock.h | 67
lib/eal/riscv/include/rte_ticketlock.h| 21 +++
lib/eal/riscv/include/rte_vect.h | 55 +++
lib/eal/riscv/meson.build | 11 ++
lib/eal/riscv/rte_cpuflags.c | 122 +++
lib/eal/riscv/rte_cycles.c| 77 ++
lib/eal/riscv/rte_hypervisor.c| 13 ++
lib/eal/riscv/rte_power_intrinsics.c | 56 +++
meson.build | 2 +
39 files changed, 1341 insertions(+), 1 deletion(-)
cre
[PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V
Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++--
drivers/net/ixgbe/meson.build | 6 --
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini
b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows = Y
ARMv8= Y
x86-32 = Y
x86-64 = Y
+rv64 = Y
[rte_flow items]
eth = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.30.2
[PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V
Define the missing __NR_memfd_create syscall id to enable the memif PMD. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 - drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.30.2
[PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V
Define the missing __NR_bpf syscall id to enable the tap PMD.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
drivers/net/tap/meson.build | 5 -
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
build = false
reason = 'only supported on Linux'
endif
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
sources = files(
'rte_eth_tap.c',
'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
# define __NR_bpf 351
# elif defined(__powerpc__)
# define __NR_bpf 361
+# elif defined(__riscv)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.30.2
[PATCH v2 5/8] examples/l3fwd: enable RISC-V operation
Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
examples/l3fwd/l3fwd_em.c | 8
examples/l3fwd/l3fwd_fib.c | 2 ++
examples/l3fwd/meson.build | 6 --
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
return vec_and(data, mask);
}
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
#include "l3fwd_neon.h"
#elif defined RTE_ARCH_PPC_64
#include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
#endif
#include "l3fwd_event.h"
#include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if dpdk_conf.has('RTE_ARCH_RISCV')
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.30.2
[PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag
From: Michal Mazurek
Add checks for all flag values defined in the RISC-V misa CSR register.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
app/test/test_cpuflags.c | 81
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
[PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh
Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- devtools/test-meson-builds.sh | 6 ++ 1 file changed, 6 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..12513e9d7f 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configurations +for f in $srcdir/config/riscv/riscv* ; do + targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2) + build $targetdir $f ABI $use_shared +done + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc -- 2.30.2
[PATCH v2 8/8] ci: add RISCV64 cross compilation job
Checks cross-compilation using Ubuntu 20.04 x86.
Signed-off-by: David Marchand
Signed-off-by: Stanislaw Kardach
---
.ci/linux-build.sh | 4
.github/workflows/build.yml | 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 877243c9c8..aa5e9ec114 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
fi
+if [ "$RISCV64" = "true" ]; then
+cross_file=config/riscv/riscv64_linux_gcc
+fi
+
if [ -n "$cross_file" ]; then
OPTS="$OPTS --cross-file $cross_file"
fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e2f94d786b..ca468da8fa 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,6 +25,7 @@ jobs:
MINI: ${{ matrix.config.mini != '' }}
PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
REF_GIT_TAG: v22.03
+ RISCV64: ${{ matrix.config.cross == 'riscv64' }}
RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
strategy:
@@ -73,6 +74,10 @@ jobs:
compiler: gcc
library: shared
cross: ppc64le
+ - os: ubuntu-20.04
+compiler: gcc
+library: shared
+cross: riscv64
steps:
- name: Checkout sources
@@ -131,8 +136,12 @@ jobs:
if: env.PPC64LE == 'true'
run: sudo apt install -y gcc-powerpc64le-linux-gnu
libc6-dev-ppc64el-cross
pkg-config-powerpc-linux-gnu
+- name: Install riscv64 cross compiling packages
+ if: env.RISCV64 == 'true'
+ run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+pkg-config-riscv64-linux-gnu
- name: Install test tools packages
- if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS ==
'true'
+ if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 !=
'true' || env.RUN_TESTS == 'true'
run: sudo apt install -y gdb
- name: Install doc generation packages
if: env.BUILD_DOCS == 'true'
--
2.30.2
[PATCH v3 0/8] Introduce support for RISC-V architecture
This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v3: - Limit test-meson-builds.sh testing to a generic rv64gc configuration. Previous version was missing this change by mistake. v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job --- NOTE: I have added maintainers for each commit based on MAINTAINERS file. However some modules (l3fwd, net/tap and cpuflags unit tests) do not have any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as if it was a commit adding new files. .ci/linux-build.sh| 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 ++ app/test/test_xmmt_ops.h | 16 ++ config/meson.build| 2 + config/riscv/meson.build | 143 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++ devtools/test-meson-builds.sh | 4 + doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++ doc/guides/linux_gsg/index.rst| 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini| 1 + doc/guides/rel_notes/release_22_07.rst| 8 + drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c| 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_fib.c| 2 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h| 52 +++ lib/eal/riscv/include/rte_byteorder.h | 44 ++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++ lib/eal/riscv/include/rte_cycles.h| 105 + lib/eal/riscv/include/rte_io.h| 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h| 63 lib/eal/riscv/include/rte_pause.h | 31 lib/eal/riscv/include/rte_pflock.h| 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++ lib/eal/riscv/include/rte_rwlock.h| 44 ++ lib/eal/riscv/include/rte_spinlock.h | 67 lib/eal/riscv/include/rte_ticketlock.h| 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c
[PATCH v3 1/8] eal: add initial support for RISC-V architecture
From: Michal Mazurek
Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.
This includes:
- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
U74 core.
Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.
Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI) and its frequency might change due to DVFS.
The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.
The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.
The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Known checkpatch errors/warnings:
- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
Depends-on: series-22867 ("test/ring: remove excessive inlining")
Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
---
MAINTAINERS | 6 +
app/test/test_xmmt_ops.h | 16 ++
config/meson.build| 2 +
config/riscv/meson.build | 143 ++
config/riscv/riscv64_linux_gcc| 17 +++
config/riscv/riscv64_sifive_u740_linux_gcc| 19 +++
doc/guides/contributing/design.rst| 2 +-
.../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++
doc/guides/linux_gsg/index.rst| 1 +
doc/guides/nics/features.rst | 5 +
doc/guides/nics/features/default.ini | 1 +
doc/guides/rel_notes/release_22_07.rst| 8 +
drivers/net/i40e/meson.build | 6 +
drivers/net/ixgbe/meson.build | 6 +
drivers/net/memif/meson.build | 5 +
drivers/net/tap/meson.build | 5 +
examples/l3fwd/meson.build| 6 +
lib/eal/riscv/include/meson.build | 23 +++
lib/eal/riscv/include/rte_atomic.h| 52 +++
lib/eal/riscv/include/rte_byteorder.h | 44 ++
lib/eal/riscv/include/rte_cpuflags.h | 55 +++
lib/eal/riscv/include/rte_cycles.h| 105 +
lib/eal/riscv/include/rte_io.h| 21 +++
lib/eal/riscv/include/rte_mcslock.h | 18 +++
lib/eal/riscv/include/rte_memcpy.h| 63
lib/eal/riscv/include/rte_pause.h | 31
lib/eal/riscv/include/rte_pflock.h| 17 +++
lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++
lib/eal/riscv/include/rte_prefetch.h | 50 ++
lib/eal/riscv/include/rte_rwlock.h| 44 ++
lib/eal/riscv/include/rte_spinlock.h | 67
lib/eal/riscv/include/rte_ticketlock.h| 21 +++
lib/eal/riscv/include/rte_vect.h | 55 +++
lib/eal/riscv/meson.build | 11 ++
lib/eal/riscv/rte_cpuflags.c | 122 +++
lib/eal/riscv/rte_cycles.c| 77 ++
lib/eal/riscv/rte_hypervisor.c| 13 ++
lib/eal/riscv/rte_power_intrinsics.c | 56 +++
meson.build | 2 +
39 files changed, 1341 insertions(+), 1 deletion(-)
cre
[PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V
Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++--
drivers/net/ixgbe/meson.build | 6 --
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini
b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows = Y
ARMv8= Y
x86-32 = Y
x86-64 = Y
+rv64 = Y
[rte_flow items]
eth = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.30.2
[PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V
Define the missing __NR_memfd_create syscall id to enable the memif PMD. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 - drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.30.2
[PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V
Define the missing __NR_bpf syscall id to enable the tap PMD.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
drivers/net/tap/meson.build | 5 -
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
build = false
reason = 'only supported on Linux'
endif
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
sources = files(
'rte_eth_tap.c',
'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
# define __NR_bpf 351
# elif defined(__powerpc__)
# define __NR_bpf 361
+# elif defined(__riscv)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.30.2
[PATCH v3 5/8] examples/l3fwd: enable RISC-V operation
Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
examples/l3fwd/l3fwd_em.c | 8
examples/l3fwd/l3fwd_fib.c | 2 ++
examples/l3fwd/meson.build | 6 --
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
return vec_and(data, mask);
}
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
#include "l3fwd_neon.h"
#elif defined RTE_ARCH_PPC_64
#include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
#endif
#include "l3fwd_event.h"
#include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if dpdk_conf.has('RTE_ARCH_RISCV')
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.30.2
[PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag
From: Michal Mazurek
Add checks for all flag values defined in the RISC-V misa CSR register.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
app/test/test_cpuflags.c | 81
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
[PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh
Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- devtools/test-meson-builds.sh | 4 1 file changed, 4 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..f732dccf6c 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,10 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configuration +build build-riscv64-linux-gcc $srcdir/config/riscv/riscv64_linux_gcc ABI \ + $use_shared + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc -- 2.30.2
[PATCH v3 8/8] ci: add RISCV64 cross compilation job
Checks cross-compilation using Ubuntu 20.04 x86.
Signed-off-by: David Marchand
Signed-off-by: Stanislaw Kardach
---
.ci/linux-build.sh | 4
.github/workflows/build.yml | 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 877243c9c8..aa5e9ec114 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
fi
+if [ "$RISCV64" = "true" ]; then
+cross_file=config/riscv/riscv64_linux_gcc
+fi
+
if [ -n "$cross_file" ]; then
OPTS="$OPTS --cross-file $cross_file"
fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e2f94d786b..ca468da8fa 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,6 +25,7 @@ jobs:
MINI: ${{ matrix.config.mini != '' }}
PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
REF_GIT_TAG: v22.03
+ RISCV64: ${{ matrix.config.cross == 'riscv64' }}
RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
strategy:
@@ -73,6 +74,10 @@ jobs:
compiler: gcc
library: shared
cross: ppc64le
+ - os: ubuntu-20.04
+compiler: gcc
+library: shared
+cross: riscv64
steps:
- name: Checkout sources
@@ -131,8 +136,12 @@ jobs:
if: env.PPC64LE == 'true'
run: sudo apt install -y gcc-powerpc64le-linux-gnu
libc6-dev-ppc64el-cross
pkg-config-powerpc-linux-gnu
+- name: Install riscv64 cross compiling packages
+ if: env.RISCV64 == 'true'
+ run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+pkg-config-riscv64-linux-gnu
- name: Install test tools packages
- if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS ==
'true'
+ if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 !=
'true' || env.RUN_TESTS == 'true'
run: sudo apt install -y gdb
- name: Install doc generation packages
if: env.BUILD_DOCS == 'true'
--
2.30.2
[PATCH v2 1/1] examples/l3fwd: fix scalar LPM compilation
The lpm_process_event_pkt() can either process a packet using an
architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
path or a scalar one. The choice is however done using an ifdef
pre-processor macro. Because of that the scalar version was apparently
not widely excersized/compiled.
Due to some copy/paste errors, the scalar logic in
lpm_process_event_pkt() retained a "continue" statement where it should
utilize rfc1812_process() and return the port/BAD_PORT.
Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
Cc: pbhagavat...@marvell.com
Signed-off-by: Stanislaw Kardach
---
v2: Replace existing logic with rfc1812_process().
---
examples/l3fwd/l3fwd_lpm.c | 24 ++--
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c
index bec22c44cd..7a1e60f6b3 100644
--- a/examples/l3fwd/l3fwd_lpm.c
+++ b/examples/l3fwd/l3fwd_lpm.c
@@ -28,6 +28,7 @@
#include
#include "l3fwd.h"
+#include "l3fwd_common.h"
#include "l3fwd_event.h"
#include "lpm_route_parse.c"
@@ -237,30 +238,17 @@ lpm_process_event_pkt(const struct lcore_conf *lconf,
struct rte_mbuf *mbuf)
struct rte_ether_hdr *eth_hdr = rte_pktmbuf_mtod(mbuf,
struct rte_ether_hdr *);
-#ifdef DO_RFC_1812_CHECKS
- struct rte_ipv4_hdr *ipv4_hdr;
- if (RTE_ETH_IS_IPV4_HDR(mbuf->packet_type)) {
- /* Handle IPv4 headers.*/
- ipv4_hdr = rte_pktmbuf_mtod_offset(mbuf,
- struct rte_ipv4_hdr *,
- sizeof(struct rte_ether_hdr));
-
- if (is_valid_ipv4_pkt(ipv4_hdr, mbuf->pkt_len)
- < 0) {
- mbuf->port = BAD_PORT;
- continue;
- }
- /* Update time to live and header checksum */
- --(ipv4_hdr->time_to_live);
- ++(ipv4_hdr->hdr_checksum);
- }
-#endif
+
/* dst addr */
*(uint64_t *)ð_hdr->dst_addr = dest_eth_addr[mbuf->port];
/* src addr */
rte_ether_addr_copy(&ports_eth_addr[mbuf->port],
ð_hdr->src_addr);
+
+ rfc1812_process(rte_pktmbuf_mtod_offset(mbuf, struct rte_ipv4_hdr *,
+ sizeof(struct rte_ether_hdr)),
+ &mbuf->port, mbuf->packet_type);
#endif
return mbuf->port;
}
--
2.30.2
[PATCH v2 1/1] test/ring: remove excessive inlining
Forcing inlining in test_ring_enqueue and test_ring_dequeue can cause
the compiled code to grow extensively when compiled with no optimization
(-O0 or -Og). This is default in the meson's debug configuration. This
can collide with compiler bugs and cause issues during linking of unit
tests where the api_type or esize are non-const variables causing
inlining cascade. In perf tests this is not the case in perf-tests as
esize and api_type are const values.
One such case was discovered when porting DPDK to RISC-V. GCC 11.2 (and
no fix still in 12.1) is generating a short relative jump instruction
(J ) for goto and for loops. When loop body grows extensively in
ring test, the target offset goes beyond supported offfset of +/- 1MB
from PC. This is an obvious bug in the GCC as RISC-V has a
two-instruction construct to jump to any absolute address (AUIPC+JALR).
However there is no reason to force inlining as the test code works
perfectly fine without it.
GCC has a bug report for a similar case (with conditionals):
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93062
Fixes: a9fe152363 test/ring: add custom element size functional tests
Signed-off-by: Stanislaw Kardach
---
app/test/test_ring.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/app/test/test_ring.h b/app/test/test_ring.h
index c8bfec8399..45c263f3ff 100644
--- a/app/test/test_ring.h
+++ b/app/test/test_ring.h
@@ -97,7 +97,7 @@ test_ring_copy_from(struct rte_ring_zc_data *zcd, void *dst,
int esize,
}
}
-static __rte_always_inline unsigned int
+static inline unsigned int
test_ring_enqueue(struct rte_ring *r, void **obj, int esize, unsigned int n,
unsigned int api_type)
{
@@ -158,7 +158,7 @@ test_ring_enqueue(struct rte_ring *r, void **obj, int
esize, unsigned int n,
}
}
-static __rte_always_inline unsigned int
+static inline unsigned int
test_ring_dequeue(struct rte_ring *r, void **obj, int esize, unsigned int n,
unsigned int api_type)
{
@@ -222,7 +222,7 @@ test_ring_dequeue(struct rte_ring *r, void **obj, int
esize, unsigned int n,
/* This function is placed here as it is required for both
* performance and functional tests.
*/
-static __rte_always_inline void *
+static inline void *
test_ring_calloc(unsigned int rsize, int esize)
{
unsigned int sz;
--
2.30.2
[PATCH v2 1/2] lpm: add const to lpm arg of rte_lpm_lookup
All other rte_lpm_lookup* functions take lpm argument as a const. As the
basic rte_lpm_lookup() performs the same function, it should also do
that.
As this function is inline, no API/ABI change happens.
Signed-off-by: Stanislaw Kardach
---
lib/lpm/rte_lpm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..1cf863a146 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -279,7 +279,7 @@ rte_lpm_delete_all(struct rte_lpm *lpm);
* -EINVAL for incorrect arguments, -ENOENT on lookup miss, 0 on lookup hit
*/
static inline int
-rte_lpm_lookup(struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
+rte_lpm_lookup(const struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
{
unsigned tbl24_index = (ip >> 8);
uint32_t tbl_entry;
--
2.30.2
[PATCH v2 2/2] lpm: add a scalar version of lookupx4 function
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with a basic level of LPM support.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
doc/guides/rel_notes/release_22_07.rst | 5
lib/lpm/meson.build| 1 +
lib/lpm/rte_lpm.h | 4 ++-
lib/lpm/rte_lpm_scalar.h | 36 ++
4 files changed, 45 insertions(+), 1 deletion(-)
create mode 100644 lib/lpm/rte_lpm_scalar.h
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index e49cacecef..0cf3f71269 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,11 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added scalar version of the LPM library.**
+
+ * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
Removed Items
-
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
indirect_headers += files(
'rte_lpm_altivec.h',
'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 1cf863a146..4f38864fde 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
#endif
#ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..2fc0e19161
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ uint32_t nh;
+ int i, ret;
+
+ for (i = 0; i < 4; i++) {
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[i], &nh);
+ hop[i] = (ret == 0) ? nh : defv;
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_SCALAR_H_ */
--
2.30.2
[PATCH v3 1/2] lpm: add const to lpm arg of rte_lpm_lookup
All other rte_lpm_lookup* functions take lpm argument as a const. As the
basic rte_lpm_lookup() performs the same function, it should also do
that.
As this function is inline, no API/ABI change happens.
Signed-off-by: Stanislaw Kardach
---
lib/lpm/rte_lpm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..1cf863a146 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -279,7 +279,7 @@ rte_lpm_delete_all(struct rte_lpm *lpm);
* -EINVAL for incorrect arguments, -ENOENT on lookup miss, 0 on lookup hit
*/
static inline int
-rte_lpm_lookup(struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
+rte_lpm_lookup(const struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
{
unsigned tbl24_index = (ip >> 8);
uint32_t tbl_entry;
--
2.30.2
[PATCH v3 2/2] lpm: add a scalar version of lookupx4 function
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with a basic level of LPM support.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
doc/guides/rel_notes/release_22_07.rst | 5
lib/lpm/meson.build| 1 +
lib/lpm/rte_lpm.h | 4 ++-
lib/lpm/rte_lpm_scalar.h | 40 ++
4 files changed, 49 insertions(+), 1 deletion(-)
create mode 100644 lib/lpm/rte_lpm_scalar.h
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index e49cacecef..0cf3f71269 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,11 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added scalar version of the LPM library.**
+
+ * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
Removed Items
-
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
indirect_headers += files(
'rte_lpm_altivec.h',
'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 1cf863a146..4f38864fde 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
#endif
#ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..4ae1b6f0b8
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include
+#include
+#include
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ uint32_t nh;
+ int ret;
+
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[0], &nh);
+ hop[0] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[1], &nh);
+ hop[1] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[2], &nh);
+ hop[2] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[3], &nh);
+ hop[3] = (ret == 0) ? nh : defv;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_SCALAR_H_ */
--
2.30.2
[PATCH v4 0/8] Introduce support for RISC-V architecture
This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v4: - Update RISC-V cross-compilation docs to remove vendor-specific instructions and better match the Ubuntu environment. - Remove optional "fence" removal in the CYCLE and TIME counter reads as those are irrelevant compared to the cost of a firmware call that allowed such removal. The per-platform build-configuration is left in meson files for setting '-mtune' and reference for future platforms. - Update cross-files to specify PKG_CONFIG_LIBDIR instead of relying on the riscv64-linux-gnu-pkg-config wrapper which was removed from Ubuntu anyway. Also use sys_root properly instead of using c_args directly. - Note: rte_rdtsc handling is left as it was in v3: TIME counter default, CYCLE via compile-time option. This is mostly due to CYCLE being core-local with values differing among cores which causes timer_autotest to run overly long if it so happens that CYCLE on core 0 is ahead of other cores' CYCLEs. This makes TIME counter more stable for general usage. Since CYCLE read in userspace can be disabled by the kernel-mode (it isn't currently), the compile-time approach is taken, same as with Aarch64. - Added details on --no-huge tests failing in the known_issues.rst. - Additional notes on tests: - link_bonding_mode4_autotest succeeds and then dpdk-test fails with segmentation fault randomly when run directly (via DPDK_TEST env variable) with MALLOC_PERTURB_. This was not noticed in any other test suggesting that there is a race condition somewhere in the link_bonding PMD that leads to use-after-free (since MALLOC_PERTURB_ causes free() to re-initialize freed memory to a given value). - ipsec_perf_autotest currently does not check whether there is any crypto device available (as ipsec_autotest does) and therefore fails. v3: - Limit test-meson-builds.sh testing to a generic rv64gc configuration. Previous version was missing this change by mistake. v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. [1] http://lists.infradead.org/pipermail/opensbi/2021-June/001219.html Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job .ci/linux-build.sh| 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 +++ app/test/test_xmmt_ops.h | 16 +++ config/meson.build| 2 + config/riscv/meson.build | 131 ++ config/riscv/riscv64_linux_gcc| 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc| 20 +++ devtools/test-meson-builds.sh | 4 + doc/guides/contributing/design.rst| 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 115
[PATCH v4 1/8] eal: add initial support for RISC-V architecture
From: Michal Mazurek
Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.
This includes:
- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
U74 core.
Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.
Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI), its frequency might change due to DVFS and
it is core-local and therefore cannot be used as a wall-clock. It can
however be used for micro-benchmarking user applications, similarly to
Aarch64's PMCCNTR PMU counter.
The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.
The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.
The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Known checkpatch errors/warnings:
- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
Depends-on: series-22867 ("test/ring: remove excessive inlining")
Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
---
MAINTAINERS | 6 +
app/test/test_xmmt_ops.h | 16 +++
config/meson.build| 2 +
config/riscv/meson.build | 131 ++
config/riscv/riscv64_linux_gcc| 17 +++
config/riscv/riscv64_sifive_u740_linux_gcc| 20 +++
doc/guides/contributing/design.rst| 2 +-
.../linux_gsg/cross_build_dpdk_for_riscv.rst | 115 +++
doc/guides/linux_gsg/index.rst| 1 +
doc/guides/nics/features.rst | 5 +
doc/guides/nics/features/default.ini | 1 +
doc/guides/rel_notes/known_issues.rst | 10 +-
doc/guides/rel_notes/release_22_07.rst| 8 ++
drivers/net/i40e/meson.build | 6 +
drivers/net/ixgbe/meson.build | 6 +
drivers/net/memif/meson.build | 5 +
drivers/net/tap/meson.build | 5 +
examples/l3fwd/meson.build| 6 +
lib/eal/riscv/include/meson.build | 23 +++
lib/eal/riscv/include/rte_atomic.h| 52 +++
lib/eal/riscv/include/rte_byteorder.h | 44 ++
lib/eal/riscv/include/rte_cpuflags.h | 55
lib/eal/riscv/include/rte_cycles.h| 101 ++
lib/eal/riscv/include/rte_io.h| 21 +++
lib/eal/riscv/include/rte_mcslock.h | 18 +++
lib/eal/riscv/include/rte_memcpy.h| 63 +
lib/eal/riscv/include/rte_pause.h | 31 +
lib/eal/riscv/include/rte_pflock.h| 17 +++
lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++
lib/eal/riscv/include/rte_prefetch.h | 50 +++
lib/eal/riscv/include/rte_rwlock.h| 44 ++
lib/eal/riscv/include/rte_spinlock.h | 67 +
lib/eal/riscv/include/rte_ticketlock.h| 21 +++
lib/eal/riscv/include/rte_vect.h | 55
lib/eal/riscv/meson.build | 11 ++
lib/eal/riscv/rte_cpuflags.c | 122
lib/eal/riscv/rte_cycles.c|
[PATCH v4 2/8] net/ixgbe: enable vector stubs for RISC-V
Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.
The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
doc/guides/nics/features/ixgbe.ini | 1 +
drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++--
drivers/net/ixgbe/meson.build | 6 --
3 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/doc/guides/nics/features/ixgbe.ini
b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows = Y
ARMv8= Y
x86-32 = Y
x86-64 = Y
+rv64 = Y
[rte_flow items]
eth = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
return 0;
}
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
int
ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
{
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
subdir('base')
--
2.30.2
[PATCH v4 3/8] net/memif: set memfd syscall ID on RISC-V
Define the missing __NR_memfd_create syscall id to enable the memif PMD. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- drivers/net/memif/meson.build | 5 - drivers/net/memif/rte_eth_memif.h | 2 ++ 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build index 9afb495953..680bc8631c 100644 --- a/drivers/net/memif/meson.build +++ b/drivers/net/memif/meson.build @@ -5,11 +5,6 @@ if not is_linux build = false reason = 'only supported on Linux' endif -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif sources = files( 'memif_socket.c', diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h index a5ee23d42e..81e7dceae0 100644 --- a/drivers/net/memif/rte_eth_memif.h +++ b/drivers/net/memif/rte_eth_memif.h @@ -180,6 +180,8 @@ const char *memif_version(void); #define __NR_memfd_create 360 #elif defined __i386__ #define __NR_memfd_create 356 +#elif defined __riscv +#define __NR_memfd_create 279 #else #error "__NR_memfd_create unknown for this architecture" #endif -- 2.30.2
[PATCH v4 4/8] net/tap: set BPF syscall ID for RISC-V
Define the missing __NR_bpf syscall id to enable the tap PMD.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
drivers/net/tap/meson.build | 5 -
drivers/net/tap/tap_bpf.h | 2 ++
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
build = false
reason = 'only supported on Linux'
endif
-if arch_subdir == 'riscv'
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
sources = files(
'rte_eth_tap.c',
'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
# define __NR_bpf 351
# elif defined(__powerpc__)
# define __NR_bpf 361
+# elif defined(__riscv)
+# define __NR_bpf 280
# else
# error __NR_bpf not defined
# endif
--
2.30.2
[PATCH v4 5/8] examples/l3fwd: enable RISC-V operation
Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Stanislaw Kardach
---
examples/l3fwd/l3fwd_em.c | 8
examples/l3fwd/l3fwd_fib.c | 2 ++
examples/l3fwd/meson.build | 6 --
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 6f8d94f120..10be24c61d 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
return vec_and(data, mask);
}
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+ xmm_t data = vect_load_128(key);
+
+ return vect_and(data, mask);
+}
#else
#error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
#endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 26d0767ae2..e02e4b3f5a 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
#include "l3fwd_neon.h"
#elif defined RTE_ARCH_PPC_64
#include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
#endif
#include "l3fwd_event.h"
#include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
# To build this example as a standalone application with an already-installed
# DPDK instance, use 'make'
-if dpdk_conf.has('RTE_ARCH_RISCV')
- build = false
- reason = 'riscv arch not supported'
- subdir_done()
-endif
-
allow_experimental_apis = true
deps += ['hash', 'lpm', 'fib', 'eventdev']
sources = files(
--
2.30.2
[PATCH v4 6/8] test/cpuflags: add test for RISC-V cpu flag
From: Michal Mazurek
Add checks for all flag values defined in the RISC-V misa CSR register.
Sponsored-by: Frank Zhao
Sponsored-by: Sam Grove
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
app/test/test_cpuflags.c | 81
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
[PATCH v4 7/8] devtools: add RISC-V to test-meson-builds.sh
Validate RISC-V compilation when test-meson-builds.sh is called. The check will be only performed if appropriate toolchain is present on the system (same as with other architectures). Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- devtools/test-meson-builds.sh | 4 1 file changed, 4 insertions(+) diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh index a653b253cb..f732dccf6c 100755 --- a/devtools/test-meson-builds.sh +++ b/devtools/test-meson-builds.sh @@ -275,6 +275,10 @@ for f in $srcdir/config/ppc/ppc* ; do build $targetdir $f ABI $use_shared done +# RISC-V configuration +build build-riscv64-linux-gcc $srcdir/config/riscv/riscv64_linux_gcc ABI \ + $use_shared + # Test installation of the x86-generic target, to be used for checking # the sample apps build using the pkg-config file for cflags and libs load_env cc -- 2.30.2
[PATCH v4 8/8] ci: add RISCV64 cross compilation job
Checks cross-compilation using Ubuntu 20.04 x86.
Signed-off-by: David Marchand
Signed-off-by: Stanislaw Kardach
---
.ci/linux-build.sh | 4
.github/workflows/build.yml | 11 ++-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 1de8962f0e..06104eca22 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
fi
+if [ "$RISCV64" = "true" ]; then
+cross_file=config/riscv/riscv64_linux_gcc
+fi
+
if [ -n "$cross_file" ]; then
OPTS="$OPTS --cross-file $cross_file"
fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ad8ad1a187..7c8528cb04 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -26,6 +26,7 @@ jobs:
MINI: ${{ matrix.config.mini != '' }}
PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
REF_GIT_TAG: v22.03
+ RISCV64: ${{ matrix.config.cross == 'riscv64' }}
RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
strategy:
@@ -74,6 +75,10 @@ jobs:
compiler: gcc
library: shared
cross: ppc64le
+ - os: ubuntu-20.04
+compiler: gcc
+library: shared
+cross: riscv64
steps:
- name: Checkout sources
@@ -132,8 +137,12 @@ jobs:
if: env.PPC64LE == 'true'
run: sudo apt install -y gcc-powerpc64le-linux-gnu
libc6-dev-ppc64el-cross
pkg-config-powerpc-linux-gnu
+- name: Install riscv64 cross compiling packages
+ if: env.RISCV64 == 'true'
+ run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+pkg-config-riscv64-linux-gnu
- name: Install test tools packages
- if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS ==
'true'
+ if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 !=
'true' || env.RUN_TESTS == 'true'
run: sudo apt install -y gdb
- name: Install doc generation packages
if: env.BUILD_DOCS == 'true'
--
2.30.2
[PATCH] test/ipsec: check for cryptodevs before testing
Make sure that ipsec_perf_autotest checks if there are any crypto
devices available before it starts performance testing.
Same test is performed in the ipsec_autotest so it seems prudent to do
it here too to not introduce false failures.
Signed-off-by: Stanislaw Kardach
---
app/test/test_ipsec_perf.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/app/test/test_ipsec_perf.c b/app/test/test_ipsec_perf.c
index 346a851648..0eca003282 100644
--- a/app/test/test_ipsec_perf.c
+++ b/app/test/test_ipsec_perf.c
@@ -597,6 +597,12 @@ test_libipsec_perf(void)
uint32_t i;
int ret;
+ ret = rte_cryptodev_count();
+ if (ret < 1) {
+ RTE_LOG(WARNING, USER1, "No crypto devices found?\n");
+ return TEST_SKIPPED;
+ }
+
if (testsuite_setup() < 0) {
testsuite_teardown();
return TEST_FAILED;
--
2.30.2
[PATCH v4 1/2] lpm: add const to lpm arg of rte_lpm_lookup
All other rte_lpm_lookup* functions take lpm argument as a const. As the
basic rte_lpm_lookup() performs the same function, it should also do
that.
As this function is inline, no API/ABI change happens.
Signed-off-by: Stanislaw Kardach
Acked-by: Vladimir Medvedkin
Acked-by: Stephen Hemminger
---
lib/lpm/rte_lpm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..1cf863a146 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -279,7 +279,7 @@ rte_lpm_delete_all(struct rte_lpm *lpm);
* -EINVAL for incorrect arguments, -ENOENT on lookup miss, 0 on lookup hit
*/
static inline int
-rte_lpm_lookup(struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
+rte_lpm_lookup(const struct rte_lpm *lpm, uint32_t ip, uint32_t *next_hop)
{
unsigned tbl24_index = (ip >> 8);
uint32_t tbl_entry;
--
2.30.2
[PATCH v4 2/2] lpm: add a scalar version of lookupx4 function
From: Michal Mazurek
Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.
This will be useful in the upcoming RISC-V port as well as any platform
which may want to start with a basic level of LPM support.
Signed-off-by: Michal Mazurek
Signed-off-by: Stanislaw Kardach
---
doc/guides/rel_notes/release_22_07.rst | 5
lib/lpm/meson.build| 1 +
lib/lpm/rte_lpm.h | 4 ++-
lib/lpm/rte_lpm_scalar.h | 37 ++
4 files changed, 46 insertions(+), 1 deletion(-)
create mode 100644 lib/lpm/rte_lpm_scalar.h
diff --git a/doc/guides/rel_notes/release_22_07.rst
b/doc/guides/rel_notes/release_22_07.rst
index e49cacecef..0cf3f71269 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -104,6 +104,11 @@ New Features
* ``RTE_EVENT_QUEUE_ATTR_WEIGHT``
* ``RTE_EVENT_QUEUE_ATTR_AFFINITY``
+* **Added scalar version of the LPM library.**
+
+ * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+implementation for platforms that don't support vector operations.
+
Removed Items
-
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
indirect_headers += files(
'rte_lpm_altivec.h',
'rte_lpm_neon.h',
+'rte_lpm_scalar.h',
'rte_lpm_sse.h',
'rte_lpm_sve.h',
)
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index 1cf863a146..4f38864fde 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip,
uint32_t hop[4],
#endif
#elif defined(RTE_ARCH_PPC_64)
#include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
#include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
#endif
#ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 00..f0d9f37894
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+ uint32_t defv)
+{
+ uint32_t nh;
+ int ret;
+
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[0], &nh);
+ hop[0] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[1], &nh);
+ hop[1] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[2], &nh);
+ hop[2] = (ret == 0) ? nh : defv;
+ ret = rte_lpm_lookup(lpm, ((rte_xmm_t)ip).u32[3], &nh);
+ hop[3] = (ret == 0) ? nh : defv;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_SCALAR_H_ */
--
2.30.2
[PATCH 1/1] maintainers: update RISC-V maintainer email
Change my email to a personal one. Signed-off-by: Stanislaw Kardach --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b9d258e627..e61c57b1be 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -310,7 +310,7 @@ F: examples/*/*_altivec.* F: examples/common/altivec/ RISC-V -M: Stanislaw Kardach +M: Stanislaw Kardach F: config/riscv/ F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst F: lib/eal/riscv/ -- 2.43.0.687.g38aa6559b0-goog
Re: [PATCH v4 4/9] dts: add ssh pexpect library
On Fri, Jul 29, 2022 at 10:55:45AM +, Juraj Linkeš wrote:
> +self.session = pxssh.pxssh(encoding="utf-8")
> +self.session.login(
> +self.node,
> +self.username,
> +self.password,
> +original_prompt="[$#>]",
> +password_regex=r"(?i)(?:password:)|(?:passphrase for
> key)|(?i)(password for .+:)",
> +)
> +self.logger.info(f"Connection to {self.node} succeeded")
> +self.send_expect("stty -echo", "#")
> +self.send_expect("stty columns 1000", "#")
First of all, thanks for those changes! Having DTS inside DPDK makes
test synchronization a lot easier. I'm happy to say (unsurprisingly)
that it works with my RISC-V HiFive Unmatched board like a charm.
Though there is a small issue with the lines above. They assume "#" as
the prompt sign, even though original_prompt was set to "[$#>]". This
touches on two problems:
1. # is usually a root prompt - is DTS assumed to be run with root
privileges? DPDK may (in theory) run without them with some permission
adjustment (hugetlb, VFIO container, etc.). If we assume DTS needs
root access, this has to be both documented and validated before
running the whole suite. Otherwise it'll be hard to debug.
2. Different shells use different prompts on different distros. Hence
perhaps there should be a regex here (same as with original_prompt)
and there could be a conf.yaml option to modify it on a per-host
basis?
--
Best Regards,
Stanislaw Kardach
Re: [PATCH v4 4/9] dts: add ssh pexpect library
On Wed, Sep 14, 2022 at 08:42:07AM +0100, Bruce Richardson wrote: > > > >As far as customizing the prompts, I think that is doable via a > >configuration option. > >As far as different shells, I don't think we were planning to support > >anything besides either bash or posix-compatible shells. At the moment > >all of the community lab systems use bash, and for ease of test > >development it will be easier to mandate that everyone uses one shell. > >Otherwise DTS CI will need to run once for each shell to catch issues, > >which in my opinion are resources better spent on more in-depth testing > >of DTS and DPDK. > > > >[Honnappa] +1 for using just bash, we can document this as well. > > > > I would agree overall. Just supporting one shell is fine - certainly for > now. Also completely agree that we need to remove hard-coded passwords and > ideally non-root. However, I think for the initial versions the main thing > should be removing the passwords so I would be ok for keeping the "root" > login requirement, so long as we support using ssh keys for login rather > than hard-coded passwords. > > /Bruce The only reason I have mentioned different shells is to illustrate that prompt might be changed not only due to user modifying PS1 env variable. I agree with the rest (root-only, bash-only). -- Best Regards, Stanislaw Kardach
Re: [PATCH v4 4/9] dts: add ssh pexpect library
"Exception happened in [%s] and output is [%s]"
> +% (command, self.get_output_before())
> +)
> +)
> +raise e
> +
> +def send_command(self, command: str, timeout: float = 1) -> str:
> +try:
> +self.clean_session()
> +self.__sendline(command)
> +except Exception as e:
> +raise e
> +
> +output = self.get_session_before(timeout=timeout)
> +self.session.PROMPT = self.session.UNIQUE_PROMPT
> +self.session.prompt(0.1)
This is wrong:
1. self.get_session_before() will return output of the command but since
it changed the expected (not real!) prompt to self.magic_prompt, that
won't be matched so the output will contain the prompt set by pxssh
(UNIQUE_PROMPT).
2. Then prompt is reset to UNIQUE_PROMPT but and prompt() is called but
that will only clean up the pxssh buffer. If get_session_before() was
not changing the session.PROMPT from UNIQUE_PROMPT to magic_prompt,
the second prompt() call would be unnecessary.
> +
> +return output
> +
> +def clean_session(self) -> None:
> +self.get_session_before(timeout=0.01)
What if remote host is slow for any reason? We'll timeout here. It seems
that such a small timeout value was used because clean_session() is
used in every send_command() call.
Come to think of it, why is this call necessary when we have
self.__flush()?
> +
> +def get_session_before(self, timeout: float = 15) -> str:
> +"""
> +Get all output before timeout
> +"""
> +self.session.PROMPT = self.magic_prompt
This line has no effect. Remote prompt was never set to
self.magic_prompt.
> +try:
> +self.session.prompt(timeout)
> +except Exception as e:
> +pass
> +
> +before = self.get_output_all()
> +self.__flush()
> +
> +return before
> +
> +def __flush(self) -> None:
> +"""
> +Clear all session buffer
> +"""
> +self.session.buffer = ""
> +self.session.before = ""
> +
> +def __prompt(self, command: str, timeout: float) -> None:
> +if not self.session.prompt(timeout):
> +raise TimeoutException(command, self.get_output_all()) from None
> +
> +def __sendline(self, command: str) -> None:
> +if not self.isalive():
> +raise SSHSessionDeadException(self.node)
> +if len(command) == 2 and command.startswith("^"):
> +self.session.sendcontrol(command[1])
> +else:
> +self.session.sendline(command)
> +
> +def get_output_before(self) -> str:
The name is missleading. In pxssh terms "before" means all the lines
before the matched expect()/prompt(). Here it returns the last line of
the output. Perhaps get_last_output_line() is better?
> +if not self.isalive():
> +raise SSHSessionDeadException(self.node)
> +before: list[str] = self.session.before.rsplit("\r\n", 1)
> +if before[0] == "[PEXPECT]":
> +before[0] = ""
Unnecessary if prompt was handled in proper way as mentioned above.
> +
> +return before[0]
> +
> +def get_output_all(self) -> str:
> +output: str = self.session.before
> +output.replace("[PEXPECT]", "")
Ditto. If session.PROMPT was restored properly, this function would not
be necessary at all.
> +return output
> +
> +def close(self, force: bool = False) -> None:
> +if force is True:
> +self.session.close()
> +else:
> +if self.isalive():
> +self.session.logout()
> +
> +def isalive(self) -> bool:
> +return self.session.isalive()
> diff --git a/dts/framework/utils.py b/dts/framework/utils.py
> new file mode 100644
> index 00..db87349827
> --- /dev/null
> +++ b/dts/framework/utils.py
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2010-2014 Intel Corporation
> +# Copyright(c) 2022 PANTHEON.tech s.r.o.
> +# Copyright(c) 2022 University of New Hampshire
> +#
> +
> +def RED(text: str) -> str:
> +return f"\u001B[31;1m{str(text)}\u001B[0m"
> +
> +
> +def GREEN(text: str) -> str:
> +return f"\u001B[32;1m{str(text)}\u001B[0m"
> --
> 2.30.2
>
--
Best Regards,
Stanislaw Kardach
Re: [PATCH v4 4/9] dts: add ssh pexpect library
as no effect. Remote prompt was never set to self.magic_prompt.
>
> I think this is to ensure that we hit the timeout.
Why would we intentionally want to hit a timeout? Unless I'm missing
something, it'll only cause us to wait for "timeout" even if the command
ended already. Also note the full logic of the "get_session_before()":
1. Trigger self.session.prompt() to get the session buffer updated with
whatever output was between now and now+timeout seconds.
2. Get the output but since we were matching the self.magic_prompt,
self.get_output_all() has to remove the real prompt ([PEXPECT]) if
the command ended.
3. Flush the pexpect's ssh buffer so that next call won't read what has
already been returned (that's the job of self.__flush()).
So I don't think there is any reason to use this always-timeout logic.
>
> > > +try:
> > > +self.session.prompt(timeout)
> > > +except Exception as e:
> > > +pass
> > > +
> > > +before = self.get_output_all()
> > > +self.__flush()
> > > +
> > > +return before
> > > +
> > > +def __flush(self) -> None:
> > > +"""
> > > +Clear all session buffer
> > > +"""
> > > +self.session.buffer = ""
> > > +self.session.before = ""
> > > +
> > > +def __prompt(self, command: str, timeout: float) -> None:
> > > +if not self.session.prompt(timeout):
> > > +raise TimeoutException(command, self.get_output_all())
> > > + from None
> > > +
> > > +def __sendline(self, command: str) -> None:
> > > +if not self.isalive():
> > > +raise SSHSessionDeadException(self.node)
> > > +if len(command) == 2 and command.startswith("^"):
> > > +self.session.sendcontrol(command[1])
> > > +else:
> > > +self.session.sendline(command)
> > > +
> > > +def get_output_before(self) -> str:
> > The name is missleading. In pxssh terms "before" means all the lines before
> > the
> > matched expect()/prompt(). Here it returns the last line of the output.
> > Perhaps
> > get_last_output_line() is better?
>
> I thought so too, but this actually returns all lines except the last:
> 'a.b.c.d'.rsplit('.', 1)[0]
> 'a.b.c'
>
Oh, I've totally missed that!
If that's the case then this function is a result of the always-timeout
logic. Note that get_output_before() is only called from
send_expect_base() (and indirectly by send_expect()) to get the output
of the command without the prompt.
So the reason why self.send_expect("echo 'foo'", "#") returns a proper
output ('foo\n') is:
0. On login() time pexpect sets the remote prompt to "[PEXPECT]#".
1. send_expect() -> self.send_expect_base() sets the match prompt to #.
This causes self.session.prompt() to update the self.session.buffer,
match # and chomp it, leaving the ssh buffer as:
foo
[PEXPECT]
2. send_expect_base() calls self.get_output_before() which cuts the last
line of the output. Note that the "if" at the end is necessary for
commands that do not return any output. Otherwise the output would
be "[PEXPECT]". Also note that if there are any control characters
printed by the remote shell, then this will also not work because
a straight string comparison is done, not a regex match.
Contrary, if self.magic_prompt was not used and pexpect's original
prompt was left undisturbed, then all the hacks above would not be
needed and the code would be cleaner.
> > > +if not self.isalive():
> > > +raise SSHSessionDeadException(self.node)
> > > +before: list[str] = self.session.before.rsplit("\r\n", 1)
> > > +if before[0] == "[PEXPECT]":
> > > +before[0] = ""
> > Unnecessary if prompt was handled in proper way as mentioned above.
> > > +
> > > +return before[0]
> > > +
> > > +def get_output_all(self) -> str:
> > > +output: str = self.session.before
> > > +output.replace("[PEXPECT]", "")
> > Ditto. If session.PROMPT was restored properly, this function would not be
> > necessary at all.
> > > +return output
> > > +
> > > +def close(self, force: bool = False) -> None:
> > > +if force is True:
> > > +self.session.close()
> > > +else:
> > > +if self.isalive():
> > > +self.session.logout()
> > > +
> > > +def isalive(self) -> bool:
> > > +return self.session.isalive()
> > > diff --git a/dts/framework/utils.py b/dts/framework/utils.py new file
> > > mode 100644 index 00..db87349827
> > > --- /dev/null
> > > +++ b/dts/framework/utils.py
> > > @@ -0,0 +1,12 @@
> > > +# SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2010-2014
> > > +Intel Corporation # Copyright(c) 2022 PANTHEON.tech s.r.o.
> > > +# Copyright(c) 2022 University of New Hampshire #
> > > +
> > > +def RED(text: str) -> str:
> > > +return f"\u001B[31;1m{str(text)}\u001B[0m"
> > > +
> > > +
> > > +def GREEN(text: str) -> str:
> > > +return f"\u001B[32;1m{str(text)}\u001B[0m"
> > > --
> > > 2.30.2
> > >
> >
> > --
> > Best Regards,
> > Stanislaw Kardach
>
--
Best Regards,
Stanislaw Kardach
Re: [PATCH v4 4/9] dts: add ssh pexpect library
On Fri, Sep 23, 2022 at 09:15:07AM +0100, Bruce Richardson wrote: > On Fri, Sep 23, 2022 at 07:22:26AM +, Juraj Linkeš wrote: > > > > Absolutely, but effective time use is also something to consider. Our > > current plan doesn't won't really have to contend with problems in the > > future, as we want to add the Farbic implementation in the next release > > cycle. I'm also working on refactoring the code a bit - I'm adding an > > abstraction that would allow us to easily replace the pexpect > > implementation with Fabric (with no impact on DTS behavior - the same APIs > > will need to be implemented). Also, we'll remove the pexpect implementation > > once Fabric is in place (unless we can think of a reason for pexpect to > > stay, in which case we'll need to refactor it). I think that instead of > > focusing on pexpect we could focus on making sure the replacement won't > > cause any issues. What do you think? > > > > Personally, I would be very keen to get the move of DTS to the main repo > underway, and so I wouldn't look to have too many massive changes required > before we start seeing patches merged in. Basic code cleanup and > refactoring is fine, but I would think that requiring massive changes like > replacing expect with fabric may be too big an ask. After all, the rest of > DPDK is moving on, meaning more and more DTS content is being added to the > separate DTS repo every release, making the job bigger each time. :-( > > Tl;dr - I'm ok to leave fabric replacement for a release next year. > > /Bruce That makes sense. I would suggest however to put comments around implementation hacks and the public APIs simply to not forget. Though I'd do the refactoring sooner than later because once tests start being merged there will be a higher possibility of them relying on hacks. -- Best Regards, Stanislaw Kardach
Re: [PATCH v5 06/10] dts: add ssh connection module
meout)
> +except Exception:
> +pass
> +
> +before = self._get_output()
> +self.__flush()
> +
> +self.logger.debug(before)
> +return before
> +
> +def __flush(self) -> None:
> +"""
> +Clear all session buffer
> +"""
> +self.session.buffer = ""
> +self.session.before = ""
> +
> +def __prompt(self, command: str, timeout: float) -> None:
> +if not self.session.prompt(timeout):
> +raise TimeoutException(command, self._get_output()) from None
> +
> +def __sendline(self, command: str) -> None:
> +if not self.is_alive():
> +raise SSHSessionDeadException(self.hostname)
> +if len(command) == 2 and command.startswith("^"):
> +self.session.sendcontrol(command[1])
> +else:
> +self.session.sendline(command)
> +
> +def _close(self, force: bool = False) -> None:
> +if force is True:
> +self.session.close()
> +else:
> +if self.is_alive():
> +self.session.logout()
> +
> +def is_alive(self) -> bool:
> +return self.session.isalive()
> diff --git a/dts/framework/utils.py b/dts/framework/utils.py
> new file mode 100644
> index 00..26b784ebb5
> --- /dev/null
> +++ b/dts/framework/utils.py
> @@ -0,0 +1,13 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2010-2014 Intel Corporation
> +# Copyright(c) 2022 PANTHEON.tech s.r.o.
> +# Copyright(c) 2022 University of New Hampshire
> +#
> +
> +
> +def RED(text: str) -> str:
> +return f"\u001B[31;1m{str(text)}\u001B[0m"
> +
> +
> +def GREEN(text: str) -> str:
> +return f"\u001B[32;1m{str(text)}\u001B[0m"
> --
> 2.30.2
>
Reviewed-by: Stanislaw Kardach
--
Best Regards,
Stanislaw Kardach
Re: [PATCH] eal: non-temporal memcpy
On Mon, Oct 10, 2022 at 11:36:11AM +0200, Morten Brørup wrote: > > For large copies, which I'm guessing is what non-temporal stores are > > usually used for, this is hair splitting. For DPDK applications, it > > might well be at least somewhat relevant, because such an application > > may make an enormous amount of copies, each roughly the size of a > > packet. > > > > If we had a rte_memcpy_ex() that only cared about copying whole cache > > line in a NT manner, the application could add a clflushopt (or the > > equivalent) after the copy, flushing the the beginning and end cache > > line of the destination buffer. > > That is a good idea. > > Furthermore, POWER and RISC-V don't have NT store, but if they have a cache > line flush instruction, NT destination memcpy could be implemented for those > architectures too - i.e. storing cache line sized blocks and flushing the > cache, and letting the application flush the cache lines at the ends, if > useful for the application. On RISC-V all stores are from a register (scalar or vector) to a memory location. So is the reasoning behind flushing the cache line to free it up to other data? Other than that there is a ratified RISC-V extension for cache management operations (including flush) - Zicbom. NT load/store hints are being worked on right now. -- Best Regards, Stanislaw Kardach
Re: [dpdk-dev] [PATCH v3 17/22] net/ena: support SMP for mz alloc counter
On Fri, May 07, 2021 at 05:48:50PM +0100, Ferruh Yigit wrote:
> On 5/6/2021 3:25 PM, Michal Krawczyk wrote:
> > From: Stanislaw Kardach
> >
> > Introduce a memory area for ENA driver shared between all the processes
> > of a same prefix (memzone backed).
> > Move the memzone allocation counter for ENA_MEM_ALLOC_COHERENT there so
> > that all processes may utilize it.
>
> Device private data is already shared between primary/secondary processes, why
> not using it, it is already there.
Please correct me if I'm wrong, the dev->data->dev_private is a
per-device space, whereas the memzone here is used as a shared memory
between all ena devices.
More precisely the memzone counter used here is required to wrap some of
the base ena code we are calling and may be called from the context of
any device. Given that memzone names have to be unique, I need this
counter to be unique too.
I believe similar thing is done in mlx5 driver
(mlx5_init_shared_data()). If there is a better way to register such a
shared segment that is going to be preserved until all processes
(primary and secondary) are closed I would be happy to rework this.
>
> Next patch sharing RSS key using this shared area, can you device private data
> so all devices can access it.
It is somewhat similar case. The default key there is generated once for
all devices and then used in each of them.
>
> >
> > Signed-off-by: Stanislaw Kardach
> > Reviewed-by: Michal Krawczyk
> > Reviewed-by: Igor Chauskin
> > Reviewed-by: Shay Agroskin
> > ---
> > drivers/net/ena/base/ena_plat_dpdk.h | 6 ++--
> > drivers/net/ena/ena_ethdev.c | 46 +++-
> > drivers/net/ena/ena_ethdev.h | 8 +
> > 3 files changed, 56 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/net/ena/base/ena_plat_dpdk.h
> > b/drivers/net/ena/base/ena_plat_dpdk.h
> > index 1d0454bebe..e17970361a 100644
> > --- a/drivers/net/ena/base/ena_plat_dpdk.h
> > +++ b/drivers/net/ena/base/ena_plat_dpdk.h
> > @@ -209,7 +209,7 @@ typedef struct {
> > * Each rte_memzone should have unique name.
> > * To satisfy it, count number of allocations and add it to name.
> > */
> > -extern rte_atomic64_t ena_alloc_cnt;
> > +extern rte_atomic64_t *ena_alloc_cnt;
> >
> > #define ENA_MEM_ALLOC_COHERENT_ALIGNED(
> >\
> > dmadev, size, virt, phys, mem_handle, alignment) \
> > @@ -219,7 +219,7 @@ extern rte_atomic64_t ena_alloc_cnt;
> > if (size > 0) {\
> > char z_name[RTE_MEMZONE_NAMESIZE]; \
> > snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\
> > - rte_atomic64_add_return(&ena_alloc_cnt, 1)); \
> > + rte_atomic64_add_return(ena_alloc_cnt, 1));\
> > mz = rte_memzone_reserve_aligned(z_name, size, \
> > SOCKET_ID_ANY, RTE_MEMZONE_IOVA_CONTIG,\
> > alignment);\
> > @@ -249,7 +249,7 @@ extern rte_atomic64_t ena_alloc_cnt;
> > if (size > 0) {\
> > char z_name[RTE_MEMZONE_NAMESIZE]; \
> > snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\
> > - rte_atomic64_add_return(&ena_alloc_cnt, 1)); \
> > + rte_atomic64_add_return(ena_alloc_cnt, 1));\
> > mz = rte_memzone_reserve_aligned(z_name, size, \
> > node, RTE_MEMZONE_IOVA_CONTIG, alignment); \
> > mem_handle = mz; \
> > diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
> > index 5d107775f4..0780e2fee2 100644
> > --- a/drivers/net/ena/ena_ethdev.c
> > +++ b/drivers/net/ena/ena_ethdev.c
> > @@ -83,11 +83,15 @@ struct ena_stats {
> > /* Device arguments */
> > #define ENA_DEVARG_LARGE_LLQ_HDR "large_llq_hdr"
> >
> > +#define ENA_MZ_SHARED_DATA "ena_shared_data"
> > +
> > /*
> > * Each rte_memzone should have unique name.
> > * To satisfy it, count number of allocation and add it to name.
> > */
> > -rte_atomic64_t ena_alloc_cnt;
> > +rte_atomic64_t *ena_alloc_cnt;
> > +
> > +struct ena_shared_data *ena
Re: [dpdk-dev] [PATCH v3 17/22] net/ena: support SMP for mz alloc counter
On Sun, May 09, 2021 at 02:41:18PM +0100, Ferruh Yigit wrote:
> On 5/7/2021 6:18 PM, Stanislaw Kardach wrote:
> > On Fri, May 07, 2021 at 05:48:50PM +0100, Ferruh Yigit wrote:
> >> On 5/6/2021 3:25 PM, Michal Krawczyk wrote:
> >>> From: Stanislaw Kardach
> >>>
> >>> Introduce a memory area for ENA driver shared between all the processes
> >>> of a same prefix (memzone backed).
> >>> Move the memzone allocation counter for ENA_MEM_ALLOC_COHERENT there so
> >>> that all processes may utilize it.
> >>
> >> Device private data is already shared between primary/secondary processes,
> >> why
> >> not using it, it is already there.
> > Please correct me if I'm wrong, the dev->data->dev_private is a
> > per-device space, whereas the memzone here is used as a shared memory
> > between all ena devices.
>
> Yes it is per-device, so instead of keeping the shared are pointer as global
> variable, it is possible to keep this pointer in the device private area, and
> initialize per device. This way shared area can be reached by both primary and
> secondary applications without additional check.
> I think this works better to store device related shared data, like RSS key.
>
> But I am not sure about 'ena_alloc_cnt', I am not clear what it is, it looks
> like intention is to make it accesible from all devices and all processes.
Come to think of it, I think we can completely eliminate this memzone.
ena_alloc_cnt is used for unique memzone name generation but same could
be achieved with port_id + per_device_counter.
Thanks for the suggestion, we'll re-think this patch.
>
>
> Btw, How this shared memory freed?
Since I think we can get by without it, this question becomes academic,
though interesting.
Short answer is can't be freed. The reason for that is in multi-process
mode the primary process may die while secondaries continue. It means the
daemon thread which handles FD passing will die and hence secondaries
cannot perform memory alloc/free.
So even using reference count to delay memzone free won't help us if the
primary is dead.
>
> > More precisely the memzone counter used here is required to wrap some of
> > the base ena code we are calling and may be called from the context of
> > any device. Given that memzone names have to be unique, I need this
> > counter to be unique too.
> > I believe similar thing is done in mlx5 driver
> > (mlx5_init_shared_data()). If there is a better way to register such a
> > shared segment that is going to be preserved until all processes
> > (primary and secondary) are closed I would be happy to rework this.
> >>
> >> Next patch sharing RSS key using this shared area, can you device private
> >> data
> >> so all devices can access it.
> > It is somewhat similar case. The default key there is generated once for
> > all devices and then used in each of them.
> >>
> >>>
> >>> Signed-off-by: Stanislaw Kardach
> >>> Reviewed-by: Michal Krawczyk
> >>> Reviewed-by: Igor Chauskin
> >>> Reviewed-by: Shay Agroskin
> >>> ---
> >>> drivers/net/ena/base/ena_plat_dpdk.h | 6 ++--
> >>> drivers/net/ena/ena_ethdev.c | 46 +++-
> >>> drivers/net/ena/ena_ethdev.h | 8 +
> >>> 3 files changed, 56 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/drivers/net/ena/base/ena_plat_dpdk.h
> >>> b/drivers/net/ena/base/ena_plat_dpdk.h
> >>> index 1d0454bebe..e17970361a 100644
> >>> --- a/drivers/net/ena/base/ena_plat_dpdk.h
> >>> +++ b/drivers/net/ena/base/ena_plat_dpdk.h
> >>> @@ -209,7 +209,7 @@ typedef struct {
> >>> * Each rte_memzone should have unique name.
> >>> * To satisfy it, count number of allocations and add it to name.
> >>> */
> >>> -extern rte_atomic64_t ena_alloc_cnt;
> >>> +extern rte_atomic64_t *ena_alloc_cnt;
> >>>
> >>> #define ENA_MEM_ALLOC_COHERENT_ALIGNED(
> >>>\
> >>> dmadev, size, virt, phys, mem_handle, alignment) \
> >>> @@ -219,7 +219,7 @@ extern rte_atomic64_t ena_alloc_cnt;
> >>> if (size > 0) {\
> >>> char z_name[RTE_MEMZONE_NAMESIZE]; \
> >>> snprintf(z_name, sizeof(z_name), "ena_alloc_%"PRIi64"",\
Re: [dpdk-dev] [PATCH v3 18/22] net/ena: move default RSS key to shared mem
On Thu, May 06, 2021 at 04:25:22PM +0200, Michal Krawczyk wrote:
> From: Stanislaw Kardach
>
> Make sure the same random generated RSS key is available to all ENA PMD
> instances in all processes.
>
> Signed-off-by: Stanislaw Kardach
> Reviewed-by: Michal Krawczyk
> Reviewed-by: Igor Chauskin
> Reviewed-by: Shay Agroskin
> ---
> drivers/net/ena/ena_ethdev.c | 16 +---
> drivers/net/ena/ena_ethdev.h | 1 +
> 2 files changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
> index 0780e2fee2..5c365e1ab5 100644
> --- a/drivers/net/ena/ena_ethdev.c
> +++ b/drivers/net/ena/ena_ethdev.c
> @@ -276,19 +276,9 @@ static const struct eth_dev_ops ena_dev_ops = {
>
> void ena_rss_key_fill(void *key, size_t size)
> {
> - static bool key_generated;
> - static uint8_t default_key[ENA_HASH_KEY_SIZE];
> - size_t i;
> -
> RTE_ASSERT(size <= ENA_HASH_KEY_SIZE);
>
> - if (!key_generated) {
> - for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
> - default_key[i] = rte_rand() & 0xff;
> - key_generated = true;
> - }
> -
> - rte_memcpy(key, default_key, size);
> + rte_memcpy(key, ena_shared_data->default_key, size);
> }
>
> static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
> @@ -1758,7 +1748,11 @@ static uint32_t ena_calc_max_io_queue_num(struct
> ena_com_dev *ena_dev,
>
> static void ena_prepare_shared_data(struct ena_shared_data *shared_data)
> {
> + size_t i;
> +
> memset(shared_data, 0, sizeof(*shared_data));
> + for (i = 0; i < ENA_HASH_KEY_SIZE; ++i)
> + shared_data->default_key[i] = rte_rand() & 0xff;
> }
>
> static int ena_shared_data_init(void)
> diff --git a/drivers/net/ena/ena_ethdev.h b/drivers/net/ena/ena_ethdev.h
> index e8858c6118..1f7383dce0 100644
> --- a/drivers/net/ena/ena_ethdev.h
> +++ b/drivers/net/ena/ena_ethdev.h
> @@ -209,6 +209,7 @@ struct ena_offloads {
>
> /* Holds data shared between all instances of ENA PMD. */
> struct ena_shared_data {
> + uint8_t default_key[ENA_HASH_KEY_SIZE];
Given Ferruh's comments on "[PATCH 17/22] net/ena: support SMP for mz
alloc counter" it is probably a better idea to have this default key
generated per-device and keep it in rte_eth_dev.data. This will allow to
eliminate the shared memory segment (freeing issues) and increase
entropy for the different devices.
> /* Each rte_memzone should have unique name.
>* To satisfy it, count number of allocation and add it to name.
>*/
> --
> 2.25.1
>
--
Best Regards,
Stanislaw Kardach
[dpdk-dev] [PATCH v2 0/3] Increase test compatibility with PA IOVA
While working on a RISC-V port, using a HiFive Unmatched (FU740) which does not have IOMMU (hence only RTE_IOVA_PA is available), I've noticed that some of the EAL tests are failing because of a totally different reason than the test itself. Namely the --no-huge flag and --iova-mode=pa can't be used together and EAL init fails warning about a lack of access to physical addresses. This patchset tries to cleanup the --no-huge usage so that it doesn't hide the real state of tests when RTE_IOVA_PA is used (i.e. on platforms without IOMMU). I'm proposing to skip the no-huge test for RTE_IOVA_PA environments as it is not supported by design as well as removing no-huge usage on Linux as it seems that it is used (along with --no-shconf) to increase the compatibility with FreeBSD. Please let me know if I'm missing a bigger picture with the --no-huge and --no-shconf usage on non-FreeBSD platforms. I'm not adding sta...@dpdk.org on purpose as this does not affect any current platform I'm aware of (at least in a production scenario). --- V2: - Fix checkpatch errors - Add affected platform in the cover letter. Stanislaw Kardach (3): test: disable no-huge test with PA IOVA test: disable no-huge where it's not necessary test: fix the -n unit test description app/test/test_eal_flags.c | 63 ++- 1 file changed, 42 insertions(+), 21 deletions(-) -- 2.27.0
