[PATCH v2] net/e1000: support launchtime feature
Enable the time-based scheduled Tx of packets based on the
RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP flag. The launchtime defines the
packet transmission time based on PTP clock at MAC layer, which should
be set to the advanced transmit descriptor.
Signed-off-by: Chuanyu Xue
---
change log:
v2:
- Add delay compensation for i210 NIC by setting tx offset register.
- Revise read_clock function.
drivers/net/e1000/base/e1000_regs.h | 1 +
drivers/net/e1000/e1000_ethdev.h| 14 +++
drivers/net/e1000/igb_ethdev.c | 63 -
drivers/net/e1000/igb_rxtx.c| 42 +++
4 files changed, 112 insertions(+), 8 deletions(-)
diff --git a/drivers/net/e1000/base/e1000_regs.h
b/drivers/net/e1000/base/e1000_regs.h
index d44de59c29..092d9d71e6 100644
--- a/drivers/net/e1000/base/e1000_regs.h
+++ b/drivers/net/e1000/base/e1000_regs.h
@@ -162,6 +162,7 @@
/* QAV Tx mode control register */
#define E1000_I210_TQAVCTRL0x3570
+#define E1000_I210_LAUNCH_OS0 0x3578
/* QAV Tx mode control register bitfields masks */
/* QAV enable */
diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h
index 718a9746ed..339ae1f4b6 100644
--- a/drivers/net/e1000/e1000_ethdev.h
+++ b/drivers/net/e1000/e1000_ethdev.h
@@ -382,6 +382,20 @@ extern struct igb_rss_filter_list igb_filter_rss_list;
TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem);
extern struct igb_flow_mem_list igb_flow_list;
+/*
+ * Macros to compensate the constant latency observed in i210 for launch time
+ *
+ * launch time = (offset_speed - offset_base + txtime) * 32
+ * offset_speed is speed dependent, set in E1000_I210_LAUNCH_OS0
+ */
+#define IGB_I210_TX_OFFSET_BASE0xffe0
+#define IGB_I210_TX_OFFSET_SPEED_100xc7a0
+#define IGB_I210_TX_OFFSET_SPEED_100 0x86e0
+#define IGB_I210_TX_OFFSET_SPEED_1000 0xbe00
+
+extern uint64_t igb_tx_timestamp_dynflag;
+extern int igb_tx_timestamp_dynfield_offset;
+
extern const struct rte_flow_ops igb_flow_ops;
/*
diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 8858f975f8..2262035710 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -223,6 +223,7 @@ static int igb_timesync_read_time(struct rte_eth_dev *dev,
struct timespec *timestamp);
static int igb_timesync_write_time(struct rte_eth_dev *dev,
const struct timespec *timestamp);
+static int eth_igb_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,
uint16_t queue_id);
static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,
@@ -313,6 +314,9 @@ static const struct rte_pci_id pci_id_igbvf_map[] = {
{ .vendor_id = 0, /* sentinel */ },
};
+uint64_t igb_tx_timestamp_dynflag;
+int igb_tx_timestamp_dynfield_offset = -1;
+
static const struct rte_eth_desc_lim rx_desc_lim = {
.nb_max = E1000_MAX_RING_DESC,
.nb_min = E1000_MIN_RING_DESC,
@@ -389,6 +393,7 @@ static const struct eth_dev_ops eth_igb_ops = {
.timesync_adjust_time = igb_timesync_adjust_time,
.timesync_read_time = igb_timesync_read_time,
.timesync_write_time = igb_timesync_write_time,
+ .read_clock = eth_igb_read_clock,
};
/*
@@ -1188,6 +1193,40 @@ eth_igb_rxtx_control(struct rte_eth_dev *dev,
E1000_WRITE_FLUSH(hw);
}
+
+static uint32_t igb_tx_offset(struct rte_eth_dev *dev)
+{
+ struct e1000_hw *hw =
+ E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+
+ uint16_t duplex, speed;
+ hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
+
+ uint32_t launch_os0 = E1000_READ_REG(hw, E1000_I210_LAUNCH_OS0);
+ if (hw->mac.type != e1000_i210) {
+ /* Set launch offset to base, no compensation */
+ launch_os0 |= IGB_I210_TX_OFFSET_BASE;
+ } else {
+ /* Set launch offset depend on link speeds */
+ switch (speed) {
+ case SPEED_10:
+ launch_os0 |= IGB_I210_TX_OFFSET_SPEED_10;
+ break;
+ case SPEED_100:
+ launch_os0 |= IGB_I210_TX_OFFSET_SPEED_100;
+ break;
+ case SPEED_1000:
+ launch_os0 |= IGB_I210_TX_OFFSET_SPEED_1000;
+ break;
+ default:
+ launch_os0 |= IGB_I210_TX_OFFSET_BASE;
+ break;
+ }
+ }
+
+ return launch_os0;
+}
+
static int
eth_igb_start(struct rte_eth_dev *dev)
{
@@ -1198,6 +1237,7 @@ eth_igb_start(struct rte_eth_dev *dev)
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
int ret, mask;
+
RE: [PATCH v6 1/2] net/iavf: fix Rx/Tx burst in multi-process
> -Original Message-
> From: Mingjin Ye
> Sent: Friday, December 29, 2023 6:11 PM
> To: dev@dpdk.org
> Cc: Yang, Qiming ; Ye, MingjinX
> ; sta...@dpdk.org; Wu, Jingjing
> ; Xing, Beilei
> Subject: [PATCH v6 1/2] net/iavf: fix Rx/Tx burst in multi-process
>
> In a multi-process environment, a secondary process operates on shared
> memory and changes the function pointer of the primary process, resulting
> in a crash when the primary process cannot find the function address during
> an Rx/Tx burst.
>
> Fixes: 5b3124a0a6ef ("net/iavf: support no polling when link down")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Mingjin Ye
> ---
> v2: Add fix for Rx burst.
> ---
> drivers/net/iavf/iavf.h | 42 +++-
> drivers/net/iavf/iavf_rxtx.c | 184 ++-
> drivers/net/iavf/iavf_rxtx.h | 8 ++
> 3 files changed, 205 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h index
> 10868f2c30..8db9f3d7cd 100644
> --- a/drivers/net/iavf/iavf.h
> +++ b/drivers/net/iavf/iavf.h
> @@ -313,6 +313,44 @@ struct iavf_devargs {
>
> struct iavf_security_ctx;
>
> +enum iavf_rx_burst_type {
> + IAVF_RX_BURST_DEFAULT,
> + IAVF_RX_BURST_FRXD,
> + IAVF_RX_BURST_BULK_ALLOC,
> + IAVF_RX_BURST_SCATTERED,
> + IAVF_RX_BURST_SFRXD,
> + IAVF_RX_BURST_VEC_SSE,
> + IAVF_RX_BURST_VEC_AVX2,
> + IAVF_RX_BURST_VEC_AVX2_OFFLOAD,
> + IAVF_RX_BURST_VEC_SSE_FRXD,
> + IAVF_RX_BURST_VEC_AVX2_FRXD,
> + IAVF_RX_BURST_VEC_AVX2_FRXD_OFFLOAD,
> + IAVF_RX_BURST_VEC_SSE_SCATTERED,
> + IAVF_RX_BURST_VEC_AVX2_SCATTERED,
> + IAVF_RX_BURST_VEC_AVX2_SCATTERED_OFFLOAD,
> + IAVF_RX_BURST_VEC_SSE_SFLEX_RXD,
> + IAVF_RX_BURST_VEC_AVX2_SFLEX_RXD,
> + IAVF_RX_BURST_VEC_AVX2_SFRXD_OFFLOAD,
> + IAVF_RX_BURST_VEC_AVX512,
> + IAVF_RX_BURST_VEC_AVX512_OFFLOAD,
> + IAVF_RX_BURST_VEC_AVX512_FRXD,
> + IAVF_RX_BURST_VEC_AVX512_FRXD_OFFLOAD,
> + IAVF_RX_BURST_VEC_AVX512_SCATTERED,
> + IAVF_RX_BURST_VEC_AVX512_SCATTERED_OFFLOAD,
> + IAVF_RX_BURST_VEC_AVX512_SFLEX_RXD,
> + IAVF_RX_BURST_VEC_AVX512_SFRXD_OFFLOAD,
What is SFLEX, SFRXD, SFRXD, FRXD, please make it clear by following a
consistent naming pattern.
Btw, you can consider removing BURST and VEC which didn't give any additional
information if you are looking for a short name.
> @@ -3809,42 +3886,64 @@ iavf_set_rx_function(struct rte_eth_dev *dev)
> }
> if (use_flex) {
> dev->rx_pkt_burst =
> iavf_recv_scattered_pkts_vec_flex_rxd;
> + rx_burst_type =
> IAVF_RX_BURST_VEC_SSE_SFLEX_RXD;
> if (use_avx2) {
> - if (check_ret == IAVF_VECTOR_PATH)
> + if (check_ret == IAVF_VECTOR_PATH)
> {
> dev->rx_pkt_burst =
>
> iavf_recv_scattered_pkts_vec_avx2_flex_rxd;
> - else
> + rx_burst_type =
> +
> IAVF_RX_BURST_VEC_AVX2_SFLEX_RXD;
As you already introduce the burst_type, its not necessary to set the function
pointer for each case.
Why not just
dev->rx_pkt_burst = rx_burst_ops[rx_burst_type] at last?
> +struct iavf_rx_burst_ops {
> + eth_rx_burst_t rx_pkt_burst;
> +};
Why create a wrapper here but not just use eth_rx_burst_t directly?
