[PATCH 00/10] add hairpin queue support
From: Beilei Xing This patchset adds hairpin queue support. It depends on the following two patch set: https://patches.dpdk.org/project/dpdk/cover/20230406074245.82991-1-beilei.x...@intel.com/ https://patches.dpdk.org/project/dpdk/cover/20230413094502.1714755-1-wenjing.q...@intel.com/ Beilei Xing (10): net/cpfl: refine structures net/cpfl: support hairpin queue capbility get common/idpf: support queue groups add/delete net/cpfl: add haipin queue group during vpotr init net/cpfl: support hairpin queue setup and release net/cpfl: support hairpin queue configuration net/cpfl: support hairpin queue start/stop net/cpfl: enable write back based on ITR expire net/cpfl: support peer ports get net/cpfl: support hairpin bind/unbind drivers/common/idpf/idpf_common_device.c | 75 ++ drivers/common/idpf/idpf_common_device.h | 4 + drivers/common/idpf/idpf_common_virtchnl.c | 138 +++- drivers/common/idpf/idpf_common_virtchnl.h | 18 + drivers/common/idpf/version.map| 6 + drivers/net/cpfl/cpfl_ethdev.c | 588 +-- drivers/net/cpfl/cpfl_ethdev.h | 33 +- drivers/net/cpfl/cpfl_rxtx.c | 807 +++-- drivers/net/cpfl/cpfl_rxtx.h | 67 ++ drivers/net/cpfl/cpfl_rxtx_vec_common.h| 21 +- 10 files changed, 1638 insertions(+), 119 deletions(-) -- 2.26.2
[PATCH 01/10] net/cpfl: refine structures
From: Beilei Xing
This patch refines some structures to support hairpin queue,
cpfl_rx_queue/cpfl_tx_queue/cpfl_vport.
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 85 +++-
drivers/net/cpfl/cpfl_ethdev.h | 6 +-
drivers/net/cpfl/cpfl_rxtx.c| 175 +---
drivers/net/cpfl/cpfl_rxtx.h| 8 ++
drivers/net/cpfl/cpfl_rxtx_vec_common.h | 17 +--
5 files changed, 196 insertions(+), 95 deletions(-)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 306b8ad769..4a507f05d5 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -124,7 +124,8 @@ static int
cpfl_dev_link_update(struct rte_eth_dev *dev,
__rte_unused int wait_to_complete)
{
- struct idpf_vport *vport = dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct rte_eth_link new_link;
unsigned int i;
@@ -156,7 +157,8 @@ cpfl_dev_link_update(struct rte_eth_dev *dev,
static int
cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
{
- struct idpf_vport *vport = dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct idpf_adapter *base = vport->adapter;
dev_info->max_rx_queues = base->caps.max_rx_q;
@@ -216,7 +218,8 @@ cpfl_dev_info_get(struct rte_eth_dev *dev, struct
rte_eth_dev_info *dev_info)
static int
cpfl_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
{
- struct idpf_vport *vport = dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
/* mtu setting is forbidden if port is start */
if (dev->data->dev_started) {
@@ -256,12 +259,12 @@ static uint64_t
cpfl_get_mbuf_alloc_failed_stats(struct rte_eth_dev *dev)
{
uint64_t mbuf_alloc_failed = 0;
- struct idpf_rx_queue *rxq;
+ struct cpfl_rx_queue *cpfl_rxq;
int i = 0;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
- rxq = dev->data->rx_queues[i];
- mbuf_alloc_failed +=
__atomic_load_n(&rxq->rx_stats.mbuf_alloc_failed,
+ cpfl_rxq = dev->data->rx_queues[i];
+ mbuf_alloc_failed +=
__atomic_load_n(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed,
__ATOMIC_RELAXED);
}
@@ -271,8 +274,8 @@ cpfl_get_mbuf_alloc_failed_stats(struct rte_eth_dev *dev)
static int
cpfl_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
{
- struct idpf_vport *vport =
- (struct idpf_vport *)dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct virtchnl2_vport_stats *pstats = NULL;
int ret;
@@ -305,20 +308,20 @@ cpfl_dev_stats_get(struct rte_eth_dev *dev, struct
rte_eth_stats *stats)
static void
cpfl_reset_mbuf_alloc_failed_stats(struct rte_eth_dev *dev)
{
- struct idpf_rx_queue *rxq;
+ struct cpfl_rx_queue *cpfl_rxq;
int i;
for (i = 0; i < dev->data->nb_rx_queues; i++) {
- rxq = dev->data->rx_queues[i];
- __atomic_store_n(&rxq->rx_stats.mbuf_alloc_failed, 0,
__ATOMIC_RELAXED);
+ cpfl_rxq = dev->data->rx_queues[i];
+ __atomic_store_n(&cpfl_rxq->base.rx_stats.mbuf_alloc_failed, 0,
__ATOMIC_RELAXED);
}
}
static int
cpfl_dev_stats_reset(struct rte_eth_dev *dev)
{
- struct idpf_vport *vport =
- (struct idpf_vport *)dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct virtchnl2_vport_stats *pstats = NULL;
int ret;
@@ -343,8 +346,8 @@ static int cpfl_dev_xstats_reset(struct rte_eth_dev *dev)
static int cpfl_dev_xstats_get(struct rte_eth_dev *dev,
struct rte_eth_xstat *xstats, unsigned int n)
{
- struct idpf_vport *vport =
- (struct idpf_vport *)dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct virtchnl2_vport_stats *pstats = NULL;
unsigned int i;
int ret;
@@ -459,7 +462,8 @@ cpfl_rss_reta_update(struct rte_eth_dev *dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
{
- struct idpf_vport *vport = dev->data->dev_private;
+ struct cpfl_vport *cpfl_vport = dev->data->dev_private;
+ struct idpf_vport *vport = &cpfl_vport->base;
struct idpf_adapter *base = vport->adapter;
uin
[PATCH 02/10] net/cpfl: support hairpin queue capbility get
From: Beilei Xing
This patch adds hairpin_cap_get ops support.
Signed-off-by: Xiao Wang
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 13 +
drivers/net/cpfl/cpfl_rxtx.h | 4
2 files changed, 17 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 4a507f05d5..114fc18f5f 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -154,6 +154,18 @@ cpfl_dev_link_update(struct rte_eth_dev *dev,
return rte_eth_linkstatus_set(dev, &new_link);
}
+static int
+cpfl_hairpin_cap_get(__rte_unused struct rte_eth_dev *dev,
+struct rte_eth_hairpin_cap *cap)
+{
+ cap->max_nb_queues = CPFL_MAX_P2P_NB_QUEUES;
+ cap->max_rx_2_tx = CPFL_MAX_HAIRPINQ_RX_2_TX;
+ cap->max_tx_2_rx = CPFL_MAX_HAIRPINQ_TX_2_RX;
+ cap->max_nb_desc = CPFL_MAX_HAIRPINQ_NB_DESC;
+
+ return 0;
+}
+
static int
cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
{
@@ -889,6 +901,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {
.xstats_get = cpfl_dev_xstats_get,
.xstats_get_names = cpfl_dev_xstats_get_names,
.xstats_reset = cpfl_dev_xstats_reset,
+ .hairpin_cap_get= cpfl_hairpin_cap_get,
};
static int
diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h
index bfb9ad97bd..b2b3537d10 100644
--- a/drivers/net/cpfl/cpfl_rxtx.h
+++ b/drivers/net/cpfl/cpfl_rxtx.h
@@ -13,6 +13,10 @@
#define CPFL_MIN_RING_DESC 32
#define CPFL_MAX_RING_DESC 4096
#define CPFL_DMA_MEM_ALIGN 4096
+#define CPFL_MAX_HAIRPINQ_RX_2_TX 1
+#define CPFL_MAX_HAIRPINQ_TX_2_RX 1
+#define CPFL_MAX_HAIRPINQ_NB_DESC 1024
+#define CPFL_MAX_P2P_NB_QUEUES 16
/* Base address of the HW descriptor ring should be 128B aligned. */
#define CPFL_RING_BASE_ALIGN 128
--
2.26.2
[PATCH 03/10] common/idpf: support queue groups add/delete
From: Beilei Xing
This patch adds queue group add/delete virtual channel support.
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/common/idpf/idpf_common_virtchnl.c | 66 ++
drivers/common/idpf/idpf_common_virtchnl.h | 9 +++
drivers/common/idpf/version.map| 2 +
3 files changed, 77 insertions(+)
diff --git a/drivers/common/idpf/idpf_common_virtchnl.c
b/drivers/common/idpf/idpf_common_virtchnl.c
index a4e129062e..76a658bb26 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.c
+++ b/drivers/common/idpf/idpf_common_virtchnl.c
@@ -359,6 +359,72 @@ idpf_vc_vport_destroy(struct idpf_vport *vport)
return err;
}
+int
+idpf_vc_queue_grps_add(struct idpf_vport *vport,
+ struct virtchnl2_add_queue_groups *ptp_queue_grps_info,
+ uint8_t *ptp_queue_grps_out)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct idpf_cmd_info args;
+ int size, qg_info_size;
+ int err = -1;
+
+ size = sizeof(*ptp_queue_grps_info) +
+ (ptp_queue_grps_info->qg_info.num_queue_groups - 1) *
+ sizeof(struct virtchnl2_queue_group_info);
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_ADD_QUEUE_GROUPS;
+ args.in_args = (uint8_t *)ptp_queue_grps_info;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ if (err != 0) {
+ DRV_LOG(ERR,
+ "Failed to execute command of
VIRTCHNL2_OP_ADD_QUEUE_GROUPS");
+ return err;
+ }
+
+ rte_memcpy(ptp_queue_grps_out, args.out_buffer, IDPF_DFLT_MBX_BUF_SIZE);
+ return 0;
+}
+
+int idpf_vc_queue_grps_del(struct idpf_vport *vport,
+ uint16_t num_q_grps,
+ struct virtchnl2_queue_group_id *qg_ids)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_delete_queue_groups *vc_del_q_grps;
+ struct idpf_cmd_info args;
+ int size;
+ int err;
+
+ size = sizeof(*vc_del_q_grps) +
+ (num_q_grps - 1) * sizeof(struct virtchnl2_queue_group_id);
+ vc_del_q_grps = rte_zmalloc("vc_del_q_grps", size, 0);
+
+ vc_del_q_grps->vport_id = vport->vport_id;
+ vc_del_q_grps->num_queue_groups = num_q_grps;
+ memcpy(vc_del_q_grps->qg_ids, qg_ids,
+ num_q_grps * sizeof(struct virtchnl2_queue_group_id));
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_DEL_QUEUE_GROUPS;
+ args.in_args = (uint8_t *)vc_del_q_grps;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ if (err != 0)
+ DRV_LOG(ERR, "Failed to execute command of
VIRTCHNL2_OP_DEL_QUEUE_GROUPS");
+
+ rte_free(vc_del_q_grps);
+ return err;
+}
+
int
idpf_vc_rss_key_set(struct idpf_vport *vport)
{
diff --git a/drivers/common/idpf/idpf_common_virtchnl.h
b/drivers/common/idpf/idpf_common_virtchnl.h
index d479d93c8e..bf1d014c8d 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.h
+++ b/drivers/common/idpf/idpf_common_virtchnl.h
@@ -64,4 +64,13 @@ int idpf_vc_ctlq_recv(struct idpf_ctlq_info *cq, u16
*num_q_msg,
__rte_internal
int idpf_vc_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
u16 *buff_count, struct idpf_dma_mem **buffs);
+__rte_internal
+int idpf_vc_queue_grps_del(struct idpf_vport *vport,
+ uint16_t num_q_grps,
+ struct virtchnl2_queue_group_id *qg_ids);
+__rte_internal
+int
+idpf_vc_queue_grps_add(struct idpf_vport *vport,
+ struct virtchnl2_add_queue_groups *ptp_queue_grps_info,
+ uint8_t *ptp_queue_grps_out);
#endif /* _IDPF_COMMON_VIRTCHNL_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 7076759024..aa67f7ee27 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -48,6 +48,8 @@ INTERNAL {
idpf_vc_irq_map_unmap_config;
idpf_vc_one_msg_read;
idpf_vc_ptype_info_query;
+ idpf_vc_queue_grps_add;
+ idpf_vc_queue_grps_del;
idpf_vc_queue_switch;
idpf_vc_queues_ena_dis;
idpf_vc_rss_hash_get;
--
2.26.2
[PATCH 04/10] net/cpfl: add haipin queue group during vpotr init
From: Beilei Xing
This patch adds haipin queue group during vpotr init.
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 125 +
drivers/net/cpfl/cpfl_ethdev.h | 17 +
drivers/net/cpfl/cpfl_rxtx.h | 4 ++
3 files changed, 146 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 114fc18f5f..ad5ddebd3a 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -856,6 +856,20 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
return 0;
}
+static int
+cpfl_p2p_queue_grps_del(struct idpf_vport *vport)
+{
+ struct virtchnl2_queue_group_id qg_ids[CPFL_P2P_NB_QUEUE_GRPS] = {0};
+ int ret = 0;
+
+ qg_ids[0].queue_group_id = CPFL_P2P_QUEUE_GRP_ID;
+ qg_ids[0].queue_group_type = VIRTCHNL2_QUEUE_GROUP_P2P;
+ ret = idpf_vc_queue_grps_del(vport, CPFL_P2P_NB_QUEUE_GRPS, qg_ids);
+ if (ret)
+ PMD_DRV_LOG(ERR, "Failed to delete p2p queue groups");
+ return ret;
+}
+
static int
cpfl_dev_close(struct rte_eth_dev *dev)
{
@@ -864,6 +878,9 @@ cpfl_dev_close(struct rte_eth_dev *dev)
struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);
cpfl_dev_stop(dev);
+
+ cpfl_p2p_queue_grps_del(vport);
+
idpf_vport_deinit(vport);
adapter->cur_vports &= ~RTE_BIT32(vport->devarg_id);
@@ -1350,6 +1367,96 @@ cpfl_vport_idx_alloc(struct cpfl_adapter_ext *adapter)
return vport_idx;
}
+static int
+cpfl_p2p_q_grps_add(struct idpf_vport *vport,
+ struct virtchnl2_add_queue_groups *p2p_queue_grps_info,
+ uint8_t *p2p_q_vc_out_info)
+{
+ int ret;
+
+ p2p_queue_grps_info->vport_id = vport->vport_id;
+ p2p_queue_grps_info->qg_info.num_queue_groups = CPFL_P2P_NB_QUEUE_GRPS;
+ p2p_queue_grps_info->qg_info.groups[0].num_rx_q =
CPFL_MAX_P2P_NB_QUEUES;
+ p2p_queue_grps_info->qg_info.groups[0].num_rx_bufq =
CPFL_P2P_NB_RX_BUFQ;
+ p2p_queue_grps_info->qg_info.groups[0].num_tx_q =
CPFL_MAX_P2P_NB_QUEUES;
+ p2p_queue_grps_info->qg_info.groups[0].num_tx_complq =
CPFL_P2P_NB_TX_COMPLQ;
+ p2p_queue_grps_info->qg_info.groups[0].qg_id.queue_group_id =
CPFL_P2P_QUEUE_GRP_ID;
+ p2p_queue_grps_info->qg_info.groups[0].qg_id.queue_group_type =
VIRTCHNL2_QUEUE_GROUP_P2P;
+ p2p_queue_grps_info->qg_info.groups[0].rx_q_grp_info.rss_lut_size = 0;
+ p2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.tx_tc = 0;
+ p2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.priority = 0;
+ p2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.is_sp = 0;
+ p2p_queue_grps_info->qg_info.groups[0].tx_q_grp_info.pir_weight = 0;
+
+ ret = idpf_vc_queue_grps_add(vport, p2p_queue_grps_info,
p2p_q_vc_out_info);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Failed to add p2p queue groups.");
+ return ret;
+ }
+
+ return ret;
+}
+
+static int
+cpfl_p2p_queue_info_init(struct cpfl_vport *cpfl_vport,
+struct virtchnl2_add_queue_groups *p2p_q_vc_out_info)
+{
+ struct p2p_queue_chunks_info *p2p_q_chunks_info =
&cpfl_vport->p2p_q_chunks_info;
+ struct virtchnl2_queue_reg_chunks *vc_chunks_out;
+ int i, type;
+
+ if (p2p_q_vc_out_info->qg_info.groups[0].qg_id.queue_group_type !=
+ VIRTCHNL2_QUEUE_GROUP_P2P) {
+ PMD_DRV_LOG(ERR, "Add queue group response mismatch.");
+ return -EINVAL;
+ }
+
+ vc_chunks_out = &p2p_q_vc_out_info->qg_info.groups[0].chunks;
+
+ for (i = 0; i < vc_chunks_out->num_chunks; i++) {
+ type = vc_chunks_out->chunks[i].type;
+ switch (type) {
+ case VIRTCHNL2_QUEUE_TYPE_TX:
+ p2p_q_chunks_info->tx_start_qid =
+ vc_chunks_out->chunks[i].start_queue_id;
+ p2p_q_chunks_info->tx_qtail_start =
+ vc_chunks_out->chunks[i].qtail_reg_start;
+ p2p_q_chunks_info->tx_qtail_spacing =
+ vc_chunks_out->chunks[i].qtail_reg_spacing;
+ break;
+ case VIRTCHNL2_QUEUE_TYPE_RX:
+ p2p_q_chunks_info->rx_start_qid =
+ vc_chunks_out->chunks[i].start_queue_id;
+ p2p_q_chunks_info->rx_qtail_start =
+ vc_chunks_out->chunks[i].qtail_reg_start;
+ p2p_q_chunks_info->rx_qtail_spacing =
+ vc_chunks_out->chunks[i].qtail_reg_spacing;
+ break;
+ case VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION:
+ p2p_q_chunks_info->tx_compl_start_qid =
+ vc_chunks_out->chunks[i].start_queue_id;
+ p2p
[PATCH 05/10] net/cpfl: support hairpin queue setup and release
From: Beilei Xing
Support hairpin Rx/Tx queue setup and release.
Signed-off-by: Xiao Wang
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 6 +
drivers/net/cpfl/cpfl_ethdev.h | 10 +
drivers/net/cpfl/cpfl_rxtx.c| 373 +++-
drivers/net/cpfl/cpfl_rxtx.h| 28 ++
drivers/net/cpfl/cpfl_rxtx_vec_common.h | 4 +
5 files changed, 420 insertions(+), 1 deletion(-)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index ad5ddebd3a..d3300f17cc 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -878,6 +878,10 @@ cpfl_dev_close(struct rte_eth_dev *dev)
struct cpfl_adapter_ext *adapter = CPFL_ADAPTER_TO_EXT(vport->adapter);
cpfl_dev_stop(dev);
+ if (cpfl_vport->p2p_mp) {
+ rte_mempool_free(cpfl_vport->p2p_mp);
+ cpfl_vport->p2p_mp = NULL;
+ }
cpfl_p2p_queue_grps_del(vport);
@@ -919,6 +923,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {
.xstats_get_names = cpfl_dev_xstats_get_names,
.xstats_reset = cpfl_dev_xstats_reset,
.hairpin_cap_get= cpfl_hairpin_cap_get,
+ .rx_hairpin_queue_setup = cpfl_rx_hairpin_queue_setup,
+ .tx_hairpin_queue_setup = cpfl_tx_hairpin_queue_setup,
};
static int
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 5e2e7a1bfb..2cc8790da0 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -88,6 +88,16 @@ struct p2p_queue_chunks_info {
struct cpfl_vport {
struct idpf_vport base;
struct p2p_queue_chunks_info p2p_q_chunks_info;
+
+ struct rte_mempool *p2p_mp;
+
+ uint16_t nb_data_rxq;
+ uint16_t nb_data_txq;
+ uint16_t nb_p2p_rxq;
+ uint16_t nb_p2p_txq;
+
+ struct idpf_rx_queue *p2p_rx_bufq;
+ struct idpf_tx_queue *p2p_tx_complq;
};
struct cpfl_adapter_ext {
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index a441e2ffbe..64ed331a6d 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -10,6 +10,79 @@
#include "cpfl_rxtx.h"
#include "cpfl_rxtx_vec_common.h"
+uint16_t
+cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset)
+{
+ return start_qid + offset;
+}
+
+uint64_t
+cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t tail_spacing)
+{
+ return tail_start + offset * tail_spacing;
+}
+
+static inline void
+cpfl_tx_hairpin_descq_reset(struct idpf_tx_queue *txq)
+{
+ uint32_t i, size;
+
+ if (!txq) {
+ PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
+ return;
+ }
+
+ size = txq->nb_tx_desc * CPFL_P2P_DESC_LEN;
+ for (i = 0; i < size; i++)
+ ((volatile char *)txq->desc_ring)[i] = 0;
+}
+
+static inline void
+cpfl_tx_hairpin_complq_reset(struct idpf_tx_queue *cq)
+{
+ uint32_t i, size;
+
+ if (!cq) {
+ PMD_DRV_LOG(DEBUG, "Pointer to complq is NULL");
+ return;
+ }
+
+ size = cq->nb_tx_desc * CPFL_P2P_DESC_LEN;
+ for (i = 0; i < size; i++)
+ ((volatile char *)cq->compl_ring)[i] = 0;
+}
+
+static inline void
+cpfl_rx_hairpin_descq_reset(struct idpf_rx_queue *rxq)
+{
+ uint16_t len;
+ uint32_t i;
+
+ if (!rxq)
+ return;
+
+ len = rxq->nb_rx_desc;
+ for (i = 0; i < len * CPFL_P2P_DESC_LEN; i++)
+ ((volatile char *)rxq->rx_ring)[i] = 0;
+}
+
+static inline void
+cpfl_rx_hairpin_bufq_reset(struct idpf_rx_queue *rxbq)
+{
+ uint16_t len;
+ uint32_t i;
+
+ if (!rxbq)
+ return;
+
+ len = rxbq->nb_rx_desc;
+ for (i = 0; i < len * CPFL_P2P_DESC_LEN; i++)
+ ((volatile char *)rxbq->rx_ring)[i] = 0;
+
+ rxbq->bufq1 = NULL;
+ rxbq->bufq2 = NULL;
+}
+
static uint64_t
cpfl_rx_offload_convert(uint64_t offload)
{
@@ -233,7 +306,10 @@ cpfl_rx_queue_release(void *rxq)
/* Split queue */
if (!q->adapter->is_rx_singleq) {
- if (q->bufq2)
+ /* the mz is shared between Tx/Rx hairpin, let Rx_release
+* free the buf, q->bufq1->mz and q->mz.
+*/
+ if (!cpfl_rxq->hairpin_info.hairpin_q && q->bufq2)
cpfl_rx_split_bufq_release(q->bufq2);
if (q->bufq1)
@@ -384,6 +460,7 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t
queue_idx,
}
}
+ cpfl_vport->nb_data_rxq++;
rxq->q_set = true;
dev->data->rx_queues[queue_idx] = cpfl_rxq;
@@ -547,6 +624,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t
queue_idx,
txq->qtx_tail = hw->hw_addr + (vport->chunks_info.tx_qtail_start +
queue_idx * vport->chunk
[PATCH 06/10] net/cpfl: support hairpin queue configuration
From: Beilei Xing
This patch supports Rx/Tx hairpin queue configuration.
Signed-off-by: Xiao Wang
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/common/idpf/idpf_common_virtchnl.c | 70 +++
drivers/common/idpf/idpf_common_virtchnl.h | 6 +
drivers/common/idpf/version.map| 2 +
drivers/net/cpfl/cpfl_ethdev.c | 136 -
drivers/net/cpfl/cpfl_rxtx.c | 80
drivers/net/cpfl/cpfl_rxtx.h | 7 ++
6 files changed, 297 insertions(+), 4 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_virtchnl.c
b/drivers/common/idpf/idpf_common_virtchnl.c
index 76a658bb26..50cd43a8dd 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.c
+++ b/drivers/common/idpf/idpf_common_virtchnl.c
@@ -1050,6 +1050,41 @@ idpf_vc_rxq_config(struct idpf_vport *vport, struct
idpf_rx_queue *rxq)
return err;
}
+int idpf_vc_rxq_config_by_info(struct idpf_vport *vport, struct
virtchnl2_rxq_info *rxq_info,
+ uint16_t num_qs)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_config_rx_queues *vc_rxqs = NULL;
+ struct idpf_cmd_info args;
+ int size, err, i;
+
+ size = sizeof(*vc_rxqs) + (num_qs - 1) *
+ sizeof(struct virtchnl2_rxq_info);
+ vc_rxqs = rte_zmalloc("cfg_rxqs", size, 0);
+ if (vc_rxqs == NULL) {
+ DRV_LOG(ERR, "Failed to allocate virtchnl2_config_rx_queues");
+ err = -ENOMEM;
+ return err;
+ }
+ vc_rxqs->vport_id = vport->vport_id;
+ vc_rxqs->num_qinfo = num_qs;
+ memcpy(vc_rxqs->qinfo, rxq_info, num_qs * sizeof(struct
virtchnl2_rxq_info));
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_CONFIG_RX_QUEUES;
+ args.in_args = (uint8_t *)vc_rxqs;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ rte_free(vc_rxqs);
+ if (err != 0)
+ DRV_LOG(ERR, "Failed to execute command of
VIRTCHNL2_OP_CONFIG_RX_QUEUES");
+
+ return err;
+}
+
int
idpf_vc_txq_config(struct idpf_vport *vport, struct idpf_tx_queue *txq)
{
@@ -1121,6 +1156,41 @@ idpf_vc_txq_config(struct idpf_vport *vport, struct
idpf_tx_queue *txq)
return err;
}
+int
+idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct virtchnl2_txq_info
*txq_info,
+ uint16_t num_qs)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_config_tx_queues *vc_txqs = NULL;
+ struct idpf_cmd_info args;
+ int size, err;
+
+ size = sizeof(*vc_txqs) + (num_qs - 1) * sizeof(struct
virtchnl2_txq_info);
+ vc_txqs = rte_zmalloc("cfg_txqs", size, 0);
+ if (vc_txqs == NULL) {
+ DRV_LOG(ERR, "Failed to allocate virtchnl2_config_tx_queues");
+ err = -ENOMEM;
+ return err;
+ }
+ vc_txqs->vport_id = vport->vport_id;
+ vc_txqs->num_qinfo = num_qs;
+ memcpy(vc_txqs->qinfo, txq_info, num_qs * sizeof(struct
virtchnl2_txq_info));
+
+ memset(&args, 0, sizeof(args));
+ args.ops = VIRTCHNL2_OP_CONFIG_TX_QUEUES;
+ args.in_args = (uint8_t *)vc_txqs;
+ args.in_args_size = size;
+ args.out_buffer = adapter->mbx_resp;
+ args.out_size = IDPF_DFLT_MBX_BUF_SIZE;
+
+ err = idpf_vc_cmd_execute(adapter, &args);
+ rte_free(vc_txqs);
+ if (err != 0)
+ DRV_LOG(ERR, "Failed to execute command of
VIRTCHNL2_OP_CONFIG_TX_QUEUES");
+
+ return err;
+}
+
int
idpf_vc_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
struct idpf_ctlq_msg *q_msg)
diff --git a/drivers/common/idpf/idpf_common_virtchnl.h
b/drivers/common/idpf/idpf_common_virtchnl.h
index bf1d014c8d..277235ba7d 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.h
+++ b/drivers/common/idpf/idpf_common_virtchnl.h
@@ -65,6 +65,12 @@ __rte_internal
int idpf_vc_ctlq_post_rx_buffs(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
u16 *buff_count, struct idpf_dma_mem **buffs);
__rte_internal
+int idpf_vc_rxq_config_by_info(struct idpf_vport *vport, struct
virtchnl2_rxq_info *rxq_info,
+ uint16_t num_qs);
+__rte_internal
+int idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct
virtchnl2_txq_info *txq_info,
+ uint16_t num_qs);
+__rte_internal
int idpf_vc_queue_grps_del(struct idpf_vport *vport,
uint16_t num_q_grps,
struct virtchnl2_queue_group_id *qg_ids);
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index aa67f7ee27..a339a4bf8e 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -59,8 +59,10 @@ INTERNAL {
idpf_
[PATCH 07/10] net/cpfl: support hairpin queue start/stop
From: Beilei Xing
This patch supports Rx/Tx hairpin queue start/stop.
Signed-off-by: Xiao Wang
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/common/idpf/idpf_common_virtchnl.c | 2 +-
drivers/common/idpf/idpf_common_virtchnl.h | 3 +
drivers/common/idpf/version.map| 1 +
drivers/net/cpfl/cpfl_ethdev.c | 39 ++
drivers/net/cpfl/cpfl_rxtx.c | 153 ++---
drivers/net/cpfl/cpfl_rxtx.h | 14 ++
6 files changed, 193 insertions(+), 19 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_virtchnl.c
b/drivers/common/idpf/idpf_common_virtchnl.c
index 50cd43a8dd..20a5bc085d 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.c
+++ b/drivers/common/idpf/idpf_common_virtchnl.c
@@ -733,7 +733,7 @@ idpf_vc_vectors_dealloc(struct idpf_vport *vport)
return err;
}
-static int
+int
idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,
uint32_t type, bool on)
{
diff --git a/drivers/common/idpf/idpf_common_virtchnl.h
b/drivers/common/idpf/idpf_common_virtchnl.h
index 277235ba7d..18db6cd8c8 100644
--- a/drivers/common/idpf/idpf_common_virtchnl.h
+++ b/drivers/common/idpf/idpf_common_virtchnl.h
@@ -71,6 +71,9 @@ __rte_internal
int idpf_vc_txq_config_by_info(struct idpf_vport *vport, struct
virtchnl2_txq_info *txq_info,
uint16_t num_qs);
__rte_internal
+int idpf_vc_ena_dis_one_queue(struct idpf_vport *vport, uint16_t qid,
+ uint32_t type, bool on);
+__rte_internal
int idpf_vc_queue_grps_del(struct idpf_vport *vport,
uint16_t num_q_grps,
struct virtchnl2_queue_group_id *qg_ids);
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index a339a4bf8e..0e87dba2ae 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -45,6 +45,7 @@ INTERNAL {
idpf_vc_cmd_execute;
idpf_vc_ctlq_post_rx_buffs;
idpf_vc_ctlq_recv;
+ idpf_vc_ena_dis_one_queue;
idpf_vc_irq_map_unmap_config;
idpf_vc_one_msg_read;
idpf_vc_ptype_info_query;
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 13edf2e706..f154c83f27 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -895,6 +895,45 @@ cpfl_start_queues(struct rte_eth_dev *dev)
}
}
+ /* For non-cross vport hairpin queues, enable Tx queue and Rx queue,
+* then enable Tx completion queue and Rx buffer queue.
+*/
+ for (i = 0; i < dev->data->nb_tx_queues; i++) {
+ cpfl_txq = dev->data->tx_queues[i];
+ if (cpfl_txq->hairpin_info.hairpin_q &&
!cpfl_txq->hairpin_info.manual_bind) {
+ err = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,
+i -
cpfl_vport->nb_data_txq,
+false, true);
+ if (err)
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin TX
queue %u on",
+ i);
+ else
+ cpfl_txq->base.q_started = true;
+ }
+ }
+
+ for (i = 0; i < dev->data->nb_rx_queues; i++) {
+ cpfl_rxq = dev->data->rx_queues[i];
+ if (cpfl_rxq->hairpin_info.hairpin_q &&
!cpfl_rxq->hairpin_info.manual_bind) {
+ err = cpfl_switch_hairpin_rxtx_queue(cpfl_vport,
+i -
cpfl_vport->nb_data_rxq,
+true, true);
+ if (err)
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin RX
queue %u on",
+ i);
+ else
+ cpfl_rxq->base.q_started = true;
+ }
+ }
+
+ if (tx_cmplq_flag == 1 && rx_bufq_flag == 1) {
+ err = cpfl_switch_hairpin_bufq_complq(cpfl_vport, true);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin Tx complq
and Rx bufq");
+ return err;
+ }
+ }
+
return err;
}
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index 040beb5bac..ed2d100c35 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -1010,6 +1010,83 @@ cpfl_hairpin_txq_config(struct idpf_vport *vport, struct
cpfl_tx_queue *cpfl_txq
return idpf_vc_txq_config_by_info(vport, txq_info, 1);
}
+int
+cpfl_switch_hairpin_bufq_complq(struct cpfl_vport *cpfl_vport, bool on)
+{
+ struct idpf_vport *vport = &cpfl_vport->base;
+ uint32_t type;
+ int err, q
[PATCH 08/10] net/cpfl: enable write back based on ITR expire
From: Beilei Xing
This patch enabls write back based on ITR expire
(WR_ON_ITR) for hairpin queue.
Signed-off-by: Mingxia Liu
Signed-off-by: Beilei Xing
---
drivers/common/idpf/idpf_common_device.c | 75
drivers/common/idpf/idpf_common_device.h | 4 ++
drivers/common/idpf/version.map | 1 +
drivers/net/cpfl/cpfl_ethdev.c | 13 +++-
4 files changed, 92 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_device.c
b/drivers/common/idpf/idpf_common_device.c
index 3b58bdd41e..86a4a54f9b 100644
--- a/drivers/common/idpf/idpf_common_device.c
+++ b/drivers/common/idpf/idpf_common_device.c
@@ -559,6 +559,81 @@ idpf_vport_irq_map_config(struct idpf_vport *vport,
uint16_t nb_rx_queues)
return ret;
}
+int
+idpf_vport_irq_map_config_by_qids(struct idpf_vport *vport, uint32_t *qids,
uint16_t nb_rx_queues)
+{
+ struct idpf_adapter *adapter = vport->adapter;
+ struct virtchnl2_queue_vector *qv_map;
+ struct idpf_hw *hw = &adapter->hw;
+ uint32_t dynctl_val, itrn_val;
+ uint32_t dynctl_reg_start;
+ uint32_t itrn_reg_start;
+ uint16_t i;
+ int ret;
+
+ qv_map = rte_zmalloc("qv_map",
+nb_rx_queues *
+sizeof(struct virtchnl2_queue_vector), 0);
+ if (qv_map == NULL) {
+ DRV_LOG(ERR, "Failed to allocate %d queue-vector map",
+ nb_rx_queues);
+ ret = -ENOMEM;
+ goto qv_map_alloc_err;
+ }
+
+ /* Rx interrupt disabled, Map interrupt only for writeback */
+
+ /* The capability flags adapter->caps.other_caps should be
+* compared with bit VIRTCHNL2_CAP_WB_ON_ITR here. The if
+* condition should be updated when the FW can return the
+* correct flag bits.
+*/
+ dynctl_reg_start =
+ vport->recv_vectors->vchunks.vchunks->dynctl_reg_start;
+ itrn_reg_start =
+ vport->recv_vectors->vchunks.vchunks->itrn_reg_start;
+ dynctl_val = IDPF_READ_REG(hw, dynctl_reg_start);
+ DRV_LOG(DEBUG, "Value of dynctl_reg_start is 0x%x", dynctl_val);
+ itrn_val = IDPF_READ_REG(hw, itrn_reg_start);
+ DRV_LOG(DEBUG, "Value of itrn_reg_start is 0x%x", itrn_val);
+ /* Force write-backs by setting WB_ON_ITR bit in DYN_CTL
+* register. WB_ON_ITR and INTENA are mutually exclusive
+* bits. Setting WB_ON_ITR bits means TX and RX Descs
+* are written back based on ITR expiration irrespective
+* of INTENA setting.
+*/
+ /* TBD: need to tune INTERVAL value for better performance. */
+ itrn_val = (itrn_val == 0) ? IDPF_DFLT_INTERVAL : itrn_val;
+ dynctl_val = VIRTCHNL2_ITR_IDX_0 <<
+PF_GLINT_DYN_CTL_ITR_INDX_S |
+PF_GLINT_DYN_CTL_WB_ON_ITR_M |
+itrn_val << PF_GLINT_DYN_CTL_INTERVAL_S;
+ IDPF_WRITE_REG(hw, dynctl_reg_start, dynctl_val);
+
+ for (i = 0; i < nb_rx_queues; i++) {
+ /* map all queues to the same vector */
+ qv_map[i].queue_id = qids[i];
+ qv_map[i].vector_id =
+ vport->recv_vectors->vchunks.vchunks->start_vector_id;
+ }
+ vport->qv_map = qv_map;
+
+ ret = idpf_vc_irq_map_unmap_config(vport, nb_rx_queues, true);
+ if (ret != 0) {
+ DRV_LOG(ERR, "config interrupt mapping failed");
+ goto config_irq_map_err;
+ }
+
+ return 0;
+
+config_irq_map_err:
+ rte_free(vport->qv_map);
+ vport->qv_map = NULL;
+
+qv_map_alloc_err:
+ return ret;
+}
+
int
idpf_vport_irq_unmap_config(struct idpf_vport *vport, uint16_t nb_rx_queues)
{
diff --git a/drivers/common/idpf/idpf_common_device.h
b/drivers/common/idpf/idpf_common_device.h
index 7cf2355bc9..1aa9d9516f 100644
--- a/drivers/common/idpf/idpf_common_device.h
+++ b/drivers/common/idpf/idpf_common_device.h
@@ -212,5 +212,9 @@ int idpf_vport_info_init(struct idpf_vport *vport,
struct virtchnl2_create_vport *vport_info);
__rte_internal
void idpf_vport_stats_update(struct virtchnl2_vport_stats *oes, struct
virtchnl2_vport_stats *nes);
+__rte_internal
+int idpf_vport_irq_map_config_by_qids(struct idpf_vport *vport,
+ uint32_t *qids,
+ uint16_t nb_rx_queues);
#endif /* _IDPF_COMMON_DEVICE_H_ */
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index 0e87dba2ae..e3a7ef0daa 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -74,6 +74,7 @@ INTERNAL {
idpf_vport_info_init;
idpf_vport_init;
idpf_vport_irq_map_config;
+ idpf_vport_irq_map_config_by_qids;
idpf_vport_irq_unmap_config;
idpf_vport_rss_config;
idpf_vport_stats_update;
diff --git a/drivers/net/cpfl/cpfl_
[PATCH 09/10] net/cpfl: support peer ports get
From: Beilei Xing
This patch supports get hairpin peer ports.
Signed-off-by: Xiao Wang
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 008686bfd4..52c4ab601f 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -1074,6 +1074,39 @@ cpfl_dev_close(struct rte_eth_dev *dev)
return 0;
}
+static int
+cpfl_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,
+ __rte_unused size_t len, uint32_t tx)
+{
+ struct cpfl_vport *cpfl_vport =
+ (struct cpfl_vport *)dev->data->dev_private;
+ struct idpf_tx_queue *txq;
+ struct idpf_rx_queue *rxq;
+ struct cpfl_tx_queue *cpfl_txq;
+ struct cpfl_rx_queue *cpfl_rxq;
+ int i, j;
+
+ if (tx > 0) {
+ for (i = cpfl_vport->nb_data_txq, j = 0; i <
dev->data->nb_tx_queues; i++, j++) {
+ txq = dev->data->tx_queues[i];
+ if (txq == NULL)
+ return -EINVAL;
+ cpfl_txq = (struct cpfl_tx_queue *)txq;
+ peer_ports[j] = cpfl_txq->hairpin_info.peer_rxp;
+ }
+ } else if (tx == 0) {
+ for (i = cpfl_vport->nb_data_rxq, j = 0; i <
dev->data->nb_rx_queues; i++, j++) {
+ rxq = dev->data->rx_queues[i];
+ if (rxq == NULL)
+ return -EINVAL;
+ cpfl_rxq = (struct cpfl_rx_queue *)rxq;
+ peer_ports[j] = cpfl_rxq->hairpin_info.peer_txp;
+ }
+ }
+
+ return j;
+}
+
static const struct eth_dev_ops cpfl_eth_dev_ops = {
.dev_configure = cpfl_dev_configure,
.dev_close = cpfl_dev_close,
@@ -1103,6 +1136,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = {
.hairpin_cap_get= cpfl_hairpin_cap_get,
.rx_hairpin_queue_setup = cpfl_rx_hairpin_queue_setup,
.tx_hairpin_queue_setup = cpfl_tx_hairpin_queue_setup,
+ .hairpin_get_peer_ports = cpfl_hairpin_get_peer_ports,
};
static int
--
2.26.2
[PATCH 10/10] net/cpfl: support hairpin bind/unbind
From: Beilei Xing
This patch supports hairpin_bind/unbind ops.
Signed-off-by: Xiao Wang
Signed-off-by: Beilei Xing
---
drivers/net/cpfl/cpfl_ethdev.c | 137 +
drivers/net/cpfl/cpfl_rxtx.c | 28 +++
drivers/net/cpfl/cpfl_rxtx.h | 2 +
3 files changed, 167 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 52c4ab601f..ddafc2f9e5 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -1107,6 +1107,141 @@ cpfl_hairpin_get_peer_ports(struct rte_eth_dev *dev,
uint16_t *peer_ports,
return j;
}
+static int
+cpfl_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port)
+{
+ struct cpfl_vport *cpfl_tx_vport = dev->data->dev_private;
+ struct idpf_vport *tx_vport = &cpfl_tx_vport->base;
+ struct cpfl_vport *cpfl_rx_vport;
+ struct cpfl_tx_queue *cpfl_txq;
+ struct cpfl_rx_queue *cpfl_rxq;
+ struct rte_eth_dev *peer_dev;
+ struct idpf_vport *rx_vport;
+ int err = 0;
+ int i;
+
+ err = cpfl_txq_hairpin_info_update(dev, rx_port);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to update Tx hairpin queue info.");
+ return err;
+ }
+
+ /* configure hairpin queues */
+ for (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {
+ cpfl_txq = dev->data->tx_queues[i];
+ err = cpfl_hairpin_txq_config(tx_vport, cpfl_txq);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to configure hairpin Tx queue
%u", i);
+ return err;
+ }
+ }
+
+ err = cpfl_hairpin_tx_complq_config(cpfl_tx_vport);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to config Tx completion queue");
+ return err;
+ }
+
+ peer_dev = &rte_eth_devices[rx_port];
+ cpfl_rx_vport = (struct cpfl_vport *)peer_dev->data->dev_private;
+ rx_vport = &cpfl_rx_vport->base;
+ cpfl_rxq_hairpin_mz_bind(peer_dev);
+
+ for (i = cpfl_rx_vport->nb_data_rxq; i < peer_dev->data->nb_rx_queues;
i++) {
+ cpfl_rxq = peer_dev->data->rx_queues[i];
+ err = cpfl_hairpin_rxq_config(rx_vport, cpfl_rxq);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to configure hairpin Rx queue
%u", i);
+ return err;
+ }
+ err = cpfl_rx_queue_init(peer_dev, i);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to init hairpin Rx queue %u", i);
+ return err;
+ }
+ }
+
+ err = cpfl_hairpin_rx_bufq_config(cpfl_rx_vport);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Fail to config Rx buffer queue");
+ return err;
+ }
+
+ /* enable hairpin queues */
+ for (i = cpfl_tx_vport->nb_data_txq; i < dev->data->nb_tx_queues; i++) {
+ cpfl_txq = dev->data->tx_queues[i];
+ err = cpfl_switch_hairpin_rxtx_queue(cpfl_tx_vport,
+i -
cpfl_tx_vport->nb_data_txq,
+false, true);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin TX queue %u
on",
+ i);
+ return err;
+ }
+ cpfl_txq->base.q_started = true;
+ }
+
+ err = cpfl_switch_hairpin_complq(cpfl_tx_vport, true);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin Tx complq");
+ return err;
+ }
+
+ for (i = cpfl_rx_vport->nb_data_rxq; i < peer_dev->data->nb_rx_queues;
i++) {
+ cpfl_rxq = peer_dev->data->rx_queues[i];
+ err = cpfl_switch_hairpin_rxtx_queue(cpfl_rx_vport,
+i -
cpfl_rx_vport->nb_data_rxq,
+true, true);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin RX queue %u
on",
+ i);
+ }
+ cpfl_rxq->base.q_started = true;
+ }
+
+ err = cpfl_switch_hairpin_bufq(cpfl_rx_vport, true);
+ if (err != 0) {
+ PMD_DRV_LOG(ERR, "Failed to switch hairpin Rx buffer queue");
+ return err;
+ }
+
+ return 0;
+}
+
+static int
+cpfl_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port)
+{
+ struct cpfl_vport *cpfl_tx_vport = dev->data->dev_private;
+ struct rte_eth_dev *peer_dev = &rte_eth_devices[rx_port];
+ struct cpfl_vport *cpfl_rx_vport = peer_dev->data->dev_private;
+ struct cpfl_tx_queue *cpfl_txq;
+ struct cpfl_rx_queue *cpfl_rxq;
+ int i;
+
+ /* disable hairpin queu
[PATCH v2 0/7] update idpf and cpfl timestamp
Add timestamp offload feature support for ACC. Using alarm to save main time to solve timestamp roll over issue. Ajust timestamp mbuf registering at dev start. Wenjing Qiao (7): common/idpf: fix 64b timestamp roll over issue net/idpf: save main time by alarm net/cpfl: save main time by alarm common/idpf: support timestamp offload feature for ACC common/idpf: add timestamp enable flag for rxq net/cpfl: register timestamp mbuf when starting dev net/idpf: register timestamp mbuf when starting dev config/meson.build | 3 + drivers/common/idpf/base/idpf_osdep.h | 48 + drivers/common/idpf/idpf_common_rxtx.c | 133 ++--- drivers/common/idpf/idpf_common_rxtx.h | 5 +- drivers/common/idpf/version.map| 4 + drivers/net/cpfl/cpfl_ethdev.c | 19 drivers/net/cpfl/cpfl_ethdev.h | 3 + drivers/net/cpfl/cpfl_rxtx.c | 2 + drivers/net/idpf/idpf_ethdev.c | 19 drivers/net/idpf/idpf_ethdev.h | 3 + drivers/net/idpf/idpf_rxtx.c | 3 + meson_options.txt | 2 + 12 files changed, 186 insertions(+), 58 deletions(-) -- 2.25.1
[PATCH v2 2/7] net/idpf: save main time by alarm
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
---
drivers/net/idpf/idpf_ethdev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index e02ec2ec5a..3f33ffbc78 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -761,6 +761,12 @@ idpf_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
{
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -810,6 +816,7 @@ static int
idpf_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -822,6 +829,11 @@ idpf_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
{
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
[PATCH v2 1/7] common/idpf: fix 64b timestamp roll over issue
Reading MTS register at first packet will cause timestamp
roll over issue. To support caculating 64b timestamp, need
an alarm to save master time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/idpf_common_rxtx.c | 108 -
drivers/common/idpf/idpf_common_rxtx.h | 3 +-
drivers/common/idpf/version.map| 1 +
3 files changed, 55 insertions(+), 57 deletions(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c
b/drivers/common/idpf/idpf_common_rxtx.c
index fc87e3e243..19bcb94077 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -4,6 +4,7 @@
#include
#include
+#include
#include "idpf_common_rxtx.h"
@@ -442,56 +443,23 @@ idpf_qc_split_rxq_mbufs_alloc(struct idpf_rx_queue *rxq)
return 0;
}
-#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 1
/* Helper function to convert a 32b nanoseconds timestamp to 64b. */
static inline uint64_t
-idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,
- uint32_t in_timestamp)
+idpf_tstamp_convert_32b_64b(uint64_t time_hw, uint32_t in_timestamp)
{
-#ifdef RTE_ARCH_X86_64
- struct idpf_hw *hw = &ad->hw;
const uint64_t mask = 0x;
- uint32_t hi, lo, lo2, delta;
+ const uint32_t half_overflow_duration = 0x1 << 31;
+ uint32_t delta;
uint64_t ns;
- if (flag != 0) {
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
- PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- /*
-* On typical system, the delta between lo and lo2 is ~1000ns,
-* so 1 seems a large-enough but not overly-big guard band.
-*/
- if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
- lo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- else
- lo2 = lo;
-
- if (lo2 < lo) {
- lo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);
- hi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);
- }
-
- ad->time_hw = ((uint64_t)hi << 32) | lo;
- }
-
- delta = (in_timestamp - (uint32_t)(ad->time_hw & mask));
- if (delta > (mask / 2)) {
- delta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);
- ns = ad->time_hw - delta;
+ delta = (in_timestamp - (uint32_t)(time_hw & mask));
+ if (delta > half_overflow_duration) {
+ delta = ((uint32_t)(time_hw & mask) - in_timestamp);
+ ns = time_hw - delta;
} else {
- ns = ad->time_hw + delta;
+ ns = time_hw + delta;
}
-
return ns;
-#else /* !RTE_ARCH_X86_64 */
- RTE_SET_USED(ad);
- RTE_SET_USED(flag);
- RTE_SET_USED(in_timestamp);
- return 0;
-#endif /* RTE_ARCH_X86_64 */
}
#define IDPF_RX_FLEX_DESC_ADV_STATUS0_XSUM_S \
@@ -659,9 +627,6 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf
**rx_pkts,
rx_desc_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rx_desc = &rx_desc_ring[rx_id];
@@ -720,10 +685,8 @@ idpf_dp_splitq_recv_pkts(void *rx_queue, struct rte_mbuf
**rx_pkts,
if (idpf_timestamp_dynflag > 0 &&
(rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* timestamp */
- ts_ns = idpf_tstamp_convert_32b_64b(ad,
-
rxq->hw_register_set,
+ ts_ns = idpf_tstamp_convert_32b_64b(ad->time_hw,
rte_le_to_cpu_32(rx_desc->ts_high));
- rxq->hw_register_set = 0;
*RTE_MBUF_DYNFIELD(rxm,
idpf_timestamp_dynfield_offset,
rte_mbuf_timestamp_t *) = ts_ns;
@@ -1077,9 +1040,6 @@ idpf_dp_singleq_recv_pkts(void *rx_queue, struct rte_mbuf
**rx_pkts,
rx_ring = rxq->rx_ring;
ptype_tbl = rxq->adapter->ptype_tbl;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0)
- rxq->hw_register_set = 1;
-
while (nb_rx < nb_pkts) {
rxdp = &rx_ring[rx_id];
rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
@@ -1142,10 +1102,8 @@ idpf_dp_
[PATCH v2 3/7] net/cpfl: save main time by alarm
Using alarm to save main time from registers every 1 second.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
---
drivers/net/cpfl/cpfl_ethdev.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index ede730fd50..82d8147494 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -767,6 +767,12 @@ cpfl_dev_start(struct rte_eth_dev *dev)
goto err_vec;
}
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
{
+ rte_eal_alarm_set(1000 * 1000,
+ &idpf_dev_read_time_hw,
+ (void *)base);
+ }
+
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
if (ret != 0) {
PMD_DRV_LOG(ERR, "Failed to allocate interrupt vectors");
@@ -816,6 +822,7 @@ static int
cpfl_dev_stop(struct rte_eth_dev *dev)
{
struct idpf_vport *vport = dev->data->dev_private;
+ struct idpf_adapter *base = vport->adapter;
if (vport->stopped == 1)
return 0;
@@ -828,6 +835,11 @@ cpfl_dev_stop(struct rte_eth_dev *dev)
idpf_vc_vectors_dealloc(vport);
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
{
+ rte_eal_alarm_cancel(idpf_dev_read_time_hw,
+base);
+ }
+
vport->stopped = 1;
return 0;
--
2.25.1
[PATCH v2 4/7] common/idpf: support timestamp offload feature for ACC
For ACC, getting main time from MTS registers by shared memory.
Notice: it is a workaround, and it will be removed after generic
solution are provided.
Signed-off-by: Wenjing Qiao
---
config/meson.build | 3 ++
drivers/common/idpf/base/idpf_osdep.h | 48 ++
drivers/common/idpf/idpf_common_rxtx.c | 30 +---
meson_options.txt | 2 ++
4 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/config/meson.build b/config/meson.build
index fa730a1b14..8d74f301b4 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -316,6 +316,9 @@ endif
if get_option('mbuf_refcnt_atomic')
dpdk_conf.set('RTE_MBUF_REFCNT_ATOMIC', true)
endif
+if get_option('enable_acc_timestamp')
+dpdk_conf.set('IDPF_ACC_TIMESTAMP', true)
+endif
dpdk_conf.set10('RTE_IOVA_IN_MBUF', get_option('enable_iova_as_pa'))
compile_time_cpuflags = []
diff --git a/drivers/common/idpf/base/idpf_osdep.h
b/drivers/common/idpf/base/idpf_osdep.h
index 99ae9cf60a..e634939a51 100644
--- a/drivers/common/idpf/base/idpf_osdep.h
+++ b/drivers/common/idpf/base/idpf_osdep.h
@@ -24,6 +24,13 @@
#include
#include
+#ifdef IDPF_ACC_TIMESTAMP
+#include
+#include
+#include
+#include
+#endif /* IDPF_ACC_TIMESTAMP */
+
#define INLINE inline
#define STATIC static
@@ -361,4 +368,45 @@ idpf_hweight32(u32 num)
#endif
+#ifdef IDPF_ACC_TIMESTAMP
+#define IDPF_ACC_TIMESYNC_BASE_ADDR 0x480D50
+#define IDPF_ACC_GLTSYN_TIME_H (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x1C)
+#define IDPF_ACC_GLTSYN_TIME_L (IDPF_ACC_TIMESYNC_BASE_ADDR + 0x10)
+
+inline uint32_t
+idpf_mmap_r32(uint64_t pa)
+{
+ int fd;
+ void *bp, *vp;
+ uint32_t rval = 0xdeadbeef;
+ uint32_t ps, ml, of;
+
+ fd = open("/dev/mem", (O_RDWR | O_SYNC));
+ if (fd == -1) {
+ perror("/dev/mem");
+ return -1;
+ }
+ ml = ps = getpagesize();
+ of = (uint32_t)pa & (ps - 1);
+ if (of + (sizeof(uint32_t) * 4) > ps)
+ ml *= 2;
+ bp = mmap(NULL, ml, (PROT_READ | PROT_WRITE), MAP_SHARED, fd, pa &
~(uint64_t)(ps - 1));
+ if (bp == MAP_FAILED) {
+ perror("mmap");
+ goto done;
+ }
+
+ vp = (char *)bp + of;
+
+ rval = *(volatile uint32_t *)vp;
+ if (munmap(bp, ml) == -1)
+ perror("munmap");
+done:
+ close(fd);
+
+ return rval;
+}
+
+#endif /* IDPF_ACC_TIMESTAMP */
+
#endif /* _IDPF_OSDEP_H_ */
diff --git a/drivers/common/idpf/idpf_common_rxtx.c
b/drivers/common/idpf/idpf_common_rxtx.c
index 19bcb94077..9c58f3fb11 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -1582,12 +1582,36 @@ idpf_qc_splitq_rx_vec_setup(struct idpf_rx_queue *rxq)
void
idpf_dev_read_time_hw(void *cb_arg)
{
-#ifdef RTE_ARCH_X86_64
struct idpf_adapter *ad = (struct idpf_adapter *)cb_arg;
uint32_t hi, lo, lo2;
int rc = 0;
+#ifndef IDPF_ACC_TIMESTAMP
struct idpf_hw *hw = &ad->hw;
+#endif /* !IDPF_ACC_TIMESTAMP */
+#ifdef IDPF_ACC_TIMESTAMP
+
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ DRV_LOG(DEBUG, "lo : %X,", lo);
+ DRV_LOG(DEBUG, "hi : %X,", hi);
+ /*
+* On typical system, the delta between lo and lo2 is ~1000ns,
+* so 1 seems a large-enough but not overly-big guard band.
+*/
+ if (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))
+ lo2 = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ else
+ lo2 = lo;
+
+ if (lo2 < lo) {
+ lo = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_L);
+ hi = idpf_mmap_r32(IDPF_ACC_GLTSYN_TIME_H);
+ }
+
+ ad->time_hw = ((uint64_t)hi << 32) | lo;
+
+#else /* !IDPF_ACC_TIMESTAMP */
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
IDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |
PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);
@@ -1608,9 +1632,7 @@ idpf_dev_read_time_hw(void *cb_arg)
}
ad->time_hw = ((uint64_t)hi << 32) | lo;
-#else /* !RTE_ARCH_X86_64 */
- ad->time_hw = 0;
-#endif /* RTE_ARCH_X86_64 */
+#endif /* IDPF_ACC_TIMESTAMP */
/* re-alarm watchdog */
rc = rte_eal_alarm_set(1000 * 1000, &idpf_dev_read_time_hw, cb_arg);
diff --git a/meson_options.txt b/meson_options.txt
index 82c8297065..31fc634aa0 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -52,3 +52,5 @@ option('tests', type: 'boolean', value: true, description:
'build unit tests')
option('use_hpet', type: 'boolean', value: false, description:
'use HPET timer in EAL')
+option('enable_acc_timestamp', type: 'boolean', value: false, description:
+ 'enable timestamp on ACC.')
--
2.25.1
[PATCH v2 5/7] common/idpf: add timestamp enable flag for rxq
A rxq can be configured with timestamp offload.
So, add timestamp enable flag for rxq.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
Suggested-by: Jingjing Wu
---
drivers/common/idpf/idpf_common_rxtx.c | 3 ++-
drivers/common/idpf/idpf_common_rxtx.h | 2 ++
drivers/common/idpf/version.map| 3 +++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/idpf_common_rxtx.c
b/drivers/common/idpf/idpf_common_rxtx.c
index 9c58f3fb11..7afe7afe3f 100644
--- a/drivers/common/idpf/idpf_common_rxtx.c
+++ b/drivers/common/idpf/idpf_common_rxtx.c
@@ -354,7 +354,7 @@ int
idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
{
int err;
- if ((rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP) != 0) {
+ if (!rxq->ts_enable && (rxq->offloads & IDPF_RX_OFFLOAD_TIMESTAMP)) {
/* Register mbuf field and flag for Rx timestamp */
err =
rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
&idpf_timestamp_dynflag);
@@ -363,6 +363,7 @@ idpf_qc_ts_mbuf_register(struct idpf_rx_queue *rxq)
"Cannot register mbuf field/flag for
timestamp");
return -EINVAL;
}
+ rxq->ts_enable = TRUE;
}
return 0;
}
diff --git a/drivers/common/idpf/idpf_common_rxtx.h
b/drivers/common/idpf/idpf_common_rxtx.h
index af1425eb3f..cb7f5a3ba8 100644
--- a/drivers/common/idpf/idpf_common_rxtx.h
+++ b/drivers/common/idpf/idpf_common_rxtx.h
@@ -142,6 +142,8 @@ struct idpf_rx_queue {
struct idpf_rx_queue *bufq2;
uint64_t offloads;
+
+ bool ts_enable; /* if timestamp is enabled */
};
struct idpf_tx_entry {
diff --git a/drivers/common/idpf/version.map b/drivers/common/idpf/version.map
index c67c554911..15b42b4d2e 100644
--- a/drivers/common/idpf/version.map
+++ b/drivers/common/idpf/version.map
@@ -69,5 +69,8 @@ INTERNAL {
idpf_vport_rss_config;
idpf_vport_stats_update;
+ idpf_timestamp_dynfield_offset;
+ idpf_timestamp_dynflag;
+
local: *;
};
--
2.25.1
[PATCH v2 6/7] net/cpfl: register timestamp mbuf when starting dev
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
Suggested-by: Jingjing Wu
---
drivers/net/cpfl/cpfl_ethdev.c | 7 +++
drivers/net/cpfl/cpfl_ethdev.h | 3 +++
drivers/net/cpfl/cpfl_rxtx.c | 2 ++
3 files changed, 12 insertions(+)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index 82d8147494..416273f567 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -771,6 +771,13 @@ cpfl_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret =
rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+
&idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for
timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 200dfcac02..eec253bc77 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -57,6 +57,9 @@
/* Device IDs */
#define IDPF_DEV_ID_CPF0x1453
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct cpfl_vport_param {
struct cpfl_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c
index de59b31b3d..cdb5b37da0 100644
--- a/drivers/net/cpfl/cpfl_rxtx.c
+++ b/drivers/net/cpfl/cpfl_rxtx.c
@@ -529,6 +529,8 @@ cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t
rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to register timestamp mbuf %u",
--
2.25.1
[PATCH v2 7/7] net/idpf: register timestamp mbuf when starting dev
Due to only support timestamp at port level, registering
timestamp mbuf should be at dev start stage.
Fixes: 8c6098afa075 ("common/idpf: add Rx/Tx data path")
Cc: sta...@dpdk.org
Signed-off-by: Wenjing Qiao
Suggested-by: Jingjing Wu
---
drivers/net/idpf/idpf_ethdev.c | 7 +++
drivers/net/idpf/idpf_ethdev.h | 3 +++
drivers/net/idpf/idpf_rxtx.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index 3f33ffbc78..7c43f51c25 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -765,6 +765,13 @@ idpf_dev_start(struct rte_eth_dev *dev)
rte_eal_alarm_set(1000 * 1000,
&idpf_dev_read_time_hw,
(void *)base);
+ /* Register mbuf field and flag for Rx timestamp */
+ ret =
rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,
+
&idpf_timestamp_dynflag);
+ if (ret != 0) {
+ PMD_DRV_LOG(ERR, "Cannot register mbuf field/flag for
timestamp");
+ return -EINVAL;
+ }
}
ret = idpf_vc_vectors_alloc(vport, req_vecs_num);
diff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h
index 3c2c932438..256e348710 100644
--- a/drivers/net/idpf/idpf_ethdev.h
+++ b/drivers/net/idpf/idpf_ethdev.h
@@ -55,6 +55,9 @@
#define IDPF_ALARM_INTERVAL5 /* us */
+extern int idpf_timestamp_dynfield_offset;
+extern uint64_t idpf_timestamp_dynflag;
+
struct idpf_vport_param {
struct idpf_adapter_ext *adapter;
uint16_t devarg_id; /* arg id from user */
diff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c
index 414f9a37f6..1aaf0142d2 100644
--- a/drivers/net/idpf/idpf_rxtx.c
+++ b/drivers/net/idpf/idpf_rxtx.c
@@ -529,6 +529,9 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t
rx_queue_id)
frame_size > rxq->rx_buf_len)
dev->data->scattered_rx = 1;
+ if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
+ rxq->ts_enable = TRUE;
+
err = idpf_qc_ts_mbuf_register(rxq);
if (err != 0) {
PMD_DRV_LOG(ERR, "fail to residter timestamp mbuf %u",
--
2.25.1
Re: [PATCH v5] enhance NUMA affinity heuristic
21/04/2023 04:34, You, KaisenX:
> From: Thomas Monjalon
> > 13/04/2023 02:56, You, KaisenX:
> > > From: You, KaisenX
> > > > From: Thomas Monjalon
> > > > >
> > > > > I'm not comfortable with this patch.
> > > > >
> > > > > First, there is no comment in the code which helps to understand the
> > logic.
> > > > > Second, I'm afraid changing the value of the per-core variable
> > > > > _socket_id may have an impact on some applications.
> > > > >
> > > Hi Thomas, I'm sorry to bother you again, but we can't think of a
> > > better solution for now, would you please give me some suggestion, and
> > then I will modify it accordingly.
> >
> > You need to better explain the logic
> > both in the commit message and in code comments.
> > When it will be done, it will be easier to have a discussion with other
> > maintainers and community experts.
> > Thank you
> >
> Thank you for your reply, I'll explain my patch in more detail next.
>
> When a DPDK application is started on only one numa node,
What do you mean by started on only one node?
> memory is allocated for only one socket.
> When interrupt threads use memory, memory may not be found
> on the socket where the interrupt thread is currently located,
Why interrupt thread is on a different socket?
> and memory has to be reallocated on the hugepage,
> this operation can lead to performance degradation.
>
> So my modification is in the function malloc_get_numa_socket to make sure
> that the first socket with memory can be returned.
>
> If you can accept my explanation and modification, I will send the V6
> version to improve the commit message and code comments.
>
> > > > Thank you for your reply.
> > > > First, about comments, I can submit a new patch to add comments to
> > > > help understand.
> > > > Second, if you do not change the value of the per-core variable_
> > > > socket_ id, /lib/eal/common/malloc_heap.c
> > > > malloc_get_numa_socket(void)
> > > > {
> > > > const struct internal_config *conf =
> > > > eal_get_internal_configuration();
> > > > unsigned int socket_id = rte_socket_id(); // The return value
> > > > of
> > > > "rte_socket_id()" is 1
> > > > unsigned int idx;
> > > >
> > > > if (socket_id != (unsigned int)SOCKET_ID_ANY)
> > > > return socket_id;//so return here
> > > >
> > > > This will cause return here, This function returns the socket_id of
> > > > unallocated memory.
> > > >
> > > > If you have a better solution, I can modify it.
[PATCH] net/idpf: refine devargs parse functions
This patch refines devargs parsing functions and use valid
variable max_vport_nb to replace IDPF_MAX_VPORT_NUM.
Signed-off-by: Mingxia Liu
---
drivers/net/idpf/idpf_ethdev.c | 61 +-
1 file changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c
index e02ec2ec5a..a8dd5a0a80 100644
--- a/drivers/net/idpf/idpf_ethdev.c
+++ b/drivers/net/idpf/idpf_ethdev.c
@@ -857,12 +857,6 @@ insert_value(struct idpf_devargs *devargs, uint16_t id)
return 0;
}
- if (devargs->req_vport_nb >= RTE_DIM(devargs->req_vports)) {
- PMD_INIT_LOG(ERR, "Total vport number can't be > %d",
-IDPF_MAX_VPORT_NUM);
- return -EINVAL;
- }
-
devargs->req_vports[devargs->req_vport_nb] = id;
devargs->req_vport_nb++;
@@ -879,12 +873,10 @@ parse_range(const char *value, struct idpf_devargs
*devargs)
result = sscanf(value, "%hu%n-%hu%n", &lo, &n, &hi, &n);
if (result == 1) {
- if (lo >= IDPF_MAX_VPORT_NUM)
- return NULL;
if (insert_value(devargs, lo) != 0)
return NULL;
} else if (result == 2) {
- if (lo > hi || hi >= IDPF_MAX_VPORT_NUM)
+ if (lo > hi)
return NULL;
for (i = lo; i <= hi; i++) {
if (insert_value(devargs, i) != 0)
@@ -969,40 +961,46 @@ idpf_parse_devargs(struct rte_pci_device *pci_dev, struct
idpf_adapter_ext *adap
return -EINVAL;
}
+ ret = rte_kvargs_process(kvlist, IDPF_VPORT, &parse_vport,
+idpf_args);
+ if (ret != 0)
+ goto fail;
+
+ ret = rte_kvargs_process(kvlist, IDPF_TX_SINGLE_Q, &parse_bool,
+&adapter->base.is_tx_singleq);
+ if (ret != 0)
+ goto fail;
+
+ ret = rte_kvargs_process(kvlist, IDPF_RX_SINGLE_Q, &parse_bool,
+&adapter->base.is_rx_singleq);
+ if (ret != 0)
+ goto fail;
+
/* check parsed devargs */
if (adapter->cur_vport_nb + idpf_args->req_vport_nb >
- IDPF_MAX_VPORT_NUM) {
+ adapter->max_vport_nb) {
PMD_INIT_LOG(ERR, "Total vport number can't be > %d",
-IDPF_MAX_VPORT_NUM);
+adapter->max_vport_nb);
ret = -EINVAL;
- goto bail;
+ goto fail;
}
for (i = 0; i < idpf_args->req_vport_nb; i++) {
+ if (idpf_args->req_vports[i] > adapter->max_vport_nb - 1) {
+ PMD_INIT_LOG(ERR, "Invalid vport id %d, it should be 0
~ %d",
+idpf_args->req_vports[i],
adapter->max_vport_nb - 1);
+ ret = -EINVAL;
+ goto fail;
+ }
if (adapter->cur_vports & RTE_BIT32(idpf_args->req_vports[i])) {
- PMD_INIT_LOG(ERR, "Vport %d has been created",
+ PMD_INIT_LOG(ERR, "Vport %d has been requested",
idpf_args->req_vports[i]);
ret = -EINVAL;
- goto bail;
+ goto fail;
}
}
- ret = rte_kvargs_process(kvlist, IDPF_VPORT, &parse_vport,
-idpf_args);
- if (ret != 0)
- goto bail;
-
- ret = rte_kvargs_process(kvlist, IDPF_TX_SINGLE_Q, &parse_bool,
-&adapter->base.is_tx_singleq);
- if (ret != 0)
- goto bail;
-
- ret = rte_kvargs_process(kvlist, IDPF_RX_SINGLE_Q, &parse_bool,
-&adapter->base.is_rx_singleq);
- if (ret != 0)
- goto bail;
-
-bail:
+fail:
rte_kvargs_free(kvlist);
return ret;
}
@@ -1152,7 +1150,8 @@ idpf_adapter_ext_init(struct rte_pci_device *pci_dev,
struct idpf_adapter_ext *a
rte_eal_alarm_set(IDPF_ALARM_INTERVAL, idpf_dev_alarm_handler, adapter);
- adapter->max_vport_nb = adapter->base.caps.max_vports;
+ adapter->max_vport_nb = adapter->base.caps.max_vports >
IDPF_MAX_VPORT_NUM ?
+ IDPF_MAX_VPORT_NUM :
adapter->base.caps.max_vports;
adapter->vports = rte_zmalloc("vports",
adapter->max_vport_nb *
--
2.34.1
Re: [PATCH] usertools: enhance CPU layout
21/04/2023 03:47, Lu, Wenzhuo: > Hi Stephen, > > From: Stephen Hemminger > > On Tue, 18 Apr 2023 13:25:41 +0800 > > Wenzhuo Lu wrote: > > > > > The cores in a single CPU may be not all the same. > > > The user tool is updated to show the > > > difference of the cores. > > > > > > This patch addes below informantion, > > > 1, Group the cores based on the die. > > > 2, A core is either a performance core or an > > >efficency core. > > >A performance core is shown as 'Core-P'. > > >An efficency core is shown as 'Core-E'. > > > 3, All the E-cores which share the same L2-cache > > >are grouped to one module. > > > > > > The known limitation. > > > 1, To tell a core is P-core or E-core is based on if > > >this core shares L2 cache with others. > > > > > > Signed-off-by: Wenzhuo Lu > > > > Side note: > > This tool only exists because of lack of simple tool at the time. > > Looking around, found that there is a tool 'lstopo' under the hwloc package > > that gives output in many formats including graphical and seems to do a > > better > > job than the DPDK python script. lstopo existed already when introducing this python script. See its home page: https://www.open-mpi.org/projects/hwloc/ We talked about dropping the DPDK script in the past: http://inbox.dpdk.org/dev/20151127161008.GA27472@bricha3-MOBL3/ I recommend using "lstopo-no-graphics --merge" > > Not sure how much farther DPDK should go in this area? > > Really should be a distro tool. > > Many thanks for your review and comments. > Have to say I'm a green hand in this field. Just imitate the existing code to > write mine. So, still trying to understand and handle the comments :) > > Better to understand more about our opinion of this script before send a v2 > patch. > I've used 'lstopo'. It's a great tool. > To my opinion, considering there're Linux tools to show all kinds of > information, the reason that DPDK has its own tool is to summarize and > emphasize the information that is important to DPDK. Here it's that some > cores are more powerful than others. When the users use a testpmd-like APP, > they can choose the appropriate cores after DPDK reminds them about the > difference between cores. > Add Thomas for more suggestions. Thanks. Adding Brice, hwloc maintainer. I think it would be better to contribute to the hwloc project. If we need a different set of info, we can probably tune it with options.
Re: [RFC] lib: set/get max memzone segments
20/04/2023 20:20, Tyler Retzlaff: > On Thu, Apr 20, 2023 at 09:43:28AM +0200, Thomas Monjalon wrote: > > 19/04/2023 16:51, Tyler Retzlaff: > > > On Wed, Apr 19, 2023 at 11:36:34AM +0300, Ophir Munk wrote: > > > > In current DPDK the RTE_MAX_MEMZONE definition is unconditionally hard > > > > coded as 2560. For applications requiring different values of this > > > > parameter – it is more convenient to set the max value via an rte API - > > > > rather than changing the dpdk source code per application. In many > > > > organizations, the possibility to compile a private DPDK library for a > > > > particular application does not exist at all. With this option there is > > > > no need to recompile DPDK and it allows using an in-box packaged DPDK. > > > > An example usage for updating the RTE_MAX_MEMZONE would be of an > > > > application that uses the DPDK mempool library which is based on DPDK > > > > memzone library. The application may need to create a number of > > > > steering tables, each of which will require its own mempool allocation. > > > > This commit is not about how to optimize the application usage of > > > > mempool nor about how to improve the mempool implementation based on > > > > memzone. It is about how to make the max memzone definition - run-time > > > > customized. > > > > This commit adds an API which must be called before rte_eal_init(): > > > > rte_memzone_max_set(int max). If not called, the default memzone > > > > (RTE_MAX_MEMZONE) is used. There is also an API to query the effective > > > > max memzone: rte_memzone_max_get(). > > > > > > > > Signed-off-by: Ophir Munk > > > > --- > > > > > > the use case of each application may want a different non-hard coded > > > value makes sense. > > > > > > it's less clear to me that requiring it be called before eal init makes > > > sense over just providing it as configuration to eal init so that it is > > > composed. > > > > Why do you think it would be better as EAL init option? > > From an API perspective, I think it is simpler to call a dedicated function. > > And I don't think a user wants to deal with it when starting the > > application. > > because a dedicated function that can be called detached from the eal > state enables an opportunity for accidental and confusing use outside > the correct context. > > i know the above prescribes not to do this but. > > now you can call set after eal init, but we protect about calling it > after init by failing. what do we do sensibly with the failure? It would be a developer mistake which could be fix during development stage very easily. I don't see a problem here. > > > can you elaborate further on why you need get if you have a one-shot > > > set? why would the application not know the value if you can only ever > > > call it once before init? > > > > The "get" function is used in this patch by test and qede driver. > > The application could use it as well, especially to query the default value. > > this seems incoherent to me, why does the application not know if it has > called set or not? if it called set it knows what the value is, if it didn't > call set it knows what the default is. No the application doesn't know the default, it is an internal value. > anyway, the use case is valid and i would like to see the ability to > change it dynamically i'd prefer not to see an api like this be introduced > as prescribed but that's for you folks to decide. > > anyway, i own a lot of apis that operate just like the proposed and > they're great source of support overhead. i prefer not to rely on > documenting a contract when i can enforce the contract and implicit state > machine mechanically with the api instead. > > fwiw a nicer pattern for doing this one of framework influencing config > might look something like this. > > struct eal_config config; > > eal_config_init(&config); // defaults are set entire state made valid > eal_config_set_max_memzone(&config, 1024); // default is overridden > > rte_eal_init(&config); In general, we discovered that functions doing too much are bad for usability and for ABI stability. In the function eal_config_init() that you propose, any change in the struct eal_config will be an ABI breakage.
[Bug 1218] memif zeor-copy mode mbuf->refcnt error
https://bugs.dpdk.org/show_bug.cgi?id=1218 Bug ID: 1218 Summary: memif zeor-copy mode mbuf->refcnt error Product: DPDK Version: unspecified Hardware: All OS: All Status: UNCONFIRMED Severity: normal Priority: Normal Component: ethdev Assignee: dev@dpdk.org Reporter: 519271...@qq.com Target Milestone: --- When I use dpdk memif zero-copy mode, use dpdk-testpmD as slave and enable zero-copy mode, and use libmemif as master, when I send a large amount of traffic, I saw that dpdk-testpmd received a refcnt error from the rte_mbuf packet, which is more likely to occur when sending larger volumes of traffic -- You are receiving this mail because: You are the assignee for the bug.
[PATCH v2 00/15] update idpf shared code
This patch set updates idpf shared code. Wenjing Qiao (15): common/idpf: remove virtchnl related shared code common/idpf: fix ctlq message send and receive common/idpf: fix ITR register definitions for AVF common/idpf: remove qregion struct variables common/idpf: move OEM capability to the last bit common/idpf: modify SSO/LSO and ITR fields common/idpf: add virtchnl2 error codes common/idpf: swap opcode and retval location in msg struct common/idpf: fix idpf_send_msg_to_cp prototypes common/idpf: fix memory leaks on ctrlq functions common/idpf: allocate static buffer at initialization common/idpf: replace MAKEMASK to IDPF_M common/idpf: add/delete queue groups commands common/idpf: add func to clean all DESCs on controlq common/idpf: update license and README .mailmap |8 + drivers/common/idpf/base/README |4 +- drivers/common/idpf/base/idpf_alloc.h |2 +- drivers/common/idpf/base/idpf_common.c| 42 +- drivers/common/idpf/base/idpf_controlq.c | 76 +- drivers/common/idpf/base/idpf_controlq.h |5 +- drivers/common/idpf/base/idpf_controlq_api.h | 12 +- .../common/idpf/base/idpf_controlq_setup.c|2 +- drivers/common/idpf/base/idpf_devids.h|2 +- drivers/common/idpf/base/idpf_lan_pf_regs.h | 37 +- drivers/common/idpf/base/idpf_lan_txrx.h | 48 +- drivers/common/idpf/base/idpf_lan_vf_regs.h | 35 +- drivers/common/idpf/base/idpf_osdep.h |4 +- drivers/common/idpf/base/idpf_prototype.h |4 +- drivers/common/idpf/base/idpf_type.h |4 +- drivers/common/idpf/base/meson.build |2 +- drivers/common/idpf/base/siov_regs.h |2 +- drivers/common/idpf/base/virtchnl.h | 2866 - drivers/common/idpf/base/virtchnl2.h | 282 +- drivers/common/idpf/base/virtchnl2_lan_desc.h | 30 +- .../common/idpf/base/virtchnl_inline_ipsec.h | 567 drivers/common/idpf/meson.build |2 + 22 files changed, 445 insertions(+), 3591 deletions(-) delete mode 100644 drivers/common/idpf/base/virtchnl.h delete mode 100644 drivers/common/idpf/base/virtchnl_inline_ipsec.h -- 2.25.1
[PATCH v2 01/15] common/idpf: remove virtchnl related shared code
Since virtchnl related shared code of iavf
and idpf has the same sourse, so remove
virtual related shared code of idpf.
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/virtchnl.h | 2866 -
.../common/idpf/base/virtchnl_inline_ipsec.h | 567
drivers/common/idpf/meson.build |2 +
3 files changed, 2 insertions(+), 3433 deletions(-)
delete mode 100644 drivers/common/idpf/base/virtchnl.h
delete mode 100644 drivers/common/idpf/base/virtchnl_inline_ipsec.h
diff --git a/drivers/common/idpf/base/virtchnl.h
b/drivers/common/idpf/base/virtchnl.h
deleted file mode 100644
index ea798e3971..00
--- a/drivers/common/idpf/base/virtchnl.h
+++ /dev/null
@@ -1,2866 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2001-2022 Intel Corporation
- */
-
-#ifndef _VIRTCHNL_H_
-#define _VIRTCHNL_H_
-
-/* Description:
- * This header file describes the Virtual Function (VF) - Physical Function
- * (PF) communication protocol used by the drivers for all devices starting
- * from our 40G product line
- *
- * Admin queue buffer usage:
- * desc->opcode is always aqc_opc_send_msg_to_pf
- * flags, retval, datalen, and data addr are all used normally.
- * The Firmware copies the cookie fields when sending messages between the
- * PF and VF, but uses all other fields internally. Due to this limitation,
- * we must send all messages as "indirect", i.e. using an external buffer.
- *
- * All the VSI indexes are relative to the VF. Each VF can have maximum of
- * three VSIs. All the queue indexes are relative to the VSI. Each VF can
- * have a maximum of sixteen queues for all of its VSIs.
- *
- * The PF is required to return a status code in v_retval for all messages
- * except RESET_VF, which does not require any response. The returned value
- * is of virtchnl_status_code type, defined here.
- *
- * In general, VF driver initialization should roughly follow the order of
- * these opcodes. The VF driver must first validate the API version of the
- * PF driver, then request a reset, then get resources, then configure
- * queues and interrupts. After these operations are complete, the VF
- * driver may start its queues, optionally add MAC and VLAN filters, and
- * process traffic.
- */
-
-/* START GENERIC DEFINES
- * Need to ensure the following enums and defines hold the same meaning and
- * value in current and future projects
- */
-
-#define VIRTCHNL_ETH_LENGTH_OF_ADDRESS 6
-
-/* These macros are used to generate compilation errors if a structure/union
- * is not exactly the correct length. It gives a divide by zero error if the
- * structure/union is not of the correct size, otherwise it creates an enum
- * that is never used.
- */
-#define VIRTCHNL_CHECK_STRUCT_LEN(n, X) enum virtchnl_static_assert_enum_##X \
- { virtchnl_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
-#define VIRTCHNL_CHECK_UNION_LEN(n, X) enum virtchnl_static_asset_enum_##X \
- { virtchnl_static_assert_##X = (n)/((sizeof(union X) == (n)) ? 1 : 0) }
-
-
-/* Error Codes
- * Note that many older versions of various iAVF drivers convert the reported
- * status code directly into an iavf_status enumeration. For this reason, it
- * is important that the values of these enumerations line up.
- */
-enum virtchnl_status_code {
- VIRTCHNL_STATUS_SUCCESS = 0,
- VIRTCHNL_STATUS_ERR_PARAM = -5,
- VIRTCHNL_STATUS_ERR_NO_MEMORY = -18,
- VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH = -38,
- VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR = -39,
- VIRTCHNL_STATUS_ERR_INVALID_VF_ID = -40,
- VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR = -53,
- VIRTCHNL_STATUS_ERR_NOT_SUPPORTED = -64,
-};
-
-/* Backward compatibility */
-#define VIRTCHNL_ERR_PARAM VIRTCHNL_STATUS_ERR_PARAM
-#define VIRTCHNL_STATUS_NOT_SUPPORTED VIRTCHNL_STATUS_ERR_NOT_SUPPORTED
-
-#define VIRTCHNL_LINK_SPEED_2_5GB_SHIFT0x0
-#define VIRTCHNL_LINK_SPEED_100MB_SHIFT0x1
-#define VIRTCHNL_LINK_SPEED_1000MB_SHIFT 0x2
-#define VIRTCHNL_LINK_SPEED_10GB_SHIFT 0x3
-#define VIRTCHNL_LINK_SPEED_40GB_SHIFT 0x4
-#define VIRTCHNL_LINK_SPEED_20GB_SHIFT 0x5
-#define VIRTCHNL_LINK_SPEED_25GB_SHIFT 0x6
-#define VIRTCHNL_LINK_SPEED_5GB_SHIFT 0x7
-
-enum virtchnl_link_speed {
- VIRTCHNL_LINK_SPEED_UNKNOWN = 0,
- VIRTCHNL_LINK_SPEED_100MB = BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT),
- VIRTCHNL_LINK_SPEED_1GB = BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT),
- VIRTCHNL_LINK_SPEED_10GB= BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT),
- VIRTCHNL_LINK_SPEED_40GB= BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),
- VIRTCHNL_LINK_SPEED_20GB= BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),
- VIRTCHNL_LINK_SPEED_25GB= BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),
- VIRTCHNL_LI
[PATCH v2 02/15] common/idpf: fix ctlq message send and receive
Fixes the ctlq send and receive functions to not cast the cookie field
to a u64 before programming. By doing a cast, it can cause endianness
issues as LE will swap the lower 32 and higher 32 bits whereas BE will
not. By treating this field as two 32 bit values, both BE and LE will
place the retval and opcode in the correct location.
Since this field is now being treated as two 32 bit values, the cfg.data
section must also be split into a data high and data low. Macros to
easily pack and read these fields have also been added.
Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")
Cc: sta...@dpdk.org
Signed-off-by: Charles Stoll
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_controlq.c | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_controlq.c
b/drivers/common/idpf/base/idpf_controlq.c
index 3af81e5a64..8e4d3ee54f 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct
idpf_ctlq_info *cq,
for (i = 0; i < num_q_msg; i++) {
struct idpf_ctlq_msg *msg = &q_msg[i];
- u64 msg_cookie;
desc = IDPF_CTLQ_DESC(cq, cq->next_to_use);
desc->opcode = CPU_TO_LE16(msg->opcode);
desc->pfid_vfid = CPU_TO_LE16(msg->func_id);
- msg_cookie = *(u64 *)&msg->cookie;
- desc->cookie_high =
- CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie));
- desc->cookie_low =
- CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie));
+ desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode);
+ desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval);
desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) <<
IDPF_CTLQ_FLAG_HOST_ID_S);
@@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16
*num_q_msg,
num_to_clean = *num_q_msg;
for (i = 0; i < num_to_clean; i++) {
- u64 msg_cookie;
-
/* Fetch next descriptor and check if marked as done */
desc = IDPF_CTLQ_DESC(cq, ntc);
flags = LE16_TO_CPU(desc->flags);
@@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16
*num_q_msg,
if (flags & IDPF_CTLQ_FLAG_ERR)
ret_code = -EBADMSG;
- msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32;
- msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low);
- idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64),
- IDPF_NONDMA_TO_NONDMA);
+ q_msg[i].cookie.mbx.chnl_opcode =
LE32_TO_CPU(desc->cookie_high);
+ q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low);
q_msg[i].opcode = LE16_TO_CPU(desc->opcode);
q_msg[i].data_len = LE16_TO_CPU(desc->datalen);
--
2.25.1
[PATCH v2 03/15] common/idpf: fix ITR register definitions for AVF
Fix ITR register definitions for AVF1.0 and AVF2.0
Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")
Cc: sta...@dpdk.org
Signed-off-by: Priyalee Kushwaha
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++--
drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 -
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h
b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 3df2347bd7..7f731ec3d6 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -77,8 +77,13 @@
#define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)
#define PF_GLINT_DYN_CTL_INTENA_MSK_S 31
#define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)
-#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start))
-#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) *
0x1000))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is
+ * spacing b/w itrn registers of the same vector.
+ */
+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+ ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */
+#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT)
* 0x1000))
#define PF_GLINT_ITR_MAX_INDEX 2
#define PF_GLINT_ITR_INTERVAL_S0
#define PF_GLINT_ITR_INTERVAL_MMAKEMASK(0xFFF,
PF_GLINT_ITR_INTERVAL_S)
diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h
b/drivers/common/idpf/base/idpf_lan_vf_regs.h
index 9cd4f757d9..13c5c5a7da 100644
--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h
@@ -90,11 +90,18 @@
#define VF_INT_DYN_CTLN_WB_ON_ITR_MBIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)
#define VF_INT_DYN_CTLN_INTENA_MSK_S 31
#define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S)
-#define VF_INT_ITR0(_i)(0x4C00 + ((_i) * 4))
-#define VF_INT_ITRN_V2(_i, _reg_start) ((_reg_start) + (((_i)) * 4))
-#define VF_INT_ITRN(_i, _INT) (0x2800 + ((_i) * 4) + ((_INT) *
0x40))
-#define VF_INT_ITRN_64(_i, _INT) (0x2C00 + ((_i) * 4) + ((_INT) *
0x100))
-#define VF_INT_ITRN_2K(_i, _INT) (0x00072000 + ((_i) * 4) + ((_INT) *
0x100))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing
+ * b/w itrn registers of the same vector
+ */
+#define VF_INT_ITR0(_ITR) (0x4C00 + ((_ITR) * 4))
+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and
itrn_indx_spacing is 0x40 */
+#define VF_INT_ITRN(_INT, _ITR)(0x2800 + ((_INT) * 4) + ((_ITR) *
0x40))
+/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and
itrn_indx_spacing is 0x100 */
+#define VF_INT_ITRN_64(_INT, _ITR) (0x2C00 + ((_INT) * 4) + ((_ITR) *
0x100))
+/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and
itrn_indx_spacing is 0x2000 */
+#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) *
0x2000))
#define VF_INT_ITRN_MAX_INDEX 2
#define VF_INT_ITRN_INTERVAL_S 0
#define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)
--
2.25.1
[PATCH v2 04/15] common/idpf: remove qregion struct variables
Existing qregion variables are not well defined and cannot be
used for TC related stuff. Remove them from create vport
struct and add those freed bytes to a new reserved field.
Add appropriate comments on how to use the dynctl and itrn
register spacing variables.
Only VF reference was used in get version comments where it
should be PF/VF.
Note: qregion variables will be added once the requirements
are defined properly.
Signed-off-by: Pavan Kumar Linga
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/virtchnl2.h | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/common/idpf/base/virtchnl2.h
b/drivers/common/idpf/base/virtchnl2.h
index d496f2388e..5c01734b65 100644
--- a/drivers/common/idpf/base/virtchnl2.h
+++ b/drivers/common/idpf/base/virtchnl2.h
@@ -426,13 +426,13 @@
/* VIRTCHNL2_OP_VERSION
- * VF posts its version number to the CP. CP responds with its version number
+ * PF/VF posts its version number to the CP. CP responds with its version
number
* in the same format, along with a return code.
- * If there is a major version mismatch, then the VF cannot operate.
- * If there is a minor version mismatch, then the VF can operate but should
+ * If there is a major version mismatch, then the PF/VF cannot operate.
+ * If there is a minor version mismatch, then the PF/VF can operate but should
* add a warning to the system log.
*
- * This version opcode MUST always be specified as == 1, regardless of other
+ * This version opcode MUST always be specified as == 1, regardless of other
* changes in the API. The CP must always respond to this message without
* error regardless of version mismatch.
*/
@@ -598,11 +598,7 @@ struct virtchnl2_create_vport {
/* see VIRTCHNL2_TX_DESC_IDS definitions */
__le64 tx_desc_ids;
-#define MAX_Q_REGIONS 16
- __le32 max_qs_per_qregion[MAX_Q_REGIONS];
- __le32 qregion_total_qs;
- __le16 qregion_type;
- __le16 pad2;
+ u8 reserved1[72];
/* see VIRTCHNL2_RSS_ALGORITHM definitions */
__le32 rss_algorithm;
@@ -665,9 +661,7 @@ struct virtchnl2_txq_info {
*/
__le16 peer_rx_queue_id;
- /* value ranges from 0 to 15 */
- __le16 qregion_id;
- u8 pad[2];
+ u8 pad[4];
/* Egress pasid is used for SIOV use case */
__le32 egress_pasid;
@@ -734,10 +728,7 @@ struct virtchnl2_rxq_info {
* if this field is set
*/
u8 bufq2_ena;
- u8 pad2;
-
- /* value ranges from 0 to 15 */
- __le16 qregion_id;
+ u8 pad2[3];
/* Ingress pasid is used for SIOV use case */
__le32 ingress_pasid;
@@ -801,9 +792,13 @@ struct virtchnl2_vector_chunk {
* interrupt indices without modifying the state of the interrupt.
*/
__le32 dynctl_reg_start;
+ /* register spacing to find the next dynctl and itrn register offset
+* from the provided dynctl_reg_start and itrn_reg_start respectively
+*/
__le32 dynctl_reg_spacing;
__le32 itrn_reg_start;
+ /* register spacing to find the individual itrn register where n=0..2 */
__le32 itrn_reg_spacing;
u8 reserved[8];
};
--
2.25.1
[PATCH v2 05/15] common/idpf: move OEM capability to the last bit
Move the existing OEM capability in VIRTCHNL2_OTHER_CAPS to the last bit. This should not break any backward compatibility as it is not used yet. And VIRTCHNL2_MEV_DEVICE is no longer upstreamed. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 5c01734b65..32d8fe8c06 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -208,11 +208,8 @@ #define VIRTCHNL2_CAP_RX_FLEX_DESC BIT(17) #define VIRTCHNL2_CAP_PTYPEBIT(18) #define VIRTCHNL2_CAP_LOOPBACK BIT(19) -#define VIRTCHNL2_CAP_OEM BIT(20) - -/* VIRTCHNL2_DEVICE_TYPE */ -/* underlying device type */ -#define VIRTCHNL2_MEV_DEVICE 0 +/* this must be the last capability */ +#define VIRTCHNL2_CAP_OEM BIT(63) /* VIRTCHNL2_TXQ_SCHED_MODE * Transmit Queue Scheduling Modes - Queue mode is the legacy mode i.e. inorder -- 2.25.1
[PATCH v2 07/15] common/idpf: add virtchnl2 error codes
Virtchnl2 error codes are required for meaningful failure information sharing between CP and PF/VF. Introduce the necessary error codes. New error codes were introduced removing the old ones. So the references to the old one should be modified to avoid CI build failures. Use appropriate error codes wherever necessary. Signed-off-by: Kazatsker Kirill Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 40 +--- 1 file changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index edf3f200b3..415e90358e 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -12,14 +12,34 @@ #include "virtchnl2_lan_desc.h" -/* Error Codes - * Note that many older versions of various iAVF drivers convert the reported - * status code directly into an iavf_status enumeration. For this reason, it - * is important that the values of these enumerations line up. - */ -#defineVIRTCHNL2_STATUS_SUCCESS0 -#defineVIRTCHNL2_STATUS_ERR_PARAM -5 -#defineVIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH-38 +/* VIRTCHNL2_ERROR_CODES */ +/* success */ +#defineVIRTCHNL2_STATUS_SUCCESS0 +/* Operation not permitted, used in case of command not permitted for sender */ +#defineVIRTCHNL2_STATUS_ERR_EPERM 1 +/* Bad opcode - virtchnl interface problem */ +#defineVIRTCHNL2_STATUS_ERR_ESRCH 3 +/* I/O error - HW access error */ +#defineVIRTCHNL2_STATUS_ERR_EIO5 +/* No such resource - Referenced resource is not allacated */ +#defineVIRTCHNL2_STATUS_ERR_ENXIO 6 +/* Permission denied - Resource is not permitted to caller */ +#defineVIRTCHNL2_STATUS_ERR_EACCES 13 +/* Device or resource busy - In case shared resource is in use by others */ +#defineVIRTCHNL2_STATUS_ERR_EBUSY 16 +/* Object already exists and not free */ +#defineVIRTCHNL2_STATUS_ERR_EEXIST 17 +/* Invalid input argument in command */ +#defineVIRTCHNL2_STATUS_ERR_EINVAL 22 +/* No space left or allocation failure */ +#defineVIRTCHNL2_STATUS_ERR_ENOSPC 28 +/* Parameter out of range */ +#defineVIRTCHNL2_STATUS_ERR_ERANGE 34 + +/* Op not allowed in current dev mode */ +#defineVIRTCHNL2_STATUS_ERR_EMODE 200 +/* State Machine error - Command sequence problem */ +#defineVIRTCHNL2_STATUS_ERR_ESM201 /* These macros are used to generate compilation errors if a structure/union * is not exactly the correct length. It gives a divide by zero error if the @@ -1445,11 +1465,11 @@ virtchnl2_vc_validate_vf_msg(__rte_unused struct virtchnl2_version_info *ver, u3 case VIRTCHNL2_OP_EVENT: case VIRTCHNL2_OP_UNKNOWN: default: - return VIRTCHNL2_STATUS_ERR_PARAM; + return VIRTCHNL2_STATUS_ERR_ESRCH; } /* few more checks */ if (err_msg_format || valid_len != msglen) - return VIRTCHNL2_STATUS_ERR_OPCODE_MISMATCH; + return VIRTCHNL2_STATUS_ERR_EINVAL; return 0; } -- 2.25.1
[PATCH v2 06/15] common/idpf: modify SSO/LSO and ITR fields
- Driver assumes minimum packet length for sso as 17 bytes
but it should be a negotiated value from CP.
- Similarly, the number of header buffers for lso that are
supported by the device should also be a negotiated value.
Add min_sso_packet_len, max_hdr_buf_per_lso to address the
above.
Also, the existing 'itrn_reg_spacing' should be used for
spacing between ITRn registers of 2 consecutive vectors and
add a new spacing field to get the spacing between ITR
registers of the same vector.
- ITR_IDX 2 is not used in the current code. Bring it back
if there exists any use case in the future.
- NO_ITR is not really a register index and it is used only
in the IDPF base code, so virtchnl support is not required for
that
- itr_idx_map is also not used as by default driver assumes
at the minimum 2 ITRs are supported by the device. If any
additional ITRs are also supported, then those should be
negotiated.
Remove all the above said fields and mark them as reserved.
Signed-off-by: Pavan Kumar Linga
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/virtchnl2.h | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/common/idpf/base/virtchnl2.h
b/drivers/common/idpf/base/virtchnl2.h
index 32d8fe8c06..edf3f200b3 100644
--- a/drivers/common/idpf/base/virtchnl2.h
+++ b/drivers/common/idpf/base/virtchnl2.h
@@ -289,8 +289,6 @@
*/
#define VIRTCHNL2_ITR_IDX_00
#define VIRTCHNL2_ITR_IDX_11
-#define VIRTCHNL2_ITR_IDX_22
-#define VIRTCHNL2_ITR_IDX_NO_ITR 3
/* VIRTCHNL2_VECTOR_LIMITS
* Since PF/VF messages are limited by __le16 size, precalculate the maximum
@@ -510,9 +508,7 @@ struct virtchnl2_get_capabilities {
*/
u8 max_sg_bufs_per_tx_pkt;
- /* see VIRTCHNL2_ITR_IDX definition */
- u8 itr_idx_map;
-
+ u8 reserved1;
__le16 pad1;
/* version of Control Plane that is running */
@@ -521,7 +517,12 @@ struct virtchnl2_get_capabilities {
/* see VIRTCHNL2_DEVICE_TYPE definitions */
__le32 device_type;
- u8 reserved[12];
+ /* min packet length supported by device for single segment offload */
+ u8 min_sso_packet_len;
+ /* max number of header buffers that can be used for an LSO */
+ u8 max_hdr_buf_per_lso;
+
+ u8 reserved[10];
};
VIRTCHNL2_CHECK_STRUCT_LEN(80, virtchnl2_get_capabilities);
@@ -789,15 +790,17 @@ struct virtchnl2_vector_chunk {
* interrupt indices without modifying the state of the interrupt.
*/
__le32 dynctl_reg_start;
- /* register spacing to find the next dynctl and itrn register offset
-* from the provided dynctl_reg_start and itrn_reg_start respectively
-*/
+ /* register spacing between dynctl registers of 2 consecutive vectors */
__le32 dynctl_reg_spacing;
__le32 itrn_reg_start;
- /* register spacing to find the individual itrn register where n=0..2 */
+ /* register spacing between itrn registers of 2 consecutive vectors */
__le32 itrn_reg_spacing;
- u8 reserved[8];
+ /* register spacing between itrn registers of the same vector
+* where n=0..2
+*/
+ __le32 itrn_index_spacing;
+ u8 reserved[4];
};
VIRTCHNL2_CHECK_STRUCT_LEN(32, virtchnl2_vector_chunk);
--
2.25.1
[PATCH v2 09/15] common/idpf: fix idpf_send_msg_to_cp prototypes
Virtchnl2 opcodes are no longer in the enum virtchnl_ops. So change
these parameters to allow int rather that compiler enum type checking.
Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")
Cc: sta...@dpdk.org
Signed-off-by: Christopher Pau
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_common.c| 2 +-
drivers/common/idpf/base/idpf_prototype.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_common.c
b/drivers/common/idpf/base/idpf_common.c
index 3a9fdb1878..69e3b32f85 100644
--- a/drivers/common/idpf/base/idpf_common.c
+++ b/drivers/common/idpf/base/idpf_common.c
@@ -146,7 +146,7 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size
ctlq_size)
* is sent asynchronously, i.e. idpf_asq_send_command() does not wait for
* completion before returning.
*/
-int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode,
+int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode,
int v_retval, u8 *msg, u16 msglen)
{
struct idpf_ctlq_msg ctlq_msg = { 0 };
diff --git a/drivers/common/idpf/base/idpf_prototype.h
b/drivers/common/idpf/base/idpf_prototype.h
index 529b62212d..3ce25e644d 100644
--- a/drivers/common/idpf/base/idpf_prototype.h
+++ b/drivers/common/idpf/base/idpf_prototype.h
@@ -40,6 +40,6 @@ int idpf_set_rss_key(struct idpf_hw *hw, u16 seid,
int idpf_set_mac_type(struct idpf_hw *hw);
int idpf_reset(struct idpf_hw *hw);
-int idpf_send_msg_to_cp(struct idpf_hw *hw, enum virtchnl_ops v_opcode,
+int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode,
int v_retval, u8 *msg, u16 msglen);
#endif /* _IDPF_PROTOTYPE_H_ */
--
2.25.1
[PATCH v2 08/15] common/idpf: swap opcode and retval location in msg struct
To make the code more readable and make it clearer that the opcode goes
in cookie_high and retval goes in cookie_low.
Add macro definitions for filling opcode and retval.
Signed-off-by: Charles Stoll
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_controlq.c | 2 ++
drivers/common/idpf/base/idpf_controlq_api.h | 6 +-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/common/idpf/base/idpf_controlq.c
b/drivers/common/idpf/base/idpf_controlq.c
index 8e4d3ee54f..8381e4000f 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -288,6 +288,8 @@ int idpf_ctlq_deinit(struct idpf_hw *hw)
* send routine via the q_msg struct / control queue specific data struct.
* The control queue will hold a reference to each send message until
* the completion for that message has been cleaned.
+ * Since all q_msgs being sent are store in native endianness, these values
+ * must be converted to LE before being written to the hw descriptor.
*/
int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
u16 num_q_msg, struct idpf_ctlq_msg q_msg[])
diff --git a/drivers/common/idpf/base/idpf_controlq_api.h
b/drivers/common/idpf/base/idpf_controlq_api.h
index 32d17baadf..80be282b42 100644
--- a/drivers/common/idpf/base/idpf_controlq_api.h
+++ b/drivers/common/idpf/base/idpf_controlq_api.h
@@ -63,9 +63,13 @@ struct idpf_ctlq_msg {
u16 status; /* when receiving a message */
};
union {
+#ifndef __KERNEL__
+#define FILL_OPCODE_V1(msg, opcode) ((msg).cookie.cfg.mbx.chnl_opcode = opcode)
+#define FILL_RETVAL_V1(msg, retval) ((msg).cookie.cfg.mbx.chnl_retval = retval)
+#endif /* __KERNEL__ */
struct {
- u32 chnl_retval;
u32 chnl_opcode;
+ u32 chnl_retval;
} mbx;
} cookie;
union {
--
2.25.1
[PATCH v2 10/15] common/idpf: fix memory leaks on ctrlq functions
idpf_init_hw needs to free it's q_info.
idpf_clean_arq_element needs to return buffers via post_rx_buffs
Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")
Cc: sta...@dpdk.org
Signed-off-by: Christopher Pau
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_common.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/common/idpf/base/idpf_common.c
b/drivers/common/idpf/base/idpf_common.c
index 69e3b32f85..de82c3458f 100644
--- a/drivers/common/idpf/base/idpf_common.c
+++ b/drivers/common/idpf/base/idpf_common.c
@@ -130,6 +130,8 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size
ctlq_size)
hw->mac.addr[4] = 0x03;
hw->mac.addr[5] = 0x14;
+ idpf_free(hw, q_info);
+
return 0;
}
@@ -219,6 +221,7 @@ bool idpf_check_asq_alive(struct idpf_hw *hw)
int idpf_clean_arq_element(struct idpf_hw *hw,
struct idpf_arq_event_info *e, u16 *pending)
{
+ struct idpf_dma_mem *dma_mem = NULL;
struct idpf_ctlq_msg msg = { 0 };
int status;
u16 msg_data_len;
@@ -226,6 +229,8 @@ int idpf_clean_arq_element(struct idpf_hw *hw,
*pending = 1;
status = idpf_ctlq_recv(hw->arq, pending, &msg);
+ if (status == -ENOMSG)
+ goto exit;
/* ctlq_msg does not align to ctlq_desc, so copy relevant data here */
e->desc.opcode = msg.opcode;
@@ -240,7 +245,14 @@ int idpf_clean_arq_element(struct idpf_hw *hw,
msg_data_len = msg.data_len;
idpf_memcpy(e->msg_buf, msg.ctx.indirect.payload->va,
msg_data_len,
IDPF_DMA_TO_NONDMA);
+ dma_mem = msg.ctx.indirect.payload;
+ } else {
+ *pending = 0;
}
+
+ status = idpf_ctlq_post_rx_buffs(hw, hw->arq, pending, &dma_mem);
+
+exit:
return status;
}
--
2.25.1
[PATCH v2 11/15] common/idpf: allocate static buffer at initialization
Some OSs don't allow allocating DMA memory at runtime. So create an
initial static buffer at initialization to hold this data.
Signed-off-by: Christopher Pau
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_common.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_common.c
b/drivers/common/idpf/base/idpf_common.c
index de82c3458f..f4a5707272 100644
--- a/drivers/common/idpf/base/idpf_common.c
+++ b/drivers/common/idpf/base/idpf_common.c
@@ -6,6 +6,7 @@
#include "idpf_prototype.h"
#include "virtchnl.h"
+struct idpf_dma_mem send_dma_mem = { 0 };
/**
* idpf_set_mac_type - Sets MAC type
@@ -132,6 +133,15 @@ int idpf_init_hw(struct idpf_hw *hw, struct idpf_ctlq_size
ctlq_size)
idpf_free(hw, q_info);
+ /*
+* Need an initial static buffer to copy DMA memory to send
+* for drivers that do not allow this allocation at runtime
+*/
+ send_dma_mem.va = (struct idpf_dma_mem *)
+ idpf_alloc_dma_mem(hw, &send_dma_mem, 4096);
+ if (!send_dma_mem.va)
+ return -ENOMEM;
+
return 0;
}
@@ -152,7 +162,6 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode,
int v_retval, u8 *msg, u16 msglen)
{
struct idpf_ctlq_msg ctlq_msg = { 0 };
- struct idpf_dma_mem dma_mem = { 0 };
int status;
ctlq_msg.opcode = idpf_mbq_opc_send_msg_to_pf;
@@ -162,19 +171,11 @@ int idpf_send_msg_to_cp(struct idpf_hw *hw, int v_opcode,
ctlq_msg.cookie.mbx.chnl_opcode = v_opcode;
if (msglen > 0) {
- dma_mem.va = (struct idpf_dma_mem *)
- idpf_alloc_dma_mem(hw, &dma_mem, msglen);
- if (!dma_mem.va)
- return -ENOMEM;
-
- idpf_memcpy(dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA);
- ctlq_msg.ctx.indirect.payload = &dma_mem;
+ idpf_memcpy(send_dma_mem.va, msg, msglen, IDPF_NONDMA_TO_DMA);
+ ctlq_msg.ctx.indirect.payload = &send_dma_mem;
}
status = idpf_ctlq_send(hw, hw->asq, 1, &ctlq_msg);
- if (dma_mem.va)
- idpf_free_dma_mem(hw, &dma_mem);
-
return status;
}
@@ -262,6 +263,9 @@ int idpf_clean_arq_element(struct idpf_hw *hw,
*/
int idpf_deinit_hw(struct idpf_hw *hw)
{
+ if (send_dma_mem.va)
+ idpf_free_dma_mem(hw, &send_dma_mem);
+
hw->asq = NULL;
hw->arq = NULL;
--
2.25.1
[PATCH v2 12/15] common/idpf: replace MAKEMASK to IDPF_M
Replace MAKEMASK to IDPF_M to avoid conflicts with MAKEMASK
redefinition from various subcomponents.
Signed-off-by: Priyalee Kushwaha
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_controlq.h | 3 --
drivers/common/idpf/base/idpf_lan_pf_regs.h | 26 +--
drivers/common/idpf/base/idpf_lan_txrx.h | 46 +--
drivers/common/idpf/base/idpf_lan_vf_regs.h | 16 +++
drivers/common/idpf/base/idpf_osdep.h | 2 +
drivers/common/idpf/base/idpf_type.h | 2 -
drivers/common/idpf/base/virtchnl2_lan_desc.h | 28 +--
7 files changed, 60 insertions(+), 63 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_controlq.h
b/drivers/common/idpf/base/idpf_controlq.h
index e7b0d803b3..47bffcf79f 100644
--- a/drivers/common/idpf/base/idpf_controlq.h
+++ b/drivers/common/idpf/base/idpf_controlq.h
@@ -97,9 +97,6 @@ struct idpf_ctlq_desc {
#define IDPF_CTLQ_FLAG_VFC BIT(IDPF_CTLQ_FLAG_VFC_S) /* 0x800 */
#define IDPF_CTLQ_FLAG_BUF BIT(IDPF_CTLQ_FLAG_BUF_S) /* 0x1000 */
-/* Host ID is a special field that has 3b and not a 1b flag */
-#define IDPF_CTLQ_FLAG_HOST_ID_M MAKE_MASK(0x7000UL, IDPF_CTLQ_FLAG_HOST_ID_S)
-
struct idpf_mbxq_desc {
u8 pad[8]; /* CTLQ flags/opcode/len/retval fields */
u32 chnl_opcode;/* avoid confusion with desc->opcode */
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h
b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 7f731ec3d6..1c665d1f3b 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -24,7 +24,7 @@
#define PF_FW_ARQBAH (PF_FW_BASE + 0x4)
#define PF_FW_ARQLEN (PF_FW_BASE + 0x8)
#define PF_FW_ARQLEN_ARQLEN_S 0
-#define PF_FW_ARQLEN_ARQLEN_M MAKEMASK(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)
+#define PF_FW_ARQLEN_ARQLEN_M IDPF_M(0x1FFF, PF_FW_ARQLEN_ARQLEN_S)
#define PF_FW_ARQLEN_ARQVFE_S 28
#define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)
#define PF_FW_ARQLEN_ARQOVFL_S 29
@@ -35,14 +35,14 @@
#define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)
#define PF_FW_ARQH (PF_FW_BASE + 0xC)
#define PF_FW_ARQH_ARQH_S 0
-#define PF_FW_ARQH_ARQH_M MAKEMASK(0x1FFF, PF_FW_ARQH_ARQH_S)
+#define PF_FW_ARQH_ARQH_M IDPF_M(0x1FFF, PF_FW_ARQH_ARQH_S)
#define PF_FW_ARQT (PF_FW_BASE + 0x10)
#define PF_FW_ATQBAL (PF_FW_BASE + 0x14)
#define PF_FW_ATQBAH (PF_FW_BASE + 0x18)
#define PF_FW_ATQLEN (PF_FW_BASE + 0x1C)
#define PF_FW_ATQLEN_ATQLEN_S 0
-#define PF_FW_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
+#define PF_FW_ATQLEN_ATQLEN_M IDPF_M(0x3FF, PF_FW_ATQLEN_ATQLEN_S)
#define PF_FW_ATQLEN_ATQVFE_S 28
#define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)
#define PF_FW_ATQLEN_ATQOVFL_S 29
@@ -53,7 +53,7 @@
#define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)
#define PF_FW_ATQH (PF_FW_BASE + 0x20)
#define PF_FW_ATQH_ATQH_S 0
-#define PF_FW_ATQH_ATQH_M MAKEMASK(0x3FF, PF_FW_ATQH_ATQH_S)
+#define PF_FW_ATQH_ATQH_M IDPF_M(0x3FF, PF_FW_ATQH_ATQH_S)
#define PF_FW_ATQT (PF_FW_BASE + 0x24)
/* Interrupts */
@@ -66,7 +66,7 @@
#define PF_GLINT_DYN_CTL_SWINT_TRIG_S 2
#define PF_GLINT_DYN_CTL_SWINT_TRIG_M BIT(PF_GLINT_DYN_CTL_SWINT_TRIG_S)
#define PF_GLINT_DYN_CTL_ITR_INDX_S3
-#define PF_GLINT_DYN_CTL_ITR_INDX_MMAKEMASK(0x3,
PF_GLINT_DYN_CTL_ITR_INDX_S)
+#define PF_GLINT_DYN_CTL_ITR_INDX_MIDPF_M(0x3, PF_GLINT_DYN_CTL_ITR_INDX_S)
#define PF_GLINT_DYN_CTL_INTERVAL_S5
#define PF_GLINT_DYN_CTL_INTERVAL_MBIT(PF_GLINT_DYN_CTL_INTERVAL_S)
#define PF_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24
@@ -86,13 +86,13 @@
#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT)
* 0x1000))
#define PF_GLINT_ITR_MAX_INDEX 2
#define PF_GLINT_ITR_INTERVAL_S0
-#define PF_GLINT_ITR_INTERVAL_MMAKEMASK(0xFFF,
PF_GLINT_ITR_INTERVAL_S)
+#define PF_GLINT_ITR_INTERVAL_MIDPF_M(0xFFF,
PF_GLINT_ITR_INTERVAL_S)
/* Timesync registers */
#define PF_TIMESYNC_BASE 0x08404000
#define PF_GLTSYN_CMD_SYNC (PF_TIMESYNC_BASE)
#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_S 0
-#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M MAKEMASK(0x3,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)
+#define PF_GLTSYN_CMD_SYNC_EXEC_CMD_M IDPF_M(0x3,
PF_GLTSYN_CMD_SYNC_EXEC_CMD_S)
#define PF_GLTSYN_CMD_SYNC_SHTIME_EN_S 2
#define PF_GLTSYN_CMD_SYNC_SHTIME_EN_M BIT(PF_GLTSYN_CMD_SYNC_SHTIME_EN_S)
#define PF_GLTSYN_SHTIME_0 (PF_TIMESYNC_BASE + 0x4)
@@ -104,23 +104,23 @@
/* Generic registers */
#define PF_INT_DIR_OICR_ENA0x08406000
#define
[PATCH v2 13/15] common/idpf: add/delete queue groups commands
Add types for new two virtchnl commands: add & delete queue group
Signed-off-by: Nizan Zorea
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/virtchnl2.h | 189 +++
1 file changed, 189 insertions(+)
diff --git a/drivers/common/idpf/base/virtchnl2.h
b/drivers/common/idpf/base/virtchnl2.h
index 415e90358e..9e70e5b10e 100644
--- a/drivers/common/idpf/base/virtchnl2.h
+++ b/drivers/common/idpf/base/virtchnl2.h
@@ -95,6 +95,8 @@
#defineVIRTCHNL2_OP_ADD_MAC_ADDR 535
#defineVIRTCHNL2_OP_DEL_MAC_ADDR 536
#defineVIRTCHNL2_OP_CONFIG_PROMISCUOUS_MODE537
+#defineVIRTCHNL2_OP_ADD_QUEUE_GROUPS 538
+#defineVIRTCHNL2_OP_DEL_QUEUE_GROUPS 539
#define VIRTCHNL2_RDMA_INVALID_QUEUE_IDX 0x
@@ -345,6 +347,14 @@
#define VIRTCHNL2_UNICAST_PROMISC BIT(0)
#define VIRTCHNL2_MULTICAST_PROMISCBIT(1)
+/* VIRTCHNL2_QUEUE_GROUP_TYPE
+ * Type of queue groups
+ * 0 till 0xFF is for general use
+ */
+#define VIRTCHNL2_QUEUE_GROUP_DATA 1
+#define VIRTCHNL2_QUEUE_GROUP_MBX 2
+#define VIRTCHNL2_QUEUE_GROUP_CONFIG 3
+
/* VIRTCHNL2_PROTO_HDR_TYPE
* Protocol header type within a packet segment. A segment consists of one or
* more protocol headers that make up a logical group of protocol headers. Each
@@ -794,6 +804,133 @@ struct virtchnl2_add_queues {
VIRTCHNL2_CHECK_STRUCT_LEN(56, virtchnl2_add_queues);
+/* Queue Groups Extension */
+
+struct virtchnl2_rx_queue_group_info {
+ /* IN/OUT, user can ask to update rss_lut size originally allocated
+* by CreateVport command. New size will be returned if allocation
+* suceeded, otherwise original rss_size from CreateVport will
+* be returned.
+*/
+ __le16 rss_lut_size;
+ /* Future extension purpose */
+ u8 pad[6];
+};
+
+VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_rx_queue_group_info);
+
+struct virtchnl2_tx_queue_group_info { /* IN */
+ /* TX TC queue group will be connected to */
+ u8 tx_tc;
+ /* Each group can have its own priority, value 0-7, while each group
+* with unique priority is strict priority.
+* It can be single set of queue groups which configured with
+* same priority, then they are assumed part of WFQ arbitration
+* group and are expected to be assigned with weight.
+*/
+ u8 priority;
+ /* Determines if queue group is expected to be Strict Priority
+* according to its priority
+*/
+ u8 is_sp;
+ u8 pad;
+
+ /* Peak Info Rate Weight in case Queue Group is part of WFQ
+* arbitration set.
+* The weights of the groups are independent of each other.
+* Possible values: 1-200
+*/
+ __le16 pir_weight;
+ /* Future extension purpose for CIR only */
+ u8 cir_pad[2];
+ /* Future extension purpose*/
+ u8 pad2[8];
+};
+
+VIRTCHNL2_CHECK_STRUCT_LEN(16, virtchnl2_tx_queue_group_info);
+
+struct virtchnl2_queue_group_id {
+ /* Queue group ID - depended on it's type
+* Data: is an ID which is relative to Vport
+* Config & Mailbox: is an ID which is relative to func.
+* This ID is use in future calls, i.e. delete.
+* Requested by host and assigned by Control plane.
+*/
+ __le16 queue_group_id;
+ /* Functional type: see VIRTCHNL2_QUEUE_GROUP_TYPE definitions */
+ __le16 queue_group_type;
+ u8 pad[4];
+};
+
+VIRTCHNL2_CHECK_STRUCT_LEN(8, virtchnl2_queue_group_id);
+
+struct virtchnl2_queue_group_info {
+ /* IN */
+ struct virtchnl2_queue_group_id qg_id;
+ /* IN, Number of queue of different types in the group. */
+ __le16 num_tx_q;
+ __le16 num_tx_complq;
+ __le16 num_rx_q;
+ __le16 num_rx_bufq;
+
+ struct virtchnl2_tx_queue_group_info tx_q_grp_info;
+ struct virtchnl2_rx_queue_group_info rx_q_grp_info;
+ /* Future extension purpose */
+ u8 pad[40];
+ struct virtchnl2_queue_reg_chunks chunks; /* OUT */
+};
+
+VIRTCHNL2_CHECK_STRUCT_LEN(120, virtchnl2_queue_group_info);
+
+struct virtchnl2_queue_groups {
+ __le16 num_queue_groups;
+ u8 pad[6];
+ struct virtchnl2_queue_group_info groups[1];
+};
+
+VIRTCHNL2_CHECK_STRUCT_LEN(128, virtchnl2_queue_groups);
+
+/* VIRTCHNL2_OP_ADD_QUEUE_GROUPS
+ * PF sends this message to request additional transmit/receive queue groups
+ * beyond the ones that were assigned via CREATE_VPORT request.
+ * virtchnl2_add_queue_groups structure is used to specify the number of each
+ * type of queues. CP responds with the same structure with the actual number
of
+ * groups and queues assigned followed by num_queue_groups and num_chunks of
+ * virtchnl2_queue_groups and virtchnl2_queue_chunk structures.
+ */
+struct virtchnl2_add_queue_groups {
+ /* I
[PATCH v2 14/15] common/idpf: add func to clean all DESCs on controlq
Add 'idpf_ctlq_clean_sq_force' which will clean all descriptors on
given control queue. It is needed in case control plane is not
running and we need to do proper driver cleanup.
Signed-off-by: NorbertX Ciosek
Signed-off-by: Wenjing Qiao
---
drivers/common/idpf/base/idpf_controlq.c | 56 ++--
drivers/common/idpf/base/idpf_controlq_api.h | 4 ++
2 files changed, 55 insertions(+), 5 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_controlq.c
b/drivers/common/idpf/base/idpf_controlq.c
index 8381e4000f..9374fce71e 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -386,13 +386,15 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct
idpf_ctlq_info *cq,
}
/**
- * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the
- * requested queue
+ * __idpf_ctlq_clean_sq - helper function to reclaim descriptors on HW write
+ * back for the requested queue
* @cq: pointer to the specific Control queue
* @clean_count: (input|output) number of descriptors to clean as input, and
* number of descriptors actually cleaned as output
* @msg_status: (output) pointer to msg pointer array to be populated; needs
* to be allocated by caller
+ * @force: (input) clean descriptors which were not done yet. Use with caution
+ * in kernel mode only
*
* Returns an array of message pointers associated with the cleaned
* descriptors. The pointers are to the original ctlq_msgs sent on the cleaned
@@ -400,8 +402,8 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct
idpf_ctlq_info *cq,
* to send will have a non-zero status. The caller is expected to free original
* ctlq_msgs and free or reuse the DMA buffers.
*/
-int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
- struct idpf_ctlq_msg *msg_status[])
+static int __idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
+ struct idpf_ctlq_msg *msg_status[], bool force)
{
struct idpf_ctlq_desc *desc;
u16 i = 0, num_to_clean;
@@ -425,7 +427,7 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16
*clean_count,
for (i = 0; i < num_to_clean; i++) {
/* Fetch next descriptor and check if marked as done */
desc = IDPF_CTLQ_DESC(cq, ntc);
- if (!(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD))
+ if (!force && !(LE16_TO_CPU(desc->flags) & IDPF_CTLQ_FLAG_DD))
break;
desc_err = LE16_TO_CPU(desc->ret_val);
@@ -435,6 +437,8 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16
*clean_count,
}
msg_status[i] = cq->bi.tx_msg[ntc];
+ if (!msg_status[i])
+ break;
msg_status[i]->status = desc_err;
cq->bi.tx_msg[ntc] = NULL;
@@ -457,6 +461,48 @@ int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16
*clean_count,
return ret;
}
+/**
+ * idpf_ctlq_clean_sq_force - reclaim all descriptors on HW write back for the
+ * requested queue. Use only in kernel mode.
+ * @cq: pointer to the specific Control queue
+ * @clean_count: (input|output) number of descriptors to clean as input, and
+ * number of descriptors actually cleaned as output
+ * @msg_status: (output) pointer to msg pointer array to be populated; needs
+ * to be allocated by caller
+ *
+ * Returns an array of message pointers associated with the cleaned
+ * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned
+ * descriptors. The status will be returned for each; any messages that failed
+ * to send will have a non-zero status. The caller is expected to free original
+ * ctlq_msgs and free or reuse the DMA buffers.
+ */
+int idpf_ctlq_clean_sq_force(struct idpf_ctlq_info *cq, u16 *clean_count,
+struct idpf_ctlq_msg *msg_status[])
+{
+ return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, true);
+}
+
+/**
+ * idpf_ctlq_clean_sq - reclaim send descriptors on HW write back for the
+ * requested queue
+ * @cq: pointer to the specific Control queue
+ * @clean_count: (input|output) number of descriptors to clean as input, and
+ * number of descriptors actually cleaned as output
+ * @msg_status: (output) pointer to msg pointer array to be populated; needs
+ * to be allocated by caller
+ *
+ * Returns an array of message pointers associated with the cleaned
+ * descriptors. The pointers are to the original ctlq_msgs sent on the cleaned
+ * descriptors. The status will be returned for each; any messages that failed
+ * to send will have a non-zero status. The caller is expected to free original
+ * ctlq_msgs and free or reuse the DMA buffers.
+ */
+int idpf_ctlq_clean_sq(struct idpf_ctlq_info *cq, u16 *clean_count,
+ struct idpf_ctlq_msg *msg_status[])
+{
+ return __idpf_ctlq_clean_sq(cq, clean_count, msg_status, false);
+}
+
/**
* idpf_ctlq_po
[PATCH v2 15/15] common/idpf: update license and README
Update license and README Signed-off-by: Wenjing Qiao --- .mailmap | 8 drivers/common/idpf/base/README| 4 ++-- drivers/common/idpf/base/idpf_alloc.h | 2 +- drivers/common/idpf/base/idpf_common.c | 2 +- drivers/common/idpf/base/idpf_controlq.c | 2 +- drivers/common/idpf/base/idpf_controlq.h | 2 +- drivers/common/idpf/base/idpf_controlq_api.h | 2 +- drivers/common/idpf/base/idpf_controlq_setup.c | 2 +- drivers/common/idpf/base/idpf_devids.h | 2 +- drivers/common/idpf/base/idpf_lan_pf_regs.h| 2 +- drivers/common/idpf/base/idpf_lan_txrx.h | 2 +- drivers/common/idpf/base/idpf_lan_vf_regs.h| 2 +- drivers/common/idpf/base/idpf_osdep.h | 2 +- drivers/common/idpf/base/idpf_prototype.h | 2 +- drivers/common/idpf/base/idpf_type.h | 2 +- drivers/common/idpf/base/meson.build | 2 +- drivers/common/idpf/base/siov_regs.h | 2 +- drivers/common/idpf/base/virtchnl2.h | 2 +- drivers/common/idpf/base/virtchnl2_lan_desc.h | 2 +- 19 files changed, 27 insertions(+), 19 deletions(-) diff --git a/.mailmap b/.mailmap index 0859104404..309b1bc69e 100644 --- a/.mailmap +++ b/.mailmap @@ -1603,3 +1603,11 @@ Ziye Yang Zoltan Kiss Zorik Machulsky Zyta Szpak +Charles Stoll +Nizan Zorea +Vinoth Kumar Chandra Mohan +NorbertX Ciosek +Pavan Kumar Linga +Jun Zhang +Priyalee Kushwaha +Kazatsker Kirill diff --git a/drivers/common/idpf/base/README b/drivers/common/idpf/base/README index 257ad6c4b1..693049c057 100644 --- a/drivers/common/idpf/base/README +++ b/drivers/common/idpf/base/README @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2021-2022 Intel Corporation + * Copyright(c) 2021-2023 Intel Corporation */ Intel® IDPF driver == This directory contains source code of BSD-3-Clause idpf driver of version -2022.09.13 released by the team which develops basic drivers for Intel IPU. +2023.02.23 released by the team which develops basic drivers for Intel IPU. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/common/idpf/base/idpf_alloc.h b/drivers/common/idpf/base/idpf_alloc.h index bc054851b3..5cc4beb5cf 100644 --- a/drivers/common/idpf/base/idpf_alloc.h +++ b/drivers/common/idpf/base/idpf_alloc.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_ALLOC_H_ diff --git a/drivers/common/idpf/base/idpf_common.c b/drivers/common/idpf/base/idpf_common.c index f4a5707272..d0efc6be66 100644 --- a/drivers/common/idpf/base/idpf_common.c +++ b/drivers/common/idpf/base/idpf_common.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_type.h" diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c index 9374fce71e..68aae6f321 100644 --- a/drivers/common/idpf/base/idpf_controlq.c +++ b/drivers/common/idpf/base/idpf_controlq.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #include "idpf_controlq.h" diff --git a/drivers/common/idpf/base/idpf_controlq.h b/drivers/common/idpf/base/idpf_controlq.h index 47bffcf79f..0fe0e94a37 100644 --- a/drivers/common/idpf/base/idpf_controlq.h +++ b/drivers/common/idpf/base/idpf_controlq.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_api.h b/drivers/common/idpf/base/idpf_controlq_api.h index a00faac05f..ad649ab356 100644 --- a/drivers/common/idpf/base/idpf_controlq_api.h +++ b/drivers/common/idpf/base/idpf_controlq_api.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ #ifndef _IDPF_CONTROLQ_API_H_ diff --git a/drivers/common/idpf/base/idpf_controlq_setup.c b/drivers/common/idpf/base/idpf_controlq_setup.c index 3a272b1f8d..0f1b52a7e9 100644 --- a/drivers/common/idpf/base/idpf_controlq_setup.c +++ b/drivers/common/idpf/base/idpf_controlq_setup.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel Corporation + * Copyright(c) 2001-2023 Intel Corporation */ diff --git a/drivers/common/idpf/base/idpf_devids.h b/drivers/common/idpf/base/idpf_devids.h index a91eb4e02a..c47762d5b7 100644 --- a/drivers/common/idpf/base/idpf_devids.h +++ b/drivers/common/idpf/base/idpf_devids.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2022 Intel
[PATCH 2/2] net/hns3: support dump media type
From: Chengwen Feng
The media type information helps locate faults such as AN or rate
switching, so add dump media type in eth_dev_priv_dump ops.
Signed-off-by: Chengwen Feng
Signed-off-by: Dongdong Liu
---
drivers/net/hns3/hns3_dump.c | 2 ++
drivers/net/hns3/hns3_ethdev.c | 2 +-
drivers/net/hns3/hns3_ethdev.h | 2 ++
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c
index 8d723f1876..0af3c2ce09 100644
--- a/drivers/net/hns3/hns3_dump.c
+++ b/drivers/net/hns3/hns3_dump.c
@@ -68,12 +68,14 @@ hns3_get_dev_mac_info(FILE *file, struct hns3_adapter *hns)
fprintf(file, " - MAC Info:\n");
fprintf(file,
+ "\t -- media_type=%s\n"
"\t -- query_type=%u\n"
"\t -- supported_speed=0x%x\n"
"\t -- advertising=0x%x\n"
"\t -- lp_advertising=0x%x\n"
"\t -- support_autoneg=%s\n"
"\t -- support_fc_autoneg=%s\n",
+ hns3_get_media_type_name(hw->mac.media_type),
hw->mac.query_type,
hw->mac.supported_speed,
hw->mac.advertising,
diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c
index a872cb8dd7..d97280e647 100644
--- a/drivers/net/hns3/hns3_ethdev.c
+++ b/drivers/net/hns3/hns3_ethdev.c
@@ -4891,7 +4891,7 @@ hns3_set_fiber_port_link_speed(struct hns3_hw *hw,
return hns3_cfg_mac_speed_dup(hw, cfg->speed, cfg->duplex);
}
-static const char *
+const char *
hns3_get_media_type_name(uint8_t media_type)
{
if (media_type == HNS3_MEDIA_TYPE_FIBER)
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index ee4dd18d7b..8268dba788 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -1054,6 +1054,8 @@ int hns3_timesync_write_time(struct rte_eth_dev *dev,
const struct timespec *ts);
int hns3_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
+const char *hns3_get_media_type_name(uint8_t media_type);
+
static inline bool
is_reset_pending(struct hns3_adapter *hns)
{
--
2.22.0
[PATCH 0/2] net/hns3: add some features for hns3 pmd
This patchset is to add some features for hns3 pmd. Chengwen Feng (1): net/hns3: support dump media type Dongdong Liu (1): net/hns3: simplify for hardware csum offloading drivers/net/hns3/hns3_cmd.c| 3 ++ drivers/net/hns3/hns3_cmd.h| 1 + drivers/net/hns3/hns3_dump.c | 3 ++ drivers/net/hns3/hns3_ethdev.c | 2 +- drivers/net/hns3/hns3_ethdev.h | 3 ++ drivers/net/hns3/hns3_rxtx.c | 52 +- drivers/net/hns3/hns3_rxtx.h | 12 +++- 7 files changed, 73 insertions(+), 3 deletions(-) -- 2.22.0
[PATCH 1/2] net/hns3: simplify for hardware csum offloading
If the NIC support simple BD mode, the hardware will calculate
the checksum from the start position of checksum and fill the
checksum result to the offset position, which simple the
HW operations of calculating the type and header length of
L3/L4. Add this mode for hns3 pmd when the packet type
is L4.
Signed-off-by: Dongdong Liu
---
drivers/net/hns3/hns3_cmd.c| 3 ++
drivers/net/hns3/hns3_cmd.h| 1 +
drivers/net/hns3/hns3_dump.c | 1 +
drivers/net/hns3/hns3_ethdev.h | 1 +
drivers/net/hns3/hns3_rxtx.c | 52 +-
drivers/net/hns3/hns3_rxtx.h | 12 +++-
6 files changed, 68 insertions(+), 2 deletions(-)
diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index bdfc85f934..d530650452 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -419,6 +419,7 @@ hns3_get_caps_name(uint32_t caps_id)
} dev_caps[] = {
{ HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
{ HNS3_CAPS_PTP_B, "ptp" },
+ { HNS3_CAPS_SIMPLE_BD_B, "simple_bd" },
{ HNS3_CAPS_TX_PUSH_B, "tx_push" },
{ HNS3_CAPS_PHY_IMP_B, "phy_imp" },
{ HNS3_CAPS_TQP_TXRX_INDEP_B, "tqp_txrx_indep" },
@@ -489,6 +490,8 @@ hns3_parse_capability(struct hns3_hw *hw,
hns3_warn(hw, "ignore PTP capability due to lack of "
"rxd advanced layout capability.");
}
+ if (hns3_get_bit(caps, HNS3_CAPS_SIMPLE_BD_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_SIMPLE_BD_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index eb394c9dec..4abe0f1d13 100644
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -313,6 +313,7 @@ enum HNS3_CAPS_BITS {
*/
HNS3_CAPS_FD_QUEUE_REGION_B = 2,
HNS3_CAPS_PTP_B,
+ HNS3_CAPS_SIMPLE_BD_B = 5,
HNS3_CAPS_TX_PUSH_B = 6,
HNS3_CAPS_PHY_IMP_B = 7,
HNS3_CAPS_TQP_TXRX_INDEP_B,
diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c
index ae62bb56c8..8d723f1876 100644
--- a/drivers/net/hns3/hns3_dump.c
+++ b/drivers/net/hns3/hns3_dump.c
@@ -96,6 +96,7 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw
*hw)
{HNS3_DEV_SUPPORT_TX_PUSH_B, "TX PUSH"},
{HNS3_DEV_SUPPORT_INDEP_TXRX_B, "INDEP TXRX"},
{HNS3_DEV_SUPPORT_STASH_B, "STASH"},
+ {HNS3_DEV_SUPPORT_SIMPLE_BD_B, "SIMPLE BD"},
{HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, "RXD Advanced Layout"},
{HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, "OUTER UDP CKSUM"},
{HNS3_DEV_SUPPORT_RAS_IMP_B, "RAS IMP"},
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 9acc5a3d7e..ee4dd18d7b 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -886,6 +886,7 @@ enum hns3_dev_cap {
HNS3_DEV_SUPPORT_TX_PUSH_B,
HNS3_DEV_SUPPORT_INDEP_TXRX_B,
HNS3_DEV_SUPPORT_STASH_B,
+ HNS3_DEV_SUPPORT_SIMPLE_BD_B,
HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
HNS3_DEV_SUPPORT_RAS_IMP_B,
diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
index 4065c519c3..8c3355bbde 100644
--- a/drivers/net/hns3/hns3_rxtx.c
+++ b/drivers/net/hns3/hns3_rxtx.c
@@ -3046,6 +3046,10 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t
idx, uint16_t nb_desc,
HNS3_PORT_BASE_VLAN_ENABLE;
else
txq->pvid_sw_shift_en = false;
+
+ if (hns3_dev_get_support(hw, SIMPLE_BD))
+ txq->simple_bd_enable = true;
+
txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
txq->configured = true;
txq->io_base = (void *)((char *)hw->io_base +
@@ -3162,7 +3166,7 @@ hns3_set_tso(struct hns3_desc *desc, uint32_t paylen,
struct rte_mbuf *rxm)
return;
desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
- desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
+ desc->tx.ckst_mss |= rte_cpu_to_le_16(rxm->tso_segsz);
}
static inline void
@@ -3901,6 +3905,50 @@ hns3_prep_pkts(__rte_unused void *tx_queue, struct
rte_mbuf **tx_pkts,
return i;
}
+static inline int
+hns3_handle_simple_bd(struct hns3_tx_queue *txq, struct hns3_desc *desc,
+ struct rte_mbuf *m)
+{
+#define HNS3_TCP_CSUM_OFFSET 16
+#define HNS3_UDP_CSUM_OFFSET 6
+
+ /*
+* In HIP09, NIC HW support Tx simple BD mode that the HW will
+* calculate the checksum from the start position of checksum and fill
+* th
[PATCH v1] crypto/ipsec_mb: add digest encrypted feature in AESNI_MB
AESNI_MB PMD does not support Digest Encrypted. This patch adds partial support for this feature. Signed-off-by: Brian Dooley --- Some out-of-place tests are still failing. Only some in-place tests are passing. Working on adding support for this feature in v2. --- app/test/1.diff| 0 drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 3 ++- 2 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 app/test/1.diff diff --git a/app/test/1.diff b/app/test/1.diff new file mode 100644 index 00..e69de29bb2 diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c index ac20d01937..fbb556af87 100644 --- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c +++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c @@ -2335,7 +2335,8 @@ RTE_INIT(ipsec_mb_register_aesni_mb) RTE_CRYPTODEV_FF_IN_PLACE_SGL | RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT | RTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT | - RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT; + RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT | + RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED; aesni_mb_data->internals_priv_size = 0; aesni_mb_data->ops = &aesni_mb_pmd_ops; -- 2.25.1
RE: [RFC] lib: set/get max memzone segments
> From: Thomas Monjalon [mailto:tho...@monjalon.net] > Sent: Friday, 21 April 2023 10.35 > > 20/04/2023 20:20, Tyler Retzlaff: > > On Thu, Apr 20, 2023 at 09:43:28AM +0200, Thomas Monjalon wrote: > > > 19/04/2023 16:51, Tyler Retzlaff: > > > > On Wed, Apr 19, 2023 at 11:36:34AM +0300, Ophir Munk wrote: > > > > > In current DPDK the RTE_MAX_MEMZONE definition is unconditionally hard > > > > > coded as 2560. For applications requiring different values of this > > > > > parameter – it is more convenient to set the max value via an rte API > - > > > > > rather than changing the dpdk source code per application. In many > > > > > organizations, the possibility to compile a private DPDK library for a > > > > > particular application does not exist at all. With this option there > is > > > > > no need to recompile DPDK and it allows using an in-box packaged DPDK. > > > > > An example usage for updating the RTE_MAX_MEMZONE would be of an > > > > > application that uses the DPDK mempool library which is based on DPDK > > > > > memzone library. The application may need to create a number of > > > > > steering tables, each of which will require its own mempool > allocation. > > > > > This commit is not about how to optimize the application usage of > > > > > mempool nor about how to improve the mempool implementation based on > > > > > memzone. It is about how to make the max memzone definition - run- > time > > > > > customized. > > > > > This commit adds an API which must be called before rte_eal_init(): > > > > > rte_memzone_max_set(int max). If not called, the default memzone > > > > > (RTE_MAX_MEMZONE) is used. There is also an API to query the > effective > > > > > max memzone: rte_memzone_max_get(). > > > > > > > > > > Signed-off-by: Ophir Munk > > > > > --- > > > > > > > > the use case of each application may want a different non-hard coded > > > > value makes sense. > > > > > > > > it's less clear to me that requiring it be called before eal init makes > > > > sense over just providing it as configuration to eal init so that it is > > > > composed. > > > > > > Why do you think it would be better as EAL init option? > > > From an API perspective, I think it is simpler to call a dedicated > function. > > > And I don't think a user wants to deal with it when starting the > application. > > > > because a dedicated function that can be called detached from the eal > > state enables an opportunity for accidental and confusing use outside > > the correct context. > > > > i know the above prescribes not to do this but. > > > > now you can call set after eal init, but we protect about calling it > > after init by failing. what do we do sensibly with the failure? > > It would be a developer mistake which could be fix during development stage > very easily. I don't see a problem here. Why is this not just a command line parameter, like other EAL configuration options? Do any other pre-init APIs exist, or are you introducing a new design pattern for configuring EAL? Any application can simply modify the command line parameters before calling EAL init. It doesn't need to pass the command line parameters as-is to EAL init. In other words: There is an existing design pattern for configuring EAL, why introduce a new design pattern? If we want to expose APIs for configuring EAL instead of passing command line parameters, such APIs should be added for all EAL configuration parameters. That would be nice, but I dislike that some EAL configuration parameters must be passed using one method and some other passed using another method.
[PATCH 0/8] add AESNI_MB optimisations
This patchset adds some optimisations for AESNI_MB PMD, many based on features that are available in intel-ipsec-mb v1.3 and future release v1.4. Marcel Cornu (1): crypto/ipsec_mb: use burst API in aesni_mb Pablo de Lara (7): crypto/ipsec_mb: use GMAC dedicated algorithms crypto/ipsec_mb: use new SGL API crypto/ipsec_mb: remove unneeded fields in crypto session crypto/ipsec_mb: store template job crypto/ipsec_mb: optimize for GCM case crypto/ipsec_mb: do not free linear_sgl always crypto/ipsec_mb: set and use session ID drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 915 drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 32 +- 2 files changed, 584 insertions(+), 363 deletions(-) -- 2.25.1
[PATCH 1/8] crypto/ipsec_mb: use GMAC dedicated algorithms
From: Pablo de Lara
AES-GMAC can be done with auth-only enums
IMB_AES_GMAC_128/192/256, which allows another cipher
algorithm to be used, instead of being part of AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 104 +++--
1 file changed, 47 insertions(+), 57 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index ac20d01937..c53548aa3b 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -57,8 +57,7 @@ is_aead_algo(IMB_HASH_ALG hash_alg, IMB_CIPHER_MODE
cipher_mode)
{
return (hash_alg == IMB_AUTH_CHACHA20_POLY1305 ||
hash_alg == IMB_AUTH_AES_CCM ||
- (hash_alg == IMB_AUTH_AES_GMAC &&
- cipher_mode == IMB_CIPHER_GCM));
+ cipher_mode == IMB_CIPHER_GCM);
}
/** Set session authentication parameters */
@@ -155,7 +154,6 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR *mb_mgr,
} else
sess->cipher.direction = IMB_DIR_DECRYPT;
- sess->auth.algo = IMB_AUTH_AES_GMAC;
if (sess->auth.req_digest_len >
get_digest_byte_length(IMB_AUTH_AES_GMAC)) {
IPSEC_MB_LOG(ERR, "Invalid digest size\n");
@@ -167,16 +165,19 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR
*mb_mgr,
switch (xform->auth.key.length) {
case IMB_KEY_128_BYTES:
+ sess->auth.algo = IMB_AUTH_AES_GMAC_128;
IMB_AES128_GCM_PRE(mb_mgr, xform->auth.key.data,
&sess->cipher.gcm_key);
sess->cipher.key_length_in_bytes = IMB_KEY_128_BYTES;
break;
case IMB_KEY_192_BYTES:
+ sess->auth.algo = IMB_AUTH_AES_GMAC_192;
IMB_AES192_GCM_PRE(mb_mgr, xform->auth.key.data,
&sess->cipher.gcm_key);
sess->cipher.key_length_in_bytes = IMB_KEY_192_BYTES;
break;
case IMB_KEY_256_BYTES:
+ sess->auth.algo = IMB_AUTH_AES_GMAC_256;
IMB_AES256_GCM_PRE(mb_mgr, xform->auth.key.data,
&sess->cipher.gcm_key);
sess->cipher.key_length_in_bytes = IMB_KEY_256_BYTES;
@@ -1039,19 +1040,20 @@ set_cpu_mb_job_params(IMB_JOB *job, struct
aesni_mb_session *session,
break;
case IMB_AUTH_AES_GMAC:
- if (session->cipher.mode == IMB_CIPHER_GCM) {
- job->u.GCM.aad = aad->va;
- job->u.GCM.aad_len_in_bytes = session->aead.aad_len;
- } else {
- /* For GMAC */
- job->u.GCM.aad = buf;
- job->u.GCM.aad_len_in_bytes = len;
- job->cipher_mode = IMB_CIPHER_GCM;
- }
+ job->u.GCM.aad = aad->va;
+ job->u.GCM.aad_len_in_bytes = session->aead.aad_len;
job->enc_keys = &session->cipher.gcm_key;
job->dec_keys = &session->cipher.gcm_key;
break;
+ case IMB_AUTH_AES_GMAC_128:
+ case IMB_AUTH_AES_GMAC_192:
+ case IMB_AUTH_AES_GMAC_256:
+ job->u.GMAC._key = &session->cipher.gcm_key;
+ job->u.GMAC._iv = iv->va;
+ job->u.GMAC.iv_len_in_bytes = session->iv.length;
+ break;
+
case IMB_AUTH_CHACHA20_POLY1305:
job->u.CHACHA20_POLY1305.aad = aad->va;
job->u.CHACHA20_POLY1305.aad_len_in_bytes =
@@ -1091,16 +1093,10 @@ set_cpu_mb_job_params(IMB_JOB *job, struct
aesni_mb_session *session,
job->dst = (uint8_t *)buf + sofs.ofs.cipher.head;
job->cipher_start_src_offset_in_bytes = sofs.ofs.cipher.head;
job->hash_start_src_offset_in_bytes = sofs.ofs.auth.head;
- if (job->hash_alg == IMB_AUTH_AES_GMAC &&
- session->cipher.mode != IMB_CIPHER_GCM) {
- job->msg_len_to_hash_in_bytes = 0;
- job->msg_len_to_cipher_in_bytes = 0;
- } else {
- job->msg_len_to_hash_in_bytes = len - sofs.ofs.auth.head -
- sofs.ofs.auth.tail;
- job->msg_len_to_cipher_in_bytes = len - sofs.ofs.cipher.head -
- sofs.ofs.cipher.tail;
- }
+ job->msg_len_to_hash_in_bytes = len - sofs.ofs.auth.head -
+ sofs.ofs.auth.tail;
+ job->msg_len_to_cipher_in_bytes = len - sofs.ofs.cipher.head -
+ sofs.ofs.cipher.tail;
job->user_data = udata;
}
@@ -1184,8 +1180,6 @@ sgl_linear_cipher_auth_len(IMB_JOB *job, uint64_t
*auth_len)
job->hash_alg == IMB_AUTH_ZUC_EIA3_BITLEN)
[PATCH 2/8] crypto/ipsec_mb: use burst API in aesni_mb
From: Marcel Cornu
Use new ipsec_mb burst API in dequeue burst function,
when ipsec_mb version is v1.3 or newer.
Signed-off-by: Marcel Cornu
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 133 -
1 file changed, 132 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index c53548aa3b..5789b82d8e 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -9,6 +9,10 @@ struct aesni_mb_op_buf_data {
uint32_t offset;
};
+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM
+static IMB_JOB *jobs[IMB_MAX_BURST_SIZE] = {NULL};
+#endif
+
/**
* Calculate the authentication pre-computes
*
@@ -1974,6 +1978,133 @@ set_job_null_op(IMB_JOB *job, struct rte_crypto_op *op)
return job;
}
+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM
+static uint16_t
+aesni_mb_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,
+ uint16_t nb_ops)
+{
+ struct ipsec_mb_qp *qp = queue_pair;
+ IMB_MGR *mb_mgr = qp->mb_mgr;
+ struct rte_crypto_op *op;
+ struct rte_crypto_op *deqd_ops[IMB_MAX_BURST_SIZE];
+ IMB_JOB *job;
+ int retval, processed_jobs = 0;
+ uint16_t i, nb_jobs;
+
+ if (unlikely(nb_ops == 0 || mb_mgr == NULL))
+ return 0;
+
+ uint8_t digest_idx = qp->digest_idx;
+ uint16_t burst_sz = (nb_ops > IMB_MAX_BURST_SIZE) ?
+ IMB_MAX_BURST_SIZE : nb_ops;
+
+ /*
+* If nb_ops is greater than the max supported
+* ipsec_mb burst size, then process in bursts of
+* IMB_MAX_BURST_SIZE until all operations are submitted
+*/
+ while (nb_ops) {
+ uint16_t nb_submit_ops;
+ uint16_t n = (nb_ops / burst_sz) ?
+ burst_sz : nb_ops;
+
+ while (unlikely((IMB_GET_NEXT_BURST(mb_mgr, n, jobs)) < n)) {
+ /*
+* Not enough free jobs in the queue
+* Flush n jobs until enough jobs available
+*/
+ nb_jobs = IMB_FLUSH_BURST(mb_mgr, n, jobs);
+ for (i = 0; i < nb_jobs; i++) {
+ job = jobs[i];
+
+ op = post_process_mb_job(qp, job);
+ if (op) {
+ ops[processed_jobs++] = op;
+ qp->stats.dequeued_count++;
+ } else {
+ qp->stats.dequeue_err_count++;
+ break;
+ }
+ }
+ }
+
+ /*
+* Get the next operations to process from ingress queue.
+* There is no need to return the job to the IMB_MGR
+* if there are no more operations to process, since
+* the IMB_MGR can use that pointer again in next
+* get_next calls.
+*/
+ nb_submit_ops = rte_ring_dequeue_burst(qp->ingress_queue,
+ (void **)deqd_ops, n, NULL);
+ for (i = 0; i < nb_submit_ops; i++) {
+ job = jobs[i];
+ op = deqd_ops[i];
+
+#ifdef AESNI_MB_DOCSIS_SEC_ENABLED
+ if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
+ retval = set_sec_mb_job_params(job, qp, op,
+ &digest_idx);
+ else
+#endif
+ retval = set_mb_job_params(job, qp, op,
+ &digest_idx, mb_mgr);
+
+ if (unlikely(retval != 0)) {
+ qp->stats.dequeue_err_count++;
+ set_job_null_op(job, op);
+ }
+ }
+
+ /* Submit jobs to multi-buffer for processing */
+#ifdef RTE_LIBRTE_PMD_AESNI_MB_DEBUG
+ int err = 0;
+
+ nb_jobs = IMB_SUBMIT_BURST(mb_mgr, nb_submit_ops, jobs);
+ err = imb_get_errno(mb_mgr);
+ if (err)
+ IPSEC_MB_LOG(ERR, "%s", imb_get_strerror(err));
+#else
+ nb_jobs = IMB_SUBMIT_BURST_NOCHECK(mb_mgr,
+ nb_submit_ops, jobs);
+#endif
+ for (i = 0; i < nb_jobs; i++) {
+ job = jobs[i];
+
+ op = post_process_mb_job(qp, job);
+ if (op) {
+ ops[processed_jobs++] = op;
+ qp->stats.dequeued_count++;
+ } else {
+
[PATCH 3/8] crypto/ipsec_mb: use new SGL API
From: Pablo de Lara
Use new SGL API available from IPSec Multi-buffer v1.3,
where only one function call is required to submit
all segments to be processed in an SGL scenario.
Instead of having one call per segment, there is only
one call per buffer.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 187 +++-
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 7 +
2 files changed, 153 insertions(+), 41 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index 5789b82d8e..3ebbade8ca 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -1241,6 +1241,141 @@ imb_lib_support_sgl_algo(IMB_CIPHER_MODE alg)
return 0;
}
+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM
+static inline int
+single_sgl_job(IMB_JOB *job, struct rte_crypto_op *op,
+ int oop, uint32_t offset, struct rte_mbuf *m_src,
+ struct rte_mbuf *m_dst, struct IMB_SGL_IOV *sgl_segs)
+{
+ uint32_t num_segs = 0;
+ struct aesni_mb_op_buf_data src_sgl = {0};
+ struct aesni_mb_op_buf_data dst_sgl = {0};
+ uint32_t total_len;
+
+ job->sgl_state = IMB_SGL_ALL;
+
+ src_sgl.m = m_src;
+ src_sgl.offset = offset;
+
+ while (src_sgl.offset >= src_sgl.m->data_len) {
+ src_sgl.offset -= src_sgl.m->data_len;
+ src_sgl.m = src_sgl.m->next;
+
+ RTE_ASSERT(src_sgl.m != NULL);
+ }
+
+ if (oop) {
+ dst_sgl.m = m_dst;
+ dst_sgl.offset = offset;
+
+ while (dst_sgl.offset >= dst_sgl.m->data_len) {
+ dst_sgl.offset -= dst_sgl.m->data_len;
+ dst_sgl.m = dst_sgl.m->next;
+
+ RTE_ASSERT(dst_sgl.m != NULL);
+ }
+ }
+ total_len = op->sym->aead.data.length;
+
+ while (total_len != 0) {
+ uint32_t data_len, part_len;
+
+ if (src_sgl.m == NULL) {
+ IPSEC_MB_LOG(ERR, "Invalid source buffer");
+ return -EINVAL;
+ }
+
+ data_len = src_sgl.m->data_len - src_sgl.offset;
+
+ sgl_segs[num_segs].in = rte_pktmbuf_mtod_offset(src_sgl.m,
uint8_t *,
+ src_sgl.offset);
+
+ if (dst_sgl.m != NULL) {
+ if (dst_sgl.m->data_len - dst_sgl.offset == 0) {
+ dst_sgl.m = dst_sgl.m->next;
+ if (dst_sgl.m == NULL) {
+ IPSEC_MB_LOG(ERR, "Invalid destination
buffer");
+ return -EINVAL;
+ }
+ dst_sgl.offset = 0;
+ }
+ part_len = RTE_MIN(data_len, (dst_sgl.m->data_len -
+ dst_sgl.offset));
+ sgl_segs[num_segs].out =
rte_pktmbuf_mtod_offset(dst_sgl.m,
+ uint8_t *, dst_sgl.offset);
+ dst_sgl.offset += part_len;
+ } else {
+ part_len = RTE_MIN(data_len, total_len);
+ sgl_segs[num_segs].out =
rte_pktmbuf_mtod_offset(src_sgl.m, uint8_t *,
+ src_sgl.offset);
+ }
+
+ sgl_segs[num_segs].len = part_len;
+
+ total_len -= part_len;
+
+ if (part_len != data_len) {
+ src_sgl.offset += part_len;
+ } else {
+ src_sgl.m = src_sgl.m->next;
+ src_sgl.offset = 0;
+ }
+ num_segs++;
+ }
+ job->num_sgl_io_segs = num_segs;
+ job->sgl_io_segs = sgl_segs;
+ return 0;
+}
+#endif
+
+static inline int
+multi_sgl_job(IMB_JOB *job, struct rte_crypto_op *op,
+ int oop, uint32_t offset, struct rte_mbuf *m_src,
+ struct rte_mbuf *m_dst, IMB_MGR *mb_mgr)
+{
+ int ret;
+ IMB_JOB base_job;
+ struct aesni_mb_op_buf_data src_sgl = {0};
+ struct aesni_mb_op_buf_data dst_sgl = {0};
+ uint32_t total_len;
+
+ base_job = *job;
+ job->sgl_state = IMB_SGL_INIT;
+ job = IMB_SUBMIT_JOB(mb_mgr);
+ total_len = op->sym->aead.data.length;
+
+ src_sgl.m = m_src;
+ src_sgl.offset = offset;
+
+ while (src_sgl.offset >= src_sgl.m->data_len) {
+ src_sgl.offset -= src_sgl.m->data_len;
+ src_sgl.m = src_sgl.m->next;
+
+ RTE_ASSERT(src_sgl.m != NULL);
+ }
+
+ if (oop) {
+ dst_sgl.m = m_dst;
+ dst_sgl.offset = offset;
+
+ while (dst_sgl.offset >= dst_sgl.m->data_len) {
+ dst_sgl.offset -= dst_sgl.m->data_l
[PATCH 4/8] crypto/ipsec_mb: remove unneeded fields in crypto session
From: Pablo de Lara
Cipher direction, cipher mode and hash algorithm are
duplicated in crypto session.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
index e17b53e4fe..3cf44f8bc4 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
@@ -852,9 +852,6 @@ get_digest_byte_length(IMB_HASH_ALG algo)
/** AES-NI multi-buffer private session structure */
struct aesni_mb_session {
- IMB_CIPHER_MODE cipher_mode;
- IMB_CIPHER_DIRECTION cipher_direction;
- IMB_HASH_ALG hash_alg;
IMB_CHAIN_ORDER chain_order;
/* common job fields */
struct {
--
2.25.1
[PATCH 5/8] crypto/ipsec_mb: store template job
From: Pablo de Lara
Store template IMB_JOB in session that
will have filled all session-related fields.
These fields include cipher direction, chain order, cipher mode,
hash algorithm, key length, IV lengths, AAD length, digest length,
and key pointers.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 403
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 20 +-
2 files changed, 159 insertions(+), 264 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index 3ebbade8ca..8ccdd2ad2e 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -76,7 +76,7 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR *mb_mgr,
uint32_t auth_precompute = 1;
if (xform == NULL) {
- sess->auth.algo = IMB_AUTH_NULL;
+ sess->template_job.hash_alg = IMB_AUTH_NULL;
return 0;
}
@@ -87,7 +87,6 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR *mb_mgr,
/* Set IV parameters */
sess->auth_iv.offset = xform->auth.iv.offset;
- sess->auth_iv.length = xform->auth.iv.length;
/* Set the request digest size */
sess->auth.req_digest_len = xform->auth.digest_length;
@@ -97,13 +96,13 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR *mb_mgr,
/* Set Authentication Parameters */
if (xform->auth.algo == RTE_CRYPTO_AUTH_NULL) {
- sess->auth.algo = IMB_AUTH_NULL;
- sess->auth.gen_digest_len = 0;
+ sess->template_job.hash_alg = IMB_AUTH_NULL;
+ sess->template_job.auth_tag_output_len_in_bytes = 0;
return 0;
}
if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_XCBC_MAC) {
- sess->auth.algo = IMB_AUTH_AES_XCBC;
+ sess->template_job.hash_alg = IMB_AUTH_AES_XCBC;
uint16_t xcbc_mac_digest_len =
get_truncated_digest_byte_length(IMB_AUTH_AES_XCBC);
@@ -111,18 +110,21 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR
*mb_mgr,
IPSEC_MB_LOG(ERR, "Invalid digest size\n");
return -EINVAL;
}
- sess->auth.gen_digest_len = sess->auth.req_digest_len;
+ sess->template_job.auth_tag_output_len_in_bytes =
sess->auth.req_digest_len;
IMB_AES_XCBC_KEYEXP(mb_mgr, xform->auth.key.data,
sess->auth.xcbc.k1_expanded,
sess->auth.xcbc.k2, sess->auth.xcbc.k3);
+ sess->template_job.u.XCBC._k1_expanded =
sess->auth.xcbc.k1_expanded;
+ sess->template_job.u.XCBC._k2 = sess->auth.xcbc.k2;
+ sess->template_job.u.XCBC._k3 = sess->auth.xcbc.k3;
return 0;
}
if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_CMAC) {
uint32_t dust[4*15];
- sess->auth.algo = IMB_AUTH_AES_CMAC;
+ sess->template_job.hash_alg = IMB_AUTH_AES_CMAC;
uint16_t cmac_digest_len =
get_digest_byte_length(IMB_AUTH_AES_CMAC);
@@ -140,70 +142,74 @@ aesni_mb_set_session_auth_parameters(const IMB_MGR
*mb_mgr,
* the requested number of bytes.
*/
if (sess->auth.req_digest_len < 4)
- sess->auth.gen_digest_len = cmac_digest_len;
+ sess->template_job.auth_tag_output_len_in_bytes =
cmac_digest_len;
else
- sess->auth.gen_digest_len = sess->auth.req_digest_len;
+ sess->template_job.auth_tag_output_len_in_bytes =
sess->auth.req_digest_len;
IMB_AES_KEYEXP_128(mb_mgr, xform->auth.key.data,
sess->auth.cmac.expkey, dust);
IMB_AES_CMAC_SUBKEY_GEN_128(mb_mgr, sess->auth.cmac.expkey,
sess->auth.cmac.skey1, sess->auth.cmac.skey2);
+ sess->template_job.u.CMAC._key_expanded =
sess->auth.cmac.expkey;
+ sess->template_job.u.CMAC._skey1 = sess->auth.cmac.skey1;
+ sess->template_job.u.CMAC._skey2 = sess->auth.cmac.skey2;
return 0;
}
if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
if (xform->auth.op == RTE_CRYPTO_AUTH_OP_GENERATE) {
- sess->cipher.direction = IMB_DIR_ENCRYPT;
- sess->chain_order = IMB_ORDER_CIPHER_HASH;
+ sess->template_job.cipher_direction = IMB_DIR_ENCRYPT;
+ sess->template_job.chain_order = IMB_ORDER_CIPHER_HASH;
} else
- sess->cipher.direction = IMB_DIR_DECRYPT;
+ sess->template_job.cipher_direction = IMB_DIR_DECRYPT;
i
[PATCH 6/8] crypto/ipsec_mb: optimize for GCM case
From: Pablo de Lara
Use a separate code path when dealing with AES-GCM.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 88 +++---
1 file changed, 79 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index 8ccdd2ad2e..9ca679606f 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -1366,6 +1366,70 @@ multi_sgl_job(IMB_JOB *job, struct rte_crypto_op *op,
}
return 0;
}
+
+static inline int
+set_gcm_job(IMB_MGR *mb_mgr, IMB_JOB *job, const uint8_t sgl,
+ struct aesni_mb_qp_data *qp_data,
+ struct rte_crypto_op *op, uint8_t *digest_idx,
+ const struct aesni_mb_session *session,
+ struct rte_mbuf *m_src, struct rte_mbuf *m_dst,
+ const int oop)
+{
+ const uint32_t m_offset = op->sym->aead.data.offset;
+
+ job->u.GCM.aad = op->sym->aead.aad.data;
+ if (sgl) {
+ job->u.GCM.ctx = &qp_data->gcm_sgl_ctx;
+ job->cipher_mode = IMB_CIPHER_GCM_SGL;
+ job->hash_alg = IMB_AUTH_GCM_SGL;
+ job->hash_start_src_offset_in_bytes = 0;
+ job->msg_len_to_hash_in_bytes = 0;
+ job->msg_len_to_cipher_in_bytes = 0;
+ job->cipher_start_src_offset_in_bytes = 0;
+ } else {
+ job->hash_start_src_offset_in_bytes =
+ op->sym->aead.data.offset;
+ job->msg_len_to_hash_in_bytes =
+ op->sym->aead.data.length;
+ job->cipher_start_src_offset_in_bytes =
+ op->sym->aead.data.offset;
+ job->msg_len_to_cipher_in_bytes = op->sym->aead.data.length;
+ }
+
+ if (session->auth.operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
+ job->auth_tag_output = qp_data->temp_digests[*digest_idx];
+ *digest_idx = (*digest_idx + 1) % IMB_MAX_JOBS;
+ } else {
+ job->auth_tag_output = op->sym->aead.digest.data;
+ }
+
+ job->iv = rte_crypto_op_ctod_offset(op, uint8_t *,
+ session->iv.offset);
+
+ /* Set user data to be crypto operation data struct */
+ job->user_data = op;
+
+ if (sgl) {
+ job->src = NULL;
+ job->dst = NULL;
+
+#if IMB_VERSION(1, 2, 0) < IMB_VERSION_NUM
+ if (m_src->nb_segs <= MAX_NUM_SEGS)
+ return single_sgl_job(job, op, oop,
+ m_offset, m_src, m_dst,
+ qp_data->sgl_segs);
+ else
+#endif
+ return multi_sgl_job(job, op, oop,
+ m_offset, m_src, m_dst, mb_mgr);
+ } else {
+ job->src = rte_pktmbuf_mtod(m_src, uint8_t *);
+ job->dst = rte_pktmbuf_mtod_offset(m_dst, uint8_t *, m_offset);
+ }
+
+ return 0;
+}
+
/**
* Process a crypto operation and complete a IMB_JOB job structure for
* submission to the multi buffer library for processing.
@@ -1403,10 +1467,10 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
return -1;
}
- memcpy(job, &session->template_job, sizeof(IMB_JOB));
+ const IMB_CIPHER_MODE cipher_mode =
+ session->template_job.cipher_mode;
- /* Set authentication parameters */
- const int aead = is_aead_algo(job->hash_alg, job->cipher_mode);
+ memcpy(job, &session->template_job, sizeof(IMB_JOB));
if (!op->sym->m_dst) {
/* in-place operation */
@@ -1424,10 +1488,17 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
if (m_src->nb_segs > 1 || m_dst->nb_segs > 1) {
sgl = 1;
- if (!imb_lib_support_sgl_algo(job->cipher_mode))
+ if (!imb_lib_support_sgl_algo(cipher_mode))
lb_sgl = 1;
}
+ if (cipher_mode == IMB_CIPHER_GCM)
+ return set_gcm_job(mb_mgr, job, sgl, qp_data,
+ op, digest_idx, session, m_src, m_dst, oop);
+
+ /* Set authentication parameters */
+ const int aead = is_aead_algo(job->hash_alg, cipher_mode);
+
switch (job->hash_alg) {
case IMB_AUTH_AES_CCM:
job->u.CCM.aad = op->sym->aead.aad.data + 18;
@@ -1474,13 +1545,12 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
else
m_offset = op->sym->cipher.data.offset;
- if (job->cipher_mode == IMB_CIPHER_ZUC_EEA3) {
+ if (cipher_mode == IMB_CIPHER_ZUC_EEA3)
m_offset >>= 3;
- } else if (job->cipher_mode == IMB_CIPHER_SNOW3G_UEA2_BITLEN) {
+ else if (cipher_mode == IMB_CIPHER_SNOW3G_UEA2_BITLEN)
m_offset = 0;
- } else if (job->cipher_mode == IMB_CIP
[PATCH 7/8] crypto/ipsec_mb: do not free linear_sgl always
From: Pablo de Lara
linear_sgl buffer only needs to be freed
if it was allocated previously.
Signed-off-by: Pablo de Lara
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index 9ca679606f..f23016c9c3 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -1898,6 +1898,7 @@ post_process_mb_job(struct ipsec_mb_qp *qp, IMB_JOB *job)
struct rte_crypto_op *op = (struct rte_crypto_op *)job->user_data;
struct aesni_mb_session *sess = NULL;
uint8_t *linear_buf = NULL;
+ int sgl = 0;
#ifdef AESNI_MB_DOCSIS_SEC_ENABLED
uint8_t is_docsis_sec = 0;
@@ -1923,6 +1924,8 @@ post_process_mb_job(struct ipsec_mb_qp *qp, IMB_JOB *job)
op->sym->m_dst->nb_segs > 1)) &&
!imb_lib_support_sgl_algo(job->cipher_mode)) {
linear_buf = (uint8_t *) job->user_data2;
+ sgl = 1;
+
post_process_sgl_linear(op, job, sess,
linear_buf);
}
@@ -1952,7 +1955,8 @@ post_process_mb_job(struct ipsec_mb_qp *qp, IMB_JOB *job)
default:
op->status = RTE_CRYPTO_OP_STATUS_ERROR;
}
- rte_free(linear_buf);
+ if (sgl)
+ rte_free(linear_buf);
}
/* Free session if a session-less crypto op */
--
2.25.1
[PATCH 8/8] crypto/ipsec_mb: set and use session ID
From: Pablo de Lara
When creating a session, get the session ID that
defines the fixed session parameters and store it in the private data.
When retrieving IMB_JOB's, if their internal session ID matches
the one in the private session data, these fixed session parameters
do not need to be filled again.
Signed-off-by: Pablo de Lara
Signed-off-by: Ciara Power
---
drivers/crypto/ipsec_mb/pmd_aesni_mb.c | 22 -
drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h | 2 ++
2 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
index f23016c9c3..8600f41897 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb.c
@@ -845,6 +845,10 @@ aesni_mb_session_configure(IMB_MGR *mb_mgr,
}
}
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ sess->session_id = imb_set_session(mb_mgr, &sess->template_job);
+#endif
+
return 0;
}
@@ -977,6 +981,10 @@ aesni_mb_set_docsis_sec_session_parameters(
goto error_exit;
}
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ ipsec_sess->session_id = imb_set_session(mb_mgr,
&ipsec_sess->template_job);
+#endif
+
error_exit:
free_mb_mgr(mb_mgr);
return ret;
@@ -1386,6 +1394,9 @@ set_gcm_job(IMB_MGR *mb_mgr, IMB_JOB *job, const uint8_t
sgl,
job->msg_len_to_hash_in_bytes = 0;
job->msg_len_to_cipher_in_bytes = 0;
job->cipher_start_src_offset_in_bytes = 0;
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ imb_set_session(mb_mgr, job);
+#endif
} else {
job->hash_start_src_offset_in_bytes =
op->sym->aead.data.offset;
@@ -1470,7 +1481,10 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
const IMB_CIPHER_MODE cipher_mode =
session->template_job.cipher_mode;
- memcpy(job, &session->template_job, sizeof(IMB_JOB));
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ if (job->session_id != session->session_id)
+#endif
+ memcpy(job, &session->template_job, sizeof(IMB_JOB));
if (!op->sym->m_dst) {
/* in-place operation */
@@ -1510,6 +1524,9 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
job->u.GCM.ctx = &qp_data->gcm_sgl_ctx;
job->cipher_mode = IMB_CIPHER_GCM_SGL;
job->hash_alg = IMB_AUTH_GCM_SGL;
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ imb_set_session(mb_mgr, job);
+#endif
}
break;
case IMB_AUTH_AES_GMAC_128:
@@ -1534,6 +1551,9 @@ set_mb_job_params(IMB_JOB *job, struct ipsec_mb_qp *qp,
job->u.CHACHA20_POLY1305.ctx = &qp_data->chacha_sgl_ctx;
job->cipher_mode = IMB_CIPHER_CHACHA20_POLY1305_SGL;
job->hash_alg = IMB_AUTH_CHACHA20_POLY1305_SGL;
+#if IMB_VERSION(1, 3, 0) < IMB_VERSION_NUM
+ imb_set_session(mb_mgr, job);
+#endif
}
break;
default:
diff --git a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
index ce9a6e4886..9b7c9edb6d 100644
--- a/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
+++ b/drivers/crypto/ipsec_mb/pmd_aesni_mb_priv.h
@@ -854,6 +854,8 @@ get_digest_byte_length(IMB_HASH_ALG algo)
struct aesni_mb_session {
IMB_JOB template_job;
/*< Template job structure */
+ uint32_t session_id;
+ /*< IPSec MB session ID */
struct {
uint16_t offset;
} iv;
--
2.25.1
[PATCH] ci: switch to Fedora 37
Fedora 35 has been declared EOL in 2022/12 (see [1]). Fedora 36 will soon be EOL too. Move to Fedora 37. Fedora 37 libbpf does not support AF_XDP anymore, now provided by libxdp. 1: https://docs.fedoraproject.org/en-US/releases/eol/ Signed-off-by: David Marchand --- .github/workflows/build.yml | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index edd39cbd62..7322eb59b7 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -149,7 +149,7 @@ jobs: fail-fast: false matrix: config: - - image: fedora:35 + - image: fedora:37 steps: - name: Generate various keys @@ -198,9 +198,9 @@ jobs: fail-fast: false matrix: config: - - image: fedora:35 + - image: fedora:37 compiler: gcc - - image: fedora:35 + - image: fedora:37 compiler: clang steps: @@ -250,7 +250,7 @@ jobs: run: docker exec -i dpdk dnf update -y || true - name: Install packages run: docker exec -i dpdk dnf install -y ccache jansson-devel -libarchive-devel libatomic libbsd-devel libbpf-devel libfdt-devel +libarchive-devel libatomic libbsd-devel libxdp-devel libfdt-devel libpcap-devel ninja-build numactl-devel openssl-devel python3-pip python3-pyelftools python3-setuptools python3-wheel rdma-core-devel zlib-devel -- 2.40.0
[PATCH v3 0/5] Support AMD CDX bus, for FPGA based CDX devices. The CDX
It uses sysfs interface and the vfio-cdx driver to discover and initialize the CDX devices. The CDX bus and VFIO support is available at Xilinx open source tree: https://github.com/Xilinx/linux-xlnx (drivers/cdx/ and drivers/vfio/cdx) Linux CDX bus patches has been added into linux next: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/cdx VFIO patches are also submitted in upstream: https://www.spinics.net/lists/kvm/msg310623.html CDX is a Hardware Architecture designed for AMD FPGA devices. It consists of mechanism for interaction between FPGA, Firmware and the APUs (Application CPUs). Firmware resides on RPU (Realtime CPUs) which interacts with the FPGA program manager and the APUs. The RPU provides memory-mapped interface (RPU if) which is used to communicate with APUs. VFIO CDX driver provides the CDX device resources like MMIO and interrupts to map to user-space. DPDK CDX bus uses sysfs interface and the vfio-cdx driver to discover and initialize the CDX devices for user-space applications. Changes v2->v3: - merged cdx bus compilation enablement in the first patch - fixed issue reported by check-git-log.sh - updated release notes - updated offset to uint64_t instead of off_t in cdx_map_resource Changes v1->v2: - Moved file rte_cdx_bus.h to internal bus_cdx_driver.h and added this file to deivce_cdx_headers - Moved cdx.h to private.h - Removed rte_ prefix from the static symbols in .c files. Changes RFC->v1: - Marked few API's as internal which were not required to be provided to user. Nipun Gupta (5): bus/cdx: introduce cdx bus bus/cdx: add DMA map and unmap support bus/cdx: add support for MSI bus/cdx: support plug unplug and dev iterator config/arm: add AMD CDX MAINTAINERS| 5 + config/arm/arm64_cdx_linux_gcc | 17 + config/arm/meson.build | 14 + doc/guides/rel_notes/release_23_07.rst | 6 + drivers/bus/cdx/bus_cdx_driver.h | 227 drivers/bus/cdx/cdx.c | 693 + drivers/bus/cdx/cdx_logs.h | 37 ++ drivers/bus/cdx/cdx_vfio.c | 615 ++ drivers/bus/cdx/meson.build| 13 + drivers/bus/cdx/private.h | 49 ++ drivers/bus/cdx/version.map| 13 + drivers/bus/meson.build| 1 + lib/eal/common/eal_common_interrupts.c | 21 + lib/eal/common/eal_interrupts.h| 1 + lib/eal/include/rte_interrupts.h | 32 ++ lib/eal/version.map| 2 + 16 files changed, 1746 insertions(+) create mode 100644 config/arm/arm64_cdx_linux_gcc create mode 100644 drivers/bus/cdx/bus_cdx_driver.h create mode 100644 drivers/bus/cdx/cdx.c create mode 100644 drivers/bus/cdx/cdx_logs.h create mode 100644 drivers/bus/cdx/cdx_vfio.c create mode 100644 drivers/bus/cdx/meson.build create mode 100644 drivers/bus/cdx/private.h create mode 100644 drivers/bus/cdx/version.map -- 2.17.1
[PATCH v3 1/5] bus/cdx: introduce cdx bus
CDX bus supports multiple type of devices, which can be
exposed to user-space via vfio-cdx.
vfio-cdx provides the MMIO IO_MEMORY regions as well as the
DMA interface for the device (IOMMU).
This support aims to enable the DPDK to support the cdx
devices in user-space using VFIO interface.
Signed-off-by: Nipun Gupta
---
MAINTAINERS| 5 +
doc/guides/rel_notes/release_23_07.rst | 6 +
drivers/bus/cdx/bus_cdx_driver.h | 201 ++
drivers/bus/cdx/cdx.c | 520 +
drivers/bus/cdx/cdx_logs.h | 37 ++
drivers/bus/cdx/cdx_vfio.c | 437 +
drivers/bus/cdx/meson.build| 13 +
drivers/bus/cdx/private.h | 49 +++
drivers/bus/cdx/version.map| 11 +
drivers/bus/meson.build| 1 +
10 files changed, 1280 insertions(+)
create mode 100644 drivers/bus/cdx/bus_cdx_driver.h
create mode 100644 drivers/bus/cdx/cdx.c
create mode 100644 drivers/bus/cdx/cdx_logs.h
create mode 100644 drivers/bus/cdx/cdx_vfio.c
create mode 100644 drivers/bus/cdx/meson.build
create mode 100644 drivers/bus/cdx/private.h
create mode 100644 drivers/bus/cdx/version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index 8df23e5099..1f9b6af9b9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -569,6 +569,11 @@ M: Parav Pandit
M: Xueming Li
F: drivers/bus/auxiliary/
+CDX bus driver
+M: Nipun Gupta
+M: Nikhil Agarwal
+F: drivers/bus/cdx/
+
Intel FPGA bus
M: Rosen Xu
F: drivers/bus/ifpga/
diff --git a/doc/guides/rel_notes/release_23_07.rst
b/doc/guides/rel_notes/release_23_07.rst
index a9b1293689..a5f581dc3d 100644
--- a/doc/guides/rel_notes/release_23_07.rst
+++ b/doc/guides/rel_notes/release_23_07.rst
@@ -55,6 +55,12 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Added CDX bus support.**
+
+ CDX bus driver has been added to support AMD CDX bus, which operates
+ on FPGA based CDX devices. The CDX devices are memory mapped on system
+ bus for embedded CPUs.
+
Removed Items
-
diff --git a/drivers/bus/cdx/bus_cdx_driver.h b/drivers/bus/cdx/bus_cdx_driver.h
new file mode 100644
index 00..7edcb019eb
--- /dev/null
+++ b/drivers/bus/cdx/bus_cdx_driver.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
+ */
+
+#ifndef _BUS_CDX_DRIVER_H_
+#define _BUS_CDX_DRIVER_H_
+
+/**
+ * @file
+ *
+ * CDX bus interface
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Forward declarations */
+struct rte_cdx_device;
+struct rte_cdx_driver;
+
+#define CDX_MAX_RESOURCE 4
+
+/** List of CDX devices */
+RTE_TAILQ_HEAD(rte_cdx_device_list, rte_cdx_device);
+/** List of CDX drivers */
+RTE_TAILQ_HEAD(rte_cdx_driver_list, rte_cdx_driver);
+
+/* CDX Bus iterators */
+#define FOREACH_DEVICE_ON_CDXBUS(p)\
+ RTE_TAILQ_FOREACH(p, &rte_cdx_bus.device_list, next)
+
+#define FOREACH_DRIVER_ON_CDXBUS(p)\
+ RTE_TAILQ_FOREACH(p, &rte_cdx_bus.driver_list, next)
+
+/** Any CDX device identifier (vendor, device) */
+#define RTE_CDX_ANY_ID (0x)
+
+#define RTE_PMD_REGISTER_CDX_TABLE(name, table) \
+static const char DRV_EXP_TAG(name, cdx_tbl_export)[] __rte_used = \
+RTE_STR(table)
+
+/**
+ * A structure describing an ID for a CDX driver. Each driver provides a
+ * table of these IDs for each device that it supports.
+ */
+struct rte_cdx_id {
+ uint16_t vendor_id; /**< Vendor ID. */
+ uint16_t device_id; /**< Device ID. */
+};
+
+/**
+ * A structure describing a CDX device.
+ */
+struct rte_cdx_device {
+ RTE_TAILQ_ENTRY(rte_cdx_device) next; /**< Next probed CDX device. */
+ struct rte_device device; /**< Inherit core device */
+ struct rte_cdx_id id; /**< CDX ID. */
+ struct rte_mem_resource mem_resource[CDX_MAX_RESOURCE];
+ /**< CDX Memory Resource */
+};
+
+/**
+ * @internal
+ * Helper macro for drivers that need to convert to struct rte_cdx_device.
+ */
+#define RTE_DEV_TO_CDX_DEV(ptr) \
+ container_of(ptr, struct rte_cdx_device, device)
+
+#define RTE_DEV_TO_CDX_DEV_CONST(ptr) \
+ container_of(ptr, const struct rte_cdx_device, device)
+
+#define RTE_ETH_DEV_TO_CDX_DEV(eth_dev)
RTE_DEV_TO_CDX_DEV((eth_dev)->device)
+
+#ifdef __cplusplus
+/** C++ macro used to help building up tables of device IDs */
+#define RTE_CDX_DEVICE(vend, dev) \
+ (vend), \
+ (dev)
+#else
+/** Macro used to help building up tables of device IDs */
+#define RTE_CDX_DEVICE(vend, dev) \
+ .vendor_id = (vend),\
+ .device_id
[PATCH v3 2/5] bus/cdx: add DMA map and unmap support
CDX bus can use VFIO interface for mapping and unmapping
of DMA addresses in the IOMMU. This change adds the callback
support for map and unmap APIs as well as fetching the IOMMU
class.
Signed-off-by: Nipun Gupta
---
drivers/bus/cdx/cdx.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/bus/cdx/cdx.c b/drivers/bus/cdx/cdx.c
index d479daa315..8cc273336e 100644
--- a/drivers/bus/cdx/cdx.c
+++ b/drivers/bus/cdx/cdx.c
@@ -505,12 +505,52 @@ cdx_find_device(const struct rte_device *start,
rte_dev_cmp_t cmp,
return NULL;
}
+static int
+cdx_dma_map(struct rte_device *dev, void *addr, uint64_t iova, size_t len)
+{
+ struct rte_cdx_device *cdx_dev = RTE_DEV_TO_CDX_DEV(dev);
+
+ if (!cdx_dev) {
+ rte_errno = EINVAL;
+ return -1;
+ }
+
+ return rte_vfio_container_dma_map(RTE_VFIO_DEFAULT_CONTAINER_FD,
+ (uintptr_t)addr, iova, len);
+}
+
+static int
+cdx_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova, size_t len)
+{
+ struct rte_cdx_device *cdx_dev = RTE_DEV_TO_CDX_DEV(dev);
+
+ if (!cdx_dev) {
+ rte_errno = EINVAL;
+ return -1;
+ }
+
+ return rte_vfio_container_dma_unmap(RTE_VFIO_DEFAULT_CONTAINER_FD,
+ (uintptr_t)addr, iova, len);
+}
+
+static enum rte_iova_mode
+cdx_get_iommu_class(void)
+{
+ if (TAILQ_EMPTY(&rte_cdx_bus.device_list))
+ return RTE_IOVA_DC;
+
+ return RTE_IOVA_VA;
+}
+
struct rte_cdx_bus rte_cdx_bus = {
.bus = {
.scan = cdx_scan,
.probe = cdx_probe,
.find_device = cdx_find_device,
.parse = cdx_parse,
+ .dma_map = cdx_dma_map,
+ .dma_unmap = cdx_dma_unmap,
+ .get_iommu_class = cdx_get_iommu_class,
},
.device_list = TAILQ_HEAD_INITIALIZER(rte_cdx_bus.device_list),
.driver_list = TAILQ_HEAD_INITIALIZER(rte_cdx_bus.driver_list),
--
2.17.1
[PATCH v3 3/5] bus/cdx: add support for MSI
MSI's are exposed to the devices using VFIO (vfio-cdx). This
patch uses the same to add support for MSI for the devices on
the cdx bus.
A couple of API's have been introduced in the EAL interrupt
framework:
- rte_intr_irq_count_set: This API is used to set the total
interrupts on the interrupt handle. This would be provided
by VFIO (irq.count) for VFIO enabled devices.
- rte_intr_irq_count_get: This API returns the total number
interrupts which were set.
Signed-off-by: Nipun Gupta
---
drivers/bus/cdx/bus_cdx_driver.h | 25
drivers/bus/cdx/cdx.c | 11 ++
drivers/bus/cdx/cdx_vfio.c | 182 -
drivers/bus/cdx/version.map| 2 +
lib/eal/common/eal_common_interrupts.c | 21 +++
lib/eal/common/eal_interrupts.h| 1 +
lib/eal/include/rte_interrupts.h | 32 +
lib/eal/version.map| 2 +
8 files changed, 274 insertions(+), 2 deletions(-)
diff --git a/drivers/bus/cdx/bus_cdx_driver.h b/drivers/bus/cdx/bus_cdx_driver.h
index 7edcb019eb..fdeaf46664 100644
--- a/drivers/bus/cdx/bus_cdx_driver.h
+++ b/drivers/bus/cdx/bus_cdx_driver.h
@@ -72,6 +72,7 @@ struct rte_cdx_device {
struct rte_cdx_id id; /**< CDX ID. */
struct rte_mem_resource mem_resource[CDX_MAX_RESOURCE];
/**< CDX Memory Resource */
+ struct rte_intr_handle *intr_handle;/**< Interrupt handle */
};
/**
@@ -173,6 +174,30 @@ void rte_cdx_unmap_device(struct rte_cdx_device *dev);
__rte_internal
void rte_cdx_register(struct rte_cdx_driver *driver);
+/**
+ * Enables VFIO Interrupts for CDX bus devices.
+ *
+ * @param intr_handle
+ * Pointer to the interrupt handle.
+ *
+ * @return
+ * 0 on success, -1 on error.
+ */
+__rte_internal
+int rte_cdx_vfio_intr_enable(const struct rte_intr_handle *intr_handle);
+
+/**
+ * Disable VFIO Interrupts for CDX bus devices.
+ *
+ * @param intr_handle
+ * Pointer to the interrupt handle.
+ *
+ * @return
+ * 0 on success, -1 on error.
+ */
+__rte_internal
+int rte_cdx_vfio_intr_disable(const struct rte_intr_handle *intr_handle);
+
/**
* Helper for CDX device registration from driver (eth, crypto, raw) instance
*/
diff --git a/drivers/bus/cdx/cdx.c b/drivers/bus/cdx/cdx.c
index 8cc273336e..6c9ceaaf7f 100644
--- a/drivers/bus/cdx/cdx.c
+++ b/drivers/bus/cdx/cdx.c
@@ -204,6 +204,15 @@ cdx_scan_one(const char *dirname, const char *dev_name)
goto err;
}
+ /* Allocate interrupt instance for cdx device */
+ dev->intr_handle =
+ rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
+ if (dev->intr_handle == NULL) {
+ CDX_BUS_ERR("Failed to create interrupt instance for %s\n",
+ dev->device.name);
+ return -ENOMEM;
+ }
+
/*
* Check if device is bound to 'vfio-cdx' driver, so that user-space
* can gracefully access the device.
@@ -394,6 +403,8 @@ cdx_probe_one_driver(struct rte_cdx_driver *dr,
return ret;
error_probe:
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
cdx_vfio_unmap_resource(dev);
error_map_device:
return ret;
diff --git a/drivers/bus/cdx/cdx_vfio.c b/drivers/bus/cdx/cdx_vfio.c
index ae11f589b3..1422b98503 100644
--- a/drivers/bus/cdx/cdx_vfio.c
+++ b/drivers/bus/cdx/cdx_vfio.c
@@ -60,6 +60,10 @@ struct mapped_cdx_resource {
/** mapped cdx device list */
TAILQ_HEAD(mapped_cdx_res_list, mapped_cdx_resource);
+/* irq set buffer length for MSI interrupts */
+#define MSI_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \
+ sizeof(int) * (RTE_MAX_RXTX_INTR_VEC_ID + 1))
+
static struct rte_tailq_elem cdx_vfio_tailq = {
.name = "VFIO_CDX_RESOURCE_LIST",
};
@@ -104,6 +108,27 @@ cdx_vfio_unmap_resource_primary(struct rte_cdx_device *dev)
char cdx_addr[PATH_MAX] = {0};
struct mapped_cdx_resource *vfio_res = NULL;
struct mapped_cdx_res_list *vfio_res_list;
+ int ret, vfio_dev_fd;
+
+ if (rte_intr_fd_get(dev->intr_handle) < 0)
+ return -1;
+
+ if (close(rte_intr_fd_get(dev->intr_handle)) < 0) {
+ CDX_BUS_ERR("Error when closing eventfd file descriptor for %s",
+ dev->device.name);
+ return -1;
+ }
+
+ vfio_dev_fd = rte_intr_dev_fd_get(dev->intr_handle);
+ if (vfio_dev_fd < 0)
+ return -1;
+
+ ret = rte_vfio_release_device(rte_cdx_get_sysfs_path(),
dev->device.name,
+ vfio_dev_fd);
+ if (ret < 0) {
+ CDX_BUS_ERR("Cannot release VFIO device");
+ return ret;
+ }
vfio_res_list =
RTE_TAILQ_CAST(cdx_vfio_tailq.head, mapped_cdx_res_list);
@@ -126,6 +151,18 @@ cdx_vfio_unmap_resource_secondary(struct rte_cdx_device
*dev)
[PATCH v3 4/5] bus/cdx: support plug unplug and dev iterator
This change adds support for plugging and unplugging
CDX devices on the CDX bus. Also, CDX dev iterator support
has been added for the CDX bus.
Signed-off-by: Nipun Gupta
---
drivers/bus/cdx/bus_cdx_driver.h | 1 +
drivers/bus/cdx/cdx.c| 122 +++
2 files changed, 123 insertions(+)
diff --git a/drivers/bus/cdx/bus_cdx_driver.h b/drivers/bus/cdx/bus_cdx_driver.h
index fdeaf46664..3d89e7c054 100644
--- a/drivers/bus/cdx/bus_cdx_driver.h
+++ b/drivers/bus/cdx/bus_cdx_driver.h
@@ -69,6 +69,7 @@ struct rte_cdx_id {
struct rte_cdx_device {
RTE_TAILQ_ENTRY(rte_cdx_device) next; /**< Next probed CDX device. */
struct rte_device device; /**< Inherit core device */
+ struct rte_cdx_driver *driver; /**< CDX driver used in probing
*/
struct rte_cdx_id id; /**< CDX ID. */
struct rte_mem_resource mem_resource[CDX_MAX_RESOURCE];
/**< CDX Memory Resource */
diff --git a/drivers/bus/cdx/cdx.c b/drivers/bus/cdx/cdx.c
index 6c9ceaaf7f..0a30b8648a 100644
--- a/drivers/bus/cdx/cdx.c
+++ b/drivers/bus/cdx/cdx.c
@@ -68,6 +68,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -82,6 +83,15 @@
#define CDX_BUS_NAME cdx
#define CDX_DEV_PREFIX "cdx-"
+enum cdx_params {
+ RTE_CDX_PARAM_NAME,
+};
+
+static const char * const cdx_params_keys[] = {
+ [RTE_CDX_PARAM_NAME] = "name",
+ NULL,
+};
+
/**
* @file
* CDX probing using Linux sysfs.
@@ -399,6 +409,7 @@ cdx_probe_one_driver(struct rte_cdx_driver *dr,
} else {
dev->device.driver = &dr->driver;
}
+ dev->driver = dr;
return ret;
@@ -516,6 +527,71 @@ cdx_find_device(const struct rte_device *start,
rte_dev_cmp_t cmp,
return NULL;
}
+/* Remove a device from CDX bus */
+static void
+cdx_remove_device(struct rte_cdx_device *cdx_dev)
+{
+ TAILQ_REMOVE(&rte_cdx_bus.device_list, cdx_dev, next);
+}
+
+/*
+ * If vendor/device ID match, call the remove() function of the
+ * driver.
+ */
+static int
+cdx_detach_dev(struct rte_cdx_device *dev)
+{
+ struct rte_cdx_driver *dr;
+ int ret = 0;
+
+ if (dev == NULL)
+ return -EINVAL;
+
+ dr = dev->driver;
+
+ CDX_BUS_DEBUG("detach device %s using driver: %s",
+ dev->device.name, dr->driver.name);
+
+ if (dr->remove) {
+ ret = dr->remove(dev);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* clear driver structure */
+ dev->driver = NULL;
+ dev->device.driver = NULL;
+
+ rte_cdx_unmap_device(dev);
+
+ rte_intr_instance_free(dev->intr_handle);
+ dev->intr_handle = NULL;
+
+ return 0;
+}
+
+static int
+cdx_plug(struct rte_device *dev)
+{
+ return cdx_probe_all_drivers(RTE_DEV_TO_CDX_DEV(dev));
+}
+
+static int
+cdx_unplug(struct rte_device *dev)
+{
+ struct rte_cdx_device *cdx_dev;
+ int ret;
+
+ cdx_dev = RTE_DEV_TO_CDX_DEV(dev);
+ ret = cdx_detach_dev(cdx_dev);
+ if (ret == 0) {
+ cdx_remove_device(cdx_dev);
+ rte_devargs_remove(dev->devargs);
+ free(cdx_dev);
+ }
+ return ret;
+}
+
static int
cdx_dma_map(struct rte_device *dev, void *addr, uint64_t iova, size_t len)
{
@@ -553,15 +629,61 @@ cdx_get_iommu_class(void)
return RTE_IOVA_VA;
}
+static int
+cdx_dev_match(const struct rte_device *dev,
+ const void *_kvlist)
+{
+ const struct rte_kvargs *kvlist = _kvlist;
+ const char *key = cdx_params_keys[RTE_CDX_PARAM_NAME];
+ const char *name;
+
+ /* no kvlist arg, all devices match */
+ if (kvlist == NULL)
+ return 0;
+
+ /* if key is present in kvlist and does not match, filter device */
+ name = rte_kvargs_get(kvlist, key);
+ if (name != NULL && strcmp(name, dev->name))
+ return -1;
+
+ return 0;
+}
+
+static void *
+cdx_dev_iterate(const void *start,
+ const char *str,
+ const struct rte_dev_iterator *it __rte_unused)
+{
+ rte_bus_find_device_t find_device;
+ struct rte_kvargs *kvargs = NULL;
+ struct rte_device *dev;
+
+ if (str != NULL) {
+ kvargs = rte_kvargs_parse(str, cdx_params_keys);
+ if (kvargs == NULL) {
+ CDX_BUS_ERR("cannot parse argument list %s", str);
+ rte_errno = EINVAL;
+ return NULL;
+ }
+ }
+ find_device = rte_cdx_bus.bus.find_device;
+ dev = find_device(start, cdx_dev_match, kvargs);
+ rte_kvargs_free(kvargs);
+ return dev;
+}
+
struct rte_cdx_bus rte_cdx_bus = {
.bus = {
.scan = cdx_scan,
.probe = cdx_probe,
.find_device = cdx_find_device,
+
[PATCH v3 5/5] config/arm: add AMD CDX
Adding support for AMD CDX devices
Signed-off-by: Nipun Gupta
---
config/arm/arm64_cdx_linux_gcc | 17 +
config/arm/meson.build | 14 ++
2 files changed, 31 insertions(+)
create mode 100644 config/arm/arm64_cdx_linux_gcc
diff --git a/config/arm/arm64_cdx_linux_gcc b/config/arm/arm64_cdx_linux_gcc
new file mode 100644
index 00..8e6d619dae
--- /dev/null
+++ b/config/arm/arm64_cdx_linux_gcc
@@ -0,0 +1,17 @@
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-ar'
+as = 'aarch64-linux-gnu-as'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+platform = 'cdx'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 5213434ca4..39b8929534 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -305,6 +305,18 @@ soc_bluefield = {
'numa': false
}
+soc_cdx = {
+'description': 'AMD CDX',
+'implementer': '0x41',
+'part_number': '0xd42',
+'flags': [
+['RTE_MACHINE', '"cdx"'],
+['RTE_MAX_LCORE', 16],
+['RTE_MAX_NUMA_NODES', 1]
+],
+'numa': false
+}
+
soc_centriq2400 = {
'description': 'Qualcomm Centriq 2400',
'implementer': '0x51',
@@ -463,6 +475,7 @@ generic_aarch32: Generic un-optimized build for armv8
aarch32 execution mode.
armada: Marvell ARMADA
bluefield: NVIDIA BlueField
bluefield3: NVIDIA BlueField-3
+cdx: AMD CDX
centriq2400: Qualcomm Centriq 2400
cn9k:Marvell OCTEON 9
cn10k: Marvell OCTEON 10
@@ -490,6 +503,7 @@ socs = {
'armada': soc_armada,
'bluefield': soc_bluefield,
'bluefield3': soc_bluefield3,
+'cdx': soc_cdx,
'centriq2400': soc_centriq2400,
'cn9k': soc_cn9k,
'cn10k' : soc_cn10k,
--
2.17.1
Re: [RFC] lib: set/get max memzone segments
21/04/2023 13:08, Morten Brørup: > > From: Thomas Monjalon [mailto:tho...@monjalon.net] > > Sent: Friday, 21 April 2023 10.35 > > 20/04/2023 20:20, Tyler Retzlaff: > > > On Thu, Apr 20, 2023 at 09:43:28AM +0200, Thomas Monjalon wrote: > > > > 19/04/2023 16:51, Tyler Retzlaff: > > > > > On Wed, Apr 19, 2023 at 11:36:34AM +0300, Ophir Munk wrote: > > > > > > In current DPDK the RTE_MAX_MEMZONE definition is unconditionally > > > > > > hard > > > > > > coded as 2560. For applications requiring different values of this > > > > > > parameter – it is more convenient to set the max value via an rte > > > > > > API > > - > > > > > > rather than changing the dpdk source code per application. In many > > > > > > organizations, the possibility to compile a private DPDK library > > > > > > for a > > > > > > particular application does not exist at all. With this option > > > > > > there > > is > > > > > > no need to recompile DPDK and it allows using an in-box packaged > > > > > > DPDK. > > > > > > An example usage for updating the RTE_MAX_MEMZONE would be of an > > > > > > application that uses the DPDK mempool library which is based on > > > > > > DPDK > > > > > > memzone library. The application may need to create a number of > > > > > > steering tables, each of which will require its own mempool > > allocation. > > > > > > This commit is not about how to optimize the application usage of > > > > > > mempool nor about how to improve the mempool implementation based on > > > > > > memzone. It is about how to make the max memzone definition - run- > > time > > > > > > customized. > > > > > > This commit adds an API which must be called before rte_eal_init(): > > > > > > rte_memzone_max_set(int max). If not called, the default memzone > > > > > > (RTE_MAX_MEMZONE) is used. There is also an API to query the > > effective > > > > > > max memzone: rte_memzone_max_get(). > > > > > > > > > > > > Signed-off-by: Ophir Munk > > > > > > --- > > > > > > > > > > the use case of each application may want a different non-hard coded > > > > > value makes sense. > > > > > > > > > > it's less clear to me that requiring it be called before eal init > > > > > makes > > > > > sense over just providing it as configuration to eal init so that it > > > > > is > > > > > composed. > > > > > > > > Why do you think it would be better as EAL init option? > > > > From an API perspective, I think it is simpler to call a dedicated > > function. > > > > And I don't think a user wants to deal with it when starting the > > application. > > > > > > because a dedicated function that can be called detached from the eal > > > state enables an opportunity for accidental and confusing use outside > > > the correct context. > > > > > > i know the above prescribes not to do this but. > > > > > > now you can call set after eal init, but we protect about calling it > > > after init by failing. what do we do sensibly with the failure? > > > > It would be a developer mistake which could be fix during development stage > > very easily. I don't see a problem here. > > Why is this not just a command line parameter, like other EAL configuration > options? > > Do any other pre-init APIs exist, or are you introducing a new design pattern > for configuring EAL? Let's say it is a "new" design pattern, as discussed multiple times in previous years. But this one is only for the application, it is not a user configuration as in rte_eal_init(int argc, char **argv). > Any application can simply modify the command line parameters before calling > EAL init. It doesn't need to pass the command line parameters as-is to EAL > init. It is not very easy to use. > In other words: There is an existing design pattern for configuring EAL, why > introduce a new design pattern? Because argc/argv is a bad pattern. We had multiple requests to avoid it. So when introducing a new option, it is better to avoid it. > If we want to expose APIs for configuring EAL instead of passing command line > parameters, such APIs should be added for all EAL configuration parameters. The memzone parameter is not supposed to be configured by the user, so it does not make sense to expose it via argc/argv. > That would be nice, but I dislike that some EAL configuration parameters must > be passed using one method and some other passed using another method. We asked multiple times for such rework. And the patches from Bruce to split some EAL parts are in this direction. If you want to propose some new functions to configure EAL, you are welcome.
RE: [RFC] lib: set/get max memzone segments
> From: Thomas Monjalon [mailto:tho...@monjalon.net] > Sent: Friday, 21 April 2023 16.57 > > 21/04/2023 13:08, Morten Brørup: > > > From: Thomas Monjalon [mailto:tho...@monjalon.net] > > > Sent: Friday, 21 April 2023 10.35 > > > 20/04/2023 20:20, Tyler Retzlaff: > > > > On Thu, Apr 20, 2023 at 09:43:28AM +0200, Thomas Monjalon wrote: > > > > > 19/04/2023 16:51, Tyler Retzlaff: > > > > > > On Wed, Apr 19, 2023 at 11:36:34AM +0300, Ophir Munk wrote: > > > > > > > In current DPDK the RTE_MAX_MEMZONE definition is unconditionally > hard > > > > > > > coded as 2560. For applications requiring different values of > this > > > > > > > parameter – it is more convenient to set the max value via an rte > API > > > - > > > > > > > rather than changing the dpdk source code per application. In > many > > > > > > > organizations, the possibility to compile a private DPDK library > for a > > > > > > > particular application does not exist at all. With this option > there > > > is > > > > > > > no need to recompile DPDK and it allows using an in-box packaged > DPDK. > > > > > > > An example usage for updating the RTE_MAX_MEMZONE would be of an > > > > > > > application that uses the DPDK mempool library which is based on > DPDK > > > > > > > memzone library. The application may need to create a number of > > > > > > > steering tables, each of which will require its own mempool > > > allocation. > > > > > > > This commit is not about how to optimize the application usage of > > > > > > > mempool nor about how to improve the mempool implementation based > on > > > > > > > memzone. It is about how to make the max memzone definition - > run- > > > time > > > > > > > customized. > > > > > > > This commit adds an API which must be called before > rte_eal_init(): > > > > > > > rte_memzone_max_set(int max). If not called, the default memzone > > > > > > > (RTE_MAX_MEMZONE) is used. There is also an API to query the > > > effective > > > > > > > max memzone: rte_memzone_max_get(). > > > > > > > > > > > > > > Signed-off-by: Ophir Munk > > > > > > > --- > > > > > > > > > > > > the use case of each application may want a different non-hard coded > > > > > > value makes sense. > > > > > > > > > > > > it's less clear to me that requiring it be called before eal init > makes > > > > > > sense over just providing it as configuration to eal init so that it > is > > > > > > composed. > > > > > > > > > > Why do you think it would be better as EAL init option? > > > > > From an API perspective, I think it is simpler to call a dedicated > > > function. > > > > > And I don't think a user wants to deal with it when starting the > > > application. > > > > > > > > because a dedicated function that can be called detached from the eal > > > > state enables an opportunity for accidental and confusing use outside > > > > the correct context. > > > > > > > > i know the above prescribes not to do this but. > > > > > > > > now you can call set after eal init, but we protect about calling it > > > > after init by failing. what do we do sensibly with the failure? > > > > > > It would be a developer mistake which could be fix during development > stage > > > very easily. I don't see a problem here. > > > > Why is this not just a command line parameter, like other EAL configuration > options? > > > > Do any other pre-init APIs exist, or are you introducing a new design > pattern for configuring EAL? > > Let's say it is a "new" design pattern, as discussed multiple times in > previous years. > But this one is only for the application, > it is not a user configuration as in rte_eal_init(int argc, char **argv). > > > Any application can simply modify the command line parameters before calling > EAL init. It doesn't need to pass the command line parameters as-is to EAL > init. > > It is not very easy to use. > > > In other words: There is an existing design pattern for configuring EAL, why > introduce a new design pattern? > > Because argc/argv is a bad pattern. > We had multiple requests to avoid it. > So when introducing a new option, it is better to avoid it. > > > If we want to expose APIs for configuring EAL instead of passing command > line parameters, such APIs should be added for all EAL configuration > parameters. > > The memzone parameter is not supposed to be configured by the user, > so it does not make sense to expose it via argc/argv. Good point! I didn't think about that; in hardware appliances, the user has no access to provide EAL command line parameters. > > > That would be nice, but I dislike that some EAL configuration parameters > must be passed using one method and some other passed using another method. > > We asked multiple times for such rework. High level directions/goals for DPDK, such as replacing EAL command line parameters with APIs, should be noted on the Roadmap web page. > And the patches from Bruce to split some EAL parts are in this direction. > If you want to propose some new functions to configure EAL
[PATCH v2 00/11] sync Truflow support with latest release
Version 2 fixes: - misspellings - whitespace issues - signed off issues Kishore Padmanabha (1): net/bnxt: fix multi-root card support Randy Schacher (9): net/bnxt: remove deprecated features net/bnxt: update bnxt hsi structure net/bnxt: update copyright date and cleanup whitespace net/bnxt: update Truflow core net/bnxt: update ULP shared session support net/bnxt: add support for RSS action and Queue action net/bnxt: add ulp support for rte meter net/bnxt: update PTP support on Thor net/bnxt: add ulp support for ecpri Shuanglin Wang (1): net/bnxt: Avoid submitting hwrm rss request when rss mode disabled drivers/net/bnxt/bnxt.h |77 +- drivers/net/bnxt/bnxt_cpr.c | 2 +- drivers/net/bnxt/bnxt_cpr.h | 2 +- drivers/net/bnxt/bnxt_ethdev.c| 211 +- drivers/net/bnxt/bnxt_filter.c| 2 +- drivers/net/bnxt/bnxt_filter.h| 6 +- drivers/net/bnxt/bnxt_flow.c |75 +- drivers/net/bnxt/bnxt_hwrm.c | 272 +- drivers/net/bnxt/bnxt_hwrm.h |40 +- drivers/net/bnxt/bnxt_irq.c | 2 +- drivers/net/bnxt/bnxt_irq.h | 3 +- drivers/net/bnxt/bnxt_nvm_defs.h | 3 +- drivers/net/bnxt/bnxt_reps.c | 4 +- drivers/net/bnxt/bnxt_reps.h | 2 +- drivers/net/bnxt/bnxt_ring.c | 7 +- drivers/net/bnxt/bnxt_ring.h | 3 +- drivers/net/bnxt/bnxt_rxq.c | 159 +- drivers/net/bnxt/bnxt_rxq.h | 2 +- drivers/net/bnxt/bnxt_rxr.c |15 +- drivers/net/bnxt/bnxt_rxr.h | 3 +- drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_common.h | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +- drivers/net/bnxt/bnxt_stats.c | 2 +- drivers/net/bnxt/bnxt_stats.h | 2 +- drivers/net/bnxt/bnxt_txq.c | 3 +- drivers/net/bnxt/bnxt_txq.h | 2 +- drivers/net/bnxt/bnxt_txr.c |95 +- drivers/net/bnxt/bnxt_txr.h | 4 +- drivers/net/bnxt/bnxt_util.c | 2 +- drivers/net/bnxt/bnxt_util.h | 3 +- drivers/net/bnxt/bnxt_vnic.c | 974 +- drivers/net/bnxt/bnxt_vnic.h |80 +- drivers/net/bnxt/hsi_struct_def_dpdk.h| 5723 ++- drivers/net/bnxt/meson.build | 5 +- drivers/net/bnxt/rte_pmd_bnxt.c | 2 +- drivers/net/bnxt/rte_pmd_bnxt.h | 2 +- drivers/net/bnxt/tf_core/bitalloc.c | 3 +- drivers/net/bnxt/tf_core/bitalloc.h | 3 +- drivers/net/bnxt/tf_core/cfa_resource_types.h | 5 +- drivers/net/bnxt/tf_core/cfa_tcam_mgr.c | 2116 + drivers/net/bnxt/tf_core/cfa_tcam_mgr.h | 523 + .../net/bnxt/tf_core/cfa_tcam_mgr_device.h| 101 + .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.c | 201 + .../net/bnxt/tf_core/cfa_tcam_mgr_hwop_msg.h |28 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.c| 921 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p4.h|20 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.c | 926 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_p58.h |20 + drivers/net/bnxt/tf_core/cfa_tcam_mgr_sbmp.h | 126 + .../net/bnxt/tf_core/cfa_tcam_mgr_session.c | 377 + .../net/bnxt/tf_core/cfa_tcam_mgr_session.h |54 + drivers/net/bnxt/tf_core/dpool.c | 3 +- drivers/net/bnxt/tf_core/dpool.h | 3 +- drivers/net/bnxt/tf_core/ll.c | 2 +- drivers/net/bnxt/tf_core/ll.h | 2 +- drivers/net/bnxt/tf_core/lookup3.h| 1 - drivers/net/bnxt/tf_core/meson.build |38 +- drivers/net/bnxt/tf_core/rand.c | 2 +- drivers/net/bnxt/tf_core/rand.h | 3 +- drivers/net/bnxt/tf_core/stack.c | 2 +- drivers/net/bnxt/tf_core/stack.h | 3 +- drivers/net/bnxt/tf_core/tf_common.h | 3 +- drivers/net/bnxt/tf_core/tf_core.c|56 +- drivers/net/bnxt/tf_core/tf_core.h| 189 +- drivers/net/bnxt/tf_core/tf_device.c |53 +- drivers/net/bnxt/tf_core/tf_device.h | 9 +- drivers/net/bnxt/tf_core/tf_device_p4.c |24 +- drivers/net/bnxt/tf_core/tf_device_p4.h | 3 +- drivers/net/bnxt/tf_core/tf_device_p58.c |94 +- drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +- drivers/net/bnxt/tf_core/tf_em.h | 3 +- drivers/net/bnxt/tf_core/tf_em_common.c |10 +- drivers/net/bnxt/tf_core/tf_em_common.h | 4 +- .../net/bnxt/tf_core/tf_
[PATCH v2 01/11] net/bnxt: remove deprecated features
- Deprecate shadow identifier
- Deprecate shadow tcam
Signed-off-by: Randy Schacher
Signed-off-by: Kishore Padmanabha
Reviewed-by: Peter Spreadborough
---
drivers/net/bnxt/bnxt_hwrm.c | 53 --
drivers/net/bnxt/bnxt_hwrm.h | 10 -
drivers/net/bnxt/tf_core/meson.build | 2 -
drivers/net/bnxt/tf_core/tf_core.c| 2 -
drivers/net/bnxt/tf_core/tf_core.h| 91 +-
drivers/net/bnxt/tf_core/tf_device.c | 35 -
drivers/net/bnxt/tf_core/tf_device.h | 6 -
drivers/net/bnxt/tf_core/tf_device_p4.c | 10 -
drivers/net/bnxt/tf_core/tf_device_p58.c | 10 -
drivers/net/bnxt/tf_core/tf_identifier.c | 108 ---
drivers/net/bnxt/tf_core/tf_identifier.h | 4 -
drivers/net/bnxt/tf_core/tf_if_tbl.h | 8 -
drivers/net/bnxt/tf_core/tf_session.c | 9 +-
drivers/net/bnxt/tf_core/tf_session.h | 18 +-
.../net/bnxt/tf_core/tf_shadow_identifier.c | 190
.../net/bnxt/tf_core/tf_shadow_identifier.h | 229 -
drivers/net/bnxt/tf_core/tf_shadow_tcam.c | 837 --
drivers/net/bnxt/tf_core/tf_shadow_tcam.h | 195
drivers/net/bnxt/tf_core/tf_tcam.c| 243 -
drivers/net/bnxt/tf_core/tf_tcam.h| 38 +-
drivers/net/bnxt/tf_core/tf_util.c| 2 -
drivers/net/bnxt/tf_ulp/bnxt_ulp.c| 3 -
22 files changed, 8 insertions(+), 2095 deletions(-)
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_identifier.h
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.c
delete mode 100644 drivers/net/bnxt/tf_core/tf_shadow_tcam.h
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index d86ac73293..3f273df6f3 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -407,59 +407,6 @@ int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
return rc;
}
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len)
-{
- int rc = 0;
- struct hwrm_cfa_tflib_input req = { .req_type = 0 };
- struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
- bool mailbox = BNXT_USE_CHIMP_MB;
-
- if (msg_len > sizeof(req.tf_req))
- return -ENOMEM;
-
- if (use_kong_mb)
- mailbox = BNXT_USE_KONG(bp);
-
- HWRM_PREP(&req, HWRM_TF, mailbox);
- /* Build request using the user supplied request payload.
-* TLV request size is checked at build time against HWRM
-* request max size, thus no checking required.
-*/
- req.tf_type = tf_type;
- req.tf_subtype = tf_subtype;
- memcpy(req.tf_req, msg, msg_len);
-
- rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
- HWRM_CHECK_RESULT();
-
- /* Copy the resp to user provided response buffer */
- if (response != NULL)
- /* Post process response data. We need to copy only
-* the 'payload' as the HWRM data structure really is
-* HWRM header + msg header + payload and the TFLIB
-* only provided a payload place holder.
-*/
- if (response_len != 0) {
- memcpy(response,
- resp->tf_resp,
- response_len);
- }
-
- /* Extract the internal tflib response code */
- *tf_response_code = resp->tf_resp_code;
- HWRM_UNLOCK();
-
- return rc;
-}
-
int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info
*vnic)
{
int rc = 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h
index a82d9fb3ef..f9d9fe0ef2 100644
--- a/drivers/net/bnxt/bnxt_hwrm.h
+++ b/drivers/net/bnxt/bnxt_hwrm.h
@@ -79,16 +79,6 @@ struct hwrm_func_qstats_output;
bp->rx_cos_queue[x].profile = \
resp->queue_id##x##_service_profile
-int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
- bool use_kong_mb,
- uint16_t tf_type,
- uint16_t tf_subtype,
- uint32_t *tf_response_code,
- void *msg,
- uint32_t msg_len,
- void *response,
- uint32_t response_len);
-
int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
bool use_kong
[PATCH v2 03/11] net/bnxt: update copyright date and cleanup whitespace
Update the Copyright to 2023 Clean up extra blank lines Clean up other whitespace issues Signed-off-by: Randy Schacher Reviewed-by: Kishore Padmanabha --- drivers/net/bnxt/bnxt_cpr.c| 2 +- drivers/net/bnxt/bnxt_cpr.h| 2 +- drivers/net/bnxt/bnxt_filter.c | 2 +- drivers/net/bnxt/bnxt_irq.c| 2 +- drivers/net/bnxt/bnxt_irq.h| 2 +- drivers/net/bnxt/bnxt_nvm_defs.h | 2 +- drivers/net/bnxt/bnxt_reps.h | 2 +- drivers/net/bnxt/bnxt_ring.h | 2 +- drivers/net/bnxt/bnxt_rxq.h| 2 +- drivers/net/bnxt/bnxt_rxr.h| 2 +- drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_common.h| 2 +- drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +- drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +- drivers/net/bnxt/bnxt_stats.c | 2 +- drivers/net/bnxt/bnxt_stats.h | 2 +- drivers/net/bnxt/bnxt_txq.h| 2 +- drivers/net/bnxt/bnxt_util.c | 2 +- drivers/net/bnxt/bnxt_util.h | 2 +- drivers/net/bnxt/meson.build | 2 +- drivers/net/bnxt/rte_pmd_bnxt.c| 2 +- drivers/net/bnxt/rte_pmd_bnxt.h| 2 +- drivers/net/bnxt/tf_core/bitalloc.c| 3 +-- drivers/net/bnxt/tf_core/bitalloc.h| 3 +-- drivers/net/bnxt/tf_core/cfa_resource_types.h | 3 +-- drivers/net/bnxt/tf_core/dpool.c | 3 ++- drivers/net/bnxt/tf_core/dpool.h | 3 +-- drivers/net/bnxt/tf_core/ll.c | 2 +- drivers/net/bnxt/tf_core/ll.h | 2 +- drivers/net/bnxt/tf_core/lookup3.h | 1 - drivers/net/bnxt/tf_core/rand.c| 2 +- drivers/net/bnxt/tf_core/rand.h| 3 +-- drivers/net/bnxt/tf_core/stack.c | 2 +- drivers/net/bnxt/tf_core/stack.h | 3 +-- drivers/net/bnxt/tf_core/tf_common.h | 3 +-- drivers/net/bnxt/tf_core/tf_core.h | 1 - drivers/net/bnxt/tf_core/tf_device.h | 1 - drivers/net/bnxt/tf_core/tf_device_p4.h| 3 +-- drivers/net/bnxt/tf_core/tf_device_p58.h | 2 +- drivers/net/bnxt/tf_core/tf_em.h | 3 +-- drivers/net/bnxt/tf_core/tf_em_common.c| 8 +--- drivers/net/bnxt/tf_core/tf_em_common.h| 4 +--- drivers/net/bnxt/tf_core/tf_em_hash_internal.c | 2 +- drivers/net/bnxt/tf_core/tf_em_host.c | 3 +-- drivers/net/bnxt/tf_core/tf_em_internal.c | 3 ++- drivers/net/bnxt/tf_core/tf_ext_flow_handle.h | 4 +--- drivers/net/bnxt/tf_core/tf_global_cfg.c | 2 +- drivers/net/bnxt/tf_core/tf_global_cfg.h | 3 +-- drivers/net/bnxt/tf_core/tf_hash.c | 2 +- drivers/net/bnxt/tf_core/tf_hash.h | 3 +-- drivers/net/bnxt/tf_core/tf_identifier.c | 2 +- drivers/net/bnxt/tf_core/tf_identifier.h | 3 +-- drivers/net/bnxt/tf_core/tf_if_tbl.h | 3 +-- drivers/net/bnxt/tf_core/tf_msg_common.h | 3 +-- drivers/net/bnxt/tf_core/tf_project.h | 3 +-- drivers/net/bnxt/tf_core/tf_resources.h| 3 +-- drivers/net/bnxt/tf_core/tf_rm.h | 6 +- drivers/net/bnxt/tf_core/tf_session.h | 1 - drivers/net/bnxt/tf_core/tf_sram_mgr.h | 1 - drivers/net/bnxt/tf_core/tf_tbl.h | 4 +--- drivers/net/bnxt/tf_core/tf_tbl_sram.h | 6 +- drivers/net/bnxt/tf_core/tf_tcam.h | 3 +-- drivers/net/bnxt/tf_core/tf_tcam_shared.h | 1 - drivers/net/bnxt/tf_core/tf_util.c | 3 +-- drivers/net/bnxt/tf_core/tf_util.h | 3 +-- drivers/net/bnxt/tf_core/tfp.c | 2 +- drivers/net/bnxt/tf_core/tfp.h | 4 +--- drivers/net/bnxt/tf_ulp/bnxt_tf_common.h | 3 +-- drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h | 1 - drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 1 - drivers/net/bnxt/tf_ulp/ulp_fc_mgr.h | 1 - drivers/net/bnxt/tf_ulp/ulp_flow_db.h | 1 - drivers/net/bnxt/tf_ulp/ulp_gen_hash.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_gen_hash.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h | 1 - drivers/net/bnxt/tf_ulp/ulp_ha_mgr.h | 1 - drivers/net/bnxt/tf_ulp/ulp_mapper.h | 1 - drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_mark_mgr.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_matcher.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_port_db.h | 1 - drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 1 - drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 1 - drivers/net/bnxt/tf_ulp/ulp_tun.c | 2 +- drivers/net/bnxt/tf_ulp/ulp_tun.h | 3 +-- drivers/net/bnxt/tf_ulp/ulp_utils.c| 2 +- drivers/net/bnxt/tf_ulp/ulp_utils.h| 3 +-- 87 files changed, 73
[PATCH v2 07/11] net/bnxt: add ulp support for rte meter
Add RTE meter support into the ULP layer
Signed-off-by: Randy Schacher
Reviewed-by: Jay Ding
---
drivers/net/bnxt/bnxt.h | 2 +
drivers/net/bnxt/bnxt_ethdev.c| 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c| 8 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.h| 3 +
drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c | 909 ++
drivers/net/bnxt/tf_ulp/meson.build | 1 +
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 29 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
9 files changed, 960 insertions(+), 2 deletions(-)
create mode 100644 drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index bbbc21fbaf..09b108e297 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -1025,6 +1025,7 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
struct rte_eth_udp_tunnel *udp_tunnel);
extern const struct rte_flow_ops bnxt_flow_ops;
+extern const struct rte_flow_ops bnxt_flow_meter_ops;
#define bnxt_acquire_flow_lock(bp) \
pthread_mutex_lock(&(bp)->flow_lock)
@@ -1076,6 +1077,7 @@ int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
void bnxt_handle_vf_cfg_change(void *arg);
+int bnxt_flow_meter_ops_get(struct rte_eth_dev *eth_dev, void *arg);
struct bnxt_vnic_info *bnxt_get_default_vnic(struct bnxt *bp);
struct tf *bnxt_get_tfp_session(struct bnxt *bp, enum bnxt_session_type type);
#endif
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index d275d8cb26..033ec176bf 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -4095,6 +4095,7 @@ static const struct eth_dev_ops bnxt_dev_ops = {
.timesync_adjust_time = bnxt_timesync_adjust_time,
.timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
+ .mtr_ops_get = bnxt_flow_meter_ops_get,
};
static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 08eb0c6063..3459140f18 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1681,6 +1681,14 @@ bnxt_ulp_init(struct bnxt *bp,
return rc;
}
+ if (ulp_dev_id == BNXT_ULP_DEVICE_ID_THOR) {
+ rc = bnxt_flow_meter_init(bp);
+ if (rc) {
+ BNXT_TF_DBG(ERR, "Failed to config meter\n");
+ goto jump_to_error;
+ }
+ }
+
BNXT_TF_DBG(DEBUG, "ulp ctx has been initialized\n");
return rc;
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index 53d76e1465..a6ad5c1eaa 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -371,6 +371,9 @@ bnxt_ulp_vxlan_ip_port_set(struct bnxt_ulp_context *ulp_ctx,
unsigned int
bnxt_ulp_vxlan_ip_port_get(struct bnxt_ulp_context *ulp_ctx);
+int32_t
+bnxt_flow_meter_init(struct bnxt *bp);
+
uint32_t
bnxt_ulp_cntxt_convert_dev_id(uint32_t ulp_dev_id);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
new file mode 100644
index 00..2461c46f90
--- /dev/null
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp_meter.c
@@ -0,0 +1,909 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014-2023 Broadcom
+ * All rights reserved.
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "bnxt.h"
+#include "bnxt_filter.h"
+#include "bnxt_hwrm.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxq.h"
+#include "bnxt_rxr.h"
+#include "bnxt_vnic.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "tfp.h"
+#include "bnxt_tf_common.h"
+#include "ulp_rte_parser.h"
+#include "ulp_matcher.h"
+#include "ulp_flow_db.h"
+#include "ulp_mapper.h"
+#include "ulp_fc_mgr.h"
+#include "ulp_port_db.h"
+#include "ulp_ha_mgr.h"
+#include "ulp_tun.h"
+#include
+
+/**
+ * Meter init status
+ */
+int bnxt_meter_initialized;
+
+/**
+ * Internal api to config global config.
+ * returns 0 on success.
+ */
+static int32_t
+bnxt_meter_global_cfg_update(struct bnxt *bp,
+enum tf_dir dir,
+enum tf_global_config_type type,
+uint32_t offset,
+uint32_t value,
+uint32_t set_flag)
+{
+ uint32_t global_cfg = 0;
+ struct tf_global_cfg_parms parms = { 0 };
+ struct tf *tfp;
+ int32_t rc = 0;
+
+ parms.dir = dir,
+ parms.type = type,
+ parms.offset = offset,
+ parms.config = (ui
[PATCH v2 08/11] net/bnxt: update PTP support on Thor
add locking and time stamp checks to ptp feature
Signed-off-by: Randy Schacher
Reviewed-by: Ajit Khaparde
---
drivers/net/bnxt/bnxt.h| 5 ++
drivers/net/bnxt/bnxt_ethdev.c | 11 +
drivers/net/bnxt/bnxt_hwrm.c | 11 -
drivers/net/bnxt/bnxt_ring.c | 3 ++
drivers/net/bnxt/bnxt_rxr.c| 8 +++-
drivers/net/bnxt/bnxt_txq.c| 1 +
drivers/net/bnxt/bnxt_txr.c| 85 --
drivers/net/bnxt/bnxt_txr.h| 1 +
8 files changed, 119 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 09b108e297..9dd663e0c2 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -349,6 +349,7 @@ struct bnxt_ptp_cfg {
BNXT_PTP_MSG_PDELAY_RESP)
uint8_t tx_tstamp_en:1;
int rx_filter;
+ uint8_t filter_all;
#define BNXT_PTP_RX_TS_L 0
#define BNXT_PTP_RX_TS_H 1
@@ -372,6 +373,8 @@ struct bnxt_ptp_cfg {
/* On P5, the Rx timestamp is present in the Rx completion record */
uint64_trx_timestamp;
uint64_tcurrent_time;
+ uint64_told_time;
+ rte_spinlock_t ptp_lock;
};
struct bnxt_coal {
@@ -733,6 +736,7 @@ struct bnxt {
#define BNXT_FW_CAP_LINK_ADMIN BIT(7)
#define BNXT_FW_CAP_TRUFLOW_EN BIT(8)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT(9)
+#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT(10)
#define BNXT_TRUFLOW_EN(bp)((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN &&\
(bp)->app_id != 0xFF)
@@ -860,6 +864,7 @@ struct bnxt {
struct bnxt_led_info*leds;
uint8_t ieee_1588;
struct bnxt_ptp_cfg *ptp_cfg;
+ uint8_t ptp_all_rx_tstamp;
uint16_tvf_resv_strategy;
struct bnxt_ctx_mem_info*ctx;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 033ec176bf..feba137959 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -1441,8 +1441,11 @@ static void bnxt_ptp_get_current_time(void *arg)
if (!ptp)
return;
+ rte_spinlock_lock(&ptp->ptp_lock);
+ ptp->old_time = ptp->current_time;
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
if (rc != 0) {
PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
@@ -1458,8 +1461,11 @@ static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
return 0;
+ rte_spinlock_lock(&ptp->ptp_lock);
bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
&ptp->current_time);
+ ptp->old_time = ptp->current_time;
+ rte_spinlock_unlock(&ptp->ptp_lock);
rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
@@ -3615,12 +3621,15 @@ bnxt_timesync_enable(struct rte_eth_dev *dev)
ptp->rx_filter = 1;
ptp->tx_tstamp_en = 1;
+ ptp->filter_all = 1;
ptp->rxctl = BNXT_PTP_MSG_EVENTS;
rc = bnxt_hwrm_ptp_cfg(bp);
if (rc)
return rc;
+ rte_spinlock_init(&ptp->ptp_lock);
+ bp->ptp_all_rx_tstamp = 1;
memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
@@ -3657,9 +3666,11 @@ bnxt_timesync_disable(struct rte_eth_dev *dev)
ptp->rx_filter = 0;
ptp->tx_tstamp_en = 0;
ptp->rxctl = 0;
+ ptp->filter_all = 0;
bnxt_hwrm_ptp_cfg(bp);
+ bp->ptp_all_rx_tstamp = 0;
if (!BNXT_CHIP_P5(bp))
bnxt_unmap_ptp_regs(bp);
else
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 77588bdf49..82679d1b32 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -669,6 +669,11 @@ int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
+ if (ptp->filter_all)
+ flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
+ else if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
+ flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
+
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
@@ -810,7 +815,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
struct hwrm_func_qca
[PATCH v2 09/11] net/bnxt: fix multi-root card support
From: Kishore Padmanabha
Changed the logic to use device serial number to identify that
different ports belong to same physical card instead of the PCI
domain address.
Signed-off-by: Kishore Padmanabha
Reviewed-by: Shahaji Bhosle
---
drivers/net/bnxt/bnxt.h| 3 +++
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c | 11 ---
drivers/net/bnxt/tf_ulp/bnxt_ulp.h | 2 ++
4 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index 9dd663e0c2..ea678d40d2 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -138,6 +138,7 @@
#define BNXT_NUM_CMPL_DMA_AGGR 36
#define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
#define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
+#define BNXT_DEVICE_SERIAL_NUM_SIZE8
#defineBNXT_DEFAULT_VNIC_STATE_MASK\
HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
@@ -874,6 +875,8 @@ struct bnxt {
uint16_tnum_reps;
struct bnxt_rep_info*rep_info;
uint16_t*cfa_code_map;
+ /* Device Serial Number */
+ uint8_t dsn[BNXT_DEVICE_SERIAL_NUM_SIZE];
/* Struct to hold adapter error recovery related info */
struct bnxt_error_recovery_info *recovery_info;
#define BNXT_MARK_TABLE_SZ (sizeof(struct bnxt_mark_info) * 64 * 1024)
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 82679d1b32..edad84c262 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -863,6 +863,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
+ memcpy(bp->dsn, resp->device_serial_number, sizeof(bp->dsn));
if (BNXT_PF(bp))
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
index 3459140f18..500c177039 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.c
@@ -1318,9 +1318,13 @@ ulp_get_session(struct bnxt *bp, struct rte_pci_addr
*pci_addr)
/* if multi root capability is enabled, then ignore the pci bus id */
STAILQ_FOREACH(session, &bnxt_ulp_session_list, next) {
- if (session->pci_info.domain == pci_addr->domain &&
- (BNXT_MULTIROOT_EN(bp) ||
- session->pci_info.bus == pci_addr->bus)) {
+ if (BNXT_MULTIROOT_EN(bp)) {
+ if (!memcmp(bp->dsn, session->dsn,
+ sizeof(session->dsn))) {
+ return session;
+ }
+ } else if (session->pci_info.domain == pci_addr->domain &&
+ session->pci_info.bus == pci_addr->bus) {
return session;
}
}
@@ -1364,6 +1368,7 @@ ulp_session_init(struct bnxt *bp,
/* Add it to the queue */
session->pci_info.domain = pci_addr->domain;
session->pci_info.bus = pci_addr->bus;
+ memcpy(session->dsn, bp->dsn, sizeof(session->dsn));
rc = pthread_mutex_init(&session->bnxt_ulp_mutex, NULL);
if (rc) {
BNXT_TF_DBG(ERR, "mutex create failed\n");
diff --git a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
index a6ad5c1eaa..92db7751fe 100644
--- a/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
+++ b/drivers/net/bnxt/tf_ulp/bnxt_ulp.h
@@ -131,11 +131,13 @@ struct bnxt_ulp_pci_info {
uint8_t bus;
};
+#define BNXT_ULP_DEVICE_SERIAL_NUM_SIZE 8
struct bnxt_ulp_session_state {
STAILQ_ENTRY(bnxt_ulp_session_state)next;
boolbnxt_ulp_init;
pthread_mutex_t bnxt_ulp_mutex;
struct bnxt_ulp_pci_infopci_info;
+ uint8_t dsn[BNXT_ULP_DEVICE_SERIAL_NUM_SIZE];
struct bnxt_ulp_data*cfg_data;
struct tf *g_tfp[BNXT_ULP_SESSION_MAX];
uint32_tsession_opened[BNXT_ULP_SESSION_MAX];
--
2.25.1
[PATCH v2 10/11] net/bnxt: add ulp support for ecpri
Add RTE ECPRI support into the ULP layer
Signed-off-by: Randy Schacher
Signed-off-by: Shahaji Bhosle
Reviewed-by: Manish Kurup
---
drivers/net/bnxt/bnxt.h | 4 +
drivers/net/bnxt/bnxt_ethdev.c| 35 +
drivers/net/bnxt/bnxt_hwrm.c | 17 +++
drivers/net/bnxt/bnxt_txr.c | 10 +-
drivers/net/bnxt/bnxt_vnic.c | 5 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.c| 7 +-
drivers/net/bnxt/tf_ulp/bnxt_tf_pmd_shim.h| 1 +
drivers/net/bnxt/tf_ulp/bnxt_ulp.c| 24
drivers/net/bnxt/tf_ulp/bnxt_ulp.h| 9 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 18 +++
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c | 4 +
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c | 120 +-
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h | 5 +
drivers/net/bnxt/tf_ulp/ulp_template_struct.h | 2 +
14 files changed, 254 insertions(+), 7 deletions(-)
diff --git a/drivers/net/bnxt/bnxt.h b/drivers/net/bnxt/bnxt.h
index ea678d40d2..43e122a641 100644
--- a/drivers/net/bnxt/bnxt.h
+++ b/drivers/net/bnxt/bnxt.h
@@ -855,10 +855,14 @@ struct bnxt {
uint8_t port_cnt;
uint8_t vxlan_port_cnt;
uint8_t geneve_port_cnt;
+ uint8_t ecpri_port_cnt;
uint16_tvxlan_port;
uint16_tgeneve_port;
+ uint16_tecpri_port;
uint16_tvxlan_fw_dst_port_id;
uint16_tgeneve_fw_dst_port_id;
+ uint16_tecpri_fw_dst_port_id;
+ uint16_tecpri_upar_in_use;
uint32_tfw_ver;
uint32_thwrm_spec_code;
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index feba137959..72494ee1da 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -2405,6 +2405,20 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
tunnel_type =
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
+ udp_tunnel->udp_port);
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Only one port allowed\n");
+ return -ENOSPC;
+ }
+ bp->ecpri_port_cnt++;
+ return 0;
+ }
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
@@ -2423,6 +2437,10 @@ bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
bp->geneve_port_cnt++;
+ if (tunnel_type ==
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI)
+ bp->ecpri_port_cnt++;
+
return rc;
}
@@ -2474,6 +2492,23 @@ bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
port = bp->geneve_fw_dst_port_id;
break;
+ case RTE_ETH_TUNNEL_TYPE_ECPRI:
+ if (!bp->ecpri_port_cnt) {
+ PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
+ return -EINVAL;
+ }
+ if (bp->ecpri_port != udp_tunnel->udp_port) {
+ PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
+ udp_tunnel->udp_port, bp->ecpri_port);
+ return -EINVAL;
+ }
+ if (--bp->ecpri_port_cnt)
+ return 0;
+
+ tunnel_type =
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI;
+ port = bp->ecpri_fw_dst_port_id;
+ break;
default:
PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
return -ENOTSUP;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index edad84c262..b944547656 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -2969,6 +2969,10 @@ bnxt_free_tunnel_ports(struct bnxt *bp)
if (bp->geneve_port_cnt)
bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
+
+ if (bp->ecpri_port_cnt)
+ bnxt_hwrm_tunnel_dst_port_free(bp, bp->ecpri_fw_dst_port_id,
+ HWRM_TUNNEL_
[PATCH v2 11/11] net/bnxt: Avoid submitting hwrm rss request when rss mode disabled
From: Shuanglin Wang On WH+, if rss mode isn't enabled, then there is no rss context. Submitting HWRM_VNIC_RSS_CFG request to firmware would hit a failure. The fix is to check the rss context. If no rss context, then don't submit the hwrm request. Signed-off-by: Shuanglin Wang Signed-off-by: Kishore Padmanabha Reviewed-by: Michael Baucom Reviewed-by: Shuanglin Wang --- drivers/net/bnxt/bnxt_hwrm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c index b944547656..06f196760f 100644 --- a/drivers/net/bnxt/bnxt_hwrm.c +++ b/drivers/net/bnxt/bnxt_hwrm.c @@ -2405,6 +2405,9 @@ bnxt_hwrm_vnic_rss_cfg_non_p5(struct bnxt *bp, struct bnxt_vnic_info *vnic) struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr; int rc = 0; + if (vnic->num_lb_ctxts == 0) + return rc; + HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB); req.hash_type = rte_cpu_to_le_32(vnic->hash_type); -- 2.25.1
[RFC] ring: improve ring performance with C11 atomics
Tail load in __rte_ring_move_cons_head and __rte_ring_move_prod_head can be changed to __ATOMIC_RELAXED from __ATOMIC_ACQUIRE. Because to calculate the addresses of the dequeue elements __rte_ring_dequeue_elems uses the old_head updated by the __atomic_compare_exchange_n intrinsic used in __rte_ring_move_prod_head. This results in an address dependency between the two operations. Therefore __rte_ring_dequeue_elems cannot happen before __rte_ring_move_prod_head. Similarly __rte_ring_enqueue_elems and __rte_ring_move_cons_head won't be reordered either. Performance on Arm N1 Gain relative to generic implementation +---+ | Bulk enq/dequeue count on size 8 (Arm N1) | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 766730 | Total count: 651686 | Total count: 812125 | | |Gain: -15%|Gain: 6% | +---+ +---+ | Bulk enq/dequeue count on size 32 (Arm N1)| +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 816745 | Total count: 646385 | Total count: 830935 | | |Gain: -21%|Gain: 2% | +---+ Performance on x86-64 Cascade Lake Gain relative to generic implementation +---+ | Bulk enq/dequeue count on size 8 | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 181640 | Total count: 181995 | Total count: 182791 | | |Gain: 0.2%|Gain: 0.6% +---+ +---+ | Bulk enq/dequeue count on size 32 | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 167495 | Total count: 161536 | Total count: 163190 | | |Gain: -3.5% |Gain: -2.6% | +---+ Signed-off-by: Wathsala Vithanage Reviewed-by: Honnappa Nagarahalli Reviewed-by: Feifei Wang --- .mailmap| 1 + lib/ring/rte_ring_c11_pvt.h | 18 +- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/.mailmap b/.mailmap index 4018f0fc47..367115d134 100644 --- a/.mailmap +++ b/.mailmap @@ -1430,6 +1430,7 @@ Walter Heymans Wang Sheng-Hui Wangyu (Eric) Waterman Cao +Wathsala Vithanage Weichun Chen Wei Dai Weifeng Li diff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h index f895950df4..1895f2bb0e 100644 --- a/lib/ring/rte_ring_c11_pvt.h +++ b/lib/ring/rte_ring_c11_pvt.h @@ -24,6 +24,13 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val, if (!single) rte_wait_until_equal_32(&ht->tail, old_val, __ATOMIC_RELAXED); + /* +* Updating of ht->tail cannot happen before elements are added to or +* removed from the ring, as it could result in data races between +* producer and consumer threads. Therefore ht->tail should be updated +* with release semantics to prevent ring data copy phase from sinking +* below it. +*/ __atomic_store_n(&ht->tail, new_val, __ATOMIC_RELEASE); } @@ -69,11 +76,8 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp, /* Ensure the head is read before tail */ __atomic_thread_fence(__ATOMIC_ACQUIRE); - /* load-acquire synchronize with store-release of ht->tail -* in update_tail. -*/ cons_tail = __atomic_load_n(&r->cons.tail, - __ATOMIC_ACQUIRE); + __ATOMIC_RELAXED); /* The subtraction is done between two unsigned 32bits value * (the result is always modulo 32 bits even if we have @@ -145,12 +149,8 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc, /* Ensure the head is read before
[RFC] ring: improve ring performance with C11 atomics
Tail load in __rte_ring_move_cons_head and __rte_ring_move_prod_head can be changed to __ATOMIC_RELAXED from __ATOMIC_ACQUIRE. Because to calculate the addresses of the dequeue elements __rte_ring_dequeue_elems uses the old_head updated by the __atomic_compare_exchange_n intrinsic used in __rte_ring_move_prod_head. This results in an address dependency between the two operations. Therefore __rte_ring_dequeue_elems cannot happen before __rte_ring_move_prod_head. Similarly __rte_ring_enqueue_elems and __rte_ring_move_cons_head won't be reordered either. Performance on Arm N1 Gain relative to generic implementation +---+ | Bulk enq/dequeue count on size 8 (Arm N1) | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 766730 | Total count: 651686 | Total count: 812125 | | |Gain: -15%|Gain: 6% | +---+ +---+ | Bulk enq/dequeue count on size 32 (Arm N1)| +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 816745 | Total count: 646385 | Total count: 830935 | | |Gain: -21%|Gain: 2% | +---+ Performance on x86-64 Cascade Lake Gain relative to generic implementation +---+ | Bulk enq/dequeue count on size 8 | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 181640 | Total count: 181995 | Total count: 182791 | | |Gain: 0.2%|Gain: 0.6% +---+ +---+ | Bulk enq/dequeue count on size 32 | +---+ | Generic | C11 atomics | C11 atomics improved | +---+ | Total count: 167495 | Total count: 161536 | Total count: 163190 | | |Gain: -3.5% |Gain: -2.6% | +---+ Signed-off-by: Wathsala Vithanage Reviewed-by: Honnappa Nagarahalli Reviewed-by: Feifei Wang --- .mailmap| 1 + lib/ring/rte_ring_c11_pvt.h | 18 +- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/.mailmap b/.mailmap index 4018f0fc47..367115d134 100644 --- a/.mailmap +++ b/.mailmap @@ -1430,6 +1430,7 @@ Walter Heymans Wang Sheng-Hui Wangyu (Eric) Waterman Cao +Wathsala Vithanage Weichun Chen Wei Dai Weifeng Li diff --git a/lib/ring/rte_ring_c11_pvt.h b/lib/ring/rte_ring_c11_pvt.h index f895950df4..1895f2bb0e 100644 --- a/lib/ring/rte_ring_c11_pvt.h +++ b/lib/ring/rte_ring_c11_pvt.h @@ -24,6 +24,13 @@ __rte_ring_update_tail(struct rte_ring_headtail *ht, uint32_t old_val, if (!single) rte_wait_until_equal_32(&ht->tail, old_val, __ATOMIC_RELAXED); + /* +* Updating of ht->tail cannot happen before elements are added to or +* removed from the ring, as it could result in data races between +* producer and consumer threads. Therefore ht->tail should be updated +* with release semantics to prevent ring data copy phase from sinking +* below it. +*/ __atomic_store_n(&ht->tail, new_val, __ATOMIC_RELEASE); } @@ -69,11 +76,8 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp, /* Ensure the head is read before tail */ __atomic_thread_fence(__ATOMIC_ACQUIRE); - /* load-acquire synchronize with store-release of ht->tail -* in update_tail. -*/ cons_tail = __atomic_load_n(&r->cons.tail, - __ATOMIC_ACQUIRE); + __ATOMIC_RELAXED); /* The subtraction is done between two unsigned 32bits value * (the result is always modulo 32 bits even if we have @@ -145,12 +149,8 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc, /* Ensure the head is read before
Re: [PATCH] ci: switch to Fedora 37
David Marchand writes: > Fedora 35 has been declared EOL in 2022/12 (see [1]). > Fedora 36 will soon be EOL too. > > Move to Fedora 37. > Fedora 37 libbpf does not support AF_XDP anymore, now provided by > libxdp. > > 1: https://docs.fedoraproject.org/en-US/releases/eol/ > > Signed-off-by: David Marchand > --- Acked-by: Aaron Conole FYI, Fedora 38 also just got released. Perhaps that can be a candidate as well, but I didn't try it out.
[PATCH v5] app/testpmd: txonly multiflow port change support
Google cloud routes traffic using IP addresses without the support of MAC
addresses, so changing source IP address for txonly-multi-flow can have
negative performance implications for net/gve when using testpmd. This
patch updates txonly multiflow mode to modify source ports instead of
source IP addresses.
The change can be tested with the following command:
dpdk-testpmd -- --forward-mode=txonly --txonly-multi-flow \
--tx-ip=,
Signed-off-by: Joshua Washington
Reviewed-by: Rushil Gupta
---
app/test-pmd/txonly.c | 39 +++
1 file changed, 23 insertions(+), 16 deletions(-)
diff --git a/app/test-pmd/txonly.c b/app/test-pmd/txonly.c
index b3d6873104..f79e0e5d0b 100644
--- a/app/test-pmd/txonly.c
+++ b/app/test-pmd/txonly.c
@@ -56,7 +56,7 @@ uint32_t tx_ip_dst_addr = (198U << 24) | (18 << 16) | (0 <<
8) | 2;
#define IP_DEFTTL 64 /* from RFC 1340. */
static struct rte_ipv4_hdr pkt_ip_hdr; /**< IP header of transmitted packets.
*/
-RTE_DEFINE_PER_LCORE(uint8_t, _ip_var); /**< IP address variation */
+RTE_DEFINE_PER_LCORE(uint8_t, _src_var); /**< Source port variation */
static struct rte_udp_hdr pkt_udp_hdr; /**< UDP header of tx packets. */
static uint64_t timestamp_mask; /**< Timestamp dynamic flag mask */
@@ -230,28 +230,35 @@ pkt_burst_prepare(struct rte_mbuf *pkt, struct
rte_mempool *mbp,
copy_buf_to_pkt(eth_hdr, sizeof(*eth_hdr), pkt, 0);
copy_buf_to_pkt(&pkt_ip_hdr, sizeof(pkt_ip_hdr), pkt,
sizeof(struct rte_ether_hdr));
+ copy_buf_to_pkt(&pkt_udp_hdr, sizeof(pkt_udp_hdr), pkt,
+ sizeof(struct rte_ether_hdr) +
+ sizeof(struct rte_ipv4_hdr));
if (txonly_multi_flow) {
- uint8_t ip_var = RTE_PER_LCORE(_ip_var);
- struct rte_ipv4_hdr *ip_hdr;
- uint32_t addr;
+ uint16_t src_var = RTE_PER_LCORE(_src_var);
+ struct rte_udp_hdr *udp_hdr;
+ uint16_t port;
- ip_hdr = rte_pktmbuf_mtod_offset(pkt,
- struct rte_ipv4_hdr *,
- sizeof(struct rte_ether_hdr));
+ udp_hdr = rte_pktmbuf_mtod_offset(pkt,
+ struct rte_udp_hdr *,
+ sizeof(struct rte_ether_hdr) +
+ sizeof(struct rte_ipv4_hdr));
/*
-* Generate multiple flows by varying IP src addr. This
-* enables packets are well distributed by RSS in
+* Generate multiple flows by varying UDP source port.
+* This enables packets are well distributed by RSS in
* receiver side if any and txonly mode can be a decent
* packet generator for developer's quick performance
* regression test.
+*
+* Only ports in the range 49152 (0xC000) and 65535 (0x)
+* will be used, with the least significant byte representing
+* the lcore ID. As such, the most significant byte will cycle
+* through 0xC0 and 0xFF.
*/
- addr = (tx_ip_dst_addr | (ip_var++ << 8)) + rte_lcore_id();
- ip_hdr->src_addr = rte_cpu_to_be_32(addr);
- RTE_PER_LCORE(_ip_var) = ip_var;
+ port = src_var++) % (0xFF - 0xC0) + 0xC0) & 0xFF) << 8)
+ + rte_lcore_id();
+ udp_hdr->src_port = rte_cpu_to_be_16(port);
+ RTE_PER_LCORE(_src_var) = src_var;
}
- copy_buf_to_pkt(&pkt_udp_hdr, sizeof(pkt_udp_hdr), pkt,
- sizeof(struct rte_ether_hdr) +
- sizeof(struct rte_ipv4_hdr));
if (unlikely(tx_pkt_split == TX_PKT_SPLIT_RND) || txonly_multi_flow)
update_pkt_header(pkt, pkt_len);
@@ -393,7 +400,7 @@ pkt_burst_transmit(struct fwd_stream *fs)
nb_tx = common_fwd_stream_transmit(fs, pkts_burst, nb_pkt);
if (txonly_multi_flow)
- RTE_PER_LCORE(_ip_var) -= nb_pkt - nb_tx;
+ RTE_PER_LCORE(_src_var) -= nb_pkt - nb_tx;
if (unlikely(nb_tx < nb_pkt)) {
if (verbose_level > 0 && fs->fwd_dropped == 0)
--
2.40.0.634.g4ca3ef3211-goog
Re: [PATCH 1/1] net/ixgbe: add a proper memory barrier for LoongArch
在 2023/4/21 9:12, zhoumin 写道: On Fri, Apr 7, 2023 at 4:50PM, Min Zhou wrote: Segmentation fault has been observed while running the ixgbe_recv_pkts_lro() function to receive packets on the Loongson 3C5000 processor which has 64 cores and 4 NUMA nodes. Reason is the read ordering of the status and the rest of the descriptor fields in this function may not be correct on the LoongArch processor. We should add rte_rmb() to ensure the read ordering be correct. We also did the same thing in the ixgbe_recv_pkts() function. Signed-off-by: Min Zhou --- drivers/net/ixgbe/ixgbe_rxtx.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index c9d6ca9efe..16391a42f9 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -1823,6 +1823,9 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, staterr = rxdp->wb.upper.status_error; if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) break; +#if defined(RTE_ARCH_LOONGARCH) + rte_rmb(); +#endif rxd = *rxdp; Hi Min, Could you add more detailed analysis aboout the issu? Althrough rxdp is declared as volatile, which is only in order for compiler. However some architectures like LoongArch are weak-ordered. For this piece of code: 1: staterr = rxdp->wb.upper.status_error; Sentence 1 can be execute after sentence 1, dd indicated that packet is ready with new value. 2: rxd = *rxdp; Sentence 2 can be execute first and get old value. ...Balabala Regards Bibo, Mao /* @@ -2122,6 +2125,9 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts, if (!(staterr & IXGBE_RXDADV_STAT_DD)) break; +#if defined(RTE_ARCH_LOONGARCH) + rte_rmb(); +#endif rxd = *rxdp; PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u " Kindly ping. Any comments or suggestions will be appreciated. Min
Re: [PATCH 2/2] config/arm: Enable NUMA for generic Arm build
On 2023/04/20 16:20, Ruifeng Wang wrote:
-Original Message-
From: Akihiko Odaki
Sent: Friday, April 14, 2023 8:42 PM
To: Ruifeng Wang ; Bruce Richardson
Cc: dev@dpdk.org; Akihiko Odaki
Subject: [PATCH 2/2] config/arm: Enable NUMA for generic Arm build
We enable NUMA even if the presence of NUMA is unknown for the other
architectures. Enable
NUMA for generic Arm build too.
Signed-off-by: Akihiko Odaki
---
config/arm/meson.build | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build index
724c00ad7e..f8ee7cdafb
100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -271,13 +271,15 @@ implementers = {
soc_generic = {
'description': 'Generic un-optimized build for armv8 aarch64 exec mode',
'implementer': 'generic',
-'part_number': 'generic'
+'part_number': 'generic',
+'numa': true
The default value of numa is true. So no need to add it here?
if not soc_config.get('numa', true)
has_libnuma = 0
endif
You're right. I confirmed this change is unnecessary. Please ignore this
patch and consider merging only the first patch of this series.
}
soc_generic_aarch32 = {
'description': 'Generic un-optimized build for armv8 aarch32 exec mode',
'implementer': 'generic',
-'part_number': 'generic_aarch32'
+'part_number': 'generic_aarch32',
+'numa': true
}
soc_armada = {
--
2.40.0
