[RFC 0/2] vhost: add port mirroring function in the vhost lib
Similar to the port mirroring function on the switch or router, this patch set also implements such function on the Vhost lib. When data is sent to a front-end, it will also send the data to its mirror front-end. When data is received from a front-end, it will also send the data to its mirrorfront-end. Cheng Jiang (1): vhost: add egress API for port mirroring datapath Wenwu Ma (1): vhost: add ingress API for port mirroring datapath lib/vhost/rte_vhost_async.h | 26 +- lib/vhost/version.map |5 + lib/vhost/vhost.h |3 +- lib/vhost/virtio_net.c | 2755 ++- 4 files changed, 2101 insertions(+), 688 deletions(-) -- 2.35.1
[RFC 1/2] vhost: add ingress API for port mirroring datapath
From: Wenwu Ma
Similar to the port mirroring function on the switch or router, this
patch also implements an ingress function on the Vhost lib. When
data is sent to a front-end, it will also send the data to its mirror
front-end.
Signed-off-by: Cheng Jiang
Signed-off-by: Wenwu Ma
---
lib/vhost/rte_vhost_async.h | 14 +-
lib/vhost/version.map | 2 +
lib/vhost/vhost.h | 3 +-
lib/vhost/virtio_net.c | 666 +++-
4 files changed, 679 insertions(+), 6 deletions(-)
diff --git a/lib/vhost/rte_vhost_async.h b/lib/vhost/rte_vhost_async.h
index ad71555a7f..b199af078c 100644
--- a/lib/vhost/rte_vhost_async.h
+++ b/lib/vhost/rte_vhost_async.h
@@ -29,6 +29,7 @@ struct rte_vhost_async_desc {
struct rte_vhost_iov_iter *src;
/** destination memory iov_iter */
struct rte_vhost_iov_iter *dst;
+ struct rte_vhost_iov_iter *mirror_dst;
};
/**
@@ -64,7 +65,7 @@ struct rte_vhost_async_channel_ops {
int32_t (*transfer_data)(int vid, uint16_t queue_id,
struct rte_vhost_async_desc *descs,
struct rte_vhost_async_status *opaque_data,
- uint16_t count);
+ uint16_t count, bool mirr_flag);
/**
* check copy-completed packets from the async engine
* @param vid
@@ -200,6 +201,12 @@ __rte_experimental
uint16_t rte_vhost_submit_enqueue_burst(int vid, uint16_t queue_id,
struct rte_mbuf **pkts, uint16_t count);
+__rte_experimental
+uint16_t
+rte_vhost_submit_ingress_mirroring_burst(int vid, uint16_t queue_id,
+ int mirror_vid, uint16_t mirror_queue_id, struct rte_mbuf
**pkts, uint16_t count);
+
+
/**
* This function checks async completion status for a specific vhost
* device queue. Packets which finish copying (enqueue) operation
@@ -220,6 +227,11 @@ __rte_experimental
uint16_t rte_vhost_poll_enqueue_completed(int vid, uint16_t queue_id,
struct rte_mbuf **pkts, uint16_t count);
+__rte_experimental
+uint16_t rte_vhost_poll_ingress_completed(int vid, uint16_t queue_id,
+ int mirror_vid, uint16_t mirror_queue_id,
+ struct rte_mbuf **pkts, uint16_t count);
+
/**
* This function returns the amount of in-flight packets for the vhost
* queue which uses async channel acceleration.
diff --git a/lib/vhost/version.map b/lib/vhost/version.map
index c92a9d4962..4c35fa4555 100644
--- a/lib/vhost/version.map
+++ b/lib/vhost/version.map
@@ -76,6 +76,8 @@ EXPERIMENTAL {
rte_vhost_async_channel_unregister;
rte_vhost_submit_enqueue_burst;
rte_vhost_poll_enqueue_completed;
+ rte_vhost_submit_ingress_mirroring_burst;
+ rte_vhost_poll_ingress_completed;
# added in 21.05
rte_vhost_get_negotiated_protocol_features;
diff --git a/lib/vhost/vhost.h b/lib/vhost/vhost.h
index 1e56311725..89a31e4ca8 100644
--- a/lib/vhost/vhost.h
+++ b/lib/vhost/vhost.h
@@ -49,7 +49,8 @@
#define MAX_PKT_BURST 32
#define VHOST_MAX_ASYNC_IT (MAX_PKT_BURST * 2)
-#define VHOST_MAX_ASYNC_VEC (BUF_VECTOR_MAX * 4)
+#define MAX_ASYNC_COPY_VECTOR 1024
+#define VHOST_MAX_ASYNC_VEC (MAX_ASYNC_COPY_VECTOR * 2)
#define PACKED_DESC_ENQUEUE_USED_FLAG(w) \
((w) ? (VRING_DESC_F_AVAIL | VRING_DESC_F_USED | VRING_DESC_F_WRITE) : \
diff --git a/lib/vhost/virtio_net.c b/lib/vhost/virtio_net.c
index f6127c7d52..c9f0bb22e5 100644
--- a/lib/vhost/virtio_net.c
+++ b/lib/vhost/virtio_net.c
@@ -1575,7 +1575,7 @@ virtio_dev_rx_async_submit_split(struct virtio_net *dev,
((VHOST_MAX_ASYNC_VEC >> 1) - segs_await <
BUF_VECTOR_MAX))) {
n_xfer = vq->async_ops.transfer_data(dev->vid,
- queue_id, tdes, 0, pkt_burst_idx);
+ queue_id, tdes, 0, pkt_burst_idx,
false);
if (likely(n_xfer >= 0)) {
n_pkts = n_xfer;
} else {
@@ -1606,7 +1606,7 @@ virtio_dev_rx_async_submit_split(struct virtio_net *dev,
}
if (pkt_burst_idx) {
- n_xfer = vq->async_ops.transfer_data(dev->vid, queue_id, tdes,
0, pkt_burst_idx);
+ n_xfer = vq->async_ops.transfer_data(dev->vid, queue_id, tdes,
0, pkt_burst_idx, false);
if (likely(n_xfer >= 0)) {
n_pkts = n_xfer;
} else {
@@ -1873,7 +1873,7 @@ virtio_dev_rx_async_submit_packed(struct virtio_net *dev,
if (unlikely(pkt_burst_idx >= VHOST_ASYNC_BATCH_THRESHOLD ||
((VHOST_MAX_ASYNC_VEC >> 1) - segs_await <
BUF_VECTOR_MAX))) {
n_xfer = vq->async_ops.transfer_data(dev->vid,
- queue_id, tdes, 0, pkt_burst_idx);
+ queue_id, tdes, 0, pkt_burst_idx,
false);
if (likely(n_xfer
[RFC 2/2] vhost: add egress API for port mirroring datapath
This patch implements such an egress function on the Vhost lib. When
data is received from a front-end, it will also send the data to its
mirrorfront-end.
Signed-off-by: Cheng Jiang
Signed-off-by: Wenwu Ma
---
lib/vhost/rte_vhost_async.h | 12 +-
lib/vhost/version.map | 3 +
lib/vhost/virtio_net.c | 729
3 files changed, 742 insertions(+), 2 deletions(-)
diff --git a/lib/vhost/rte_vhost_async.h b/lib/vhost/rte_vhost_async.h
index b199af078c..b0772c2db7 100644
--- a/lib/vhost/rte_vhost_async.h
+++ b/lib/vhost/rte_vhost_async.h
@@ -85,11 +85,12 @@ struct rte_vhost_async_channel_ops {
};
/**
- * inflight async packet information
+ * in-flight async packet information
*/
struct async_inflight_info {
struct rte_mbuf *mbuf;
- uint16_t descs; /* num of descs inflight */
+ struct virtio_net_hdr nethdr;
+ uint16_t descs; /* num of descs in-flight */
uint16_t nr_buffers; /* num of buffers inflight for packed ring */
};
@@ -268,4 +269,11 @@ __rte_experimental
uint16_t rte_vhost_clear_queue_thread_unsafe(int vid, uint16_t queue_id,
struct rte_mbuf **pkts, uint16_t count);
+__rte_experimental
+uint16_t
+rte_vhost_async_try_egress_burst(int vid, uint16_t queue_id,
+ int mirr_vid, uint16_t mirr_queue_id,
+ struct rte_mempool *mbuf_pool, struct rte_mbuf **pkts, uint16_t count,
+ int *nr_inflight);
+
#endif /* _RTE_VHOST_ASYNC_H_ */
diff --git a/lib/vhost/version.map b/lib/vhost/version.map
index 4c35fa4555..2529943a91 100644
--- a/lib/vhost/version.map
+++ b/lib/vhost/version.map
@@ -87,4 +87,7 @@ EXPERIMENTAL {
rte_vhost_async_channel_register_thread_unsafe;
rte_vhost_async_channel_unregister_thread_unsafe;
rte_vhost_clear_queue_thread_unsafe;
+
+ # added in 21.11
+ rte_vhost_async_try_egress_burst;
};
diff --git a/lib/vhost/virtio_net.c b/lib/vhost/virtio_net.c
index c9f0bb22e5..92074377b2 100644
--- a/lib/vhost/virtio_net.c
+++ b/lib/vhost/virtio_net.c
@@ -3827,3 +3827,732 @@ rte_vhost_dequeue_burst(int vid, uint16_t queue_id,
return count;
}
+
+static __rte_always_inline uint16_t
+async_poll_egress_completed_split(struct virtio_net *dev,
+ struct vhost_virtqueue *vq, uint16_t queue_id,
+ struct virtio_net *mirr_dev, struct vhost_virtqueue *mirr_vq,
+ struct rte_mbuf **pkts, uint16_t count, bool legacy_ol_flags)
+{
+ uint16_t n_pkts_cpl = 0, n_pkts_put = 0;
+ uint16_t start_idx, pkt_idx, from;
+ struct async_inflight_info *pkts_info;
+ uint16_t mirror_n_pkts_cpl = 0, n_descs = 0;
+
+ pkt_idx = vq->async_pkts_idx & (vq->size - 1);
+ pkts_info = vq->async_pkts_info;
+ start_idx = virtio_dev_rx_async_get_info_idx(pkt_idx, vq->size,
+ vq->async_pkts_inflight_n);
+
+ if (count > vq->async_last_pkts_n) {
+ int ret;
+
+ ret = vq->async_ops.check_completed_copies(dev->vid, queue_id,
+ 0, count - vq->async_last_pkts_n);
+ if (unlikely(ret < 0)) {
+ VHOST_LOG_DATA(ERR, "(%d) async channel poll error\n",
dev->vid);
+ ret = 0;
+ }
+ n_pkts_cpl = ret;
+ }
+
+ n_pkts_cpl += vq->async_last_pkts_n;
+ mirror_n_pkts_cpl += mirr_vq->async_last_pkts_n;
+ if (unlikely(n_pkts_cpl == 0)) {
+ mirr_vq->async_last_pkts_n = mirror_n_pkts_cpl;
+ return 0;
+ }
+
+ n_pkts_put = RTE_MIN(count, n_pkts_cpl);
+
+ for (pkt_idx = 0; pkt_idx < n_pkts_put; pkt_idx++) {
+ from = (start_idx + pkt_idx) & (vq->size - 1);
+ pkts[pkt_idx] = pkts_info[from].mbuf;
+ n_descs += pkts_info[from].descs;
+
+ if (virtio_net_with_host_offload(dev))
+ vhost_dequeue_offload(&pkts_info[from].nethdr,
+ pkts[pkt_idx], legacy_ol_flags);
+ }
+
+ /* write back completed descs to used ring and update used idx */
+ write_back_completed_descs_split(vq, n_pkts_put);
+ __atomic_add_fetch(&vq->used->idx, n_pkts_put, __ATOMIC_RELEASE);
+ vhost_vring_call_split(dev, vq);
+
+ vq->async_last_pkts_n = n_pkts_cpl - n_pkts_put;
+ vq->async_pkts_inflight_n -= n_pkts_put;
+
+ if (likely(mirr_vq->enabled && mirr_vq->access_ok)) {
+ write_back_completed_descs_split(mirr_vq, n_descs);
+
+ __atomic_add_fetch(&mirr_vq->used->idx, n_descs,
+ __ATOMIC_RELEASE);
+ vhost_vring_call_split(mirr_dev, mirr_vq);
+ } else {
+ mirr_vq->last_async_desc_idx_split += n_descs;
+ }
+
+ return n_pkts_put;
+}
+
+static __rte_always_inline void
+egress_async_fill_desc(struct rte_vhost_async_desc *desc,
+ struct rte_vhost_iov_iter *src, struct rt
RE: [Patch v2] net/mlx4: fix verbs fd leak in the secondary process
Hi,
> -Original Message-
> From: lon...@linuxonhyperv.com
> Sent: Wednesday, July 6, 2022 8:49 PM
> To: Matan Azrad ; Ferruh Yigit
>
> Cc: dev@dpdk.org; Karanjot Singh ; NBU-
> Contact-longli (EXTERNAL)
> Subject: [Patch v2] net/mlx4: fix verbs fd leak in the secondary process
>
> From: Long Li
>
> FDs passed from rte_mp_msg are duplicated to the secondary process and
> need to be closed.
>
> Fixes: 0203d33a10 ("net/mlx4: support secondary process")
> Signed-off-by: Long Li
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
RE: [Patch v2] net/mlx5: fix verbs fd leak in the secondary process
Hi,
> -Original Message-
> From: lon...@linuxonhyperv.com
> Sent: Wednesday, July 6, 2022 8:49 PM
> To: Matan Azrad ; Ferruh Yigit
>
> Cc: dev@dpdk.org; Karanjot Singh ; NBU-
> Contact-longli (EXTERNAL)
> Subject: [Patch v2] net/mlx5: fix verbs fd leak in the secondary process
>
> From: Long Li
>
> FDs passed from rte_mp_msg are duplicated to the secondary process and
> need to be closed.
>
> Fixes: 9a8ab29b84 ("net/mlx5: replace IPC socket with EAL API")
> Signed-off-by: Long Li
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
RE: [PATCH v3] common/mlx5: update DevX error logging
Hi, > -Original Message- > From: Gregory Etelson > Sent: Sunday, July 10, 2022 7:03 PM > To: dev@dpdk.org > Cc: Gregory Etelson ; Matan Azrad > ; Raslan Darawsheh ; NBU- > Contact-Thomas Monjalon (EXTERNAL) ; Slava > Ovsiienko > Subject: [PATCH v3] common/mlx5: update DevX error logging > > Current PMD logs all DevX errors at error level. > > DevX interface can fail queue counters allocation on some hardware types. > That is a known issue. > PMD fallback to VERB API to allocate queue counters when it detects the > fault. > That DevX failure should not be logged as PMD error. > > The patch provides DevX with flexible API that selects log level. > > Signed-off-by: Gregory Etelson > Acked-by: Matan Azrad > --- > v2: fix warnings in old gcc versions > v3: remove cc stable Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh
[PATCH v1 0/2] vhost: introduce DMA vchannel unconfiguration
From: Xuan Ding This patchset introduces a new API rte_vhost_async_dma_unconfigure() to help user to manually free the DMA vchannel finished to use. Note: this API should be called after async channel unregister. Xuan Ding (2): vhost: introduce DMA vchannel unconfiguration example/vhost: unconfigure DMA vchannel doc/guides/prog_guide/vhost_lib.rst| 5 doc/guides/rel_notes/release_22_11.rst | 2 ++ examples/vhost/main.c | 7 + lib/vhost/rte_vhost_async.h| 17 lib/vhost/version.map | 3 +++ lib/vhost/vhost.c | 37 ++ 6 files changed, 71 insertions(+) -- 2.17.1
[PATCH v1 1/2] vhost: introduce DMA vchannel unconfiguration
From: Xuan Ding
This patch adds a new API rte_vhost_async_dma_unconfigure() to unconfigure
DMA vchannels in vhost async data path.
Signed-off-by: Xuan Ding
---
doc/guides/prog_guide/vhost_lib.rst| 5
doc/guides/rel_notes/release_22_11.rst | 2 ++
lib/vhost/rte_vhost_async.h| 17
lib/vhost/version.map | 3 +++
lib/vhost/vhost.c | 37 ++
5 files changed, 64 insertions(+)
diff --git a/doc/guides/prog_guide/vhost_lib.rst
b/doc/guides/prog_guide/vhost_lib.rst
index bad4d819e1..78b1943d29 100644
--- a/doc/guides/prog_guide/vhost_lib.rst
+++ b/doc/guides/prog_guide/vhost_lib.rst
@@ -323,6 +323,11 @@ The following is an overview of some key Vhost API
functions:
Get device type of vDPA device, such as VDPA_DEVICE_TYPE_NET,
VDPA_DEVICE_TYPE_BLK.
+* ``rte_vhost_async_dma_unconfigure(dma_id, vchan_id)``
+
+ Clear DMA vChannels finished to use. This function needs to
+ be called after async unregister.
+
Vhost-user Implementations
--
diff --git a/doc/guides/rel_notes/release_22_11.rst
b/doc/guides/rel_notes/release_22_11.rst
index 8c021cf050..e94c006e39 100644
--- a/doc/guides/rel_notes/release_22_11.rst
+++ b/doc/guides/rel_notes/release_22_11.rst
@@ -55,6 +55,8 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Added vhost API to unconfigure DMA vchannels.**
+ Added an API which helps to unconfigure DMA vchannels.
Removed Items
-
diff --git a/lib/vhost/rte_vhost_async.h b/lib/vhost/rte_vhost_async.h
index 1db2a10124..0442e027fd 100644
--- a/lib/vhost/rte_vhost_async.h
+++ b/lib/vhost/rte_vhost_async.h
@@ -266,6 +266,23 @@ rte_vhost_async_try_dequeue_burst(int vid, uint16_t
queue_id,
struct rte_mempool *mbuf_pool, struct rte_mbuf **pkts, uint16_t count,
int *nr_inflight, int16_t dma_id, uint16_t vchan_id);
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice.
+ *
+ * Unconfigure DMA vChannels in asynchronous data path.
+ *
+ * @param dma_id
+ * the identifier of DMA device
+ * @param vchan_id
+ * the identifier of virtual DMA channel
+ * @return
+ * 0 on success, and -1 on failure
+ */
+__rte_experimental
+int
+rte_vhost_async_dma_unconfigure(int16_t dma_id, uint16_t vchan_id);
+
#ifdef __cplusplus
}
#endif
diff --git a/lib/vhost/version.map b/lib/vhost/version.map
index 18574346d5..013a6bcc42 100644
--- a/lib/vhost/version.map
+++ b/lib/vhost/version.map
@@ -96,6 +96,9 @@ EXPERIMENTAL {
rte_vhost_async_try_dequeue_burst;
rte_vhost_driver_get_vdpa_dev_type;
rte_vhost_clear_queue;
+
+ # added in 22.11
+ rte_vhost_async_dma_unconfigure;
};
INTERNAL {
diff --git a/lib/vhost/vhost.c b/lib/vhost/vhost.c
index 60cb05a0ff..d215c917a2 100644
--- a/lib/vhost/vhost.c
+++ b/lib/vhost/vhost.c
@@ -1863,6 +1863,43 @@ rte_vhost_async_channel_unregister_thread_unsafe(int
vid, uint16_t queue_id)
return 0;
}
+int
+rte_vhost_async_dma_unconfigure(int16_t dma_id, uint16_t vchan_id)
+{
+ struct rte_dma_info info;
+ void *pkts_cmpl_flag_addr;
+
+ if (!rte_dma_is_valid(dma_id)) {
+ VHOST_LOG_CONFIG("dma", ERR, "DMA %d is not found.\n", dma_id);
+ return -1;
+ }
+
+ if (rte_dma_info_get(dma_id, &info) != 0) {
+ VHOST_LOG_CONFIG("dma", ERR, "Fail to get DMA %d
information.\n", dma_id);
+ return -1;
+ }
+
+ if (vchan_id >= info.max_vchans) {
+ VHOST_LOG_CONFIG("dma", ERR, "Invalid DMA %d vChannel %u.\n",
dma_id, vchan_id);
+ return -1;
+ }
+
+ pkts_cmpl_flag_addr =
dma_copy_track[dma_id].vchans[vchan_id].pkts_cmpl_flag_addr;
+ if (pkts_cmpl_flag_addr) {
+ rte_free(pkts_cmpl_flag_addr);
+ pkts_cmpl_flag_addr = NULL;
+ }
+
+ if (dma_copy_track[dma_id].vchans) {
+ rte_free(dma_copy_track[dma_id].vchans);
+ dma_copy_track[dma_id].vchans = NULL;
+ }
+
+ dma_copy_track[dma_id].nr_vchans--;
+
+ return 0;
+}
+
int
rte_vhost_async_dma_configure(int16_t dma_id, uint16_t vchan_id)
{
--
2.17.1
[PATCH v1 2/2] example/vhost: unconfigure DMA vchannel
From: Xuan Ding
This patch uses rte_vhost_async_dma_unconfigure() API
to manually free 'dma_coy_track' array rather than wait for
the program to finish before being freed.
Signed-off-by: Xuan Ding
---
examples/vhost/main.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/examples/vhost/main.c b/examples/vhost/main.c
index 7e1666f42a..1dba9724c2 100644
--- a/examples/vhost/main.c
+++ b/examples/vhost/main.c
@@ -2060,6 +2060,13 @@ main(int argc, char *argv[])
RTE_LCORE_FOREACH_WORKER(lcore_id)
rte_eal_wait_lcore(lcore_id);
+ for (i = 0; i < dma_count; i++) {
+ if (rte_vhost_async_dma_unconfigure(dmas_id[i], 0) < 0) {
+ RTE_LOG(ERR, VHOST_PORT, "Failed to unconfigure DMA in
vhost.\n");
+ rte_exit(EXIT_FAILURE, "Cannot use given DMA device\n");
+ }
+ }
+
/* clean up the EAL */
rte_eal_cleanup();
--
2.17.1
Re: [RFC 1/2] vhost: add ingress API for port mirroring datapath
On Sun, 14 Aug 2022 12:49:19 + Cheng Jiang wrote: > From: Wenwu Ma > > Similar to the port mirroring function on the switch or router, this > patch also implements an ingress function on the Vhost lib. When > data is sent to a front-end, it will also send the data to its mirror > front-end. > > Signed-off-by: Cheng Jiang > Signed-off-by: Wenwu Ma We already have rte_flow, packet capture, and rx/tx callbacks. This seems like re-invention.
[PATCH] net/vhost: support asynchronous data path
Vhost asynchronous data-path offloads packet copy from the CPU
to the DMA engine. As a result, large packet copy can be accelerated
by the DMA engine, and vhost can free CPU cycles for higher level
functions.
In this patch, we enable asynchronous data-path for vhostpmd.
Asynchronous data path is enabled per tx/rx queue, and users need
to specify the DMA device used by the tx/rx queue. Each tx/rx queue
only supports to use one DMA device, but one DMA device can be shared
among multiple tx/rx queues of different vhostpmd ports.
Two PMD parameters are added:
- dmas: specify the used DMA device for a tx/rx queue
(Default: no queues enable asynchronous data path)
- dma-ring-size: DMA ring size.
(Default: 2048).
Here is an example:
--vdev
'eth_vhost0,iface=./s0,dmas=[txq0@:00.01.0;rxq0@:00.01.1],dma-ring-size=4096'
Signed-off-by: Jiayu Hu
Signed-off-by: Yuan Wang
Signed-off-by: Wenwu Ma
---
drivers/net/vhost/meson.build | 1 +
drivers/net/vhost/rte_eth_vhost.c | 488 --
drivers/net/vhost/rte_eth_vhost.h | 14 +
3 files changed, 470 insertions(+), 33 deletions(-)
diff --git a/drivers/net/vhost/meson.build b/drivers/net/vhost/meson.build
index f481a3a4b8..22a0ab3a58 100644
--- a/drivers/net/vhost/meson.build
+++ b/drivers/net/vhost/meson.build
@@ -9,4 +9,5 @@ endif
deps += 'vhost'
sources = files('rte_eth_vhost.c')
+testpmd_sources = files('vhost_testpmd.c')
headers = files('rte_eth_vhost.h')
diff --git a/drivers/net/vhost/rte_eth_vhost.c
b/drivers/net/vhost/rte_eth_vhost.c
index 7e512d94bf..361e5d66c6 100644
--- a/drivers/net/vhost/rte_eth_vhost.c
+++ b/drivers/net/vhost/rte_eth_vhost.c
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
#include "rte_eth_vhost.h"
@@ -36,8 +38,13 @@ enum {VIRTIO_RXQ, VIRTIO_TXQ, VIRTIO_QNUM};
#define ETH_VHOST_LINEAR_BUF "linear-buffer"
#define ETH_VHOST_EXT_BUF "ext-buffer"
#define ETH_VHOST_LEGACY_OL_FLAGS "legacy-ol-flags"
+#define ETH_VHOST_DMA_ARG "dmas"
+#define ETH_VHOST_DMA_RING_SIZE"dma-ring-size"
#define VHOST_MAX_PKT_BURST 32
+#define INVALID_DMA_ID -1
+#define DEFAULT_DMA_RING_SIZE 2048
+
static const char *valid_arguments[] = {
ETH_VHOST_IFACE_ARG,
ETH_VHOST_QUEUES_ARG,
@@ -48,6 +55,8 @@ static const char *valid_arguments[] = {
ETH_VHOST_LINEAR_BUF,
ETH_VHOST_EXT_BUF,
ETH_VHOST_LEGACY_OL_FLAGS,
+ ETH_VHOST_DMA_ARG,
+ ETH_VHOST_DMA_RING_SIZE,
NULL
};
@@ -79,8 +88,39 @@ struct vhost_queue {
struct vhost_stats stats;
int intr_enable;
rte_spinlock_t intr_lock;
+
+ /* Flag of enabling async data path */
+ bool async_register;
+ /* DMA device ID */
+ int16_t dma_id;
+ /**
+* For a Rx queue, "txq" points to its peer Tx queue.
+* For a Tx queue, "txq" is never used.
+*/
+ struct vhost_queue *txq;
+ /* Array to keep DMA completed packets */
+ struct rte_mbuf *cmpl_pkts[VHOST_MAX_PKT_BURST];
};
+struct dma_input_info {
+ int16_t dmas[RTE_MAX_QUEUES_PER_PORT * 2];
+ uint16_t dma_ring_size;
+};
+
+static int16_t configured_dmas[RTE_DMADEV_DEFAULT_MAX];
+static int dma_count;
+
+/**
+ * By default, its Rx path to call rte_vhost_poll_enqueue_completed() for
enqueue operations.
+ * However, Rx function is never been called in testpmd "txonly" mode, thus
causing virtio
+ * cannot receive DMA completed packets. To make txonly mode work correctly,
we provide a
+ * command in testpmd to call rte_vhost_poll_enqueue_completed() in Tx path.
+ *
+ * When set async_tx_poll_completed to true, Tx path calls
rte_vhost_poll_enqueue_completed();
+ * otherwise, Rx path calls it.
+ */
+bool async_tx_poll_completed;
+
struct pmd_internal {
rte_atomic32_t dev_attached;
char *iface_name;
@@ -93,6 +133,10 @@ struct pmd_internal {
bool vlan_strip;
bool rx_sw_csum;
bool tx_sw_csum;
+ struct {
+ int16_t dma_id;
+ bool async_register;
+ } queue_dmas[RTE_MAX_QUEUES_PER_PORT * 2];
};
struct internal_list {
@@ -123,6 +167,17 @@ struct rte_vhost_vring_state {
static struct rte_vhost_vring_state *vring_states[RTE_MAX_ETHPORTS];
+static bool
+dma_is_configured(int16_t dma_id)
+{
+ int i;
+
+ for (i = 0; i < dma_count; i++)
+ if (configured_dmas[i] == dma_id)
+ return true;
+ return false;
+}
+
static int
vhost_dev_xstats_reset(struct rte_eth_dev *dev)
{
@@ -395,6 +450,17 @@ vhost_dev_rx_sw_csum(struct rte_mbuf *mbuf)
mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
}
+static inline void
+vhost_tx_free_completed(uint16_t vid, uint16_t virtqueue_id, int16_t dma_id,
+ struct rte_mbuf **pkts, uint16_t count)
+{
+ uint16_t i, ret;
+
+ ret = rte_vhost_poll_enqueue_completed(vid, virtqueue_id,
[PATCH 0/3] security: support MACsec
Added support for MACsec in rte_security for offloading MACsec Protocol operation to inline NIC device or a crypto device. To support MACsec we cannot just make one security session and send with the packet to process it. MACsec specifications suggest, it can have 3 different entities - SECY Entity, SC(secure channel) and SA(security association). And same SA can be used by multiple SCs and similarly many SECY can have same SCs. Hence, in order to support this many to one relationships between all entities, 2 new APIs are created - rte_security_macsec_sc_create and rte_security_sa_create. Flow of execution of the APIs would be as - rte_security_macsec_sa_create - rte_security_macsec_sc_create - rte_security_session_create(for secy) And in case of inline protocol processing rte_flow can be created with rte_security action similar to IPsec flows except that the flow item will be MACsec instead of IPsec. A new flow item is added for MACsec header and a set of events are added to specify the errors occurred during inline protocol processing. New APIs are also created for getting SC and SA stats. Akhil Goyal (3): net: add MACsec header security: support MACsec ethdev: add MACsec flow item doc/api/doxy-api-index.md | 3 +- doc/guides/prog_guide/rte_security.rst | 107 +++- lib/ethdev/rte_ethdev.h| 55 lib/ethdev/rte_flow.h | 18 ++ lib/net/meson.build| 1 + lib/net/rte_macsec.h | 56 lib/security/rte_security.c| 86 ++ lib/security/rte_security.h| 362 - lib/security/rte_security_driver.h | 86 ++ lib/security/version.map | 6 + 10 files changed, 766 insertions(+), 14 deletions(-) create mode 100644 lib/net/rte_macsec.h -- 2.25.1
[PATCH 1/3] net: add MACsec header
Added MACsec protocol header to be used for supporting
MACsec protocol offload in hardware or directly in the application.
Signed-off-by: Akhil Goyal
---
doc/api/doxy-api-index.md | 3 ++-
lib/net/meson.build | 1 +
lib/net/rte_macsec.h | 56 +++
3 files changed, 59 insertions(+), 1 deletion(-)
create mode 100644 lib/net/rte_macsec.h
diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md
index 186a258be4..99e49340d3 100644
--- a/doc/api/doxy-api-index.md
+++ b/doc/api/doxy-api-index.md
@@ -126,7 +126,8 @@ The public API headers are grouped by topics:
[Geneve](@ref rte_geneve.h),
[eCPRI](@ref rte_ecpri.h),
[L2TPv2](@ref rte_l2tpv2.h),
- [PPP](@ref rte_ppp.h)
+ [PPP](@ref rte_ppp.h),
+ [MACsec](@ref rte_macsec.h)
- **QoS**:
[metering](@ref rte_meter.h),
diff --git a/lib/net/meson.build b/lib/net/meson.build
index e899846578..3e63abaca8 100644
--- a/lib/net/meson.build
+++ b/lib/net/meson.build
@@ -21,6 +21,7 @@ headers = files(
'rte_geneve.h',
'rte_l2tpv2.h',
'rte_ppp.h',
+'rte_macsec.h',
)
sources = files(
diff --git a/lib/net/rte_macsec.h b/lib/net/rte_macsec.h
new file mode 100644
index 00..f1b59253f6
--- /dev/null
+++ b/lib/net/rte_macsec.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#ifndef _RTE_MACSEC_H_
+#define _RTE_MACSEC_H_
+
+/**
+ * @file
+ *
+ * MACsec-related defines
+ */
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* SecTAG length = macsec ether header without the optional SCI */
+#define RTE_MACSEC_TAG_LEN 6
+#define RTE_MACSEC_SCI_LEN 8
+
+#define RTE_MACSEC_TCI_VERSION 0x80 /**< Version mask for MACsec. Should be 0.
*/
+#define RTE_MACSEC_TCI_ES 0x40 /**< End station - SCI is not valid */
+#define RTE_MACSEC_TCI_SC 0x20 /**< SCI present */
+#define RTE_MACSEC_TCI_SCB 0x10 /**< Secure channel support EPON single
copy broadcast */
+#define RTE_MACSEC_TCI_E 0x08 /**< User data is encrypted */
+#define RTE_MACSEC_TCI_C 0x04 /**< User data was changed (because of
encryption) */
+#define RTE_MACSEC_AN_MASK 0x03 /**< Association number mask in tci_an */
+#define RTE_MACSEC_NUM_AN 4/**< 2 bits for the association number */
+#define RTE_MACSEC_SALT_LEN12 /**< Salt length for MACsec SA */
+
+/**
+ * MACsec Header
+ */
+struct rte_macsec_hdr {
+ /* SecTAG */
+ uint8_t tci_an;/**< Tag control information and Association
number of SC */
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+ uint8_t short_length : 6; /**< Short Length */
+ uint8_t unused : 2;
+#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+ uint8_t unused : 2;
+ uint8_t short_length : 6;
+#endif
+ rte_be32_t packet_number; /**< Packet number to support replay
protection */
+ uint8_t secure_channel_id[8]; /* optional */
+} __rte_packed;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MACSEC_H_ */
--
2.25.1
[PATCH 2/3] security: support MACsec
Added support for MACsec in rte_security for offloading
MACsec Protocol operation to inline NIC device or a crypto device.
To support MACsec we cannot just make one security session and
send with the packet to process it. MACsec specifications suggest,
it has 3 different entities - SECY Entity, SC(secure channel) and
SA(security association). And same SA can be used by multiple SCs and
similarly many SECY can have same SCs. Hence, in order to support this
many to one relationships between all entities, 2 new APIs are created -
rte_security_macsec_sc_create and rte_security_macsec_sa_create.
Flow of execution of the APIs would be as
- rte_security_macsec_sa_create
- rte_security_macsec_sc_create
- rte_security_session_create(for secy)
And in case of inline protocol processing rte_flow can be created with
rte_security action. A new flow item will be added for MACsec header.
New APIs are also created for getting SC and SA stats.
Signed-off-by: Akhil Goyal
---
doc/guides/prog_guide/rte_security.rst | 107 +++-
lib/security/rte_security.c| 86 ++
lib/security/rte_security.h| 362 -
lib/security/rte_security_driver.h | 86 ++
lib/security/version.map | 6 +
5 files changed, 634 insertions(+), 13 deletions(-)
diff --git a/doc/guides/prog_guide/rte_security.rst
b/doc/guides/prog_guide/rte_security.rst
index 72ca0bd330..1af4d60c75 100644
--- a/doc/guides/prog_guide/rte_security.rst
+++ b/doc/guides/prog_guide/rte_security.rst
@@ -345,6 +345,55 @@ The CRC is Ethernet CRC-32 as specified in
Ethernet/[ISO/IEC 8802-3].
* Other DOCSIS protocol functionality such as Header Checksum (HCS)
calculation may be added in the future.
+MACSEC Protocol
+~~~
+
+Media Access Control security (MACsec) provides point-to-point security on
Ethernet
+links and is defined by IEEE standard 802.1AE. MACsec secures an Ethernet link
for
+almost all traffic, including frames from the Link Layer Discovery Protocol
(LLDP),
+Link Aggregation Control Protocol (LACP), Dynamic Host Configuration Protocol
(DHCP),
+Address Resolution Protocol (ARP), and other protocols that are not typically
secured
+on an Ethernet link because of limitations with other security solutions.
+
+.. code-block:: c
+
+ ReceiveTransmit
+ ---
+
+ Ethernet frame Ethernet frame
+ from network towards
network
+| ^
+~ |
+| ~
+V |
++---+ +--+
+-+
+| Secure frame verify | | Cipher Suite(SA) | | Secure Frame
Generation |
+
+---+<-+--+->+-+
+| SecTAG + ICV remove | | SECY | SC | | SecTAG + ICV
Added |
++---+---+ +--+
+-+
+| ^
+| |
+V |
+Packet to Core/App Packet from
core/App
+
+
+
+To configure MACsec on an inline NIC device or a lookaside crypto device, a
security
+association(SA) and a secure channel(SC) are created before creating
rte_security
+session.
+
+SA is created using API ``rte_security_macsec_sa_create`` which allows setting
+SA keys, salt, SSCI, packet number(PN) into the PMD and the API returns a
handle
+which can be used to map it with a secure channel using the API
+``rte_security_macsec_sc_create``. Same SAs can be used for multiple SCs.
+The Rx SC will need a set of 4 SAs for each of the association numbers(AN).
+For Tx SC a single SA is set which will be used by hardware to process the
packet.
+
+The API ``rte_security_macsec_sc_create`` returns a handle for SC and this
handle
+is set in ``rte_security_macsec_xform`` to create a MACsec session using
+``rte_security_session_create``.
+
+
Device Features and Capabilities
-
@@ -517,6 +566,35 @@ protocol.
RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
};
+Below is the example PMD capability for MACsec
+
+.. code-block:: c
+
+static const struct rte_security_capability pmd_security_capabilities[] = {
+{ /* DOCSIS Uplink */
+.action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,
+.protocol = RTE_SECURITY_
[PATCH 3/3] ethdev: add MACsec flow item
A new flow item is defined for MACsec flows which can be
offloaded to an inline device. If the flow matches with
MACsec header, device will process as per the security
session created using rte_security APIs.
If an error comes while MACsec processing in HW, PMD will
notify with the events defined in this patch.
Signed-off-by: Akhil Goyal
---
lib/ethdev/rte_ethdev.h | 55 +
lib/ethdev/rte_flow.h | 18 ++
2 files changed, 73 insertions(+)
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index de9e970d4d..24661b01e9 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -3864,6 +3864,61 @@ rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts,
uint16_t unsent,
int
rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t
free_cnt);
+/**
+ * Subtypes for MACsec offload event(@ref RTE_ETH_EVENT_MACSEC) raised by
+ * Ethernet device.
+ */
+enum rte_eth_macsec_event_subtype {
+ RTE_ETH_MACSEC_SUBEVENT_UNKNOWN,
+ /* subevents of RTE_ETH_MACSEC_EVENT_SECTAG_VAL_ERR sectag validation
events
+* RTE_ETH_MACSEC_EVENT_RX_SECTAG_V_EQ1
+* Validation check: SecTag.TCI.V = 1
+* RTE_ETH_MACSEC_EVENT_RX_SECTAG_E_EQ0_C_EQ1
+* Validation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1
+* RTE_ETH_MACSEC_EVENT_RX_SECTAG_SL_GTE48
+* Validation check: SecTag.SL >= 'd48
+* RTE_ETH_MACSEC_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1
+* Validation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1
+* RTE_ETH_MACSEC_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1
+* Validation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1
+*/
+ RTE_ETH_MACSEC_SUBEVENT_RX_SECTAG_V_EQ1,
+ RTE_ETH_MACSEC_SUBEVENT_RX_SECTAG_E_EQ0_C_EQ1,
+ RTE_ETH_MACSEC_SUBEVENT_RX_SECTAG_SL_GTE48,
+ RTE_ETH_MACSEC_SUBEVENT_RX_SECTAG_ES_EQ1_SC_EQ1,
+ RTE_ETH_MACSEC_SUBEVENT_RX_SECTAG_SC_EQ1_SCB_EQ1,
+};
+
+enum rte_eth_macsec_event_type {
+ RTE_ETH_MACSEC_EVENT_UNKNOWN,
+ RTE_ETH_MACSEC_EVENT_SECTAG_VAL_ERR,
+ RTE_ETH_MACSEC_EVENT_RX_SA_PN_HARD_EXP,
+ RTE_ETH_MACSEC_EVENT_RX_SA_PN_SOFT_EXP,
+ RTE_ETH_MACSEC_EVENT_TX_SA_PN_HARD_EXP,
+ RTE_ETH_MACSEC_EVENT_TX_SA_PN_SOFT_EXP,
+ /* Notifies Invalid SA event */
+ RTE_ETH_MACSEC_EVENT_SA_NOT_VALID,
+};
+
+/**
+ * Descriptor for @ref RTE_ETH_EVENT_MACSEC event. Used by eth dev to send
extra
+ * information of the MACsec offload event.
+ */
+struct rte_eth_event_macsec_desc {
+ enum rte_eth_macsec_event_type type;
+ enum rte_eth_macsec_event_subtype subtype;
+ /**
+* Event specific metadata.
+*
+* For the following events, *userdata* registered
+* with the *rte_security_session* would be returned
+* as metadata,
+*
+* @see struct rte_security_session_conf
+*/
+ uint64_t metadata;
+};
+
/**
* Subtypes for IPsec offload event(@ref RTE_ETH_EVENT_IPSEC) raised by
* eth device.
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index a79f1e7ef0..4114c84a02 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -35,6 +35,7 @@
#include
#include
#include
+#include
#ifdef __cplusplus
extern "C" {
@@ -668,6 +669,13 @@ enum rte_flow_item_type {
* See struct rte_flow_item_gre_opt.
*/
RTE_FLOW_ITEM_TYPE_GRE_OPTION,
+
+ /**
+* Matches MACsec Ethernet Header.
+*
+* See struct rte_flow_item_macsec.
+*/
+ RTE_FLOW_ITEM_TYPE_MACSEC,
};
/**
@@ -1214,6 +1222,16 @@ struct rte_flow_item_gre_opt {
struct rte_gre_hdr_opt_sequence sequence;
};
+/**
+ * RTE_FLOW_ITEM_TYPE_MACSEC.
+ *
+ * Matches MACsec header.
+ */
+struct rte_flow_item_macsec {
+ struct rte_macsec_hdr macsec_hdr;
+};
+
+
/**
* RTE_FLOW_ITEM_TYPE_FUZZY
*
--
2.25.1
[PATCH 00/70] ice base code update
Update ice base code to 2022-Aug internal release. Summary: 1. Baseline support for L2TPv2 FDIR/RSS. 2. Refactor DDP module. 3. Support 56G PHY 4. Add GTP/GRE tunnel. 6. Clean code and fix bug 5. update copyright. Qi Zhang (70): net/ice/base: add netlist helper functions net/ice/base: get NVM CSS Header length from the CSS Header net/ice/base: combine functions for VSI promisc net/ice/base: make function names more generic net/ice/base: fix incorrect division during E822 PTP init net/ice/base: added auto drop blocking packets functionality net/ice/base: fix 100M speed net/ice/base: support VXLAN and GRE for RSS net/ice/base: fix DSCP PFC TLV creation net/ice/base: complete the health status codes net/ice/base: explicitly name E822 HW-dependent functions net/ice/base: move code block net/ice/base: add PHY 56G destination address net/ice/base: add 56G PHY register definitions net/ice/base: implement 56G PHY access functions net/ice/base: implement 56G PHY setup functions net/ice/base: work around missing PTP caps net/ice/base: enable calling of ETH56G functions net/ice/base: fix PHY type 10G SFI C2C to media type mapping net/ice/base: refactor DDP code net/ice/base: add E822 generic PCI device ID net/ice/base: support double VLAN rules net/ice/base: report NVM version numbers on mismatch net/ice/base: create duplicate detection for ACL rules net/ice/base: fix incorrect function descriptions for parser net/ice/base: fix endian format net/ice/base: convert IO expander handle to u16 net/ice/base: convert array of u8 to bitmap net/ice/base: fix array overflow in add switch recipe code net/ice/base: fix bit finding range over ptype bitmap net/ice/base: move function to internal net/ice/base: change PHY/QUAD/ports definitions net/ice/base: add AQ command to config node attribute net/ice/base: fix null pointer dereference during net/ice/base: refine default VSI config net/ice/base: ice-shared: fix add mac rule net/ice/base: support Tx topo config net/ice/base: adjust the VSI/Aggregator layers net/ice/base: add data typecasting to match sizes net/ice/base: add helper function to check if device is E823 net/ice/base: add low latency Tx timestamp read net/ice/base: fix double VLAN error in promisc mode net/ice/base: move functions net/ice/base: complete support for Tx balancing net/ice/base: update definitions for AQ internal debug dump net/ice/base: update macros of L2TPv2 ptype value net/ice/base: refine header file include net/ice/base: ignore already exist error net/ice/base: clean up with no lookups net/ice/base: add support for Auto FEC with FEC disabled net/ice/base: update PHY type high max index net/ice/base: clean the main timer command register net/ice/base: add support for custom WPC and LGB NICs net/ice/base: add generic MAC with 3K signature segment net/ice/base: enable RSS support for L2TPv2 session ID net/ice/base: enable FDIR support for L2TPv2 net/ice/base: add GRE Tap tunnel type net/ice/base: fix wrong inputset of GTPoGRE packet net/ice/base: add unload flag for control queue shutdown net/ice/base: update comment for overloaded GCO bit net/ice/base: complete pending LLDP MIB net/ice/base: add function to parse DCBX config net/ice/base: handle default VSI lookup type net/ice/base: convert 1588 structs to use bitfields net/ice/base: remove unnecessary fields net/ice/base: add GTP tunnel net/ice/base: check for PTP HW lock more frequently net/ice/base: expose API for move sched element net/ice/base: couple code clean net/ice/base: update copyright drivers/net/ice/base/README |4 +- drivers/net/ice/base/ice_acl.c |2 +- drivers/net/ice/base/ice_acl.h |2 +- drivers/net/ice/base/ice_acl_ctrl.c | 36 +- drivers/net/ice/base/ice_adminq_cmd.h| 175 +- drivers/net/ice/base/ice_alloc.h |2 +- drivers/net/ice/base/ice_bitops.h|7 +- drivers/net/ice/base/ice_bst_tcam.c |8 +- drivers/net/ice/base/ice_bst_tcam.h |2 +- drivers/net/ice/base/ice_cgu_regs.h |2 +- drivers/net/ice/base/ice_common.c| 371 ++- drivers/net/ice/base/ice_common.h| 22 +- drivers/net/ice/base/ice_controlq.c | 33 +- drivers/net/ice/base/ice_controlq.h |2 +- drivers/net/ice/base/ice_dcb.c | 52 +- drivers/net/ice/base/ice_dcb.h |4 +- drivers/net/ice/base/ice_ddp.c | 2475 drivers/net/ice/base/ice_ddp.h | 466 drivers/net/ice/base/ice_defs.h | 49 + drivers/net/ice/base/ice_devids.h|9 +- drivers/net/ice/base/ice_fdir.c | 812 ++- drivers/net/ice/base/ice_fdir.h | 28 +- drivers/net/ice/base/ice_flex_pipe.c | 2541 +++-- drivers/net/ice/base/ice_flex_pipe.h | 66 +- drivers/net/ice/base/ice_flex_type.h |
[PATCH 01/70] net/ice/base: add netlist helper functions
Add new functions to check in netlist if HW has:
- Recovered Clock device,
- Clock Generation Unit,
- Clock Multiplexer,
- GPS generic device.
Signed-off-by: Michal Michalik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 54 +++
drivers/net/ice/base/ice_common.c | 130 +-
drivers/net/ice/base/ice_common.h | 10 ++
drivers/net/ice/base/ice_ptp_hw.c | 37 +---
drivers/net/ice/base/ice_ptp_hw.h | 1 +
5 files changed, 195 insertions(+), 37 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 253b971dfd..a3add411b8 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1635,6 +1635,7 @@ struct ice_aqc_link_topo_params {
#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS11
#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
@@ -1672,9 +1673,61 @@ struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48
u8 rsvd[9];
};
+/* Get Link Topology Pin (direct, 0x06E1) */
+struct ice_aqc_get_link_topo_pin {
+ struct ice_aqc_link_topo_addr addr;
+ u8 input_io_params;
+#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0
+#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \
+ (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S)
+#define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1
+#define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N2
+#define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N3
+#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4
+#define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5
+#define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6
+#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10
+#define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP11
+/* 12 repeats intentionally due to two different uses depending on context */
+#define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12
+#define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED13
+#define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \
+ (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO 3
+/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
+ u8 output_io_params;
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \
+ (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S)
+/* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \
+ (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
+/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
+ u8 output_io_flags;
+#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0
+#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \
+ (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S)
+#define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3
+#define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \
+ (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S)
+#define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5)
+#define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6)
+#define ICE_AQC_LINK_TOPO_OUTPUT_DRIVENBIT(7)
+ u8 rsvd[7];
+};
+
/* Read/Write I2C (direct, 0x06E2/0x06E3) */
struct ice_aqc_i2c {
struct ice_aqc_link_topo_addr topo_addr;
@@ -2936,6 +2989,7 @@ struct ice_aq_desc {
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;
+ struct ice_aqc_get_link_topo_pin get_link_topo_pin;
struct ice_aqc_set_health_status_config
set_health_status_config;
struct ice_aqc_get_supported_health_status_codes
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index db87bacd97..edc24030ec 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -396,37 +396,103 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
}
/**
- * ice_aq_get_link_topo_handle - get link topology node return status
- * @pi: port information s
[PATCH 02/70] net/ice/base: get NVM CSS Header length from the CSS Header
The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To
support changes in CSS Header length, calculate the CSS Header
length from the NVM CSS Header length field plus the Authentication
Header length.
Signed-off-by: Paul Greenwalt
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_nvm.c | 61 +
drivers/net/ice/base/ice_type.h | 12 +++
2 files changed, 59 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 7860006206..ad2496e873 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -350,6 +350,42 @@ ice_read_nvm_module(struct ice_hw *hw, enum
ice_bank_select bank, u32 offset, u1
return status;
}
+/**
+ * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
+ * @hw: pointer to the HW struct
+ * @bank: whether to read from the active or inactive flash bank
+ * @hdr_len: storage for header length in words
+ *
+ * Read the CSS header length from the NVM CSS header and add the
Authentication
+ * header size, and then convert to words.
+ */
+static enum ice_status
+ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
+ u32 *hdr_len)
+{
+ u16 hdr_len_l, hdr_len_h;
+ enum ice_status status;
+ u32 hdr_len_dword;
+
+ status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
+&hdr_len_l);
+ if (status)
+ return status;
+
+ status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
+&hdr_len_h);
+ if (status)
+ return status;
+
+ /* CSS header length is in DWORD, so convert to words and add
+* authentication header size
+*/
+ hdr_len_dword = hdr_len_h << 16 | hdr_len_l;
+ *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
* @hw: pointer to the HW structure
@@ -363,7 +399,16 @@ ice_read_nvm_module(struct ice_hw *hw, enum
ice_bank_select bank, u32 offset, u1
static enum ice_status
ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset,
u16 *data)
{
- return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET +
offset, data);
+ enum ice_status status;
+ u32 hdr_len;
+
+ status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
+ if (status)
+ return status;
+
+ hdr_len = ROUND_UP(hdr_len, 32);
+
+ return ice_read_nvm_module(hw, bank, hdr_len + offset, data);
}
/**
@@ -633,22 +678,26 @@ enum ice_status ice_get_inactive_nvm_ver(struct ice_hw
*hw, struct ice_nvm_info
*/
static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum
ice_bank_select bank, u32 *srev)
{
+ u32 orom_size_word = hw->flash.banks.orom_size / 2;
enum ice_status status;
u16 srev_l, srev_h;
u32 css_start;
+ u32 hdr_len;
- if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
+ status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
+ if (status)
+ return status;
+
+ if (orom_size_word < hdr_len) {
ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
hw->flash.banks.orom_size);
return ICE_ERR_CFG;
}
/* calculate how far into the Option ROM the CSS header starts. Note
-* that ice_read_orom_module takes a word offset so we need to
-* divide by 2 here.
+* that ice_read_orom_module takes a word offset
*/
- css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) /
2;
-
+ css_start = orom_size_word - hdr_len;
status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L,
&srev_l);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index d81984633a..d4d0cab089 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1419,17 +1419,13 @@ struct ice_aq_get_set_rss_lut_params {
#define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
/* CSS Header words */
+#define ICE_NVM_CSS_HDR_LEN_L 0x02
+#define ICE_NVM_CSS_HDR_LEN_H 0x03
#define ICE_NVM_CSS_SREV_L 0x14
#define ICE_NVM_CSS_SREV_H 0x15
-/* Length of CSS header section in words */
-#define ICE_CSS_HEADER_LENGTH 330
-
-/* Offset of Shadow RAM copy in the NVM bank area. */
-#define ICE_NVM_SR_COPY_WORD_OFFSETROUND_UP(ICE_CSS_HEADER_LENGTH,
32)
-
-/* Size in bytes of Option ROM trailer */
-#define ICE_NVM_OROM_TRAILER_LENGTH(2 * ICE_CSS_HEADER_LENGTH)
+/* Length of Authentication header section in words */
+#define ICE_NVM_AUTH
[PATCH 03/70] net/ice/base: combine functions for VSI promisc
Remove ice_get_vsi_vlan_promisc,
cause of similar implementation as ice_get_vsi_promisc,
which will now handle the use case of ice_get_vsi_vlan_promisc.
Signed-off-by: Wiktor Pilarczyk
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 58 ++-
1 file changed, 11 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index c0df3a1815..513623a0a4 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5825,22 +5825,25 @@ static u8 ice_determine_promisc_mask(struct
ice_fltr_info *fi)
* @promisc_mask: pointer to mask to be filled in
* @vid: VLAN ID of promisc VLAN VSI
* @sw: pointer to switch info struct for which function add rule
+ * @lkup: switch rule filter lookup type
*/
static enum ice_status
_ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
-u16 *vid, struct ice_switch_info *sw)
+u16 *vid, struct ice_switch_info *sw,
+enum ice_sw_lkup_type lkup)
{
struct ice_fltr_mgmt_list_entry *itr;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
- if (!ice_is_vsi_valid(hw, vsi_handle))
+ if (!ice_is_vsi_valid(hw, vsi_handle) ||
+ (lkup != ICE_SW_LKUP_PROMISC && lkup != ICE_SW_LKUP_PROMISC_VLAN))
return ICE_ERR_PARAM;
*vid = 0;
*promisc_mask = 0;
- rule_head = &sw->recp_list[ICE_SW_LKUP_PROMISC].filt_rules;
- rule_lock = &sw->recp_list[ICE_SW_LKUP_PROMISC].filt_rule_lock;
+ rule_head = &sw->recp_list[lkup].filt_rules;
+ rule_lock = &sw->recp_list[lkup].filt_rule_lock;
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
@@ -5870,47 +5873,7 @@ ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
u8 *promisc_mask,
u16 *vid)
{
return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
- vid, hw->switch_info);
-}
-
-/**
- * _ice_get_vsi_vlan_promisc - get VLAN promiscuous mode of given VSI
- * @hw: pointer to the hardware structure
- * @vsi_handle: VSI handle to retrieve info from
- * @promisc_mask: pointer to mask to be filled in
- * @vid: VLAN ID of promisc VLAN VSI
- * @sw: pointer to switch info struct for which function add rule
- */
-static enum ice_status
-_ice_get_vsi_vlan_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
- u16 *vid, struct ice_switch_info *sw)
-{
- struct ice_fltr_mgmt_list_entry *itr;
- struct LIST_HEAD_TYPE *rule_head;
- struct ice_lock *rule_lock; /* Lock to protect filter rule list */
-
- if (!ice_is_vsi_valid(hw, vsi_handle))
- return ICE_ERR_PARAM;
-
- *vid = 0;
- *promisc_mask = 0;
- rule_head = &sw->recp_list[ICE_SW_LKUP_PROMISC_VLAN].filt_rules;
- rule_lock = &sw->recp_list[ICE_SW_LKUP_PROMISC_VLAN].filt_rule_lock;
-
- ice_acquire_lock(rule_lock);
- LIST_FOR_EACH_ENTRY(itr, rule_head, ice_fltr_mgmt_list_entry,
- list_entry) {
- /* Continue if this filter doesn't apply to this VSI or the
-* VSI ID is not in the VSI map for this filter
-*/
- if (!ice_vsi_uses_fltr(itr, vsi_handle))
- continue;
-
- *promisc_mask |= ice_determine_promisc_mask(&itr->fltr_info);
- }
- ice_release_lock(rule_lock);
-
- return ICE_SUCCESS;
+ vid, hw->switch_info, ICE_SW_LKUP_PROMISC);
}
/**
@@ -5924,8 +5887,9 @@ enum ice_status
ice_get_vsi_vlan_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
u16 *vid)
{
- return _ice_get_vsi_vlan_promisc(hw, vsi_handle, promisc_mask,
-vid, hw->switch_info);
+ return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
+ vid, hw->switch_info,
+ ICE_SW_LKUP_PROMISC_VLAN);
}
/**
--
2.31.1
[PATCH 04/70] net/ice/base: make function names more generic
Previously "e810t" was part of few function names.
In the future it will require to add similar functions
for different NIC types.
Make "NIC type" a suffix of the function name.
Signed-off-by: Arkadiusz Kubalewski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 12 ++--
drivers/net/ice/base/ice_ptp_hw.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 5b366c95c5..632a3f5bae 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -3161,7 +3161,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw)
}
/**
- * ice_read_e810t_pca9575_reg
+ * ice_read_pca9575_reg_e810t
* @hw: pointer to the hw struct
* @offset: GPIO controller register offset
* @data: pointer to data to be read from the GPIO controller
@@ -3169,7 +3169,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw)
* Read the register from the GPIO controller
*/
enum ice_status
-ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
+ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
{
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
@@ -3191,7 +3191,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset,
u8 *data)
}
/**
- * ice_write_e810t_pca9575_reg
+ * ice_write_pca9575_reg_e810t
* @hw: pointer to the hw struct
* @offset: GPIO controller register offset
* @data: data to be written to the GPIO controller
@@ -3199,7 +3199,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset,
u8 *data)
* Write the data to the GPIO controller register
*/
enum ice_status
-ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data)
+ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data)
{
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
@@ -3283,12 +3283,12 @@ enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw
*hw, u8 data)
}
/**
- * ice_e810t_is_pca9575_present
+ * ice_is_pca9575_present
* @hw: pointer to the hw struct
*
* Check if the SW IO expander is present in the netlist
*/
-bool ice_e810t_is_pca9575_present(struct ice_hw *hw)
+bool ice_is_pca9575_present(struct ice_hw *hw)
{
enum ice_status status;
__le16 handle = 0;
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 4f349593aa..d27815fd94 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -224,12 +224,12 @@ enum ice_status ice_phy_exit_bypass_e822(struct ice_hw
*hw, u8 port);
bool ice_is_gps_present_e810t(struct ice_hw *hw);
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
enum ice_status
-ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
+ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
enum ice_status
-ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data);
+ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data);
enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
-bool ice_e810t_is_pca9575_present(struct ice_hw *hw);
+bool ice_is_pca9575_present(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
--
2.31.1
[PATCH 05/70] net/ice/base: fix incorrect division during E822 PTP init
When initializing the device hardware for PTP, the E822 devices
requirea number of values to be calculated and programmed to
hardware.These values are calculated using unsigned 64-bit
division.
The DIV_64BIT macro currently translates into a specific Linux
functionthat triggers a *signed* division. This produces incorrect
results when operating on a dividend larger than an s64. The
division calculation effectively overflows and results in totally
unexpected behavior.
In this case, the UIX value for 10Gb/40Gb link speeds are calculated
incorrectly. This ultimately cascades into a failure of the Tx
timestamps. Specifically, the reported Tx timestamps become wildly
inaccurate and not representing nominal time.
The root cause of this bug is the assumption that DIV_64BIT can
correctly handle both signed and unsigned division. In fact the
entire reason we need this is because the Linux kernel compilation
target does not provide native 64 bit division ops, and requires
explicit use of kernel functions which explicitly do either signed
or unsigned division.
To correctly solve this, introduce new functions, DIV_U64 and
DIV_S64 which are specifically intended for signed or unsigned
division. To help catch issues, use static inline functions so
that we get strict type checking.
Fixes: 97f4f78bbd9f ("net/ice/base: add functions for device clock control")
Cc: sta...@dpdk.org
Signed-off-by: Jacob Keller
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 56 +++
drivers/net/ice/base/ice_sched.c | 24 ++---
drivers/net/ice/base/ice_type.h | 30 +++--
3 files changed, 68 insertions(+), 42 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 632a3f5bae..76119364e4 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw
*hw, u8 port)
#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
/* Program the 10Gb/40Gb conversion ratio */
- uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
+ uix = DIV_U64(tu_per_sec * LINE_UI_10G_40G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
uix);
@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw
*hw, u8 port)
}
/* Program the 25Gb/100Gb conversion ratio */
- uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
+ uix = DIV_U64(tu_per_sec * LINE_UI_25G_100G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
uix);
@@ -1727,8 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_par_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_par_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].tx_par_clk);
else
phy_tus = 0;
@@ -1739,8 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].rx_par_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].rx_par_clk);
else
phy_tus = 0;
@@ -1751,8 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_pcs_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].tx_pcs_clk);
else
phy_tus = 0;
@@ -1763,8 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].rx_pcs_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].rx_pcs_clk);
else
phy_tus = 0;
@@ -1775,8 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_desk_rsgb_par);
+ phy_tus = DIV_U64(tu_per_sec,
+
[PATCH 06/70] net/ice/base: added auto drop blocking packets functionality
Extended ice_aq_set_mac_cfg()function to add support for
auto drop blocking packets.
Signed-off-by: Mateusz Rusinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 22 --
drivers/net/ice/base/ice_common.h | 5 -
drivers/net/ice/base/ice_type.h | 6 ++
drivers/net/ice/ice_ethdev.c | 2 +-
4 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index edc24030ec..f9640d9403 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -788,12 +788,14 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* ice_aq_set_mac_cfg
* @hw: pointer to the HW struct
* @max_frame_size: Maximum Frame Size to be supported
+ * @auto_drop: Tell HW to drop packets if TC queue is blocked
* @cd: pointer to command details structure or NULL
*
* Set MAC configuration (0x0603)
*/
enum ice_status
-ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop,
+ struct ice_sq_cd *cd)
{
struct ice_aqc_set_mac_cfg *cmd;
struct ice_aq_desc desc;
@@ -807,6 +809,8 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size,
struct ice_sq_cd *cd)
cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
+ if (ice_is_fw_auto_drop_supported(hw) && auto_drop)
+ cmd->drop_opts |= ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS;
ice_fill_tx_timer_and_fc_thresh(hw, cmd);
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
@@ -1106,7 +1110,8 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
goto err_unroll_fltr_mgmt_struct;
/* enable jumbo frame support at MAC level */
- status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
+ status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, false,
+ NULL);
if (status)
goto err_unroll_fltr_mgmt_struct;
@@ -5921,3 +5926,16 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
}
return false;
}
+/**
+ * ice_is_fw_auto_drop_supported
+ * @hw: pointer to the hardware structure
+ *
+ * Checks if the firmware supports auto drop feature
+ */
+bool ice_is_fw_auto_drop_supported(struct ice_hw *hw)
+{
+ if (hw->api_maj_ver >= ICE_FW_API_AUTO_DROP_MAJ &&
+ hw->api_min_ver >= ICE_FW_API_AUTO_DROP_MIN)
+ return true;
+ return false;
+}
diff --git a/drivers/net/ice/base/ice_common.h
b/drivers/net/ice/base/ice_common.h
index 1044a3088e..1051cc1176 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -191,7 +191,8 @@ enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);
enum ice_status
-ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd
*cd);
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop,
+ struct ice_sq_cd *cd);
enum ice_status
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
struct ice_link_status *link, struct ice_sq_cd *cd);
@@ -289,4 +290,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct
ice_aqc_link_topo_addr topo_addr,
u16 bus_addr, __le16 addr, u8 params, u8 *data,
struct ice_sq_cd *cd);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
+/* AQ API version for FW auto drop reports */
+bool ice_is_fw_auto_drop_supported(struct ice_hw *hw);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 3da3de38af..15b12bfc8d 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1539,5 +1539,11 @@ struct ice_aq_get_set_rss_lut_params {
/* AQ API version for report default configuration */
#define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
#define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
+
#define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
+/* AQ API version for FW auto drop reports */
+#define ICE_FW_API_AUTO_DROP_MAJ 1
+#define ICE_FW_API_AUTO_DROP_MIN 4
+
+
#endif /* _ICE_TYPE_H_ */
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 587b01cf23..2e522376e3 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -3662,7 +3662,7 @@ ice_dev_start(struct rte_eth_dev *dev)
ICE_FRAME_SIZE_MAX;
/* Set the max frame size to HW*/
- ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
+ ice_aq_set_mac_cfg(hw, max_frame_size, false, NULL);
if (ad->devargs.pps_out_ena) {
ret = ice_pps_out_cfg(hw, pin_idx, timer);
--
2.31.1
[PATCH 07/70] net/ice/base: fix 100M speed
Couple of 10GBase-T devices don't support advertising 100M
speed. For these devices, ice_is_100m_speed_supported should
return false. Meanwhile add device that supports 100M speed.
Fixes: 486d29fda54c ("net/ice/base: add dedicate MAC type for E810")
Cc: sta...@dpdk.org
Signed-off-by: Anirudh Venkataramanan
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index f9640d9403..e22600c46d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3113,12 +3113,10 @@ ice_aq_set_port_params(struct ice_port_info *pi, u16
bad_frame_vsi,
bool ice_is_100m_speed_supported(struct ice_hw *hw)
{
switch (hw->device_id) {
- case ICE_DEV_ID_E822C_10G_BASE_T:
case ICE_DEV_ID_E822C_SGMII:
- case ICE_DEV_ID_E822L_10G_BASE_T:
case ICE_DEV_ID_E822L_SGMII:
- case ICE_DEV_ID_E823L_10G_BASE_T:
case ICE_DEV_ID_E823L_1GBE:
+ case ICE_DEV_ID_E823C_SGMII:
return true;
default:
return false;
--
2.31.1
[PATCH 08/70] net/ice/base: support VXLAN and GRE for RSS
Add RSS of inner headers for VXLAN tunnel packet.
Add packet types for packets with outer IPv4/IPv6 header
support GRE and VXLAN tunnel packet.
Following rules can use new packet types:
- eth / ipv4(6) / udp / vxlan / ipv4(6)
- eth / ipv4(6) / udp / vxlan / ipv4(6) / tcp
- eth / ipv4(6) / udp / vxlan / ipv4(6) / udp
- eth / ipv4(6) / gre / ipv4(6)
- eth / ipv4(6) / gre / ipv4(6) / tcp
- eth / ipv4(6) / gre / ipv4(6) / udp
Signed-off-by: Jie Wang
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flow.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index d7eecc0d54..bdb584c7f5 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -262,7 +262,7 @@ static const u32 ice_ptypes_macvlan_il[] = {
* does NOT include IPV4 other PTYPEs
*/
static const u32 ice_ptypes_ipv4_ofos[] = {
- 0x1D80, 0x24000800, 0x, 0x,
+ 0x1D80, 0xBFBF7800, 0x01DF, 0x,
0x, 0x0155, 0x, 0x,
0x, 0x000FC000, 0x02A0, 0x0010,
0x1500, 0x, 0x, 0x,
@@ -316,8 +316,8 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
* includes IPV6 other PTYPEs
*/
static const u32 ice_ptypes_ipv6_ofos_all[] = {
- 0x, 0x, 0x7600, 0x1EFDE000,
- 0x, 0x02AA, 0x, 0x,
+ 0x, 0x, 0x7600, 0xFEFDE000,
+ 0x077E, 0x02AA, 0x, 0x,
0x, 0x03F0, 0x7C1F0540, 0x0206,
0xFC002000, 0x003F, 0xBC00, 0x0002FBEF,
0x, 0x, 0x, 0x,
@@ -985,8 +985,9 @@ struct ice_flow_prof_params {
ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \
ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \
ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \
+ ICE_FLOW_SEG_HDR_VXLAN | ICE_FLOW_SEG_HDR_GRE | \
ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \
- ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE)
+ ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP)
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
--
2.31.1
[PATCH 09/70] net/ice/base: fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC. This means that traffic classes 4-7 could not be
enabled for PFC.
Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.
Fixes: 8ea78b169603 ("net/ice/base: support L3 DSCP QoS")
Cc: sta...@dpdk.org
Signed-off-by: Dave Ertman
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_dcb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index cb6c5ba182..3d630757f8 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -1376,7 +1376,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct
ice_dcbx_cfg *dcbcfg)
tlv->ouisubtype = HTONL(ouisubtype);
buf[0] = dcbcfg->pfc.pfccap & 0xF;
- buf[1] = dcbcfg->pfc.pfcena & 0xF;
+ buf[1] = dcbcfg->pfc.pfcena;
}
/**
--
2.31.1
[PATCH 10/70] net/ice/base: complete the health status codes
add definitions for async health status codes.
Signed-off-by: Leszek Zygo
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index a3add411b8..517af4b6ef 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2821,6 +2821,7 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
#define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
+#define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109
#define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
@@ -2842,7 +2843,16 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
+#define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION0x507
+#define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508
#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
+#define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A
+#define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET0x50B
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL0x50C
+#define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002
/* Get Health Status codes (indirect 0xFF21) */
struct ice_aqc_get_supported_health_status_codes {
--
2.31.1
[PATCH 11/70] net/ice/base: explicitly name E822 HW-dependent functions
Add the suffix to E822 HW-dependent function names
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 23 ---
drivers/net/ice/base/ice_ptp_hw.h | 7 ---
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 76119364e4..23d90b127d 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1268,7 +1268,7 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32
target_time)
}
/**
- * ice_ptp_read_port_capture - Read a port's local time capture
+ * ice_ptp_read_port_capture_e822 - Read a port's local time capture
* @hw: pointer to HW struct
* @port: Port number to read
* @tx_ts: on return, the Tx port time capture
@@ -1279,7 +1279,8 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32
target_time)
* Note this has no equivalent for the E810 devices.
*/
enum ice_status
-ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
+ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts,
+ u64 *rx_ts)
{
enum ice_status status;
@@ -1309,7 +1310,7 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64
*tx_ts, u64 *rx_ts)
}
/**
- * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
+ * ice_ptp_one_port_cmd_e822 - Prepare a single PHY port for a timer command
* @hw: pointer to HW struct
* @port: Port to which cmd has to be sent
* @cmd: Command to be sent to the port
@@ -1321,8 +1322,8 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64
*tx_ts, u64 *rx_ts)
* always handles all external PHYs internally.
*/
enum ice_status
-ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
-bool lock_sbq)
+ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq)
{
enum ice_status status;
u32 cmd_val, val;
@@ -1416,7 +1417,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
enum ice_status status;
- status = ice_ptp_one_port_cmd(hw, port, cmd, lock_sbq);
+ status = ice_ptp_one_port_cmd_e822(hw, port, cmd, lock_sbq);
if (status)
return status;
}
@@ -2318,7 +2319,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8
port, u64 *phy_time,
ice_ptp_src_cmd(hw, READ_TIME);
/* Prepare the PHY timer for a READ_TIME capture command */
- status = ice_ptp_one_port_cmd(hw, port, READ_TIME, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, READ_TIME, true);
if (status)
return status;
@@ -2331,7 +2332,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8
port, u64 *phy_time,
*phc_time = (u64)lo << 32 | zo;
/* Read the captured PHY time from the PHY shadow registers */
- status = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
+ status = ice_ptp_read_port_capture_e822(hw, port, &tx_time, &rx_time);
if (status)
return status;
@@ -2388,7 +2389,7 @@ static enum ice_status ice_sync_phy_timer_e822(struct
ice_hw *hw, u8 port)
if (status)
goto err_unlock;
- status = ice_ptp_one_port_cmd(hw, port, ADJ_TIME, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, ADJ_TIME, true);
if (status)
goto err_unlock;
@@ -2513,7 +2514,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool
bypass)
if (status)
return status;
- status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);
if (status)
return status;
@@ -2538,7 +2539,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool
bypass)
if (status)
return status;
- status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index d27815fd94..9cc3436aa8 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -157,10 +157,11 @@ ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port,
s64 time,
enum ice_status
ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval);
enum ice_status
-ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
+ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,
+ u64 *tx_ts, u64 *rx_ts);
enum ice_status
-ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd c
[PATCH 12/70] net/ice/base: move code block
Move some code block to the beginning of ice_ptp_hw.c to align
withkernel driver.
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 997 +++---
1 file changed, 498 insertions(+), 499 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 23d90b127d..22d0774dd7 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -101,6 +101,286 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw)
return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
}
+/**
+ * ice_read_cgu_reg_e822 - Read a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to read
+ * @val: storage for register value read
+ *
+ * Read the contents of a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_rd;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x,
status %d\n",
+ addr, status);
+ return status;
+ }
+
+ *val = cgu_msg.data;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_write_cgu_reg_e822 - Write a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to write
+ * @val: value to write into the register
+ *
+ * Write the specified value to a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_wr;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+ cgu_msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register
0x%04x, status %d\n",
+ addr, status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_clk_freq_str - Convert time_ref_freq to string
+ * @clk_freq: Clock frequency
+ *
+ * Convert the specified TIME_REF clock frequency to a string.
+ */
+static const char *ice_clk_freq_str(u8 clk_freq)
+{
+ switch ((enum ice_time_ref_freq)clk_freq) {
+ case ICE_TIME_REF_FREQ_25_000:
+ return "25 MHz";
+ case ICE_TIME_REF_FREQ_122_880:
+ return "122.88 MHz";
+ case ICE_TIME_REF_FREQ_125_000:
+ return "125 MHz";
+ case ICE_TIME_REF_FREQ_153_600:
+ return "153.6 MHz";
+ case ICE_TIME_REF_FREQ_156_250:
+ return "156.25 MHz";
+ case ICE_TIME_REF_FREQ_245_760:
+ return "245.76 MHz";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_clk_src_str - Convert time_ref_src to string
+ * @clk_src: Clock source
+ *
+ * Convert the specified clock source to its string name.
+ */
+static const char *ice_clk_src_str(u8 clk_src)
+{
+ switch ((enum ice_clk_src)clk_src) {
+ case ICE_CLK_SRC_TCX0:
+ return "TCX0";
+ case ICE_CLK_SRC_TIME_REF:
+ return "TIME_REF";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCX0)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ */
+enum ice_status
+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
+enum ice_clk_src clk_src)
+{
+ union tspll_ro_bwm_lf bwm_lf;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ enum ice_status status;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ ice_warn(hw, "Invalid clock source %u\n", clk_src);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCX0 &&
+ clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ ice_warn(hw, "TCX0 only supports 25 MHz frequency\n");
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw
[PATCH 13/70] net/ice/base: add PHY 56G destination address
Add PHY 56G destination address. PHY56G is a single device
incorporating all SerDes lanes
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_sbq_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ice/base/ice_sbq_cmd.h
b/drivers/net/ice/base/ice_sbq_cmd.h
index a5fe43bf26..76c718b252 100644
--- a/drivers/net/ice/base/ice_sbq_cmd.h
+++ b/drivers/net/ice/base/ice_sbq_cmd.h
@@ -48,6 +48,7 @@ struct ice_sbq_evt_desc {
};
enum ice_sbq_msg_dev {
+ phy_56g = 0x02,
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
--
2.31.1
[PATCH 14/70] net/ice/base: add 56G PHY register definitions
Add 56G PHY register address definitions to facilitate 56G PHY support. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.h | 75 +++ 1 file changed, 75 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9cc3436aa8..ecb79eaea9 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -482,5 +482,80 @@ bool ice_is_pca9575_present(struct ice_hw *hw); #define ICE_E810T_SMA_MIN_BIT 3 #define ICE_E810T_SMA_MAX_BIT 7 #define ICE_E810T_P1_OFFSET8 +/* 56G PHY quad register base addresses */ +#define ICE_PHY0_BASE 0x092000 +#define ICE_PHY1_BASE 0x126000 +#define ICE_PHY2_BASE 0x1BA000 +#define ICE_PHY3_BASE 0x24E000 +#define ICE_PHY4_BASE 0x2E2000 + +/* Timestamp memory */ +#define PHY_PTP_LANE_ADDR_STEP 0x98 + +#define PHY_PTP_MEM_START 0x1000 +#define PHY_PTP_MEM_LANE_STEP 0x04A0 +#define PHY_PTP_MEM_LOCATIONS 0x40 + +/* Number of PHY ports */ +#define ICE_NUM_PHY_PORTS 5 +/* Timestamp PHY incval registers */ +#define PHY_REG_TIMETUS_L 0x8 +#define PHY_REG_TIMETUS_U 0xC + +/* Timestamp init registers */ +#define PHY_REG_RX_TIMER_INC_PRE_L 0x64 +#define PHY_REG_RX_TIMER_INC_PRE_U 0x68 + +#define PHY_REG_TX_TIMER_INC_PRE_L 0x44 +#define PHY_REG_TX_TIMER_INC_PRE_U 0x48 + +/* Timestamp match and adjust target registers */ +#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C +#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70 + +#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C +#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50 + +/* Timestamp command registers */ +#define PHY_REG_TX_TMR_CMD 0x40 +#define PHY_REG_RX_TMR_CMD 0x60 + +/* Phy offset ready registers */ +#define PHY_REG_TX_OFFSET_READY0x54 +#define PHY_REG_RX_OFFSET_READY0x74 +/* Phy total offset registers */ +#define PHY_REG_TOTAL_TX_OFFSET_L 0x38 +#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C + +#define PHY_REG_TOTAL_RX_OFFSET_L 0x58 +#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C + +/* Timestamp capture registers */ +#define PHY_REG_TX_CAPTURE_L 0x78 +#define PHY_REG_TX_CAPTURE_U 0x7C + +#define PHY_REG_RX_CAPTURE_L 0x8C +#define PHY_REG_RX_CAPTURE_U 0x90 + +/* Memory status registers */ +#define PHY_REG_TX_MEMORY_STATUS_L 0x80 +#define PHY_REG_TX_MEMORY_STATUS_U 0x84 + +/* Interrupt config register */ +#define PHY_REG_TS_INT_CONFIG 0x88 + +#define PHY_PTP_INT_STATUS 0x7FD140 + +#define PHY_TS_INT_CONFIG_THRESHOLD_S 0 +#define PHY_TS_INT_CONFIG_THRESHOLD_M MAKEMASK(0x3F, 0) +#define PHY_TS_INT_CONFIG_ENA_S6 +#define PHY_TS_INT_CONFIG_ENA_MBIT(6) + +/* Macros to derive offsets for TimeStampLow and TimeStampHigh */ +#define PHY_TSTAMP_L(x) (((x) * 8) + 0) +#define PHY_TSTAMP_U(x) (((x) * 8) + 4) + +#define PHY_REG_REVISION 0x85000 +#define PHY_REVISION_ETH56G0x10200 #endif /* _ICE_PTP_HW_H_ */ -- 2.31.1
[PATCH 15/70] net/ice/base: implement 56G PHY access functions
Implement 56G PHY register and memory read/write functions
to facilitate PTP support
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 1094 +++--
drivers/net/ice/base/ice_ptp_hw.h | 44 +-
drivers/net/ice/base/ice_type.h | 11 +
3 files changed, 1090 insertions(+), 59 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 22d0774dd7..1c5fd799f6 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -395,7 +395,976 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)
ice_flush(hw);
}
-/* E822 family functions
+/**
+ * ice_ptp_clean_cmd - Clean the timer command register
+ * @hw: pointer to HW struct
+ *
+ * Zero out the GLTSYN_CMD to avoid any residual command execution.
+ */
+static void ice_ptp_clean_cmd(struct ice_hw *hw)
+{
+ wr32(hw, GLTSYN_CMD, 0);
+ ice_flush(hw);
+}
+
+/* 56G PHY access functions */
+static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = {
+ ICE_PHY0_BASE,
+ ICE_PHY1_BASE,
+ ICE_PHY2_BASE,
+ ICE_PHY3_BASE,
+ ICE_PHY4_BASE,
+};
+
+/**
+ * ice_write_phy_eth56g_raw_lp - Write a PHY port register with lock parameter
+ * @hw: pointer to the HW struct
+ * @reg_addr: PHY register address
+ * @val: Value to write
+ * @lock_sbq: true to lock the sideband queue
+ */
+static enum ice_status
+ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input phy_msg;
+ enum ice_status status;
+
+ phy_msg.opcode = ice_sbq_msg_wr;
+
+ phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
+ phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
+
+ phy_msg.data = val;
+ phy_msg.dest_dev = phy_56g;
+
+ status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
+
+ if (status)
+ ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
+ status);
+
+ return status;
+}
+
+/**
+ * ice_read_phy_eth56g_raw_lp - Read a PHY port register with lock parameter
+ * @hw: pointer to the HW struct
+ * @reg_addr: PHY port register address
+ * @val: Pointer to the value to read (out param)
+ * @lock_sbq: true to lock the sideband queue
+ */
+static enum ice_status
+ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,
+ bool lock_sbq)
+{
+ struct ice_sbq_msg_input phy_msg;
+ enum ice_status status;
+
+ phy_msg.opcode = ice_sbq_msg_rd;
+
+ phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
+ phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
+
+ phy_msg.dest_dev = phy_56g;
+
+ status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
+
+ if (status)
+ ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
+ status);
+ else
+ *val = phy_msg.data;
+
+ return status;
+}
+
+/**
+ * ice_phy_port_reg_address_eth56g - Calculate a PHY port register address
+ * @port: Port number to be written
+ * @offset: Offset from PHY port register base
+ * @address: The result address
+ */
+static enum ice_status
+ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32 *address)
+{
+ u8 phy, lane;
+
+ if (port >= ICE_NUM_EXTERNAL_PORTS)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ phy = port / ICE_PORTS_PER_QUAD;
+ lane = port % ICE_PORTS_PER_QUAD;
+
+ *address = offset + eth56g_port_base[phy] +
+ PHY_PTP_LANE_ADDR_STEP * lane;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter
+ * @hw: pointer to the HW struct
+ * @port: Port number to be written
+ * @offset: Offset from PHY port register base
+ * @val: Value to write
+ * @lock_sbq: true to lock the sideband queue
+ */
+static enum ice_status
+ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
+ bool lock_sbq)
+{
+ enum ice_status status;
+ u32 reg_addr;
+
+ status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
+ if (status)
+ return status;
+
+ return ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
+}
+
+/**
+ * ice_write_phy_reg_eth56g - Write a PHY port register with sbq locked
+ * @hw: pointer to the HW struct
+ * @port: Port number to be written
+ * @offset: Offset from PHY port register base
+ * @val: Value to write
+ */
+enum ice_status
+ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
+{
+ return ice_write_phy_reg_eth56g_lp(hw, port, offset, val, true);
+}
+
+/**
+ * ice_read_phy_reg_eth56g_lp - Read a PHY port register with
+ * lock parameter
+ * @hw: pointer to the HW struct
+ * @port: Port number to be read
+ * @offset: Offset from PHY port register base
+ * @val: Pointer to the value to read
[PATCH 16/70] net/ice/base: implement 56G PHY setup functions
Implement setup functions for the 56G PHY Simics model
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 29 +
drivers/net/ice/base/ice_ptp_hw.h | 2 ++
2 files changed, 31 insertions(+)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 1c5fd799f6..093331331d 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1363,6 +1363,35 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw
*hw, u32 *ts_status)
return ICE_SUCCESS;
}
+/**
+ * ice_ptp_init_phy_cfg - Get the current TX timestamp status
+ * mask. Returns the mask of ports where TX timestamps are available
+ * @hw: pointer to the HW struct
+ */
+enum ice_status
+ice_ptp_init_phy_cfg(struct ice_hw *hw)
+{
+ enum ice_status status;
+ u32 phy_rev;
+
+ status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
+ true);
+ if (status)
+ return status;
+
+ if (phy_rev == PHY_REVISION_ETH56G) {
+ hw->phy_cfg = ICE_PHY_ETH56G;
+ return ICE_SUCCESS;
+ }
+
+ if (ice_is_e810(hw))
+ hw->phy_cfg = ICE_PHY_E810;
+ else
+ hw->phy_cfg = ICE_PHY_E822;
+
+ return ICE_SUCCESS;
+}
+
/*
* E822 family functions
*
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index a030a9d4ed..1e016ef177 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -266,6 +266,8 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool
bypass);
enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
+enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);
+
#define PFTSYN_SEM_BYTES 4
#define ICE_PTP_CLOCK_INDEX_0 0x00
--
2.31.1
[PATCH 17/70] net/ice/base: work around missing PTP caps
Provide a WA for missing PTP caps on Simics, this code shall be
removed after cap reporting is fixed
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index e22600c46d..cedce2dcf5 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2516,7 +2516,12 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct
ice_hw_func_caps *func_p,
struct ice_aqc_list_caps_elem *cap)
{
struct ice_ts_func_info *info = &func_p->ts_func_info;
- u32 number = LE32_TO_CPU(cap->number);
+ u32 number = ICE_TS_FUNC_ENA_M | ICE_TS_SRC_TMR_OWND_M |
+ICE_TS_TMR_ENA_M | ICE_TS_TMR_IDX_OWND_M |
+ICE_TS_TMR_IDX_ASSOC_M;
+ u8 clk_freq;
+
+ ice_debug(hw, ICE_DBG_INIT, "1588 func caps: raw value %x\n", number);
info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0);
func_p->common_cap.ieee_1588 = info->ena;
--
2.31.1
[PATCH 18/70] net/ice/base: enable calling of ETH56G functions
Enable calling of ETH56G functions in the base code when the
appropriate PHY has been detected
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 523 --
1 file changed, 498 insertions(+), 25 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 093331331d..1fb0c57a8c 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -502,6 +502,29 @@ ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32
*address)
return ICE_SUCCESS;
}
+/**
+ * ice_phy_port_mem_address_eth56g - Calculate a PHY port memory address
+ * @port: Port number to be written
+ * @offset: Offset from PHY port register base
+ * @address: The result address
+ */
+static enum ice_status
+ice_phy_port_mem_address_eth56g(u8 port, u16 offset, u32 *address)
+{
+ u8 phy, lane;
+
+ if (port >= ICE_NUM_EXTERNAL_PORTS)
+ return ICE_ERR_OUT_OF_RANGE;
+
+ phy = port / ICE_PORTS_PER_QUAD;
+ lane = port % ICE_PORTS_PER_QUAD;
+
+ *address = offset + eth56g_port_base[phy] +
+ PHY_PTP_MEM_START + PHY_PTP_MEM_LANE_STEP * lane;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter
* @hw: pointer to the HW struct
@@ -573,6 +596,80 @@ ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16
offset, u32 *val)
return ice_read_phy_reg_eth56g_lp(hw, port, offset, val, true);
}
+/**
+ * ice_phy_port_mem_read_eth56g_lp - Read a PHY port memory location
+ * with lock parameter
+ * @hw: pointer to the HW struct
+ * @port: Port number to be read
+ * @offset: Offset from PHY port register base
+ * @val: Pointer to the value to read (out param)
+ * @lock_sbq: true to lock the sideband queue
+ */
+static enum ice_status
+ice_phy_port_mem_read_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
+ u32 *val, bool lock_sbq)
+{
+ enum ice_status status;
+ u32 mem_addr;
+
+ status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
+ if (status)
+ return status;
+
+ return ice_read_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
+}
+
+/**
+ * ice_phy_port_mem_read_eth56g - Read a PHY port memory location with
+ * sbq locked
+ * @hw: pointer to the HW struct
+ * @port: Port number to be read
+ * @offset: Offset from PHY port register base
+ * @val: Pointer to the value to read (out param)
+ */
+static enum ice_status
+ice_phy_port_mem_read_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
+{
+ return ice_phy_port_mem_read_eth56g_lp(hw, port, offset, val, true);
+}
+
+/**
+ * ice_phy_port_mem_write_eth56g_lp - Write a PHY port memory location with
+ * lock parameter
+ * @hw: pointer to the HW struct
+ * @port: Port number to be read
+ * @offset: Offset from PHY port register base
+ * @val: Pointer to the value to read (out param)
+ * @lock_sbq: true to lock the sideband queue
+ */
+static enum ice_status
+ice_phy_port_mem_write_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
+u32 val, bool lock_sbq)
+{
+ enum ice_status status;
+ u32 mem_addr;
+
+ status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
+ if (status)
+ return status;
+
+ return ice_write_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
+}
+
+/**
+ * ice_phy_port_mem_write_eth56g - Write a PHY port memory location with
+ * sbq locked
+ * @hw: pointer to the HW struct
+ * @port: Port number to be read
+ * @offset: Offset from PHY port register base
+ * @val: Pointer to the value to read (out param)
+ */
+static enum ice_status
+ice_phy_port_mem_write_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
+{
+ return ice_phy_port_mem_write_eth56g_lp(hw, port, offset, val, true);
+}
+
/**
* ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
* @low_addr: the low address to check
@@ -778,6 +875,140 @@ ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val)
return ICE_SUCCESS;
}
+/**
+ * ice_read_phy_tstamp_eth56g - Read a PHY timestamp out of the port memory
+ * @hw: pointer to the HW struct
+ * @port: the port to read from
+ * @idx: the timestamp index to read
+ * @tstamp: on return, the 40bit timestamp value
+ *
+ * Read a 40bit timestamp value out of the two associated entries in the
+ * port memory block of the internal PHYs of the 56G devices.
+ */
+static enum ice_status
+ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp)
+{
+ enum ice_status status;
+ u16 lo_addr, hi_addr;
+ u32 lo, hi;
+
+ lo_addr = (u16)PHY_TSTAMP_L(idx);
+ hi_addr = (u16)PHY_TSTAMP_U(idx);
+
+ status = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read lo
[PATCH 19/70] net/ice/base: fix PHY type 10G SFI C2C to media type mapping
PHY type ICE_PHY_TYPE_LOW_10G_SFI_C2C is incorrectly mapped to media
type Fiber which results in ethtool reporting the wrong Supported
ports.
PHY type ICE_PHY_TYPE_LOW_10G_SFI_C2C should map to media type
Backplane.
Fixes: 453d087ccaff ("net/ice/base: add common functions")
Cc: sta...@dpdk.org
Signed-off-by: Paul Greenwalt
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index cedce2dcf5..57602a31e1 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -561,7 +561,6 @@ static enum ice_media_type ice_get_media_type(struct
ice_port_info *pi)
case ICE_PHY_TYPE_LOW_1000BASE_LX:
case ICE_PHY_TYPE_LOW_10GBASE_SR:
case ICE_PHY_TYPE_LOW_10GBASE_LR:
- case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_SR:
case ICE_PHY_TYPE_LOW_25GBASE_LR:
case ICE_PHY_TYPE_LOW_40GBASE_SR4:
@@ -618,6 +617,7 @@ static enum ice_media_type ice_get_media_type(struct
ice_port_info *pi)
case ICE_PHY_TYPE_LOW_2500BASE_X:
case ICE_PHY_TYPE_LOW_5GBASE_KR:
case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
+ case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_KR:
case ICE_PHY_TYPE_LOW_25GBASE_KR1:
case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
--
2.31.1
[PATCH 21/70] net/ice/base: add E822 generic PCI device ID
The E822 has a generic PCI device ID that can be used in the PLDM
header when updating the device so add it.
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_devids.h | 3 ++-
drivers/net/ice/ice_ethdev.c | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_devids.h
b/drivers/net/ice/base/ice_devids.h
index 96f2528c5e..96dbb92e0a 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -6,7 +6,6 @@
#define _ICE_DEVIDS_H_
/* Device IDs */
-/* Intel(R) Ethernet Connection E823-L for backplane */
#define ICE_DEV_ID_E823L_BACKPLANE 0x124C
/* Intel(R) Ethernet Connection E823-L for SFP */
#define ICE_DEV_ID_E823L_SFP 0x124D
@@ -31,6 +30,8 @@
/* Intel(R) Ethernet Controller E810-XXV for SFP */
#define ICE_DEV_ID_E810_XXV_SFP0x159B
/* Intel(R) Ethernet Connection E823-C for backplane */
+#define ICE_DEV_ID_E822_SI_DFLT0x1888
+/* Intel(R) Ethernet Connection E823-L for backplane */
#define ICE_DEV_ID_E823C_BACKPLANE 0x188A
/* Intel(R) Ethernet Connection E823-C for QSFP */
#define ICE_DEV_ID_E823C_QSFP 0x188B
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 2e522376e3..551be3566f 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -187,6 +187,7 @@ static const struct rte_pci_id pci_id_ice_map[] = {
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
+ { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822_SI_DFLT) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
--
2.31.1
[PATCH 22/70] net/ice/base: support double VLAN rules
Add support for double vlan rules with c-tag and s-tag in it.
Enable the caller to configure double vlan rules, and use extended
package capabilities to allow adding flow with double vlans.
The patch also re-order the code in ice_switch.c to align with
kernel driver.
Signed-off-by: Wiktor Pilarczyk
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 846 --
1 file changed, 441 insertions(+), 405 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index ad61dde397..e59d191c46 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -15,8 +15,8 @@
#define ICE_PPP_IPV6_PROTO_ID 0x0057
#define ICE_TCP_PROTO_ID 0x06
#define ICE_GTPU_PROFILE 24
-#define ICE_ETH_P_8021Q0x8100
#define ICE_MPLS_ETHER_ID 0x8847
+#define ICE_ETH_P_8021Q0x8100
/* Dummy ethernet header needed in the ice_aqc_sw_rules_elem
* struct to configure any switch filter rules.
@@ -321,25 +321,6 @@ static const u8 dummy_tcp_packet[] = {
0x00, 0x00, /* 2 bytes for 4 byte alignment */
};
-/* offset info for MAC + MPLS dummy packet */
-static const struct ice_dummy_pkt_offsets dummy_mpls_packet_offsets[] = {
- { ICE_MAC_OFOS, 0 },
- { ICE_ETYPE_OL, 12 },
- { ICE_PROTOCOL_LAST,0 },
-};
-
-/* Dummy packet for MAC + MPLS */
-static const u8 dummy_mpls_packet[] = {
- 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
- 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00,
-
- 0x88, 0x47, /* ICE_ETYPE_OL 12 */
- 0x00, 0x00, 0x01, 0x00,
-
- 0x00, 0x00, /* 2 bytes for 4 byte alignment */
-};
-
/* offset info for MAC + VLAN (C-tag, 802.1Q) + IPv4 + TCP dummy packet */
static const struct ice_dummy_pkt_offsets dummy_vlan_tcp_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
@@ -1115,63 +1096,198 @@ static const u8 dummy_ipv6_gtpu_ipv6_packet[] = {
0x00, 0x00,
};
-static const struct ice_dummy_pkt_offsets dummy_udp_gtp_packet_offsets[] = {
+static const
+struct ice_dummy_pkt_offsets dummy_ipv4_gtp_no_pay_packet_offsets[] = {
{ ICE_MAC_OFOS, 0 },
{ ICE_IPV4_OFOS,14 },
{ ICE_UDP_OF, 34 },
- { ICE_GTP, 42 },
+ { ICE_GTP_NO_PAY, 42 },
{ ICE_PROTOCOL_LAST,0 },
};
-static const u8 dummy_udp_gtp_packet[] = {
+static const
+struct ice_dummy_pkt_offsets dummy_ipv6_gtp_no_pay_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_IPV6_OFOS,14 },
+ { ICE_UDP_OF, 54 },
+ { ICE_GTP_NO_PAY, 62 },
+ { ICE_PROTOCOL_LAST,0 },
+};
+
+static const u8 dummy_ipv6_gtp_packet[] = {
0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
- 0x08, 0x00,
+ 0x86, 0xdd,
- 0x45, 0x00, 0x00, 0x30, /* ICE_IPV4_OFOS 14 */
+ 0x60, 0x00, 0x00, 0x00, /* ICE_IPV6_OFOS 14 */
+ 0x00, 0x6c, 0x11, 0x00, /* Next header UDP*/
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x08, 0x68, 0x08, 0x68, /* ICE_UDP_OF 54 */
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x30, 0x00, 0x00, 0x28, /* ICE_GTP 62 */
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00,
+};
+
+static const struct ice_dummy_pkt_offsets dummy_qinq_ipv4_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV4_OFOS,22 },
+ { ICE_PROTOCOL_LAST,0 },
+};
+
+static const u8 dummy_qinq_ipv4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x91, 0x00, 0x00, 0x00, /* ICE_VLAN_EX 12 */
+ 0x81, 0x00, 0x00, 0x00, /* ICE_VLAN_IN 16 */
+ 0x08, 0x00, /* ICE_ETYPE_OL 20 */
+
+ 0x45, 0x00, 0x00, 0x14, /* ICE_IPV4_OFOS 22 */
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+
+ 0x00, 0x00, /* 2 bytes for 4 byte alignment */
+};
+
+static const
+struct ice_dummy_pkt_offsets dummy_qinq_ipv4_udp_packet_offsets[] = {
+ { ICE_MAC_OFOS, 0 },
+ { ICE_VLAN_EX, 12 },
+ { ICE_VLAN_IN, 16 },
+ { ICE_ETYPE_OL, 20 },
+ { ICE_IPV4_OFOS,22 },
+ { ICE_UDP_ILOS, 42 },
+ { ICE_PROTOCOL_LAST,0 },
+};
+
+static const u8 dummy_qinq_ipv4_udp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, /* ICE_MAC_OFOS 0 */
0x00, 0x00, 0
[PATCH 23/70] net/ice/base: report NVM version numbers on mismatch
Report NVM version numbers (both detected and expected) when a
mismatch b/w driver and firmware is detected.
This would provide more useful information about which NVM
version the driver expects instead of looking up the code
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_controlq.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_controlq.c
b/drivers/net/ice/base/ice_controlq.c
index cdd067ce7f..d83d0d76d0 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -495,12 +495,18 @@ static bool ice_aq_ver_check(struct ice_hw *hw)
return false;
} else if (hw->api_maj_ver == EXP_FW_API_VER_MAJOR) {
if (hw->api_min_ver > (EXP_FW_API_VER_MINOR + 2))
- ice_info(hw, "The driver for the device detected a
newer version of the NVM image than expected. Please install the most recent
version of the network driver.\n");
+ ice_info(hw, "The driver for the device detected a
newer version (%u.%u) of the NVM image than expected (%u.%u). Please install
the most recent version of the network driver.\n",
+hw->api_maj_ver, hw->api_min_ver,
+EXP_FW_API_VER_MAJOR, EXP_FW_API_VER_MINOR);
else if ((hw->api_min_ver + 2) < EXP_FW_API_VER_MINOR)
- ice_info(hw, "The driver for the device detected an
older version of the NVM image than expected. Please update the NVM image.\n");
+ ice_info(hw, "The driver for the device detected an
older version (%u.%u) of the NVM image than expected (%u.%u). Please update the
NVM image.\n",
+hw->api_maj_ver, hw->api_min_ver,
+EXP_FW_API_VER_MAJOR, EXP_FW_API_VER_MINOR);
} else {
/* Major API version is older than expected, log a warning */
- ice_info(hw, "The driver for the device detected an older
version of the NVM image than expected. Please update the NVM image.\n");
+ ice_info(hw, "The driver for the device detected an older
version (%u.%u) of the NVM image than expected (%u.%u). Please update the NVM
image.\n",
+hw->api_maj_ver, hw->api_min_ver,
+EXP_FW_API_VER_MAJOR, EXP_FW_API_VER_MINOR);
}
return true;
}
--
2.31.1
[PATCH 24/70] net/ice/base: create duplicate detection for ACL rules
Currently there is no check for adding duplicate ACL rules,
this creates subtle bugs, for example unability to remove
filters. Adding check + refactoring a redundant function.
Signed-off-by: Michal Wilczynski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_fdir.c | 99 -
drivers/net/ice/base/ice_fdir.h | 5 ++
2 files changed, 42 insertions(+), 62 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index ae76361102..6bbab0c843 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -4204,70 +4204,56 @@ ice_fdir_update_cntrs(struct ice_hw *hw, enum
ice_fltr_ptype flow,
}
/**
- * ice_cmp_ipv6_addr - compare 2 IP v6 addresses
- * @a: IP v6 address
- * @b: IP v6 address
+ * ice_fdir_comp_rules_basic - compare 2 filters
+ * @a: a Flow Director filter data structure
+ * @b: a Flow Director filter data structure
*
- * Returns 0 on equal, returns non-0 if different
+ * Returns true if the filters match
*/
-static int ice_cmp_ipv6_addr(__be32 *a, __be32 *b)
+bool
+ice_fdir_comp_rules_basic(struct ice_fdir_fltr *a, struct ice_fdir_fltr *b)
{
- return memcmp(a, b, 4 * sizeof(__be32));
+ if (a->flow_type != b->flow_type)
+ return false;
+ if (memcmp(&a->ip, &b->ip, sizeof(a->ip)))
+ return false;
+ if (memcmp(&a->mask, &b->mask, sizeof(a->mask)))
+ return false;
+
+ return true;
}
/**
- * ice_fdir_comp_rules - compare 2 filters
+ * ice_fdir_comp_rules_extended - compare 2 filters
* @a: a Flow Director filter data structure
* @b: a Flow Director filter data structure
- * @v6: bool true if v6 filter
*
* Returns true if the filters match
*/
-static bool
-ice_fdir_comp_rules(struct ice_fdir_fltr *a, struct ice_fdir_fltr *b, bool v6)
+bool
+ice_fdir_comp_rules_extended(struct ice_fdir_fltr *a, struct ice_fdir_fltr *b)
{
- enum ice_fltr_ptype flow_type = a->flow_type;
+ if (!ice_fdir_comp_rules_basic(a, b))
+ return false;
- /* The calling function already checks that the two filters have the
-* same flow_type.
-*/
- if (!v6) {
- if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_TCP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV4_UDP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV4_SCTP) {
- if (a->ip.v4.dst_ip == b->ip.v4.dst_ip &&
- a->ip.v4.src_ip == b->ip.v4.src_ip &&
- a->ip.v4.dst_port == b->ip.v4.dst_port &&
- a->ip.v4.src_port == b->ip.v4.src_port)
- return true;
- } else if (flow_type == ICE_FLTR_PTYPE_NONF_IPV4_OTHER) {
- if (a->ip.v4.dst_ip == b->ip.v4.dst_ip &&
- a->ip.v4.src_ip == b->ip.v4.src_ip &&
- a->ip.v4.l4_header == b->ip.v4.l4_header &&
- a->ip.v4.proto == b->ip.v4.proto &&
- a->ip.v4.ip_ver == b->ip.v4.ip_ver &&
- a->ip.v4.tos == b->ip.v4.tos)
- return true;
- }
- } else {
- if (flow_type == ICE_FLTR_PTYPE_NONF_IPV6_UDP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV6_TCP ||
- flow_type == ICE_FLTR_PTYPE_NONF_IPV6_SCTP) {
- if (a->ip.v6.dst_port == b->ip.v6.dst_port &&
- a->ip.v6.src_port == b->ip.v6.src_port &&
- !ice_cmp_ipv6_addr(a->ip.v6.dst_ip,
- b->ip.v6.dst_ip) &&
- !ice_cmp_ipv6_addr(a->ip.v6.src_ip,
- b->ip.v6.src_ip))
- return true;
- } else if (flow_type == ICE_FLTR_PTYPE_NONF_IPV6_OTHER) {
- if (a->ip.v6.dst_port == b->ip.v6.dst_port &&
- a->ip.v6.src_port == b->ip.v6.src_port)
- return true;
- }
- }
+ if (memcmp(&a->gtpu_data, &b->gtpu_data, sizeof(a->gtpu_data)))
+ return false;
+ if (memcmp(&a->gtpu_mask, &b->gtpu_mask, sizeof(a->gtpu_mask)))
+ return false;
+ if (memcmp(&a->l2tpv3_data, &b->l2tpv3_data, sizeof(a->l2tpv3_data)))
+ return false;
+ if (memcmp(&a->l2tpv3_mask, &b->l2tpv3_mask, sizeof(a->l2tpv3_mask)))
+ return false;
+ if (memcmp(&a->ext_data, &b->ext_data, sizeof(a->ext_data)))
+ return false;
+ if (memcmp(&a->ext_mask, &b->ext_mask, sizeof(a->ext_mask)))
+ return false;
+ if (memcmp(&a->ecpri_data, &b->ecpri_data, sizeof(a->ecpri_data)))
+ return false;
+ if (memcmp(&a->ecpri_mask, &b->ecpri_mask, sizeof(a->ecpri_mask)))
+
[PATCH 25/70] net/ice/base: fix incorrect function descriptions for parser
Some function descriptions for parser are mismatched, thus fixed
with this patch.
Fixes: 7fe2d98070e0 ("net/ice/base: add parser create and destroy skeleton")
Fixes: 1792942b2df6 ("net/ice/base: init boost TCAM table for parser")
Fixes: f787952d13d2 ("net/ice/base: init flag redirect table for parser")
Fixes: b3e73a812f98 ("net/ice/base: init IMEM table for parser")
Fixes: 2f7a1864cc19 ("net/ice/base: init metainit table for parser")
Fixes: 90bbd7d9545f ("net/ice/base: init marker group table for parser")
Fixes: c55b1ba93f07 ("net/ice/base: init parse graph CAM table for parser")
Fixes: 7b61be517fd5 ("net/ice/base: init protocol group table for parser")
Fixes: 111871087cdf ("net/ice/base: init ptype marker TCAM table for parser")
Fixes: 0cbacf60dce7 ("net/ice/base: init XLT key builder for parser")
Cc: sta...@dpdk.org
Signed-off-by: Junfeng Guo
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_bst_tcam.c | 6 +++---
drivers/net/ice/base/ice_flg_rd.c| 4 ++--
drivers/net/ice/base/ice_imem.c | 4 ++--
drivers/net/ice/base/ice_metainit.c | 4 ++--
drivers/net/ice/base/ice_mk_grp.c| 4 ++--
drivers/net/ice/base/ice_parser.c| 7 ---
drivers/net/ice/base/ice_pg_cam.c| 12 ++--
drivers/net/ice/base/ice_proto_grp.c | 4 ++--
drivers/net/ice/base/ice_ptype_mk.c | 4 ++--
drivers/net/ice/base/ice_xlt_kb.c| 10 +-
10 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/net/ice/base/ice_bst_tcam.c
b/drivers/net/ice/base/ice_bst_tcam.c
index 306f62db2a..74a2de869e 100644
--- a/drivers/net/ice/base/ice_bst_tcam.c
+++ b/drivers/net/ice/base/ice_bst_tcam.c
@@ -53,7 +53,7 @@ static void _bst_alu_dump(struct ice_hw *hw, struct ice_alu
*alu, int index)
/**
* ice_bst_tcam_dump - dump a boost tcam info
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
* @item: boost tcam to dump
*/
void ice_bst_tcam_dump(struct ice_hw *hw, struct ice_bst_tcam_item *item)
@@ -205,7 +205,7 @@ static void _bst_parse_item(struct ice_hw *hw, u16 idx,
void *item,
/**
* ice_bst_tcam_table_get - create a boost tcam table
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
*/
struct ice_bst_tcam_item *ice_bst_tcam_table_get(struct ice_hw *hw)
{
@@ -228,7 +228,7 @@ static void _parse_lbl_item(struct ice_hw *hw, u16 idx,
void *item,
/**
* ice_bst_lbl_table_get - create a boost label table
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
*/
struct ice_lbl_item *ice_bst_lbl_table_get(struct ice_hw *hw)
{
diff --git a/drivers/net/ice/base/ice_flg_rd.c
b/drivers/net/ice/base/ice_flg_rd.c
index 833986cac3..80d3b51ad6 100644
--- a/drivers/net/ice/base/ice_flg_rd.c
+++ b/drivers/net/ice/base/ice_flg_rd.c
@@ -9,7 +9,7 @@
/**
* ice_flg_rd_dump - dump a flag redirect item info
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
* @item: flag redirect item to dump
*/
void ice_flg_rd_dump(struct ice_hw *hw, struct ice_flg_rd_item *item)
@@ -40,7 +40,7 @@ static void _flg_rd_parse_item(struct ice_hw *hw, u16 idx,
void *item,
/**
* ice_flg_rd_table_get - create a flag redirect table
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
*/
struct ice_flg_rd_item *ice_flg_rd_table_get(struct ice_hw *hw)
{
diff --git a/drivers/net/ice/base/ice_imem.c b/drivers/net/ice/base/ice_imem.c
index 2136e0393b..9a76d21ce5 100644
--- a/drivers/net/ice/base/ice_imem.c
+++ b/drivers/net/ice/base/ice_imem.c
@@ -69,7 +69,7 @@ static void _imem_alu_dump(struct ice_hw *hw, struct ice_alu
*alu, int index)
/**
* ice_imem_dump - dump an imem item info
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
* @item: imem item to dump
*/
void ice_imem_dump(struct ice_hw *hw, struct ice_imem_item *item)
@@ -231,7 +231,7 @@ static void _imem_parse_item(struct ice_hw *hw, u16 idx,
void *item,
/**
* ice_imem_table_get - create an imem table
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
*/
struct ice_imem_item *ice_imem_table_get(struct ice_hw *hw)
{
diff --git a/drivers/net/ice/base/ice_metainit.c
b/drivers/net/ice/base/ice_metainit.c
index 3f9e5d6833..a899125b37 100644
--- a/drivers/net/ice/base/ice_metainit.c
+++ b/drivers/net/ice/base/ice_metainit.c
@@ -9,7 +9,7 @@
/**
* ice_metainit_dump - dump an metainit item info
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
* @item: metainit item to dump
*/
void ice_metainit_dump(struct ice_hw *hw, struct ice_metainit_item *item)
@@ -130,7 +130,7 @@ static void _metainit_parse_item(struct ice_hw *hw, u16
idx, void *item,
/**
* ice_metainit_table_get - create a metainit table
- * @ice_hw: pointer to the hardware structure
+ * @hw: pointer to the hardware structure
*/
struct
[PATCH 26/70] net/ice/base: fix endian format
A few functions failed to properly convert some values into Little
Endian format before sending them to the firmware. This will produce
incorrect results when running on a Big Endian platform.
Fix this by adding the necessary CPU_TO_LE* macros around the input
to firmware.
These issues were detected by sparse.
Fixes: 0f61c2af88c8 ("net/ice/base: add set/get GPIO helper functions")
Cc: sta...@dpdk.org
Signed-off-by: Jacob Keller
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index 57602a31e1..cb06fdf42b 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -4028,7 +4028,7 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_read_topo_dev_nvm);
- desc.datalen = data_size;
+ desc.datalen = CPU_TO_LE16(data_size);
ice_memcpy(&cmd->topo_params, topo_params, sizeof(*topo_params),
ICE_NONDMA_TO_NONDMA);
cmd->start_address = CPU_TO_LE32(start_address);
@@ -5682,7 +5682,7 @@ ice_aq_set_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle,
u8 pin_idx, bool value,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_gpio);
cmd = &desc.params.read_write_gpio;
- cmd->gpio_ctrl_handle = gpio_ctrl_handle;
+ cmd->gpio_ctrl_handle = CPU_TO_LE16(gpio_ctrl_handle);
cmd->gpio_num = pin_idx;
cmd->gpio_val = value ? 1 : 0;
@@ -5710,7 +5710,7 @@ ice_aq_get_gpio(struct ice_hw *hw, u16 gpio_ctrl_handle,
u8 pin_idx,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_gpio);
cmd = &desc.params.read_write_gpio;
- cmd->gpio_ctrl_handle = gpio_ctrl_handle;
+ cmd->gpio_ctrl_handle = CPU_TO_LE16(gpio_ctrl_handle);
cmd->gpio_num = pin_idx;
status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
--
2.31.1
[PATCH 27/70] net/ice/base: convert IO expander handle to u16
The io_expander_handle cached value is marked as an __le16, but
several places track the node handle with u16 values. Unify all
the interfaces so that it is stored and reported as a u16, and
keep the low level conversion to LE16 only at the direct firmware
interface.
This fixes warnings from sparse about mixing __le16 and u16, and
will fix related issues on platforms which use Big Endian format.
Signed-off-by: Jacob Keller
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 10 +++---
drivers/net/ice/base/ice_type.h | 2 +-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 1fb0c57a8c..3df0915cd3 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4483,7 +4483,7 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
* will return cached value
*/
static enum ice_status
-ice_get_pca9575_handle(struct ice_hw *hw, __le16 *pca9575_handle)
+ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
{
struct ice_aqc_get_link_topo cmd;
u8 node_part_number, idx;
@@ -4564,13 +4564,15 @@ ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8
offset, u8 *data)
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
__le16 addr;
+ u16 handle;
memset(&link_topo, 0, sizeof(link_topo));
- status = ice_get_pca9575_handle(hw, &link_topo.handle);
+ status = ice_get_pca9575_handle(hw, &handle);
if (status)
return status;
+ link_topo.handle = CPU_TO_LE16(handle);
link_topo.topo_params.node_type_ctx =
(ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
ICE_AQC_LINK_TOPO_NODE_CTX_S);
@@ -4594,13 +4596,15 @@ ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8
offset, u8 data)
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
__le16 addr;
+ u16 handle;
memset(&link_topo, 0, sizeof(link_topo));
- status = ice_get_pca9575_handle(hw, &link_topo.handle);
+ status = ice_get_pca9575_handle(hw, &handle);
if (status)
return status;
+ link_topo.handle = CPU_TO_LE16(handle);
link_topo.topo_params.node_type_ctx =
(ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
ICE_AQC_LINK_TOPO_NODE_CTX_S);
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index d94fdcda67..b8be0d948a 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1259,7 +1259,7 @@ struct ice_hw {
struct LIST_HEAD_TYPE rss_list_head;
ice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);
u8 dvm_ena;
- __le16 io_expander_handle;
+ u16 io_expander_handle;
};
/* Statistics collected by each port, VSI, VEB, and S-channel */
--
2.31.1
[PATCH 28/70] net/ice/base: convert array of u8 to bitmap
Previously the ice_add_prof function took an array of u8 and looped
over it with for_each_set_bit, examining each 8 bit value as a bitmap.
This was just hard to understand and unnecessary, and was triggering
undefined behavior sanitizers with unaligned accesses within bitmap
fields. Since the ptype being passed in was already declared as a
bitmap, refactor this to use native types with the advantage of
simplifying the code to use a single loop.
Signed-off-by: Jacob Keller
Signed-off-by: Jesse Brandeburg
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_pipe.c | 76 ++--
drivers/net/ice/base/ice_flex_pipe.h | 6 +--
drivers/net/ice/base/ice_flow.c | 4 +-
3 files changed, 32 insertions(+), 54 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c
b/drivers/net/ice/base/ice_flex_pipe.c
index a43d7ef76b..0840b976aa 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3170,7 +3170,7 @@ void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id)
* @hw: pointer to the HW struct
* @blk: hardware block
* @id: profile tracking ID
- * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
+ * @ptypes: bitmap indicating ptypes (ICE_FLOW_PTYPE_MAX bits)
* @attr: array of attributes
* @attr_cnt: number of elements in attrib array
* @es: extraction sequence (length of array is determined by the block)
@@ -3183,16 +3183,15 @@ void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id)
* the ID value used here.
*/
enum ice_status
-ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],
-const struct ice_ptype_attributes *attr, u16 attr_cnt,
-struct ice_fv_word *es, u16 *masks, bool fd_swap)
+ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id,
+ice_bitmap_t *ptypes, const struct ice_ptype_attributes *attr,
+u16 attr_cnt, struct ice_fv_word *es, u16 *masks, bool fd_swap)
{
- u32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);
ice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);
struct ice_prof_map *prof;
enum ice_status status;
- u8 byte = 0;
u8 prof_id;
+ u16 ptype;
ice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);
@@ -3241,56 +3240,35 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64
id, u8 ptypes[],
prof->context = 0;
/* build list of ptgs */
- while (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {
- u8 bit;
+ ice_for_each_set_bit(ptype, ptypes, ICE_FLOW_PTYPE_MAX) {
+ u8 ptg;
- if (!ptypes[byte]) {
- bytes--;
- byte++;
+ /* The package should place all ptypes in a non-zero
+* PTG, so the following call should never fail.
+*/
+ if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
continue;
- }
-
- /* Examine 8 bits per byte */
- ice_for_each_set_bit(bit, (ice_bitmap_t *)&ptypes[byte],
-BITS_PER_BYTE) {
- u16 ptype;
- u8 ptg;
-
- ptype = byte * BITS_PER_BYTE + bit;
- /* The package should place all ptypes in a non-zero
-* PTG, so the following call should never fail.
-*/
- if (ice_ptg_find_ptype(hw, blk, ptype, &ptg))
- continue;
+ /* If PTG is already added, skip and continue */
+ if (ice_is_bit_set(ptgs_used, ptg))
+ continue;
- /* If PTG is already added, skip and continue */
- if (ice_is_bit_set(ptgs_used, ptg))
- continue;
+ ice_set_bit(ptg, ptgs_used);
+ /* Check to see there are any attributes for this ptype, and
+* add them if found.
+*/
+ status = ice_add_prof_attrib(prof, ptg, ptype, attr, attr_cnt);
+ if (status == ICE_ERR_MAX_LIMIT)
+ break;
+ if (status) {
+ /* This is simple a ptype/PTG with no attribute */
+ prof->ptg[prof->ptg_cnt] = ptg;
+ prof->attr[prof->ptg_cnt].flags = 0;
+ prof->attr[prof->ptg_cnt].mask = 0;
- ice_set_bit(ptg, ptgs_used);
- /* Check to see there are any attributes for this
-* ptype, and add them if found.
-*/
- status = ice_add_prof_attrib(prof, ptg, ptype, attr,
-attr_cnt);
- if (status == ICE_ERR_MAX_LIMIT)
+ if (++pro
[PATCH 29/70] net/ice/base: fix array overflow in add switch recipe code
The array indexes in this function are used with a zero index in the
fv_idx table, and with a +1 index in the lkup_idx arrays. The code
was using the lookup index for the field vector in only one place in
this function, but the code was never used after this point so just
remove the bad line.
This was caught by the undefined behavior sanitizer.
Fixes: fed0c5ca5f19 ("net/ice/base: support programming a new switch recipe")
Cc: sta...@dpdk.org
Signed-off-by: Jesse Brandeburg
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index e59d191c46..b8e733f539 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -7315,7 +7315,6 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe
*rm,
last_chain_entry->chain_idx = ICE_INVAL_CHAIN_IND;
LIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry,
l_entry) {
- last_chain_entry->fv_idx[i] = entry->chain_idx;
buf[recps].content.lkup_indx[i] = entry->chain_idx;
buf[recps].content.mask[i++] = CPU_TO_LE16(0x);
ice_set_bit(entry->rid, rm->r_bitmap);
--
2.31.1
[PATCH 30/70] net/ice/base: fix bit finding range over ptype bitmap
The 2nd argument to function ice_find_first_bit is the bitmap size,
(in bits) not a mask. Thus, use of UINT16_MAX or 0x will allow a
potential run off the end of the ptype array.
Also, the ptype bitmap (i.e., prof->ptypes) is declared with size
ICE_FLOW_PTYPE_MAX, thus finding the bits within this bitmap should
not exceed this bound.
Fixes: 8ebb93942b2c ("net/ice/base: add function to set HW profile for raw
flow")
Cc: sta...@dpdk.org
Signed-off-by: Junfeng Guo
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flow.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 54181044f1..b196e51276 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -2561,7 +2561,7 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16
dest_vsi_handle,
u16 fdir_vsi_handle, struct ice_parser_profile *prof,
enum ice_block blk)
{
- int id = ice_find_first_bit(prof->ptypes, UINT16_MAX);
+ int id = ice_find_first_bit(prof->ptypes, ICE_FLOW_PTYPE_MAX);
struct ice_flow_prof_params *params;
u8 fv_words = hw->blk[blk].es.fvw;
enum ice_status status;
--
2.31.1
[PATCH 31/70] net/ice/base: move function to internal
The function ice_disable_fd_swap should be defined as static.
Signed-off-by: Junfeng Guo
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_pipe.c | 2 +-
drivers/net/ice/base/ice_flex_pipe.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c
b/drivers/net/ice/base/ice_flex_pipe.c
index 0840b976aa..aea0d97b9d 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3133,7 +3133,7 @@ ice_add_prof_attrib(struct ice_prof_map *prof, u8 ptg,
u16 ptype,
* @hw: pointer to the HW struct
* @prof_id: profile ID
*/
-void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id)
+static void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id)
{
u8 swap_val = ICE_SWAP_VALID;
u8 i;
diff --git a/drivers/net/ice/base/ice_flex_pipe.h
b/drivers/net/ice/base/ice_flex_pipe.h
index 90a9c0..8fde36dfa6 100644
--- a/drivers/net/ice/base/ice_flex_pipe.h
+++ b/drivers/net/ice/base/ice_flex_pipe.h
@@ -38,7 +38,6 @@ bool ice_hw_ptype_ena(struct ice_hw *hw, u16 ptype);
/* XLT2/VSI group functions */
enum ice_status
ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);
-void ice_disable_fd_swap(struct ice_hw *hw, u16 prof_id);
enum ice_status
ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id,
ice_bitmap_t *ptypes, const struct ice_ptype_attributes *attr,
--
2.31.1
[PATCH 32/70] net/ice/base: change PHY/QUAD/ports definitions
Rename PHY/QUAD/ports definitions to reflect the correct HW
specification.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 45 ---
drivers/net/ice/base/ice_type.h | 14 +-
2 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 3df0915cd3..7ed420be8e 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1794,9 +1794,9 @@ ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8
port, u16 offset)
{
int phy_port, phy, quadtype;
- phy_port = port % ICE_PORTS_PER_PHY;
- phy = port / ICE_PORTS_PER_PHY;
- quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE;
+ phy_port = port % ICE_PORTS_PER_PHY_E822;
+ phy = port / ICE_PORTS_PER_PHY_E822;
+ quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_QUADS_PER_PHY_E822;
if (quadtype == 0) {
msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port);
@@ -2184,20 +2184,25 @@ ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port,
u16 low_addr, u64 val)
* Fill a message buffer for accessing a register in a quad shared between
* multiple PHYs.
*/
-static void
+static enum ice_status
ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)
{
u32 addr;
+ if (quad >= ICE_MAX_QUAD)
+ return ICE_ERR_PARAM;
+
msg->dest_dev = rmn_0;
- if ((quad % ICE_NUM_QUAD_TYPE) == 0)
+ if ((quad % ICE_QUADS_PER_PHY_E822) == 0)
addr = Q_0_BASE + offset;
else
addr = Q_1_BASE + offset;
msg->msg_addr_low = ICE_LO_WORD(addr);
msg->msg_addr_high = ICE_HI_WORD(addr);
+
+ return ICE_SUCCESS;
}
/**
@@ -2218,22 +2223,21 @@ ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad,
u16 offset, u32 *val,
struct ice_sbq_msg_input msg = {0};
enum ice_status status;
- if (quad >= ICE_MAX_QUAD)
- return ICE_ERR_PARAM;
+ status = ice_fill_quad_msg_e822(&msg, quad, offset);
+ if (status)
+ goto exit_err;
- ice_fill_quad_msg_e822(&msg, quad, offset);
msg.opcode = ice_sbq_msg_rd;
status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
+exit_err:
+ if (status)
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy,
status %d\n",
status);
- return status;
- }
-
- *val = msg.data;
+ else
+ *val = msg.data;
- return ICE_SUCCESS;
+ return status;
}
enum ice_status
@@ -2260,21 +2264,20 @@ ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad,
u16 offset, u32 val,
struct ice_sbq_msg_input msg = {0};
enum ice_status status;
- if (quad >= ICE_MAX_QUAD)
- return ICE_ERR_PARAM;
+ status = ice_fill_quad_msg_e822(&msg, quad, offset);
+ if (status)
+ goto exit_err;
- ice_fill_quad_msg_e822(&msg, quad, offset);
msg.opcode = ice_sbq_msg_wr;
msg.data = val;
status = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);
- if (status) {
+exit_err:
+ if (status)
ice_debug(hw, ICE_DBG_PTP, "Failed to send message to phy,
status %d\n",
status);
- return status;
- }
- return ICE_SUCCESS;
+ return status;
}
enum ice_status
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index b8be0d948a..5c7cc06e0c 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1191,13 +1191,13 @@ struct ice_hw {
/* true if VSIs can share unicast MAC addr */
u8 umac_shared;
-#define ICE_PHY_PER_NAC1
-#define ICE_MAX_QUAD 2
-#define ICE_NUM_QUAD_TYPE 2
-#define ICE_PORTS_PER_QUAD 4
-#define ICE_PHY_0_LAST_QUAD1
-#define ICE_PORTS_PER_PHY 8
-#define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
+#define ICE_PHY_PER_NAC_E822 1
+#define ICE_MAX_QUAD 2
+#define ICE_QUADS_PER_PHY_E822 2
+#define ICE_PORTS_PER_PHY_E822 8
+#define ICE_PORTS_PER_QUAD 4
+#define ICE_PORTS_PER_PHY_E810 4
+#define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
/* bitmap of enabled logical ports */
u32 ena_lports;
--
2.31.1
[PATCH 33/70] net/ice/base: add AQ command to config node attribute
Added AQ command to config nod attribute.
Signed-off-by: Ben Shelton
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 17 +
drivers/net/ice/base/ice_sched.c | 27 +++
drivers/net/ice/base/ice_sched.h | 4
3 files changed, 48 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 8f7e13096c..9f84ffca67 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1215,6 +1215,22 @@ struct ice_aqc_rl_profile_elem {
__le16 rl_encode;
};
+/* Config Node Attributes (indirect 0x0419)
+ * Query Node Attributes (indirect 0x041A)
+ */
+struct ice_aqc_node_attr {
+ __le16 num_entries; /* Number of attributes structures in the buffer */
+ u8 reserved[6];
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
+struct ice_aqc_node_attr_elem {
+ __le32 node_teid;
+ __le16 max_children;
+ __le16 children_level;
+};
+
/* Configure L2 Node CGD (indirect 0x0414)
* This indirect command allows configuring a congestion domain for given L2
* node TEIDs in the scheduler topology.
@@ -2976,6 +2992,7 @@ struct ice_aq_desc {
struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
struct ice_aqc_query_port_ets port_ets;
struct ice_aqc_rl_profile rl_profile;
+ struct ice_aqc_node_attr node_attr;
struct ice_aqc_nvm nvm;
struct ice_aqc_nvm_cfg nvm_cfg;
struct ice_aqc_nvm_checksum nvm_checksum;
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 71b5677f43..6f938d71a1 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -839,6 +839,33 @@ void ice_sched_cleanup_all(struct ice_hw *hw)
hw->max_cgds = 0;
}
+/**
+ * ice_aq_cfg_node_attr - configure nodes' per-cone flattening attributes
+ * @hw: pointer to the HW struct
+ * @num_nodes: the number of nodes whose attributes to configure
+ * @buf: pointer to buffer
+ * @buf_size: buffer size in bytes
+ * @cd: pointer to command details structure or NULL
+ *
+ * Configure Node Attributes (0x0417)
+ */
+enum ice_status
+ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes,
+struct ice_aqc_node_attr_elem *buf, u16 buf_size,
+struct ice_sq_cd *cd)
+{
+ struct ice_aqc_node_attr *cmd;
+ struct ice_aq_desc desc;
+
+ cmd = &desc.params.node_attr;
+ ice_fill_dflt_direct_cmd_desc(&desc,
+ ice_aqc_opc_cfg_node_attr);
+ desc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);
+
+ cmd->num_entries = CPU_TO_LE16(num_nodes);
+ return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
+}
+
/**
* ice_aq_cfg_l2_node_cgd - configures L2 node to CGD mapping
* @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index c9f3f79eff..6b12a0688a 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -78,6 +78,10 @@ ice_aq_query_rl_profile(struct ice_hw *hw, u16 num_profiles,
struct ice_aqc_rl_profile_elem *buf, u16 buf_size,
struct ice_sq_cd *cd);
enum ice_status
+ice_aq_cfg_node_attr(struct ice_hw *hw, u16 num_nodes,
+struct ice_aqc_node_attr_elem *buf, u16 buf_size,
+struct ice_sq_cd *cd);
+enum ice_status
ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes,
struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size,
struct ice_sq_cd *cd);
--
2.31.1
[PATCH 34/70] net/ice/base: fix null pointer dereference during
Sometimes, during the shutdown process, an PCIe unrecoverable error
occurs. This leads to the following NULL pointer dereference error
while clearing hardware tables:
The patch fixes this bug by checking every table pointer against
NULL before reference it, as some of them probably have been cleared
in advance.
Fixes: 969890d505b1 ("net/ice/base: enable clearing of HW tables")
Cc: sta...@dpdk.org
Signed-off-by: Roman Storozhenko
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_pipe.c | 332 +++
1 file changed, 179 insertions(+), 153 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c
b/drivers/net/ice/base/ice_flex_pipe.c
index aea0d97b9d..2d95ce4d74 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -2144,6 +2144,129 @@ void ice_init_flow_profs(struct ice_hw *hw, u8 blk_idx)
INIT_LIST_HEAD(&hw->fl_profs[blk_idx]);
}
+/**
+ * ice_init_hw_tbls - init hardware table memory
+ * @hw: pointer to the hardware structure
+ */
+enum ice_status ice_init_hw_tbls(struct ice_hw *hw)
+{
+ u8 i;
+
+ ice_init_lock(&hw->rss_locks);
+ INIT_LIST_HEAD(&hw->rss_list_head);
+ if (!hw->dcf_enabled)
+ ice_init_all_prof_masks(hw);
+ for (i = 0; i < ICE_BLK_COUNT; i++) {
+ struct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir;
+ struct ice_prof_tcam *prof = &hw->blk[i].prof;
+ struct ice_xlt1 *xlt1 = &hw->blk[i].xlt1;
+ struct ice_xlt2 *xlt2 = &hw->blk[i].xlt2;
+ struct ice_es *es = &hw->blk[i].es;
+ u16 j;
+
+ if (hw->blk[i].is_list_init)
+ continue;
+
+ ice_init_flow_profs(hw, i);
+ ice_init_lock(&es->prof_map_lock);
+ INIT_LIST_HEAD(&es->prof_map);
+ hw->blk[i].is_list_init = true;
+
+ hw->blk[i].overwrite = blk_sizes[i].overwrite;
+ es->reverse = blk_sizes[i].reverse;
+
+ xlt1->sid = ice_blk_sids[i][ICE_SID_XLT1_OFF];
+ xlt1->count = blk_sizes[i].xlt1;
+
+ xlt1->ptypes = (struct ice_ptg_ptype *)
+ ice_calloc(hw, xlt1->count, sizeof(*xlt1->ptypes));
+
+ if (!xlt1->ptypes)
+ goto err;
+
+ xlt1->ptg_tbl = (struct ice_ptg_entry *)
+ ice_calloc(hw, ICE_MAX_PTGS, sizeof(*xlt1->ptg_tbl));
+
+ if (!xlt1->ptg_tbl)
+ goto err;
+
+ xlt1->t = (u8 *)ice_calloc(hw, xlt1->count, sizeof(*xlt1->t));
+ if (!xlt1->t)
+ goto err;
+
+ xlt2->sid = ice_blk_sids[i][ICE_SID_XLT2_OFF];
+ xlt2->count = blk_sizes[i].xlt2;
+
+ xlt2->vsis = (struct ice_vsig_vsi *)
+ ice_calloc(hw, xlt2->count, sizeof(*xlt2->vsis));
+
+ if (!xlt2->vsis)
+ goto err;
+
+ xlt2->vsig_tbl = (struct ice_vsig_entry *)
+ ice_calloc(hw, xlt2->count, sizeof(*xlt2->vsig_tbl));
+ if (!xlt2->vsig_tbl)
+ goto err;
+
+ for (j = 0; j < xlt2->count; j++)
+ INIT_LIST_HEAD(&xlt2->vsig_tbl[j].prop_lst);
+
+ xlt2->t = (u16 *)ice_calloc(hw, xlt2->count, sizeof(*xlt2->t));
+ if (!xlt2->t)
+ goto err;
+
+ prof->sid = ice_blk_sids[i][ICE_SID_PR_OFF];
+ prof->count = blk_sizes[i].prof_tcam;
+ prof->max_prof_id = blk_sizes[i].prof_id;
+ prof->cdid_bits = blk_sizes[i].prof_cdid_bits;
+ prof->t = (struct ice_prof_tcam_entry *)
+ ice_calloc(hw, prof->count, sizeof(*prof->t));
+
+ if (!prof->t)
+ goto err;
+
+ prof_redir->sid = ice_blk_sids[i][ICE_SID_PR_REDIR_OFF];
+ prof_redir->count = blk_sizes[i].prof_redir;
+ prof_redir->t = (u8 *)ice_calloc(hw, prof_redir->count,
+sizeof(*prof_redir->t));
+
+ if (!prof_redir->t)
+ goto err;
+
+ es->sid = ice_blk_sids[i][ICE_SID_ES_OFF];
+ es->count = blk_sizes[i].es;
+ es->fvw = blk_sizes[i].fvw;
+ es->t = (struct ice_fv_word *)
+ ice_calloc(hw, (u32)(es->count * es->fvw),
+ sizeof(*es->t));
+ if (!es->t)
+ goto err;
+
+ es->ref_count = (u16 *)
+ ice_calloc(hw, es->count, sizeof(*es->ref_count));
+
+ if (!es->ref_count)
+ goto err;
+
+ es->written = (u8 *)
+ ice_calloc(hw, es->count, sizeof(*es->written));
+
+ if (!es->written)
[PATCH 35/70] net/ice/base: refine default VSI config
Refine API ice_cfg_dflt_vsi and add new API
ice_check_if_dflt_vsi.
Signed-off-by: Michal Wilczynski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 95 +--
drivers/net/ice/base/ice_switch.h | 2 +
2 files changed, 53 insertions(+), 44 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index b8e733f539..124b4fad1b 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -2382,6 +2382,9 @@ static void ice_get_recp_to_prof_map(struct ice_hw *hw)
}
}
+static bool
+ice_vsi_uses_fltr(struct ice_fltr_mgmt_list_entry *fm_entry, u16 vsi_handle);
+
/**
* ice_init_def_sw_recp - initialize the recipe book keeping tables
* @hw: pointer to the HW struct
@@ -5496,24 +5499,19 @@ enum ice_status
ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,
u8 direction)
{
- struct ice_aqc_sw_rules_elem *s_rule;
+ struct ice_fltr_list_entry f_list_entry;
+ struct ice_sw_recipe *recp_list;
struct ice_fltr_info f_info;
struct ice_hw *hw = pi->hw;
- enum ice_adminq_opc opcode;
enum ice_status status;
- u16 s_rule_size;
+ u8 lport = pi->lport;
u16 hw_vsi_id;
+ recp_list = &pi->hw->switch_info->recp_list[ICE_SW_LKUP_DFLT];
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
- hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
-
- s_rule_size = set ? ICE_SW_RULE_RX_TX_ETH_HDR_SIZE :
- ICE_SW_RULE_RX_TX_NO_HDR_SIZE;
- s_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);
- if (!s_rule)
- return ICE_ERR_NO_MEMORY;
+ hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
ice_memset(&f_info, 0, sizeof(f_info), ICE_NONDMA_MEM);
@@ -5521,54 +5519,63 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16
vsi_handle, bool set,
f_info.flag = direction;
f_info.fltr_act = ICE_FWD_TO_VSI;
f_info.fwd_id.hw_vsi_id = hw_vsi_id;
+ f_info.vsi_handle = vsi_handle;
if (f_info.flag & ICE_FLTR_RX) {
f_info.src = pi->lport;
f_info.src_id = ICE_SRC_ID_LPORT;
- if (!set)
- f_info.fltr_rule_id =
- pi->dflt_rx_vsi_rule_id;
} else if (f_info.flag & ICE_FLTR_TX) {
f_info.src_id = ICE_SRC_ID_VSI;
f_info.src = hw_vsi_id;
- if (!set)
- f_info.fltr_rule_id =
- pi->dflt_tx_vsi_rule_id;
}
+ f_list_entry.fltr_info = f_info;
if (set)
- opcode = ice_aqc_opc_add_sw_rules;
+ status = ice_add_rule_internal(hw, recp_list, lport,
+ &f_list_entry);
else
- opcode = ice_aqc_opc_remove_sw_rules;
-
- ice_fill_sw_rule(hw, &f_info, s_rule, opcode);
-
- status = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opcode, NULL);
- if (status || !(f_info.flag & ICE_FLTR_TX_RX))
- goto out;
- if (set) {
- u16 index = LE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);
-
- if (f_info.flag & ICE_FLTR_TX) {
- pi->dflt_tx_vsi_num = hw_vsi_id;
- pi->dflt_tx_vsi_rule_id = index;
- } else if (f_info.flag & ICE_FLTR_RX) {
- pi->dflt_rx_vsi_num = hw_vsi_id;
- pi->dflt_rx_vsi_rule_id = index;
- }
- } else {
- if (f_info.flag & ICE_FLTR_TX) {
- pi->dflt_tx_vsi_num = ICE_DFLT_VSI_INVAL;
- pi->dflt_tx_vsi_rule_id = ICE_INVAL_ACT;
- } else if (f_info.flag & ICE_FLTR_RX) {
- pi->dflt_rx_vsi_num = ICE_DFLT_VSI_INVAL;
- pi->dflt_rx_vsi_rule_id = ICE_INVAL_ACT;
+ status = ice_remove_rule_internal(hw, recp_list,
+ &f_list_entry);
+
+ return status;
+}
+
+/**
+ * ice_check_if_dflt_vsi - check if VSI is default VSI
+ * @pi: pointer to the port_info structure
+ * @vsi_handle: vsi handle to check for in filter list
+ * @rule_exists: indicates if there are any VSI's in the rule list
+ *
+ * checks if the VSI is in a default VSI list, and also indicates
+ * if the default VSI list is empty
+ */
+bool ice_check_if_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle,
+ bool *rule_exists)
+{
+ struct ice_fltr_mgmt_list_entry *fm_entry;
+ struct LIST_HEAD_TYPE *rule_head;
+ struct ice_sw_recipe *recp_list;
+ struct ice_lock *rule_lock;
+ bool ret = false;
+ recp_list = &pi->hw->switch_info->recp_list[ICE_SW_LKUP_DFLT];
+ rule_lock = &recp_list->filt_rule_lock;
+ rule_head = &recp_list->f
[PATCH 36/70] net/ice/base: ice-shared: fix add mac rule
Fix ice_add_mac_rule function by not overriding action value
with vsi id. It's possible to add MAC based switch filters
with action other than FWD_TO_VSI.
In current implementation fwd_id member of filter config
structure was always overwritten with hw vsi index, regardless
of action type.
Fix it, by setting hw vsi index only for FWD_TO_VSI action
filter and leave it as it is in case of other actions.
Fixes: 3ee1b0159ee5 ("net/ice/base: support adding MAC rules on specific port")
Cc: d...@stable.org
Signed-off-by: Grzegorz Nitka
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index 124b4fad1b..edcfa89bcb 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -4858,7 +4858,8 @@ ice_add_mac_rule(struct ice_hw *hw, struct LIST_HEAD_TYPE
*m_list,
if (!ice_is_vsi_valid(hw, vsi_handle))
return ICE_ERR_PARAM;
hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);
- m_list_itr->fltr_info.fwd_id.hw_vsi_id = hw_vsi_id;
+ if (m_list_itr->fltr_info.fltr_act == ICE_FWD_TO_VSI)
+ m_list_itr->fltr_info.fwd_id.hw_vsi_id = hw_vsi_id;
/* update the src in case it is VSI num */
if (m_list_itr->fltr_info.src_id != ICE_SRC_ID_VSI)
return ICE_ERR_PARAM;
--
2.31.1
[PATCH 37/70] net/ice/base: support Tx topo config
Complete the Tx topo config implementation.
Signed-off-by: Victor Raj
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 3 +++
drivers/net/ice/base/ice_common.c | 3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 9f84ffca67..8efbb137da 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -127,6 +127,9 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
+#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
+#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
+#define ICE_AQC_CAPS_ROCEV2_LAG0x0092
u8 major_ver;
u8 minor_ver;
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index cb06fdf42b..db78bf4152 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2453,6 +2453,9 @@ ice_parse_common_caps(struct ice_hw *hw, struct
ice_hw_common_caps *caps,
caps->ext_topo_dev_img_prog_en[index]);
break;
}
+ case ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE:
+ caps->tx_sched_topo_comp_mode_en = (number == 1);
+ break;
default:
/* Not one of the recognized common capabilities */
found = false;
--
2.31.1
[PATCH 38/70] net/ice/base: adjust the VSI/Aggregator layers
Adjust the VSI/Aggregator layers based on the number of logical
layers supported by the FW. Currently the VSI and aggregator layers are
fixed based on the 9 layer scheduler tree layout. Due to performance
reasons the number of layers of the scheduler tree is changing from
9 to 5. It requires a readjument of these VSI/Aggregator layer
values.
Signed-off-by: Victor Raj
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_sched.c | 34
drivers/net/ice/base/ice_sched.h | 3 +++
2 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index 6f938d71a1..4d31e96fd0 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -1130,12 +1130,11 @@ static u8 ice_sched_get_vsi_layer(struct ice_hw *hw)
* 5 or less sw_entry_point_layer
*/
/* calculate the VSI layer based on number of layers. */
- if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {
- u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;
-
- if (layer > hw->sw_entry_point_layer)
- return layer;
- }
+ if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)
+ return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;
+ else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS)
+ /* qgroup and VSI layers are same */
+ return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;
return hw->sw_entry_point_layer;
}
@@ -1152,12 +1151,8 @@ static u8 ice_sched_get_agg_layer(struct ice_hw *hw)
* 7 or less sw_entry_point_layer
*/
/* calculate the aggregator layer based on number of layers. */
- if (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) {
- u8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;
-
- if (layer > hw->sw_entry_point_layer)
- return layer;
- }
+ if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)
+ return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;
return hw->sw_entry_point_layer;
}
@@ -1542,10 +1537,11 @@ ice_sched_get_free_qparent(struct ice_port_info *pi,
u16 vsi_handle, u8 tc,
{
struct ice_sched_node *vsi_node, *qgrp_node;
struct ice_vsi_ctx *vsi_ctx;
+ u8 qgrp_layer, vsi_layer;
u16 max_children;
- u8 qgrp_layer;
qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);
+ vsi_layer = ice_sched_get_vsi_layer(pi->hw);
max_children = pi->hw->max_children[qgrp_layer];
vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
@@ -1556,6 +1552,12 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16
vsi_handle, u8 tc,
if (!vsi_node)
return NULL;
+ /* If the queue group and vsi layer are same then queues
+* are all attached directly to VSI
+*/
+ if (qgrp_layer == vsi_layer)
+ return vsi_node;
+
/* get the first queue group node from VSI sub-tree */
qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer);
while (qgrp_node) {
@@ -4060,7 +4062,7 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum
ice_rl_type rl_type,
enum ice_status status;
u8 profile_type;
- if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ if (!hw || layer_num >= hw->num_tx_sched_layers)
return NULL;
switch (rl_type) {
case ICE_MIN_BW:
@@ -4076,8 +4078,6 @@ ice_sched_add_rl_profile(struct ice_hw *hw, enum
ice_rl_type rl_type,
return NULL;
}
- if (!hw)
- return NULL;
LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],
ice_aqc_rl_profile_info, list_entry)
if ((rl_prof_elem->profile.flags & ICE_AQC_RL_PROFILE_TYPE_M) ==
@@ -4279,7 +4279,7 @@ ice_sched_rm_rl_profile(struct ice_hw *hw, u8 layer_num,
u8 profile_type,
struct ice_aqc_rl_profile_info *rl_prof_elem;
enum ice_status status = ICE_SUCCESS;
- if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)
+ if (!hw || layer_num >= hw->num_tx_sched_layers)
return ICE_ERR_PARAM;
/* Check the existing list for RL profile */
LIST_FOR_EACH_ENTRY(rl_prof_elem, &hw->rl_prof_list[layer_num],
diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h
index 6b12a0688a..53a68dbe51 100644
--- a/drivers/net/ice/base/ice_sched.h
+++ b/drivers/net/ice/base/ice_sched.h
@@ -7,6 +7,9 @@
#include "ice_common.h"
+#define ICE_SCHED_5_LAYERS 5
+#define ICE_SCHED_9_LAYERS 9
+
#define ICE_QGRP_LAYER_OFFSET 2
#define ICE_VSI_LAYER_OFFSET 4
#define ICE_AGG_LAYER_OFFSET 6
--
2.31.1
[PATCH 39/70] net/ice/base: add data typecasting to match sizes
Adding typecast to variables to avoid compiler warnings generated if
variables of a particular data type are assigned to ones of a
smaller data type. For example assigning an unsigned 16 bit integer
to an 8 bit integer could trigger data loss warnings or errors.
Signed-off-by: Vignesh Sridhar
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_acl_ctrl.c | 34 +--
drivers/net/ice/base/ice_adminq_cmd.h | 4 ++--
drivers/net/ice/base/ice_common.c | 13 +-
drivers/net/ice/base/ice_dcb.c| 8 +++
drivers/net/ice/base/ice_flex_pipe.c | 2 +-
drivers/net/ice/base/ice_flow.c | 26 ++--
drivers/net/ice/base/ice_nvm.c| 2 +-
drivers/net/ice/base/ice_sched.c | 5 ++--
drivers/net/ice/base/ice_switch.c | 12 +-
9 files changed, 52 insertions(+), 54 deletions(-)
diff --git a/drivers/net/ice/base/ice_acl_ctrl.c
b/drivers/net/ice/base/ice_acl_ctrl.c
index 27aa6b62d4..2dd08e326e 100644
--- a/drivers/net/ice/base/ice_acl_ctrl.c
+++ b/drivers/net/ice/base/ice_acl_ctrl.c
@@ -6,10 +6,10 @@
#include "ice_flow.h"
/* Determine the TCAM index of entry 'e' within the ACL table */
-#define ICE_ACL_TBL_TCAM_IDX(e) ((e) / ICE_AQC_ACL_TCAM_DEPTH)
+#define ICE_ACL_TBL_TCAM_IDX(e) ((u8)((e) / ICE_AQC_ACL_TCAM_DEPTH))
/* Determine the entry index within the TCAM */
-#define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((e) % ICE_AQC_ACL_TCAM_DEPTH)
+#define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((u16)((e) % ICE_AQC_ACL_TCAM_DEPTH))
#define ICE_ACL_SCEN_ENTRY_INVAL 0x
@@ -251,10 +251,8 @@ ice_acl_assign_act_mems_to_tcam(struct ice_acl_tbl *tbl,
u8 cur_tcam,
*/
static void ice_acl_divide_act_mems_to_tcams(struct ice_acl_tbl *tbl)
{
- u16 num_cscd, stack_level, stack_idx, min_act_mem;
- u8 tcam_idx = tbl->first_tcam;
- u16 max_idx_to_get_extra;
- u8 mem_idx = 0;
+ u16 num_cscd, stack_level, stack_idx, max_idx_to_get_extra;
+ u8 min_act_mem, tcam_idx = tbl->first_tcam, mem_idx = 0;
/* Determine number of stacked TCAMs */
stack_level = DIVIDE_AND_ROUND_UP(tbl->info.depth,
@@ -326,7 +324,8 @@ ice_acl_create_tbl(struct ice_hw *hw, struct
ice_acl_tbl_params *params)
depth = ICE_ALIGN(params->depth, ICE_ACL_ENTRY_ALLOC_UNIT);
if (params->entry_act_pairs < width / ICE_AQC_ACL_KEY_WIDTH_BYTES) {
- params->entry_act_pairs = width / ICE_AQC_ACL_KEY_WIDTH_BYTES;
+ params->entry_act_pairs =
+ (u8)(width / ICE_AQC_ACL_KEY_WIDTH_BYTES);
if (params->entry_act_pairs > ICE_AQC_TBL_MAX_ACTION_PAIRS)
params->entry_act_pairs = ICE_AQC_TBL_MAX_ACTION_PAIRS;
@@ -587,7 +586,7 @@ ice_acl_fill_tcam_select(struct ice_aqc_acl_scen *scen_buf,
*/
for (j = 0; j < ICE_AQC_ACL_KEY_WIDTH_BYTES; j++) {
/* PKT DIR uses the 1st location of Byte Selection Base: + 1 */
- u8 val = ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx;
+ u8 val = (u8)(ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx);
if (tcam_idx_in_cascade == cascade_cnt - 1) {
if (j == ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM)
@@ -793,7 +792,7 @@ ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16
num_entries,
/* set the START_SET bit at the beginning of the stack */
scen_buf.tcam_cfg[k].start_cmp_set |= ICE_AQC_ACL_ALLOC_SCE_START_SET;
while (k <= last_tcam) {
- u8 last_tcam_idx_cascade = cascade_cnt + k - 1;
+ u16 last_tcam_idx_cascade = cascade_cnt + k - 1;
/* set start_cmp for the first cascaded TCAM */
scen_buf.tcam_cfg[k].start_cmp_set |=
@@ -972,10 +971,10 @@ ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen
*scen,
enum ice_acl_entry_prio prio, u8 *keys, u8 *inverts,
struct ice_acl_act_entry *acts, u8 acts_cnt, u16 *entry_idx)
{
- u8 i, entry_tcam, num_cscd, offset;
struct ice_aqc_acl_data buf;
+ u8 entry_tcam, offset;
+ u16 i, num_cscd, idx;
enum ice_status status = ICE_SUCCESS;
- u16 idx;
if (!scen)
return ICE_ERR_DOES_NOT_EXIST;
@@ -1005,7 +1004,7 @@ ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen
*scen,
* be programmed first; the TCAM entry of the leftmost TCAM
* should be programmed last.
*/
- offset = num_cscd - i - 1;
+ offset = (u8)(num_cscd - i - 1);
ice_memcpy(&buf.entry_key.val,
&keys[offset * sizeof(buf.entry_key.val)],
sizeof(buf.entry_key.val), ICE_NONDMA_TO_NONDMA);
@@ -1049,10 +1048,9 @@ ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen
*scen,
struct ice_acl_act_entry *acts, u8 acts_cnt,
u16 entry_idx)
{
- u8 entry_tcam, num_cscd, i, actx_idx = 0;
+
[PATCH 40/70] net/ice/base: add helper function to check if device is E823
Add a simple function checking if the device is E823-L or E823-C
based.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 25 +
drivers/net/ice/base/ice_common.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index f8a3017df8..c90ae20c43 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -231,6 +231,31 @@ bool ice_is_e810t(struct ice_hw *hw)
return false;
}
+/**
+ * ice_is_e823
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E823-L or E823-C based, false if not.
+ */
+bool ice_is_e823(struct ice_hw *hw)
+{
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E823L_BACKPLANE:
+ case ICE_DEV_ID_E823L_SFP:
+ case ICE_DEV_ID_E823L_10G_BASE_T:
+ case ICE_DEV_ID_E823L_1GBE:
+ case ICE_DEV_ID_E823L_QSFP:
+ case ICE_DEV_ID_E823C_BACKPLANE:
+ case ICE_DEV_ID_E823C_QSFP:
+ case ICE_DEV_ID_E823C_SFP:
+ case ICE_DEV_ID_E823C_10G_BASE_T:
+ case ICE_DEV_ID_E823C_SGMII:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
diff --git a/drivers/net/ice/base/ice_common.h
b/drivers/net/ice/base/ice_common.h
index 1051cc1176..b15cf240f9 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -259,6 +259,7 @@ void ice_print_rollback_msg(struct ice_hw *hw);
bool ice_is_generic_mac(struct ice_hw *hw);
bool ice_is_e810(struct ice_hw *hw);
bool ice_is_e810t(struct ice_hw *hw);
+bool ice_is_e823(struct ice_hw *hw);
enum ice_status
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
struct ice_aqc_txsched_elem_data *buf);
--
2.31.1
[PATCH 41/70] net/ice/base: add low latency Tx timestamp read
E810 products can support low latency Tx timestamp register read.
Add a check for the device capability and use the new method if
supported.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 7 ++-
drivers/net/ice/base/ice_ptp_hw.c | 95 +++
drivers/net/ice/base/ice_ptp_hw.h | 12 +++-
drivers/net/ice/base/ice_type.h | 2 +
4 files changed, 101 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index c90ae20c43..2014f8361d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2757,7 +2757,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct
ice_hw_dev_caps *dev_p,
info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);
info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);
- info->ena_ports = logical_id;
+ info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);
+
info->tmr_own_map = phys_id;
ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 = %u\n",
@@ -2774,8 +2775,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct
ice_hw_dev_caps *dev_p,
info->tmr1_owned);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr1_ena = %u\n",
info->tmr1_ena);
- ice_debug(hw, ICE_DBG_INIT, "dev caps: ieee_1588 ena_ports = %u\n",
- info->ena_ports);
+ ice_debug(hw, ICE_DBG_INIT, "dev caps: ts_ll_read = %u\n",
+ info->ts_ll_read);
ice_debug(hw, ICE_DBG_INIT, "dev caps: tmr_own_map = %u\n",
info->tmr_own_map);
}
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 7ed420be8e..712b7dedfb 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4142,38 +4142,111 @@ ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr,
u32 val)
}
/**
- * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
+ * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
+ * @hw: pointer to the HW struct
+ * @idx: the timestamp index to read
+ * @hi: 8 bit timestamp high value
+ * @lo: 32 bit timestamp low value
+ *
+ * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
+ * timestamp block of the external PHY on the E810 device using the low latency
+ * timestamp read.
+ */
+static enum ice_status
+ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)
+{
+ u8 i;
+
+ /* Write TS index to read to the PF register so the FW can read it */
+ wr32(hw, PF_SB_ATQBAL, TS_LL_READ_TS_IDX(idx));
+
+ /* Read the register repeatedly until the FW provides us the TS */
+ for (i = TS_LL_READ_RETRIES; i > 0; i--) {
+ u32 val = rd32(hw, PF_SB_ATQBAL);
+
+ /* When the bit is cleared, the TS is ready in the register */
+ if (!(val & TS_LL_READ_TS)) {
+ /* High 8 bit value of the TS is on the bits 16:23 */
+ *hi = (u8)(val >> TS_LL_READ_TS_HIGH_S);
+
+ /* Read the low 32 bit value and set the TS valid bit */
+ *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;
+ return ICE_SUCCESS;
+ }
+
+ ice_usec_delay(10, false);
+ }
+
+ /* FW failed to provide the TS in time */
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low
latency read\n");
+ return ICE_ERR_NOT_READY;
+}
+
+/**
+ * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the
sbq
* @hw: pointer to the HW struct
* @lport: the lport to read from
* @idx: the timestamp index to read
- * @tstamp: on return, the 40bit timestamp value
+ * @hi: 8 bit timestamp high value
+ * @lo: 32 bit timestamp low value
*
- * Read a 40bit timestamp value out of the timestamp block of the external PHY
- * on the E810 device.
+ * Read a 8bit timestamp high value and 32 bit timestamp low value out of the
+ * timestamp block of the external PHY on the E810 device using sideband queue.
*/
static enum ice_status
-ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)
+ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,
+u32 *lo)
{
+ u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
+ u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
enum ice_status status;
- u32 lo_addr, hi_addr, lo, hi;
-
- lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);
- hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);
+ u32 lo_val, hi_val;
- status = ice_read_phy_reg_e810(hw, lo_addr, &lo);
+ status = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);
if (status) {
ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp
register, s
[PATCH 42/70] net/ice/base: fix double VLAN error in promisc mode
Avoid enabling or disabling vlan 0 when trying to set promiscuous
vlan mode if double vlan mode is enabled. This fix is needed
because the driver tries to add the vlan 0 filter twice (once for
inner and once for outer) when double VLAN mode is enabled. The
filter program is rejected by the firmware when double vlan is
enabled, because the promiscuous filter only needs to be set once.
This issue was missed in the initial implementation of double vlan
mode.
Fixes: 60ff6f5ce2d8 ("net/ice/base: consolidate VF promiscuous mode")
Cc: sta...@dpdk.org
Signed-off-by: Grzegorz Siwik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index a8f83f62ff..6a94e3fde9 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6263,6 +6263,13 @@ _ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16
vsi_handle, u8 promisc_mask,
LIST_FOR_EACH_ENTRY(list_itr, &vsi_list_head, ice_fltr_list_entry,
list_entry) {
+ /* Avoid enabling or disabling vlan zero twice when in double
+* vlan mode
+*/
+ if (ice_is_dvm_ena(hw) &&
+ list_itr->fltr_info.l_data.vlan.tpid == 0)
+ continue;
+
vlan_id = list_itr->fltr_info.l_data.vlan.vlan_id;
if (rm_vlan_promisc)
status = _ice_clear_vsi_promisc(hw, vsi_handle,
--
2.31.1
[PATCH 43/70] net/ice/base: move functions
Move function ice_ptp_set_vernier_wl and ice_ptp_src_cmd to align with
kernel driver.
Signed-off-by: Jacob Keller
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 130 +++---
1 file changed, 66 insertions(+), 64 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 712b7dedfb..dfb9d08224 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -381,6 +381,47 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)
return ICE_SUCCESS;
}
+/**
+ * ice_ptp_src_cmd - Prepare source timer for a timer command
+ * @hw: pointer to HW structure
+ * @cmd: Timer command
+ *
+ * Prepare the source timer for an upcoming timer sync command.
+ */
+void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
+{
+ u32 cmd_val;
+ u8 tmr_idx;
+
+ tmr_idx = ice_get_ptp_src_clock_index(hw);
+ cmd_val = tmr_idx << SEL_CPK_SRC;
+
+ switch (cmd) {
+ case ICE_PTP_INIT_TIME:
+ cmd_val |= GLTSYN_CMD_INIT_TIME;
+ break;
+ case ICE_PTP_INIT_INCVAL:
+ cmd_val |= GLTSYN_CMD_INIT_INCVAL;
+ break;
+ case ICE_PTP_ADJ_TIME:
+ cmd_val |= GLTSYN_CMD_ADJ_TIME;
+ break;
+ case ICE_PTP_ADJ_TIME_AT_TIME:
+ cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
+ break;
+ case ICE_PTP_READ_TIME:
+ cmd_val |= GLTSYN_CMD_READ_TIME;
+ break;
+ case ICE_PTP_NOP:
+ break;
+ default:
+ ice_warn(hw, "Unknown timer command %u\n", cmd);
+ return;
+ }
+
+ wr32(hw, GLTSYN_CMD, cmd_val);
+}
+
/**
* ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
* @hw: pointer to HW struct
@@ -2365,6 +2406,31 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8
idx)
return ICE_SUCCESS;
}
+/**
+ * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
+ * @hw: pointer to the HW struct
+ *
+ * Set the window length used for the vernier port calibration process.
+ */
+enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)
+{
+ u8 port;
+
+ for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
+ enum ice_status status;
+
+ status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
+ PTP_VERNIER_WL, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier
window length for port %u, status %d\n",
+ port, status);
+ return status;
+ }
+ }
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization
* @hw: pointer to HW struct
@@ -2817,31 +2883,6 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
* port.
*/
-/**
- * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
- * @hw: pointer to the HW struct
- *
- * Set the window length used for the vernier port calibration process.
- */
-enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)
-{
- u8 port;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- enum ice_status status;
-
- status = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,
- PTP_VERNIER_WL, true);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier
window length for port %u, status %d\n",
- port, status);
- return status;
- }
- }
-
- return ICE_SUCCESS;
-}
-
/**
* ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode
* @hw: pointer to HW struct
@@ -4829,45 +4870,6 @@ void ice_ptp_unlock(struct ice_hw *hw)
wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
}
-/**
- * ice_ptp_src_cmd - Prepare source timer for a timer command
- * @hw: pointer to HW structure
- * @cmd: Timer command
- *
- * Prepare the source timer for an upcoming timer sync command.
- */
-void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)
-{
- u32 cmd_val;
- u8 tmr_idx;
-
- tmr_idx = ice_get_ptp_src_clock_index(hw);
- cmd_val = tmr_idx << SEL_CPK_SRC;
-
- switch (cmd) {
- case ICE_PTP_INIT_TIME:
- cmd_val |= GLTSYN_CMD_INIT_TIME;
- break;
- case ICE_PTP_INIT_INCVAL:
- cmd_val |= GLTSYN_CMD_INIT_INCVAL;
- break;
- case ICE_PTP_ADJ_TIME:
- cmd_val |= GLTSYN_CMD_ADJ_TIME;
- break;
- case ICE_PTP_ADJ_TIME_AT_TIME:
- cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;
- break;
- case ICE_PTP_READ_TIME:
- cmd_val
[PATCH 44/70] net/ice/base: complete support for Tx balancing
Add module ID and struct necessary to read and save Tx Scheduler
Topology Tree User Selection data from PFA TLV.
Signed-off-by: Lukasz Czapnik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 7f9bdd3cb0..ebffee1b93 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1936,6 +1936,15 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */
#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
+#define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B
+
+struct ice_aqc_nvm_tx_topo_user_sel {
+ __le16 length;
+ u8 data;
+#define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)
+ u8 reserved;
+};
+
/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {
u8 cmd_flags;
--
2.31.1
[PATCH 45/70] net/ice/base: update definitions for AQ internal debug dump
Add defines for Queue Mng and Full CSR Space in debug
dump internal data. This defines are used in Lanconf for
debug dump. Added QV_SUPPORT macro in ifdef for ACL.
Signed-off-by: Dawid Zielinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index ebffee1b93..6a1b8a40f2 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2841,17 +2841,19 @@ struct ice_aqc_event_lan_overflow {
/* Debug Dump Internal Data (indirect 0xFF08) */
struct ice_aqc_debug_dump_internals {
u8 cluster_id;
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL1
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED2
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL1
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED2
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
/* EMP_DRAM only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
/* AUX_REGS only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB7
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P8
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB7
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P8
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21
u8 reserved;
__le16 table_id; /* Used only for non-memory clusters */
__le32 idx; /* In table entries for tables, in bytes for memory */
--
2.31.1
[PATCH 46/70] net/ice/base: update macros of L2TPv2 ptype value
Because the macros of L2TPv2 packet type value were changed in
ice_ppp-o-l2tpv2-o-udp-1.3.4.0.pkg. So update the macros of L2TPv2
packet type value and the bitmaps of packet types for relevant
protocol header to match the new DDP package.
Signed-off-by: Jie Wang
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_type.h | 60 ++--
drivers/net/ice/base/ice_flow.c | 34
2 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_type.h
b/drivers/net/ice/base/ice_flex_type.h
index d45653b637..2855d67831 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -174,36 +174,36 @@ struct ice_fv {
#define ICE_MAC_IPV6_PFCP_SESSION 354
#define ICE_MAC_IPV4_L2TPV3360
#define ICE_MAC_IPV6_L2TPV3361
-#define ICE_MAC_IPV4_L2TPV2_CONTROL392
-#define ICE_MAC_IPV6_L2TPV2_CONTROL393
-#define ICE_MAC_IPV4_L2TPV2394
-#define ICE_MAC_IPV6_L2TPV2395
-#define ICE_MAC_IPV4_PPPOL2TPV2396
-#define ICE_MAC_IPV6_PPPOL2TPV2397
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_FRAG 398
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_PAY 399
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_UDP_PAY 400
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_TCP 401
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_SCTP 402
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_ICMP 403
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_FRAG 404
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_PAY 405
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_UDP_PAY 406
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_TCP 407
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_SCTP 408
-#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_ICMPV6409
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_FRAG 410
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_PAY 411
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_UDP_PAY 412
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_TCP 413
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_SCTP 414
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_ICMP 415
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_FRAG 416
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_PAY 417
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_UDP_PAY 418
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_TCP 419
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_SCTP 420
-#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_ICMPV6421
+#define ICE_MAC_IPV4_L2TPV2_CONTROL396
+#define ICE_MAC_IPV6_L2TPV2_CONTROL397
+#define ICE_MAC_IPV4_L2TPV2398
+#define ICE_MAC_IPV6_L2TPV2399
+#define ICE_MAC_IPV4_PPPOL2TPV2400
+#define ICE_MAC_IPV6_PPPOL2TPV2401
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_FRAG 402
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_PAY 403
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_UDP_PAY 404
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_TCP 405
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_SCTP 406
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV4_ICMP 407
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_FRAG 408
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_PAY 409
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_UDP_PAY 410
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_TCP 411
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_SCTP 412
+#define ICE_MAC_IPV4_PPPOL2TPV2_IPV6_ICMPV6413
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_FRAG 414
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_PAY 415
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_UDP_PAY 416
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_TCP 417
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_SCTP 418
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV4_ICMP 419
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_FRAG 420
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_PAY 421
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_UDP_PAY 422
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_TCP 423
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_SCTP 424
+#define ICE_MAC_IPV6_PPPOL2TPV2_IPV6_ICMPV6425
#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_FRAG 450
#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_PAY451
#define MAC_IPV4_TUN_IPV4_GTPU_IPV4_UDP_PAY452
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 80e7a447c3..bdc51ca9d2 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -239,7 +239,7 @@ static const u32 ice_ptypes_mac_ofos[] = {
0xFDC00846, 0xBFBF7F7E, 0xF70001DF, 0xFEFDFDFB,
0x077E, 0x03FF, 0x, 0x,
0x0040, 0x03FFF000, 0xFFE0, 0x00100707,
- 0xFF00, 0x003F, 0x, 0x,
+ 0xF000, 0x03FF, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
0x, 0x, 0x, 0x,
@@ -265,7 +265,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = {
0x1D80, 0xBFBF7800,
[PATCH 47/70] net/ice/base: refine header file include
The ice_switch.h and ice_fdir.h headers include ice_common.h. They are both themselves included in ice_common.h. This causes a circular dependency ordering. Signed-off-by: Jacob Keller Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_switch.c | 1 + drivers/net/ice/base/ice_switch.h | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_fdir.h b/drivers/net/ice/base/ice_fdir.h index 008636072a..d57b1daecd 100644 --- a/drivers/net/ice/base/ice_fdir.h +++ b/drivers/net/ice/base/ice_fdir.h @@ -5,7 +5,7 @@ #ifndef _ICE_FDIR_H_ #define _ICE_FDIR_H_ -#include "ice_common.h" +#include "ice_type.h" #define ICE_FDIR_IP_PROTOCOLS #define ICE_IP_PROTO_TCP 6 diff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c index 6a94e3fde9..6863696d9d 100644 --- a/drivers/net/ice/base/ice_switch.c +++ b/drivers/net/ice/base/ice_switch.c @@ -2,6 +2,7 @@ * Copyright(c) 2001-2021 Intel Corporation */ +#include "ice_common.h" #include "ice_switch.h" #include "ice_flex_type.h" #include "ice_flow.h" diff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h index ad1397ba5a..3c05a1531f 100644 --- a/drivers/net/ice/base/ice_switch.h +++ b/drivers/net/ice/base/ice_switch.h @@ -5,7 +5,7 @@ #ifndef _ICE_SWITCH_H_ #define _ICE_SWITCH_H_ -#include "ice_common.h" +#include "ice_type.h" #include "ice_protocol_type.h" #define ICE_SW_CFG_MAX_BUF_LEN 2048 -- 2.31.1
[PATCH 48/70] net/ice/base: ignore already exist error
Ignore ERR_ALREADY_EXISTS error when setting promiscuous mode.
This fix is needed because the driver could set promiscuous mode
when it still has not cleared properly.
Promiscuous mode could be set only once, so setting it second
time will be rejected.
Fixes: 60ff6f5ce2d8 ("net/ice/base: consolidate VF promiscuous mode")
Cc: sta...@dpdk.org
Signed-off-by: Grzegorz Siwik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index 6863696d9d..91a959e10f 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -6280,7 +6280,7 @@ _ice_set_vlan_vsi_promisc(struct ice_hw *hw, u16
vsi_handle, u8 promisc_mask,
status = _ice_set_vsi_promisc(hw, vsi_handle,
promisc_mask, vlan_id,
lport, sw);
- if (status)
+ if (status && status != ICE_ERR_ALREADY_EXISTS)
break;
}
--
2.31.1
[PATCH 49/70] net/ice/base: clean up with no lookups
The add rule functionality works fine with a NULL lookups parameter.
However when running the undefined behavior sanitizer it noticed that
the function could trigger a memcpy from a NULL target.
Fix the code to handle NULL lkups and a zero lkups_cnt variable more
explicitly, and clean up the test to just directly pass a NULL value
instead of allocating a stack variable assigned to NULL and passing
that as a pointer.
Signed-off-by: Jesse Brandeburg
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index 91a959e10f..01441211ff 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -9002,9 +9002,13 @@ ice_add_adv_rule(struct ice_hw *hw, struct
ice_adv_lkup_elem *lkups,
goto err_ice_add_adv_rule;
}
- adv_fltr->lkups = (struct ice_adv_lkup_elem *)
- ice_memdup(hw, lkups, lkups_cnt * sizeof(*lkups),
- ICE_NONDMA_TO_NONDMA);
+ if (lkups_cnt) {
+ adv_fltr->lkups = (struct ice_adv_lkup_elem *)
+ ice_memdup(hw, lkups, lkups_cnt * sizeof(*lkups),
+ ICE_NONDMA_TO_NONDMA);
+ } else {
+ adv_fltr->lkups = NULL;
+ }
if (!adv_fltr->lkups && !prof_rule) {
status = ICE_ERR_NO_MEMORY;
goto err_ice_add_adv_rule;
--
2.31.1
[PATCH 50/70] net/ice/base: add support for Auto FEC with FEC disabled
The default Link Establishment State Machine (LESM) behavior does
not allow the use of FEC disable mode if the media does not support
FEC disabled. However users may want to override this behavior.
Add support for settng Auto FEC with FEC disabled.
Signed-off-by: Paul Greenwalt
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 2 +
drivers/net/ice/base/ice_common.c | 129 +++---
drivers/net/ice/base/ice_common.h | 2 +
drivers/net/ice/base/ice_type.h | 12 ++-
4 files changed, 111 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 6a1b8a40f2..dc72d70dfe 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1439,6 +1439,7 @@ struct ice_aqc_get_phy_caps_data {
#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
+#define ICE_AQC_PHY_FEC_DISBIT(5)
#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
#define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
@@ -3275,6 +3276,7 @@ enum ice_adminq_opc {
ice_aqc_opc_lldp_set_local_mib = 0x0A08,
ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
ice_aqc_opc_lldp_filter_ctrl= 0x0A0A,
+ ice_execute_pending_lldp_mib= 0x0A0B,
/* RSS commands */
ice_aqc_opc_set_rss_key = 0x0B02,
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index 2014f8361d..9a41f36fed 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3494,8 +3494,12 @@ enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
*/
enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
{
- if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
- return ICE_FEC_AUTO;
+ if (caps & ICE_AQC_PHY_EN_AUTO_FEC) {
+ if (fec_options & ICE_AQC_PHY_FEC_DIS)
+ return ICE_FEC_DIS_AUTO;
+ else
+ return ICE_FEC_AUTO;
+ }
if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
@@ -3788,6 +3792,12 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct
ice_aqc_set_phy_cfg_data *cfg,
/* Clear all FEC option bits. */
cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
break;
+ case ICE_FEC_DIS_AUTO:
+ /* Set No FEC and auto FEC */
+ if (!ice_fw_supports_fec_dis_auto(hw))
+ return ICE_ERR_NOT_SUPPORTED;
+ cfg->link_fec_opt |= ICE_AQC_PHY_FEC_DIS;
+ /* fall-through */
case ICE_FEC_AUTO:
/* AND auto FEC bit, and all caps bits. */
cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
@@ -5750,26 +5760,70 @@ ice_aq_get_gpio(struct ice_hw *hw, u16
gpio_ctrl_handle, u8 pin_idx,
}
/**
- * ice_fw_supports_link_override
+ * ice_is_fw_api_min_ver
* @hw: pointer to the hardware structure
+ * @maj: major version
+ * @min: minor version
+ * @patch: patch version
*
- * Checks if the firmware supports link override
+ * Checks if the firmware is minimum version
*/
-bool ice_fw_supports_link_override(struct ice_hw *hw)
+static bool ice_is_fw_api_min_ver(struct ice_hw *hw, u8 maj, u8 min, u8 patch)
{
- if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
- if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
+ if (hw->api_maj_ver == maj) {
+ if (hw->api_min_ver > min)
+ return true;
+ if (hw->api_min_ver == min && hw->api_patch >= patch)
return true;
- if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
- hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
+ } else if (hw->api_maj_ver > maj) {
+ return true;
+ }
+
+ return false;
+}
+
+/**
+ * ice_is_fw_min_ver
+ * @hw: pointer to the hardware structure
+ * @branch: branch version
+ * @maj: major version
+ * @min: minor version
+ * @patch: patch version
+ *
+ * Checks if the firmware is minimum version
+ */
+static bool ice_is_fw_min_ver(struct ice_hw *hw, u8 branch, u8 maj, u8 min,
+ u8 patch)
+{
+ if (hw->fw_branch == branch) {
+ if (hw->fw_maj_ver > maj)
return true;
- } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
+ if (hw->fw_maj_ver == maj) {
+ if (hw->fw_min_ver > min)
+ return true;
+ if (hw->fw_min_ver == min && h
[PATCH 51/70] net/ice/base: update PHY type high max index
ICE_PHY_TYPE_HIGH_MAX_INDEX should be the maximum index value and
not the length/number of ICE_PHY_TYPE_HIGH.
Signed-off-by: Paul Greenwalt
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index dc72d70dfe..e1a6847157 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1398,7 +1398,7 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACCBIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX5
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX4
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
--
2.31.1
[PATCH 52/70] net/ice/base: clean the main timer command register
Clean the main timer command register after use to avoid residual command execution, such as re-initialization of the main timer. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c index dfb9d08224..f5ebf5f328 100644 --- a/drivers/net/ice/base/ice_ptp_hw.c +++ b/drivers/net/ice/base/ice_ptp_hw.c @@ -3751,6 +3751,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time, /* Issue the sync to start the ICE_PTP_READ_TIME capture */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); /* Read the captured PHC time from the shadow time registers */ zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); @@ -3825,6 +3826,7 @@ static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) /* Issue the sync to activate the time adjustment */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); /* Re-capture the timer values to flush the command registers and * verify that the time was properly adjusted. @@ -3920,6 +3922,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) u64 incval; u8 tmr_idx; + ice_ptp_clean_cmd(hw); tmr_idx = ice_get_ptp_src_clock_index(hw); status = ice_stop_phy_timer_e822(hw, port, false); @@ -4913,6 +4916,7 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq) * commands synchronously */ ice_ptp_exec_tmr_cmd(hw); + ice_ptp_clean_cmd(hw); return ICE_SUCCESS; } -- 2.31.1
[PATCH 53/70] net/ice/base: add support for custom WPC and LGB NICs
There are few custom Westport Channel (WPC) and Logan Beach (LGB)
network interface cards (NICs) - add their subdevice IDs to be
able to distinguish them.
Signed-off-by: Michal Michalik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 15 ---
drivers/net/ice/base/ice_devids.h | 4
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index 9a41f36fed..c3024dd0b7 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -216,13 +216,22 @@ bool ice_is_e810t(struct ice_hw *hw)
{
switch (hw->device_id) {
case ICE_DEV_ID_E810C_SFP:
- if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
- hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ switch (hw->subsystem_device_id) {
+ case ICE_SUBDEV_ID_E810T:
+ case ICE_SUBDEV_ID_E810T2:
+ case ICE_SUBDEV_ID_E810T3:
+ case ICE_SUBDEV_ID_E810T4:
+ case ICE_SUBDEV_ID_E810T5:
return true;
+ }
break;
case ICE_DEV_ID_E810C_QSFP:
- if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ switch (hw->subsystem_device_id) {
+ case ICE_SUBDEV_ID_E810T2:
+ case ICE_SUBDEV_ID_E810T5:
+ case ICE_SUBDEV_ID_E810T6:
return true;
+ }
break;
default:
break;
diff --git a/drivers/net/ice/base/ice_devids.h
b/drivers/net/ice/base/ice_devids.h
index 96dbb92e0a..937111844d 100644
--- a/drivers/net/ice/base/ice_devids.h
+++ b/drivers/net/ice/base/ice_devids.h
@@ -23,6 +23,10 @@
#define ICE_DEV_ID_E810C_SFP 0x1593
#define ICE_SUBDEV_ID_E810T0x000E
#define ICE_SUBDEV_ID_E810T2 0x000F
+#define ICE_SUBDEV_ID_E810T3 0x02E9
+#define ICE_SUBDEV_ID_E810T4 0x02EA
+#define ICE_SUBDEV_ID_E810T5 0x0010
+#define ICE_SUBDEV_ID_E810T6 0x0012
/* Intel(R) Ethernet Controller E810-XXV for backplane */
#define ICE_DEV_ID_E810_XXV_BACKPLANE 0x1599
/* Intel(R) Ethernet Controller E810-XXV for QSFP */
--
2.31.1
[PATCH 54/70] net/ice/base: add generic MAC with 3K signature segment
Define new type id ICE_MAC_GENERIC_3k in ice_mac_type enum, to
distinguish devices which use RSA-3K/SHA-384 segment signature type.
Use 3k signinig type for E824S device.
Signed-off-by: Grzegorz Nitka
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index c3024dd0b7..44592d20bf 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -192,7 +192,8 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
*/
bool ice_is_generic_mac(struct ice_hw *hw)
{
- return hw->mac_type == ICE_MAC_GENERIC;
+ return (hw->mac_type == ICE_MAC_GENERIC ||
+ hw->mac_type == ICE_MAC_GENERIC_3K);
}
/**
--
2.31.1
[PATCH 55/70] net/ice/base: enable RSS support for L2TPv2 session ID
Add L2TPv2 session ID field support for RSS.
Enable L2TPv2 non-tunneled packet types for UDP protocol header
bitmaps.
Signed-off-by: Jie Wang
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flow.c | 12
drivers/net/ice/base/ice_flow.h | 14 ++
2 files changed, 26 insertions(+)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index bdc51ca9d2..182fac08a9 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -38,6 +38,8 @@
#define ICE_FLOW_FLD_SZ_NAT_T_ESP_SPI 4
#define ICE_FLOW_FLD_SZ_VXLAN_VNI 4
#define ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID2
+#define ICE_FLOW_FLD_SZ_L2TPV2_SESS_ID 2
+#define ICE_FLOW_FLD_SZ_L2TPV2_LEN_SESS_ID 2
/* Describe properties of a protocol header field */
struct ice_flow_field_info {
@@ -229,6 +231,14 @@ struct ice_flow_field_info
ice_flds_info[ICE_FLOW_FIELD_IDX_MAX] = {
/* ICE_FLOW_FIELD_IDX_UDP_ECPRI_TP0_PC_ID */
ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0, 12,
ICE_FLOW_FLD_SZ_ECPRI_TP0_PC_ID),
+ /* L2TPV2 */
+ /* ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_L2TPV2, 12,
+ ICE_FLOW_FLD_SZ_L2TPV2_SESS_ID),
+ /* L2TPV2_LEN */
+ /* ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID */
+ ICE_FLOW_FLD_INFO(ICE_FLOW_SEG_HDR_L2TPV2, 14,
+ ICE_FLOW_FLD_SZ_L2TPV2_LEN_SESS_ID),
};
/* Bitmaps indicating relevant packet types for a particular protocol header
@@ -1492,6 +1502,8 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct
ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_GTPU_EH_QFI:
case ICE_FLOW_FIELD_IDX_GTPU_UP_QFI:
case ICE_FLOW_FIELD_IDX_GTPU_DWN_QFI:
+ case ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID:
+ case ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID:
/* GTP is accessed through UDP OF protocol */
prot_id = ICE_PROT_UDP_OF;
break;
diff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h
index f941ce4333..5729392362 100644
--- a/drivers/net/ice/base/ice_flow.h
+++ b/drivers/net/ice/base/ice_flow.h
@@ -149,6 +149,16 @@
#define ICE_FLOW_HASH_NAT_T_ESP_IPV6_SPI \
(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_NAT_T_ESP_SPI)
+#define ICE_FLOW_HASH_L2TPV2_SESS_ID \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID))
+#define ICE_FLOW_HASH_L2TPV2_SESS_ID_ETH \
+ (ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_L2TPV2_SESS_ID)
+
+#define ICE_FLOW_HASH_L2TPV2_LEN_SESS_ID \
+ (BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID))
+#define ICE_FLOW_HASH_L2TPV2_LEN_SESS_ID_ETH \
+ (ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_L2TPV2_LEN_SESS_ID)
+
#define ICE_FLOW_FIELD_IPV4_SRC_OFFSET 12
#define ICE_FLOW_FIELD_IPV4_DST_OFFSET 16
#define ICE_FLOW_FIELD_IPV6_SRC_OFFSET 8
@@ -297,6 +307,10 @@ enum ice_flow_field {
ICE_FLOW_FIELD_IDX_ECPRI_TP0_PC_ID,
/* UDP_ECPRI_TP0 */
ICE_FLOW_FIELD_IDX_UDP_ECPRI_TP0_PC_ID,
+ /* L2TPV2 SESSION ID*/
+ ICE_FLOW_FIELD_IDX_L2TPV2_SESS_ID,
+ /* L2TPV2_LEN SESSION ID */
+ ICE_FLOW_FIELD_IDX_L2TPV2_LEN_SESS_ID,
/* The total number of enums must not exceed 64 */
ICE_FLOW_FIELD_IDX_MAX
};
--
2.31.1
[PATCH 56/70] net/ice/base: enable FDIR support for L2TPv2
Add L2TPv2(include PPP over L2TPv2) support for FDIR.
And add support PPPoL2TPv2oUDP with inner IPV4/IPV6/UDP/TCP for
FDIR.
The supported L2TPv2 packets are defined as below:
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_CONTROL
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4_UDP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV4_TCP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6_UDP
ICE_FLTR_PTYPE_NONF_IPV4_L2TPV2_PPP_IPV6_TCP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_CONTROL
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4_UDP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV4_TCP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6_UDP
ICE_FLTR_PTYPE_NONF_IPV6_L2TPV2_PPP_IPV6_TCP
Signed-off-by: Jie Wang
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_fdir.c | 711 +++-
drivers/net/ice/base/ice_fdir.h | 19 +
drivers/net/ice/base/ice_type.h | 27 ++
3 files changed, 755 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_fdir.c b/drivers/net/ice/base/ice_fdir.c
index 6bbab0c843..a554379075 100644
--- a/drivers/net/ice/base/ice_fdir.c
+++ b/drivers/net/ice/base/ice_fdir.c
@@ -1827,6 +1827,289 @@ static const u8 ice_fdir_tcp6_gtpu4_eh_up_gre6_pkt[] = {
0x00, 0x00, 0x00, 0x00,
};
+/* IPV4 L2TPV2 control */
+static const u8 ice_fdir_ipv4_l2tpv2_ctrl_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xc2, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x14,
+ 0x2c, 0x6b, 0xc8, 0x02, 0x00, 0x0c, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 L2TPV2 */
+static const u8 ice_fdir_ipv4_l2tpv2_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x28, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xc2, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x14,
+ 0x2c, 0x6b, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00,
+};
+
+/* IPV4 PPPOL2TPV2 */
+static const u8 ice_fdir_ipv4_l2tpv2_ppp_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x26, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xc4, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x12,
+ 0xf5, 0x77, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x03, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 PPPOL2TPV2 IPV4 */
+static const u8 ice_fdir_ipv4_l2tpv2_ppp4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xb0, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x26,
+ 0xf5, 0x2e, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x03, 0x00, 0x21, 0x45, 0x00, 0x00, 0x14,
+ 0x00, 0x01, 0x00, 0x00, 0x40, 0x00, 0x7c, 0xe7,
+ 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01,
+ 0x00, 0x00,
+};
+
+/* IPV4 PPPOL2TPV2 IPV4 UDP */
+static const u8 ice_fdir_udp4_l2tpv2_ppp4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x42, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0xa8, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x2e,
+ 0xf3, 0x3a, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x03, 0x00, 0x21, 0x45, 0x00, 0x00, 0x1c,
+ 0x00, 0x01, 0x00, 0x00, 0x40, 0x11, 0x7c, 0xce,
+ 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01,
+ 0x00, 0x35, 0x00, 0x35, 0x00, 0x08, 0x01, 0x72,
+ 0x00, 0x00,
+};
+
+/* IPV4 PPPOL2TPV2 IPV4 TCP */
+static const u8 ice_fdir_tcp4_l2tpv2_ppp4_pkt[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x45, 0x00,
+ 0x00, 0x4e, 0x00, 0x01, 0x00, 0x00, 0x40, 0x11,
+ 0x7c, 0x9c, 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00,
+ 0x00, 0x01, 0x06, 0xa5, 0x06, 0xa5, 0x00, 0x3a,
+ 0xf3, 0x23, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x03, 0x00, 0x21, 0x45, 0x00, 0x00, 0x28,
+ 0x00, 0x01, 0x00, 0x00, 0x40, 0x06, 0x7c, 0xcd,
+ 0x7f, 0x00, 0x00, 0x01, 0x7f, 0x00, 0x00, 0x01,
+ 0x00, 0x14, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x50, 0x02, 0x20, 0x00,
+ 0x91, 0x7c, 0x00, 0x00, 0x00, 0x00,
+};
+
+/* IPV4 PPPOL2TPV2 IPV6 */
+static const u8 ice_fdir_ipv6_l2tpv2_ppp4_pkt[] = {
+ 0x00, 0x00, 0x00, 0
[PATCH 57/70] net/ice/base: add GRE Tap tunnel type
Added new tunnel type to support NvGRE
Signed-off-by: Michal Swiatkowski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_type.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ice/base/ice_flex_type.h
b/drivers/net/ice/base/ice_flex_type.h
index 2855d67831..070d2aeb1e 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -441,6 +441,7 @@ struct ice_prof_redir_section {
enum ice_tunnel_type {
TNL_VXLAN = 0,
TNL_GENEVE,
+ TNL_GRETAP,
TNL_ECPRI,
TNL_GTP,
TNL_LAST = 0xFF,
--
2.31.1
[PATCH 58/70] net/ice/base: fix wrong inputset of GTPoGRE packet
For GTPoGRE, When setting the prot_id of prot, it should be
set to second inner.
Fixes: 34a0e7c44f2b ("net/ice/base: improve flow director masking")
Cc: sta...@dpdk.org
Signed-off-by: Kevin Liu
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flow.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 182fac08a9..33e97ec333 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -1404,7 +1404,10 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct
ice_flow_prof_params *params,
case ICE_FLOW_FIELD_IDX_IPV4_TTL:
case ICE_FLOW_FIELD_IDX_IPV4_PROT:
prot_id = seg == 0 ? ICE_PROT_IPV4_OF_OR_S : ICE_PROT_IPV4_IL;
-
+ if (params->prof->segs[0].hdrs & ICE_FLOW_SEG_HDR_GRE &&
+ params->prof->segs[1].hdrs & ICE_FLOW_SEG_HDR_GTPU &&
+ seg == 1)
+ prot_id = ICE_PROT_IPV4_IL_IL;
/* TTL and PROT share the same extraction seq. entry.
* Each is considered a sibling to the other in terms of sharing
* the same extraction sequence entry.
@@ -1432,7 +1435,10 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct
ice_flow_prof_params *params,
prot_id = seg == 0 ?
ICE_PROT_IPV6_NEXT_PROTO :
ICE_PROT_IPV6_IL;
-
+ if (params->prof->segs[0].hdrs & ICE_FLOW_SEG_HDR_GRE &&
+ params->prof->segs[1].hdrs & ICE_FLOW_SEG_HDR_GTPU &&
+ seg == 1)
+ prot_id = ICE_PROT_IPV6_IL_IL;
/* TTL and PROT share the same extraction seq. entry.
* Each is considered a sibling to the other in terms of sharing
* the same extraction sequence entry.
--
2.31.1
[PATCH 59/70] net/ice/base: add unload flag for control queue shutdown
Admin queue command for shutdown AQ contains flag to indicate
driver unload. However the flag is always set in driver, even
for the resets. It causes Firmware to consider driver as unloaded
once the PF reset is triggered on all ports of device. Firmware then
restores default configuration of some features like Tx Balancing,
which is not expected behavior.
This patch added an additional function parameter to indicate
driver unload.
Signed-off-by: Piotr Gardocki
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.h | 2 +-
drivers/net/ice/base/ice_controlq.c | 19 +++
drivers/net/ice/ice_ethdev.c| 2 +-
3 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.h
b/drivers/net/ice/base/ice_common.h
index ac13a979b1..9101ae11af 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -32,7 +32,7 @@ enum ice_status ice_reset(struct ice_hw *hw, enum
ice_reset_req req);
enum ice_status ice_create_all_ctrlq(struct ice_hw *hw);
enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
-void ice_shutdown_all_ctrlq(struct ice_hw *hw);
+void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading);
void ice_destroy_all_ctrlq(struct ice_hw *hw);
enum ice_status
ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
diff --git a/drivers/net/ice/base/ice_controlq.c
b/drivers/net/ice/base/ice_controlq.c
index d83d0d76d0..8a6311572c 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -661,10 +661,12 @@ static bool ice_is_sbq_supported(struct ice_hw *hw)
* ice_shutdown_ctrlq - shutdown routine for any control queue
* @hw: pointer to the hardware structure
* @q_type: specific Control queue type
+ * @unloading: is the driver unloading itself
*
* NOTE: this function does not destroy the control queue locks.
*/
-static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
+static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type,
+ bool unloading)
{
struct ice_ctl_q_info *cq;
@@ -674,7 +676,7 @@ static void ice_shutdown_ctrlq(struct ice_hw *hw, enum
ice_ctl_q q_type)
case ICE_CTL_Q_ADMIN:
cq = &hw->adminq;
if (ice_check_sq_alive(hw, cq))
- ice_aq_q_shutdown(hw, true);
+ ice_aq_q_shutdown(hw, unloading);
break;
case ICE_CTL_Q_SB:
cq = &hw->sbq;
@@ -693,21 +695,22 @@ static void ice_shutdown_ctrlq(struct ice_hw *hw, enum
ice_ctl_q q_type)
/**
* ice_shutdown_all_ctrlq - shutdown routine for all control queues
* @hw: pointer to the hardware structure
+ * @unloading: is the driver unloading itself
*
* NOTE: this function does not destroy the control queue locks. The driver
* may call this at runtime to shutdown and later restart control queues, such
* as in response to a reset event.
*/
-void ice_shutdown_all_ctrlq(struct ice_hw *hw)
+void ice_shutdown_all_ctrlq(struct ice_hw *hw, bool unloading)
{
ice_debug(hw, ICE_DBG_TRACE, "%s\n", __func__);
/* Shutdown FW admin queue */
- ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
+ ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN, unloading);
/* Shutdown PHY Sideband */
if (ice_is_sbq_supported(hw))
- ice_shutdown_ctrlq(hw, ICE_CTL_Q_SB);
+ ice_shutdown_ctrlq(hw, ICE_CTL_Q_SB, unloading);
/* Shutdown PF-VF Mailbox */
- ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);
+ ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX, unloading);
}
/**
@@ -741,7 +744,7 @@ enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)
break;
ice_debug(hw, ICE_DBG_AQ_MSG, "Retry Admin Queue init due to FW
critical error\n");
- ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
+ ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN, true);
ice_msec_delay(ICE_CTL_Q_ADMIN_INIT_MSEC, true);
} while (retry++ < ICE_CTL_Q_ADMIN_INIT_TIMEOUT);
@@ -822,7 +825,7 @@ static void ice_destroy_ctrlq_locks(struct ice_ctl_q_info
*cq)
void ice_destroy_all_ctrlq(struct ice_hw *hw)
{
/* shut down all the control queues first */
- ice_shutdown_all_ctrlq(hw);
+ ice_shutdown_all_ctrlq(hw, true);
ice_destroy_ctrlq_locks(&hw->adminq);
if (ice_is_sbq_supported(hw))
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 551be3566f..172eb2fbdb 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2521,7 +2521,7 @@ ice_dev_close(struct rte_eth_dev *dev)
ice_free_hw_tbls(hw);
rte_free(hw->port_info);
hw->port_info = NULL;
- ice_shutdown_all_ctrlq(hw);
+ ice_shutdown_all_ctrlq(hw, true);
rte_free(pf->proto_xtr);
pf->proto_xtr = NULL;
--
2.31.1
[PATCH 60/70] net/ice/base: update comment for overloaded GCO bit
The bit that is overloaded is bit 11 in the flex descriptor,
updating the comment to have the right one reflected.
Signed-off-by: Alice Michael
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_lan_tx_rx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h
b/drivers/net/ice/base/ice_lan_tx_rx.h
index 2b6f039dcb..ba1b9a66d8 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -544,7 +544,7 @@ struct ice_32b_rx_flex_desc_nic_raw_csum {
__le32 rss_hash;
/* Qword 2 */
- __le16 status_error1; /* bit 6 Raw CSUM present */
+ __le16 status_error1; /* bit 11 Raw CSUM present */
u8 flexi_flags2;
u8 ts_low;
__le16 l2tag2_1st;
--
2.31.1
[PATCH 61/70] net/ice/base: complete pending LLDP MIB
Completed structure ice_aqc_lldp_get_mib.
Added 'Pending Event Enable' bit.
Signed-off-by: Tsotne Chakhvadze
Signed-off-by: Karen Sornek
Signed-off-by: Anatolii Gerasymenko
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 20 ++--
drivers/net/ice/base/ice_dcb.c| 3 +++
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index e1a6847157..dc3c3269d4 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1998,14 +1998,25 @@ struct ice_aqc_lldp_get_mib {
#define ICE_AQ_LLDP_TX_ACTIVE 0
#define ICE_AQ_LLDP_TX_SUSPENDED 1
#define ICE_AQ_LLDP_TX_FLUSHED 3
+/* DCBX mode */
+#define ICE_AQ_LLDP_DCBX_S 6
+#define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S)
+#define ICE_AQ_LLDP_DCBX_NA0
+#define ICE_AQ_LLDP_DCBX_IEEE 1
+#define ICE_AQ_LLDP_DCBX_CEE 2
/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
* and in the LLDP MIB Change Event (0x0A01). They are valid for the
* Get LLDP MIB (0x0A00) response only.
*/
- u8 reserved1;
+ u8 state;
+#define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0
+#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \
+ (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S)
+#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED0
+#define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1
__le16 local_len;
__le16 remote_len;
- u8 reserved2[2];
+ u8 reserved[2];
__le32 addr_high;
__le32 addr_low;
};
@@ -2016,6 +2027,11 @@ struct ice_aqc_lldp_set_mib_change {
u8 command;
#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
+#define ICE_AQ_LLDP_MIB_PENDING_S 1
+#define ICE_AQ_LLDP_MIB_PENDING_M \
+ (0x1 << ICE_AQ_LLDP_MIB_PENDING_S)
+#define ICE_AQ_LLDP_MIB_PENDING_DISABLE0
+#define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1
u8 reserved[15];
};
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 7a850e62f4..d511a5f5ec 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -74,6 +74,9 @@ ice_aq_cfg_lldp_mib_change(struct ice_hw *hw, bool ena_update,
if (!ena_update)
cmd->command |= ICE_AQ_LLDP_MIB_UPDATE_DIS;
+ else
+ cmd->command |= ICE_AQ_LLDP_MIB_PENDING_ENABLE <<
+ ICE_AQ_LLDP_MIB_PENDING_S;
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}
--
2.31.1
[PATCH 62/70] net/ice/base: add function to parse DCBX config
LLDP MIB Change Event (opcode 0x0A01) already contains MIB, which
has been changed. Add ice_dcb_process_lldp_set_mib_change() function,
which will set local/remote DCBX config from LLDP MIB Change Event's
buffer.
This function will be used in a base driver handler for LLDP MIB
Chang Event.
Signed-off-by: Anatolii Gerasymenko
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_dcb.c | 37 ++
drivers/net/ice/base/ice_dcb.h | 2 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index d511a5f5ec..30494e868e 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -970,6 +970,43 @@ enum ice_status ice_get_dcb_cfg(struct ice_port_info *pi)
return ret;
}
+/**
+ * ice_get_dcb_cfg_from_mib_change
+ * @pi: port information structure
+ * @event: pointer to the admin queue receive event
+ *
+ * Set DCB configuration from received MIB Change event
+ */
+void ice_get_dcb_cfg_from_mib_change(struct ice_port_info *pi,
+struct ice_rq_event_info *event)
+{
+ struct ice_dcbx_cfg *dcbx_cfg = &pi->qos_cfg.local_dcbx_cfg;
+ struct ice_aqc_lldp_get_mib *mib;
+ u8 change_type, dcbx_mode;
+
+ mib = (struct ice_aqc_lldp_get_mib *)&event->desc.params.raw;
+
+ change_type = mib->type & ICE_AQ_LLDP_MIB_TYPE_M;
+ if (change_type == ICE_AQ_LLDP_MIB_REMOTE)
+ dcbx_cfg = &pi->qos_cfg.remote_dcbx_cfg;
+
+ dcbx_mode = ((mib->type & ICE_AQ_LLDP_DCBX_M) >>
+ICE_AQ_LLDP_DCBX_S);
+
+ switch (dcbx_mode) {
+ case ICE_AQ_LLDP_DCBX_IEEE:
+ dcbx_cfg->dcbx_mode = ICE_DCBX_MODE_IEEE;
+ ice_lldp_to_dcb_cfg(event->msg_buf, dcbx_cfg);
+ break;
+
+ case ICE_AQ_LLDP_DCBX_CEE:
+ pi->qos_cfg.desired_dcbx_cfg = pi->qos_cfg.local_dcbx_cfg;
+ ice_cee_to_dcb_cfg((struct ice_aqc_get_cee_dcb_cfg_resp *)
+ event->msg_buf, pi);
+ break;
+ }
+}
+
/**
* ice_init_dcb
* @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index 24c8da2dc8..7e1e4d0297 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -205,6 +205,8 @@ ice_aq_get_dcb_cfg(struct ice_hw *hw, u8 mib_type, u8
bridgetype,
struct ice_dcbx_cfg *dcbcfg);
enum ice_status ice_get_dcb_cfg(struct ice_port_info *pi);
enum ice_status ice_set_dcb_cfg(struct ice_port_info *pi);
+void ice_get_dcb_cfg_from_mib_change(struct ice_port_info *pi,
+struct ice_rq_event_info *event);
enum ice_status ice_init_dcb(struct ice_hw *hw, bool enable_mib_change);
void ice_dcb_cfg_to_lldp(u8 *lldpmib, u16 *miblen, struct ice_dcbx_cfg
*dcbcfg);
enum ice_status
--
2.31.1
[PATCH 63/70] net/ice/base: handle default VSI lookup type
ICE_SW_LKUP_DFLT is handled in ice_update_vsi_list_rule and
ice_aq_alloc_free_vsi_list.
Signed-off-by: Lukasz Kupczak
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index 01441211ff..afc0fff84b 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -3181,6 +3181,7 @@ ice_aq_alloc_free_vsi_list(struct ice_hw *hw, u16
*vsi_list_id,
lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||
lkup_type == ICE_SW_LKUP_PROMISC ||
lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||
+ lkup_type == ICE_SW_LKUP_DFLT ||
lkup_type == ICE_SW_LKUP_LAST) {
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_VSI_LIST_REP);
} else if (lkup_type == ICE_SW_LKUP_VLAN) {
@@ -4095,6 +4096,7 @@ ice_update_vsi_list_rule(struct ice_hw *hw, u16
*vsi_handle_arr, u16 num_vsi,
lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||
lkup_type == ICE_SW_LKUP_PROMISC ||
lkup_type == ICE_SW_LKUP_PROMISC_VLAN ||
+ lkup_type == ICE_SW_LKUP_DFLT ||
lkup_type == ICE_SW_LKUP_LAST)
rule_type = remove ? ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR :
ICE_AQC_SW_RULES_T_VSI_LIST_SET;
--
2.31.1
[PATCH 64/70] net/ice/base: convert 1588 structs to use bitfields
Use bitfields in 1588 structs so they don't waste too much space.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_type.h | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 6d0adf0dd1..043dae7781 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -662,12 +662,12 @@ struct ice_ts_func_info {
/* Function specific info */
enum ice_time_ref_freq time_ref;
u8 clk_freq;
- u8 clk_src;
- u8 tmr_index_assoc;
- u8 ena;
- u8 tmr_index_owned;
- u8 src_tmr_owned;
- u8 tmr_ena;
+ u8 clk_src : 1;
+ u8 tmr_index_assoc : 1;
+ u8 ena : 1;
+ u8 tmr_index_owned : 1;
+ u8 src_tmr_owned : 1;
+ u8 tmr_ena : 1;
};
/* Device specific definitions */
@@ -685,14 +685,14 @@ struct ice_ts_dev_info {
/* Device specific info */
u32 ena_ports;
u32 tmr_own_map;
- u32 tmr0_owner;
- u32 tmr1_owner;
- u8 tmr0_owned;
- u8 tmr1_owned;
- u8 ena;
- u8 tmr0_ena;
- u8 tmr1_ena;
- u8 ts_ll_read;
+ u8 tmr0_owner;
+ u8 tmr1_owner;
+ u8 tmr0_owned : 1;
+ u8 tmr1_owned : 1;
+ u8 ena : 1;
+ u8 tmr0_ena : 1;
+ u8 tmr1_ena : 1;
+ u8 ts_ll_read : 1;
};
/* Function specific capabilities */
--
2.31.1
[PATCH 65/70] net/ice/base: remove unnecessary fields
Remove unnecessary fields in data structure for 1588 and QoS
func capabilities.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 5 ++---
drivers/net/ice/base/ice_switch.c | 2 --
drivers/net/ice/base/ice_type.h | 6 --
3 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index 44592d20bf..3d4e05f2b0 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -2579,7 +2579,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct
ice_hw_func_caps *func_p,
* related information.
*/
ice_debug(hw, ICE_DBG_INIT, "1588 func caps: unknown clock
frequency %u\n",
- info->clk_freq);
+ clk_freq);
info->time_ref = ICE_TIME_REF_FREQ_25_000;
}
@@ -2594,7 +2594,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct
ice_hw_func_caps *func_p,
ice_debug(hw, ICE_DBG_INIT, "func caps: tmr_index_assoc = %u\n",
info->tmr_index_assoc);
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_freq = %u\n",
- info->clk_freq);
+ clk_freq);
ice_debug(hw, ICE_DBG_INIT, "func caps: clk_src = %u\n",
info->clk_src);
}
@@ -2752,7 +2752,6 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct
ice_hw_dev_caps *dev_p,
struct ice_aqc_list_caps_elem *cap)
{
struct ice_ts_dev_info *info = &dev_p->ts_dev_info;
- u32 logical_id = LE32_TO_CPU(cap->logical_id);
u32 phys_id = LE32_TO_CPU(cap->phys_id);
u32 number = LE32_TO_CPU(cap->number);
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index afc0fff84b..ac045790ad 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -3546,8 +3546,6 @@ ice_init_port_info(struct ice_port_info *pi, u16
vsi_port_num, u8 type,
pi->sw_id = swid;
pi->pf_vf_num = pf_vf_num;
pi->is_vf = is_vf;
- pi->dflt_tx_vsi_num = ICE_DFLT_VSI_INVAL;
- pi->dflt_rx_vsi_num = ICE_DFLT_VSI_INVAL;
break;
default:
ice_debug(pi->hw, ICE_DBG_SW, "incorrect VSI/port type
received\n");
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 043dae7781..fc5b4b4c5c 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -661,7 +661,6 @@ enum ice_clk_src {
struct ice_ts_func_info {
/* Function specific info */
enum ice_time_ref_freq time_ref;
- u8 clk_freq;
u8 clk_src : 1;
u8 tmr_index_assoc : 1;
u8 ena : 1;
@@ -683,7 +682,6 @@ struct ice_ts_func_info {
struct ice_ts_dev_info {
/* Device specific info */
- u32 ena_ports;
u32 tmr_own_map;
u8 tmr0_owner;
u8 tmr1_owner;
@@ -1098,10 +1096,6 @@ struct ice_port_info {
#define ICE_SCHED_PORT_STATE_READY 0x1
u8 lport;
#define ICE_LPORT_MASK 0xff
- u16 dflt_tx_vsi_rule_id;
- u16 dflt_tx_vsi_num;
- u16 dflt_rx_vsi_rule_id;
- u16 dflt_rx_vsi_num;
struct ice_fc_info fc;
struct ice_mac_info mac;
struct ice_phy_info phy;
--
2.31.1
[PATCH 66/70] net/ice/base: add GTP tunnel
Added GTP tunnel type and also re-order the code to align with
kernel driver.
Signed-off-by: Marcin Szycik
Signed-off-by: Michal Swiatkowski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flex_type.h | 10 +++---
drivers/net/ice/base/ice_protocol_type.h | 2 +-
drivers/net/ice/base/ice_switch.c| 8
drivers/net/ice/base/ice_switch.h| 3 +++
4 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ice/base/ice_flex_type.h
b/drivers/net/ice/base/ice_flex_type.h
index 070d2aeb1e..988a2db958 100644
--- a/drivers/net/ice/base/ice_flex_type.h
+++ b/drivers/net/ice/base/ice_flex_type.h
@@ -442,8 +442,10 @@ enum ice_tunnel_type {
TNL_VXLAN = 0,
TNL_GENEVE,
TNL_GRETAP,
- TNL_ECPRI,
TNL_GTP,
+ TNL_GTPC,
+ TNL_GTPU,
+ TNL_ECPRI,
TNL_LAST = 0xFF,
TNL_ALL = 0xFF,
};
@@ -724,8 +726,10 @@ enum ice_prof_type {
ICE_PROF_NON_TUN = 0x1,
ICE_PROF_TUN_UDP = 0x2,
ICE_PROF_TUN_GRE = 0x4,
- ICE_PROF_TUN_PPPOE = 0x8,
- ICE_PROF_TUN_ALL = 0xE,
+ ICE_PROF_TUN_GTPU = 0x8,
+ ICE_PROF_TUN_GTPC = 0x10,
+ ICE_PROF_TUN_PPPOE = 0x20,
+ ICE_PROF_TUN_ALL = 0x3E,
ICE_PROF_ALL = 0xFF,
};
diff --git a/drivers/net/ice/base/ice_protocol_type.h
b/drivers/net/ice/base/ice_protocol_type.h
index 74107de988..da1f65fb22 100644
--- a/drivers/net/ice/base/ice_protocol_type.h
+++ b/drivers/net/ice/base/ice_protocol_type.h
@@ -45,13 +45,13 @@ enum ice_protocol_type {
ICE_VXLAN_GPE,
ICE_NVGRE,
ICE_GTP,
+ ICE_GTP_NO_PAY,
ICE_PPPOE,
ICE_PFCP,
ICE_L2TPV3,
ICE_ESP,
ICE_AH,
ICE_NAT_T,
- ICE_GTP_NO_PAY,
ICE_VLAN_EX,
ICE_VLAN_IN,
ICE_FLG_DIR,
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index ac045790ad..bb7e76bd29 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -8556,10 +8556,6 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem
*lkups, u16 lkups_cnt,
len = sizeof(struct ice_udp_tnl_hdr);
break;
- case ICE_GTP:
- case ICE_GTP_NO_PAY:
- len = sizeof(struct ice_udp_gtp_hdr);
- break;
case ICE_PPPOE:
len = sizeof(struct ice_pppoe_hdr);
break;
@@ -8575,6 +8571,10 @@ ice_fill_adv_dummy_packet(struct ice_adv_lkup_elem
*lkups, u16 lkups_cnt,
case ICE_L2TPV3:
len = sizeof(struct ice_l2tpv3_sess_hdr);
break;
+ case ICE_GTP:
+ case ICE_GTP_NO_PAY:
+ len = sizeof(struct ice_udp_gtp_hdr);
+ break;
default:
return ICE_ERR_PARAM;
}
diff --git a/drivers/net/ice/base/ice_switch.h
b/drivers/net/ice/base/ice_switch.h
index 3c05a1531f..dbad9363c4 100644
--- a/drivers/net/ice/base/ice_switch.h
+++ b/drivers/net/ice/base/ice_switch.h
@@ -28,7 +28,10 @@
#define ICE_PROFID_PPPOE_IPV6_UDP 39
#define ICE_PROFID_PPPOE_IPV6_OTHER40
#define ICE_PROFID_IPV4_GTPC_TEID 41
+#define ICE_PROFID_IPV4_GTPC_NO_TEID 42
#define ICE_PROFID_IPV4_GTPU_TEID 43
+#define ICE_PROFID_IPV6_GTPC_TEID 44
+#define ICE_PROFID_IPV6_GTPC_NO_TEID 45
#define ICE_PROFID_IPV6_GTPU_TEID 46
#define ICE_PROFID_IPV4_GTPU_EH_IPV4_OTHER 47
#define ICE_PROFID_IPV4_GTPU_IPV4_OTHER48
--
2.31.1
[PATCH 67/70] net/ice/base: check for PTP HW lock more frequently
PTP HW semaphore can be held for ~50 ms in worst case.
SW should wait longer and check more frequently if
the HW lock is held.
Signed-off-by: Karol Kolacinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index f5ebf5f328..974c96f60c 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -4844,18 +4844,18 @@ bool ice_ptp_lock(struct ice_hw *hw)
u32 hw_lock;
int i;
-#define MAX_TRIES 5
+#define MAX_TRIES 15
for (i = 0; i < MAX_TRIES; i++) {
hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
hw_lock = hw_lock & PFTSYN_SEM_BUSY_M;
if (hw_lock) {
/* Somebody is holding the lock */
- ice_msec_delay(10, true);
+ ice_msec_delay(5, true);
continue;
- } else {
- break;
}
+
+ break;
}
return !hw_lock;
--
2.31.1
[PATCH 68/70] net/ice/base: expose API for move sched element
Exposed ice_aq_move_sched_elems to support sched element moving by AQ command. Signed-off-by: Ben Shelton Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 10 +++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index f87b1c4897..3162b528c0 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -440,7 +440,7 @@ ice_aq_cfg_sched_elems(struct ice_hw *hw, u16 elems_req, * * Move scheduling elements (0x0408) */ -static enum ice_status +enum ice_status ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, struct ice_aqc_move_elem *buf, u16 buf_size, u16 *grps_movd, struct ice_sq_cd *cd) diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index 53a68dbe51..3793fd3df7 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -89,6 +89,10 @@ ice_aq_cfg_l2_node_cgd(struct ice_hw *hw, u16 num_nodes, struct ice_aqc_cfg_l2_node_cgd_elem *buf, u16 buf_size, struct ice_sq_cd *cd); enum ice_status +ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, + struct ice_aqc_move_elem *buf, u16 buf_size, + u16 *grps_movd, struct ice_sq_cd *cd); +enum ice_status ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, struct ice_aqc_txsched_elem_data *buf, u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd); @@ -176,12 +180,12 @@ enum ice_status ice_cfg_agg_bw_no_shared_lmt_per_tc(struct ice_port_info *pi, u32 agg_id, u8 tc); enum ice_status -ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, - struct ice_sched_node *node, u8 priority); -enum ice_status ice_cfg_vsi_q_priority(struct ice_port_info *pi, u16 num_qs, u32 *q_ids, u8 *q_prio); enum ice_status +ice_sched_cfg_sibl_node_prio_lock(struct ice_port_info *pi, + struct ice_sched_node *node, u8 priority); +enum ice_status ice_cfg_q_bw_alloc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, enum ice_rl_type rl_type, u32 bw_alloc); enum ice_status -- 2.31.1
[PATCH 69/70] net/ice/base: couple code clean
1. remove unused code
2. reduce variable scope
3. fix comment
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c| 2 +-
drivers/net/ice/base/ice_flex_pipe.c | 20 ++--
drivers/net/ice/base/ice_flow.c | 1 -
drivers/net/ice/base/ice_nvm.c | 2 +-
drivers/net/ice/base/ice_ptp_hw.c| 13 +
drivers/net/ice/base/ice_sched.c | 12
drivers/net/ice/base/ice_switch.c| 7 +--
7 files changed, 26 insertions(+), 31 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index 3d4e05f2b0..29d4be6618 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -801,7 +801,7 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* LFC. Thus, we will use index =
* PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
*
-* Also, because we are opearating on transmit timer and fc
+* Also, because we are operating on transmit timer and fc
* threshold of LFC, we don't turn on any bit in tx_tmr_priority
*/
#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
diff --git a/drivers/net/ice/base/ice_flex_pipe.c
b/drivers/net/ice/base/ice_flex_pipe.c
index 63ddda2df9..aec6ec3323 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -8,17 +8,6 @@
#include "ice_protocol_type.h"
#include "ice_flow.h"
-/* For supporting double VLAN mode, it is necessary to enable or disable
certain
- * boost tcam entries. The metadata labels names that match the following
- * prefixes will be saved to allow enabling double VLAN mode.
- */
-#define ICE_DVM_PRE"BOOST_MAC_VLAN_DVM"/* enable these entries */
-#define ICE_SVM_PRE"BOOST_MAC_VLAN_SVM"/* disable these entries */
-
-/* To support tunneling entries by PF, the package will append the PF number to
- * the label; for example TNL_VXLAN_PF0, TNL_VXLAN_PF1, TNL_VXLAN_PF2, etc.
- */
-#define ICE_TNL_PRE"TNL_"
static const struct ice_tunnel_type_scan tnls[] = {
{ TNL_VXLAN,"TNL_VXLAN_PF" },
{ TNL_GENEVE, "TNL_GENEVE_PF" },
@@ -526,10 +515,11 @@ ice_upd_dvm_boost_entry(struct ice_hw *hw, struct
ice_dvm_entry *entry)
*/
enum ice_status ice_set_dvm_boost_entries(struct ice_hw *hw)
{
- enum ice_status status;
u16 i;
for (i = 0; i < hw->dvm_upd.count; i++) {
+ enum ice_status status;
+
status = ice_upd_dvm_boost_entry(hw, &hw->dvm_upd.tbl[i]);
if (status)
return status;
@@ -3414,12 +3404,13 @@ ice_rem_vsig(struct ice_hw *hw, enum ice_block blk, u16
vsig,
u16 idx = vsig & ICE_VSIG_IDX_M;
struct ice_vsig_vsi *vsi_cur;
struct ice_vsig_prof *d, *t;
- enum ice_status status;
/* remove TCAM entries */
LIST_FOR_EACH_ENTRY_SAFE(d, t,
&hw->blk[blk].xlt2.vsig_tbl[idx].prop_lst,
ice_vsig_prof, list) {
+ enum ice_status status;
+
status = ice_rem_prof_id(hw, blk, d);
if (status)
return status;
@@ -3469,12 +3460,13 @@ ice_rem_prof_id_vsig(struct ice_hw *hw, enum ice_block
blk, u16 vsig, u64 hdl,
{
u16 idx = vsig & ICE_VSIG_IDX_M;
struct ice_vsig_prof *p, *t;
- enum ice_status status;
LIST_FOR_EACH_ENTRY_SAFE(p, t,
&hw->blk[blk].xlt2.vsig_tbl[idx].prop_lst,
ice_vsig_prof, list)
if (p->profile_cookie == hdl) {
+ enum ice_status status;
+
if (ice_vsig_prof_id_count(hw, blk, vsig) == 1)
/* this is the last profile, remove the VSIG */
return ice_rem_vsig(hw, blk, vsig, chg);
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index 33e97ec333..8a44823895 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -2583,7 +2583,6 @@ ice_flow_set_hw_prof(struct ice_hw *hw, u16
dest_vsi_handle,
struct ice_flow_prof_params *params;
u8 fv_words = hw->blk[blk].es.fvw;
enum ice_status status;
- u16 vsi_num;
int i, idx;
params = (struct ice_flow_prof_params *)ice_malloc(hw, sizeof(*params));
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 293b71905d..25a38e1610 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -725,7 +725,6 @@ ice_get_orom_civd_data(struct ice_hw *hw, enum
ice_bank_select bank,
struct ice_orom_civd_info *civd)
{
struct ice_orom_civd_info tmp;
- enum ice_status status;
u32 offset;
/* The CIVD section is located in the Option ROM aligned to 512 bytes.
@@ -734,6 +733,7 @@ ice_g
[PATCH 70/70] net/ice/base: update copyright
Updated copyright to 2022 and update base code version. Signed-off-by: Paul M. Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/README | 4 ++-- drivers/net/ice/base/ice_acl.c | 2 +- drivers/net/ice/base/ice_acl.h | 2 +- drivers/net/ice/base/ice_acl_ctrl.c | 2 +- drivers/net/ice/base/ice_adminq_cmd.h| 2 +- drivers/net/ice/base/ice_alloc.h | 2 +- drivers/net/ice/base/ice_bitops.h| 2 +- drivers/net/ice/base/ice_bst_tcam.c | 2 +- drivers/net/ice/base/ice_bst_tcam.h | 2 +- drivers/net/ice/base/ice_cgu_regs.h | 2 +- drivers/net/ice/base/ice_common.c| 2 +- drivers/net/ice/base/ice_common.h| 2 +- drivers/net/ice/base/ice_controlq.c | 2 +- drivers/net/ice/base/ice_controlq.h | 2 +- drivers/net/ice/base/ice_dcb.c | 2 +- drivers/net/ice/base/ice_dcb.h | 2 +- drivers/net/ice/base/ice_devids.h| 2 +- drivers/net/ice/base/ice_fdir.c | 2 +- drivers/net/ice/base/ice_fdir.h | 2 +- drivers/net/ice/base/ice_flex_pipe.c | 2 +- drivers/net/ice/base/ice_flex_pipe.h | 2 +- drivers/net/ice/base/ice_flex_type.h | 2 +- drivers/net/ice/base/ice_flg_rd.c| 2 +- drivers/net/ice/base/ice_flg_rd.h| 2 +- drivers/net/ice/base/ice_flow.c | 2 +- drivers/net/ice/base/ice_flow.h | 2 +- drivers/net/ice/base/ice_hw_autogen.h| 2 +- drivers/net/ice/base/ice_imem.c | 2 +- drivers/net/ice/base/ice_imem.h | 2 +- drivers/net/ice/base/ice_lan_tx_rx.h | 2 +- drivers/net/ice/base/ice_metainit.c | 2 +- drivers/net/ice/base/ice_metainit.h | 2 +- drivers/net/ice/base/ice_mk_grp.c| 2 +- drivers/net/ice/base/ice_mk_grp.h| 2 +- drivers/net/ice/base/ice_nvm.c | 2 +- drivers/net/ice/base/ice_nvm.h | 2 +- drivers/net/ice/base/ice_osdep.h | 2 +- drivers/net/ice/base/ice_parser.c| 2 +- drivers/net/ice/base/ice_parser.h| 2 +- drivers/net/ice/base/ice_parser_rt.c | 2 +- drivers/net/ice/base/ice_parser_rt.h | 2 +- drivers/net/ice/base/ice_parser_util.h | 2 +- drivers/net/ice/base/ice_pg_cam.c| 2 +- drivers/net/ice/base/ice_pg_cam.h| 2 +- drivers/net/ice/base/ice_proto_grp.c | 2 +- drivers/net/ice/base/ice_proto_grp.h | 2 +- drivers/net/ice/base/ice_protocol_type.h | 2 +- drivers/net/ice/base/ice_ptp_consts.h| 2 +- drivers/net/ice/base/ice_ptp_hw.c| 2 +- drivers/net/ice/base/ice_ptp_hw.h| 2 +- drivers/net/ice/base/ice_ptype_mk.c | 2 +- drivers/net/ice/base/ice_ptype_mk.h | 2 +- drivers/net/ice/base/ice_sbq_cmd.h | 2 +- drivers/net/ice/base/ice_sched.c | 2 +- drivers/net/ice/base/ice_sched.h | 2 +- drivers/net/ice/base/ice_status.h| 2 +- drivers/net/ice/base/ice_switch.c| 2 +- drivers/net/ice/base/ice_switch.h| 2 +- drivers/net/ice/base/ice_tmatch.h| 2 +- drivers/net/ice/base/ice_type.h | 2 +- drivers/net/ice/base/ice_vlan_mode.c | 2 +- drivers/net/ice/base/ice_vlan_mode.h | 2 +- drivers/net/ice/base/ice_xlt_kb.c| 2 +- drivers/net/ice/base/ice_xlt_kb.h| 2 +- 64 files changed, 65 insertions(+), 65 deletions(-) diff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README index 8123ec8c30..0e37a5f7a1 100644 --- a/drivers/net/ice/base/README +++ b/drivers/net/ice/base/README @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2020-2021 Intel Corporation + * Copyright(c) 2020-2022 Intel Corporation */ Intel® ICE driver == This directory contains source code of FreeBSD ice driver of version -2021.11.02 released by the team which develops +2022.08.04 released by the team which develops basic drivers for any ice NIC. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below diff --git a/drivers/net/ice/base/ice_acl.c b/drivers/net/ice/base/ice_acl.c index 6e1d1ad393..23b6c608be 100644 --- a/drivers/net/ice/base/ice_acl.c +++ b/drivers/net/ice/base/ice_acl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2021 Intel Corporation + * Copyright(c) 2001-2022 Intel Corporation */ #include "ice_acl.h" diff --git a/drivers/net/ice/base/ice_acl.h b/drivers/net/ice/base/ice_acl.h index a63b90faf8..b5f2ec04a4 100644 --- a/drivers/net/ice/base/ice_acl.h +++ b/drivers/net/ice/base/ice_acl.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright(c) 2001-2021 Intel Corporation + * Copyright(c) 2001-2022 Intel Corporation */ #ifndef _ICE_ACL_H_ diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c index 2dd08e326e..3a912f2aa0 100644 --- a/drivers/net/ice/base/ice_acl_ctrl.c +++ b/drivers/net/ice/base/ice_acl_ctrl.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - *
[PATCH v2 00/70] ice base code update
Update ice base code to 2022-Aug internal release. Summary: 1. Baseline support for L2TPv2 FDIR/RSS. 2. Refactor DDP module. 3. Support 56G PHY 4. Add GTP/GRE tunnel. 6. Clean code and fix bug 5. update copyright v2: - fix couple patchwork warnings. Qi Zhang (70): net/ice/base: add netlist helper functions net/ice/base: get NVM CSS Header length from the CSS Header net/ice/base: combine functions for VSI promisc net/ice/base: make function names more generic net/ice/base: fix incorrect division during E822 PTP init net/ice/base: added auto drop blocking packets functionality net/ice/base: fix 100M speed net/ice/base: support VXLAN and GRE for RSS net/ice/base: fix DSCP PFC TLV creation net/ice/base: complete the health status codes net/ice/base: explicitly name E822 HW-dependent functions net/ice/base: move code block net/ice/base: add PHY 56G destination address net/ice/base: add 56G PHY register definitions net/ice/base: implement 56G PHY access functions net/ice/base: implement 56G PHY setup functions net/ice/base: work around missing PTP caps net/ice/base: enable calling of ETH56G functions net/ice/base: fix PHY type 10G SFI C2C to media type mapping net/ice/base: refactor DDP code net/ice/base: add E822 generic PCI device ID net/ice/base: support double VLAN rules net/ice/base: report NVM version numbers on mismatch net/ice/base: create duplicate detection for ACL rules net/ice/base: fix incorrect function descriptions for parser net/ice/base: fix endian format net/ice/base: convert IO expander handle to u16 net/ice/base: convert array of u8 to bitmap net/ice/base: fix array overflow in add switch recipe code net/ice/base: fix bit finding range over ptype bitmap net/ice/base: move function to internal net/ice/base: change PHY/QUAD/ports definitions net/ice/base: add AQ command to config node attribute net/ice/base: fix null pointer dereference during net/ice/base: refine default VSI config net/ice/base: fix add mac rule net/ice/base: support Tx topo config net/ice/base: adjust the VSI/Aggregator layers net/ice/base: add data typecasting to match sizes net/ice/base: add helper function to check if device is E823 net/ice/base: add low latency Tx timestamp read net/ice/base: fix double VLAN error in promisc mode net/ice/base: move functions net/ice/base: complete support for Tx balancing net/ice/base: update definitions for AQ internal debug dump net/ice/base: update macros of L2TPv2 ptype value net/ice/base: refine header file include net/ice/base: ignore already exist error net/ice/base: clean up with no lookups net/ice/base: add support for Auto FEC with FEC disabled net/ice/base: update PHY type high max index net/ice/base: clean the main timer command register net/ice/base: add support for custom WPC and LGB NICs net/ice/base: add generic MAC with 3K signature segment net/ice/base: enable RSS support for L2TPv2 session ID net/ice/base: enable FDIR support for L2TPv2 net/ice/base: add GRE Tap tunnel type net/ice/base: fix wrong inputset of GTPoGRE packet net/ice/base: add unload flag for control queue shutdown net/ice/base: update comment for overloaded GCO bit net/ice/base: complete pending LLDP MIB net/ice/base: add function to parse DCBX config net/ice/base: handle default VSI lookup type net/ice/base: convert 1588 structs to use bitfields net/ice/base: remove unnecessary fields net/ice/base: add GTP tunnel net/ice/base: check for PTP HW lock more frequently net/ice/base: expose API for move sched element net/ice/base: couple code clean net/ice/base: update copyright drivers/net/ice/base/README |4 +- drivers/net/ice/base/ice_acl.c |2 +- drivers/net/ice/base/ice_acl.h |2 +- drivers/net/ice/base/ice_acl_ctrl.c | 36 +- drivers/net/ice/base/ice_adminq_cmd.h| 175 +- drivers/net/ice/base/ice_alloc.h |2 +- drivers/net/ice/base/ice_bitops.h|7 +- drivers/net/ice/base/ice_bst_tcam.c |8 +- drivers/net/ice/base/ice_bst_tcam.h |2 +- drivers/net/ice/base/ice_cgu_regs.h |2 +- drivers/net/ice/base/ice_common.c| 371 ++- drivers/net/ice/base/ice_common.h| 22 +- drivers/net/ice/base/ice_controlq.c | 33 +- drivers/net/ice/base/ice_controlq.h |2 +- drivers/net/ice/base/ice_dcb.c | 52 +- drivers/net/ice/base/ice_dcb.h |4 +- drivers/net/ice/base/ice_ddp.c | 2475 drivers/net/ice/base/ice_ddp.h | 466 drivers/net/ice/base/ice_defs.h | 49 + drivers/net/ice/base/ice_devids.h|9 +- drivers/net/ice/base/ice_fdir.c | 812 ++- drivers/net/ice/base/ice_fdir.h | 28 +- drivers/net/ice/base/ice_flex_pipe.c | 2541 +++-- drivers/net/ice/base/ice_flex_pipe.h | 66 +- drivers/net/ice/bas
[PATCH v2 01/70] net/ice/base: add netlist helper functions
Add new functions to check in netlist if HW has:
- Recovered Clock device,
- Clock Generation Unit,
- Clock Multiplexer,
- GPS generic device.
Signed-off-by: Michal Michalik
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 54 +++
drivers/net/ice/base/ice_common.c | 130 +-
drivers/net/ice/base/ice_common.h | 10 ++
drivers/net/ice/base/ice_ptp_hw.c | 37 +---
drivers/net/ice/base/ice_ptp_hw.h | 1 +
5 files changed, 195 insertions(+), 37 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 253b971dfd..a3add411b8 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1635,6 +1635,7 @@ struct ice_aqc_link_topo_params {
#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
+#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPS11
#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
@@ -1672,9 +1673,61 @@ struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_GEN_GPS 0x48
u8 rsvd[9];
};
+/* Get Link Topology Pin (direct, 0x06E1) */
+struct ice_aqc_get_link_topo_pin {
+ struct ice_aqc_link_topo_addr addr;
+ u8 input_io_params;
+#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0
+#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \
+ (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S)
+#define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1
+#define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N2
+#define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N3
+#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4
+#define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5
+#define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6
+#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10
+#define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP11
+/* 12 repeats intentionally due to two different uses depending on context */
+#define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12
+#define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12
+#define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED13
+#define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \
+ (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
+#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_GPIO 3
+/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
+ u8 output_io_params;
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \
+ (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S)
+/* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5
+#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \
+ (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S)
+/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */
+ u8 output_io_flags;
+#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0
+#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \
+ (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S)
+#define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3
+#define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \
+ (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S)
+#define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5)
+#define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6)
+#define ICE_AQC_LINK_TOPO_OUTPUT_DRIVENBIT(7)
+ u8 rsvd[7];
+};
+
/* Read/Write I2C (direct, 0x06E2/0x06E3) */
struct ice_aqc_i2c {
struct ice_aqc_link_topo_addr topo_addr;
@@ -2936,6 +2989,7 @@ struct ice_aq_desc {
struct ice_aqc_get_link_status get_link_status;
struct ice_aqc_event_lan_overflow lan_overflow;
struct ice_aqc_get_link_topo get_link_topo;
+ struct ice_aqc_get_link_topo_pin get_link_topo_pin;
struct ice_aqc_set_health_status_config
set_health_status_config;
struct ice_aqc_get_supported_health_status_codes
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index db87bacd97..edc24030ec 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -396,37 +396,103 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
}
/**
- * ice_aq_get_link_topo_handle - get link topology node return status
- * @pi: port information s
[PATCH v2 02/70] net/ice/base: get NVM CSS Header length from the CSS Header
The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To
support changes in CSS Header length, calculate the CSS Header
length from the NVM CSS Header length field plus the Authentication
Header length.
Signed-off-by: Paul Greenwalt
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_nvm.c | 61 +
drivers/net/ice/base/ice_type.h | 12 +++
2 files changed, 59 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 7860006206..ad2496e873 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -350,6 +350,42 @@ ice_read_nvm_module(struct ice_hw *hw, enum
ice_bank_select bank, u32 offset, u1
return status;
}
+/**
+ * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header
+ * @hw: pointer to the HW struct
+ * @bank: whether to read from the active or inactive flash bank
+ * @hdr_len: storage for header length in words
+ *
+ * Read the CSS header length from the NVM CSS header and add the
Authentication
+ * header size, and then convert to words.
+ */
+static enum ice_status
+ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,
+ u32 *hdr_len)
+{
+ u16 hdr_len_l, hdr_len_h;
+ enum ice_status status;
+ u32 hdr_len_dword;
+
+ status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,
+&hdr_len_l);
+ if (status)
+ return status;
+
+ status = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,
+&hdr_len_h);
+ if (status)
+ return status;
+
+ /* CSS header length is in DWORD, so convert to words and add
+* authentication header size
+*/
+ hdr_len_dword = hdr_len_h << 16 | hdr_len_l;
+ *hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank
* @hw: pointer to the HW structure
@@ -363,7 +399,16 @@ ice_read_nvm_module(struct ice_hw *hw, enum
ice_bank_select bank, u32 offset, u1
static enum ice_status
ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset,
u16 *data)
{
- return ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET +
offset, data);
+ enum ice_status status;
+ u32 hdr_len;
+
+ status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
+ if (status)
+ return status;
+
+ hdr_len = ROUND_UP(hdr_len, 32);
+
+ return ice_read_nvm_module(hw, bank, hdr_len + offset, data);
}
/**
@@ -633,22 +678,26 @@ enum ice_status ice_get_inactive_nvm_ver(struct ice_hw
*hw, struct ice_nvm_info
*/
static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum
ice_bank_select bank, u32 *srev)
{
+ u32 orom_size_word = hw->flash.banks.orom_size / 2;
enum ice_status status;
u16 srev_l, srev_h;
u32 css_start;
+ u32 hdr_len;
- if (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {
+ status = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);
+ if (status)
+ return status;
+
+ if (orom_size_word < hdr_len) {
ice_debug(hw, ICE_DBG_NVM, "Unexpected Option ROM Size of %u\n",
hw->flash.banks.orom_size);
return ICE_ERR_CFG;
}
/* calculate how far into the Option ROM the CSS header starts. Note
-* that ice_read_orom_module takes a word offset so we need to
-* divide by 2 here.
+* that ice_read_orom_module takes a word offset
*/
- css_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) /
2;
-
+ css_start = orom_size_word - hdr_len;
status = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L,
&srev_l);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index d81984633a..d4d0cab089 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1419,17 +1419,13 @@ struct ice_aq_get_set_rss_lut_params {
#define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR 0x118
/* CSS Header words */
+#define ICE_NVM_CSS_HDR_LEN_L 0x02
+#define ICE_NVM_CSS_HDR_LEN_H 0x03
#define ICE_NVM_CSS_SREV_L 0x14
#define ICE_NVM_CSS_SREV_H 0x15
-/* Length of CSS header section in words */
-#define ICE_CSS_HEADER_LENGTH 330
-
-/* Offset of Shadow RAM copy in the NVM bank area. */
-#define ICE_NVM_SR_COPY_WORD_OFFSETROUND_UP(ICE_CSS_HEADER_LENGTH,
32)
-
-/* Size in bytes of Option ROM trailer */
-#define ICE_NVM_OROM_TRAILER_LENGTH(2 * ICE_CSS_HEADER_LENGTH)
+/* Length of Authentication header section in words */
+#define ICE_NVM_AUTH
[PATCH v2 03/70] net/ice/base: combine functions for VSI promisc
Remove ice_get_vsi_vlan_promisc,
cause of similar implementation as ice_get_vsi_promisc,
which will now handle the use case of ice_get_vsi_vlan_promisc.
Signed-off-by: Wiktor Pilarczyk
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_switch.c | 58 ++-
1 file changed, 11 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ice/base/ice_switch.c
b/drivers/net/ice/base/ice_switch.c
index c0df3a1815..513623a0a4 100644
--- a/drivers/net/ice/base/ice_switch.c
+++ b/drivers/net/ice/base/ice_switch.c
@@ -5825,22 +5825,25 @@ static u8 ice_determine_promisc_mask(struct
ice_fltr_info *fi)
* @promisc_mask: pointer to mask to be filled in
* @vid: VLAN ID of promisc VLAN VSI
* @sw: pointer to switch info struct for which function add rule
+ * @lkup: switch rule filter lookup type
*/
static enum ice_status
_ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
-u16 *vid, struct ice_switch_info *sw)
+u16 *vid, struct ice_switch_info *sw,
+enum ice_sw_lkup_type lkup)
{
struct ice_fltr_mgmt_list_entry *itr;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
- if (!ice_is_vsi_valid(hw, vsi_handle))
+ if (!ice_is_vsi_valid(hw, vsi_handle) ||
+ (lkup != ICE_SW_LKUP_PROMISC && lkup != ICE_SW_LKUP_PROMISC_VLAN))
return ICE_ERR_PARAM;
*vid = 0;
*promisc_mask = 0;
- rule_head = &sw->recp_list[ICE_SW_LKUP_PROMISC].filt_rules;
- rule_lock = &sw->recp_list[ICE_SW_LKUP_PROMISC].filt_rule_lock;
+ rule_head = &sw->recp_list[lkup].filt_rules;
+ rule_lock = &sw->recp_list[lkup].filt_rule_lock;
ice_acquire_lock(rule_lock);
LIST_FOR_EACH_ENTRY(itr, rule_head,
@@ -5870,47 +5873,7 @@ ice_get_vsi_promisc(struct ice_hw *hw, u16 vsi_handle,
u8 *promisc_mask,
u16 *vid)
{
return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
- vid, hw->switch_info);
-}
-
-/**
- * _ice_get_vsi_vlan_promisc - get VLAN promiscuous mode of given VSI
- * @hw: pointer to the hardware structure
- * @vsi_handle: VSI handle to retrieve info from
- * @promisc_mask: pointer to mask to be filled in
- * @vid: VLAN ID of promisc VLAN VSI
- * @sw: pointer to switch info struct for which function add rule
- */
-static enum ice_status
-_ice_get_vsi_vlan_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
- u16 *vid, struct ice_switch_info *sw)
-{
- struct ice_fltr_mgmt_list_entry *itr;
- struct LIST_HEAD_TYPE *rule_head;
- struct ice_lock *rule_lock; /* Lock to protect filter rule list */
-
- if (!ice_is_vsi_valid(hw, vsi_handle))
- return ICE_ERR_PARAM;
-
- *vid = 0;
- *promisc_mask = 0;
- rule_head = &sw->recp_list[ICE_SW_LKUP_PROMISC_VLAN].filt_rules;
- rule_lock = &sw->recp_list[ICE_SW_LKUP_PROMISC_VLAN].filt_rule_lock;
-
- ice_acquire_lock(rule_lock);
- LIST_FOR_EACH_ENTRY(itr, rule_head, ice_fltr_mgmt_list_entry,
- list_entry) {
- /* Continue if this filter doesn't apply to this VSI or the
-* VSI ID is not in the VSI map for this filter
-*/
- if (!ice_vsi_uses_fltr(itr, vsi_handle))
- continue;
-
- *promisc_mask |= ice_determine_promisc_mask(&itr->fltr_info);
- }
- ice_release_lock(rule_lock);
-
- return ICE_SUCCESS;
+ vid, hw->switch_info, ICE_SW_LKUP_PROMISC);
}
/**
@@ -5924,8 +5887,9 @@ enum ice_status
ice_get_vsi_vlan_promisc(struct ice_hw *hw, u16 vsi_handle, u8 *promisc_mask,
u16 *vid)
{
- return _ice_get_vsi_vlan_promisc(hw, vsi_handle, promisc_mask,
-vid, hw->switch_info);
+ return _ice_get_vsi_promisc(hw, vsi_handle, promisc_mask,
+ vid, hw->switch_info,
+ ICE_SW_LKUP_PROMISC_VLAN);
}
/**
--
2.31.1
[PATCH v2 04/70] net/ice/base: make function names more generic
Previously "e810t" was part of few function names.
In the future it will require to add similar functions
for different NIC types.
Make "NIC type" a suffix of the function name.
Signed-off-by: Arkadiusz Kubalewski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 12 ++--
drivers/net/ice/base/ice_ptp_hw.h | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 5b366c95c5..632a3f5bae 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -3161,7 +3161,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw)
}
/**
- * ice_read_e810t_pca9575_reg
+ * ice_read_pca9575_reg_e810t
* @hw: pointer to the hw struct
* @offset: GPIO controller register offset
* @data: pointer to data to be read from the GPIO controller
@@ -3169,7 +3169,7 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw)
* Read the register from the GPIO controller
*/
enum ice_status
-ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
+ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
{
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
@@ -3191,7 +3191,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset,
u8 *data)
}
/**
- * ice_write_e810t_pca9575_reg
+ * ice_write_pca9575_reg_e810t
* @hw: pointer to the hw struct
* @offset: GPIO controller register offset
* @data: data to be written to the GPIO controller
@@ -3199,7 +3199,7 @@ ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset,
u8 *data)
* Write the data to the GPIO controller register
*/
enum ice_status
-ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data)
+ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data)
{
struct ice_aqc_link_topo_addr link_topo;
enum ice_status status;
@@ -3283,12 +3283,12 @@ enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw
*hw, u8 data)
}
/**
- * ice_e810t_is_pca9575_present
+ * ice_is_pca9575_present
* @hw: pointer to the hw struct
*
* Check if the SW IO expander is present in the netlist
*/
-bool ice_e810t_is_pca9575_present(struct ice_hw *hw)
+bool ice_is_pca9575_present(struct ice_hw *hw)
{
enum ice_status status;
__le16 handle = 0;
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 4f349593aa..d27815fd94 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -224,12 +224,12 @@ enum ice_status ice_phy_exit_bypass_e822(struct ice_hw
*hw, u8 port);
bool ice_is_gps_present_e810t(struct ice_hw *hw);
enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);
enum ice_status
-ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
+ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
enum ice_status
-ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data);
+ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data);
enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
-bool ice_e810t_is_pca9575_present(struct ice_hw *hw);
+bool ice_is_pca9575_present(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
--
2.31.1
[PATCH v2 05/70] net/ice/base: fix incorrect division during E822 PTP init
When initializing the device hardware for PTP, the E822 devices
requirea number of values to be calculated and programmed to
hardware.These values are calculated using unsigned 64-bit
division.
The DIV_64BIT macro currently translates into a specific Linux
functionthat triggers a *signed* division. This produces incorrect
results when operating on a dividend larger than an s64. The
division calculation effectively overflows and results in totally
unexpected behavior.
In this case, the UIX value for 10Gb/40Gb link speeds are calculated
incorrectly. This ultimately cascades into a failure of the Tx
timestamps. Specifically, the reported Tx timestamps become wildly
inaccurate and not representing nominal time.
The root cause of this bug is the assumption that DIV_64BIT can
correctly handle both signed and unsigned division. In fact the
entire reason we need this is because the Linux kernel compilation
target does not provide native 64 bit division ops, and requires
explicit use of kernel functions which explicitly do either signed
or unsigned division.
To correctly solve this, introduce new functions, DIV_U64 and
DIV_S64 which are specifically intended for signed or unsigned
division. To help catch issues, use static inline functions so
that we get strict type checking.
Fixes: 97f4f78bbd9f ("net/ice/base: add functions for device clock control")
Cc: sta...@dpdk.org
Signed-off-by: Jacob Keller
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 56 +++
drivers/net/ice/base/ice_sched.c | 24 ++---
drivers/net/ice/base/ice_type.h | 30 +++--
3 files changed, 68 insertions(+), 42 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 632a3f5bae..76119364e4 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw
*hw, u8 port)
#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
/* Program the 10Gb/40Gb conversion ratio */
- uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
+ uix = DIV_U64(tu_per_sec * LINE_UI_10G_40G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
uix);
@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw
*hw, u8 port)
}
/* Program the 25Gb/100Gb conversion ratio */
- uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
+ uix = DIV_U64(tu_per_sec * LINE_UI_25G_100G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
uix);
@@ -1727,8 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_par_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_par_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].tx_par_clk);
else
phy_tus = 0;
@@ -1739,8 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].rx_par_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].rx_par_clk);
else
phy_tus = 0;
@@ -1751,8 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_pcs_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].tx_pcs_clk);
else
phy_tus = 0;
@@ -1763,8 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].rx_pcs_clk);
+ phy_tus = DIV_U64(tu_per_sec,
+ e822_vernier[link_spd].rx_pcs_clk);
else
phy_tus = 0;
@@ -1775,8 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct
ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
- phy_tus = DIV_64BIT(tu_per_sec,
- e822_vernier[link_spd].tx_desk_rsgb_par);
+ phy_tus = DIV_U64(tu_per_sec,
+
[PATCH v2 06/70] net/ice/base: added auto drop blocking packets functionality
Extended ice_aq_set_mac_cfg()function to add support for
auto drop blocking packets.
Signed-off-by: Mateusz Rusinski
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 22 --
drivers/net/ice/base/ice_common.h | 5 -
drivers/net/ice/base/ice_type.h | 6 ++
drivers/net/ice/ice_ethdev.c | 2 +-
4 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index edc24030ec..f9640d9403 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -788,12 +788,14 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
* ice_aq_set_mac_cfg
* @hw: pointer to the HW struct
* @max_frame_size: Maximum Frame Size to be supported
+ * @auto_drop: Tell HW to drop packets if TC queue is blocked
* @cd: pointer to command details structure or NULL
*
* Set MAC configuration (0x0603)
*/
enum ice_status
-ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop,
+ struct ice_sq_cd *cd)
{
struct ice_aqc_set_mac_cfg *cmd;
struct ice_aq_desc desc;
@@ -807,6 +809,8 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size,
struct ice_sq_cd *cd)
cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
+ if (ice_is_fw_auto_drop_supported(hw) && auto_drop)
+ cmd->drop_opts |= ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS;
ice_fill_tx_timer_and_fc_thresh(hw, cmd);
return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
@@ -1106,7 +1110,8 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
goto err_unroll_fltr_mgmt_struct;
/* enable jumbo frame support at MAC level */
- status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
+ status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, false,
+ NULL);
if (status)
goto err_unroll_fltr_mgmt_struct;
@@ -5921,3 +5926,16 @@ bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw)
}
return false;
}
+/**
+ * ice_is_fw_auto_drop_supported
+ * @hw: pointer to the hardware structure
+ *
+ * Checks if the firmware supports auto drop feature
+ */
+bool ice_is_fw_auto_drop_supported(struct ice_hw *hw)
+{
+ if (hw->api_maj_ver >= ICE_FW_API_AUTO_DROP_MAJ &&
+ hw->api_min_ver >= ICE_FW_API_AUTO_DROP_MIN)
+ return true;
+ return false;
+}
diff --git a/drivers/net/ice/base/ice_common.h
b/drivers/net/ice/base/ice_common.h
index 1044a3088e..1051cc1176 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -191,7 +191,8 @@ enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd);
enum ice_status
-ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd
*cd);
+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop,
+ struct ice_sq_cd *cd);
enum ice_status
ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
struct ice_link_status *link, struct ice_sq_cd *cd);
@@ -289,4 +290,6 @@ ice_aq_write_i2c(struct ice_hw *hw, struct
ice_aqc_link_topo_addr topo_addr,
u16 bus_addr, __le16 addr, u8 params, u8 *data,
struct ice_sq_cd *cd);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
+/* AQ API version for FW auto drop reports */
+bool ice_is_fw_auto_drop_supported(struct ice_hw *hw);
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 3da3de38af..15b12bfc8d 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1539,5 +1539,11 @@ struct ice_aq_get_set_rss_lut_params {
/* AQ API version for report default configuration */
#define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
#define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
+
#define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
+/* AQ API version for FW auto drop reports */
+#define ICE_FW_API_AUTO_DROP_MAJ 1
+#define ICE_FW_API_AUTO_DROP_MIN 4
+
+
#endif /* _ICE_TYPE_H_ */
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 587b01cf23..2e522376e3 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -3662,7 +3662,7 @@ ice_dev_start(struct rte_eth_dev *dev)
ICE_FRAME_SIZE_MAX;
/* Set the max frame size to HW*/
- ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
+ ice_aq_set_mac_cfg(hw, max_frame_size, false, NULL);
if (ad->devargs.pps_out_ena) {
ret = ice_pps_out_cfg(hw, pin_idx, timer);
--
2.31.1
[PATCH v2 07/70] net/ice/base: fix 100M speed
Couple of 10GBase-T devices don't support advertising 100M
speed. For these devices, ice_is_100m_speed_supported should
return false. Meanwhile add device that supports 100M speed.
Fixes: 486d29fda54c ("net/ice/base: add dedicate MAC type for E810")
Cc: sta...@dpdk.org
Signed-off-by: Anirudh Venkataramanan
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_common.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/ice/base/ice_common.c
b/drivers/net/ice/base/ice_common.c
index f9640d9403..e22600c46d 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -3113,12 +3113,10 @@ ice_aq_set_port_params(struct ice_port_info *pi, u16
bad_frame_vsi,
bool ice_is_100m_speed_supported(struct ice_hw *hw)
{
switch (hw->device_id) {
- case ICE_DEV_ID_E822C_10G_BASE_T:
case ICE_DEV_ID_E822C_SGMII:
- case ICE_DEV_ID_E822L_10G_BASE_T:
case ICE_DEV_ID_E822L_SGMII:
- case ICE_DEV_ID_E823L_10G_BASE_T:
case ICE_DEV_ID_E823L_1GBE:
+ case ICE_DEV_ID_E823C_SGMII:
return true;
default:
return false;
--
2.31.1
[PATCH v2 08/70] net/ice/base: support VXLAN and GRE for RSS
Add RSS of inner headers for VXLAN tunnel packet.
Add packet types for packets with outer IPv4/IPv6 header
support GRE and VXLAN tunnel packet.
Following rules can use new packet types:
- eth / ipv4(6) / udp / vxlan / ipv4(6)
- eth / ipv4(6) / udp / vxlan / ipv4(6) / tcp
- eth / ipv4(6) / udp / vxlan / ipv4(6) / udp
- eth / ipv4(6) / gre / ipv4(6)
- eth / ipv4(6) / gre / ipv4(6) / tcp
- eth / ipv4(6) / gre / ipv4(6) / udp
Signed-off-by: Jie Wang
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_flow.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c
index d7eecc0d54..bdb584c7f5 100644
--- a/drivers/net/ice/base/ice_flow.c
+++ b/drivers/net/ice/base/ice_flow.c
@@ -262,7 +262,7 @@ static const u32 ice_ptypes_macvlan_il[] = {
* does NOT include IPV4 other PTYPEs
*/
static const u32 ice_ptypes_ipv4_ofos[] = {
- 0x1D80, 0x24000800, 0x, 0x,
+ 0x1D80, 0xBFBF7800, 0x01DF, 0x,
0x, 0x0155, 0x, 0x,
0x, 0x000FC000, 0x02A0, 0x0010,
0x1500, 0x, 0x, 0x,
@@ -316,8 +316,8 @@ static const u32 ice_ptypes_ipv6_ofos[] = {
* includes IPV6 other PTYPEs
*/
static const u32 ice_ptypes_ipv6_ofos_all[] = {
- 0x, 0x, 0x7600, 0x1EFDE000,
- 0x, 0x02AA, 0x, 0x,
+ 0x, 0x, 0x7600, 0xFEFDE000,
+ 0x077E, 0x02AA, 0x, 0x,
0x, 0x03F0, 0x7C1F0540, 0x0206,
0xFC002000, 0x003F, 0xBC00, 0x0002FBEF,
0x, 0x, 0x, 0x,
@@ -985,8 +985,9 @@ struct ice_flow_prof_params {
ICE_FLOW_SEG_HDR_PFCP_SESSION | ICE_FLOW_SEG_HDR_L2TPV3 | \
ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \
ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \
+ ICE_FLOW_SEG_HDR_VXLAN | ICE_FLOW_SEG_HDR_GRE | \
ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \
- ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE)
+ ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP)
#define ICE_FLOW_SEG_HDRS_L2_MASK \
(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)
--
2.31.1
[PATCH v2 09/70] net/ice/base: fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC. This means that traffic classes 4-7 could not be
enabled for PFC.
Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.
Fixes: 8ea78b169603 ("net/ice/base: support L3 DSCP QoS")
Cc: sta...@dpdk.org
Signed-off-by: Dave Ertman
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_dcb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index cb6c5ba182..3d630757f8 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -1376,7 +1376,7 @@ ice_add_dscp_pfc_tlv(struct ice_lldp_org_tlv *tlv, struct
ice_dcbx_cfg *dcbcfg)
tlv->ouisubtype = HTONL(ouisubtype);
buf[0] = dcbcfg->pfc.pfccap & 0xF;
- buf[1] = dcbcfg->pfc.pfcena & 0xF;
+ buf[1] = dcbcfg->pfc.pfcena;
}
/**
--
2.31.1
[PATCH v2 10/70] net/ice/base: complete the health status codes
add definitions for async health status codes.
Signed-off-by: Leszek Zygo
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index a3add411b8..517af4b6ef 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2821,6 +2821,7 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
#define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
+#define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109
#define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
@@ -2842,7 +2843,16 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
+#define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION0x507
+#define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508
#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
+#define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A
+#define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET0x50B
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL0x50C
+#define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002
/* Get Health Status codes (indirect 0xFF21) */
struct ice_aqc_get_supported_health_status_codes {
--
2.31.1
[PATCH v2 11/70] net/ice/base: explicitly name E822 HW-dependent functions
Add the suffix to E822 HW-dependent function names
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 23 ---
drivers/net/ice/base/ice_ptp_hw.h | 7 ---
2 files changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 76119364e4..23d90b127d 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1268,7 +1268,7 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32
target_time)
}
/**
- * ice_ptp_read_port_capture - Read a port's local time capture
+ * ice_ptp_read_port_capture_e822 - Read a port's local time capture
* @hw: pointer to HW struct
* @port: Port number to read
* @tx_ts: on return, the Tx port time capture
@@ -1279,7 +1279,8 @@ ice_ptp_prep_phy_adj_target_e822(struct ice_hw *hw, u32
target_time)
* Note this has no equivalent for the E810 devices.
*/
enum ice_status
-ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts)
+ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port, u64 *tx_ts,
+ u64 *rx_ts)
{
enum ice_status status;
@@ -1309,7 +1310,7 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64
*tx_ts, u64 *rx_ts)
}
/**
- * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command
+ * ice_ptp_one_port_cmd_e822 - Prepare a single PHY port for a timer command
* @hw: pointer to HW struct
* @port: Port to which cmd has to be sent
* @cmd: Command to be sent to the port
@@ -1321,8 +1322,8 @@ ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64
*tx_ts, u64 *rx_ts)
* always handles all external PHYs internally.
*/
enum ice_status
-ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
-bool lock_sbq)
+ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,
+ bool lock_sbq)
{
enum ice_status status;
u32 cmd_val, val;
@@ -1416,7 +1417,7 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
enum ice_status status;
- status = ice_ptp_one_port_cmd(hw, port, cmd, lock_sbq);
+ status = ice_ptp_one_port_cmd_e822(hw, port, cmd, lock_sbq);
if (status)
return status;
}
@@ -2318,7 +2319,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8
port, u64 *phy_time,
ice_ptp_src_cmd(hw, READ_TIME);
/* Prepare the PHY timer for a READ_TIME capture command */
- status = ice_ptp_one_port_cmd(hw, port, READ_TIME, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, READ_TIME, true);
if (status)
return status;
@@ -2331,7 +2332,7 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8
port, u64 *phy_time,
*phc_time = (u64)lo << 32 | zo;
/* Read the captured PHY time from the PHY shadow registers */
- status = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time);
+ status = ice_ptp_read_port_capture_e822(hw, port, &tx_time, &rx_time);
if (status)
return status;
@@ -2388,7 +2389,7 @@ static enum ice_status ice_sync_phy_timer_e822(struct
ice_hw *hw, u8 port)
if (status)
goto err_unlock;
- status = ice_ptp_one_port_cmd(hw, port, ADJ_TIME, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, ADJ_TIME, true);
if (status)
goto err_unlock;
@@ -2513,7 +2514,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool
bypass)
if (status)
return status;
- status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);
if (status)
return status;
@@ -2538,7 +2539,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool
bypass)
if (status)
return status;
- status = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL, true);
+ status = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);
if (status)
return status;
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index d27815fd94..9cc3436aa8 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -157,10 +157,11 @@ ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port,
s64 time,
enum ice_status
ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval);
enum ice_status
-ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts);
+ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,
+ u64 *tx_ts, u64 *rx_ts);
enum ice_status
-ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd c
[PATCH v2 12/70] net/ice/base: move code block
Move some code block to the beginning of ice_ptp_hw.c to align
withkernel driver.
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_ptp_hw.c | 997 +++---
1 file changed, 498 insertions(+), 499 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 23d90b127d..22d0774dd7 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -101,6 +101,286 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw)
return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;
}
+/**
+ * ice_read_cgu_reg_e822 - Read a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to read
+ * @val: storage for register value read
+ *
+ * Read the contents of a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_rd;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x,
status %d\n",
+ addr, status);
+ return status;
+ }
+
+ *val = cgu_msg.data;
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_write_cgu_reg_e822 - Write a CGU register
+ * @hw: pointer to the HW struct
+ * @addr: Register address to write
+ * @val: value to write into the register
+ *
+ * Write the specified value to a register of the Clock Generation Unit. Only
+ * applicable to E822 devices.
+ */
+static enum ice_status
+ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)
+{
+ struct ice_sbq_msg_input cgu_msg;
+ enum ice_status status;
+
+ cgu_msg.opcode = ice_sbq_msg_wr;
+ cgu_msg.dest_dev = cgu;
+ cgu_msg.msg_addr_low = addr;
+ cgu_msg.msg_addr_high = 0x0;
+ cgu_msg.data = val;
+
+ status = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);
+ if (status) {
+ ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register
0x%04x, status %d\n",
+ addr, status);
+ return status;
+ }
+
+ return ICE_SUCCESS;
+}
+
+/**
+ * ice_clk_freq_str - Convert time_ref_freq to string
+ * @clk_freq: Clock frequency
+ *
+ * Convert the specified TIME_REF clock frequency to a string.
+ */
+static const char *ice_clk_freq_str(u8 clk_freq)
+{
+ switch ((enum ice_time_ref_freq)clk_freq) {
+ case ICE_TIME_REF_FREQ_25_000:
+ return "25 MHz";
+ case ICE_TIME_REF_FREQ_122_880:
+ return "122.88 MHz";
+ case ICE_TIME_REF_FREQ_125_000:
+ return "125 MHz";
+ case ICE_TIME_REF_FREQ_153_600:
+ return "153.6 MHz";
+ case ICE_TIME_REF_FREQ_156_250:
+ return "156.25 MHz";
+ case ICE_TIME_REF_FREQ_245_760:
+ return "245.76 MHz";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_clk_src_str - Convert time_ref_src to string
+ * @clk_src: Clock source
+ *
+ * Convert the specified clock source to its string name.
+ */
+static const char *ice_clk_src_str(u8 clk_src)
+{
+ switch ((enum ice_clk_src)clk_src) {
+ case ICE_CLK_SRC_TCX0:
+ return "TCX0";
+ case ICE_CLK_SRC_TIME_REF:
+ return "TIME_REF";
+ default:
+ return "Unknown";
+ }
+}
+
+/**
+ * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit
+ * @hw: pointer to the HW struct
+ * @clk_freq: Clock frequency to program
+ * @clk_src: Clock source to select (TIME_REF, or TCX0)
+ *
+ * Configure the Clock Generation Unit with the desired clock frequency and
+ * time reference, enabling the PLL which drives the PTP hardware clock.
+ */
+enum ice_status
+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
+enum ice_clk_src clk_src)
+{
+ union tspll_ro_bwm_lf bwm_lf;
+ union nac_cgu_dword19 dw19;
+ union nac_cgu_dword22 dw22;
+ union nac_cgu_dword24 dw24;
+ union nac_cgu_dword9 dw9;
+ enum ice_status status;
+
+ if (clk_freq >= NUM_ICE_TIME_REF_FREQ) {
+ ice_warn(hw, "Invalid TIME_REF frequency %u\n", clk_freq);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src >= NUM_ICE_CLK_SRC) {
+ ice_warn(hw, "Invalid clock source %u\n", clk_src);
+ return ICE_ERR_PARAM;
+ }
+
+ if (clk_src == ICE_CLK_SRC_TCX0 &&
+ clk_freq != ICE_TIME_REF_FREQ_25_000) {
+ ice_warn(hw, "TCX0 only supports 25 MHz frequency\n");
+ return ICE_ERR_PARAM;
+ }
+
+ status = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw
[PATCH v2 13/70] net/ice/base: add PHY 56G destination address
Add PHY 56G destination address. PHY56G is a single device
incorporating all SerDes lanes
Signed-off-by: Sergey Temerkhanov
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_sbq_cmd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ice/base/ice_sbq_cmd.h
b/drivers/net/ice/base/ice_sbq_cmd.h
index a5fe43bf26..76c718b252 100644
--- a/drivers/net/ice/base/ice_sbq_cmd.h
+++ b/drivers/net/ice/base/ice_sbq_cmd.h
@@ -48,6 +48,7 @@ struct ice_sbq_evt_desc {
};
enum ice_sbq_msg_dev {
+ phy_56g = 0x02,
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
--
2.31.1
[PATCH v2 14/70] net/ice/base: add 56G PHY register definitions
Add 56G PHY register address definitions to facilitate 56G PHY support. Signed-off-by: Sergey Temerkhanov Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_ptp_hw.h | 75 +++ 1 file changed, 75 insertions(+) diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h index 9cc3436aa8..ecb79eaea9 100644 --- a/drivers/net/ice/base/ice_ptp_hw.h +++ b/drivers/net/ice/base/ice_ptp_hw.h @@ -482,5 +482,80 @@ bool ice_is_pca9575_present(struct ice_hw *hw); #define ICE_E810T_SMA_MIN_BIT 3 #define ICE_E810T_SMA_MAX_BIT 7 #define ICE_E810T_P1_OFFSET8 +/* 56G PHY quad register base addresses */ +#define ICE_PHY0_BASE 0x092000 +#define ICE_PHY1_BASE 0x126000 +#define ICE_PHY2_BASE 0x1BA000 +#define ICE_PHY3_BASE 0x24E000 +#define ICE_PHY4_BASE 0x2E2000 + +/* Timestamp memory */ +#define PHY_PTP_LANE_ADDR_STEP 0x98 + +#define PHY_PTP_MEM_START 0x1000 +#define PHY_PTP_MEM_LANE_STEP 0x04A0 +#define PHY_PTP_MEM_LOCATIONS 0x40 + +/* Number of PHY ports */ +#define ICE_NUM_PHY_PORTS 5 +/* Timestamp PHY incval registers */ +#define PHY_REG_TIMETUS_L 0x8 +#define PHY_REG_TIMETUS_U 0xC + +/* Timestamp init registers */ +#define PHY_REG_RX_TIMER_INC_PRE_L 0x64 +#define PHY_REG_RX_TIMER_INC_PRE_U 0x68 + +#define PHY_REG_TX_TIMER_INC_PRE_L 0x44 +#define PHY_REG_TX_TIMER_INC_PRE_U 0x48 + +/* Timestamp match and adjust target registers */ +#define PHY_REG_RX_TIMER_CNT_ADJ_L 0x6C +#define PHY_REG_RX_TIMER_CNT_ADJ_U 0x70 + +#define PHY_REG_TX_TIMER_CNT_ADJ_L 0x4C +#define PHY_REG_TX_TIMER_CNT_ADJ_U 0x50 + +/* Timestamp command registers */ +#define PHY_REG_TX_TMR_CMD 0x40 +#define PHY_REG_RX_TMR_CMD 0x60 + +/* Phy offset ready registers */ +#define PHY_REG_TX_OFFSET_READY0x54 +#define PHY_REG_RX_OFFSET_READY0x74 +/* Phy total offset registers */ +#define PHY_REG_TOTAL_TX_OFFSET_L 0x38 +#define PHY_REG_TOTAL_TX_OFFSET_U 0x3C + +#define PHY_REG_TOTAL_RX_OFFSET_L 0x58 +#define PHY_REG_TOTAL_RX_OFFSET_U 0x5C + +/* Timestamp capture registers */ +#define PHY_REG_TX_CAPTURE_L 0x78 +#define PHY_REG_TX_CAPTURE_U 0x7C + +#define PHY_REG_RX_CAPTURE_L 0x8C +#define PHY_REG_RX_CAPTURE_U 0x90 + +/* Memory status registers */ +#define PHY_REG_TX_MEMORY_STATUS_L 0x80 +#define PHY_REG_TX_MEMORY_STATUS_U 0x84 + +/* Interrupt config register */ +#define PHY_REG_TS_INT_CONFIG 0x88 + +#define PHY_PTP_INT_STATUS 0x7FD140 + +#define PHY_TS_INT_CONFIG_THRESHOLD_S 0 +#define PHY_TS_INT_CONFIG_THRESHOLD_M MAKEMASK(0x3F, 0) +#define PHY_TS_INT_CONFIG_ENA_S6 +#define PHY_TS_INT_CONFIG_ENA_MBIT(6) + +/* Macros to derive offsets for TimeStampLow and TimeStampHigh */ +#define PHY_TSTAMP_L(x) (((x) * 8) + 0) +#define PHY_TSTAMP_U(x) (((x) * 8) + 4) + +#define PHY_REG_REVISION 0x85000 +#define PHY_REVISION_ETH56G0x10200 #endif /* _ICE_PTP_HW_H_ */ -- 2.31.1
