RE: [PATCH v2 06/16] net/dpaa2: support multiple txqs en-queue for ordered

[Nipun Gupta]

> -Original Message-
> From: Nipun Gupta
> Sent: 03 January 2022 11:17
> To: Stephen Hemminger 
> Cc: dev@dpdk.org; tho...@monjalon.net; ferruh.yi...@intel.com; Hemant
> Agrawal ; Jun Yang 
> Subject: RE: [PATCH v2 06/16] net/dpaa2: support multiple txqs en-queue for
> ordered
> 
> 
> 
> > -Original Message-
> > From: Stephen Hemminger 
> > Sent: 27 December 2021 23:32
> > To: Nipun Gupta 
> > Cc: dev@dpdk.org; tho...@monjalon.net; ferruh.yi...@intel.com; Hemant
> > Agrawal ; Jun Yang 
> > Subject: Re: [PATCH v2 06/16] net/dpaa2: support multiple txqs en-queue for
> > ordered
> >
> > On Mon, 27 Dec 2021 21:46:35 +0530
> > nipun.gu...@nxp.com wrote:
> >
> > > @@ -1003,16 +1003,20 @@ dpaa2_eventdev_txa_enqueue(void *port,
> > >  struct rte_event ev[],
> > >  uint16_t nb_events)
> > >  {
> > > - struct rte_mbuf *m = (struct rte_mbuf *)ev[0].mbuf;
> > > + void *txq[32];
> > > + struct rte_mbuf *m[32];
> >
> > You are assuming nb_events <= 32.
> > Why not size the array based on nb_events.
> 
> Agree. Actually I will use DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH here.
> 
> >
> > >   uint8_t qid, i;
> > >
> > >   RTE_SET_USED(port);
> > >
> > >   for (i = 0; i < nb_events; i++) {
> > > - qid = rte_event_eth_tx_adapter_txq_get(m);
> > > - rte_eth_tx_burst(m->port, qid, &m, 1);
> > > + m[i] = (struct rte_mbuf *)ev[i].mbuf;
> >
> > Why the cast? it is already the right type.
> 
> Will remove the cast.

mbuf is void *type in event structure, so it seems better to cast here.

> 
> Thanks,
> Nipun
> 
> >
> > > + qid = rte_event_eth_tx_adapter_txq_get(m[i]);
> > > + txq[i] = rte_eth_devices[m[i]->port].data->tx_queues[qid];

RE: [PATCH v2] app/eventdev: add crypto producer mode

[Gujjar, Abhinandan S]

Hi Shijith,

> -Original Message-
> From: Shijith Thotton 
> Sent: Monday, January 3, 2022 11:34 AM
> To: Gujjar, Abhinandan S ; dev@dpdk.org; Jerin
> Jacob Kollanukkaran 
> Cc: Anoob Joseph ; Pavan Nikhilesh Bhagavatula
> ; Akhil Goyal 
> Subject: RE: [PATCH v2] app/eventdev: add crypto producer mode
> 
> Hi Abhinandan,
> 
> >> Subject: [PATCH v2] app/eventdev: add crypto producer mode
> >>
> >> In crypto producer mode, producer core enqueues cryptodev with
> >> software generated crypto ops and worker core dequeues crypto
> >> completion events from the eventdev. Event crypto metadata used for
> >> above processing is pre- populated in each crypto session.
> >>
> >> Parameter --prod_type_cryptodev can be used to enable crypto producer
> >mode.
> >> Parameter --crypto_adptr_mode can be set to select the crypto adapter
> >> mode,
> >0
> >> for OP_NEW and 1 for OP_FORWARD.
> >>
> >> This mode can be used to measure the performance of crypto adapter.
> >>
> >> Example:
> >>   ./dpdk-test-eventdev -l 0-2 -w  -w  -- \
> >>   --prod_type_cryptodev --crypto_adptr_mode 1 --test=perf_atq \
> >>   --stlist=a --wlcores 1 --plcores 2
> >
> >This patch has some perf failure as shown below. Could you please look into
> this?
> >105300 --> performance testing fail
> >
> >Test environment and result as below:
> >
> >Ubuntu 20.04
> >Kernel: 4.15.0-generic
> >Compiler: gcc 7.4
> >NIC: Intel Corporation Ethernet Converged Network Adapter 82599ES 1
> >Mbps
> >Target: x86_64-native-linuxapp-gcc
> >Fail/Total: 0/4
> >
> >Detail performance results:
> >++-+--+-+--+
> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
> >| difference from
> >|
> >|| |  | |   expected 
> >  |
> >++=+==+=+=
> >=+
> >| 64 | 512 | 1| 1   | 0.3%   
> >  |
> >++-+--+-+--+
> >| 64 | 2048| 1| 1   | -0.2%  
> >  |
> >++-+--+-+--+
> >| 64 | 512 | 1| 2   | 0.0%   
> >  |
> >++-+--+-+--+
> >| 64 | 2048| 1| 2   | 0.3%   
> >  |
> >++-+--+-+--+
> >
> >Ubuntu 20.04
> >Kernel: 4.15.0-generic
> >Compiler: gcc 7.4
> >NIC: Intel Corporation Ethernet Converged Network Adapter XL710-QDA2
> >4 Mbps
> >Target: x86_64-native-linuxapp-gcc
> >Fail/Total: 1/4
> >
> >Detail performance results:
> >++-+--+-+--+
> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
> >| difference from
> >|
> >|| |  | |   expected 
> >  |
> >++=+==+=+=
> >=+
> >| 64 | 512 | 1| 1   | 0.2%   
> >  |
> >++-+--+-+--+
> >| 64 | 2048| 1| 1   | -0.7%  
> >  |
> >++-+--+-+--+
> >| 64 | 512 | 1| 2   | -1.5%  
> >  |
> >++-+--+-+--+
> >| 64 | 2048| 1| 2   | -5.3%  
> >  |
> >++-+--+-+--+
> >
> >Ubuntu 20.04 ARM
> >Kernel: 4.15.0-132-generic
> >Compiler: gcc 7.5
> >NIC: Arm Intel Corporation Ethernet Converged Network Adapter
> >XL710-QDA2
> >4 Mbps
> >Target: x86_64-native-linuxapp-gcc
> >Fail/Total: 0/2
> >
> >Detail performance results:
> >++-+--+-+--+
> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
> >| difference from
> >|
> >|| |  | |   expected 
> >  |
> >++=+==+=+=
> >=+
> >| 64 | 512 | 1| 1   | 0.1%   
> >  |
> >++-+--+-+--+
> >| 64 | 2048| 1| 1   | -0.5%  
> >  |
> >++-+--+-+--+
> >
> >To view detailed results, visit:
> >https://urldefense.proofpoint.com/v2/url?u=https-
> >3A__lab.dpdk.org_results_dashboard_patchsets_20534_&d=DwIFA

RE: [PATCH v2] app/eventdev: add crypto producer mode

[Shijith Thotton]

>> >>
>> >> In crypto producer mode, producer core enqueues cryptodev with
>> >> software generated crypto ops and worker core dequeues crypto
>> >> completion events from the eventdev. Event crypto metadata used for
>> >> above processing is pre- populated in each crypto session.
>> >>
>> >> Parameter --prod_type_cryptodev can be used to enable crypto producer
>> >mode.
>> >> Parameter --crypto_adptr_mode can be set to select the crypto adapter
>> >> mode,
>> >0
>> >> for OP_NEW and 1 for OP_FORWARD.
>> >>
>> >> This mode can be used to measure the performance of crypto adapter.
>> >>
>> >> Example:
>> >>   ./dpdk-test-eventdev -l 0-2 -w  -w  -- \
>> >>   --prod_type_cryptodev --crypto_adptr_mode 1 --test=perf_atq \
>> >>   --stlist=a --wlcores 1 --plcores 2
>> >
>> >This patch has some perf failure as shown below. Could you please look into
>> this?
>> >105300 --> performance testing fail
>> >
>> >Test environment and result as below:
>> >
>> >Ubuntu 20.04
>> >Kernel: 4.15.0-generic
>> >Compiler: gcc 7.4
>> >NIC: Intel Corporation Ethernet Converged Network Adapter 82599ES 1
>> >Mbps
>> >Target: x86_64-native-linuxapp-gcc
>> >Fail/Total: 0/4
>> >
>> >Detail performance results:
>> >++-+--+-+--+
>> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
>> >| difference from
>> >|
>> >|| |  | |   expected
>> >   |
>>
>>++=+==+=+
>=
>> >=+
>> >| 64 | 512 | 1| 1   | 0.3%  
>> >   |
>> >++-+--+-+--+
>> >| 64 | 2048| 1| 1   | -0.2% 
>> >   |
>> >++-+--+-+--+
>> >| 64 | 512 | 1| 2   | 0.0%  
>> >   |
>> >++-+--+-+--+
>> >| 64 | 2048| 1| 2   | 0.3%  
>> >   |
>> >++-+--+-+--+
>> >
>> >Ubuntu 20.04
>> >Kernel: 4.15.0-generic
>> >Compiler: gcc 7.4
>> >NIC: Intel Corporation Ethernet Converged Network Adapter XL710-QDA2
>> >4 Mbps
>> >Target: x86_64-native-linuxapp-gcc
>> >Fail/Total: 1/4
>> >
>> >Detail performance results:
>> >++-+--+-+--+
>> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
>> >| difference from
>> >|
>> >|| |  | |   expected
>> >   |
>>
>>++=+==+=+
>=
>> >=+
>> >| 64 | 512 | 1| 1   | 0.2%  
>> >   |
>> >++-+--+-+--+
>> >| 64 | 2048| 1| 1   | -0.7% 
>> >   |
>> >++-+--+-+--+
>> >| 64 | 512 | 1| 2   | -1.5% 
>> >   |
>> >++-+--+-+--+
>> >| 64 | 2048| 1| 2   | -5.3% 
>> >   |
>> >++-+--+-+--+
>> >
>> >Ubuntu 20.04 ARM
>> >Kernel: 4.15.0-132-generic
>> >Compiler: gcc 7.5
>> >NIC: Arm Intel Corporation Ethernet Converged Network Adapter
>> >XL710-QDA2
>> >4 Mbps
>> >Target: x86_64-native-linuxapp-gcc
>> >Fail/Total: 0/2
>> >
>> >Detail performance results:
>> >++-+--+-+--+
>> >| frame_size | txd/rxd | num_cpus | num_threads |  throughput
>> >| difference from
>> >|
>> >|| |  | |   expected
>> >   |
>>
>>++=+==+=+
>=
>> >=+
>> >| 64 | 512 | 1| 1   | 0.1%  
>> >   |
>> >++-+--+-+--+
>> >| 64 | 2048| 1| 1   | -0.5% 
>> >   |
>> >++-+--+-+--+
>> >
>> >To view detailed results, visit:
>> >https://urldefense.proofpoint.com/v2/url?u=https-
>>
>>3A__lab.dpdk.org_results_dashboard_patchsets_20534_&d=DwIFAg&c=nKjWe
>> c2
>> >b6R0mOyPaz7xtfQ&r=G9w4KsPaQLACBfGCL35PtiRH996yqJDxAZwrWegU2qQ&
>> m=
>>
>>dPDgmKiLC_KqhgjwZrodyFlBdlFPgckVr9IW0c7t2cIHpkw6u9pGqgElFqqwuU1v&s
>> =E
>> >ajYUFziZY27q6LB4p5sOGuFlty3VlOjbMsLXaQ5MeI&e=
>> >
>>
>> Performance regression is reported by nic_sing

[PATCH v3 00/15] features and fixes on NXP eth devices

[nipun . gupta]

From: Nipun Gupta 

This series adds few features and important fixes on DPAA,
PFE and ENETC devices.

Features added:
- level 2 support for shaping on DPAA2
- loopback configuration for DPNI devices on DPAA2
- Multiple TXQ's enqueue for ordered queues for performance
- VFs support on ENETC

Fixes:
- fix unregistering interrupt handler on DPAA2
- fix timestamping for IEEE1588 on DPAA1

Changes in v2:
- fix checkpatch errors

Changes in v3:
- remove unrequired PFE HW checksum patch
- use predefined API for adding delay
- use macro value for allocating mbuf in event

Apeksha Gupta (1):
  net/pfe: remove setting unused value

Gagandeep Singh (3):
  net/dpaa2: add support for level 2 in traffic management
  net/enetc: add support for VFs
  net/pfe: reduce driver initialization time

Jun Yang (4):
  net/dpaa2: support multiple txqs en-queue for ordered
  net/dpaa2: secondary process handling for dpni
  bus/fslmc: add and scan dprc devices
  net/dpaa2: support recycle loopback port

Nipun Gupta (4):
  bus/fslmc: update MC to 10.29
  bus/fslmc: use dmb oshst for synchronization before I/O
  net/dpaa: check status before configuring shared MAC
  net/dpaa: enable checksum for shared MAC interface

Rohit Raj (1):
  net/dpaa2: warn user in case of high nb desc

Vanshika Shukla (2):
  net/dpaa2: fix unregistering interrupt handler
  net/dpaa2: fix timestamping for IEEE1588

 doc/guides/nics/dpaa2.rst |   2 +-
 drivers/bus/dpaa/base/fman/fman_hw.c  |  11 +
 drivers/bus/dpaa/include/fsl_fman.h   |   2 +
 drivers/bus/dpaa/version.map  |   1 +
 drivers/bus/fslmc/fslmc_bus.c |  15 +-
 drivers/bus/fslmc/fslmc_vfio.c|  18 +-
 drivers/bus/fslmc/mc/dprc.c   | 129 
 drivers/bus/fslmc/mc/fsl_dpmng.h  |   2 +-
 drivers/bus/fslmc/mc/fsl_dprc.h   |  46 ++
 drivers/bus/fslmc/mc/fsl_dprc_cmd.h   |  48 ++
 drivers/bus/fslmc/meson.build |   4 +-
 drivers/bus/fslmc/portal/dpaa2_hw_dprc.c  | 100 +++
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h   |  15 +-
 drivers/bus/fslmc/qbman/include/compat.h  |   4 +-
 drivers/bus/fslmc/rte_fslmc.h |  10 +-
 drivers/event/dpaa2/dpaa2_eventdev.c  |  12 +-
 drivers/mempool/dpaa2/dpaa2_hw_mempool.c  |  23 +
 drivers/mempool/dpaa2/rte_dpaa2_mempool.h |  15 +
 drivers/mempool/dpaa2/version.map |   1 +
 drivers/net/dpaa/dpaa_ethdev.c|  17 +-
 drivers/net/dpaa2/base/dpaa2_hw_dpni.c|   5 +-
 drivers/net/dpaa2/dpaa2_ethdev.c  | 117 +++-
 drivers/net/dpaa2/dpaa2_ethdev.h  |  38 +-
 drivers/net/dpaa2/dpaa2_ptp.c |   8 +-
 drivers/net/dpaa2/dpaa2_recycle.c | 780 ++
 drivers/net/dpaa2/dpaa2_rxtx.c| 181 -
 drivers/net/dpaa2/dpaa2_tm.c  | 563 +---
 drivers/net/dpaa2/dpaa2_tm.h  |  17 +-
 drivers/net/dpaa2/mc/dpdmux.c |   8 +
 drivers/net/dpaa2/mc/dpkg.c   |   7 +-
 drivers/net/dpaa2/mc/dpni.c   | 417 
 drivers/net/dpaa2/mc/fsl_dpdmux.h |   3 +
 drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h |   5 +-
 drivers/net/dpaa2/mc/fsl_dpni.h   | 173 +++--
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h   | 137 ++--
 drivers/net/dpaa2/meson.build |   1 +
 drivers/net/dpaa2/version.map |   1 +
 drivers/net/enetc/enetc_ethdev.c  |  25 +-
 drivers/net/pfe/pfe_ethdev.c  |   3 +-
 drivers/net/pfe/pfe_hif.c |   4 +-
 40 files changed, 2519 insertions(+), 449 deletions(-)
 create mode 100644 drivers/bus/fslmc/mc/dprc.c
 create mode 100644 drivers/bus/fslmc/mc/fsl_dprc.h
 create mode 100644 drivers/bus/fslmc/mc/fsl_dprc_cmd.h
 create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dprc.c
 create mode 100644 drivers/net/dpaa2/dpaa2_recycle.c

-- 
2.17.1

[PATCH v3 01/15] bus/fslmc: update MC to 10.29

[nipun . gupta]

From: Nipun Gupta 

update MC firmware library version to 10.29

Signed-off-by: Nipun Gupta 
Signed-off-by: Gagandeep Singh 
---
 drivers/bus/fslmc/mc/fsl_dpmng.h  |   2 +-
 drivers/net/dpaa2/mc/dpdmux.c |   8 ++
 drivers/net/dpaa2/mc/dpkg.c   |   7 +-
 drivers/net/dpaa2/mc/dpni.c   | 111 --
 drivers/net/dpaa2/mc/fsl_dpdmux.h |   3 +
 drivers/net/dpaa2/mc/fsl_dpdmux_cmd.h |   5 +-
 drivers/net/dpaa2/mc/fsl_dpni.h   |  54 ++---
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h   |  57 +++--
 8 files changed, 181 insertions(+), 66 deletions(-)

diff --git a/drivers/bus/fslmc/mc/fsl_dpmng.h b/drivers/bus/fslmc/mc/fsl_dpmng.h
index 7e9bd96429..073d47efbf 100644
--- a/drivers/bus/fslmc/mc/fsl_dpmng.h
+++ b/drivers/bus/fslmc/mc/fsl_dpmng.h
@@ -20,7 +20,7 @@ struct fsl_mc_io;
  * Management Complex firmware version information
  */
 #define MC_VER_MAJOR 10
-#define MC_VER_MINOR 28
+#define MC_VER_MINOR 29
 
 /**
  * struct mc_version
diff --git a/drivers/net/dpaa2/mc/dpdmux.c b/drivers/net/dpaa2/mc/dpdmux.c
index edbb01b45b..1bb153cad7 100644
--- a/drivers/net/dpaa2/mc/dpdmux.c
+++ b/drivers/net/dpaa2/mc/dpdmux.c
@@ -398,6 +398,9 @@ int dpdmux_get_attributes(struct fsl_mc_io *mc_io,
attr->num_ifs = le16_to_cpu(rsp_params->num_ifs);
attr->mem_size = le16_to_cpu(rsp_params->mem_size);
attr->default_if = le16_to_cpu(rsp_params->default_if);
+   attr->max_dmat_entries = le16_to_cpu(rsp_params->max_dmat_entries);
+   attr->max_mc_groups = le16_to_cpu(rsp_params->max_mc_groups);
+   attr->max_vlan_ids = le16_to_cpu(rsp_params->max_vlan_ids);
 
return 0;
 }
@@ -470,6 +473,11 @@ int dpdmux_if_disable(struct fsl_mc_io *mc_io,
  * will be updated with the minimum value of the mfls of the connected
  * dpnis and the actual value of dmux mfl.
  *
+ * If dpdmux object is created using DPDMUX_OPT_AUTO_MAX_FRAME_LEN and maximum
+ * frame length is changed for a dpni connected to dpdmux interface the change
+ * is propagated through dpdmux interfaces and will overwrite the value set 
using
+ * this API.
+ *
  * Return: '0' on Success; Error code otherwise.
  */
 int dpdmux_set_max_frame_length(struct fsl_mc_io *mc_io,
diff --git a/drivers/net/dpaa2/mc/dpkg.c b/drivers/net/dpaa2/mc/dpkg.c
index 1e171eedc7..4789976b7d 100644
--- a/drivers/net/dpaa2/mc/dpkg.c
+++ b/drivers/net/dpaa2/mc/dpkg.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
  *
- * Copyright 2017 NXP
+ * Copyright 2017-2021 NXP
  *
  */
 #include 
@@ -63,10 +63,7 @@ dpkg_prepare_key_cfg(const struct dpkg_profile_cfg *cfg, 
uint8_t *key_cfg_buf)
dpkg_set_field(extr->extract_type, EXTRACT_TYPE,
   cfg->extracts[i].type);
 
-   if (extr->num_of_byte_masks > DPKG_NUM_OF_MASKS)
-   return -EINVAL;
-
-   for (j = 0; j < extr->num_of_byte_masks; j++) {
+   for (j = 0; j < DPKG_NUM_OF_MASKS; j++) {
extr->masks[j].mask = cfg->extracts[i].masks[j].mask;
extr->masks[j].offset =
cfg->extracts[i].masks[j].offset;
diff --git a/drivers/net/dpaa2/mc/dpni.c b/drivers/net/dpaa2/mc/dpni.c
index 60048d6c43..cf78295d90 100644
--- a/drivers/net/dpaa2/mc/dpni.c
+++ b/drivers/net/dpaa2/mc/dpni.c
@@ -128,6 +128,7 @@ int dpni_create(struct fsl_mc_io *mc_io,
cmd_params->num_cgs = cfg->num_cgs;
cmd_params->num_opr = cfg->num_opr;
cmd_params->dist_key_size = cfg->dist_key_size;
+   cmd_params->num_channels = cfg->num_channels;
 
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
@@ -203,7 +204,7 @@ int dpni_set_pools(struct fsl_mc_io *mc_io,
cmd_params = (struct dpni_cmd_set_pools *)cmd.params;
cmd_params->num_dpbp = cfg->num_dpbp;
cmd_params->pool_options = cfg->pool_options;
-   for (i = 0; i < cmd_params->num_dpbp; i++) {
+   for (i = 0; i < DPNI_MAX_DPBP; i++) {
cmd_params->pool[i].dpbp_id =
cpu_to_le16(cfg->pools[i].dpbp_id);
cmd_params->pool[i].priority_mask =
@@ -592,6 +593,7 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io,
attr->num_tx_tcs = rsp_params->num_tx_tcs;
attr->mac_filter_entries = rsp_params->mac_filter_entries;
attr->vlan_filter_entries = rsp_params->vlan_filter_entries;
+   attr->num_channels = rsp_params->num_channels;
attr->qos_entries = rsp_params->qos_entries;
attr->fs_entries = le16_to_cpu(rsp_params->fs_entries);
attr->qos_key_size = rsp_params->qos_key_size;
@@ -815,6 +817,9 @@ int dpni_get_offload(struct fsl_mc_io *mc_io,
  * in all enqueue operations
  *
  * Return: '0' on Success; Error code otherwise.
+ *
+ * If dpni object is created using multiple Tc channels this function will 
return
+ * qdid value for the first channel
  */
 int dpni_

[PATCH v3 02/15] bus/fslmc: use dmb oshst for synchronization before I/O

[nipun . gupta]

From: Nipun Gupta 

Outer Shareable Store (oshst) is sufficient for Data Memory
Barrier (dmb) when doing IO on the interface via QBMAN.

This will sync L3/DDR with the L1/L2 cached data.

Signed-off-by: Nipun Gupta 
---
 drivers/bus/fslmc/qbman/include/compat.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/bus/fslmc/qbman/include/compat.h 
b/drivers/bus/fslmc/qbman/include/compat.h
index a4471a80af..ece5da5906 100644
--- a/drivers/bus/fslmc/qbman/include/compat.h
+++ b/drivers/bus/fslmc/qbman/include/compat.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  * Copyright (c) 2008-2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017,2021 NXP
  *
  */
 
@@ -81,7 +81,7 @@ do { \
 #define __raw_readl(p) (*(const volatile unsigned int *)(p))
 #define __raw_writel(v, p) {*(volatile unsigned int *)(p) = (v); }
 
-#define dma_wmb()  rte_smp_mb()
+#define dma_wmb()  rte_io_wmb()
 
 #define atomic_trte_atomic32_t
 #define atomic_read(v)  rte_atomic32_read(v)
-- 
2.17.1

[PATCH v3 03/15] net/dpaa2: warn user in case of high nb desc

[nipun . gupta]

From: Rohit Raj 

Added warning message if application is configuring nb_desc
more than supported by PEB memory suggesting user to configure
HW descriptors in normal memory rather than in faster PEB
memory.

Signed-off-by: Rohit Raj 
---
 drivers/net/dpaa2/dpaa2_ethdev.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index a3706439d5..f5cac8f9d9 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -74,6 +74,9 @@ int dpaa2_timestamp_dynfield_offset = -1;
 /* Enable error queue */
 bool dpaa2_enable_err_queue;
 
+#define MAX_NB_RX_DESC 11264
+int total_nb_rx_desc;
+
 struct rte_dpaa2_xstats_name_off {
char name[RTE_ETH_XSTATS_NAME_SIZE];
uint8_t page_id; /* dpni statistics page id */
@@ -694,6 +697,13 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
dev, rx_queue_id, mb_pool, rx_conf);
 
+   total_nb_rx_desc += nb_rx_desc;
+   if (total_nb_rx_desc > MAX_NB_RX_DESC) {
+   DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use 
Normal buffers",
+  MAX_NB_RX_DESC);
+   DPAA2_PMD_WARN("To use Normal buffers, run 'export 
DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
+   }
+
/* Rx deferred start is not supported */
if (rx_conf->rx_deferred_start) {
DPAA2_PMD_ERR("%p:Rx deferred start not supported",
@@ -984,6 +994,9 @@ dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, 
uint16_t rx_queue_id)
 
memset(&cfg, 0, sizeof(struct dpni_queue));
PMD_INIT_FUNC_TRACE();
+
+   total_nb_rx_desc -= dpaa2_q->nb_desc;
+
if (dpaa2_q->cgid != 0xff) {
options = DPNI_QUEUE_OPT_CLEAR_CGID;
cfg.cgid = dpaa2_q->cgid;
-- 
2.17.1

[PATCH v3 04/15] net/dpaa2: fix unregistering interrupt handler

[nipun . gupta]

From: Vanshika Shukla 

This patch fixes code that handles unregistering LSC
interrupt handler in dpaa2_dev_stop API.

Fixes: c5acbb5ea20e ("net/dpaa2: support link status event")
Cc: sta...@dpdk.org

Signed-off-by: Vanshika Shukla 
---
 drivers/net/dpaa2/dpaa2_ethdev.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index f5cac8f9d9..18ff07249f 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -1265,7 +1265,12 @@ dpaa2_dev_stop(struct rte_eth_dev *dev)
struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
int ret;
struct rte_eth_link link;
-   struct rte_intr_handle *intr_handle = dev->intr_handle;
+   struct rte_device *rdev = dev->device;
+   struct rte_intr_handle *intr_handle;
+   struct rte_dpaa2_device *dpaa2_dev;
+
+   dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
+   intr_handle = dpaa2_dev->intr_handle;
 
PMD_INIT_FUNC_TRACE();
 
-- 
2.17.1

[PATCH v3 05/15] net/dpaa2: fix timestamping for IEEE1588

[nipun . gupta]

From: Vanshika Shukla 

The current implementation of DPAA2 driver code is such
that it records Rx and Tx timestamp for PTP without checking
if they are PTP packets or not. Packets for which
RTE_MBUF_F_RX_IEEE1588_TMST and RTE_MBUF_F_TX_IEEE1588_TMST
is not set, Rx and Tx timestamp should not be recorded.

This patch fixes this issue by checking if the required
flags are set in the mbuf before recording timestamps.

Also this change defines separate values for
DPAA2_TX_CONF_ENABLE and DPAA2_NO_PREFETCH_RX

Fixes: e806bf878c17 ("net/dpaa2: support timestamp")
Cc: sta...@dpdk.org

Signed-off-by: Vanshika Shukla 
---
 drivers/net/dpaa2/dpaa2_ethdev.h |  2 +-
 drivers/net/dpaa2/dpaa2_ptp.c|  8 ---
 drivers/net/dpaa2/dpaa2_rxtx.c   | 39 +---
 3 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index c5e9267bf0..c21571e63d 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -62,7 +62,7 @@
 /* Disable RX tail drop, default is enable */
 #define DPAA2_RX_TAILDROP_OFF  0x04
 /* Tx confirmation enabled */
-#define DPAA2_TX_CONF_ENABLE   0x08
+#define DPAA2_TX_CONF_ENABLE   0x06
 
 #define DPAA2_RSS_OFFLOAD_ALL ( \
RTE_ETH_RSS_L2_PAYLOAD | \
diff --git a/drivers/net/dpaa2/dpaa2_ptp.c b/drivers/net/dpaa2/dpaa2_ptp.c
index 8d79e39244..3a4536dd69 100644
--- a/drivers/net/dpaa2/dpaa2_ptp.c
+++ b/drivers/net/dpaa2/dpaa2_ptp.c
@@ -111,10 +111,12 @@ int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev 
*dev,
 {
struct dpaa2_dev_priv *priv = dev->data->dev_private;
 
-   if (priv->next_tx_conf_queue)
-   dpaa2_dev_tx_conf(priv->next_tx_conf_queue);
-   else
+   if (priv->next_tx_conf_queue) {
+   while (!priv->tx_timestamp)
+   dpaa2_dev_tx_conf(priv->next_tx_conf_queue);
+   } else {
return -1;
+   }
*timestamp = rte_ns_to_timespec(priv->tx_timestamp);
 
return 0;
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index c65589a5f3..ee3ed1b152 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -140,8 +140,10 @@ dpaa2_dev_rx_parse_slow(struct rte_mbuf *mbuf,
annotation->word3, annotation->word4);
 
 #if defined(RTE_LIBRTE_IEEE1588)
-   if (BIT_ISSET_AT_POS(annotation->word1, DPAA2_ETH_FAS_PTP))
+   if (BIT_ISSET_AT_POS(annotation->word1, DPAA2_ETH_FAS_PTP)) {
mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_TMST;
+   }
 #endif
 
if (BIT_ISSET_AT_POS(annotation->word3, L2_VLAN_1_PRESENT)) {
@@ -769,7 +771,10 @@ dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, 
uint16_t nb_pkts)
else
bufs[num_rx] = eth_fd_to_mbuf(fd, eth_data->port_id);
 #if defined(RTE_LIBRTE_IEEE1588)
-   priv->rx_timestamp = *dpaa2_timestamp_dynfield(bufs[num_rx]);
+   if (bufs[num_rx]->ol_flags & PKT_RX_IEEE1588_TMST) {
+   priv->rx_timestamp =
+   *dpaa2_timestamp_dynfield(bufs[num_rx]);
+   }
 #endif
 
if (eth_data->dev_conf.rxmode.offloads &
@@ -986,6 +991,13 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t 
nb_pkts)
bufs[num_rx] = eth_fd_to_mbuf(fd,
eth_data->port_id);
 
+#if defined(RTE_LIBRTE_IEEE1588)
+   if (bufs[num_rx]->ol_flags & PKT_RX_IEEE1588_TMST) {
+   priv->rx_timestamp =
+   *dpaa2_timestamp_dynfield(bufs[num_rx]);
+   }
+#endif
+
if (eth_data->dev_conf.rxmode.offloads &
RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
rte_vlan_strip(bufs[num_rx]);
@@ -1021,6 +1033,8 @@ uint16_t dpaa2_dev_tx_conf(void *queue)
struct rte_eth_dev_data *eth_data = dpaa2_q->eth_data;
struct dpaa2_dev_priv *priv = eth_data->dev_private;
struct dpaa2_annot_hdr *annotation;
+   void *v_addr;
+   struct rte_mbuf *mbuf;
 #endif
 
if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
@@ -1105,10 +1119,16 @@ uint16_t dpaa2_dev_tx_conf(void *queue)
num_tx_conf++;
num_pulled++;
 #if defined(RTE_LIBRTE_IEEE1588)
-   annotation = (struct dpaa2_annot_hdr *)((size_t)
-   DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) +
-   DPAA2_FD_PTA_SIZE);
-   priv->tx_timestamp = annotation->word2;
+   v_addr = DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd));
+   mbuf = DPAA2_INLINE_MBUF_FROM_BUF(v_addr,
+   
rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_d

[PATCH v3 06/15] net/dpaa2: support multiple txqs en-queue for ordered

[nipun . gupta]

From: Jun Yang 

Support the tx enqueue in order queue mode, where queue id
for each event may be different.

Signed-off-by: Jun Yang 
---
 drivers/event/dpaa2/dpaa2_eventdev.c |  12 ++-
 drivers/net/dpaa2/dpaa2_ethdev.h |   4 +
 drivers/net/dpaa2/dpaa2_rxtx.c   | 142 +++
 drivers/net/dpaa2/version.map|   1 +
 4 files changed, 155 insertions(+), 4 deletions(-)

diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c 
b/drivers/event/dpaa2/dpaa2_eventdev.c
index 4d94c315d2..ffc7b8b073 100644
--- a/drivers/event/dpaa2/dpaa2_eventdev.c
+++ b/drivers/event/dpaa2/dpaa2_eventdev.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2017,2019 NXP
+ * Copyright 2017,2019-2021 NXP
  */
 
 #include 
@@ -1003,16 +1003,20 @@ dpaa2_eventdev_txa_enqueue(void *port,
   struct rte_event ev[],
   uint16_t nb_events)
 {
-   struct rte_mbuf *m = (struct rte_mbuf *)ev[0].mbuf;
+   void *txq[DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH];
+   struct rte_mbuf *m[DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH];
uint8_t qid, i;
 
RTE_SET_USED(port);
 
for (i = 0; i < nb_events; i++) {
-   qid = rte_event_eth_tx_adapter_txq_get(m);
-   rte_eth_tx_burst(m->port, qid, &m, 1);
+   m[i] = (struct rte_mbuf *)ev[i].mbuf;
+   qid = rte_event_eth_tx_adapter_txq_get(m[i]);
+   txq[i] = rte_eth_devices[m[i]->port].data->tx_queues[qid];
}
 
+   dpaa2_dev_tx_multi_txq_ordered(txq, m, nb_events);
+
return nb_events;
 }
 
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index c21571e63d..e001a7e49d 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -241,6 +241,10 @@ void dpaa2_dev_process_ordered_event(struct qbman_swp *swp,
 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,
  uint16_t nb_pkts);
+__rte_internal
+uint16_t dpaa2_dev_tx_multi_txq_ordered(void **queue,
+   struct rte_mbuf **bufs, uint16_t nb_pkts);
+
 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);
 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);
 void dpaa2_flow_clean(struct rte_eth_dev *dev);
diff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c
index ee3ed1b152..1096b1cf1d 100644
--- a/drivers/net/dpaa2/dpaa2_rxtx.c
+++ b/drivers/net/dpaa2/dpaa2_rxtx.c
@@ -1468,6 +1468,148 @@ dpaa2_set_enqueue_descriptor(struct dpaa2_queue 
*dpaa2_q,
*dpaa2_seqn(m) = DPAA2_INVALID_MBUF_SEQN;
 }
 
+uint16_t
+dpaa2_dev_tx_multi_txq_ordered(void **queue,
+   struct rte_mbuf **bufs, uint16_t nb_pkts)
+{
+   /* Function to transmit the frames to multiple queues respectively.*/
+   uint32_t loop, retry_count;
+   int32_t ret;
+   struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
+   uint32_t frames_to_send;
+   struct rte_mempool *mp;
+   struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
+   struct dpaa2_queue *dpaa2_q[MAX_TX_RING_SLOTS];
+   struct qbman_swp *swp;
+   uint16_t bpid;
+   struct rte_mbuf *mi;
+   struct rte_eth_dev_data *eth_data;
+   struct dpaa2_dev_priv *priv;
+   struct dpaa2_queue *order_sendq;
+
+   if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
+   ret = dpaa2_affine_qbman_swp();
+   if (ret) {
+   DPAA2_PMD_ERR(
+   "Failed to allocate IO portal, tid: %d\n",
+   rte_gettid());
+   return 0;
+   }
+   }
+   swp = DPAA2_PER_LCORE_PORTAL;
+
+   for (loop = 0; loop < nb_pkts; loop++) {
+   dpaa2_q[loop] = (struct dpaa2_queue *)queue[loop];
+   eth_data = dpaa2_q[loop]->eth_data;
+   priv = eth_data->dev_private;
+   qbman_eq_desc_clear(&eqdesc[loop]);
+   if (*dpaa2_seqn(*bufs) && priv->en_ordered) {
+   order_sendq = (struct dpaa2_queue *)priv->tx_vq[0];
+   dpaa2_set_enqueue_descriptor(order_sendq,
+(*bufs),
+&eqdesc[loop]);
+   } else {
+   qbman_eq_desc_set_no_orp(&eqdesc[loop],
+DPAA2_EQ_RESP_ERR_FQ);
+   qbman_eq_desc_set_fq(&eqdesc[loop],
+dpaa2_q[loop]->fqid);
+   }
+
+   retry_count = 0;
+   while (qbman_result_SCN_state(dpaa2_q[loop]->cscn)) {
+   retry_count++;
+   /* Retry for some time before giving up */
+   if (retry_count > CONG_RETRY_COUNT)
+ 

[PATCH v3 07/15] net/dpaa2: add support for level 2 in traffic management

[nipun . gupta]

From: Gagandeep Singh 

This patch adds support for level 2 for QoS shaping.

Signed-off-by: Gagandeep Singh 
---
 doc/guides/nics/dpaa2.rst   |   2 +-
 drivers/net/dpaa2/dpaa2_ethdev.c|  55 ++-
 drivers/net/dpaa2/dpaa2_ethdev.h|   6 +-
 drivers/net/dpaa2/dpaa2_tm.c| 563 ++--
 drivers/net/dpaa2/dpaa2_tm.h|  17 +-
 drivers/net/dpaa2/mc/dpni.c | 302 +--
 drivers/net/dpaa2/mc/fsl_dpni.h | 119 +++---
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h |  79 ++--
 8 files changed, 791 insertions(+), 352 deletions(-)

diff --git a/doc/guides/nics/dpaa2.rst b/doc/guides/nics/dpaa2.rst
index 831bc56488..2d113f53df 100644
--- a/doc/guides/nics/dpaa2.rst
+++ b/doc/guides/nics/dpaa2.rst
@@ -588,7 +588,7 @@ Supported Features
 
 The following capabilities are supported:
 
-- Level0 (root node) and Level1 are supported.
+- Level0 (root node), Level1 and Level2 are supported.
 - 1 private shaper at root node (port level) is supported.
 - 8 TX queues per port supported (1 channel per port)
 - Both SP and WFQ scheduling mechanisms are supported on all 8 queues.
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 18ff07249f..b91e773605 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -852,6 +852,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
struct dpni_queue tx_conf_cfg;
struct dpni_queue tx_flow_cfg;
uint8_t options = 0, flow_id;
+   uint16_t channel_id;
struct dpni_queue_id qid;
uint32_t tc_id;
int ret;
@@ -877,20 +878,6 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 
-   tc_id = tx_queue_id;
-   flow_id = 0;
-
-   ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
-   tc_id, flow_id, options, &tx_flow_cfg);
-   if (ret) {
-   DPAA2_PMD_ERR("Error in setting the tx flow: "
-   "tc_id=%d, flow=%d err=%d",
-   tc_id, flow_id, ret);
-   return -1;
-   }
-
-   dpaa2_q->flow_id = flow_id;
-
if (tx_queue_id == 0) {
/*Set tx-conf and error configuration*/
if (priv->flags & DPAA2_TX_CONF_ENABLE)
@@ -907,10 +894,26 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
return -1;
}
}
+
+   tc_id = tx_queue_id % priv->num_tx_tc;
+   channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % 
priv->num_channels;
+   flow_id = 0;
+
+   ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
+   ((channel_id << 8) | tc_id), flow_id, options, 
&tx_flow_cfg);
+   if (ret) {
+   DPAA2_PMD_ERR("Error in setting the tx flow: "
+   "tc_id=%d, flow=%d err=%d",
+   tc_id, flow_id, ret);
+   return -1;
+   }
+
+   dpaa2_q->flow_id = flow_id;
+
dpaa2_q->tc_index = tc_id;
 
ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
-DPNI_QUEUE_TX, dpaa2_q->tc_index,
+DPNI_QUEUE_TX, ((channel_id << 8) | 
dpaa2_q->tc_index),
 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
if (ret) {
DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
@@ -942,7 +945,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
   priv->token,
   DPNI_QUEUE_TX,
-  tc_id,
+  ((channel_id << 8) | 
tc_id),
   &cong_notif_cfg);
if (ret) {
DPAA2_PMD_ERR(
@@ -959,7 +962,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
options = options | DPNI_QUEUE_OPT_USER_CTX;
tx_conf_cfg.user_context = (size_t)(dpaa2_q);
ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
-DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | 
dpaa2_tx_conf_q->tc_index),
 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
if (ret) {
DPAA2_PMD_ERR("Error in setting the tx conf flow: "
@@ -970,7 +973,7 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
}
 
ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
-DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
+DPNI_QUEUE

[PATCH v3 08/15] net/dpaa2: secondary process handling for dpni

[nipun . gupta]

From: Jun Yang 

This change uses 'dev->process_private' instead of 'priv->hw'
to get dpmcp per process while setting flow distribution,
as priv->hw is only valid for primary process.
It also initialize rte_dpaa2_bpid_info in secondary process.

Signed-off-by: Jun Yang 
---
 drivers/mempool/dpaa2/dpaa2_hw_mempool.c  | 23 +++
 drivers/mempool/dpaa2/rte_dpaa2_mempool.h | 15 +++
 drivers/mempool/dpaa2/version.map |  1 +
 drivers/net/dpaa2/base/dpaa2_hw_dpni.c|  5 ++---
 drivers/net/dpaa2/dpaa2_ethdev.c  | 10 --
 drivers/net/dpaa2/dpaa2_ethdev.h  |  3 ++-
 6 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c 
b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
index 39c6252a63..56c629c681 100644
--- a/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
+++ b/drivers/mempool/dpaa2/dpaa2_hw_mempool.c
@@ -263,6 +263,29 @@ rte_dpaa2_mbuf_release(struct rte_mempool *pool 
__rte_unused,
}
 }
 
+int rte_dpaa2_bpid_info_init(struct rte_mempool *mp)
+{
+   struct dpaa2_bp_info *bp_info = mempool_to_bpinfo(mp);
+   uint32_t bpid = bp_info->bpid;
+
+   if (!rte_dpaa2_bpid_info) {
+   rte_dpaa2_bpid_info = (struct dpaa2_bp_info *)rte_malloc(NULL,
+ sizeof(struct dpaa2_bp_info) * MAX_BPID,
+ RTE_CACHE_LINE_SIZE);
+   if (rte_dpaa2_bpid_info == NULL)
+   return -ENOMEM;
+   memset(rte_dpaa2_bpid_info, 0,
+  sizeof(struct dpaa2_bp_info) * MAX_BPID);
+   }
+
+   rte_dpaa2_bpid_info[bpid].meta_data_size = sizeof(struct rte_mbuf)
+   + rte_pktmbuf_priv_size(mp);
+   rte_dpaa2_bpid_info[bpid].bp_list = bp_info->bp_list;
+   rte_dpaa2_bpid_info[bpid].bpid = bpid;
+
+   return 0;
+}
+
 uint16_t
 rte_dpaa2_mbuf_pool_bpid(struct rte_mempool *mp)
 {
diff --git a/drivers/mempool/dpaa2/rte_dpaa2_mempool.h 
b/drivers/mempool/dpaa2/rte_dpaa2_mempool.h
index 4a22b7c42e..28dea74326 100644
--- a/drivers/mempool/dpaa2/rte_dpaa2_mempool.h
+++ b/drivers/mempool/dpaa2/rte_dpaa2_mempool.h
@@ -46,6 +46,21 @@ rte_dpaa2_mbuf_pool_bpid(struct rte_mempool *mp);
 struct rte_mbuf *
 rte_dpaa2_mbuf_from_buf_addr(struct rte_mempool *mp, void *buf_addr);
 
+/**
+ * Initialize the rte_dpaa2_bpid_info
+ * In generial, it is called in the secondary process and
+ * mp has been created in the primary process.
+ *
+ * @param mp
+ *   memory pool
+ *
+ * @return
+ *  - 0 on success.
+ *  - (<0) on failure.
+ */
+__rte_internal
+int rte_dpaa2_bpid_info_init(struct rte_mempool *mp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/drivers/mempool/dpaa2/version.map 
b/drivers/mempool/dpaa2/version.map
index 49c460ec54..cfd4ae617a 100644
--- a/drivers/mempool/dpaa2/version.map
+++ b/drivers/mempool/dpaa2/version.map
@@ -11,5 +11,6 @@ INTERNAL {
global:
 
rte_dpaa2_bpid_info;
+   rte_dpaa2_bpid_info_init;
rte_dpaa2_mbuf_alloc_bulk;
 };
diff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c 
b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
index 3170694841..9509f6e8a3 100644
--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni.c
@@ -95,7 +95,7 @@ dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev,
uint64_t req_dist_set, int tc_index)
 {
struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
-   struct fsl_mc_io *dpni = priv->hw;
+   struct fsl_mc_io *dpni = eth_dev->process_private;
struct dpni_rx_dist_cfg tc_cfg;
struct dpkg_profile_cfg kg_cfg;
void *p_params;
@@ -457,13 +457,12 @@ dpaa2_distset_to_dpkg_profile_cfg(
 
 int
 dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv,
-void *blist)
+   struct fsl_mc_io *dpni, void *blist)
 {
/* Function to attach a DPNI with a buffer pool list. Buffer pool list
 * handle is passed in blist.
 */
int32_t retcode;
-   struct fsl_mc_io *dpni = priv->hw;
struct dpni_pools_cfg bpool_cfg;
struct dpaa2_bp_list *bp_list = (struct dpaa2_bp_list *)blist;
struct dpni_buffer_layout layout;
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index b91e773605..a45beed75f 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include "rte_dpaa2_mempool.h"
 
 #include "dpaa2_pmd_logs.h"
 #include 
@@ -712,9 +713,14 @@ dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
}
 
if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
+   if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
+   ret = rte_dpaa2_bpid_info_init(mb_pool);
+   if (ret)
+   return ret;
+   }
bpid = mempool_to_bpid(mb_pool);
-   ret = dpaa2_attach_bp

[PATCH v3 09/15] bus/fslmc: add and scan dprc devices

[nipun . gupta]

From: Jun Yang 

In order to get connection endpoint of each objects,
scan the dprc object.

Signed-off-by: Jun Yang 
Signed-off-by: Nipun Gupta 
---
 drivers/bus/fslmc/fslmc_bus.c|  15 ++-
 drivers/bus/fslmc/fslmc_vfio.c   |  18 +++-
 drivers/bus/fslmc/mc/dprc.c  | 129 +++
 drivers/bus/fslmc/mc/fsl_dprc.h  |  46 
 drivers/bus/fslmc/mc/fsl_dprc_cmd.h  |  48 +
 drivers/bus/fslmc/meson.build|   4 +-
 drivers/bus/fslmc/portal/dpaa2_hw_dprc.c | 100 ++
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h  |  12 +++
 drivers/bus/fslmc/rte_fslmc.h|  10 +-
 9 files changed, 374 insertions(+), 8 deletions(-)
 create mode 100644 drivers/bus/fslmc/mc/dprc.c
 create mode 100644 drivers/bus/fslmc/mc/fsl_dprc.h
 create mode 100644 drivers/bus/fslmc/mc/fsl_dprc_cmd.h
 create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dprc.c

diff --git a/drivers/bus/fslmc/fslmc_bus.c b/drivers/bus/fslmc/fslmc_bus.c
index a0ef24cdc8..a3c0d838c4 100644
--- a/drivers/bus/fslmc/fslmc_bus.c
+++ b/drivers/bus/fslmc/fslmc_bus.c
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- *   Copyright 2016,2018-2019 NXP
+ *   Copyright 2016,2018-2021 NXP
  *
  */
 
@@ -136,10 +136,6 @@ scan_one_fslmc_device(char *dev_name)
if (!dev_name)
return ret;
 
-   /* Ignore the Container name itself */
-   if (!strncmp("dprc", dev_name, 4))
-   return 0;
-
/* Creating a temporary copy to perform cut-parse over string */
dup_dev_name = strdup(dev_name);
if (!dup_dev_name) {
@@ -197,6 +193,8 @@ scan_one_fslmc_device(char *dev_name)
dev->dev_type = DPAA2_MUX;
else if (!strncmp("dprtc", t_ptr, 5))
dev->dev_type = DPAA2_DPRTC;
+   else if (!strncmp("dprc", t_ptr, 4))
+   dev->dev_type = DPAA2_DPRC;
else
dev->dev_type = DPAA2_UNKNOWN;
 
@@ -339,6 +337,13 @@ rte_fslmc_scan(void)
goto scan_fail;
}
 
+   /* Scan the DPRC container object */
+   ret = scan_one_fslmc_device(fslmc_container);
+   if (ret != 0) {
+   /* Error in parsing directory - exit gracefully */
+   goto scan_fail_cleanup;
+   }
+
while ((entry = readdir(dir)) != NULL) {
if (entry->d_name[0] == '.' || entry->d_type != DT_DIR)
continue;
diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c
index b4704eeae4..1b89a56bbc 100644
--- a/drivers/bus/fslmc/fslmc_vfio.c
+++ b/drivers/bus/fslmc/fslmc_vfio.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2019 NXP
+ *   Copyright 2016-2021 NXP
  *
  */
 
@@ -728,6 +728,7 @@ fslmc_process_iodevices(struct rte_dpaa2_device *dev)
case DPAA2_BPOOL:
case DPAA2_DPRTC:
case DPAA2_MUX:
+   case DPAA2_DPRC:
TAILQ_FOREACH(object, &dpaa2_obj_list, next) {
if (dev->dev_type == object->dev_type)
object->create(dev_fd, &device_info,
@@ -881,6 +882,21 @@ fslmc_vfio_process_group(void)
return -1;
}
 
+   /* Search for DPRC device next as it updates endpoint of
+* other devices.
+*/
+   current_device = 0;
+   RTE_TAILQ_FOREACH_SAFE(dev, &rte_fslmc_bus.device_list, next, dev_temp) 
{
+   if (dev->dev_type == DPAA2_DPRC) {
+   ret = fslmc_process_iodevices(dev);
+   if (ret) {
+   DPAA2_BUS_ERR("Unable to process dprc");
+   return -1;
+   }
+   TAILQ_REMOVE(&rte_fslmc_bus.device_list, dev, next);
+   }
+   }
+
current_device = 0;
RTE_TAILQ_FOREACH_SAFE(dev, &rte_fslmc_bus.device_list, next,
dev_temp) {
diff --git a/drivers/bus/fslmc/mc/dprc.c b/drivers/bus/fslmc/mc/dprc.c
new file mode 100644
index 00..491081c7c8
--- /dev/null
+++ b/drivers/bus/fslmc/mc/dprc.c
@@ -0,0 +1,129 @@
+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
+ *
+ * Copyright 2013-2016 Freescale Semiconductor Inc.
+ * Copyright 2016-2021 NXP
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+
+/** @addtogroup dprc
+ * @{
+ */
+
+/**
+ * dprc_open() - Open DPRC object for use
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @container_id:  Container ID to open
+ * @token: Returned token of DPRC object
+ *
+ * Return: '0' on Success; Error code otherwise.
+ *
+ * @warningRequired before any operation on the object.
+ */
+int dprc_open(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ int container_id,
+ uint

[PATCH v3 10/15] net/dpaa2: support recycle loopback port

[nipun . gupta]

From: Jun Yang 

DPAA2 recycle port is used for configuring the device
in the loopback mode. Loopback configuration can be at
dpni level or at serdes level.

Signed-off-by: Jun Yang 
---
 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h |   3 +-
 drivers/net/dpaa2/dpaa2_ethdev.c|  32 +-
 drivers/net/dpaa2/dpaa2_ethdev.h|  23 +
 drivers/net/dpaa2/dpaa2_recycle.c   | 780 
 drivers/net/dpaa2/mc/dpni.c |  32 +
 drivers/net/dpaa2/mc/fsl_dpni_cmd.h |   1 +
 drivers/net/dpaa2/meson.build   |   1 +
 7 files changed, 870 insertions(+), 2 deletions(-)
 create mode 100644 drivers/net/dpaa2/dpaa2_recycle.c

diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h 
b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
index 8cb4d404aa..4d0f7e4b5d 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
- *   Copyright 2016-2020 NXP
+ *   Copyright 2016-2021 NXP
  *
  */
 
@@ -176,6 +176,7 @@ struct dpaa2_queue {
uint16_t nb_desc;
uint16_t resv;
uint64_t offloads;
+   uint64_t lpbk_cntx;
 } __rte_cache_aligned;
 
 struct swp_active_dqs {
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index a45beed75f..d81f8cb07a 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -668,6 +668,30 @@ dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 
+   if (eth_conf->lpbk_mode) {
+   ret = dpaa2_dev_recycle_config(dev);
+   if (ret) {
+   DPAA2_PMD_ERR("Error to configure %s to recycle port.",
+   dev->data->name);
+
+   return ret;
+   }
+   } else {
+   /** User may disable loopback mode by calling
+* "dev_configure" with lpbk_mode cleared.
+* No matter the port was configured recycle or not,
+* recycle de-configure is called here.
+* If port is not recycled, the de-configure will return 
directly.
+*/
+   ret = dpaa2_dev_recycle_deconfig(dev);
+   if (ret) {
+   DPAA2_PMD_ERR("Error to de-configure recycle port %s.",
+   dev->data->name);
+
+   return ret;
+   }
+   }
+
dpaa2_tm_init(dev);
 
return 0;
@@ -2601,6 +2625,9 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
return -1;
}
 
+   if (eth_dev->data->dev_conf.lpbk_mode)
+   dpaa2_dev_recycle_deconfig(eth_dev);
+
/* Clean the device first */
ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
if (ret) {
@@ -2624,6 +2651,7 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
priv->dist_queues = attr.num_queues;
priv->num_channels = attr.num_channels;
priv->channel_inuse = 0;
+   rte_spinlock_init(&priv->lpbk_qp_lock);
 
/* only if the custom CG is enabled */
if (attr.options & DPNI_OPT_CUSTOM_CG)
@@ -2808,7 +2836,9 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
return ret;
}
}
-   RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
+   RTE_LOG(INFO, PMD, "%s: netdev created, connected to %s\n",
+   eth_dev->data->name, dpaa2_dev->ep_name);
+
return 0;
 init_err:
dpaa2_dev_close(eth_dev);
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index bd33a22a8e..b032da9eff 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -11,6 +11,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include "dpaa2_tm.h"
 
@@ -65,6 +66,18 @@
 /* Tx confirmation enabled */
 #define DPAA2_TX_CONF_ENABLE   0x06
 
+/* HW loopback the egress traffic to self ingress*/
+#define DPAA2_TX_MAC_LOOPBACK_MODE 0x20
+
+#define DPAA2_TX_SERDES_LOOPBACK_MODE 0x40
+
+#define DPAA2_TX_DPNI_LOOPBACK_MODE 0x80
+
+#define DPAA2_TX_LOOPBACK_MODE \
+   (DPAA2_TX_MAC_LOOPBACK_MODE | \
+   DPAA2_TX_SERDES_LOOPBACK_MODE | \
+   DPAA2_TX_DPNI_LOOPBACK_MODE)
+
 #define DPAA2_RSS_OFFLOAD_ALL ( \
RTE_ETH_RSS_L2_PAYLOAD | \
RTE_ETH_RSS_IP | \
@@ -192,6 +205,7 @@ struct dpaa2_dev_priv {
struct dpaa2_queue *next_tx_conf_queue;
 
struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */
+   rte_spinlock_t lpbk_qp_lock;
 
uint8_t channel_inuse;
LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */
@@ -268,4 +282,13 @@ int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev 
*dev,
uin

[PATCH v3 11/15] net/dpaa: check status before configuring shared MAC

[nipun . gupta]

From: Nipun Gupta 

For shared MAC interface, it is a prerequisite to enable the
interface in the kernel, before using it in user-space. This
patch makes sure that device is not getting configured in
case shared MAC interface is not enabled in the kernel.

Signed-off-by: Nipun Gupta 
---
 drivers/bus/dpaa/base/fman/fman_hw.c | 11 +++
 drivers/bus/dpaa/include/fsl_fman.h  |  2 ++
 drivers/bus/dpaa/version.map |  1 +
 drivers/net/dpaa/dpaa_ethdev.c   | 13 -
 4 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/bus/dpaa/base/fman/fman_hw.c 
b/drivers/bus/dpaa/base/fman/fman_hw.c
index af9bac76c2..24a99f7235 100644
--- a/drivers/bus/dpaa/base/fman/fman_hw.c
+++ b/drivers/bus/dpaa/base/fman/fman_hw.c
@@ -314,6 +314,17 @@ fman_if_disable_rx(struct fman_if *p)
out_be32(__if->ccsr_map + 8, in_be32(__if->ccsr_map + 8) & ~(u32)2);
 }
 
+int
+fman_if_get_rx_status(struct fman_if *p)
+{
+   struct __fman_if *__if = container_of(p, struct __fman_if, __if);
+
+   assert(fman_ccsr_map_fd != -1);
+
+   /* return true if RX bit is set */
+   return !!(in_be32(__if->ccsr_map + 8) & (u32)2);
+}
+
 void
 fman_if_loopback_enable(struct fman_if *p)
 {
diff --git a/drivers/bus/dpaa/include/fsl_fman.h 
b/drivers/bus/dpaa/include/fsl_fman.h
index f3a5d05970..acb344584f 100644
--- a/drivers/bus/dpaa/include/fsl_fman.h
+++ b/drivers/bus/dpaa/include/fsl_fman.h
@@ -81,6 +81,8 @@ __rte_internal
 void fman_if_enable_rx(struct fman_if *p);
 __rte_internal
 void fman_if_disable_rx(struct fman_if *p);
+__rte_internal
+int fman_if_get_rx_status(struct fman_if *p);
 
 /* Enable/disable loopback on specific interfaces */
 __rte_internal
diff --git a/drivers/bus/dpaa/version.map b/drivers/bus/dpaa/version.map
index 900635b210..1a840fd1a5 100644
--- a/drivers/bus/dpaa/version.map
+++ b/drivers/bus/dpaa/version.map
@@ -33,6 +33,7 @@ INTERNAL {
fman_if_get_fdoff;
fman_if_get_maxfrm;
fman_if_get_sg_enable;
+   fman_if_get_rx_status;
fman_if_loopback_disable;
fman_if_loopback_enable;
fman_if_promiscuous_disable;
diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index e49f765434..3972ecaed8 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -195,6 +195,7 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev)
struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
uint64_t rx_offloads = eth_conf->rxmode.offloads;
uint64_t tx_offloads = eth_conf->txmode.offloads;
+   struct dpaa_if *dpaa_intf = dev->data->dev_private;
struct rte_device *rdev = dev->device;
struct rte_eth_link *link = &dev->data->dev_link;
struct rte_dpaa_device *dpaa_dev;
@@ -203,7 +204,7 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev)
struct rte_intr_handle *intr_handle;
uint32_t max_rx_pktlen;
int speed, duplex;
-   int ret;
+   int ret, rx_status;
 
PMD_INIT_FUNC_TRACE();
 
@@ -211,6 +212,16 @@ dpaa_eth_dev_configure(struct rte_eth_dev *dev)
intr_handle = dpaa_dev->intr_handle;
__fif = container_of(fif, struct __fman_if, __if);
 
+   /* Check if interface is enabled in case of shared MAC */
+   if (fif->is_shared_mac) {
+   rx_status = fman_if_get_rx_status(fif);
+   if (!rx_status) {
+   DPAA_PMD_ERR("%s Interface not enabled in kernel!",
+dpaa_intf->name);
+   return -EHOSTDOWN;
+   }
+   }
+
/* Rx offloads which are enabled by default */
if (dev_rx_offloads_nodis & ~rx_offloads) {
DPAA_PMD_INFO(
-- 
2.17.1

[PATCH v3 12/15] net/dpaa: enable checksum for shared MAC interface

[nipun . gupta]

From: Nipun Gupta 

In case of shared MAC B0V bit in contextA is required
to be set to set so that ASPID is 0.

Signed-off-by: Brick Yang 
Signed-off-by: Nipun Gupta 
---
 drivers/net/dpaa/dpaa_ethdev.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/net/dpaa/dpaa_ethdev.c b/drivers/net/dpaa/dpaa_ethdev.c
index 3972ecaed8..7135a5998d 100644
--- a/drivers/net/dpaa/dpaa_ethdev.c
+++ b/drivers/net/dpaa/dpaa_ethdev.c
@@ -1755,6 +1755,10 @@ static int dpaa_tx_queue_init(struct qman_fq *fq,
/* no tx-confirmation */
opts.fqd.context_a.hi = 0x8000 | fman_dealloc_bufs_mask_hi;
opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
+   if (fman_ip_rev >= FMAN_V3) {
+   /* Set B0V bit in contextA to set ASPID to 0 */
+   opts.fqd.context_a.hi |= 0x0400;
+   }
DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
 
if (cgr_tx) {
-- 
2.17.1

[PATCH v3 13/15] net/enetc: add support for VFs

[nipun . gupta]

From: Gagandeep Singh 

Add virtual function support for enetc devices

Signed-off-by: Gagandeep Singh 
---
 drivers/net/enetc/enetc_ethdev.c | 25 -
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c
index 7cdb8ce463..1b4337bc48 100644
--- a/drivers/net/enetc/enetc_ethdev.c
+++ b/drivers/net/enetc/enetc_ethdev.c
@@ -19,6 +19,9 @@ enetc_dev_start(struct rte_eth_dev *dev)
uint32_t val;
 
PMD_INIT_FUNC_TRACE();
+   if (hw->device_id == ENETC_DEV_ID_VF)
+   return 0;
+
val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG);
enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG,
  val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
@@ -55,6 +58,9 @@ enetc_dev_stop(struct rte_eth_dev *dev)
 
PMD_INIT_FUNC_TRACE();
dev->data->dev_started = 0;
+   if (hw->device_id == ENETC_DEV_ID_VF)
+   return 0;
+
/* Disable port */
val = enetc_port_rd(enetc_hw, ENETC_PMR);
enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN));
@@ -160,11 +166,20 @@ enetc_hardware_init(struct enetc_eth_hw *hw)
/* Enabling Station Interface */
enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN);
 
-   *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
-   high_mac = (uint32_t)*mac;
-   mac++;
-   *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
-   low_mac = (uint16_t)*mac;
+
+   if (hw->device_id == ENETC_DEV_ID_VF) {
+   *mac = (uint32_t)enetc_rd(enetc_hw, ENETC_SIPMAR0);
+   high_mac = (uint32_t)*mac;
+   mac++;
+   *mac = (uint32_t)enetc_rd(enetc_hw, ENETC_SIPMAR1);
+   low_mac = (uint16_t)*mac;
+   } else {
+   *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0));
+   high_mac = (uint32_t)*mac;
+   mac++;
+   *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0));
+   low_mac = (uint16_t)*mac;
+   }
 
if ((high_mac | low_mac) == 0) {
char *first_byte;
-- 
2.17.1

[PATCH v3 14/15] net/pfe: reduce driver initialization time

[nipun . gupta]

From: Gagandeep Singh 

This patch reduces the delay in the device init.

Signed-off-by: Gagandeep Singh 
Signed-off-by: Nipun Gupta 
---
 drivers/net/pfe/pfe_hif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/pfe/pfe_hif.c b/drivers/net/pfe/pfe_hif.c
index c4a7154ba7..8a10f10f56 100644
--- a/drivers/net/pfe/pfe_hif.c
+++ b/drivers/net/pfe/pfe_hif.c
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2021 NXP
  */
 
 #include "pfe_logs.h"
@@ -766,7 +766,7 @@ pfe_hif_rx_idle(struct pfe_hif *hif)
if (rx_status & BDP_CSR_RX_DMA_ACTV)
send_dummy_pkt_to_hif();
 
-   sleep(1);
+   rte_delay_ms(1);
} while (--hif_stop_loop);
 
if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
-- 
2.17.1

[PATCH v3 15/15] net/pfe: remove setting unused value

[nipun . gupta]

From: Apeksha Gupta 

remove setting link status where it is not being used

Signed-off-by: Apeksha Gupta 
---
 drivers/net/pfe/pfe_ethdev.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/pfe/pfe_ethdev.c b/drivers/net/pfe/pfe_ethdev.c
index 047010e15e..e5aaf5dcfd 100644
--- a/drivers/net/pfe/pfe_ethdev.c
+++ b/drivers/net/pfe/pfe_ethdev.c
@@ -587,8 +587,7 @@ pfe_eth_link_update(struct rte_eth_dev *dev, int 
wait_to_complete __rte_unused)
ret = ioctl(priv->link_fd, ioctl_cmd, &lstatus);
if (ret != 0) {
PFE_PMD_ERR("Unable to fetch link status (ioctl)\n");
-   /* use dummy link value */
-   link.link_status = 1;
+   return -1;
}
PFE_PMD_DEBUG("Fetched link state (%d) for dev %d.\n",
  lstatus, priv->id);
-- 
2.17.1

Re: [RFC 1/1] vhost: integrate dmadev in asynchronous datapath

[Maxime Coquelin]

Hi Jiayu,

On 12/28/21 02:15, Hu, Jiayu wrote:

Hi Maxime,

Thanks for your comments, and some replies are inline.

Thanks,
Jiayu


-Original Message-
From: Maxime Coquelin 
Sent: Friday, December 24, 2021 6:40 PM
To: Hu, Jiayu ; dev@dpdk.org
Cc: i.maxim...@ovn.org; Xia, Chenbo ; Richardson,
Bruce ; Van Haaren, Harry
; Mcnamara, John
; Pai G, Sunil 
Subject: Re: [RFC 1/1] vhost: integrate dmadev in asynchronous datapath

Hi Jiayu,

This is a first review, I need to spend more time on the series to understand
it well. Do you have a prototype of the OVS part, so that it helps us to grasp
how the full integration would look like?


I think OVS patch will be sent soon. And we will send the deq side 
implementation too.



On 11/22/21 11:54, Jiayu Hu wrote:

Since dmadev is introduced in 21.11, to avoid the overhead of vhost
DMA abstraction layer and simplify application logics, this patch
integrates dmadev in asynchronous data path.

Signed-off-by: Jiayu Hu 
Signed-off-by: Sunil Pai G 
---
   doc/guides/prog_guide/vhost_lib.rst |  63 
   examples/vhost/ioat.c   | 218 
   examples/vhost/ioat.h   |  63 
   examples/vhost/main.c   | 144 +++---
   examples/vhost/main.h   |  12 ++
   examples/vhost/meson.build  |   6 +-
   lib/vhost/meson.build   |   3 +-
   lib/vhost/rte_vhost_async.h |  73 +++---
   lib/vhost/vhost.c   |  37 ++---
   lib/vhost/vhost.h   |  45 +-
   lib/vhost/virtio_net.c  | 198 -
   11 files changed, 410 insertions(+), 452 deletions(-)
   delete mode 100644 examples/vhost/ioat.c
   delete mode 100644 examples/vhost/ioat.h



...


diff --git a/lib/vhost/vhost.c b/lib/vhost/vhost.c
index 13a9bb9dd1..595cf63b8d 100644
--- a/lib/vhost/vhost.c
+++ b/lib/vhost/vhost.c
@@ -344,6 +344,7 @@ vhost_free_async_mem(struct vhost_virtqueue *vq)
return;

rte_free(vq->async->pkts_info);
+   rte_free(vq->async->pkts_cmpl_flag);

rte_free(vq->async->buffers_packed);
vq->async->buffers_packed = NULL;
@@ -1626,8 +1627,7 @@ rte_vhost_extern_callback_register(int vid,
   }

diff --git a/lib/vhost/vhost.h b/lib/vhost/vhost.h
index 7085e0885c..974e495b56 100644
--- a/lib/vhost/vhost.h
+++ b/lib/vhost/vhost.h
@@ -51,6 +51,11 @@
   #define VHOST_MAX_ASYNC_IT (MAX_PKT_BURST)
   #define VHOST_MAX_ASYNC_VEC 2048

+/* DMA device copy operation tracking ring size. */
+#define VHOST_ASYNC_DMA_TRACK_RING_SIZE (uint32_t)4096


How is this value chosen? Is that specific to your hardware?


Yes. But in fact, this value should be equal to or greater than vchan
desc number, and it should be dynamic. In addition, the context tracking
array " dma_copy_track" should be per-vchan basis, rather than per-device,
although existed DMA devices only supports 1 vchan at most.

I have reworked this part which can be configured by users dynamically.


Wouldn't it be better to use the max_desc value from from struct
rte_dma_info?

[Bug 913] [dpdk-19.11.11]'mk' makefile build failed on Freebsd13 with clang11.0.1

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=913

Christian Ehrhardt (christian.ehrha...@canonical.com) changed:

   What|Removed |Added

 Resolution|--- |FIXED
 CC||christian.ehrhardt@canonica
   ||l.com
 Status|UNCONFIRMED |RESOLVED

--- Comment #2 from Christian Ehrhardt (christian.ehrha...@canonical.com) ---
Thanks, Queued for 19.11.11 as it improves some other recently added compiler
fixes and we'd want to avoid those breaking older clang builds.

-- 
You are receiving this mail because:
You are the assignee for the bug.

[PATCH 0/1] Minor mistake in ring (en|de)queueing

[Andrzej Ostruszka]

Hi all,

Recently I was going through the ring implementation and I believe I've
found a small mistake.  Not a functional error, just a slightly
suboptimal behaviour for the specific case when we want to enqueue
exactly the number of elements that we can before wrapping to the ring
beginning (the same goes for dequeueing).

Imagine we have a ring of size 16 depicted below with indexes underneath
and consumer/producer pointing as shown.

|  **|
 0123456789ABCDEF
   ^ ^
   c p

Now if we try to enqueue 8 elements we will end up at the check:

if (likely(idx + n < size)) {

where idx (=8) is a producer head and n=8.  We will fail this check
even though we have the case of 8 elements available without wrapping to
the beginning of the ring.

I hope I'm not completely off the base here :), if I'm not then the
subsequent patch attempts to fix this.

Wit regards
Andrzej Ostruszka

Andrzej Ostruszka (1):
  ring: fix off by 1 mistake

 lib/ring/rte_ring_elem_pvt.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

-- 
2.34.1.448.ga2b2bfdf31-goog

[PATCH 1/1] ring: fix off by 1 mistake

[Andrzej Ostruszka]

When enqueueing/dequeueing to/from the ring we try to optimize by manual
loop unrolling.  The check for this optimization looks like:

if (likely(idx + n < size)) {

where 'idx' points to the first usable element (empty slot for enqueue,
data for dequeue).  The correct comparison here should be '<=' instead
of '<'.

This is not a functional error since we fall back to the loop with
correct checks on indexes.  Just a minor suboptimal behaviour for the
case when we want to enqueue/dequeue exactly the number of elements that
we have in the ring before wrapping to its beginning.

Signed-off-by: Andrzej Ostruszka 
---
 lib/ring/rte_ring_elem_pvt.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/lib/ring/rte_ring_elem_pvt.h b/lib/ring/rte_ring_elem_pvt.h
index 275ec55393..83788c56e6 100644
--- a/lib/ring/rte_ring_elem_pvt.h
+++ b/lib/ring/rte_ring_elem_pvt.h
@@ -17,7 +17,7 @@ __rte_ring_enqueue_elems_32(struct rte_ring *r, const 
uint32_t size,
unsigned int i;
uint32_t *ring = (uint32_t *)&r[1];
const uint32_t *obj = (const uint32_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x7); i += 8, idx += 8) {
ring[idx] = obj[i];
ring[idx + 1] = obj[i + 1];
@@ -62,7 +62,7 @@ __rte_ring_enqueue_elems_64(struct rte_ring *r, uint32_t 
prod_head,
uint32_t idx = prod_head & r->mask;
uint64_t *ring = (uint64_t *)&r[1];
const unaligned_uint64_t *obj = (const unaligned_uint64_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x3); i += 4, idx += 4) {
ring[idx] = obj[i];
ring[idx + 1] = obj[i + 1];
@@ -95,7 +95,7 @@ __rte_ring_enqueue_elems_128(struct rte_ring *r, uint32_t 
prod_head,
uint32_t idx = prod_head & r->mask;
rte_int128_t *ring = (rte_int128_t *)&r[1];
const rte_int128_t *obj = (const rte_int128_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x1); i += 2, idx += 2)
memcpy((void *)(ring + idx),
(const void *)(obj + i), 32);
@@ -151,7 +151,7 @@ __rte_ring_dequeue_elems_32(struct rte_ring *r, const 
uint32_t size,
unsigned int i;
uint32_t *ring = (uint32_t *)&r[1];
uint32_t *obj = (uint32_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x7); i += 8, idx += 8) {
obj[i] = ring[idx];
obj[i + 1] = ring[idx + 1];
@@ -196,7 +196,7 @@ __rte_ring_dequeue_elems_64(struct rte_ring *r, uint32_t 
prod_head,
uint32_t idx = prod_head & r->mask;
uint64_t *ring = (uint64_t *)&r[1];
unaligned_uint64_t *obj = (unaligned_uint64_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x3); i += 4, idx += 4) {
obj[i] = ring[idx];
obj[i + 1] = ring[idx + 1];
@@ -229,7 +229,7 @@ __rte_ring_dequeue_elems_128(struct rte_ring *r, uint32_t 
prod_head,
uint32_t idx = prod_head & r->mask;
rte_int128_t *ring = (rte_int128_t *)&r[1];
rte_int128_t *obj = (rte_int128_t *)obj_table;
-   if (likely(idx + n < size)) {
+   if (likely(idx + n <= size)) {
for (i = 0; i < (n & ~0x1); i += 2, idx += 2)
memcpy((void *)(obj + i), (void *)(ring + idx), 32);
switch (n & 0x1) {
-- 
2.34.1.448.ga2b2bfdf31-goog

[PATCH v3] mempool: fix the description of some function return values

[Zhiheng Chen]

In rte_mempool_ring.c, the committer uses the symbol ENOBUFS to
describe the return value of function common_ring_sc_dequeue,
but in rte_mempool.h, the symbol ENOENT is used to describe
the return value of function rte_mempool_get. If the user of
dpdk uses the symbol ENOENT as the judgment condition of
the return value, it may cause some abnormal phenomena
in their own programs, such as when the mempool space is exhausted.

v2:
* Update the descriptions of underlying functions.

v3:
* Correct the description that the return value cannot be greater than 0
* Update the description of the dequeue function prototype

Signed-off-by: Zhiheng Chen 
---
 lib/mempool/rte_mempool.h | 34 ++
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/lib/mempool/rte_mempool.h b/lib/mempool/rte_mempool.h
index 1e7a3c1527..cae81d8a32 100644
--- a/lib/mempool/rte_mempool.h
+++ b/lib/mempool/rte_mempool.h
@@ -447,6 +447,16 @@ typedef int (*rte_mempool_enqueue_t)(struct rte_mempool 
*mp,
 
 /**
  * Dequeue an object from the external pool.
+ *
+ * @param mp
+ *   Pointer to the memory pool.
+ * @param obj_table
+ *   Pointer to a table of void * pointers (objects).
+ * @param n
+ *   Number of objects to get.
+ * @return
+ *   - 0: Success; got n objects.
+ *   - -ENOBUFS: Not enough entries in the mempool; no object is retrieved.
  */
 typedef int (*rte_mempool_dequeue_t)(struct rte_mempool *mp,
void **obj_table, unsigned int n);
@@ -738,7 +748,7 @@ rte_mempool_ops_alloc(struct rte_mempool *mp);
  *   Number of objects to get.
  * @return
  *   - 0: Success; got n objects.
- *   - <0: Error; code of dequeue function.
+ *   - -ENOBUFS: Not enough entries in the mempool; no object is retrieved.
  */
 static inline int
 rte_mempool_ops_dequeue_bulk(struct rte_mempool *mp,
@@ -1452,8 +1462,8 @@ rte_mempool_put(struct rte_mempool *mp, void *obj)
  * @param cache
  *   A pointer to a mempool cache structure. May be NULL if not needed.
  * @return
- *   - >=0: Success; number of objects supplied.
- *   - <0: Error; code of ring dequeue function.
+ *   - 0: Success; got n objects.
+ *   - -ENOBUFS: Not enough entries in the mempool; no object is retrieved.
  */
 static __rte_always_inline int
 rte_mempool_do_generic_get(struct rte_mempool *mp, void **obj_table,
@@ -1521,7 +1531,7 @@ rte_mempool_do_generic_get(struct rte_mempool *mp, void 
**obj_table,
  * Get several objects from the mempool.
  *
  * If cache is enabled, objects will be retrieved first from cache,
- * subsequently from the common pool. Note that it can return -ENOENT when
+ * subsequently from the common pool. Note that it can return -ENOBUFS when
  * the local cache and common pool are empty, even if cache from other
  * lcores are full.
  *
@@ -1534,8 +1544,8 @@ rte_mempool_do_generic_get(struct rte_mempool *mp, void 
**obj_table,
  * @param cache
  *   A pointer to a mempool cache structure. May be NULL if not needed.
  * @return
- *   - 0: Success; objects taken.
- *   - -ENOENT: Not enough entries in the mempool; no object is retrieved.
+ *   - 0: Success; got n objects.
+ *   - -ENOBUFS: Not enough entries in the mempool; no object is retrieved.
  */
 static __rte_always_inline int
 rte_mempool_generic_get(struct rte_mempool *mp, void **obj_table,
@@ -1557,7 +1567,7 @@ rte_mempool_generic_get(struct rte_mempool *mp, void 
**obj_table,
  * mempool creation time (see flags).
  *
  * If cache is enabled, objects will be retrieved first from cache,
- * subsequently from the common pool. Note that it can return -ENOENT when
+ * subsequently from the common pool. Note that it can return -ENOBUFS when
  * the local cache and common pool are empty, even if cache from other
  * lcores are full.
  *
@@ -1568,8 +1578,8 @@ rte_mempool_generic_get(struct rte_mempool *mp, void 
**obj_table,
  * @param n
  *   The number of objects to get from the mempool to obj_table.
  * @return
- *   - 0: Success; objects taken
- *   - -ENOENT: Not enough entries in the mempool; no object is retrieved.
+ *   - 0: Success; got n objects.
+ *   - -ENOBUFS: Not enough entries in the mempool; no object is retrieved.
  */
 static __rte_always_inline int
 rte_mempool_get_bulk(struct rte_mempool *mp, void **obj_table, unsigned int n)
@@ -1588,7 +1598,7 @@ rte_mempool_get_bulk(struct rte_mempool *mp, void 
**obj_table, unsigned int n)
  * mempool creation (see flags).
  *
  * If cache is enabled, objects will be retrieved first from cache,
- * subsequently from the common pool. Note that it can return -ENOENT when
+ * subsequently from the common pool. Note that it can return -ENOBUFS when
  * the local cache and common pool are empty, even if cache from other
  * lcores are full.
  *
@@ -1597,8 +1607,8 @@ rte_mempool_get_bulk(struct rte_mempool *mp, void 
**obj_table, unsigned int n)
  * @param obj_p
  *   A pointer to a void * pointer (object) that will be filled.
  * @return
- *   - 0: Success; objects taken.
- *   - -ENOENT: Not enough e

Re: [PATCH v2] mempool: fix the description of some function return values

[zhiheng chen]

Thank you for pointing out my problem, I will fix it in the next version

> 2021年12月22日 下午7:45，Morten Brørup  写道：
> 
>> From: Zhiheng Chen [mailto:chenzhiheng0...@gmail.com 
>> ]
>> Sent: Wednesday, 22 December 2021 09.26
>> 
>> Compared to patch version 1, this version updates the descriptions
>> of underlying functions.
> 
> Some comments inline below, regarding the return value of success.
> 
> You should also update the description of the dequeue function prototype on 
> line 451, so no one implements an alternative dequeue operation that returns 
> anything else than -ENOBUFS as error value.
> 
> @Olivier, @Andrew: Do we want to impose this restriction on the API?
> 
> Otherwise, the patch should take the opposite direction, and update the 
> descriptions of high level functions - i.e. rte_mempool_generic_get(), 
> rte_mempool_get_bulk(), rte_mempool_get(), etc. - to reflect that any error 
> value <0 can be returned, originating from the underlying function.
> 
>> 
>> In rte_mempool_ring.c, the committer uses the symbol ENOBUFS to
>> describe the return value of function common_ring_sc_dequeue,
>> but in rte_mempool.h, the symbol ENOENT is used to describe
>> the return value of function rte_mempool_get. If the user of
>> dpdk uses the symbol ENOENT as the judgment condition of
>> the return value, it may cause some abnormal phenomena
>> in their own programs, such as when the mempool space is exhausted.
>> 
>> Fixes: ea5dd2744b90 ("mempool: cache optimisations")
>> 
>> Signed-off-by: Zhiheng Chen 
>> ---
>> lib/mempool/rte_mempool.h | 22 +++---
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>> 
>> diff --git a/lib/mempool/rte_mempool.h b/lib/mempool/rte_mempool.h
>> index 1e7a3c1527..3b52bd6737 100644
>> --- a/lib/mempool/rte_mempool.h
>> +++ b/lib/mempool/rte_mempool.h
>> @@ -737,8 +737,8 @@ rte_mempool_ops_alloc(struct rte_mempool *mp);
>>  * @param n
>>  *   Number of objects to get.
>>  * @return
>> - *   - 0: Success; got n objects.
>> - *   - <0: Error; code of dequeue function.
>> + *   - >=0: Success; number of objects supplied.
>> + *   - -ENOBUFS: Not enough entries in the mempool; no object is
>> retrieved.
> 
> NAK regarding success: Return value 0 is correct, >=0 cannot happen.
> 
>>  */
>> static inline int
>> rte_mempool_ops_dequeue_bulk(struct rte_mempool *mp,
>> @@ -1453,7 +1453,7 @@ rte_mempool_put(struct rte_mempool *mp, void
>> *obj)
>>  *   A pointer to a mempool cache structure. May be NULL if not
>> needed.
>>  * @return
>>  *   - >=0: Success; number of objects supplied.
> 
> This is also wrong. It should be:
> -*   - >=0: Success; number of objects supplied.
> +*   - 0: Success; got n objects.
> 
>> - *   - <0: Error; code of ring dequeue function.
>> + *   - -ENOBUFS: Not enough entries in the mempool; no object is
>> retrieved.
>>  */
>> static __rte_always_inline int
>> rte_mempool_do_generic_get(struct rte_mempool *mp, void **obj_table,
>> @@ -1521,7 +1521,7 @@ rte_mempool_do_generic_get(struct rte_mempool
>> *mp, void **obj_table,
>>  * Get several objects from the mempool.
>>  *
>>  * If cache is enabled, objects will be retrieved first from cache,
>> - * subsequently from the common pool. Note that it can return -ENOENT
>> when
>> + * subsequently from the common pool. Note that it can return -ENOBUFS
>> when
>>  * the local cache and common pool are empty, even if cache from other
>>  * lcores are full.
>>  *
>> @@ -1534,8 +1534,8 @@ rte_mempool_do_generic_get(struct rte_mempool
>> *mp, void **obj_table,
>>  * @param cache
>>  *   A pointer to a mempool cache structure. May be NULL if not
>> needed.
>>  * @return
>> - *   - 0: Success; objects taken.
>> - *   - -ENOENT: Not enough entries in the mempool; no object is
>> retrieved.
>> + *   - >=0: Success; number of objects supplied.
>> + *   - -ENOBUFS: Not enough entries in the mempool; no object is
>> retrieved.
> 
> NAK regarding success: Return value 0 is correct, >=0 cannot happen.
> 
>>  */
>> static __rte_always_inline int
>> rte_mempool_generic_get(struct rte_mempool *mp, void **obj_table,
>> @@ -1557,7 +1557,7 @@ rte_mempool_generic_get(struct rte_mempool *mp,
>> void **obj_table,
>>  * mempool creation time (see flags).
>>  *
>>  * If cache is enabled, objects will be retrieved first from cache,
>> - * subsequently from the common pool. Note that it can return -ENOENT
>> when
>> + * subsequently from the common pool. Note that it can return -ENOBUFS
>> when
>>  * the local cache and common pool are empty, even if cache from other
>>  * lcores are full.
>>  *
>> @@ -1568,8 +1568,8 @@ rte_mempool_generic_get(struct rte_mempool *mp,
>> void **obj_table,
>>  * @param n
>>  *   The number of objects to get from the mempool to obj_table.
>>  * @return
>> - *   - 0: Success; objects taken
>> - *   - -ENOENT: Not enough entries in the mempool; no object is
>> retrieved.
>> + *   - >=0: Success; number of objects supplied.
>> + *   - -ENOBUFS: Not enough entrie

RE: [PATCH 1/1] ring: fix off by 1 mistake

[Morten Brørup]

+Ring queue maintainers: Honnappa Nagarahalli , 
Konstantin Ananyev 

> From: Andrzej Ostruszka [mailto:a...@semihalf.com]
> Sent: Monday, 3 January 2022 15.22
> 
> When enqueueing/dequeueing to/from the ring we try to optimize by
> manual
> loop unrolling.  The check for this optimization looks like:
> 
>   if (likely(idx + n < size)) {
> 
> where 'idx' points to the first usable element (empty slot for enqueue,
> data for dequeue).  The correct comparison here should be '<=' instead
> of '<'.
> 
> This is not a functional error since we fall back to the loop with
> correct checks on indexes.  Just a minor suboptimal behaviour for the
> case when we want to enqueue/dequeue exactly the number of elements
> that
> we have in the ring before wrapping to its beginning.
> 
> Signed-off-by: Andrzej Ostruszka 
> ---
>  lib/ring/rte_ring_elem_pvt.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/ring/rte_ring_elem_pvt.h
> b/lib/ring/rte_ring_elem_pvt.h
> index 275ec55393..83788c56e6 100644
> --- a/lib/ring/rte_ring_elem_pvt.h
> +++ b/lib/ring/rte_ring_elem_pvt.h
> @@ -17,7 +17,7 @@ __rte_ring_enqueue_elems_32(struct rte_ring *r, const
> uint32_t size,
>   unsigned int i;
>   uint32_t *ring = (uint32_t *)&r[1];
>   const uint32_t *obj = (const uint32_t *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x7); i += 8, idx += 8) {
>   ring[idx] = obj[i];
>   ring[idx + 1] = obj[i + 1];
> @@ -62,7 +62,7 @@ __rte_ring_enqueue_elems_64(struct rte_ring *r,
> uint32_t prod_head,
>   uint32_t idx = prod_head & r->mask;
>   uint64_t *ring = (uint64_t *)&r[1];
>   const unaligned_uint64_t *obj = (const unaligned_uint64_t
> *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x3); i += 4, idx += 4) {
>   ring[idx] = obj[i];
>   ring[idx + 1] = obj[i + 1];
> @@ -95,7 +95,7 @@ __rte_ring_enqueue_elems_128(struct rte_ring *r,
> uint32_t prod_head,
>   uint32_t idx = prod_head & r->mask;
>   rte_int128_t *ring = (rte_int128_t *)&r[1];
>   const rte_int128_t *obj = (const rte_int128_t *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x1); i += 2, idx += 2)
>   memcpy((void *)(ring + idx),
>   (const void *)(obj + i), 32);
> @@ -151,7 +151,7 @@ __rte_ring_dequeue_elems_32(struct rte_ring *r,
> const uint32_t size,
>   unsigned int i;
>   uint32_t *ring = (uint32_t *)&r[1];
>   uint32_t *obj = (uint32_t *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x7); i += 8, idx += 8) {
>   obj[i] = ring[idx];
>   obj[i + 1] = ring[idx + 1];
> @@ -196,7 +196,7 @@ __rte_ring_dequeue_elems_64(struct rte_ring *r,
> uint32_t prod_head,
>   uint32_t idx = prod_head & r->mask;
>   uint64_t *ring = (uint64_t *)&r[1];
>   unaligned_uint64_t *obj = (unaligned_uint64_t *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x3); i += 4, idx += 4) {
>   obj[i] = ring[idx];
>   obj[i + 1] = ring[idx + 1];
> @@ -229,7 +229,7 @@ __rte_ring_dequeue_elems_128(struct rte_ring *r,
> uint32_t prod_head,
>   uint32_t idx = prod_head & r->mask;
>   rte_int128_t *ring = (rte_int128_t *)&r[1];
>   rte_int128_t *obj = (rte_int128_t *)obj_table;
> - if (likely(idx + n < size)) {
> + if (likely(idx + n <= size)) {
>   for (i = 0; i < (n & ~0x1); i += 2, idx += 2)
>   memcpy((void *)(obj + i), (void *)(ring + idx), 32);
>   switch (n & 0x1) {
> --
> 2.34.1.448.ga2b2bfdf31-goog
> 

Well spotted! I took a very good look at it, and came to the same conclusion: 
It not a functional bug; the only consequence is that the optimized code path 
may not be taken in a situation where it could be taken. But it should be fixed 
as suggested in your patch.

Reviewed-by: Morten Brørup 

[PATCH 0/8] ethdev: introduce IP reassembly offload

[Akhil Goyal]

As discussed in the RFC[1] sent in 21.11, a new offload is
introduced in ethdev for IP reassembly.

This patchset add the RX offload and an application to test it.
Currently, the offload is tested along with inline IPsec processing.
It can also be updated as a standalone offload without IPsec, if there
are some hardware available to test it.
The patchset is tested on cnxk platform. The driver implementation is
added as a separate patchset.

[1]: 
http://patches.dpdk.org/project/dpdk/patch/20210823100259.1619886-1-gak...@marvell.com/


Akhil Goyal (8):
  ethdev: introduce IP reassembly offload
  ethdev: add dev op for IP reassembly configuration
  ethdev: add mbuf dynfield for incomplete IP reassembly
  security: add IPsec option for IP reassembly
  app/test: add unit cases for inline IPsec offload
  app/test: add IP reassembly case with no frags
  app/test: add IP reassembly cases with multiple fragments
  app/test: add IP reassembly negative cases

 app/test/meson.build  |1 +
 app/test/test_inline_ipsec.c  | 1036 +
 .../test_inline_ipsec_reassembly_vectors.h|  790 +
 doc/guides/nics/features.rst  |   12 +
 lib/ethdev/ethdev_driver.h|   27 +
 lib/ethdev/rte_ethdev.c   |   47 +
 lib/ethdev/rte_ethdev.h   |  117 +-
 lib/ethdev/version.map|5 +
 lib/mbuf/rte_mbuf_core.h  |3 +-
 lib/security/rte_security.h   |   12 +-
 10 files changed, 2047 insertions(+), 3 deletions(-)
 create mode 100644 app/test/test_inline_ipsec.c
 create mode 100644 app/test/test_inline_ipsec_reassembly_vectors.h

-- 
2.25.1

[PATCH 1/8] ethdev: introduce IP reassembly offload

[Akhil Goyal]

IP Reassembly is a costly operation if it is done in software.
The operation becomes even more costlier if IP fragmants are encrypted.
However, if it is offloaded to HW, it can considerably save application cycles.

Hence, a new offload RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY is introduced in
ethdev for devices which can attempt reassembly of packets in hardware.
rte_eth_dev_info is updated with the reassembly capabilities which a device
can support.

The resulting reassembled packet would be a typical segmented mbuf in
case of success.

And if reassembly of fragments is failed or is incomplete (if fragments do
not come before the reass_timeout), the mbuf ol_flags can be updated.
This is updated in a subsequent patch.

Signed-off-by: Akhil Goyal 
---
 doc/guides/nics/features.rst | 12 
 lib/ethdev/rte_ethdev.c  |  1 +
 lib/ethdev/rte_ethdev.h  | 32 +++-
 3 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
index 27be2d2576..1dfdee9602 100644
--- a/doc/guides/nics/features.rst
+++ b/doc/guides/nics/features.rst
@@ -602,6 +602,18 @@ Supports inner packet L4 checksum.
   ``tx_offload_capa,tx_queue_offload_capa:RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM``.
 
 
+.. _nic_features_ip_reassembly:
+
+IP reassembly
+-
+
+Supports IP reassembly in hardware.
+
+* **[uses] rte_eth_rxconf,rte_eth_rxmode**: 
``offloads:RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY``.
+* **[provides] mbuf**: 
``mbuf.ol_flags:RTE_MBUF_F_RX_IP_REASSEMBLY_INCOMPLETE``.
+* **[provides] rte_eth_dev_info**: ``reass_capa``.
+
+
 .. _nic_features_shared_rx_queue:
 
 Shared Rx queue
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index a1d475a292..d9a03f12f9 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -126,6 +126,7 @@ static const struct {
RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
RTE_RX_OFFLOAD_BIT2STR(RSS_HASH),
RTE_RX_OFFLOAD_BIT2STR(BUFFER_SPLIT),
+   RTE_RX_OFFLOAD_BIT2STR(IP_REASSEMBLY),
 };
 
 #undef RTE_RX_OFFLOAD_BIT2STR
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index fa299c8ad7..11427b2e4d 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -1586,6 +1586,7 @@ struct rte_eth_conf {
 #define RTE_ETH_RX_OFFLOAD_RSS_HASH RTE_BIT64(19)
 #define DEV_RX_OFFLOAD_RSS_HASH RTE_ETH_RX_OFFLOAD_RSS_HASH
 #define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT RTE_BIT64(20)
+#define RTE_ETH_RX_OFFLOAD_IP_REASSEMBLYRTE_BIT64(21)
 
 #define RTE_ETH_RX_OFFLOAD_CHECKSUM (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \
 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \
@@ -1781,6 +1782,33 @@ enum rte_eth_representor_type {
RTE_ETH_REPRESENTOR_PF,   /**< representor of Physical Function. */
 };
 
+/* Flag to offload IP reassembly for IPv4 packets. */
+#define RTE_ETH_DEV_REASSEMBLY_F_IPV4 (RTE_BIT32(0))
+/* Flag to offload IP reassembly for IPv6 packets. */
+#define RTE_ETH_DEV_REASSEMBLY_F_IPV6 (RTE_BIT32(1))
+/**
+ * @warning
+ * @b EXPERIMENTAL: this structure may change without prior notice.
+ *
+ * A structure used to set IP reassembly configuration.
+ *
+ * If RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY flag is set in offloads field,
+ * the PMD will attempt IP reassembly for the received packets as per
+ * properties defined in this structure:
+ *
+ */
+struct rte_eth_ip_reass_params {
+   /** Maximum time in ms which PMD can wait for other fragments. */
+   uint32_t reass_timeout;
+   /** Maximum number of fragments that can be reassembled. */
+   uint16_t max_frags;
+   /**
+* Flags to enable reassembly of packet types -
+* RTE_ETH_DEV_REASSEMBLY_F_xxx.
+*/
+   uint16_t flags;
+};
+
 /**
  * A structure used to retrieve the contextual information of
  * an Ethernet device, such as the controlling driver of the
@@ -1841,8 +1869,10 @@ struct rte_eth_dev_info {
 * embedded managed interconnect/switch.
 */
struct rte_eth_switch_info switch_info;
+   /** IP reassembly offload capabilities that a device can support. */
+   struct rte_eth_ip_reass_params reass_capa;
 
-   uint64_t reserved_64s[2]; /**< Reserved for future fields */
+   uint64_t reserved_64s[1]; /**< Reserved for future fields */
void *reserved_ptrs[2];   /**< Reserved for future fields */
 };
 
-- 
2.25.1

[PATCH 2/8] ethdev: add dev op for IP reassembly configuration

[Akhil Goyal]

A new ethernet device op is added to give application control over
the IP reassembly configuration. This operation is an optional
call from the application, default values are set by PMD and
exposed via rte_eth_dev_info.
Application should always first retreive the capabilities from
rte_eth_dev_info and then set the fields accordingly.

Signed-off-by: Akhil Goyal 
---
 lib/ethdev/ethdev_driver.h | 19 +++
 lib/ethdev/rte_ethdev.c| 30 ++
 lib/ethdev/rte_ethdev.h| 28 
 lib/ethdev/version.map |  3 +++
 4 files changed, 80 insertions(+)

diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h
index d95605a355..0ed53c14f3 100644
--- a/lib/ethdev/ethdev_driver.h
+++ b/lib/ethdev/ethdev_driver.h
@@ -990,6 +990,22 @@ typedef int (*eth_representor_info_get_t)(struct 
rte_eth_dev *dev,
 typedef int (*eth_rx_metadata_negotiate_t)(struct rte_eth_dev *dev,
   uint64_t *features);
 
+/**
+ * @internal
+ * Set configuration parameters for enabling IP reassembly offload in hardware.
+ *
+ * @param dev
+ *   Port (ethdev) handle
+ *
+ * @param[in] conf
+ *   Configuration parameters for IP reassembly.
+ *
+ * @return
+ *   Negative errno value on error, zero otherwise
+ */
+typedef int (*eth_ip_reassembly_conf_set_t)(struct rte_eth_dev *dev,
+  struct rte_eth_ip_reass_params *conf);
+
 /**
  * @internal A structure containing the functions exported by an Ethernet 
driver.
  */
@@ -1186,6 +1202,9 @@ struct eth_dev_ops {
 * kinds of metadata to the PMD
 */
eth_rx_metadata_negotiate_t rx_metadata_negotiate;
+
+   /** Set IP reassembly configuration */
+   eth_ip_reassembly_conf_set_t ip_reassembly_conf_set;
 };
 
 /**
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index d9a03f12f9..ecc6c1fe37 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -6473,6 +6473,36 @@ rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t 
*features)
   (*dev->dev_ops->rx_metadata_negotiate)(dev, features));
 }
 
+int
+rte_eth_ip_reassembly_conf_set(uint16_t port_id,
+  struct rte_eth_ip_reass_params *conf)
+{
+   struct rte_eth_dev *dev;
+
+   RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
+   dev = &rte_eth_devices[port_id];
+
+   if ((dev->data->dev_conf.rxmode.offloads &
+   RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY) == 0) {
+   RTE_ETHDEV_LOG(ERR,
+   "The port (ID=%"PRIu16") is not configured for IP 
reassembly\n",
+   port_id);
+   return -EINVAL;
+   }
+
+
+   if (conf == NULL) {
+   RTE_ETHDEV_LOG(ERR,
+   "Invalid IP reassembly configuration (NULL)\n");
+   return -EINVAL;
+   }
+
+   RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->ip_reassembly_conf_set,
+   -ENOTSUP);
+   return eth_err(port_id,
+  (*dev->dev_ops->ip_reassembly_conf_set)(dev, conf));
+}
+
 RTE_LOG_REGISTER_DEFAULT(rte_eth_dev_logtype, INFO);
 
 RTE_INIT(ethdev_init_telemetry)
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index 11427b2e4d..891f9a6e06 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -5218,6 +5218,34 @@ int rte_eth_representor_info_get(uint16_t port_id,
 __rte_experimental
 int rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Set IP reassembly configuration parameters if device rx offload
+ * flag (RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY) is enabled and the PMD
+ * supports IP reassembly offload. User should first check the
+ * reass_capa in rte_eth_dev_info before setting the configuration.
+ * The values of configuration parameters must not exceed the device
+ * capabilities. The use of this API is optional and if called, it
+ * should be called before rte_eth_dev_start().
+ *
+ * @param port_id
+ *   The port identifier of the device.
+ * @param conf
+ *   A pointer to rte_eth_ip_reass_params structure.
+ * @return
+ *   - (-ENOTSUP) if offload configuration is not supported by device.
+ *   - (-EINVAL) if offload is not enabled in rte_eth_conf.
+ *   - (-ENODEV) if *port_id* invalid.
+ *   - (-EIO) if device is removed.
+ *   - (0) on success.
+ */
+__rte_experimental
+int rte_eth_ip_reassembly_conf_set(uint16_t port_id,
+  struct rte_eth_ip_reass_params *conf);
+
+
 #include 
 
 /**
diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map
index c2fb0669a4..f08fe72044 100644
--- a/lib/ethdev/version.map
+++ b/lib/ethdev/version.map
@@ -256,6 +256,9 @@ EXPERIMENTAL {
rte_flow_flex_item_create;
rte_flow_flex_item_release;
rte_flow_pick_transfer_proxy;
+
+   #added in 22.0

[PATCH 3/8] ethdev: add mbuf dynfield for incomplete IP reassembly

[Akhil Goyal]

Hardware IP reassembly may be incomplete for multiple reasons like
reassembly timeout reached, duplicate fragments, etc.
To save application cycles to process these packets again, a new
mbuf ol_flag (RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE) is added to
show that the mbuf received is not reassembled properly.

Now if this flag is set, application can retreive corresponding chain of
mbufs using mbuf dynfield set by the PMD. Now, it will be upto
application to either drop those fragments or wait for more time.

Signed-off-by: Akhil Goyal 
---
 lib/ethdev/ethdev_driver.h |  8 ++
 lib/ethdev/rte_ethdev.c| 16 +++
 lib/ethdev/rte_ethdev.h| 57 ++
 lib/ethdev/version.map |  2 ++
 lib/mbuf/rte_mbuf_core.h   |  3 +-
 5 files changed, 85 insertions(+), 1 deletion(-)

diff --git a/lib/ethdev/ethdev_driver.h b/lib/ethdev/ethdev_driver.h
index 0ed53c14f3..9a0bab9a61 100644
--- a/lib/ethdev/ethdev_driver.h
+++ b/lib/ethdev/ethdev_driver.h
@@ -1671,6 +1671,14 @@ int
 rte_eth_hairpin_queue_peer_unbind(uint16_t cur_port, uint16_t cur_queue,
  uint32_t direction);
 
+/**
+ * @internal
+ * Register mbuf dynamic field for IP reassembly incomplete case.
+ */
+__rte_internal
+int
+rte_eth_ip_reass_dynfield_register(void);
+
 
 /*
  * Legacy ethdev API used internally by drivers.
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index ecc6c1fe37..d53ce4eaca 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -6503,6 +6503,22 @@ rte_eth_ip_reassembly_conf_set(uint16_t port_id,
   (*dev->dev_ops->ip_reassembly_conf_set)(dev, conf));
 }
 
+#define RTE_ETH_IP_REASS_DYNFIELD_NAME "rte_eth_ip_reass_dynfield"
+int rte_eth_ip_reass_dynfield_offset = -1;
+
+int
+rte_eth_ip_reass_dynfield_register(void)
+{
+   static const struct rte_mbuf_dynfield dynfield_desc = {
+   .name = RTE_ETH_IP_REASS_DYNFIELD_NAME,
+   .size = sizeof(rte_eth_ip_reass_dynfield_t),
+   .align = __alignof__(rte_eth_ip_reass_dynfield_t),
+   };
+   rte_eth_ip_reass_dynfield_offset =
+   rte_mbuf_dynfield_register(&dynfield_desc);
+   return rte_eth_ip_reass_dynfield_offset;
+}
+
 RTE_LOG_REGISTER_DEFAULT(rte_eth_dev_logtype, INFO);
 
 RTE_INIT(ethdev_init_telemetry)
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index 891f9a6e06..c4024d2265 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -5245,6 +5245,63 @@ __rte_experimental
 int rte_eth_ip_reassembly_conf_set(uint16_t port_id,
   struct rte_eth_ip_reass_params *conf);
 
+/**
+ * In case of IP reassembly offload failure, ol_flags in mbuf will be set
+ * with RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE and packets will be returned
+ * without alteration. The application can retrieve the attached fragments
+ * using mbuf dynamic field.
+ */
+typedef struct {
+   /**
+* Next fragment packet. Application should fetch dynamic field of
+* each fragment until a NULL is received and nb_frags is 0.
+*/
+   struct rte_mbuf *next_frag;
+   /** Time spent(in ms) by HW in waiting for further fragments. */
+   uint16_t time_spent;
+   /** Number of more fragments attached in mbuf dynamic fields. */
+   uint16_t nb_frags;
+} rte_eth_ip_reass_dynfield_t;
+
+extern int rte_eth_ip_reass_dynfield_offset;
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Get pointer to mbuf dynamic field for getting incomplete
+ * reassembled fragments.
+ *
+ * For performance reason, no check is done,
+ * the dynamic field may not be registered.
+ * @see rte_eth_ip_reass_dynfield_is_registered
+ *
+ * @param  mbufpacket to access
+ * @return pointer to mbuf dynamic field
+ */
+__rte_experimental
+static inline rte_eth_ip_reass_dynfield_t *
+rte_eth_ip_reass_dynfield(struct rte_mbuf *mbuf)
+{
+   return RTE_MBUF_DYNFIELD(mbuf,
+   rte_eth_ip_reass_dynfield_offset,
+   rte_eth_ip_reass_dynfield_t *);
+}
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ *
+ * Check whether the dynamic field is registered.
+ *
+ * @return true if rte_eth_ip_reass_dynfield_register() has been called.
+ */
+__rte_experimental
+static inline bool rte_eth_ip_reass_dynfield_is_registered(void)
+{
+   return rte_eth_ip_reass_dynfield_offset >= 0;
+}
+
 
 #include 
 
diff --git a/lib/ethdev/version.map b/lib/ethdev/version.map
index f08fe72044..e824b776b1 100644
--- a/lib/ethdev/version.map
+++ b/lib/ethdev/version.map
@@ -259,6 +259,7 @@ EXPERIMENTAL {
 
#added in 22.03
rte_eth_ip_reassembly_conf_set;
+   rte_eth_ip_reass_dynfield_offset;
 };
 
 INTERNAL {
@@ -282,6 +283,7 @@ INTERNAL {
rte_eth_hairpin_queue_peer_bind;
rte_eth_hairpin_queue_peer_unbind;
rte_eth_hairpin_queue_peer_update;
+   rte_eth_ip_reass_

[PATCH 4/8] security: add IPsec option for IP reassembly

[Akhil Goyal]

A new option is added in IPsec to enable and attempt reassembly
of inbound packets.

Signed-off-by: Akhil Goyal 
---
 lib/security/rte_security.h | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/lib/security/rte_security.h b/lib/security/rte_security.h
index 1228b6c8b1..168b837a82 100644
--- a/lib/security/rte_security.h
+++ b/lib/security/rte_security.h
@@ -264,6 +264,16 @@ struct rte_security_ipsec_sa_options {
 */
uint32_t l4_csum_enable : 1;
 
+   /** Enable reassembly on incoming packets.
+*
+* * 1: Enable driver to try reassembly of encrypted IP packets for
+*  this SA, if supported by the driver. This feature will work
+*  only if rx_offload RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY is set in
+*  inline Ethernet device.
+* * 0: Disable reassembly of packets (default).
+*/
+   uint32_t reass_en : 1;
+
/** Reserved bit fields for future extension
 *
 * User should ensure reserved_opts is cleared as it may change in
@@ -271,7 +281,7 @@ struct rte_security_ipsec_sa_options {
 *
 * Note: Reduce number of bits in reserved_opts for every new option.
 */
-   uint32_t reserved_opts : 18;
+   uint32_t reserved_opts : 17;
 };
 
 /** IPSec security association direction */
-- 
2.25.1

[PATCH 5/8] app/test: add unit cases for inline IPsec offload

[Akhil Goyal]

A new test suite is added in test app to test inline IPsec protocol
offload. In this patch, a couple of predefined plain and cipher test
vectors are used to verify the IPsec functionality without the need of
external traffic generators. The sent packet is loopbacked onto the same
interface which is received and matched with the expected output.
The test suite can be updated further with other functional test cases.
The testsuite can be run using:
RTE> inline_ipsec_autotest

Signed-off-by: Akhil Goyal 
---
 app/test/meson.build  |   1 +
 app/test/test_inline_ipsec.c  | 728 ++
 .../test_inline_ipsec_reassembly_vectors.h| 198 +
 3 files changed, 927 insertions(+)
 create mode 100644 app/test/test_inline_ipsec.c
 create mode 100644 app/test/test_inline_ipsec_reassembly_vectors.h

diff --git a/app/test/meson.build b/app/test/meson.build
index 2b480adfba..9c88240e3f 100644
--- a/app/test/meson.build
+++ b/app/test/meson.build
@@ -74,6 +74,7 @@ test_sources = files(
 'test_hash_readwrite.c',
 'test_hash_perf.c',
 'test_hash_readwrite_lf_perf.c',
+   'test_inline_ipsec.c',
 'test_interrupts.c',
 'test_ipfrag.c',
 'test_ipsec.c',
diff --git a/app/test/test_inline_ipsec.c b/app/test/test_inline_ipsec.c
new file mode 100644
index 00..54b56ba9e8
--- /dev/null
+++ b/app/test/test_inline_ipsec.c
@@ -0,0 +1,728 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "test_inline_ipsec_reassembly_vectors.h"
+#include "test.h"
+
+#define NB_ETHPORTS_USED(1)
+#define NB_SOCKETS  (2)
+#define MEMPOOL_CACHE_SIZE 32
+#define MAX_PKT_BURST   (32)
+#define RTE_TEST_RX_DESC_DEFAULT(1024)
+#define RTE_TEST_TX_DESC_DEFAULT(1024)
+#define RTE_PORT_ALL(~(uint16_t)0x0)
+
+/*
+ * RX and TX Prefetch, Host, and Write-back threshold values should be
+ * carefully set for optimal performance. Consult the network
+ * controller's datasheet and supporting DPDK documentation for guidance
+ * on how these parameters should be set.
+ */
+#define RX_PTHRESH 8 /**< Default values of RX prefetch threshold reg. */
+#define RX_HTHRESH 8 /**< Default values of RX host threshold reg. */
+#define RX_WTHRESH 0 /**< Default values of RX write-back threshold reg. */
+
+#define TX_PTHRESH 32 /**< Default values of TX prefetch threshold reg. */
+#define TX_HTHRESH 0  /**< Default values of TX host threshold reg. */
+#define TX_WTHRESH 0  /**< Default values of TX write-back threshold reg. */
+
+#define MAX_TRAFFIC_BURST  2048
+
+#define NB_MBUF 1024
+
+#define APP_REASS_TIMEOUT  20
+
+static struct rte_mempool *mbufpool[NB_SOCKETS];
+static struct rte_mempool *sess_pool[NB_SOCKETS];
+static struct rte_mempool *sess_priv_pool[NB_SOCKETS];
+/* ethernet addresses of ports */
+static struct rte_ether_addr ports_eth_addr[RTE_MAX_ETHPORTS];
+
+static struct rte_eth_conf port_conf = {
+   .rxmode = {
+   .mq_mode = RTE_ETH_MQ_RX_NONE,
+   .split_hdr_size = 0,
+   .offloads = RTE_ETH_RX_OFFLOAD_IP_REASSEMBLY |
+   RTE_ETH_RX_OFFLOAD_CHECKSUM |
+   RTE_ETH_RX_OFFLOAD_SECURITY,
+   },
+   .txmode = {
+   .mq_mode = RTE_ETH_MQ_TX_NONE,
+   .offloads = RTE_ETH_TX_OFFLOAD_SECURITY |
+   RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE,
+   },
+   .lpbk_mode = 1,  /* enable loopback */
+};
+
+static struct rte_eth_rxconf rx_conf = {
+   .rx_thresh = {
+   .pthresh = RX_PTHRESH,
+   .hthresh = RX_HTHRESH,
+   .wthresh = RX_WTHRESH,
+   },
+   .rx_free_thresh = 32,
+};
+
+static struct rte_eth_txconf tx_conf = {
+   .tx_thresh = {
+   .pthresh = TX_PTHRESH,
+   .hthresh = TX_HTHRESH,
+   .wthresh = TX_WTHRESH,
+   },
+   .tx_free_thresh = 32, /* Use PMD default values */
+   .tx_rs_thresh = 32, /* Use PMD default values */
+};
+
+enum {
+   LCORE_INVALID = 0,
+   LCORE_AVAIL,
+   LCORE_USED,
+};
+
+struct lcore_cfg {
+   uint8_t status;
+   uint8_t socketid;
+   uint16_t nb_ports;
+   uint16_t port;
+} __rte_cache_aligned;
+
+struct lcore_cfg lcore_cfg;
+
+static uint64_t link_mbps;
+
+/* Create Inline IPsec session */
+static int
+create_inline_ipsec_session(struct ipsec_session_data *sa,
+   uint16_t portid, struct rte_ipsec_session *ips,
+   enum rte_security_ipsec_sa_direction dir,
+   enum rte_security_ipsec_tunnel_type tun_type)
+{
+   int32_t ret = 0;
+   struct rte_security_ctx *sec_ctx;
+   uint32_t src_v4 = rte_cpu_to_be_32(RTE_IPV4(192, 168, 1, 0));
+   uint32_t dst_v4 =

[PATCH 6/8] app/test: add IP reassembly case with no frags

[Akhil Goyal]

test_inline_ipsec testsuite is extended to test IP reassembly of inbound
fragmented packets. The fragmented packet is sent on an interface
which encrypts the packet and then it is loopbacked on the
same interface which decrypts the packet and then attempts IP reassembly
of the decrypted packets.
In this patch, a case is added for packets without fragmentation to
verify the complete path. Other cases are added in subsequent patches.

Signed-off-by: Akhil Goyal 
---
 app/test/test_inline_ipsec.c | 154 +++
 1 file changed, 154 insertions(+)

diff --git a/app/test/test_inline_ipsec.c b/app/test/test_inline_ipsec.c
index 54b56ba9e8..f704725c0f 100644
--- a/app/test/test_inline_ipsec.c
+++ b/app/test/test_inline_ipsec.c
@@ -460,6 +460,145 @@ create_default_flow(uint16_t port_id)
 
 struct rte_mbuf **tx_pkts_burst;
 
+static int
+compare_pkt_data(struct rte_mbuf *m, uint8_t *ref, unsigned int tot_len)
+{
+   unsigned int len;
+   unsigned int nb_segs = m->nb_segs;
+   unsigned int matched = 0;
+
+   while (m && nb_segs != 0) {
+   len = tot_len;
+   if (len > m->data_len)
+   len = m->data_len;
+   if (len != 0) {
+   if (memcmp(rte_pktmbuf_mtod(m, char *),
+   ref + matched, len)) {
+   printf("\nReassembly case failed: Data 
Mismatch");
+   rte_hexdump(stdout, "Reassembled",
+   rte_pktmbuf_mtod(m, char *),
+   len);
+   rte_hexdump(stdout, "reference",
+   ref + matched,
+   len);
+   return TEST_FAILED;
+   }
+   }
+   tot_len -= len;
+   matched += len;
+   m = m->next;
+   nb_segs--;
+   }
+   return TEST_SUCCESS;
+}
+
+static int
+test_reassembly(struct reassembly_vector *vector,
+   enum rte_security_ipsec_tunnel_type tun_type)
+{
+   struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
+   unsigned i, portid, nb_rx = 0, nb_tx = 0;
+   struct rte_ipsec_session out_ips = {0};
+   struct rte_ipsec_session in_ips = {0};
+   struct rte_eth_dev_info dev_info = {0};
+   int ret = 0;
+
+   /* Initialize mbuf with test vectors. */
+   nb_tx = reass_test_vectors_init(vector);
+
+   portid = lcore_cfg.port;
+   rte_eth_dev_info_get(portid, &dev_info);
+   if (dev_info.reass_capa.max_frags < nb_tx)
+   return TEST_SKIPPED;
+
+   /**
+* Set some finite value in timeout incase PMD support much
+* more than requied in this app.
+*/
+   if (dev_info.reass_capa.reass_timeout > APP_REASS_TIMEOUT) {
+   dev_info.reass_capa.reass_timeout = APP_REASS_TIMEOUT;
+   rte_eth_ip_reassembly_conf_set(portid, &dev_info.reass_capa);
+   }
+
+   init_traffic(mbufpool[lcore_cfg.socketid],
+   tx_pkts_burst, vector->frags, nb_tx);
+
+   /* Create Inline IPsec outbound session. */
+   ret = create_inline_ipsec_session(vector->sa_data, portid, &out_ips,
+   RTE_SECURITY_IPSEC_SA_DIR_EGRESS, tun_type);
+   if (ret)
+   return ret;
+   for (i = 0; i < nb_tx; i++) {
+   if (out_ips.security.ol_flags &
+   RTE_SECURITY_TX_OLOAD_NEED_MDATA)
+   rte_security_set_pkt_metadata(out_ips.security.ctx,
+   out_ips.security.ses, tx_pkts_burst[i], NULL);
+   tx_pkts_burst[i]->ol_flags |= RTE_MBUF_F_TX_SEC_OFFLOAD;
+   tx_pkts_burst[i]->l2_len = RTE_ETHER_HDR_LEN;
+   }
+   /* Create Inline IPsec inbound session. */
+   create_inline_ipsec_session(vector->sa_data, portid, &in_ips,
+   RTE_SECURITY_IPSEC_SA_DIR_INGRESS, tun_type);
+   create_default_flow(portid);
+
+   nb_tx = rte_eth_tx_burst(portid, 0, tx_pkts_burst, nb_tx);
+
+   rte_pause();
+
+   do {
+   nb_rx = rte_eth_rx_burst(portid, 0, pkts_burst, MAX_PKT_BURST);
+   for (i = 0; i < nb_rx; i++) {
+   if ((pkts_burst[i]->ol_flags &
+   RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE) &&
+   rte_eth_ip_reass_dynfield_is_registered()) {
+   rte_eth_ip_reass_dynfield_t 
*dynfield[MAX_PKT_BURST];
+   int j = 0;
+
+   dynfield[j] = 
rte_eth_ip_reass_dynfield(pkts_burst[i]);
+   while ((dynfield[j]->next_frag->ol_flags &
+   RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE) &&
+   dynfield[j]->nb_frags > 0) {
+
+

[PATCH 7/8] app/test: add IP reassembly cases with multiple fragments

[Akhil Goyal]

More cases are added in test_inline_ipsec test suite to verify packets
having multiple IP(v4/v6) fragments. These fragments are encrypted
and then decrypted as per inline IPsec processing and then an attempt
is made to reassemble the fragments. The reassembled packet
content is matched with the known test vectors.

Signed-off-by: Akhil Goyal 
---
 app/test/test_inline_ipsec.c  | 101 +++
 .../test_inline_ipsec_reassembly_vectors.h| 592 ++
 2 files changed, 693 insertions(+)

diff --git a/app/test/test_inline_ipsec.c b/app/test/test_inline_ipsec.c
index f704725c0f..3f3731760d 100644
--- a/app/test/test_inline_ipsec.c
+++ b/app/test/test_inline_ipsec.c
@@ -853,6 +853,89 @@ test_reassembly_ipv4_nofrag(void) {
RTE_SECURITY_IPSEC_TUNNEL_IPV4);
 }
 
+static int
+test_reassembly_ipv4_2frag(void) {
+   struct reassembly_vector ipv4_2frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p1,
+   .frags[0] = &pkt_ipv4_udp_p1_f1,
+   .frags[1] = &pkt_ipv4_udp_p1_f2,
+
+   };
+   return test_reassembly(&ipv4_2frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
+
+static int
+test_reassembly_ipv6_2frag(void) {
+   struct reassembly_vector ipv6_2frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv6_udp_p1,
+   .frags[0] = &pkt_ipv6_udp_p1_f1,
+   .frags[1] = &pkt_ipv6_udp_p1_f2,
+   };
+   return test_reassembly(&ipv6_2frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV6);
+}
+
+static int
+test_reassembly_ipv4_4frag(void) {
+   struct reassembly_vector ipv4_4frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p2,
+   .frags[0] = &pkt_ipv4_udp_p2_f1,
+   .frags[1] = &pkt_ipv4_udp_p2_f2,
+   .frags[2] = &pkt_ipv4_udp_p2_f3,
+   .frags[3] = &pkt_ipv4_udp_p2_f4,
+   };
+   return test_reassembly(&ipv4_4frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
+
+static int
+test_reassembly_ipv6_4frag(void) {
+   struct reassembly_vector ipv6_4frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv6_udp_p2,
+   .frags[0] = &pkt_ipv6_udp_p2_f1,
+   .frags[1] = &pkt_ipv6_udp_p2_f2,
+   .frags[2] = &pkt_ipv6_udp_p2_f3,
+   .frags[3] = &pkt_ipv6_udp_p2_f4,
+   };
+   return test_reassembly(&ipv6_4frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV6);
+}
+
+static int
+test_reassembly_ipv4_5frag(void) {
+   struct reassembly_vector ipv4_5frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p3,
+   .frags[0] = &pkt_ipv4_udp_p3_f1,
+   .frags[1] = &pkt_ipv4_udp_p3_f2,
+   .frags[2] = &pkt_ipv4_udp_p3_f3,
+   .frags[3] = &pkt_ipv4_udp_p3_f4,
+   .frags[4] = &pkt_ipv4_udp_p3_f5,
+   };
+   return test_reassembly(&ipv4_5frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
+
+static int
+test_reassembly_ipv6_5frag(void) {
+   struct reassembly_vector ipv6_5frag_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv6_udp_p3,
+   .frags[0] = &pkt_ipv6_udp_p3_f1,
+   .frags[1] = &pkt_ipv6_udp_p3_f2,
+   .frags[2] = &pkt_ipv6_udp_p3_f3,
+   .frags[3] = &pkt_ipv6_udp_p3_f4,
+   .frags[4] = &pkt_ipv6_udp_p3_f5,
+   };
+   return test_reassembly(&ipv6_5frag_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV6);
+}
+
 
 static struct unit_test_suite inline_ipsec_testsuite  = {
.suite_name = "Inline IPsec Ethernet Device Unit Test Suite",
@@ -868,6 +951,24 @@ static struct unit_test_suite inline_ipsec_testsuite  = {
TEST_CASE_ST(ut_setup_inline_ipsec,
ut_teardown_inline_ipsec,
test_reassembly_ipv4_nofrag),
+   TEST_CASE_ST(ut_setup_inline_ipsec,
+   ut_teardown_inline_ipsec,
+   test_reassembly_ipv4_2frag),
+   TEST_CASE_ST(ut_setup_inline_ipsec,
+   ut_teardown_inline_ipsec,
+

[PATCH 8/8] app/test: add IP reassembly negative cases

[Akhil Goyal]

test_inline_ipsec testsuite is added with cases where the IP reassembly
is incomplete and software will need to reassemble them later.
The failure cases added are:
- all fragments are not received.
- same fragment is received more than once.
- out of order fragments.

Signed-off-by: Akhil Goyal 
---
 app/test/test_inline_ipsec.c | 53 
 1 file changed, 53 insertions(+)

diff --git a/app/test/test_inline_ipsec.c b/app/test/test_inline_ipsec.c
index 3f3731760d..0d74e23359 100644
--- a/app/test/test_inline_ipsec.c
+++ b/app/test/test_inline_ipsec.c
@@ -936,6 +936,50 @@ test_reassembly_ipv6_5frag(void) {
RTE_SECURITY_IPSEC_TUNNEL_IPV6);
 }
 
+static int
+test_reassembly_incomplete(void) {
+   /* Negative test case, not sending all fragments. */
+   struct reassembly_vector ipv4_incomplete_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p2,
+   .frags[0] = &pkt_ipv4_udp_p2_f1,
+   .frags[1] = &pkt_ipv4_udp_p2_f2,
+   .frags[2] = NULL,
+   .frags[3] = NULL,
+   };
+   return test_reassembly(&ipv4_incomplete_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
+
+static int
+test_reassembly_overlap(void) {
+   /* Negative test case, sending 1 fragment twice. */
+   struct reassembly_vector ipv4_overlap_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p2,
+   .frags[0] = &pkt_ipv4_udp_p2_f1,
+   .frags[1] = &pkt_ipv4_udp_p2_f2,
+   .frags[2] = &pkt_ipv4_udp_p2_f2, /* overlap */
+   .frags[3] = &pkt_ipv4_udp_p2_f3,
+   };
+   return test_reassembly(&ipv4_overlap_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
+
+static int
+test_reassembly_out_of_order(void) {
+   /* Negative test case, sending 1 fragment twice. */
+   struct reassembly_vector ipv4_ooo_case = {
+   .sa_data = &conf_aes_128_gcm,
+   .full_pkt = &pkt_ipv4_udp_p2,
+   .frags[0] = &pkt_ipv4_udp_p2_f4,
+   .frags[1] = &pkt_ipv4_udp_p2_f3,
+   .frags[2] = &pkt_ipv4_udp_p2_f1,
+   .frags[3] = &pkt_ipv4_udp_p2_f2,
+   };
+   return test_reassembly(&ipv4_ooo_case,
+   RTE_SECURITY_IPSEC_TUNNEL_IPV4);
+}
 
 static struct unit_test_suite inline_ipsec_testsuite  = {
.suite_name = "Inline IPsec Ethernet Device Unit Test Suite",
@@ -969,6 +1013,15 @@ static struct unit_test_suite inline_ipsec_testsuite  = {
TEST_CASE_ST(ut_setup_inline_ipsec,
ut_teardown_inline_ipsec,
test_reassembly_ipv6_5frag),
+   TEST_CASE_ST(ut_setup_inline_ipsec,
+   ut_teardown_inline_ipsec,
+   test_reassembly_incomplete),
+   TEST_CASE_ST(ut_setup_inline_ipsec,
+   ut_teardown_inline_ipsec,
+   test_reassembly_overlap),
+   TEST_CASE_ST(ut_setup_inline_ipsec,
+   ut_teardown_inline_ipsec,
+   test_reassembly_out_of_order),
 
TEST_CASES_END() /**< NULL terminate unit test array */
}
-- 
2.25.1

[PATCH 0/5] net/cnxk: support IP reassembly offload

[Akhil Goyal]

cn10k platform can support IP reassembly offload for upto 4 fragments
in the inline IPsec path.
The feature is enabled and tested as per [1].

The patchset depends on [1] and [2] patchsets.

[1]: http://patches.dpdk.org/project/dpdk/list/?series=21052
[2]: http://patches.dpdk.org/project/dpdk/list/?series=20922


Nithin Dabilpuram (2):
  net/cnxk: add dev args for min-max spi
  net/cnxk: add option to override outbound inline sa iv

Vidya Sagar Velumuri (3):
  common/cnxk: configure reassembly specific params
  net/cnxk: reassembly support
  net/cnxk: support IP reassembly mbuf dynfield

 drivers/common/cnxk/cnxk_security.c   |   5 +-
 drivers/common/cnxk/roc_nix.h |   1 +
 drivers/common/cnxk/roc_nix_inl.c |  83 ++-
 drivers/common/cnxk/roc_nix_inl.h |  15 +-
 drivers/common/cnxk/roc_nix_inl_dev.c |  22 +-
 drivers/common/cnxk/roc_nix_inl_priv.h|   4 +-
 drivers/common/cnxk/roc_nix_priv.h|   1 +
 drivers/common/cnxk/version.map   |   3 +-
 drivers/event/cnxk/cn10k_eventdev.c   |   1 -
 drivers/event/cnxk/cn10k_worker.h |  12 +-
 drivers/event/cnxk/deq/cn10k/deq_128_143.c|  12 +
 .../event/cnxk/deq/cn10k/deq_128_143_burst.c  |  14 +
 drivers/event/cnxk/deq/cn10k/deq_128_143_ca.c |  12 +
 .../cnxk/deq/cn10k/deq_128_143_ca_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_128_143_ca_seg.c |  12 +
 .../cnxk/deq/cn10k/deq_128_143_ca_seg_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_128_143_ca_tmo.c |  12 +
 .../cnxk/deq/cn10k/deq_128_143_ca_tmo_burst.c |  14 +
 .../cnxk/deq/cn10k/deq_128_143_ca_tmo_seg.c   |  13 +
 .../deq/cn10k/deq_128_143_ca_tmo_seg_burst.c  |  14 +
 .../event/cnxk/deq/cn10k/deq_128_143_dual.c   |  12 +
 .../event/cnxk/deq/cn10k/deq_128_143_seg.c|  12 +
 .../cnxk/deq/cn10k/deq_128_143_seg_burst.c|  14 +
 .../event/cnxk/deq/cn10k/deq_128_143_tmo.c|  12 +
 .../cnxk/deq/cn10k/deq_128_143_tmo_burst.c|  14 +
 .../cnxk/deq/cn10k/deq_128_143_tmo_seg.c  |  12 +
 .../deq/cn10k/deq_128_143_tmo_seg_burst.c |  14 +
 drivers/event/cnxk/deq/cn10k/deq_144_159.c|  12 +
 .../event/cnxk/deq/cn10k/deq_144_159_burst.c  |  14 +
 drivers/event/cnxk/deq/cn10k/deq_144_159_ca.c |  12 +
 .../cnxk/deq/cn10k/deq_144_159_ca_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_144_159_ca_seg.c |  12 +
 .../cnxk/deq/cn10k/deq_144_159_ca_seg_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_144_159_ca_tmo.c |  12 +
 .../cnxk/deq/cn10k/deq_144_159_ca_tmo_burst.c |  14 +
 .../cnxk/deq/cn10k/deq_144_159_ca_tmo_seg.c   |  13 +
 .../deq/cn10k/deq_144_159_ca_tmo_seg_burst.c  |  14 +
 .../event/cnxk/deq/cn10k/deq_144_159_dual.c   |  12 +
 .../event/cnxk/deq/cn10k/deq_144_159_seg.c|  12 +
 .../cnxk/deq/cn10k/deq_144_159_seg_burst.c|  14 +
 .../event/cnxk/deq/cn10k/deq_144_159_tmo.c|  12 +
 .../cnxk/deq/cn10k/deq_144_159_tmo_burst.c|  14 +
 .../cnxk/deq/cn10k/deq_144_159_tmo_seg.c  |  12 +
 .../deq/cn10k/deq_144_159_tmo_seg_burst.c |  14 +
 drivers/event/cnxk/deq/cn10k/deq_160_175.c|  12 +
 .../event/cnxk/deq/cn10k/deq_160_175_burst.c  |  14 +
 drivers/event/cnxk/deq/cn10k/deq_160_175_ca.c |  12 +
 .../cnxk/deq/cn10k/deq_160_175_ca_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_160_175_ca_seg.c |  12 +
 .../cnxk/deq/cn10k/deq_160_175_ca_seg_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_160_175_ca_tmo.c |  12 +
 .../cnxk/deq/cn10k/deq_160_175_ca_tmo_burst.c |  14 +
 .../cnxk/deq/cn10k/deq_160_175_ca_tmo_seg.c   |  13 +
 .../deq/cn10k/deq_160_175_ca_tmo_seg_burst.c  |  14 +
 .../event/cnxk/deq/cn10k/deq_160_175_dual.c   |  12 +
 .../event/cnxk/deq/cn10k/deq_160_175_seg.c|  12 +
 .../cnxk/deq/cn10k/deq_160_175_seg_burst.c|  14 +
 .../event/cnxk/deq/cn10k/deq_160_175_tmo.c|  12 +
 .../cnxk/deq/cn10k/deq_160_175_tmo_burst.c|  14 +
 .../cnxk/deq/cn10k/deq_160_175_tmo_seg.c  |  12 +
 .../deq/cn10k/deq_160_175_tmo_seg_burst.c |  14 +
 drivers/event/cnxk/deq/cn10k/deq_176_191.c|  12 +
 .../event/cnxk/deq/cn10k/deq_176_191_burst.c  |  14 +
 drivers/event/cnxk/deq/cn10k/deq_176_191_ca.c |  12 +
 .../cnxk/deq/cn10k/deq_176_191_ca_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_176_191_ca_seg.c |  12 +
 .../cnxk/deq/cn10k/deq_176_191_ca_seg_burst.c |  14 +
 .../event/cnxk/deq/cn10k/deq_176_191_ca_tmo.c |  12 +
 .../cnxk/deq/cn10k/deq_176_191_ca_tmo_burst.c |  14 +
 .../cnxk/deq/cn10k/deq_176_191_ca_tmo_seg.c   |  13 +
 .../deq/cn10k/deq_176_191_ca_tmo_seg_burst.c  |  14 +
 .../event/cnxk/deq/cn10k/deq_176_191_dual.c   |  12 +
 .../event/cnxk/deq/cn10k/deq_176_191_seg.c|  12 +
 .../cnxk/deq/cn10k/deq_176_191_seg_burst.c|  14 +
 .../event/cnxk/deq/cn10k/deq_176_191_tmo.c|  12 +
 .../cnxk/deq/cn10k/deq_176_191_tmo_burst.c|  14 +
 .../cnxk/deq/cn10k/deq_176_191_tmo_seg.c  |  12 +
 .../deq/cn10k/deq_176_191_tmo_seg_burst.c |  14 +
 drivers/event/cnxk/deq/cn10k/deq_192_207.c|  12 +
 .../event/cnxk/deq/cn10k/deq_192_207_burst.c  |  1

[PATCH 1/5] common/cnxk: configure reassembly specific params

[Akhil Goyal]

From: Vidya Sagar Velumuri 

When reassembly is enabled by application, set corresponding
flags in SA during creation.

Provide roc API to configure reassembly unit with active and zombie limits
and step size

Signed-off-by: Vidya Sagar Velumuri 
---
 drivers/common/cnxk/cnxk_security.c |  5 -
 drivers/common/cnxk/roc_nix_inl.c   | 23 +++
 drivers/common/cnxk/roc_nix_inl.h   |  7 +++
 drivers/common/cnxk/version.map |  1 +
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/cnxk_security.c 
b/drivers/common/cnxk/cnxk_security.c
index 30562b46e3..9bd85fc4b4 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -295,9 +295,12 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 * second pass meta and no defrag.
 */
sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
-   sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+   sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG;
sa->w0.s.pkind = ROC_OT_CPT_META_PKIND;
 
+   if (ipsec_xfrm->options.reass_en)
+   sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
+
/* ESN */
sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
if (ipsec_xfrm->options.udp_encap) {
diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index f0fc690417..6bfd10adde 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -200,6 +200,29 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool 
inb_inl_dev, uint32_t spi)
return (sa_base + (spi * sz));
 }
 
+int
+roc_nix_reass_configure(uint32_t max_wait_time, uint16_t max_frags)
+{
+   struct idev_cfg *idev = idev_get_cfg();
+   struct roc_cpt *roc_cpt;
+   struct roc_cpt_rxc_time_cfg *cfg;
+
+   roc_cpt = idev->cpt;
+   if (!roc_cpt) {
+   plt_err("Cannot support inline inbound, cryptodev not probed");
+   return -ENOTSUP;
+   }
+
+   cfg->step = (max_wait_time / ROC_NIX_INL_REAS_ACTIVE_LIMIT) * 1000;
+   cfg->zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
+   cfg->zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
+   cfg->active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT;
+   cfg->active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
+
+   roc_cpt_rxc_time_cfg(roc_cpt, cfg);
+   return 0;
+}
+
 int
 roc_nix_inl_inb_init(struct roc_nix *roc_nix)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl.h 
b/drivers/common/cnxk/roc_nix_inl.h
index abbeac684a..73a17276c4 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -43,6 +43,11 @@
 /* Alignment of SA Base */
 #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
 
+#define ROC_NIX_INL_REAS_ACTIVE_LIMIT0xFFF
+#define ROC_NIX_INL_REAS_ACTIVE_THRESHOLD 10
+#define ROC_NIX_INL_REAS_ZOMBIE_LIMIT0xFFF
+#define ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD 10
+
 static inline struct roc_onf_ipsec_inb_sa *
 roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx)
 {
@@ -124,6 +129,8 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev 
*roc_inl_dev);
 bool __roc_api roc_nix_inl_dev_is_probed(void);
 void __roc_api roc_nix_inl_dev_lock(void);
 void __roc_api roc_nix_inl_dev_unlock(void);
+int __roc_api roc_nix_reass_configure(uint32_t max_wait_time,
+ uint16_t max_frags);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 07c6720f0c..9b04f3518a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -203,6 +203,7 @@ INTERNAL {
roc_nix_ptp_tx_ena_dis;
roc_nix_queues_ctx_dump;
roc_nix_ras_intr_ena_dis;
+   roc_nix_reass_configure;
roc_nix_register_cq_irqs;
roc_nix_register_queue_irqs;
roc_nix_rq_dump;
-- 
2.25.1

[PATCH 3/5] net/cnxk: support IP reassembly mbuf dynfield

[Akhil Goyal]

From: Vidya Sagar Velumuri 

Register the dynamic field for IPsec reassembly.
Attach the fragments using the dynamic field in case of incomplete
reassembly

Signed-off-by: Vidya Sagar Velumuri 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c |  3 +++
 drivers/net/cnxk/cn10k_rx.h | 38 +++--
 2 files changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 235c16840e..f20a111cd9 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -249,6 +249,9 @@ cn10k_eth_sec_session_create(void *device,
if (rte_security_dynfield_register() < 0)
return -ENOTSUP;
 
+   if (rte_eth_ip_reass_dynfield_register() < 0)
+   return -rte_errno;
+
if (rte_eal_process_type() == RTE_PROC_PRIMARY)
roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
 
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 5c415634a9..0ba60ed22f 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -94,7 +94,7 @@ nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr,
uint32_t offset = hdr->w2.fi_offset;
union nix_rx_parse_u *frag_rx;
struct cpt_frag_info_s *finfo;
-   struct rte_mbuf *head, *mbuf;
+   struct rte_mbuf *head, *mbuf, *mbuf_prev;
uint64_t *frag_ptr;
uint16_t frag_size;
uint16_t rlen;
@@ -115,10 +115,15 @@ nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr,
mbuf = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
mbuf->data_len = frag_size;
mbuf->pkt_len = frag_size;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE;
head = mbuf;
+   mbuf_prev = mbuf;
/* Update dynamic field with userdata */
*rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
 
+   rte_eth_ip_reass_dynfield(head)->nb_frags = hdr->w0.num_frags - 1;
+   rte_eth_ip_reass_dynfield(head)->next_frag = NULL;
+
/* Frag-1: */
if (hdr->w0.num_frags > 1) {
wqe = (uint64_t *)(rte_be_to_cpu_64(hdr->frag1_wqe_ptr));
@@ -128,13 +133,19 @@ nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr,
frag_size = rlen + frag_rx->lcptr - frag_rx->laptr;
frag_rx->pkt_lenm1 = frag_size - 1;
 
-   mbuf->next = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
-   mbuf = mbuf->next;
+   mbuf = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
mbuf->data_len = frag_size;
mbuf->pkt_len = frag_size;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE;
 
/* Update dynamic field with userdata */
*rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
+
+   rte_eth_ip_reass_dynfield(mbuf)->nb_frags =
+   hdr->w0.num_frags - 2;
+   rte_eth_ip_reass_dynfield(mbuf)->next_frag = NULL;
+   rte_eth_ip_reass_dynfield(mbuf_prev)->next_frag = mbuf;
+   mbuf_prev = mbuf;
}
 
/* Frag-2: */
@@ -147,13 +158,19 @@ nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr,
frag_size = rlen + frag_rx->lcptr - frag_rx->laptr;
frag_rx->pkt_lenm1 = frag_size - 1;
 
-   mbuf->next = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
-   mbuf = mbuf->next;
+   mbuf = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
mbuf->data_len = frag_size;
mbuf->pkt_len = frag_size;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE;
 
/* Update dynamic field with userdata */
*rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
+
+   rte_eth_ip_reass_dynfield(mbuf)->nb_frags =
+   hdr->w0.num_frags - 3;
+   rte_eth_ip_reass_dynfield(mbuf)->next_frag = NULL;
+   rte_eth_ip_reass_dynfield(mbuf_prev)->next_frag = mbuf;
+   mbuf_prev = mbuf;
}
 
/* Frag-3: */
@@ -165,16 +182,21 @@ nix_sec_attach_frags(const struct cpt_parse_hdr_s *hdr,
frag_size = rlen + frag_rx->lcptr - frag_rx->laptr;
frag_rx->pkt_lenm1 = frag_size - 1;
 
-   mbuf->next = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
-   mbuf = mbuf->next;
+   mbuf = (struct rte_mbuf *)(wqe - sizeof(struct rte_mbuf));
mbuf->data_len = frag_size;
mbuf->pkt_len = frag_size;
+   mbuf->ol_flags |= RTE_MBUF_F_RX_IPREASSEMBLY_INCOMPLETE;
 
/* Update dynamic field with userdata */
*rte_security_dynfield(mbuf) = (uint64_t)inb_priv->userdata;
+
+   rte_eth_ip_reass_dynfield(mbuf)->nb_frags =
+   hdr->w0.num_frags

[PATCH 4/5] net/cnxk: add dev args for min-max spi

[Akhil Goyal]

From: Nithin Dabilpuram 

Dev args for setting minimum and maximum SPI value that the
hardware can support and create database for SA lookup in
inline IPsec processing is added.

Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/cnxk/roc_nix.h  |  1 +
 drivers/common/cnxk/roc_nix_inl.c  | 59 --
 drivers/common/cnxk/roc_nix_inl.h  |  8 ++--
 drivers/common/cnxk/roc_nix_inl_dev.c  | 22 +++---
 drivers/common/cnxk/roc_nix_inl_priv.h |  4 +-
 drivers/common/cnxk/roc_nix_priv.h |  1 +
 drivers/common/cnxk/version.map|  2 +-
 drivers/net/cnxk/cn10k_ethdev_sec.c| 13 --
 drivers/net/cnxk/cn9k_ethdev_sec.c | 10 +++--
 drivers/net/cnxk/cnxk_ethdev_devargs.c | 19 ++---
 drivers/net/cnxk/cnxk_ethdev_sec.c | 13 --
 drivers/net/cnxk/cnxk_lookup.c |  3 +-
 12 files changed, 101 insertions(+), 54 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 69a5e8e7b4..912ad9b990 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -381,6 +381,7 @@ struct roc_nix {
uint32_t outb_nb_desc;
uint16_t outb_nb_crypto_qs;
uint16_t ipsec_in_max_spi;
+   uint16_t ipsec_in_min_spi;
uint16_t ipsec_out_max_sa;
/* End of input parameters */
/* LMT line base for "Per Core Tx LMT line" mode*/
diff --git a/drivers/common/cnxk/roc_nix_inl.c 
b/drivers/common/cnxk/roc_nix_inl.c
index a06872f6f3..05afabd10a 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -20,11 +20,15 @@ static int
 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 {
uint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
+   uint16_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
struct roc_nix_ipsec_cfg cfg;
+   uint64_t max_sa, i;
size_t inb_sa_sz;
-   int rc, i;
void *sa;
+   int rc;
+
+   max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
 
/* CN9K SA size is different */
if (roc_model_is_cn9k())
@@ -34,14 +38,15 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 
/* Alloc contiguous memory for Inbound SA's */
nix->inb_sa_sz = inb_sa_sz;
-   nix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
+   nix->inb_spi_mask = max_sa - 1;
+   nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
   ROC_NIX_INL_SA_BASE_ALIGN);
if (!nix->inb_sa_base) {
plt_err("Failed to allocate memory for Inbound SA");
return -ENOMEM;
}
if (roc_model_is_cn10k()) {
-   for (i = 0; i < ipsec_in_max_spi; i++) {
+   for (i = 0; i < max_sa; i++) {
sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
roc_nix_inl_inb_sa_init(sa);
}
@@ -50,7 +55,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
memset(&cfg, 0, sizeof(cfg));
cfg.sa_size = inb_sa_sz;
cfg.iova = (uintptr_t)nix->inb_sa_base;
-   cfg.max_sa = ipsec_in_max_spi + 1;
+   cfg.max_sa = max_sa;
cfg.tt = SSO_TT_ORDERED;
 
/* Setup device specific inb SA table */
@@ -129,26 +134,34 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool 
inb_inl_dev)
 }
 
 uint32_t
-roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
+roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,
+ uint32_t *min_spi, uint32_t *max_spi)
 {
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
struct idev_cfg *idev = idev_get_cfg();
+   uint32_t min = 0, max = 0, mask = 0;
struct nix_inl_dev *inl_dev;
 
-   if (idev == NULL)
-   return 0;
-
-   if (!nix->inl_inb_ena)
-   return 0;
+   if (idev == NULL || !nix->inl_inb_ena)
+   goto exit;
 
inl_dev = idev->nix_inl_dev;
-   if (inb_inl_dev) {
-   if (inl_dev)
-   return inl_dev->ipsec_in_max_spi;
-   return 0;
+   if (inb_inl_dev && inl_dev) {
+   min = inl_dev->ipsec_in_min_spi;
+   max = inl_dev->ipsec_in_max_spi;
+   mask = inl_dev->inb_spi_mask;
+   } else if (!inb_inl_dev) {
+   min = roc_nix->ipsec_in_min_spi;
+   max = roc_nix->ipsec_in_max_spi;
+   mask = nix->inb_spi_mask;
}
 
-   return roc_nix->ipsec_in_max_spi;
+exit:
+   if (min_spi)
+   *min_spi = min;
+   if (max_spi)
+   *max_spi = max;
+   return mask;
 }
 
 uint32_t
@@ -175,8 +188,8 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool 
inl_dev_sa)
 uintptr_t
 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 {
+   uint32_t max_spi, min_spi, mask;
uintptr_t sa_bas

[PATCH 5/5] net/cnxk: add option to override outbound inline sa iv

[Akhil Goyal]

From: Nithin Dabilpuram 

Add option to override outbound inline sa iv for debug
purposes via environment variable. User can set env variable as:
export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..."

Signed-off-by: Nithin Dabilpuram 
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 35 +
 1 file changed, 35 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c 
b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 854498ef46..04ae300497 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -225,6 +225,36 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
rte_pktmbuf_free(mbuf);
 }
 
+static void
+outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str)
+{
+   uint8_t *iv_dbg = outb_sa->iv.iv_dbg;
+   char *iv_str = strdup(__iv_str);
+   char *iv_b = NULL, len = 16;
+   char *save;
+   int i;
+
+   if (!iv_str)
+   return;
+
+   if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM ||
+   outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC)
+   len = 8;
+
+   memset(iv_dbg, len, sizeof(outb_sa->iv.iv_dbg));
+
+   for (i = 0; i < len; i++) {
+   iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
+   if (!iv_b)
+   break;
+   iv_dbg[i] = strtoul(iv_b, NULL, 0);
+   }
+
+   /* Update source of IV */
+   outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA;
+   free(iv_str);
+}
+
 static int
 cn10k_eth_sec_session_create(void *device,
 struct rte_security_session_conf *conf,
@@ -359,6 +389,7 @@ cn10k_eth_sec_session_create(void *device,
struct cn10k_outb_priv_data *outb_priv;
struct cnxk_ipsec_outb_rlens *rlens;
uint64_t sa_base = dev->outb.sa_base;
+   const char *iv_str;
uint32_t sa_idx;
 
PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) <
@@ -384,6 +415,10 @@ cn10k_eth_sec_session_create(void *device,
goto mempool_put;
}
 
+   iv_str = getenv("CN10K_ETH_SEC_IV_OVR");
+   if (iv_str)
+   outb_dbg_iv_update(outb_sa_dptr, iv_str);
+
/* Save userdata */
outb_priv->userdata = conf->userdata;
outb_priv->sa_idx = sa_idx;
-- 
2.25.1

[PATCH] buildtools: fix avx512 check for Python 3.5

[Lance Richardson]

Python 3.5 subprocess.run() does not have a capture_output
parameter (it is present only in 3.7 and up). Capture output
by using subprocess.PIPE for stdout instead.

Fixes: bb9cd91095b3 ("buildtools: make AVX512 check portable")
Cc: sta...@dpdk.org
Signed-off-by: Lance Richardson 
---
 buildtools/binutils-avx512-check.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/buildtools/binutils-avx512-check.py 
b/buildtools/binutils-avx512-check.py
index a4e14f3593..9d7d360d95 100644
--- a/buildtools/binutils-avx512-check.py
+++ b/buildtools/binutils-avx512-check.py
@@ -15,7 +15,7 @@
 src = '__asm__("vpgatherqq {}");'.format(gather_params).encode('utf-8')
 subprocess.run(cc + ['-c', '-xc', '-o', obj.name, '-'], input=src, 
check=True)
 asm = subprocess.run([objdump, '-d', '--no-show-raw-insn', obj.name],
- capture_output=True, 
check=True).stdout.decode('utf-8')
+ stdout=subprocess.PIPE, 
check=True).stdout.decode('utf-8')
 if gather_params not in asm:
print('vpgatherqq displacement error with as')
sys.exit(1)
-- 
2.25.1



smime.p7s
Description: S/MIME Cryptographic Signature

[PATCH v1 0/3] GPU memory aligned

[eagostini]

From: Elena Agostini 

Applications may need to allocate GPU memory buffers
with memory address aligned to some value
(e.g. page size).

Similarly to the rte_malloc function, aligned size
can be provided as input to rte_gpu_mem_alloc.

This set of patches implements this functionality
in the gpudev library and the GPU CUDA driver.

Elena Agostini (3):
  gpudev: mem alloc aligned memory
  app/test-gpudev: test aligned memory allocation
  gpu/cuda: mem alloc aligned memory

 app/test-gpudev/main.c | 13 ++---
 drivers/gpu/cuda/cuda.c| 21 -
 lib/gpudev/gpudev.c| 10 --
 lib/gpudev/gpudev_driver.h |  2 +-
 lib/gpudev/rte_gpudev.h| 10 +++---
 5 files changed, 42 insertions(+), 14 deletions(-)

-- 
2.17.1

[PATCH v1 1/3] gpudev: mem alloc aligned memory

[eagostini]

From: Elena Agostini 

Similarly to rte_malloc, rte_gpu_mem_alloc accept as
input the memory alignment size.

GPU driver should return GPU memory address aligned
with the input value.

Signed-off-by: Elena Agostini 
---
 lib/gpudev/gpudev.c| 10 --
 lib/gpudev/gpudev_driver.h |  2 +-
 lib/gpudev/rte_gpudev.h| 10 +++---
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c
index 9ae36dbae9..dc8c3baefa 100644
--- a/lib/gpudev/gpudev.c
+++ b/lib/gpudev/gpudev.c
@@ -527,7 +527,7 @@ rte_gpu_info_get(int16_t dev_id, struct rte_gpu_info *info)
 }
 
 void *
-rte_gpu_mem_alloc(int16_t dev_id, size_t size)
+rte_gpu_mem_alloc(int16_t dev_id, size_t size, unsigned int align)
 {
struct rte_gpu *dev;
void *ptr;
@@ -549,7 +549,13 @@ rte_gpu_mem_alloc(int16_t dev_id, size_t size)
if (size == 0) /* dry-run */
return NULL;
 
-   ret = dev->ops.mem_alloc(dev, size, &ptr);
+   if (align && !rte_is_power_of_2(align)) {
+   GPU_LOG(ERR, "requested alignment is not a power of two %u", 
align);
+   rte_errno = EINVAL;
+   return NULL;
+   }
+
+   ret = dev->ops.mem_alloc(dev, size, &ptr, align);
 
switch (ret) {
case 0:
diff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h
index cb7b101f2f..d06f465194 100644
--- a/lib/gpudev/gpudev_driver.h
+++ b/lib/gpudev/gpudev_driver.h
@@ -27,7 +27,7 @@ enum rte_gpu_state {
 struct rte_gpu;
 typedef int (rte_gpu_close_t)(struct rte_gpu *dev);
 typedef int (rte_gpu_info_get_t)(struct rte_gpu *dev, struct rte_gpu_info 
*info);
-typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t size, void 
**ptr);
+typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t size, void 
**ptr, unsigned int align);
 typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void 
*ptr);
 typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr);
diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h
index fa3f3aad4f..9e2e2c5dce 100644
--- a/lib/gpudev/rte_gpudev.h
+++ b/lib/gpudev/rte_gpudev.h
@@ -364,18 +364,22 @@ int rte_gpu_info_get(int16_t dev_id, struct rte_gpu_info 
*info);
  * @param size
  *   Number of bytes to allocate.
  *   Requesting 0 will do nothing.
- *
+ * @param align
+ *   If 0, the return is a pointer that is suitably aligned for any kind of
+ *   variable (in the same manner as malloc()).
+ *   Otherwise, the return is a pointer that is a multiple of *align*. In
+ *   this case, it must obviously be a power of two.
  * @return
  *   A pointer to the allocated memory, otherwise NULL and rte_errno is set:
  *   - ENODEV if invalid dev_id
- *   - EINVAL if reserved flags
+ *   - EINVAL if align is not a power of two
  *   - ENOTSUP if operation not supported by the driver
  *   - E2BIG if size is higher than limit
  *   - ENOMEM if out of space
  *   - EPERM if driver error
  */
 __rte_experimental
-void *rte_gpu_mem_alloc(int16_t dev_id, size_t size)
+void *rte_gpu_mem_alloc(int16_t dev_id, size_t size, unsigned int align)
 __rte_alloc_size(2);
 
 /**
-- 
2.17.1

[PATCH v1 2/3] app/test-gpudev: test aligned memory allocation

[eagostini]

From: Elena Agostini 

Update gpudev app to test GPU memory aligned allocation.

Signed-off-by: Elena Agostini 
---
 app/test-gpudev/main.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/app/test-gpudev/main.c b/app/test-gpudev/main.c
index 5c1aa3d52f..f36f46cbca 100644
--- a/app/test-gpudev/main.c
+++ b/app/test-gpudev/main.c
@@ -69,11 +69,12 @@ alloc_gpu_memory(uint16_t gpu_id)
void *ptr_2 = NULL;
size_t buf_bytes = 1024;
int ret;
+   unsigned align = 4096;
 
printf("\n===> TEST: Allocate GPU memory\n\n");
 
-   /* Alloc memory on GPU 0 */
-   ptr_1 = rte_gpu_mem_alloc(gpu_id, buf_bytes);
+   /* Alloc memory on GPU 0 without any specific alignment */
+   ptr_1 = rte_gpu_mem_alloc(gpu_id, buf_bytes, 0);
if (ptr_1 == NULL) {
fprintf(stderr, "rte_gpu_mem_alloc GPU memory returned 
error\n");
goto error;
@@ -81,7 +82,8 @@ alloc_gpu_memory(uint16_t gpu_id)
printf("GPU memory allocated at 0x%p size is %zd bytes\n",
ptr_1, buf_bytes);
 
-   ptr_2 = rte_gpu_mem_alloc(gpu_id, buf_bytes);
+   /* Alloc memory on GPU 0 with 4kB alignment */
+   ptr_2 = rte_gpu_mem_alloc(gpu_id, buf_bytes, align);
if (ptr_2 == NULL) {
fprintf(stderr, "rte_gpu_mem_alloc GPU memory returned 
error\n");
goto error;
@@ -89,6 +91,11 @@ alloc_gpu_memory(uint16_t gpu_id)
printf("GPU memory allocated at 0x%p size is %zd bytes\n",
ptr_2, buf_bytes);
 
+   if (((uintptr_t)ptr_2) % align) {
+   fprintf(stderr, "Memory address 0x%p is not aligned to %u\n", 
ptr_2, align);
+   goto error;
+   }
+
ret = rte_gpu_mem_free(gpu_id, (uint8_t *)(ptr_1)+0x700);
if (ret < 0) {
printf("GPU memory 0x%p NOT freed: GPU driver didn't find this 
memory address internally.\n",
-- 
2.17.1

[PATCH v1 3/3] gpu/cuda: mem alloc aligned memory

[eagostini]

From: Elena Agostini 

Implement aligned GPU memory allocation in GPU CUDA driver.

Signed-off-by: Elena Agostini 
---
 drivers/gpu/cuda/cuda.c | 21 -
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/cuda/cuda.c b/drivers/gpu/cuda/cuda.c
index 882df08e56..4ad3f5fc90 100644
--- a/drivers/gpu/cuda/cuda.c
+++ b/drivers/gpu/cuda/cuda.c
@@ -139,8 +139,10 @@ typedef uintptr_t cuda_ptr_key;
 /* Single entry of the memory list */
 struct mem_entry {
CUdeviceptr ptr_d;
+   CUdeviceptr ptr_orig_d;
void *ptr_h;
size_t size;
+   size_t size_orig;
struct rte_gpu *dev;
CUcontext ctx;
cuda_ptr_key pkey;
@@ -569,7 +571,7 @@ cuda_dev_info_get(struct rte_gpu *dev, struct rte_gpu_info 
*info)
  */
 
 static int
-cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)
+cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr, unsigned int 
align)
 {
CUresult res;
const char *err_string;
@@ -610,8 +612,10 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
**ptr)
 
/* Allocate memory */
mem_alloc_list_tail->size = size;
-   res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_d),
-   mem_alloc_list_tail->size);
+   mem_alloc_list_tail->size_orig = size + align;
+
+   res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_orig_d),
+   mem_alloc_list_tail->size_orig);
if (res != 0) {
pfn_cuGetErrorString(res, &(err_string));
rte_cuda_log(ERR, "cuCtxSetCurrent current failed with %s",
@@ -620,6 +624,13 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
**ptr)
return -rte_errno;
}
 
+
+   /* Align memory address */
+   mem_alloc_list_tail->ptr_d = mem_alloc_list_tail->ptr_orig_d;
+   if (align && ((uintptr_t)mem_alloc_list_tail->ptr_d) % align)
+   mem_alloc_list_tail->ptr_d += (align -
+   (((uintptr_t)mem_alloc_list_tail->ptr_d) % 
align));
+
/* GPUDirect RDMA attribute required */
res = pfn_cuPointerSetAttribute(&flag,
CU_POINTER_ATTRIBUTE_SYNC_MEMOPS,
@@ -634,7 +645,6 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)
 
mem_alloc_list_tail->pkey = get_hash_from_ptr((void 
*)mem_alloc_list_tail->ptr_d);
mem_alloc_list_tail->ptr_h = NULL;
-   mem_alloc_list_tail->size = size;
mem_alloc_list_tail->dev = dev;
mem_alloc_list_tail->ctx = 
(CUcontext)((uintptr_t)dev->mpshared->info.context);
mem_alloc_list_tail->mtype = GPU_MEM;
@@ -761,6 +771,7 @@ cuda_mem_register(struct rte_gpu *dev, size_t size, void 
*ptr)
mem_alloc_list_tail->dev = dev;
mem_alloc_list_tail->ctx = 
(CUcontext)((uintptr_t)dev->mpshared->info.context);
mem_alloc_list_tail->mtype = CPU_REGISTERED;
+   mem_alloc_list_tail->ptr_orig_d = mem_alloc_list_tail->ptr_d;
 
/* Restore original ctx as current ctx */
res = pfn_cuCtxSetCurrent(current_ctx);
@@ -796,7 +807,7 @@ cuda_mem_free(struct rte_gpu *dev, void *ptr)
}
 
if (mem_item->mtype == GPU_MEM) {
-   res = pfn_cuMemFree(mem_item->ptr_d);
+   res = pfn_cuMemFree(mem_item->ptr_orig_d);
if (res != 0) {
pfn_cuGetErrorString(res, &(err_string));
rte_cuda_log(ERR, "cuMemFree current failed with %s",
-- 
2.17.1

Re: [PATCH] buildtools: fix avx512 check for Python 3.5

[Dmitry Kozlyuk]

2022-01-03 12:09 (UTC-0500), Lance Richardson:
> Python 3.5 subprocess.run() does not have a capture_output
> parameter (it is present only in 3.7 and up). Capture output
> by using subprocess.PIPE for stdout instead.
> 
> Fixes: bb9cd91095b3 ("buildtools: make AVX512 check portable")
> Cc: sta...@dpdk.org
> Signed-off-by: Lance Richardson 

Acked-by: Dmitry Kozlyuk 

Re: [PATCH v1 3/3] gpu/cuda: mem alloc aligned memory

[Stephen Hemminger]

On Tue, 4 Jan 2022 01:47:21 +
 wrote:

>  static int
> -cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)
> +cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr, unsigned int 
> align)
>  {
>   CUresult res;
>   const char *err_string;
> @@ -610,8 +612,10 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
> **ptr)
>  
>   /* Allocate memory */
>   mem_alloc_list_tail->size = size;
> - res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_d),
> - mem_alloc_list_tail->size);
> + mem_alloc_list_tail->size_orig = size + align;
> +
> + res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_orig_d),
> + mem_alloc_list_tail->size_orig);
>   if (res != 0) {
>   pfn_cuGetErrorString(res, &(err_string));
>   rte_cuda_log(ERR, "cuCtxSetCurrent current failed with %s",
> @@ -620,6 +624,13 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
> **ptr)
>   return -rte_errno;
>   }
>  
> +
> + /* Align memory address */
> + mem_alloc_list_tail->ptr_d = mem_alloc_list_tail->ptr_orig_d;
> + if (align && ((uintptr_t)mem_alloc_list_tail->ptr_d) % align)
> + mem_alloc_list_tail->ptr_d += (align -
> + (((uintptr_t)mem_alloc_list_tail->ptr_d) % 
> align));


Posix memalign takes size_t for both size and alignment.

Better to put the input parameters first, and then the resulting output 
parameter last
for consistency; follows the Rusty API design manifesto.

Alignment only makes sense if power of two. The code should check that and 
optimize
for that.

Re: [PATCH v1 3/3] gpu/cuda: mem alloc aligned memory

[Elena Agostini]

> From: Stephen Hemminger 
> Date: Monday, 3 January 2022 at 19:05
> To: Elena Agostini 
> Cc: dev@dpdk.org 
> Subject: Re: [PATCH v1 3/3] gpu/cuda: mem alloc aligned memory
> External email: Use caution opening links or attachments>
>

> On Tue, 4 Jan 2022 01:47:21 +
>  wrote:>

> >  static int
> > -cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)
> > +cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr, unsigned int 
> > align)
> >  {
> >   CUresult res;
> >   const char *err_string;
> > @@ -610,8 +612,10 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
> > **ptr)
> >
> >   /* Allocate memory */
> >   mem_alloc_list_tail->size = size;
> > - res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_d),
> > - mem_alloc_list_tail->size);
> > + mem_alloc_list_tail->size_orig = size + align;
> > +
> > + res = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_orig_d),
> > + mem_alloc_list_tail->size_orig);
> >   if (res != 0) {
> >   pfn_cuGetErrorString(res, &(err_string));
> >   rte_cuda_log(ERR, "cuCtxSetCurrent current failed with %s",
> > @@ -620,6 +624,13 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void 
> > **ptr)
> >   return -rte_errno;
> >   }
> >
> > +
> > + /* Align memory address */
> > + mem_alloc_list_tail->ptr_d = mem_alloc_list_tail->ptr_orig_d;
> > + if (align && ((uintptr_t)mem_alloc_list_tail->ptr_d) % align)
> > + mem_alloc_list_tail->ptr_d += (align -
> > + (((uintptr_t)mem_alloc_list_tail->ptr_d) % 
> > align));>
>

> Posix memalign takes size_t for both size and alignment.

I've created this patch based on the rte_malloc function definition for 
consistency.

void * rte_malloc(const char *type, size_t size, unsigned align)


> Better to put the input parameters first, and then the resulting output 
> parameter last
> for consistency; follows the Rusty API design manifesto.

Got it, will do.

> Alignment only makes sense if power of two. The code should check that and 
> optimize
> for that.
>

The alignment value is checked in the gpudev library before
passing it to the driver.

Adding this kind of checks in the driver has been rejected in the past because 
it was
considered dead code (the library was already checking input parameters).

Let me know what are the preferred options.

Re: [PATCH v1 3/3] gpu/cuda: mem alloc aligned memory

[Stephen Hemminger]

On Mon, 3 Jan 2022 18:15:11 +
Elena Agostini  wrote:

> > Alignment only makes sense if power of two. The code should check that and 
> > optimize
> > for that.
> >  
> 
> The alignment value is checked in the gpudev library before
> passing it to the driver.
> 
> Adding this kind of checks in the driver has been rejected in the past 
> because it was
> considered dead code (the library was already checking input parameters).
> 
> Let me know what are the preferred options.

Driver could use the mask instead of slow divide operation.

[Bug 919] Error attaching device to DPDK

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=919

Bug ID: 919
   Summary: Error attaching device to DPDK
   Product: DPDK
   Version: 19.11
  Hardware: x86
OS: Linux
Status: UNCONFIRMED
  Severity: normal
  Priority: Normal
 Component: ethdev
  Assignee: dev@dpdk.org
  Reporter: jmo...@me.com
  Target Milestone: ---

Error attaching device to DPDK while adding interfaces to OVS bond on Ubuntu.

Ubuntu 20.04.3
DPDK 19.11.10
OVS 2.13.3
NICs Intel x710 (fw 7.10)

Command:

ovs-vsctl add-bond ovsbr0 bond0  ens2f0 ens2f1 ens3f0 ens3f1 \
   -- set Interface ens2f0 type=dpdk  "options:dpdk-devargs=:5e:00.0" \
   -- set Interface ens2f1 type=dpdk  "options:dpdk-devargs=:5e:00.1" \
   -- set Interface ens3f0 type=dpdk  "options:dpdk-devargs=:d8:00.0" \
   -- set Interface ens3f1 type=dpdk  "options:dpdk-devargs=:d8:00.1"

Output:

ovs-vsctl: Error detected while setting up 'ens2f0': Error attaching device
':5e:00.0' to DPDK.  See ovs-vswitchd log for details.
ovs-vsctl: Error detected while setting up 'ens2f1': Error attaching device
':5e:00.1' to DPDK.  See ovs-vswitchd log for details.
ovs-vsctl: Error detected while setting up 'ens3f0': Error attaching device
':d8:00.0' to DPDK.  See ovs-vswitchd log for details.
ovs-vsctl: Error detected while setting up 'ens3f1': Error attaching device
':d8:00.1' to DPDK.  See ovs-vswitchd log for details.
ovs-vsctl: The default log directory is "/var/log/openvswitch".

/var/log/openvswitch/ovs-vswitchd.log

2022-01-03T16:00:05.776Z|00083|dpdk|ERR|EAL: Driver cannot attach the device
(:d8:00.1)
2022-01-03T16:00:05.776Z|00084|dpdk|ERR|EAL: Failed to attach device on primary
process
2022-01-03T16:00:05.776Z|00085|netdev_dpdk|WARN|Error attaching device
':d8:00.1' to DPDK
2022-01-03T16:00:05.776Z|00086|netdev|WARN|ens3f1: could not set configuration
(Invalid argument)
2022-01-03T16:00:05.776Z|00087|dpdk|ERR|Invalid port_id=32

VT-d support is enabled:

cat /proc/cmdline 
BOOT_IMAGE=/boot/vmlinuz-5.4.0-91-generic
root=UUID=2849776f-b167-447f-a5d1-ea4b5c831c35 ro iommu=pt intel_iommu=on

-- 
You are receiving this mail because:
You are the assignee for the bug.

Re: [PATCH v1 3/3] gpu/cuda: mem alloc aligned memory

[Elena Agostini]

> On Mon, 3 Jan 2022 18:15:11 +
> Elena Agostini  wrote:
>
> > > Alignment only makes sense if power of two. The code should check that 
> > > and optimize
> > > for that.
> > >
> >
> > The alignment value is checked in the gpudev library before
> > passing it to the driver.
> >
> > Adding this kind of checks in the driver has been rejected in the past 
> > because it was
> > considered dead code (the library was already checking input parameters).
> >
> > Let me know what are the preferred options.
>
> Driver could use the mask instead of slow divide operation.

I'd not be concerned about performance here.
Memory allocation is expensive, typically you want to do it
at initialization time.

What do you suggest for my other comments?

[PATCH v1] gpudev: pin GPU memory

[eagostini]

From: Elena Agostini 

Enable the possibility to make a GPU memory area accessible from
the CPU.

GPU memory has to be allocated via rte_gpu_mem_alloc().

This patch allows the gpudev library to pin, through the GPU driver,
a chunk of GPU memory and to return a memory pointer usable
by the CPU to access the GPU memory area.

Signed-off-by: Elena Agostini 
---
 lib/gpudev/gpudev.c| 47 +++
 lib/gpudev/gpudev_driver.h |  6 +
 lib/gpudev/rte_gpudev.h| 50 ++
 lib/gpudev/version.map |  2 ++
 4 files changed, 105 insertions(+)

diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c
index 9ae36dbae9..ca627e44b3 100644
--- a/lib/gpudev/gpudev.c
+++ b/lib/gpudev/gpudev.c
@@ -634,6 +634,53 @@ rte_gpu_mem_unregister(int16_t dev_id, void *ptr)
return GPU_DRV_RET(dev->ops.mem_unregister(dev, ptr));
 }
 
+int
+rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "pin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_pin == NULL) {
+   GPU_LOG(ERR, "mem pinning not supported");
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL || size == 0) /* dry-run  */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_pin(dev, size, ptr));
+}
+
+int
+rte_gpu_mem_unpin(int16_t dev_id, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "unpin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_unpin == NULL) {
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL) /* dry-run */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_unpin(dev, ptr));
+}
+
 int
 rte_gpu_wmb(int16_t dev_id)
 {
diff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h
index cb7b101f2f..a616941926 100644
--- a/lib/gpudev/gpudev_driver.h
+++ b/lib/gpudev/gpudev_driver.h
@@ -31,6 +31,8 @@ typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t 
size, void **ptr);
 typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void 
*ptr);
 typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr);
+typedef int (rte_gpu_mem_pin_t)(struct rte_gpu *dev, size_t size, void *ptr);
+typedef int (rte_gpu_mem_unpin_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_wmb_t)(struct rte_gpu *dev);
 
 struct rte_gpu_ops {
@@ -46,6 +48,10 @@ struct rte_gpu_ops {
rte_gpu_mem_register_t *mem_register;
/* Unregister CPU memory from device. */
rte_gpu_mem_unregister_t *mem_unregister;
+/* Pin GPU memory. */
+rte_gpu_mem_pin_t *mem_pin;
+/* Unpin GPU memory. */
+rte_gpu_mem_unpin_t *mem_unpin;
/* Enforce GPU write memory barrier. */
rte_gpu_wmb_t *wmb;
 };
diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h
index fa3f3aad4f..0a9033c6e0 100644
--- a/lib/gpudev/rte_gpudev.h
+++ b/lib/gpudev/rte_gpudev.h
@@ -447,6 +447,56 @@ int rte_gpu_mem_register(int16_t dev_id, size_t size, void 
*ptr);
 __rte_experimental
 int rte_gpu_mem_unregister(int16_t dev_id, void *ptr);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Pin a chunk of GPU memory to make it accessible from the CPU
+ * using the memory pointer returned by the function.
+ * GPU memory has to be allocated via rte_gpu_mem_alloc().
+ *
+ * @param dev_id
+ *   Device ID requiring pinned memory.
+ * @param size
+ *   Number of bytes to pin.
+ *   Requesting 0 will do nothing.
+ * @param ptr
+ *   Pointer to the GPU memory area to be pinned.
+ *   NULL is a no-op accepted value.
+
+ * @return
+ *   A pointer to the pinned GPU memory usable by the CPU, otherwise NULL and 
rte_errno is set:
+ *   - ENODEV if invalid dev_id
+ *   - EINVAL if reserved flags
+ *   - ENOTSUP if operation not supported by the driver
+ *   - E2BIG if size is higher than limit
+ *   - ENOMEM if out of space
+ *   - EPERM if driver error
+ */
+__rte_experimental
+int rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr);
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Unpin a chunk of GPU memory previously pinned with rte_gpu_mem_pin()
+ *
+ * @param dev_id
+ *   Reference device ID.
+ * @param ptr
+ *   Pointer to the memory area to be unpinned.
+ *   NULL is a no-op accepted value.
+ *
+ * @return
+ *   0 on success, -rte_errno otherwise:
+ *   - ENODEV if invalid dev_id
+ *   - ENOTSUP if operation not supported by the driver
+ * 

[PATCH v2] gpudev: pin GPU memory

[eagostini]

From: Elena Agostini 

Enable the possibility to make a GPU memory area accessible from
the CPU.

GPU memory has to be allocated via rte_gpu_mem_alloc().

This patch allows the gpudev library to pin, through the GPU driver,
a chunk of GPU memory and to return a memory pointer usable
by the CPU to access the GPU memory area.

Signed-off-by: Elena Agostini 
---
 lib/gpudev/gpudev.c| 47 +++
 lib/gpudev/gpudev_driver.h |  6 +
 lib/gpudev/rte_gpudev.h| 50 ++
 lib/gpudev/version.map |  2 ++
 4 files changed, 105 insertions(+)

diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c
index 9ae36dbae9..ca627e44b3 100644
--- a/lib/gpudev/gpudev.c
+++ b/lib/gpudev/gpudev.c
@@ -634,6 +634,53 @@ rte_gpu_mem_unregister(int16_t dev_id, void *ptr)
return GPU_DRV_RET(dev->ops.mem_unregister(dev, ptr));
 }
 
+int
+rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "pin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_pin == NULL) {
+   GPU_LOG(ERR, "mem pinning not supported");
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL || size == 0) /* dry-run  */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_pin(dev, size, ptr));
+}
+
+int
+rte_gpu_mem_unpin(int16_t dev_id, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "unpin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_unpin == NULL) {
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL) /* dry-run */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_unpin(dev, ptr));
+}
+
 int
 rte_gpu_wmb(int16_t dev_id)
 {
diff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h
index cb7b101f2f..13dd8dac43 100644
--- a/lib/gpudev/gpudev_driver.h
+++ b/lib/gpudev/gpudev_driver.h
@@ -31,6 +31,8 @@ typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t 
size, void **ptr);
 typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void 
*ptr);
 typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr);
+typedef int (rte_gpu_mem_pin_t)(struct rte_gpu *dev, size_t size, void *ptr);
+typedef int (rte_gpu_mem_unpin_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_wmb_t)(struct rte_gpu *dev);
 
 struct rte_gpu_ops {
@@ -46,6 +48,10 @@ struct rte_gpu_ops {
rte_gpu_mem_register_t *mem_register;
/* Unregister CPU memory from device. */
rte_gpu_mem_unregister_t *mem_unregister;
+   /* Pin GPU memory. */
+   rte_gpu_mem_pin_t *mem_pin;
+   /* Unpin GPU memory. */
+   rte_gpu_mem_unpin_t *mem_unpin;
/* Enforce GPU write memory barrier. */
rte_gpu_wmb_t *wmb;
 };
diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h
index fa3f3aad4f..0a9033c6e0 100644
--- a/lib/gpudev/rte_gpudev.h
+++ b/lib/gpudev/rte_gpudev.h
@@ -447,6 +447,56 @@ int rte_gpu_mem_register(int16_t dev_id, size_t size, void 
*ptr);
 __rte_experimental
 int rte_gpu_mem_unregister(int16_t dev_id, void *ptr);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Pin a chunk of GPU memory to make it accessible from the CPU
+ * using the memory pointer returned by the function.
+ * GPU memory has to be allocated via rte_gpu_mem_alloc().
+ *
+ * @param dev_id
+ *   Device ID requiring pinned memory.
+ * @param size
+ *   Number of bytes to pin.
+ *   Requesting 0 will do nothing.
+ * @param ptr
+ *   Pointer to the GPU memory area to be pinned.
+ *   NULL is a no-op accepted value.
+
+ * @return
+ *   A pointer to the pinned GPU memory usable by the CPU, otherwise NULL and 
rte_errno is set:
+ *   - ENODEV if invalid dev_id
+ *   - EINVAL if reserved flags
+ *   - ENOTSUP if operation not supported by the driver
+ *   - E2BIG if size is higher than limit
+ *   - ENOMEM if out of space
+ *   - EPERM if driver error
+ */
+__rte_experimental
+int rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr);
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Unpin a chunk of GPU memory previously pinned with rte_gpu_mem_pin()
+ *
+ * @param dev_id
+ *   Reference device ID.
+ * @param ptr
+ *   Pointer to the memory area to be unpinned.
+ *   NULL is a no-op accepted value.
+ *
+ * @return
+ *   0 on success, -rte_errno otherwise:
+ *   - ENODEV if invalid dev_id
+ *   - ENOTSUP if operation not supported by the driver
+ *   - 

[PATCH v2] gpudev: pin GPU memory

[eagostini]

From: Elena Agostini 

Enable the possibility to make a GPU memory area accessible from
the CPU.

GPU memory has to be allocated via rte_gpu_mem_alloc().

This patch allows the gpudev library to pin, through the GPU driver,
a chunk of GPU memory and to return a memory pointer usable
by the CPU to access the GPU memory area.

Signed-off-by: Elena Agostini 
---
 lib/gpudev/gpudev.c| 47 +++
 lib/gpudev/gpudev_driver.h |  6 +
 lib/gpudev/rte_gpudev.h| 50 ++
 lib/gpudev/version.map |  2 ++
 4 files changed, 105 insertions(+)

diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c
index 9ae36dbae9..ca627e44b3 100644
--- a/lib/gpudev/gpudev.c
+++ b/lib/gpudev/gpudev.c
@@ -634,6 +634,53 @@ rte_gpu_mem_unregister(int16_t dev_id, void *ptr)
return GPU_DRV_RET(dev->ops.mem_unregister(dev, ptr));
 }
 
+int
+rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "pin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_pin == NULL) {
+   GPU_LOG(ERR, "mem pinning not supported");
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL || size == 0) /* dry-run  */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_pin(dev, size, ptr));
+}
+
+int
+rte_gpu_mem_unpin(int16_t dev_id, void *ptr)
+{
+   struct rte_gpu *dev;
+
+   dev = gpu_get_by_id(dev_id);
+   if (dev == NULL) {
+   GPU_LOG(ERR, "unpin mem for invalid device ID %d", dev_id);
+   rte_errno = ENODEV;
+   return -rte_errno;
+   }
+
+   if (dev->ops.mem_unpin == NULL) {
+   rte_errno = ENOTSUP;
+   return -rte_errno;
+   }
+
+   if (ptr == NULL) /* dry-run */
+   return 0;
+
+   return GPU_DRV_RET(dev->ops.mem_unpin(dev, ptr));
+}
+
 int
 rte_gpu_wmb(int16_t dev_id)
 {
diff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h
index cb7b101f2f..13dd8dac43 100644
--- a/lib/gpudev/gpudev_driver.h
+++ b/lib/gpudev/gpudev_driver.h
@@ -31,6 +31,8 @@ typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t 
size, void **ptr);
 typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void 
*ptr);
 typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr);
+typedef int (rte_gpu_mem_pin_t)(struct rte_gpu *dev, size_t size, void *ptr);
+typedef int (rte_gpu_mem_unpin_t)(struct rte_gpu *dev, void *ptr);
 typedef int (rte_gpu_wmb_t)(struct rte_gpu *dev);
 
 struct rte_gpu_ops {
@@ -46,6 +48,10 @@ struct rte_gpu_ops {
rte_gpu_mem_register_t *mem_register;
/* Unregister CPU memory from device. */
rte_gpu_mem_unregister_t *mem_unregister;
+   /* Pin GPU memory. */
+   rte_gpu_mem_pin_t *mem_pin;
+   /* Unpin GPU memory. */
+   rte_gpu_mem_unpin_t *mem_unpin;
/* Enforce GPU write memory barrier. */
rte_gpu_wmb_t *wmb;
 };
diff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h
index fa3f3aad4f..0a9033c6e0 100644
--- a/lib/gpudev/rte_gpudev.h
+++ b/lib/gpudev/rte_gpudev.h
@@ -447,6 +447,56 @@ int rte_gpu_mem_register(int16_t dev_id, size_t size, void 
*ptr);
 __rte_experimental
 int rte_gpu_mem_unregister(int16_t dev_id, void *ptr);
 
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Pin a chunk of GPU memory to make it accessible from the CPU
+ * using the memory pointer returned by the function.
+ * GPU memory has to be allocated via rte_gpu_mem_alloc().
+ *
+ * @param dev_id
+ *   Device ID requiring pinned memory.
+ * @param size
+ *   Number of bytes to pin.
+ *   Requesting 0 will do nothing.
+ * @param ptr
+ *   Pointer to the GPU memory area to be pinned.
+ *   NULL is a no-op accepted value.
+
+ * @return
+ *   A pointer to the pinned GPU memory usable by the CPU, otherwise NULL and 
rte_errno is set:
+ *   - ENODEV if invalid dev_id
+ *   - EINVAL if reserved flags
+ *   - ENOTSUP if operation not supported by the driver
+ *   - E2BIG if size is higher than limit
+ *   - ENOMEM if out of space
+ *   - EPERM if driver error
+ */
+__rte_experimental
+int rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr);
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Unpin a chunk of GPU memory previously pinned with rte_gpu_mem_pin()
+ *
+ * @param dev_id
+ *   Reference device ID.
+ * @param ptr
+ *   Pointer to the memory area to be unpinned.
+ *   NULL is a no-op accepted value.
+ *
+ * @return
+ *   0 on success, -rte_errno otherwise:
+ *   - ENODEV if invalid dev_id
+ *   - ENOTSUP if operation not supported by the driver
+ *   - 

[PATCH] net/mlx5: fix risk in Rx descriptor read in NEON vector path

[Ruifeng Wang]

In NEON vector PMD, vector load loads two contiguous 8B of
descriptor data into vector register. Given vector load ensures no
16B atomicity, read of the word that includes op_own field could be
reordered after read of other words. In this case, some words could
contain invalid data.

Reloaded qword0 after read barrier to update vector register. This
ensures that the fetched data is correct.

Testpmd single core test on N1SDP/ThunderX2 showed no performance drop.

Fixes: 1742c2d9fab0 ("net/mlx5: fix synchronization on polling Rx completions")
Cc: sta...@dpdk.org

Signed-off-by: Ruifeng Wang 
---
 drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h 
b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
index b1d16baa61..b1ec615b51 100644
--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h
@@ -647,6 +647,14 @@ rxq_cq_process_v(struct mlx5_rxq_data *rxq, volatile 
struct mlx5_cqe *cq,
c0 = vld1q_u64((uint64_t *)(p0 + 48));
/* Synchronize for loading the rest of blocks. */
rte_io_rmb();
+   /* B.0 (CQE 3) reload lower half of the block. */
+   c3 = vld1q_lane_u64((uint64_t *)(p3 + 48), c3, 0);
+   /* B.0 (CQE 2) reload lower half of the block. */
+   c2 = vld1q_lane_u64((uint64_t *)(p2 + 48), c2, 0);
+   /* B.0 (CQE 1) reload lower half of the block. */
+   c1 = vld1q_lane_u64((uint64_t *)(p1 + 48), c1, 0);
+   /* B.0 (CQE 0) reload lower half of the block. */
+   c0 = vld1q_lane_u64((uint64_t *)(p0 + 48), c0, 0);
/* Prefetch next 4 CQEs. */
if (pkts_n - pos >= 2 * MLX5_VPMD_DESCS_PER_LOOP) {
unsigned int next = pos + MLX5_VPMD_DESCS_PER_LOOP;
-- 
2.25.1