Re: [dpdk-dev] [PATCH v2] net/i40e: fix set rss hash function invalid
> -Original Message-
> From: Yang, SteveX
> Sent: Friday, June 11, 2021 2:55 PM
> To: dev@dpdk.org
> Cc: Xing, Beilei ; Yang, SteveX
>
> Subject: [PATCH v2] net/i40e: fix set rss hash function invalid
>
> i40e can support following rss hash function types: default/toeplitz,
> symmetric toeplitz, and simple_xor. However, when filter engine parses
> pattern action, it only supports symmetric toeplitz & default.
>
> Add simple_xor and toeplitz hash functions support when parsing pattern
> action.
>
> Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow")
Why didn't CC stable?
>
> Signed-off-by: Steve Yang
> ---
> v2:
> - add the fix line.
> - support simple_xor and toeplitz hash functions explicitly.
>
> drivers/net/i40e/i40e_hash.c | 20 ++--
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_hash.c b/drivers/net/i40e/i40e_hash.c
> index b1cb24f437..0cef21c88f 100644
> --- a/drivers/net/i40e/i40e_hash.c
> +++ b/drivers/net/i40e/i40e_hash.c
> @@ -1105,13 +1105,21 @@ i40e_hash_parse_pattern_act(const struct
> rte_eth_dev *dev,
> NULL,
> "RSS Queues not supported when
> pattern specified");
>
> - if (rss_act->func ==
> RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
> + switch (rss_act->func) {
> + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ:
> rss_conf->symmetric_enable = true;
> - else if (rss_act->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
> - return rte_flow_error_set(error, -EINVAL,
> -
> RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> - NULL,
> - "Only symmetric TOEPLITZ
> supported when pattern specified");
> + break;
> + case RTE_ETH_HASH_FUNCTION_DEFAULT:
> + case RTE_ETH_HASH_FUNCTION_TOEPLITZ:
> + case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR:
> + break;
> + default:
> + return rte_flow_error_set(error, EINVAL,
> + RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> + NULL,
> + "RSS hash function not supported "
> + "when pattern specified");
> + }
>
> if (!i40e_hash_validate_rss_types(rss_act->types))
> return rte_flow_error_set(error, EINVAL,
> --
> 2.27.0
[dpdk-dev] [PATCH v2] net/i40e: fix data path corrupt on secondary process
From: Dapeng Yu
The rte_eth_devices array is not in share memory, it should not be
referenced by i40e_adapter which is shared by primary and secondary.
Any process set i40e_adapter->eth_dev will corrupt another process's
context.
The patch removed the field "eth_dev" from i40e_adapter.
Now, when the data paths try to access the rte_eth_dev_data instance,
they should replace adapter->eth_dev->data with adapter->pf.dev_data.
Fixes: 4861cde46116 ("i40e: new poll mode driver")
Cc: sta...@dpdk.org
Signed-off-by: Dapeng Yu
---
V2:
* Just list commit id which introduced the bug, because other following
up commits are not guilty and shall not be listed here
* fix typos in commit message of V1
---
drivers/net/i40e/i40e_ethdev.c | 44 +-
drivers/net/i40e/i40e_ethdev.h | 7 ++--
drivers/net/i40e/i40e_fdir.c | 4 +--
drivers/net/i40e/i40e_flow.c | 2 +-
drivers/net/i40e/i40e_hash.c | 7 ++--
drivers/net/i40e/i40e_rxtx.c | 4 +--
drivers/net/i40e/i40e_vf_representor.c | 37 --
7 files changed, 55 insertions(+), 50 deletions(-)
diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index dd61258739..ebaf20486f 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -732,10 +732,11 @@ i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t
reg_addr,
uint32_t reg_val)
{
uint32_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
i40e_write_rx_ctl(hw, reg_addr, reg_val);
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
@@ -1321,7 +1322,9 @@ i40e_aq_debug_write_global_register(struct i40e_hw *hw,
struct i40e_asq_cmd_details *cmd_details)
{
uint64_t ori_reg_val;
- struct rte_eth_dev *dev;
+ struct rte_eth_dev_data *dev_data =
+ ((struct i40e_adapter *)hw->back)->pf.dev_data;
+ struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
int ret;
ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
@@ -1331,7 +1334,6 @@ i40e_aq_debug_write_global_register(struct i40e_hw *hw,
reg_addr);
return -EIO;
}
- dev = ((struct i40e_adapter *)hw->back)->eth_dev;
if (ori_reg_val != reg_val)
PMD_DRV_LOG(WARNING,
@@ -1450,7 +1452,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void
*init_params __rte_unused)
dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
- pf->adapter->eth_dev = dev;
pf->dev_data = dev->data;
hw->back = I40E_PF_TO_ADAPTER(pf);
@@ -1977,7 +1978,7 @@ i40e_dev_configure(struct rte_eth_dev *dev)
void
i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@ -2093,7 +2094,7 @@ __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t
msix_vect,
int
i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@ -2169,7 +2170,7 @@ i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t
itr_idx)
void
i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@ -2196,7 +2197,7 @@ i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
void
i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
{
- struct rte_eth_dev *dev = vsi->adapter->eth_dev;
+ struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
@@ -6411,8 +6412,7 @@ i40e_dev_tx_init(struct i40e_pf *pf)
break;
}
if (ret == I40E_SUCCESS)
Re: [dpdk-dev] [PATCH] net/e1000: fix nic ops function was no initialized in secondary process
> -Original Message-
> From: Tengfei Zhang
> Sent: Saturday, June 19, 2021 01:27
> To: Wang, Haiyue
> Cc: dev@dpdk.org; Tengfei Zhang
> Subject: [PATCH] net/e1000: fix nic ops function was no initialized in
> secondary process
>
> 'e1000_setup_init_funcs' was not called in secondary process,
> it initialize mac,phy,nvm ops.
> when secondary process get link status,it will coredump.
Thanks, Tengfei.
Since primary / secondary is so complicated, AFAIK, the control path is in
primary, the secondary is mainly for rx/tx ops officially, like new Intel
ice PMD:
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
ice_set_rx_function(dev);
ice_set_tx_function(dev);
return 0;
}
So you can keep your patch as private for special secondary usage. ;-)
>
> Signed-off-by: Tengfei Zhang
> ---
> drivers/net/e1000/em_ethdev.c | 1 +
> drivers/net/e1000/igb_ethdev.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
> index a0ca371b02..cd5faa4228 100644
> --- a/drivers/net/e1000/em_ethdev.c
> +++ b/drivers/net/e1000/em_ethdev.c
> @@ -258,6 +258,7 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev)
>* has already done this work. Only check we don't need a different
>* RX function */
> if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
> if (eth_dev->data->scattered_rx)
> eth_dev->rx_pkt_burst =
> (eth_rx_burst_t)ð_em_recv_scattered_pkts;
> diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
> index 10ee0f3341..7d9d60497d 100644
> --- a/drivers/net/e1000/igb_ethdev.c
> +++ b/drivers/net/e1000/igb_ethdev.c
> @@ -737,6 +737,7 @@ eth_igb_dev_init(struct rte_eth_dev *eth_dev)
>* has already done this work. Only check we don't need a different
>* RX function */
> if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
> if (eth_dev->data->scattered_rx)
> eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
> return 0;
> @@ -931,6 +932,7 @@ eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
>* has already done this work. Only check we don't need a different
>* RX function */
> if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
> if (eth_dev->data->scattered_rx)
> eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
> return 0;
> --
> 2.26.2
[dpdk-dev] [RFC PATCH v3 0/3] Add PIE support for HQoS library
DPDK sched library is equipped with mechanism that secures it from the bufferbloat problem which is a situation when excess buffers in the network cause high latency and latency variation. Currently, it supports RED for active queue management (which is designed to control the queue length but it does not control latency directly and is now being obsoleted). However, more advanced queue management is required to address this problem and provide desirable quality of service to users. This solution (RFC) proposes usage of new algorithm called "PIE" (Proportional Integral controller Enhanced) that can effectively and directly control queuing latency to address the bufferbloat problem. The implementation of mentioned functionality includes modification of existing and adding a new set of data structures to the library, adding PIE related APIs. This affects structures in public API/ABI. That is why deprecation notice is going to be prepared and sent. Liguzinski, WojciechX (3): sched: add PIE based congestion management example/qos_sched: add PIE support example/ip_pipeline: add PIE support config/rte_config.h | 1 - drivers/net/softnic/rte_eth_softnic_tm.c | 6 +- examples/ip_pipeline/tmgr.c | 6 +- examples/qos_sched/app_thread.c | 1 - examples/qos_sched/cfg_file.c| 82 - examples/qos_sched/init.c| 7 +- examples/qos_sched/profile.cfg | 196 lib/sched/meson.build| 10 +- lib/sched/rte_pie.c | 78 + lib/sched/rte_pie.h | 388 +++ lib/sched/rte_sched.c| 229 + lib/sched/rte_sched.h| 53 +++- 12 files changed, 876 insertions(+), 181 deletions(-) create mode 100644 lib/sched/rte_pie.c create mode 100644 lib/sched/rte_pie.h -- 2.17.1
[dpdk-dev] [RFC PATCH v3 2/3] example/qos_sched: add PIE support
patch add support enable PIE or RED by
parsing config file.
Signed-off-by: Liguzinski, WojciechX
---
config/rte_config.h | 1 -
examples/qos_sched/app_thread.c | 1 -
examples/qos_sched/cfg_file.c | 82 ++---
examples/qos_sched/init.c | 7 +-
examples/qos_sched/profile.cfg | 196 +---
5 files changed, 200 insertions(+), 87 deletions(-)
diff --git a/config/rte_config.h b/config/rte_config.h
index 590903c07d..48132f27df 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -89,7 +89,6 @@
#define RTE_MAX_LCORE_FREQS 64
/* rte_sched defines */
-#undef RTE_SCHED_RED
#undef RTE_SCHED_COLLECT_STATS
#undef RTE_SCHED_SUBPORT_TC_OV
#define RTE_SCHED_PORT_N_GRINDERS 8
diff --git a/examples/qos_sched/app_thread.c b/examples/qos_sched/app_thread.c
index dbc878b553..895c0d3592 100644
--- a/examples/qos_sched/app_thread.c
+++ b/examples/qos_sched/app_thread.c
@@ -205,7 +205,6 @@ app_worker_thread(struct thread_conf **confs)
if (likely(nb_pkt)) {
int nb_sent = rte_sched_port_enqueue(conf->sched_port,
mbufs,
nb_pkt);
-
APP_STATS_ADD(conf->stat.nb_drop, nb_pkt - nb_sent);
APP_STATS_ADD(conf->stat.nb_rx, nb_pkt);
}
diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c
index cd167bd8e6..657763ca90 100644
--- a/examples/qos_sched/cfg_file.c
+++ b/examples/qos_sched/cfg_file.c
@@ -242,20 +242,20 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
rte_sched_subport_params *subpo
memset(active_queues, 0, sizeof(active_queues));
n_active_queues = 0;
-#ifdef RTE_SCHED_RED
- char sec_name[CFG_NAME_LEN];
- struct rte_red_params
red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
+#ifdef RTE_SCHED_AQM
+ enum rte_sched_aqm_mode aqm_mode;
- snprintf(sec_name, sizeof(sec_name), "red");
+ struct rte_red_params
red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
- if (rte_cfgfile_has_section(cfg, sec_name)) {
+ if (rte_cfgfile_has_section(cfg, "red")) {
+ aqm_mode = RTE_SCHED_AQM_WRED;
for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
char str[32];
/* Parse WRED min thresholds */
snprintf(str, sizeof(str), "tc %d wred min", i);
- entry = rte_cfgfile_get_entry(cfg, sec_name, str);
+ entry = rte_cfgfile_get_entry(cfg, "red", str);
if (entry) {
char *next;
/* for each packet colour (green, yellow, red)
*/
@@ -315,7 +315,42 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
rte_sched_subport_params *subpo
}
}
}
-#endif /* RTE_SCHED_RED */
+
+ struct rte_pie_params pie_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];
+
+ if (rte_cfgfile_has_section(cfg, "pie")) {
+ aqm_mode = RTE_SCHED_AQM_PIE;
+
+ for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
+ char str[32];
+
+ /* Parse Queue Delay Ref value */
+ snprintf(str, sizeof(str), "tc %d qdelay ref", i);
+ entry = rte_cfgfile_get_entry(cfg, "pie", str);
+ if (entry)
+ pie_params[i].qdelay_ref = (uint16_t)
atoi(entry);
+
+ /* Parse Max Burst value */
+ snprintf(str, sizeof(str), "tc %d max burst", i);
+ entry = rte_cfgfile_get_entry(cfg, "pie", str);
+ if (entry)
+ pie_params[i].max_burst = (uint16_t)
atoi(entry);
+
+ /* Parse Update Interval Value */
+ snprintf(str, sizeof(str), "tc %d update interval", i);
+ entry = rte_cfgfile_get_entry(cfg, "pie", str);
+ if (entry)
+ pie_params[i].dp_update_interval = (uint16_t)
atoi(entry);
+
+ /* Parse Tailq Threshold Value */
+ snprintf(str, sizeof(str), "tc %d tailq th", i);
+ entry = rte_cfgfile_get_entry(cfg, "pie", str);
+ if (entry)
+ pie_params[i].tailq_th = (uint16_t) atoi(entry);
+
+ }
+ }
+#endif /* RTE_SCHED_AQM */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
char sec_name[CFG_NAME_LEN];
@@ -393,17 +428,30 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct
rte_sched_subport_params *subpo
}
}
}
-#ifdef RTE_SCHED_RED
+#ifdef RTE_SCHED_AQM
+
[dpdk-dev] [RFC PATCH v3 1/3] sched: add PIE based congestion management
Implement PIE based congestion management based on rfc8033
Signed-off-by: Liguzinski, WojciechX
---
drivers/net/softnic/rte_eth_softnic_tm.c | 6 +-
lib/sched/meson.build| 10 +-
lib/sched/rte_pie.c | 78 +
lib/sched/rte_pie.h | 388 +++
lib/sched/rte_sched.c| 229 +
lib/sched/rte_sched.h| 53 +++-
6 files changed, 673 insertions(+), 91 deletions(-)
create mode 100644 lib/sched/rte_pie.c
create mode 100644 lib/sched/rte_pie.h
diff --git a/drivers/net/softnic/rte_eth_softnic_tm.c
b/drivers/net/softnic/rte_eth_softnic_tm.c
index 90baba15ce..5b6c4e6d4b 100644
--- a/drivers/net/softnic/rte_eth_softnic_tm.c
+++ b/drivers/net/softnic/rte_eth_softnic_tm.c
@@ -420,7 +420,7 @@ pmd_tm_node_type_get(struct rte_eth_dev *dev,
return 0;
}
-#ifdef RTE_SCHED_RED
+#ifdef RTE_SCHED_AQM
#define WRED_SUPPORTED 1
#else
#define WRED_SUPPORTED 0
@@ -2306,7 +2306,7 @@ tm_tc_wred_profile_get(struct rte_eth_dev *dev, uint32_t
tc_id)
return NULL;
}
-#ifdef RTE_SCHED_RED
+#ifdef RTE_SCHED_AQM
static void
wred_profiles_set(struct rte_eth_dev *dev, uint32_t subport_id)
@@ -2321,7 +2321,7 @@ wred_profiles_set(struct rte_eth_dev *dev, uint32_t
subport_id)
for (tc_id = 0; tc_id < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; tc_id++)
for (color = RTE_COLOR_GREEN; color < RTE_COLORS; color++) {
struct rte_red_params *dst =
- &pp->red_params[tc_id][color];
+ &pp->wred_params[tc_id][color];
struct tm_wred_profile *src_wp =
tm_tc_wred_profile_get(dev, tc_id);
struct rte_tm_red_params *src =
diff --git a/lib/sched/meson.build b/lib/sched/meson.build
index b24f7b8775..e7ae9bcf19 100644
--- a/lib/sched/meson.build
+++ b/lib/sched/meson.build
@@ -1,11 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-sources = files('rte_sched.c', 'rte_red.c', 'rte_approx.c')
-headers = files(
-'rte_approx.h',
-'rte_red.h',
-'rte_sched.h',
-'rte_sched_common.h',
-)
+sources = files('rte_sched.c', 'rte_red.c', 'rte_approx.c', 'rte_pie.c')
+headers = files('rte_sched.h', 'rte_sched_common.h',
+ 'rte_red.h', 'rte_approx.h', 'rte_pie.h')
deps += ['mbuf', 'meter']
diff --git a/lib/sched/rte_pie.c b/lib/sched/rte_pie.c
new file mode 100644
index 00..f538dda21d
--- /dev/null
+++ b/lib/sched/rte_pie.c
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2020 Intel Corporation
+ */
+
+#include
+
+#include "rte_pie.h"
+#include
+#include
+
+#ifdef __INTEL_COMPILER
+#pragma warning(disable:2259) /* conversion may lose significant bits */
+#endif
+
+int
+rte_pie_rt_data_init(struct rte_pie *pie)
+{
+ if (pie == NULL)
+ return -1;
+
+ pie->active = 0;
+ pie->in_measurement = 0;
+ pie->departed_bytes_count = 0;
+ pie->start_measurement = 0;
+ pie->last_measurement = 0;
+ pie->qlen = 0;
+ pie->avg_dq_time = 0;
+ pie->burst_allowance = 0;
+ pie->qdelay_old = 0;
+ pie->drop_prob = 0;
+ pie->accu_prob = 0;
+
+ return 0;
+}
+
+int
+rte_pie_config_init(struct rte_pie_config *pie_cfg,
+ const uint16_t qdelay_ref,
+ const uint16_t dp_update_interval,
+ const uint16_t max_burst,
+ const uint16_t tailq_th)
+{
+ uint64_t tsc_hz = rte_get_tsc_hz();
+
+ if (pie_cfg == NULL)
+ return -1;
+
+ if (qdelay_ref <= 0) {
+ RTE_LOG(ERR, SCHED,
+ "%s: Incorrect value for qdelay_ref\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dp_update_interval <= 0) {
+ RTE_LOG(ERR, SCHED,
+ "%s: Incorrect value for dp_update_interval\n",
__func__);
+ return -EINVAL;
+ }
+
+ if (max_burst <= 0) {
+ RTE_LOG(ERR, SCHED,
+ "%s: Incorrect value for max_burst\n", __func__);
+ return -EINVAL;
+ }
+
+ if (tailq_th <= 0) {
+ RTE_LOG(ERR, SCHED,
+ "%s: Incorrect value for tailq_th\n", __func__);
+ return -EINVAL;
+ }
+
+ pie_cfg->qdelay_ref = (tsc_hz * qdelay_ref) / 1000;
+ pie_cfg->dp_update_interval = (tsc_hz * dp_update_interval) / 1000;
+ pie_cfg->max_burst = (tsc_hz * max_burst) / 1000;
+ pie_cfg->tailq_th = tailq_th;
+
+ return 0;
+}
diff --git a/lib/sched/rte_pie.h b/lib/sched/rte_pie.h
new file mode 100644
index 00..9295f39c07
--- /dev/null
+++ b/lib/sched/rte_pie.h
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 202
[dpdk-dev] [RFC PATCH v3 3/3] example/ip_pipeline: add PIE support
Adding the PIE support for IP Pipeline
Signed-off-by: Liguzinski, WojciechX
---
examples/ip_pipeline/tmgr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/examples/ip_pipeline/tmgr.c b/examples/ip_pipeline/tmgr.c
index e4e364cbc0..73da2da870 100644
--- a/examples/ip_pipeline/tmgr.c
+++ b/examples/ip_pipeline/tmgr.c
@@ -25,8 +25,8 @@ static const struct rte_sched_subport_params
subport_params_default = {
.pipe_profiles = pipe_profile,
.n_pipe_profiles = 0, /* filled at run time */
.n_max_pipe_profiles = RTE_DIM(pipe_profile),
-#ifdef RTE_SCHED_RED
-.red_params = {
+#ifdef RTE_SCHED_AQM
+.wred_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
@@ -92,7 +92,7 @@ static const struct rte_sched_subport_params
subport_params_default = {
[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
-#endif /* RTE_SCHED_RED */
+#endif /* RTE_SCHED_AQM */
};
static struct tmgr_port_list tmgr_port_list;
--
2.17.1
[dpdk-dev] [PATCH] net/hns3: fix traffic management
From: Huisong Li
In a multi-TC scenario, if the length of packets destined for different
TCs is different, for example, 64B and 1500B packets destined for TC0 and
TC1 respectively. There is a problem that the bandwidth of the TC to which
large packets are sent is preempted by the TC to which small packets are
sent on the Kunpeng 920 network engine. As a result, the TC bandwidth
accuracy is inaccurate.
To solve this problem, this patch made the following adjustments:
1/ During initialization, firmware reports the capability bit indicating
whether the TM function is supported.
2/ The command word for configuring TC and port rate limiting is added,
instead of reusing the existing command word. And firmware configured
to the correct module.
3/ When the PF driver is loaded, firmware completes the default
initialization of the TC and port.
Fixes: c09c7847d892 ("net/hns3: support traffic management")
Signed-off-by: Huisong Li
Signed-off-by: Min Hu (Connor)
---
drivers/net/hns3/hns3_cmd.c| 5 ++-
drivers/net/hns3/hns3_cmd.h| 4 +++
drivers/net/hns3/hns3_dcb.c| 4 +--
drivers/net/hns3/hns3_dcb.h| 2 --
drivers/net/hns3/hns3_ethdev.h | 4 +++
drivers/net/hns3/hns3_tm.c | 69 +-
drivers/net/hns3/hns3_tm.h | 12
7 files changed, 74 insertions(+), 26 deletions(-)
diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
index 44a4e28..cdccbf5 100644
--- a/drivers/net/hns3/hns3_cmd.c
+++ b/drivers/net/hns3/hns3_cmd.c
@@ -427,7 +427,8 @@ hns3_get_caps_name(uint32_t caps_id)
{ HNS3_CAPS_STASH_B, "stash" },
{ HNS3_CAPS_UDP_TUNNEL_CSUM_B, "udp_tunnel_csum" },
{ HNS3_CAPS_RAS_IMP_B, "ras_imp" },
- { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" }
+ { HNS3_CAPS_RXD_ADV_LAYOUT_B, "rxd_adv_layout" },
+ { HNS3_CAPS_TM_B, "tm_capability" }
};
uint32_t i;
@@ -503,6 +504,8 @@ hns3_parse_capability(struct hns3_hw *hw,
HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, 1);
if (hns3_get_bit(caps, HNS3_CAPS_RAS_IMP_B))
hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RAS_IMP_B, 1);
+ if (hns3_get_bit(caps, HNS3_CAPS_TM_B))
+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TM_B, 1);
}
static uint32_t
diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
index eafa365..0c9b8fc 100644
--- a/drivers/net/hns3/hns3_cmd.h
+++ b/drivers/net/hns3/hns3_cmd.h
@@ -162,6 +162,9 @@ enum hns3_opcode_type {
HNS3_OPC_TM_INTERNAL_CNT= 0x0851,
HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852,
+ HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870,
+ HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871,
+
/* Mailbox cmd */
HNS3_OPC_MBX_VF_TO_PF = 0x2001,
@@ -319,6 +322,7 @@ enum HNS3_CAPS_BITS {
HNS3_CAPS_UDP_TUNNEL_CSUM_B,
HNS3_CAPS_RAS_IMP_B,
HNS3_CAPS_RXD_ADV_LAYOUT_B = 15,
+ HNS3_CAPS_TM_B = 17,
};
enum HNS3_API_CAP_BITS {
diff --git a/drivers/net/hns3/hns3_dcb.c b/drivers/net/hns3/hns3_dcb.c
index 90c0d04..f15c899 100644
--- a/drivers/net/hns3/hns3_dcb.c
+++ b/drivers/net/hns3/hns3_dcb.c
@@ -415,7 +415,7 @@ hns3_dcb_pg_shapping_cfg(struct hns3_hw *hw, enum
hns3_shap_bucket bucket,
return hns3_cmd_send(hw, &desc, 1);
}
-int
+static int
hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate)
{
struct hns3_shaper_parameter shaper_parameter;
@@ -551,7 +551,7 @@ hns3_dcb_pri_shapping_cfg(struct hns3_hw *hw, enum
hns3_shap_bucket bucket,
return hns3_cmd_send(hw, &desc, 1);
}
-int
+static int
hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate)
{
struct hns3_shaper_parameter shaper_parameter;
diff --git a/drivers/net/hns3/hns3_dcb.h b/drivers/net/hns3/hns3_dcb.h
index f378bd4..e06ec17 100644
--- a/drivers/net/hns3/hns3_dcb.h
+++ b/drivers/net/hns3/hns3_dcb.h
@@ -209,8 +209,6 @@ int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t
nb_rx_q,
int hns3_update_queue_map_configure(struct hns3_adapter *hns);
int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);
-int hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate);
-int hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate);
uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);
#endif /* _HNS3_DCB_H_ */
diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
index 575bacd..0b11a8d 100644
--- a/drivers/net/hns3/hns3_ethdev.h
+++ b/drivers/net/hns3/hns3_ethdev.h
@@ -868,6 +868,7 @@ enum {
HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
HNS3_DEV_SUPPORT_RAS_IMP_B,
+ HNS3_DEV_SUPPORT_TM_B,
};
#define hns3_dev_dcb_supported(hw) \
@@ -904,6 +905,9 @@ enum {
#define hns3_dev_tx_p
[dpdk-dev] [PATCH v6 0/3] support AVF RSS and FDIR for GTPoGRE packet
Support AVF RSS and FDIR for GTPoGRE packet. Lingyu Liu (3): net/iavf: support flow pattern for GTPoGRE net/iavf: support AVF FDIR for GTPoGRE tunnel packet net/iavf: support AVF RSS for GTPoGRE packet --- V6 change: - rebase and remove GRE pattern parse in FDIR V5 change: - refine protocol header for two tunnels case - move IPV6 patterns to the IPV6 block in pattern list V4 change: - add RTE_FLOW_ITEM_TYPE_GRE in hash parse pattern function V3 change: - add GTPU extension header pattern drivers/net/iavf/iavf_fdir.c | 48 +++ drivers/net/iavf/iavf_generic_flow.c | 600 +++ drivers/net/iavf/iavf_generic_flow.h | 80 drivers/net/iavf/iavf_hash.c | 142 +-- 4 files changed, 846 insertions(+), 24 deletions(-) -- 2.25.1
[dpdk-dev] [PATCH v6 1/3] net/iavf: support flow pattern for GTPoGRE
Add GTPoGRE pattern support for AVF FDIR and RSS.
Signed-off-by: Lingyu Liu
---
drivers/net/iavf/iavf_generic_flow.c | 600 +++
drivers/net/iavf/iavf_generic_flow.h | 80
2 files changed, 680 insertions(+)
diff --git a/drivers/net/iavf/iavf_generic_flow.c
b/drivers/net/iavf/iavf_generic_flow.c
index d9ba5735b2..f6f6adc886 100644
--- a/drivers/net/iavf/iavf_generic_flow.c
+++ b/drivers/net/iavf/iavf_generic_flow.c
@@ -433,6 +433,606 @@ enum rte_flow_item_type
iavf_pattern_eth_ipv4_gtpu_ipv4_icmp[] = {
RTE_FLOW_ITEM_TYPE_END,
};
+/* IPV4 GRE IPv4 UDP GTPU IPv4*/
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_udp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_tcp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_TCP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+/* IPV4 GRE IPv4 UDP GTPU IPv6*/
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6_udp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6_tcp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_TCP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+/* IPV4 GRE IPv6 UDP GTPU IPv4*/
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_udp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_tcp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_TCP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+/* IPV4 GRE IPv6 UDP GTPU IPv6*/
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6_udp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_END,
+};
+
+enum rte_flow_item_type iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6_tcp[] = {
+ RTE_FLOW_ITEM_TYPE_ETH,
+ RTE_FLOW_ITEM_TYPE_IPV4,
+ RTE_FLOW_ITEM_TYPE_GRE,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ RTE_FLOW_ITEM_TYPE_UDP,
+ RTE_FLOW_ITEM_TYPE_GTPU,
+ RTE_FLOW_ITEM_TYPE_IPV6,
+ R
[dpdk-dev] [PATCH v6 2/3] net/iavf: support AVF FDIR for GTPoGRE tunnel packet
Support AVF FDIR for inner header of GTPoGRE tunnel packet.
++---+
|Pattern |Input Set |
++---+
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4|inner: src/dst ip |
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6|inner: src/dst ip |
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv4/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4|inner: src/dst ip |
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6|inner: src/dst ip |
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv4/gre/ipv6/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4|inner: src/dst ip |
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6|inner: src/dst ip |
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv4/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4|inner: src/dst ip |
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv4/tcp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6|inner: src/dst ip |
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6/udp|inner: src/dst ip, src/dst port|
|eth/ipv6/gre/ipv6/gtpu/(eh/)ipv6/tcp|inner: src/dst ip, src/dst port|
++---+
Signed-off-by: Lingyu Liu
---
drivers/net/iavf/iavf_fdir.c | 48
1 file changed, 48 insertions(+)
diff --git a/drivers/net/iavf/iavf_fdir.c b/drivers/net/iavf/iavf_fdir.c
index dde25c18ce..935ac50cab 100644
--- a/drivers/net/iavf/iavf_fdir.c
+++ b/drivers/net/iavf/iavf_fdir.c
@@ -193,6 +193,54 @@ static struct iavf_pattern_match_item iavf_fdir_pattern[]
= {
{iavf_pattern_eth_ipv4_gtpu_eh_ipv6, IAVF_FDIR_INSET_GTPU_IPV6,
IAVF_INSET_NONE},
{iavf_pattern_eth_ipv4_gtpu_eh_ipv6_udp, IAVF_FDIR_INSET_GTPU_IPV6_UDP,
IAVF_INSET_NONE},
{iavf_pattern_eth_ipv4_gtpu_eh_ipv6_tcp, IAVF_FDIR_INSET_GTPU_IPV6_TCP,
IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4,
IAVF_FDIR_INSET_GTPU_IPV4, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_udp,
IAVF_FDIR_INSET_GTPU_IPV4_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_tcp,
IAVF_FDIR_INSET_GTPU_IPV4_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6,
IAVF_FDIR_INSET_GTPU_IPV6, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6_udp,
IAVF_FDIR_INSET_GTPU_IPV6_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv6_tcp,
IAVF_FDIR_INSET_GTPU_IPV6_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4,
IAVF_FDIR_INSET_GTPU_IPV4, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_udp,
IAVF_FDIR_INSET_GTPU_IPV4_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_tcp,
IAVF_FDIR_INSET_GTPU_IPV4_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6,
IAVF_FDIR_INSET_GTPU_IPV6, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6_udp,
IAVF_FDIR_INSET_GTPU_IPV6_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv6_tcp,
IAVF_FDIR_INSET_GTPU_IPV6_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4,
IAVF_FDIR_INSET_GTPU_IPV4, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4_udp,
IAVF_FDIR_INSET_GTPU_IPV4_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4_tcp,
IAVF_FDIR_INSET_GTPU_IPV4_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv6,
IAVF_FDIR_INSET_GTPU_IPV6, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv6_udp,
IAVF_FDIR_INSET_GTPU_IPV6_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv6_tcp,
IAVF_FDIR_INSET_GTPU_IPV6_TCP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4,
IAVF_FDIR_INSET_GTPU_IPV4, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4_udp,
IAVF_FDIR_INSET_GTPU_IPV4_UDP, IAVF_INSET_NONE},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4_tcp,
IAVF_FDIR_INSET_GTPU_IPV4_TCP, IAVF_INSET_NONE},
+
[dpdk-dev] [PATCH v6 3/3] net/iavf: support AVF RSS for GTPoGRE packet
Support AVF RSS for inner most header of GTPoGRE packet. It supports
RSS based on inner most IP src + dst address and TCP/UDP src + dst
port.
Signed-off-by: Lingyu Liu
---
drivers/net/iavf/iavf_hash.c | 142 +--
1 file changed, 118 insertions(+), 24 deletions(-)
diff --git a/drivers/net/iavf/iavf_hash.c b/drivers/net/iavf/iavf_hash.c
index f4f0bcbfef..03dae5d999 100644
--- a/drivers/net/iavf/iavf_hash.c
+++ b/drivers/net/iavf/iavf_hash.c
@@ -31,6 +31,9 @@
#define IAVF_PHINT_OUTER_IPV4 BIT_ULL(4)
#define IAVF_PHINT_OUTER_IPV6 BIT_ULL(5)
#define IAVF_PHINT_GRE BIT_ULL(6)
+/* the second IP header of GTPoGRE */
+#define IAVF_PHINT_MID_IPV4BIT_ULL(7)
+#define IAVF_PHINT_MID_IPV6BIT_ULL(8)
#define IAVF_PHINT_GTPU_MSK(IAVF_PHINT_GTPU| \
IAVF_PHINT_GTPU_EH | \
@@ -233,6 +236,30 @@ struct virtchnl_proto_hdrs inner_ipv4_tcp_tmplt = {
TUNNEL_LEVEL_INNER, 2, {proto_hdr_ipv4_with_prot, proto_hdr_tcp}
};
+struct virtchnl_proto_hdrs second_inner_ipv4_tmplt = {
+ 2, 1, {proto_hdr_ipv4}
+};
+
+struct virtchnl_proto_hdrs second_inner_ipv4_udp_tmplt = {
+ 2, 2, {proto_hdr_ipv4_with_prot, proto_hdr_udp}
+};
+
+struct virtchnl_proto_hdrs second_inner_ipv4_tcp_tmplt = {
+ 2, 2, {proto_hdr_ipv4_with_prot, proto_hdr_tcp}
+};
+
+struct virtchnl_proto_hdrs second_inner_ipv6_tmplt = {
+ 2, 1, {proto_hdr_ipv6}
+};
+
+struct virtchnl_proto_hdrs second_inner_ipv6_udp_tmplt = {
+ 2, 2, {proto_hdr_ipv6_with_prot, proto_hdr_udp}
+};
+
+struct virtchnl_proto_hdrs second_inner_ipv6_tcp_tmplt = {
+ 2, 2, {proto_hdr_ipv6_with_prot, proto_hdr_tcp}
+};
+
struct virtchnl_proto_hdrs inner_ipv4_sctp_tmplt = {
TUNNEL_LEVEL_INNER, 2, {proto_hdr_ipv4, proto_hdr_sctp}
};
@@ -421,6 +448,30 @@ static struct iavf_pattern_match_item
iavf_hash_pattern_list[] = {
{iavf_pattern_eth_ipv6_gtpu_eh_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&inner_ipv4_tmplt},
{iavf_pattern_eth_ipv6_gtpu_eh_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&inner_ipv4_udp_tmplt},
{iavf_pattern_eth_ipv6_gtpu_eh_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv6_gtpu_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_eh_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_eh_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv4_gtpu_eh_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_eh_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_eh_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv4_gre_ipv6_gtpu_eh_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_eh_ipv4,
IAVF_RSS_TYPE_GTPU_IPV4,&second_inner_ipv4_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_eh_ipv4_udp,
IAVF_RSS_TYPE_GTPU_IPV4_UDP,&second_inner_ipv4_udp_tmplt},
+ {iavf_pattern_eth_ipv6_gre_ipv4_gtpu_eh_ipv4_tcp,
IAVF_RSS_TYPE_GTPU_IPV4_TCP,&second_inner_ipv4_tcp_tmplt},
+ {iavf_p
[dpdk-dev] [PATCH v3 01/15] net/i40e/base: add new versions of send ASQ command functions
ASQ send command functions are returning only i40e status codes
yet some calling functions also need Admin Queue status
that is stored in hw->aq.asq_last_status. Since hw object
is stored on a heap it introduces a possibility for
a race condition in access to hw if calling function is not
fast enough to read hw->aq.asq_last_status before next
send ASQ command is executed.
Added new versions of send ASQ command functions that return
Admin Queue status on the stack to avoid race conditions
in access to hw->aq.asq_last_status.
Added new _v2 version of i40e_aq_remove_macvlan and i40e_aq_add_macvlan
that is using new _v2 versions of ASQ send command functions and
returns the Admin Queue status on the stack.
Signed-off-by: Sylwester Dziedziuch
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq.c| 73 +++--
drivers/net/i40e/base/i40e_common.c| 139 ++---
drivers/net/i40e/base/i40e_prototype.h | 17 +++
3 files changed, 205 insertions(+), 24 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq.c
b/drivers/net/i40e/base/i40e_adminq.c
index 0da45f03e4..eafacbdbec 100644
--- a/drivers/net/i40e/base/i40e_adminq.c
+++ b/drivers/net/i40e/base/i40e_adminq.c
@@ -834,7 +834,7 @@ STATIC bool i40e_asq_done(struct i40e_hw *hw)
}
/**
- * i40e_asq_send_command - send command to Admin Queue
+ * i40e_asq_send_command_exec - send command to Admin Queue
* @hw: pointer to the hw struct
* @desc: prefilled descriptor describing the command (non DMA mem)
* @buff: buffer to use for indirect commands
@@ -844,11 +844,12 @@ STATIC bool i40e_asq_done(struct i40e_hw *hw)
* This is the main send command driver routine for the Admin Queue send
* queue. It runs the queue, cleans the queue, etc
**/
-enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
- struct i40e_aq_desc *desc,
- void *buff, /* can be NULL */
- u16 buff_size,
- struct i40e_asq_cmd_details *cmd_details)
+STATIC enum i40e_status_code
+i40e_asq_send_command_exec(struct i40e_hw *hw,
+ struct i40e_aq_desc *desc,
+ void *buff, /* can be NULL */
+ u16 buff_size,
+ struct i40e_asq_cmd_details *cmd_details)
{
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_dma_mem *dma_buff = NULL;
@@ -858,8 +859,6 @@ enum i40e_status_code i40e_asq_send_command(struct i40e_hw
*hw,
u16 retval = 0;
u32 val = 0;
- i40e_acquire_spinlock(&hw->aq.asq_spinlock);
-
hw->aq.asq_last_status = I40E_AQ_RC_OK;
if (hw->aq.asq.count == 0) {
@@ -1042,6 +1041,64 @@ enum i40e_status_code i40e_asq_send_command(struct
i40e_hw *hw,
}
asq_send_command_error:
+ return status;
+}
+
+/**
+ * i40e_asq_send_command - send command to Admin Queue
+ * @hw: pointer to the hw struct
+ * @desc: prefilled descriptor describing the command (non DMA mem)
+ * @buff: buffer to use for indirect commands
+ * @buff_size: size of buffer for indirect commands
+ * @cmd_details: pointer to command details structure
+ *
+ * Acquires the lock and calls the main send command execution
+ * routine.
+ **/
+enum i40e_status_code
+i40e_asq_send_command(struct i40e_hw *hw,
+ struct i40e_aq_desc *desc,
+ void *buff, /* can be NULL */
+ u16 buff_size,
+ struct i40e_asq_cmd_details *cmd_details)
+{
+ enum i40e_status_code status = I40E_SUCCESS;
+
+ i40e_acquire_spinlock(&hw->aq.asq_spinlock);
+ status = i40e_asq_send_command_exec(hw, desc, buff, buff_size,
+ cmd_details);
+ i40e_release_spinlock(&hw->aq.asq_spinlock);
+ return status;
+}
+
+/**
+ * i40e_asq_send_command_v2 - send command to Admin Queue
+ * @hw: pointer to the hw struct
+ * @desc: prefilled descriptor describing the command (non DMA mem)
+ * @buff: buffer to use for indirect commands
+ * @buff_size: size of buffer for indirect commands
+ * @cmd_details: pointer to command details structure
+ * @aq_status: pointer to Admin Queue status return value
+ *
+ * Acquires the lock and calls the main send command execution
+ * routine. Returns the last Admin Queue status in aq_status
+ * to avoid race conditions in access to hw->aq.asq_last_status.
+ **/
+enum i40e_status_code
+i40e_asq_send_command_v2(struct i40e_hw *hw,
+struct i40e_aq_desc *desc,
+void *buff, /* can be NULL */
+u16 buff_size,
+struct i40e_asq_cmd_details *cmd_details,
+enum i40e_admin_queue_err *aq_status)
+{
+ enum i40e_status_code status = I40E_SUCCESS;
+
+ i40e_acquire_spinlock(&hw->aq.asq_spinlock);
+ status = i40e_asq_
[dpdk-dev] [PATCH v3 03/15] net/i40e/base: add support for Min Rollback Revision for 4 more X722 modules
This change increments X722 API version and adds new constants related to
the extended implementation of Security Version Opt-In.
Signed-off-by: Stanislaw Grzeszczak
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
b/drivers/net/i40e/base/i40e_adminq_cmd.h
index b5ac74787b..a73a08aae6 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -12,7 +12,7 @@
*/
#define I40E_FW_API_VERSION_MAJOR 0x0001
-#define I40E_FW_API_VERSION_MINOR_X722 0x000B
+#define I40E_FW_API_VERSION_MINOR_X722 0x000C
#define I40E_FW_API_VERSION_MINOR_X710 0x000E
#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
@@ -2425,11 +2425,15 @@ struct i40e_aqc_rollback_revision_update {
u8 optin_mode; /* bool */
#define I40E_AQ_RREV_OPTION_MODE 0x01
u8 module_selected;
-#define I40E_AQ_RREV_MODULE_PCIE_ANALOG0
-#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1
-#define I40E_AQ_RREV_MODULE_OPTION_ROM 2
-#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3
-#define I40E_AQ_RREV_MODULE_PE_IMAGE 4
+#define I40E_AQ_RREV_MODULE_PCIE_ANALOG0
+#define I40E_AQ_RREV_MODULE_PHY_ANALOG 1
+#define I40E_AQ_RREV_MODULE_OPTION_ROM 2
+#define I40E_AQ_RREV_MODULE_EMP_IMAGE 3
+#define I40E_AQ_RREV_MODULE_PE_IMAGE 4
+#define I40E_AQ_RREV_MODULE_PHY_PLL_O_CONFIGURATION5
+#define I40E_AQ_RREV_MODULE_PHY_0_CONFIGURATION6
+#define I40E_AQ_RREV_MODULE_PHY_PLL_1_CONFIGURATION7
+#define I40E_AQ_RREV_MODULE_PHY_1_CONFIGURATION8
u8 reserved1[2];
u32 min_rrev;
u8 reserved2[8];
--
2.25.1
[dpdk-dev] [PATCH v3 04/15] net/i40e/base: set TSA table values when parsing CEE configuration
Driver did not Set TSA table values when parsing CEE configuration
obtained from FW.
Signed-off-by: Pawel Malinowski
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_dcb.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/net/i40e/base/i40e_dcb.c b/drivers/net/i40e/base/i40e_dcb.c
index 388af3d64d..27b52bc365 100644
--- a/drivers/net/i40e/base/i40e_dcb.c
+++ b/drivers/net/i40e/base/i40e_dcb.c
@@ -315,9 +315,15 @@ static void i40e_parse_cee_pgcfg_tlv(struct
i40e_cee_feat_tlv *tlv,
*|pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
*-
*/
- for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
+ for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
etscfg->tcbwtable[i] = buf[offset++];
+ if (etscfg->prioritytable[i] == I40E_CEE_PGID_STRICT)
+ dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_STRICT;
+ else
+ dcbcfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
+ }
+
/* Number of TCs supported (1 octet) */
etscfg->maxtcs = buf[offset];
}
--
2.25.1
[dpdk-dev] [PATCH v3 05/15] net/i40e/base: define new Shadow RAM pointers
Add definitions for Shadow RAM pointers: 6th FPA module, 5th FPA module
in X722 and Preservation Rules Module.
Signed-off-by: Stanislaw Grzeszczak
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_type.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/i40e/base/i40e_type.h
b/drivers/net/i40e/base/i40e_type.h
index cf41345834..e5a3729183 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -1555,6 +1555,9 @@ struct i40e_hw_port_stats {
#define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49
#define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D
#define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E
+#define I40E_SR_PRESERVATION_RULES_PTR 0x70
+#define I40E_X722_SR_5TH_FREE_PROVISION_AREA_PTR 0x71
+#define I40E_SR_6TH_FREE_PROVISION_AREA_PTR0x71
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
#define I40E_SR_VPD_MODULE_MAX_SIZE1024
--
2.25.1
[dpdk-dev] [PATCH v3 00/15] i40e base code update
update i40e base code.
source code of i40e driver:
cid-i40e.2021.04.29.tar.gz
changelog in i40e share repo:
>From 59a080f4fafe ("i40e-shared: Add opcode 0x0406 and 0x0416 to Linux
support") To bedcbea1063 ("i40e-shared: Fix potentially uninitialized
variables in NVM code")
The following commits are ignored:
cb9139e3bce8 ("i40e-shared: Fix not blinking X722 with x557 PHY via
‘ethtool -p'")
c09d4f9cf390 ("i40e-shared: i40e-shared: Fix build warning -Wformat
related to integer size")
ff8a1abc6c17 ("i40e-shared: Fix build warning with __packed")
59a080f4fafe ("i40e-shared: Add opcode 0x0406 and 0x0416 to Linux
support")
v2:
- refine commit messages and macro name
v3:
- there has a fix patch contains two issues, split it into two patches
Robin Zhang (15):
net/i40e/base: add new versions of send ASQ command functions
net/i40e/base: update X710 FW API version to 1.14
net/i40e/base: add support for Min Rollback Revision for 4 more X722
modules
net/i40e/base: set TSA table values when parsing CEE configuration
net/i40e/base: define new Shadow RAM pointers
net/i40e/base: fix PHY type identifiers for 2.5G and 5G adapters
net/i40e/base: fix PF reset failed
net/i40e/base: fix update link data for X722
net/i40e/base: fix AOC media type reported by ethtool
net/i40e/base: add flags and fields for double vlan processing
net/i40e/base: 10GBASE-ER Optical modules recognition
net/i40e/base: fix headers to match functions
net/i40e/base: fix potentially uninitialized variables in NVM code
net/i40e/base: fix checksum is used before return value is checked
net/i40e/base: update version in readme
drivers/net/i40e/base/README| 2 +-
drivers/net/i40e/base/i40e_adminq.c | 79 +--
drivers/net/i40e/base/i40e_adminq_cmd.h | 48 +--
drivers/net/i40e/base/i40e_common.c | 176 +++-
drivers/net/i40e/base/i40e_dcb.c| 10 +-
drivers/net/i40e/base/i40e_lan_hmc.c| 2 +-
drivers/net/i40e/base/i40e_nvm.c| 7 +-
drivers/net/i40e/base/i40e_prototype.h | 17 +++
drivers/net/i40e/base/i40e_type.h | 12 +-
9 files changed, 288 insertions(+), 65 deletions(-)
--
2.25.1
[dpdk-dev] [PATCH v3 06/15] net/i40e/base: fix PHY type identifiers for 2.5G and 5G adapters
Unlike other supported adapters, 2.5G and 5G use different
PHY type identifiers for reading/writing PHY settings
and for reading link status. This commit intruduces
separate PHY identifiers for these two operation types.
Fixes: 988ed63c7441 ("net/i40e/base: add support for Carlsville device")
Cc: sta...@dpdk.org
Signed-off-by: Dawid Lukwinski
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 6 --
drivers/net/i40e/base/i40e_common.c | 4 ++--
drivers/net/i40e/base/i40e_type.h | 8 ++--
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
b/drivers/net/i40e/base/i40e_adminq_cmd.h
index a73a08aae6..1aafe1de38 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -1947,8 +1947,10 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_25GBASE_LR= 0x22,
I40E_PHY_TYPE_25GBASE_AOC = 0x23,
I40E_PHY_TYPE_25GBASE_ACC = 0x24,
- I40E_PHY_TYPE_2_5GBASE_T= 0x30,
- I40E_PHY_TYPE_5GBASE_T = 0x31,
+ I40E_PHY_TYPE_2_5GBASE_T= 0x26,
+ I40E_PHY_TYPE_5GBASE_T = 0x27,
+ I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS= 0x30,
+ I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
I40E_PHY_TYPE_MAX,
I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
I40E_PHY_TYPE_EMPTY = 0xFE,
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index 32642f3e2b..ceedec68bf 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1280,8 +1280,8 @@ STATIC enum i40e_media_type i40e_get_media_type(struct
i40e_hw *hw)
break;
case I40E_PHY_TYPE_100BASE_TX:
case I40E_PHY_TYPE_1000BASE_T:
- case I40E_PHY_TYPE_2_5GBASE_T:
- case I40E_PHY_TYPE_5GBASE_T:
+ case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
+ case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
case I40E_PHY_TYPE_10GBASE_T:
media = I40E_MEDIA_TYPE_BASET;
break;
diff --git a/drivers/net/i40e/base/i40e_type.h
b/drivers/net/i40e/base/i40e_type.h
index e5a3729183..0323887550 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -329,12 +329,8 @@ struct i40e_phy_info {
I40E_PHY_TYPE_OFFSET)
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
I40E_PHY_TYPE_OFFSET)
-/* Offset for 2.5G/5G PHY Types value to bit number conversion */
-#define I40E_PHY_TYPE_OFFSET2 (-10)
-#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \
-I40E_PHY_TYPE_OFFSET2)
-#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \
-I40E_PHY_TYPE_OFFSET2)
+#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
+#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
#define I40E_HW_CAP_MAX_GPIO 30
#define I40E_HW_CAP_MDIO_PORT_MODE_MDIO0
#define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1
--
2.25.1
[dpdk-dev] [PATCH v3 07/15] net/i40e/base: fix PF reset failed
PF has to delete all the filters during reset.
If it is fully loaded with filters then it is possible
that it will take more than 200 ms to finish the reset
resulting in timeout during pf_reset and
PF reset failed, -15 error indication.
Increasing the timeout value for PF reset from 200 to 1000
to give PF more time to finish reset if it is loaded with filters.
Fixes: 1e32378f0774 ("i40e/base: increase PF reset max loop limit")
Cc: sta...@dpdk.org
Signed-off-by: Sylwester Dziedziuch
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index ceedec68bf..aa424e6010 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1341,7 +1341,7 @@ STATIC enum i40e_status_code i40e_poll_globr(struct
i40e_hw *hw,
return I40E_ERR_RESET_FAILED;
}
-#define I40E_PF_RESET_WAIT_COUNT 200
+#define I40E_PF_RESET_WAIT_COUNT 1000
/**
* i40e_pf_reset - Reset the PF
* @hw: pointer to the hardware structure
--
2.25.1
[dpdk-dev] [PATCH v3 08/15] net/i40e/base: fix update link data for X722
The X722 card has 'Link Type' information elsewhere than the X710.
Previously, for all cards, the 'Link Type' information was retrieved by
opcode 0x0607 and this value was wrong for all X722 cards.
Now this information for X722 only is taken by opcode 0x0600
(function: i40e_aq_get_phy_capabilities) instead of an opcode
0x0607 (function: i40e_aq_get_link_info).
All other parameters read by opcode 0x0607 unchanged.
Fixes: e6691b428eb1 ("i40e/base: fix PHY NVM interaction")
Fixes: 75c3de654ead ("net/i40e/base: fix long link down notification time")
Cc: sta...@dpdk.org
Signed-off-by: Jaroslaw Gawin
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_common.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index aa424e6010..ef061a6b63 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -2078,6 +2078,9 @@ enum i40e_status_code i40e_aq_get_link_info(struct
i40e_hw *hw,
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
+ /* 'Get Link Status' response data structure from X722 FW has
+* different format and does not contain this information
+*/
if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
hw->mac.type != I40E_MAC_X722) {
__le32 tmp;
@@ -2948,10 +2951,13 @@ enum i40e_status_code i40e_update_link_info(struct
i40e_hw *hw)
return status;
/* extra checking needed to ensure link info to user is timely */
- if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
- ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
-!(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
- status = i40e_aq_get_phy_capabilities(hw, false, false,
+ if (((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
+((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
+ !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) ||
+ hw->mac.type == I40E_MAC_X722) {
+ status = i40e_aq_get_phy_capabilities(hw, false,
+ hw->mac.type ==
+ I40E_MAC_X722,
&abilities, NULL);
if (status)
return status;
--
2.25.1
[dpdk-dev] [PATCH v3 02/15] net/i40e/base: update X710 FW API version to 1.14
Update X710 FW increment API version to 1.14 Signed-off-by: Sylwester Dziedziuch Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 2ca41db5d3..b5ac74787b 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -13,7 +13,7 @@ #define I40E_FW_API_VERSION_MAJOR 0x0001 #define I40E_FW_API_VERSION_MINOR_X722 0x000B -#define I40E_FW_API_VERSION_MINOR_X710 0x000C +#define I40E_FW_API_VERSION_MINOR_X710 0x000E #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ I40E_FW_API_VERSION_MINOR_X710 : \ -- 2.25.1
[dpdk-dev] [PATCH v3 09/15] net/i40e/base: fix AOC media type reported by ethtool
For Active Optical Cable (AOC) the correct media type is "Fibre",
not "Direct Attach Copper".
Fixes: d749d4d89969 ("i40e/base: add AOC PHY types")
Fixes: aa153cc89ff0 ("net/i40e/base: add new PHY types for 25G AOC and
ACC")
Cc: sta...@dpdk.org
Signed-off-by: Dawid Lukwinski
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_common.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index ef061a6b63..2ca6a13e79 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1276,6 +1276,9 @@ STATIC enum i40e_media_type i40e_get_media_type(struct
i40e_hw *hw)
case I40E_PHY_TYPE_40GBASE_LR4:
case I40E_PHY_TYPE_25GBASE_LR:
case I40E_PHY_TYPE_25GBASE_SR:
+ case I40E_PHY_TYPE_10GBASE_AOC:
+ case I40E_PHY_TYPE_25GBASE_AOC:
+ case I40E_PHY_TYPE_40GBASE_AOC:
media = I40E_MEDIA_TYPE_FIBER;
break;
case I40E_PHY_TYPE_100BASE_TX:
@@ -1290,10 +1293,7 @@ STATIC enum i40e_media_type i40e_get_media_type(struct
i40e_hw *hw)
case I40E_PHY_TYPE_10GBASE_CR1:
case I40E_PHY_TYPE_40GBASE_CR4:
case I40E_PHY_TYPE_10GBASE_SFPP_CU:
- case I40E_PHY_TYPE_40GBASE_AOC:
- case I40E_PHY_TYPE_10GBASE_AOC:
case I40E_PHY_TYPE_25GBASE_CR:
- case I40E_PHY_TYPE_25GBASE_AOC:
case I40E_PHY_TYPE_25GBASE_ACC:
media = I40E_MEDIA_TYPE_DA;
break;
--
2.25.1
[dpdk-dev] [PATCH v3 10/15] net/i40e/base: add flags and fields for double vlan processing
Add flags for outer vlan and include set port parameters in Linux
compilation.
Add flags, which describe port and switch state for both double vlan
functionality and outer vlan processing.
Signed-off-by: Przemyslaw Patynowski
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
b/drivers/net/i40e/base/i40e_adminq_cmd.h
index 1aafe1de38..646cfd0398 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -768,6 +768,7 @@ struct i40e_aqc_set_switch_config {
#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
#define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT0x0004
+#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008
__le16 valid_flags;
/* The ethertype in switch_tag is dropped on ingress and used
* internally by the switch. Set this to zero for the default
@@ -904,7 +905,7 @@ struct i40e_aqc_vsi_properties_data {
u8 sec_reserved;
/* VLAN section */
__le16 pvid; /* VLANS include priority bits */
- __le16 fcoe_pvid;
+ __le16 outer_vlan;
u8 port_vlan_flags;
#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
#define I40E_AQ_VSI_PVLAN_MODE_MASK(0x03 << \
@@ -920,7 +921,24 @@ struct i40e_aqc_vsi_properties_data {
#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
- u8 pvlan_reserved[3];
+ u8 outer_vlan_flags;
+#define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00
+#define I40E_AQ_VSI_OVLAN_MODE_MASK(0x03 << \
+I40E_AQ_VSI_OVLAN_MODE_SHIFT)
+#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED0x01
+#define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02
+#define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03
+#define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04
+#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03
+#define I40E_AQ_VSI_OVLAN_EMOD_MASK(0x03 <<\
+I40E_AQ_VSI_OVLAN_EMOD_SHIFT)
+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL0x00
+#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01
+#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL0x02
+#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03
+#define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04
+
+ u8 pvlan_reserved[2];
/* ingress egress up sections */
__le32 ingress_table; /* bitmap, 3 bits per up */
#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
--
2.25.1
[dpdk-dev] [PATCH v3 11/15] net/i40e/base: 10GBASE-ER Optical modules recognition
This change adds a new PHY type for 10GBASE-ER modules.
Signed-off-by: Stanislaw Grzeszczak
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 2 ++
drivers/net/i40e/base/i40e_common.c | 1 +
drivers/net/i40e/base/i40e_type.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
b/drivers/net/i40e/base/i40e_adminq_cmd.h
index 646cfd0398..c41dc71cdf 100644
--- a/drivers/net/i40e/base/i40e_adminq_cmd.h
+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h
@@ -1945,6 +1945,7 @@ enum i40e_aq_phy_type {
I40E_PHY_TYPE_40GBASE_AOC = 0xD,
I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
I40E_PHY_TYPE_UNSUPPORTED = 0xF,
+ I40E_PHY_TYPE_10GBASE_ER= 0x10,
I40E_PHY_TYPE_100BASE_TX= 0x11,
I40E_PHY_TYPE_1000BASE_T= 0x12,
I40E_PHY_TYPE_10GBASE_T = 0x13,
@@ -1991,6 +1992,7 @@ enum i40e_aq_phy_type {
BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
+ BIT_ULL(I40E_PHY_TYPE_10GBASE_ER) | \
BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index 2ca6a13e79..e077bf8fd3 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -1268,6 +1268,7 @@ STATIC enum i40e_media_type i40e_get_media_type(struct
i40e_hw *hw)
enum i40e_media_type media;
switch (hw->phy.link_info.phy_type) {
+ case I40E_PHY_TYPE_10GBASE_ER:
case I40E_PHY_TYPE_10GBASE_SR:
case I40E_PHY_TYPE_10GBASE_LR:
case I40E_PHY_TYPE_1000BASE_SX:
diff --git a/drivers/net/i40e/base/i40e_type.h
b/drivers/net/i40e/base/i40e_type.h
index 0323887550..86b9eeeb43 100644
--- a/drivers/net/i40e/base/i40e_type.h
+++ b/drivers/net/i40e/base/i40e_type.h
@@ -294,6 +294,7 @@ struct i40e_phy_info {
#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
+#define I40E_CAP_PHY_TYPE_10GBASE_ER BIT_ULL(I40E_PHY_TYPE_10GBASE_ER)
#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
--
2.25.1
[dpdk-dev] [PATCH v3 12/15] net/i40e/base: fix headers to match functions
Fix several kernel-doc warnings when building with W=1. These changes
are only to comments.
Fixes: 8db9e2a1b232 ("i40e: base driver")
Fixes: 842ea1996335 ("i40e/base: save link module type")
Fixes: fd72a2284a89 ("i40e/base: support LED blinking with new PHY")
Fixes: 788fc17b2dec ("i40e/base: support proxy config for X722")
Cc: sta...@dpdk.org
Signed-off-by: Jesse Brandeburg
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_common.c | 10 +-
drivers/net/i40e/base/i40e_dcb.c | 2 +-
drivers/net/i40e/base/i40e_lan_hmc.c | 2 +-
drivers/net/i40e/base/i40e_nvm.c | 2 +-
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_common.c
b/drivers/net/i40e/base/i40e_common.c
index e077bf8fd3..3f3896aea4 100644
--- a/drivers/net/i40e/base/i40e_common.c
+++ b/drivers/net/i40e/base/i40e_common.c
@@ -2678,7 +2678,7 @@ enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct
i40e_hw *hw,
}
/**
- * i40e_get_vsi_params - get VSI configuration info
+ * i40e_aq_get_vsi_params - get VSI configuration info
* @hw: pointer to the hw struct
* @vsi_ctx: pointer to a vsi context struct
* @cmd_details: pointer to command details structure or NULL
@@ -2939,7 +2939,7 @@ enum i40e_status_code i40e_get_link_status(struct i40e_hw
*hw, bool *link_up)
}
/**
- * i40e_updatelink_status - update status of the HW network link
+ * i40e_update_link_info - update status of the HW network link
* @hw: pointer to the hw struct
**/
enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
@@ -4831,7 +4831,7 @@ enum i40e_status_code i40e_aq_del_udp_tunnel(struct
i40e_hw *hw, u8 index,
}
/**
- * i40e_aq_get_switch_resource_alloc (0x0204)
+ * i40e_aq_get_switch_resource_alloc - command (0x0204) to get allocations
* @hw: pointer to the hw struct
* @num_entries: pointer to u8 to store the number of resource entries returned
* @buf: pointer to a user supplied buffer. This buffer must be large enough
@@ -6978,7 +6978,7 @@ u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
}
/**
- * i40e_blink_phy_led
+ * i40e_blink_phy_link_led
* @hw: pointer to the HW structure
* @time: time how long led will blinks in secs
* @interval: gap between LED on and off in msecs
@@ -7825,7 +7825,7 @@ enum i40e_status_code i40e_aq_set_arp_proxy_config(struct
i40e_hw *hw,
}
/**
- * i40e_aq_opc_set_ns_proxy_table_entry
+ * i40e_aq_set_ns_proxy_table_entry
* @hw: pointer to the HW structure
* @ns_proxy_table_entry: pointer to NS table entry command struct
* @cmd_details: pointer to command details
diff --git a/drivers/net/i40e/base/i40e_dcb.c b/drivers/net/i40e/base/i40e_dcb.c
index 27b52bc365..8f9b7e823f 100644
--- a/drivers/net/i40e/base/i40e_dcb.c
+++ b/drivers/net/i40e/base/i40e_dcb.c
@@ -235,7 +235,7 @@ static void i40e_parse_ieee_app_tlv(struct
i40e_lldp_org_tlv *tlv,
}
/**
- * i40e_parse_ieee_etsrec_tlv
+ * i40e_parse_ieee_tlv
* @tlv: IEEE 802.1Qaz TLV
* @dcbcfg: Local store to update ETS REC data
*
diff --git a/drivers/net/i40e/base/i40e_lan_hmc.c
b/drivers/net/i40e/base/i40e_lan_hmc.c
index d3969396f0..d3bd683ff3 100644
--- a/drivers/net/i40e/base/i40e_lan_hmc.c
+++ b/drivers/net/i40e/base/i40e_lan_hmc.c
@@ -516,7 +516,7 @@ enum i40e_status_code i40e_configure_lan_hmc(struct i40e_hw
*hw,
}
/**
- * i40e_delete_hmc_object - remove hmc objects
+ * i40e_delete_lan_hmc_object - remove hmc objects
* @hw: pointer to the HW structure
* @info: pointer to i40e_hmc_delete_obj_info struct
*
diff --git a/drivers/net/i40e/base/i40e_nvm.c b/drivers/net/i40e/base/i40e_nvm.c
index 561ed21136..67e58cc195 100644
--- a/drivers/net/i40e/base/i40e_nvm.c
+++ b/drivers/net/i40e/base/i40e_nvm.c
@@ -7,7 +7,7 @@
#include "i40e_prototype.h"
/**
- * i40e_init_nvm_ops - Initialize NVM function pointers
+ * i40e_init_nvm - Initialize NVM function pointers
* @hw: pointer to the HW structure
*
* Setup the function pointers and the NVM info structure. Should be called
--
2.25.1
[dpdk-dev] [PATCH v3 13/15] net/i40e/base: fix potentially uninitialized variables in NVM code
The status of i40e_read_nvm_word is not checked, so variables set
from this function could be used uninitialized. In this case, preserve
the existing flow that does not block initialization by initializing
these values from the start.
Fixes: 8d6c51fcd24b ("i40e/base: get OEM version")
Fixes: 2db70574247b ("net/i40e/base: limit PF/VF specific code to that driver
only")
Cc: sta...@dpdk.org
Signed-off-by: Christopher Pau
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_adminq.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq.c
b/drivers/net/i40e/base/i40e_adminq.c
index eafacbdbec..d27ccde29a 100644
--- a/drivers/net/i40e/base/i40e_adminq.c
+++ b/drivers/net/i40e/base/i40e_adminq.c
@@ -648,8 +648,10 @@ enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw)
{
struct i40e_adminq_info *aq = &hw->aq;
enum i40e_status_code ret_code;
- u16 cfg_ptr, oem_hi, oem_lo;
- u16 eetrack_lo, eetrack_hi;
+ u16 oem_hi = 0, oem_lo = 0;
+ u16 eetrack_hi = 0;
+ u16 eetrack_lo = 0;
+ u16 cfg_ptr = 0;
int retry = 0;
/* verify input for valid configuration */
--
2.25.1
[dpdk-dev] [PATCH v3 14/15] net/i40e/base: fix checksum is used before return value is checked
The variable checksum from i40e_calc_nvm_checksum is used before return
value is checked. Fix this logic.
Fixes: 8db9e2a1b232 ("i40e: base driver")
Fixes: 3ed6c3246f43 ("i40e/base: handle AQ timeout when releasing NVM")
Cc: sta...@dpdk.org
Signed-off-by: Christopher Pau
Signed-off-by: Robin Zhang
---
drivers/net/i40e/base/i40e_nvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_nvm.c b/drivers/net/i40e/base/i40e_nvm.c
index 67e58cc195..f385042601 100644
--- a/drivers/net/i40e/base/i40e_nvm.c
+++ b/drivers/net/i40e/base/i40e_nvm.c
@@ -755,10 +755,11 @@ enum i40e_status_code i40e_update_nvm_checksum(struct
i40e_hw *hw)
DEBUGFUNC("i40e_update_nvm_checksum");
ret_code = i40e_calc_nvm_checksum(hw, &checksum);
- le_sum = CPU_TO_LE16(checksum);
- if (ret_code == I40E_SUCCESS)
+ if (ret_code == I40E_SUCCESS) {
+ le_sum = CPU_TO_LE16(checksum);
ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
1, &le_sum, true);
+ }
return ret_code;
}
--
2.25.1
[dpdk-dev] [PATCH v3 15/15] net/i40e/base: update version in readme
Update base code version in README. Signed-off-by: Robin Zhang --- drivers/net/i40e/base/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/i40e/base/README b/drivers/net/i40e/base/README index 6af2993116..c84764005b 100644 --- a/drivers/net/i40e/base/README +++ b/drivers/net/i40e/base/README @@ -6,7 +6,7 @@ Intel® I40E driver == This directory contains source code of FreeBSD i40e driver of version -cid-i40e.2020.08.27.tar.gz released by the team which develops +cid-i40e.2021.04.29.tar.gz released by the team which develops basic drivers for any i40e NIC. The directory of base/ contains the original source package. This driver is valid for the product(s) listed below -- 2.25.1
[dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function invalid
i40e can support following rss hash function types: default/toeplitz,
symmetric toeplitz, and simple_xor. However, when filter engine parses
pattern action, it only supports symmetric toeplitz & default.
Add simple_xor and toeplitz hash functions support when parsing pattern
action.
Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow")
Cc: sta...@dpdk.org
Signed-off-by: Steve Yang
---
v3:
- add Cc stable line.
v2:
- add the fix line.
- support simple_xor and toeplitz hash functions explicitly.
drivers/net/i40e/i40e_hash.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/net/i40e/i40e_hash.c b/drivers/net/i40e/i40e_hash.c
index b1cb24f437..0cef21c88f 100644
--- a/drivers/net/i40e/i40e_hash.c
+++ b/drivers/net/i40e/i40e_hash.c
@@ -1105,13 +1105,21 @@ i40e_hash_parse_pattern_act(const struct rte_eth_dev
*dev,
NULL,
"RSS Queues not supported when
pattern specified");
- if (rss_act->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
+ switch (rss_act->func) {
+ case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ:
rss_conf->symmetric_enable = true;
- else if (rss_act->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
- return rte_flow_error_set(error, -EINVAL,
- RTE_FLOW_ERROR_TYPE_ACTION_CONF,
- NULL,
- "Only symmetric TOEPLITZ supported
when pattern specified");
+ break;
+ case RTE_ETH_HASH_FUNCTION_DEFAULT:
+ case RTE_ETH_HASH_FUNCTION_TOEPLITZ:
+ case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR:
+ break;
+ default:
+ return rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ACTION_CONF,
+ NULL,
+ "RSS hash function not supported "
+ "when pattern specified");
+ }
if (!i40e_hash_validate_rss_types(rss_act->types))
return rte_flow_error_set(error, EINVAL,
--
2.27.0
Re: [dpdk-dev] [PATCH v4 1/2] devargs: add common key definition
13/06/2021 14:58, Xueming Li:
> --- a/lib/eal/include/rte_devargs.h
> +++ b/lib/eal/include/rte_devargs.h
> @@ -25,6 +25,10 @@ extern "C" {
> #include
> #include
>
> +#define RTE_DEVARGS_KEY_BUS "bus"
> +#define RTE_DEVARGS_KEY_CLASS "class"
> +#define RTE_DEVARGS_KEY_DRIVER "driver"
These macros must be documented as part of the API.
It must be said how it is used.
Re: [dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function invalid
> -Original Message-
> From: dev On Behalf Of Steve Yang
> Sent: Monday, June 21, 2021 4:04 PM
> To: dev@dpdk.org
> Cc: Xing, Beilei ; Yang, SteveX
> ; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function invalid
>
> i40e can support following rss hash function types: default/toeplitz,
> symmetric toeplitz, and simple_xor. However, when filter engine parses
> pattern action, it only supports symmetric toeplitz & default.
>
> Add simple_xor and toeplitz hash functions support when parsing pattern
> action.
>
> Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Steve Yang
> ---
> v3:
> - add Cc stable line.
> v2:
> - add the fix line.
> - support simple_xor and toeplitz hash functions explicitly.
>
> drivers/net/i40e/i40e_hash.c | 20 ++--
> 1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_hash.c b/drivers/net/i40e/i40e_hash.c
> index b1cb24f437..0cef21c88f 100644
> --- a/drivers/net/i40e/i40e_hash.c
> +++ b/drivers/net/i40e/i40e_hash.c
> @@ -1105,13 +1105,21 @@ i40e_hash_parse_pattern_act(const struct
> rte_eth_dev *dev,
> NULL,
> "RSS Queues not supported when
> pattern specified");
>
> - if (rss_act->func ==
> RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
> + switch (rss_act->func) {
> + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ:
> rss_conf->symmetric_enable = true;
> - else if (rss_act->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
> - return rte_flow_error_set(error, -EINVAL,
> -
> RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> - NULL,
> - "Only symmetric TOEPLITZ
> supported when pattern specified");
> + break;
> + case RTE_ETH_HASH_FUNCTION_DEFAULT:
> + case RTE_ETH_HASH_FUNCTION_TOEPLITZ:
> + case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR:
> + break;
> + default:
> + return rte_flow_error_set(error, EINVAL,
> + RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> + NULL,
> + "RSS hash function not supported "
> + "when pattern specified");
> + }
>
> if (!i40e_hash_validate_rss_types(rss_act->types))
> return rte_flow_error_set(error, EINVAL,
> --
> 2.27.0
Acked-by: Beilei Xing
Re: [dpdk-dev] [PATCH v6 0/3] support AVF RSS and FDIR for GTPoGRE packet
> -Original Message- > From: Liu, Lingyu > Sent: Monday, June 21, 2021 10:23 PM > To: dev@dpdk.org; Zhang, Qi Z ; Xing, Beilei > ; Wu, Jingjing > Cc: Guo, Junfeng ; Liu, Lingyu > Subject: [PATCH v6 0/3] support AVF RSS and FDIR for GTPoGRE packet > > Support AVF RSS and FDIR for GTPoGRE packet. > > Lingyu Liu (3): > net/iavf: support flow pattern for GTPoGRE > net/iavf: support AVF FDIR for GTPoGRE tunnel packet > net/iavf: support AVF RSS for GTPoGRE packet > --- > V6 change: > - rebase and remove GRE pattern parse in FDIR > V5 change: > - refine protocol header for two tunnels case > - move IPV6 patterns to the IPV6 block in pattern list > V4 change: > - add RTE_FLOW_ITEM_TYPE_GRE in hash parse pattern function > V3 change: > - add GTPU extension header pattern > > drivers/net/iavf/iavf_fdir.c | 48 +++ > drivers/net/iavf/iavf_generic_flow.c | 600 +++ > drivers/net/iavf/iavf_generic_flow.h | 80 > drivers/net/iavf/iavf_hash.c | 142 +-- > 4 files changed, 846 insertions(+), 24 deletions(-) > > -- > 2.25.1 Acked-by: Qi Zhang Applied to dpdk-next-net-intel. Thanks Qi
Re: [dpdk-dev] [PATCH v3 19/20] net/sfc: support flow action COUNT in transfer rules
On Fri, Jun 18, 2021 at 3:41 PM Andrew Rybchenko
wrote:
> diff --git a/drivers/net/sfc/meson.build b/drivers/net/sfc/meson.build
> index f8880f740a..32b58e3d76 100644
> --- a/drivers/net/sfc/meson.build
> +++ b/drivers/net/sfc/meson.build
> @@ -39,6 +39,16 @@ foreach flag: extra_flags
> endif
> endforeach
>
> +# for clang 32-bit compiles we need libatomic for 64-bit atomic ops
> +if cc.get_id() == 'clang' and dpdk_conf.get('RTE_ARCH_64') == false
> +ext_deps += cc.find_library('atomic')
> +endif
I don't think this block is needed.
The atomic library is globally required in config/meson.build for the
clang + 32bits case.
> +
> +# for gcc compiles we need -latomic for 128-bit atomic ops
> +if cc.get_id() == 'gcc'
> +ext_deps += cc.find_library('atomic')
> +endif
> +
This patch breaks compilation on rhel/fedora (most failures in UNH for
this series are linked to this issue) when the libatomic rpm is not
installed.
ninja: Entering directory `/home/dmarchan/builds/build-gcc-static'
[1/18] Linking target drivers/librte_net_sfc.so.21.3
FAILED: drivers/librte_net_sfc.so.21.3
gcc -o drivers/librte_net_sfc.so.21.3
drivers/librte_net_sfc.so.21.3.p/meson-generated_.._rte_net_sfc.pmd.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ethdev.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_kvargs.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_mcdi.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_sriov.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_intr.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ev.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_port.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_rx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_tx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_tso.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_filter.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_switch.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_mae.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_mae_counter.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_flow.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_dp.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ef10_rx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ef10_essb_rx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ef10_tx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ef100_rx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_ef100_tx.c.o
drivers/libtmp_rte_net_sfc.a.p/net_sfc_sfc_service.c.o
-I/home/dmarchan/intel-ipsec-mb/install/include
-L/home/dmarchan/intel-ipsec-mb/install/lib -Wl,--as-needed
-Wl,--no-undefined -shared -fPIC -Wl,--start-group
-Wl,-soname,librte_net_sfc.so.21 -Wl,--no-as-needed -pthread -lm -ldl
-lnuma -lfdt lib/librte_ethdev.so.21.3 lib/librte_eal.so.21.3
lib/librte_kvargs.so.21.3 lib/librte_telemetry.so.21.3
lib/librte_net.so.21.3 lib/librte_mbuf.so.21.3
lib/librte_mempool.so.21.3 lib/librte_ring.so.21.3
lib/librte_meter.so.21.3 drivers/librte_bus_pci.so.21.3
lib/librte_pci.so.21.3 drivers/librte_bus_vdev.so.21.3
drivers/librte_common_sfc_efx.so.21.3
-Wl,--version-script=/home/dmarchan/dpdk/drivers/net/sfc/version.map
/usr/lib/gcc/x86_64-redhat-linux/10/libatomic.so /usr/lib64/libbsd.so
-Wl,--end-group '-Wl,-rpath,$ORIGIN/../lib:$ORIGIN/'
-Wl,-rpath-link,/home/dmarchan/builds/build-gcc-static/lib
-Wl,-rpath-link,/home/dmarchan/builds/build-gcc-static/drivers
/usr/bin/ld: cannot find /usr/lib64/libatomic.so.1.2.0
collect2: error: ld returned 1 exit status
It seems meson related.
I do see:
Library atomic found: YES
Message: drivers/net/sfc: Defining dependency "net_sfc"
But looking at /home/dmarchan/build/build-gcc-static/meson-logs/meson-log.txt:
"""
Running compile:
Working directory:
/home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z
Command line: gcc -L/home/dmarchan/intel-ipsec-mb/install/lib
-I/home/dmarchan/intel-ipsec-mb/install/include
/home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z/testfile.c
-o /home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z/output.exe
-pipe -D_FILE_OFFSET_BITS=64 -O0 -Wl,--start-group -latomic
-Wl,--end-group -Wl,--allow-shlib-undefined
Code:
int main(void) { return 0; }
Compiler stdout:
Compiler stderr:
/usr/bin/ld: cannot find /usr/lib64/libatomic.so.1.2.0
collect2: error: ld returned 1 exit status
Library atomic found: YES
"""
And:
[dmarchan@wsfd-netdev66 dpdk]$ cat
/usr/lib/gcc/x86_64-redhat-linux/10/libatomic.so
INPUT ( /usr/lib64/libatomic.so.1.2.0 )
[dmarchan@wsfd-netdev66 dpdk]$ file /usr/lib64/libatomic.so.1.2.0
/usr/lib64/libatomic.so.1.2.0: cannot open
`/usr/lib64/libatomic.so.1.2.0' (No such file or directory)
[dmarchan@wsfd-netdev66 dpdk]$ meson --version
0.55.3
--
David Marchand
Re: [dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function invalid
> -Original Message-
> From: dev On Behalf Of Xing, Beilei
> Sent: Monday, June 21, 2021 4:19 PM
> To: Yang, SteveX ; dev@dpdk.org
> Cc: Yang, SteveX ; sta...@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function invalid
>
>
>
> > -Original Message-
> > From: dev On Behalf Of Steve Yang
> > Sent: Monday, June 21, 2021 4:04 PM
> > To: dev@dpdk.org
> > Cc: Xing, Beilei ; Yang, SteveX
> > ; sta...@dpdk.org
> > Subject: [dpdk-dev] [PATCH v3] net/i40e: fix set rss hash function
> > invalid
> >
> > i40e can support following rss hash function types: default/toeplitz,
> > symmetric toeplitz, and simple_xor. However, when filter engine parses
> > pattern action, it only supports symmetric toeplitz & default.
> >
> > Add simple_xor and toeplitz hash functions support when parsing
> > pattern action.
> >
> > Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow")
> > Cc: sta...@dpdk.org
> >
> > Signed-off-by: Steve Yang
> > ---
> > v3:
> > - add Cc stable line.
> > v2:
> > - add the fix line.
> > - support simple_xor and toeplitz hash functions explicitly.
> >
> > drivers/net/i40e/i40e_hash.c | 20 ++--
> > 1 file changed, 14 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/net/i40e/i40e_hash.c
> > b/drivers/net/i40e/i40e_hash.c index b1cb24f437..0cef21c88f 100644
> > --- a/drivers/net/i40e/i40e_hash.c
> > +++ b/drivers/net/i40e/i40e_hash.c
> > @@ -1105,13 +1105,21 @@ i40e_hash_parse_pattern_act(const struct
> > rte_eth_dev *dev,
> > NULL,
> > "RSS Queues not supported when pattern
> specified");
> >
> > - if (rss_act->func ==
> > RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
> > + switch (rss_act->func) {
> > + case RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ:
> > rss_conf->symmetric_enable = true;
> > - else if (rss_act->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
> > - return rte_flow_error_set(error, -EINVAL,
> > -
> > RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> > - NULL,
> > - "Only symmetric TOEPLITZ
> > supported when pattern specified");
> > + break;
> > + case RTE_ETH_HASH_FUNCTION_DEFAULT:
> > + case RTE_ETH_HASH_FUNCTION_TOEPLITZ:
> > + case RTE_ETH_HASH_FUNCTION_SIMPLE_XOR:
> > + break;
> > + default:
> > + return rte_flow_error_set(error, EINVAL,
> > + RTE_FLOW_ERROR_TYPE_ACTION_CONF,
> > + NULL,
> > + "RSS hash function not supported "
> > + "when pattern specified");
> > + }
> >
> > if (!i40e_hash_validate_rss_types(rss_act->types))
> > return rte_flow_error_set(error, EINVAL,
> > --
> > 2.27.0
>
> Acked-by: Beilei Xing
Applied to dpdk-next-net-intel.
Thanks
Qi
Re: [dpdk-dev] [PATCH] net/e1000: fix nic ops function was no initialized in secondary process
发件人: Wang, Haiyue
发送时间: 2021年6月21日星期一 15:31
收件人: Tengfei Zhang
抄送: dev@dpdk.org; Zhang, Qi Z; Lin, Xueqin
主题: RE: [PATCH] net/e1000: fix nic ops function was no initialized in secondary
process
> -Original Message-
> From: Tengfei Zhang
> Sent: Saturday, June 19, 2021 01:27
> To: Wang, Haiyue
> Cc: dev@dpdk.org; Tengfei Zhang
> Subject: [PATCH] net/e1000: fix nic ops function was no initialized in
> secondary process
>
> 'e1000_setup_init_funcs' was not called in secondary process,
> it initialize mac,phy,nvm ops.
> when secondary process get link status,it will coredump.
Thanks, Tengfei.
Since primary / secondary is so complicated, AFAIK, the control path is in
primary, the secondary is mainly for rx/tx ops officially, like new Intel
ice PMD:
if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
ice_set_rx_function(dev);
ice_set_tx_function(dev);
return 0;
}
So you can keep your patch as private for special secondary usage. ;-)
>
> Signed-off-by: Tengfei Zhang
> ---
> drivers/net/e1000/em_ethdev.c | 1 +
> drivers/net/e1000/igb_ethdev.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c
> index a0ca371b02..cd5faa4228 100644
> --- a/drivers/net/e1000/em_ethdev.c
> +++ b/drivers/net/e1000/em_ethdev.c
> @@ -258,6 +258,7 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev)
> * has already done this work. Only check we don't need a different
> * RX function */
>if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
>if (eth_dev->data->scattered_rx)
>eth_dev->rx_pkt_burst =
>(eth_rx_burst_t)ð_em_recv_scattered_pkts;
> diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
> index 10ee0f3341..7d9d60497d 100644
> --- a/drivers/net/e1000/igb_ethdev.c
> +++ b/drivers/net/e1000/igb_ethdev.c
> @@ -737,6 +737,7 @@ eth_igb_dev_init(struct rte_eth_dev *eth_dev)
> * has already done this work. Only check we don't need a different
> * RX function */
>if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
>if (eth_dev->data->scattered_rx)
>eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
>return 0;
> @@ -931,6 +932,7 @@ eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
> * has already done this work. Only check we don't need a different
> * RX function */
>if (rte_eal_process_type() != RTE_PROC_PRIMARY){
> + e1000_setup_init_funcs(hw, TRUE);
>if (eth_dev->data->scattered_rx)
>eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
>return 0;
> --
> 2.26.2
this issue does not appear in ice, i40e, vmxnet3 PMD drivers. Only in e1000 ,
ixgbe drivers.
Ice pmd driver gets link status by read reg directly.
I agree with what you said "primary, the secondary is mainly for rx/tx ops
officially".
My opinion is the "set actions" shouldn't called in secondary process, but "get
actions" was very common operation, they shouldn't be banned.
Thanks for your reply
Re: [dpdk-dev] [PATCH] net/i40e: fix L2 payload RSS mask input set
> -Original Message-
> From: Zhang, AlvinX
> Sent: Friday, June 18, 2021 4:38 PM
> To: Xing, Beilei
> Cc: dev@dpdk.org; Zhang, AlvinX ;
> sta...@dpdk.org
> Subject: [PATCH] net/i40e: fix L2 payload RSS mask input set
>
> Allow VLAN tag being added to L2 payload packet type RSS input set.
>
> Fixes: ef4c16fd9148 ("net/i40e: refactor RSS flow")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Alvin Zhang
> ---
> drivers/net/i40e/i40e_hash.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/i40e/i40e_hash.c b/drivers/net/i40e/i40e_hash.c
> index b1cb24f..722edc9 100644
> --- a/drivers/net/i40e/i40e_hash.c
> +++ b/drivers/net/i40e/i40e_hash.c
> @@ -201,11 +201,11 @@ struct i40e_hash_match_pattern { #define
> I40E_HASH_MAP_CUS_PATTERN(pattern, rss_mask, cus_pctype) { \
> pattern, rss_mask, true, cus_pctype }
>
> -#define I40E_HASH_L2_RSS_MASK(ETH_RSS_ETH |
> ETH_RSS_L2_SRC_ONLY | \
> +#define I40E_HASH_L2_RSS_MASK(ETH_RSS_VLAN |
> ETH_RSS_ETH | \
> + ETH_RSS_L2_SRC_ONLY | \
> ETH_RSS_L2_DST_ONLY)
>
> #define I40E_HASH_L23_RSS_MASK (I40E_HASH_L2_RSS_MASK |
> \
> - ETH_RSS_VLAN | \
> ETH_RSS_L3_SRC_ONLY | \
> ETH_RSS_L3_DST_ONLY)
>
> --
> 1.8.3.1
Acked-by: Beilei Xing
Re: [dpdk-dev] [PATCH v2 00/32] add support for baseband phy
On Tue, Jun 15, 2021 at 4:33 PM Tomasz Duszynski wrote: > > This series adds initial support for baseband PHY available on SOCs > belonging to Fusion family. BPHY is a hardware block comprising > accelerators and DSPs specifically tailored for 5G/LTE inline usecases. > > This series introduces two rawdev PMDs along with low level common code. > > CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to > BPHY via standard enqueue/dequeue operations. > > BPHY PMD provides an out-of-band access to PCI device BARs and a set of > experimental APIs allowing one to setup custom IRQs handlers. This > functionality is backed by kernel module using ioctl() mechanism. Series > has nothing to do with 5G/LTE baseband protocol processing. This series looks good to me. Feel free to add my reviewed by for the series after fix the following 1) Typo diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst -``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal loobback while the latter +``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal loopback while the latter 2) checkpatch WARNING:LONG_LINE: line length of 85 exceeds 80 columns #88: FILE: drivers/common/cnxk/roc_bphy_cgx.c:77: + if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) == ETH_EVT_ASYNC && 3) In the release notes, the following items can be removed. + Added new Baseband phy PMD which provides means for configuring baseband hardware via + standard rawdev enq/deq operations. Baseband phy is a hardware subsystem accelerating + 5G/LTE related tasks. + + Both BPHY and BPHY CGX/RPM drivers are related hence kept together to ease maintenance. > > v2: > - change some errors to more relevant ones (-EINVAL/-ENODEV) > - fix MAINTAINERS styling issues > - fix dpdk-devbind.py > - fix meson.build styling issues > - fix warning related to possibly uninitialized scr0 variable > - fix warning releated to unused function > - improve documentation > - improve enums items naming > - spread documentation across relevant patches > > Tomasz Duszynski (28): > common/cnxk: add bphy cgx/rpm initialization and cleanup > common/cnxk: support for communication with atf > common/cnxk: support for getting link information > common/cnxk: support for changing internal loopback > common/cnxk: support for changing ptp mode > common/cnxk: support for setting link mode > common/cnxk: support for changing link state > common/cnxk: support for lmac start/stop > raw/cnxk_bphy: add bphy cgx/rpm skeleton driver > raw/cnxk_bphy: support for reading queue configuration > raw/cnxk_bphy: support for reading queue count > raw/cnxk_bphy: support for enqueue operation > raw/cnxk_bphy: support for dequeue operation > raw/cnxk_bphy: support for performing selftest > common/cnxk: support for device init and fini > common/cnxk: support for baseband PHY irq setup > common/cnxk: support for checking irq availability > common/cnxk: support for retrieving irq stack > common/cnxk: support for removing irq stack > common/cnxk: support for setting bphy irq handler > common/cnxk: support for clearing bphy irq handler > common/cnxk: support for registering bphy irq > raw/cnxk_bphy: add baseband PHY skeleton driver > raw/cnxk_bphy: support for reading bphy queue configuration > raw/cnxk_bphy: support for reading bphy queue count > raw/cnxk_bphy: support for bphy enqueue operation > raw/cnxk_bphy: support for bphy dequeue operation > raw/cnxk_bphy: support for interrupt init and cleanup > raw/cnxk_bphy: support for reading number of bphy irqs > raw/cnxk_bphy: support for retrieving bphy device memory > raw/cnxk_bphy: support for registering bphy irq handlers > raw/cnxk_bphy: support for bphy selftest > > MAINTAINERS| 7 +- > doc/guides/rawdevs/cnxk_bphy.rst | 154 > doc/guides/rawdevs/index.rst | 1 + > doc/guides/rel_notes/release_21_08.rst | 13 + > drivers/common/cnxk/meson.build| 3 + > drivers/common/cnxk/roc_api.h | 7 + > drivers/common/cnxk/roc_bphy.c | 40 ++ > drivers/common/cnxk/roc_bphy.h | 17 + > drivers/common/cnxk/roc_bphy_cgx.c | 396 +++ > drivers/common/cnxk/roc_bphy_cgx.h | 120 ++ > drivers/common/cnxk/roc_bphy_cgx_priv.h| 131 +++ > drivers/common/cnxk/roc_bphy_irq.c | 422 + > drivers/common/cnxk/roc_bphy_irq.h | 49 +++ > drivers/common/cnxk/roc_idev.c | 1 + > drivers/common/cnxk/roc_idev_priv.h| 2 + > drivers/common/cnxk/roc_io.h | 9 + > drivers/common/cnxk/roc_io_generic.h | 5 + > drivers/common/cnxk/roc_priv.h | 3 + > drivers/common/cnxk/version.map| 22 ++ > drivers/raw/cnxk_bphy/cnxk_bphy.c | 329 > drivers/raw/cnxk_bph
Re: [dpdk-dev] [EXT] Re: [RFC 0/7] crypto/ipsec_mb: introduce ipsec_mb framework
Hi Akhil, We targeted this patchset for 21.11. Just want to know everybody's thoughts before submitting V1. Regards, Fan > -Original Message- > From: Akhil Goyal > Sent: Friday, June 18, 2021 5:05 PM > To: David Marchand ; Bronowski, PiotrX > > Cc: dev ; Zhang, Roy Fan ; > Thomas Monjalon ; Yigit, Ferruh > ; Doherty, Declan > Subject: RE: [EXT] Re: [dpdk-dev] [RFC 0/7] crypto/ipsec_mb: introduce > ipsec_mb framework > > Hi David, > > Hello, > > > > On Fri, Jun 18, 2021 at 2:18 PM pbronowx > > wrote: > > > > > > This set of patches introduces the new framework making all common > code > > of > > > SW crypto PMDs implementations build on top of intel-ipsec-mb library > > > sharable, also helps to reduce future effort on the code maintenance and > > > future updates. It also moves all SW PMD implementations specific > details > > > into single file located in crypto/ipsec_mb folder. > > > > As you described it, this framework should go to drivers/common/. > > This patch set is moving a lot of SW crypto drivers into a single driver > In drivers/crypto/ipsec_mb. > This should be part of drivers/crypto only. > But this patchset is a bit late as V1 deadline is already crossed for 21.08. > > Regards, > Akhil
[dpdk-dev] [PATCH v5] vhost: check header for legacy dequeue offload
When parsing the virtio net header and packet header for dequeue offload,
we need to perform sanity check on the packet header to ensure:
- No out-of-boundary memory access.
- The packet header and virtio_net header are valid and aligned.
Fixes: d0cf91303d73 ("vhost: add Tx offload capabilities")
Cc: sta...@dpdk.org
Signed-off-by: Xiao Wang
---
v5:
- Redefine the function parse_ethernet() to parse_headers(). (David)
- Use mbuf helpers e.g. rte_pktmbuf_data_len() and rte_pktmbuf_mtod_offset().
(David)
- Reset mbuf l2_len, l3_len and ol_flags when detecting anything invalid.
(David)
- Improve some check conditions. (David)
- Move the data_len check for L4 header into parse_headers(), in order to avoid
duplicated checks in CSUM and GSO.
- Use uint8_t instead of uint16_t for l4_proto variable.
- Detect more invalid corner cases.
v4:
- Rebase on head of main branch.
- Allow empty L4 payload in GSO.
v3:
- Check data_len before calling rte_pktmbuf_mtod. (David)
v2:
- Allow empty L4 payload for cksum offload. (Konstantin)
---
lib/vhost/virtio_net.c | 117 +
1 file changed, 89 insertions(+), 28 deletions(-)
diff --git a/lib/vhost/virtio_net.c b/lib/vhost/virtio_net.c
index 8da8a86a10..fb21b56558 100644
--- a/lib/vhost/virtio_net.c
+++ b/lib/vhost/virtio_net.c
@@ -2259,14 +2259,17 @@ virtio_net_with_host_offload(struct virtio_net *dev)
return false;
}
-static void
-parse_ethernet(struct rte_mbuf *m, uint16_t *l4_proto, void **l4_hdr)
+static int
+parse_headers(struct rte_mbuf *m, uint8_t *l4_proto)
{
struct rte_ipv4_hdr *ipv4_hdr;
struct rte_ipv6_hdr *ipv6_hdr;
- void *l3_hdr = NULL;
struct rte_ether_hdr *eth_hdr;
uint16_t ethertype;
+ uint16_t data_len = rte_pktmbuf_data_len(m);
+
+ if (data_len < sizeof(struct rte_ether_hdr))
+ return -EINVAL;
eth_hdr = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
@@ -2274,6 +2277,10 @@ parse_ethernet(struct rte_mbuf *m, uint16_t *l4_proto,
void **l4_hdr)
ethertype = rte_be_to_cpu_16(eth_hdr->ether_type);
if (ethertype == RTE_ETHER_TYPE_VLAN) {
+ if (data_len < sizeof(struct rte_ether_hdr) +
+ sizeof(struct rte_vlan_hdr))
+ goto error;
+
struct rte_vlan_hdr *vlan_hdr =
(struct rte_vlan_hdr *)(eth_hdr + 1);
@@ -2281,70 +2288,118 @@ parse_ethernet(struct rte_mbuf *m, uint16_t *l4_proto,
void **l4_hdr)
ethertype = rte_be_to_cpu_16(vlan_hdr->eth_proto);
}
- l3_hdr = (char *)eth_hdr + m->l2_len;
-
switch (ethertype) {
case RTE_ETHER_TYPE_IPV4:
- ipv4_hdr = l3_hdr;
- *l4_proto = ipv4_hdr->next_proto_id;
+ if (data_len < m->l2_len + sizeof(struct rte_ipv4_hdr))
+ goto error;
+ ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *,
+ m->l2_len);
m->l3_len = rte_ipv4_hdr_len(ipv4_hdr);
- *l4_hdr = (char *)l3_hdr + m->l3_len;
+ if (data_len < m->l2_len + m->l3_len)
+ goto error;
m->ol_flags |= PKT_TX_IPV4;
+ *l4_proto = ipv4_hdr->next_proto_id;
break;
case RTE_ETHER_TYPE_IPV6:
- ipv6_hdr = l3_hdr;
- *l4_proto = ipv6_hdr->proto;
+ if (data_len < m->l2_len + sizeof(struct rte_ipv6_hdr))
+ goto error;
+ ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv6_hdr *,
+ m->l2_len);
m->l3_len = sizeof(struct rte_ipv6_hdr);
- *l4_hdr = (char *)l3_hdr + m->l3_len;
m->ol_flags |= PKT_TX_IPV6;
+ *l4_proto = ipv6_hdr->proto;
break;
default:
- m->l3_len = 0;
- *l4_proto = 0;
- *l4_hdr = NULL;
+ /* a valid L3 header is needed for further L4 parsing */
+ goto error;
+ }
+
+ /* both CSUM and GSO need a valid L4 header */
+ switch (*l4_proto) {
+ case IPPROTO_TCP:
+ if (data_len < m->l2_len + m->l3_len +
+ sizeof(struct rte_tcp_hdr))
+ goto error;
+ break;
+ case IPPROTO_UDP:
+ if (data_len < m->l2_len + m->l3_len +
+ sizeof(struct rte_udp_hdr))
+ goto error;
break;
+ case IPPROTO_SCTP:
+ if (data_len < m->l2_len + m->l3_len +
+ sizeof(struct rte_sctp_hdr))
+ goto error;
+ break;
+ default:
+ goto error;
}
+
+ return 0;
+
+error:
+ m->l2_len = 0;
+ m->l3_len = 0;
+ m->ol_flags
Re: [dpdk-dev] [EXT] Re: [PATCH 4/4] drivers/net/enetfec: add enqueue and dequeue support
Hi, I will be reworking on the 'enetfec' driver. It may take time to send the V2 patch. Thanks & Regards, Apeksha > -Original Message- > From: Andrew Rybchenko > Sent: Tuesday, June 8, 2021 7:12 PM > To: Apeksha Gupta ; ferruh.yi...@intel.com > Cc: dev@dpdk.org; Hemant Agrawal ; Sachin > Saxena > Subject: [EXT] Re: [dpdk-dev] [PATCH 4/4] drivers/net/enetfec: add enqueue and > dequeue support > > Caution: EXT Email > > On 4/30/21 7:34 AM, Apeksha Gupta wrote: > > This patch supported checksum offloads and add burst enqueue and > > dequeue operations to the enetfec PMD. > > > > Loopback mode is added, compile time flag 'ENETFEC_LOOPBACK' is > > used to enable this feature. By default loopback mode is disabled. > > Basic features added like promiscuous enable, basic stats. > > Please, apply style fixes from the previous patches > to the patch as well. > > > > > Signed-off-by: Sachin Saxena > > Signed-off-by: Apeksha Gupta > > --- > > doc/guides/nics/enetfec.rst | 4 + > > doc/guides/nics/features/enetfec.ini | 5 + > > drivers/net/enetfec/enet_ethdev.c| 212 +++- > > drivers/net/enetfec/enet_rxtx.c | 499 +++ > > 4 files changed, 719 insertions(+), 1 deletion(-) > > create mode 100644 drivers/net/enetfec/enet_rxtx.c > > > > diff --git a/doc/guides/nics/enetfec.rst b/doc/guides/nics/enetfec.rst > > index 10f495fb9..adbb52392 100644 > > --- a/doc/guides/nics/enetfec.rst > > +++ b/doc/guides/nics/enetfec.rst > > @@ -75,6 +75,10 @@ ENETFEC driver. > > ENETFEC Features > > ~ > > > > +- Basic stats > > +- Promiscuous > > +- VLAN offload > > +- L3/L4 checksum offload > > - ARMv8 > > > > Supported ENETFEC SoCs > > diff --git a/doc/guides/nics/features/enetfec.ini > b/doc/guides/nics/features/enetfec.ini > > index 570069798..fcc217773 100644 > > --- a/doc/guides/nics/features/enetfec.ini > > +++ b/doc/guides/nics/features/enetfec.ini > > @@ -4,5 +4,10 @@ > > ; Refer to default.ini for the full list of available PMD features. > > ; > > [Features] > > +Basic stats = Y > > +Promiscuous mode = Y > > +VLAN offload = Y > > +L3 checksum offload = Y > > +L4 checksum offload = Y > > I don't understand why all above features are in the patch. > It looks like all could be added one by one after > the patch with adds basic Rx/Tx suppport.
[dpdk-dev] [PATCH v1] net/ice/base: fix wrong first mask value setting
Since each pf does not share the same structure space, the first
mask value should start at 0 instead of hw->pf_id * per_pf to avoid
address overflow. Otherwise, address space will overlap when
masks.first + masks.count > ICE_PROF_MASK_COUNT, and it may lead to
unexpected variable assignment, which causes segmentation fault.
Fixes: 9467486f179f ("net/ice/base: enable masking for RSS and FD field
vectors")
Cc: sta...@dpdk.org
Signed-off-by: Wenjun Wu
---
drivers/net/ice/base/ice_flex_pipe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ice/base/ice_flex_pipe.c
b/drivers/net/ice/base/ice_flex_pipe.c
index fabff039ec..aa42177833 100644
--- a/drivers/net/ice/base/ice_flex_pipe.c
+++ b/drivers/net/ice/base/ice_flex_pipe.c
@@ -3435,7 +3435,7 @@ static void ice_init_prof_masks(struct ice_hw *hw, enum
ice_block blk)
per_pf = ICE_PROF_MASK_COUNT / hw->dev_caps.num_funcs;
hw->blk[blk].masks.count = per_pf;
- hw->blk[blk].masks.first = hw->pf_id * per_pf;
+ hw->blk[blk].masks.first = 0;
ice_memset(hw->blk[blk].masks.masks, 0,
sizeof(hw->blk[blk].masks.masks), ICE_NONDMA_MEM);
--
2.25.1
Re: [dpdk-dev] [PATCH] devtools: script to track map symbols
> > pylint reports some things that should be fixed. Don't worry about the naming > style > and docstring but others should be addressed. [SNIP] Ah, rookie mistake, I ran checkpatch and thought that I was all good. I will sort it out thanks. Ray K
[dpdk-dev] [Bug 721] Wrong event pointer in rx adapter
https://bugs.dpdk.org/show_bug.cgi?id=721 Pavan Nikhilesh Bhagavatula (pbhagavat...@marvell.com) changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |INVALID CC||pbhagavat...@marvell.com --- Comment #7 from Pavan Nikhilesh Bhagavatula (pbhagavat...@marvell.com) --- As Jay mentioned, the intent is to give the callback events generated in the current Rx cycle which the current code already does. Marking the bug as resolved. Pavan. -- You are receiving this mail because: You are the assignee for the bug.
Re: [dpdk-dev] [PATCH v3 19/20] net/sfc: support flow action COUNT in transfer rules
21/06/2021 10:28, David Marchand:
> On Fri, Jun 18, 2021 at 3:41 PM Andrew Rybchenko
> > +# for gcc compiles we need -latomic for 128-bit atomic ops
> > +if cc.get_id() == 'gcc'
> > +ext_deps += cc.find_library('atomic')
> > +endif
>
> This patch breaks compilation on rhel/fedora (most failures in UNH for
> this series are linked to this issue) when the libatomic rpm is not
> installed.
[...]
> """
> Running compile:
> Working directory:
> /home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z
> Command line: gcc -L/home/dmarchan/intel-ipsec-mb/install/lib
> -I/home/dmarchan/intel-ipsec-mb/install/include
> /home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z/testfile.c
> -o /home/dmarchan/builds/build-gcc-static/meson-private/tmpdu27j15z/output.exe
> -pipe -D_FILE_OFFSET_BITS=64 -O0 -Wl,--start-group -latomic
> -Wl,--end-group -Wl,--allow-shlib-undefined
>
> Code:
> int main(void) { return 0; }
>
> Compiler stdout:
>
> Compiler stderr:
> /usr/bin/ld: cannot find /usr/lib64/libatomic.so.1.2.0
> collect2: error: ld returned 1 exit status
>
> Library atomic found: YES
> """
Indeed it looks like a bug in meson.
How does it behave with clang 32-bit?
For reference, in config/meson.build:
"""
# for clang 32-bit compiles we need libatomic for 64-bit atomic ops
if cc.get_id() == 'clang' and dpdk_conf.get('RTE_ARCH_64') == false
atomic_dep = cc.find_library('atomic', required: true)
add_project_link_arguments('-latomic', language: 'c')
dpdk_extra_ldflags += '-latomic'
endif
"""
> [dmarchan@wsfd-netdev66 dpdk]$ cat
> /usr/lib/gcc/x86_64-redhat-linux/10/libatomic.so
> INPUT ( /usr/lib64/libatomic.so.1.2.0 )
> [dmarchan@wsfd-netdev66 dpdk]$ file /usr/lib64/libatomic.so.1.2.0
> /usr/lib64/libatomic.so.1.2.0: cannot open
> `/usr/lib64/libatomic.so.1.2.0' (No such file or directory)
We must handle this case where libatomic is not completely installed.
Hope there is a good fix possible.
[dpdk-dev] max_rx_pkt_len
Hi DPDK developers, We have an external DPDK KNI interface in our product, and we experienced that ethernet payload of size 1500 cannot be received, only 1496. It is important that the traffic is VLAN tagged. We have encountered this report: https://dev.dpdk.narkive.com/xGGOQC8R/dpdk-dev-issue-with-mtu-max-rx-pkt-len-handling-by-different-nics-pmd-drivers, which pretty much similar to our case. We started to experiment with max_rx_pkt_len, but no matter what we set it to it won't work with 1500 payload only 1496. Then we checked rte_eth_dev_configure and realized that max_rx_pkt_len is defaulted to ETHER_MAX_LEN in case max_rx_pkt_len is set to > ETHER_MAX_LEN. ETHER_MAX_LEN is 1518 and thus doesn't contain enough bytes for possible vlan header. As a workaround we have enabled JUMBO frames and set max_rx_pkt_len to 2048. This way traffic is fine. But I want to know what should be the official way to support 1500 payload in VLAN tagged frames with standard frame size? Regards, Balazs
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
Hi everyone,
> > >>> One more thought here - if we are talking about rte_ethdev[] in
> > >>> particular, I think we can:
> > >>> 1. move public function pointers (rx_pkt_burst(), etc.) from rte_ethdev
> > >>> into a separate flat array.
> > >>> We can keep it public to still use inline functions for 'fast' calls
> > >>> rte_eth_rx_burst(), etc. to avoid
> > >>> any regressions.
> > >>> That could still be flat array with max_size specified at application
> > >>> startup.
> > >>> 2. Hide rest of rte_ethdev struct in .c.
> > >>> That will allow us to change the struct itself and the whole
> > >>> rte_ethdev[] table in a way we like
> > >>> (flat array, vector, hash, linked list) without ABI/API breakages.
> > >>>
> > >>> Yes, it would require all PMDs to change prototype for pkt_rx_burst()
> > >>> function
> > >>> (to accept port_id, queue_id instead of queue pointer), but the change
> > >>> is mechanical one.
> > >>> Probably some macro can be provided to simplify it.
> > >>>
> > >>
> > >> We are already planning some tasks for ABI stability for v21.11, I think
> > >> splitting 'struct rte_eth_dev' can be part of that task, it enables
> > >> hiding more
> > >> internal data.
> > >
> > > Ok, sounds good.
> > >
> > >>
> > >>> The only significant complication I can foresee with implementing that
> > >>> approach -
> > >>> we'll need a an array of 'fast' function pointers per queue, not per
> > >>> device as we have now
> > >>> (to avoid extra indirection for callback implementation).
> > >>> Though as a bonus we'll have ability to use different RX/TX funcions
> > >>> per queue.
> > >>>
> > >>
> > >> What do you think split Rx/Tx callback into its own struct too?
> > >>
> > >> Overall 'rte_eth_dev' can be split into three as:
> > >> 1. rte_eth_dev
> > >> 2. rte_eth_dev_burst
> > >> 3. rte_eth_dev_cb
> > >>
> > >> And we can hide 1 from applications even with the inline functions.
> > >
> > > As discussed off-line, I think:
> > > it is possible.
> > > My absolute preference would be to have just 1/2 (with CB hidden).
> >
> > How can we hide the callbacks since they are used by inline burst functions.
>
> I probably I owe a better explanation to what I meant in first mail.
> Otherwise it sounds confusing.
> I'll try to write a more detailed one in next few days.
Actually I gave it another thought over weekend, and might be we can
hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
an example, but the same principle applies to other 'fast' functions.
1. Needed changes for PMDs rx_pkt_burst():
a) change function prototype to accept 'uint16_t port_id' and 'uint16_t
queue_id',
instead of current 'void *'.
b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog() function
at return.
This inline function will do all CB calls for that queue.
To be more specific, let say we have some PMD: xyz with RX function:
uint16_t
xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
{
struct xyz_rx_queue *rxq = rx_queue;
uint16_t nb_rx = 0;
/* do actual stuff here */
return nb_rx;
}
It will be transformed to:
uint16_t
xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts)
{
struct xyz_rx_queue *rxq;
uint16_t nb_rx;
rxq = _rte_eth_rx_prolog(port_id, queue_id);
if (rxq == NULL)
return 0;
nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts, nb_pkts);
}
And somewhere in ethdev_private.h:
static inline void *
_rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
{
struct rte_eth_dev *dev = &rte_eth_devices[port_id];
#ifdef RTE_ETHDEV_DEBUG_RX
RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
if (queue_id >= dev->data->nb_rx_queues) {
RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
return NULL;
}
#endif
return dev->data->rx_queues[queue_id];
}
static inline uint16_t
_rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
**rx_pkts, const uint16_t nb_pkts);
{
struct rte_eth_dev *dev = &rte_eth_devices[port_id];
#ifdef RTE_ETHDEV_RXTX_CALLBACKS
struct rte_eth_rxtx_callback *cb;
/* __ATOMIC_RELEASE memory order was used when the
* call back was inserted into the list.
* Since there is a clear dependency between loading
* cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
* not required.
*/
cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
__ATOMIC_RELAXED);
if (unlikely(cb != NULL)) {
do {
nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx,
nb_pkts, cb->param);
Re: [dpdk-dev] [PATCH] kni: fix wrong mbuf alloc count in kni_allocate_mbufs
On 6/21/2021 4:27 AM, wangyunjian wrote:
>> -Original Message-
>> From: Ferruh Yigit [mailto:ferruh.yi...@intel.com]
>> Sent: Friday, June 18, 2021 9:37 PM
>> To: wangyunjian ; dev@dpdk.org
>> Cc: liucheng (J) ; dingxiaoxiong
>>
>> Subject: Re: [dpdk-dev] [PATCH] kni: fix wrong mbuf alloc count in
>> kni_allocate_mbufs
>>
>> On 5/31/2021 1:09 PM, wangyunjian wrote:
>>> From: Yunjian Wang
>>>
>>> In kni_allocate_mbufs(), we alloc mbuf for alloc_q as this code.
>>> allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1) \
>>> & (MAX_MBUF_BURST_NUM - 1);
>>> The value of allocq_free maybe zero (e.g 32 & (32 - 1) = 0), and it
>>> will not fill the alloc_q. When the alloc_q's free count is zero, it
>>> will drop the packet in kernel kni.
>>>
>>
>> nack
>>
>> Both 'read' & 'write' pointers can be max 'len-1', so 'read - write - 1'
>> can't be
>> 'len'.
>> For above example first part can't be '32'.
>>
>> But if you are observing a problem, can you please describe it a little
>> more, it
>> may be because of something else.
>
> The ring size is 1024. After init, write = read = 0. Then we fill
> kni->alloc_q to full. At this time, write = 1023, read = 0.
> Then the kernel send 32 packets to userspace. At this time, write = 1023,
> read = 32.
> And then the userspace recieve this 32 packets. Then fill the kni->alloc_q,
> (32 - 1023 - 1)&31 = 0, fill nothing.
> ...
> Then the kernel send 32 packets to userspace. At this time, write = 1023,
> read = 992.
> And then the userspace recieve this 32 packets. Then fill the kni->alloc_q,
> (992 - 1023 - 1)&31 = 0, fill nothing.
> Then the kernel send 32 packets to userspace. The kni->alloc_q only has 31
> mbufs and will drop one packet.
>
> Absolutely, this is a special scene. Normally, it will fill some mbufs
> everytime, but may not enough for the kernel to use.
> In this patch, we always keep the kni->alloc_q to full for the kernel to use.
>
I see now, yes it is technically possible to have above scenario and it can
cause glitch in the datapath.
Below fix looks good, +1 to use 'kni_fifo_free_count()' instead of calculation
within the function which may be wrong for the 'RTE_USE_C11_MEM_MODEL' case.
Can you please add fixes line too?
> Thanks
>
>>
>>> In this patch, we set the allocq_free as the min between
>>> MAX_MBUF_BURST_NUM and the free count of the alloc_q.
>>>
>>> Signed-off-by: Cheng Liu
>>> Signed-off-by: Yunjian Wang
>>> ---
>>> lib/kni/rte_kni.c | 5 +++--
>>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/lib/kni/rte_kni.c b/lib/kni/rte_kni.c index
>>> 9dae6a8d7c..20d8f20cef 100644
>>> --- a/lib/kni/rte_kni.c
>>> +++ b/lib/kni/rte_kni.c
>>> @@ -677,8 +677,9 @@ kni_allocate_mbufs(struct rte_kni *kni)
>>> return;
>>> }
>>>
>>> - allocq_free = (kni->alloc_q->read - kni->alloc_q->write - 1)
>>> - & (MAX_MBUF_BURST_NUM - 1);
>>> + allocq_free = kni_fifo_free_count(kni->alloc_q);
>>> + allocq_free = (allocq_free > MAX_MBUF_BURST_NUM) ?
>>> + MAX_MBUF_BURST_NUM : allocq_free;
>>> for (i = 0; i < allocq_free; i++) {
>>> pkts[i] = rte_pktmbuf_alloc(kni->pktmbuf_pool);
>>> if (unlikely(pkts[i] == NULL)) {
>>>
>
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> Konstantin
>
> > > How can we hide the callbacks since they are used by inline burst
> functions.
> >
> > I probably I owe a better explanation to what I meant in first mail.
> > Otherwise it sounds confusing.
> > I'll try to write a more detailed one in next few days.
>
> Actually I gave it another thought over weekend, and might be we can
> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> an example, but the same principle applies to other 'fast' functions.
>
> 1. Needed changes for PMDs rx_pkt_burst():
> a) change function prototype to accept 'uint16_t port_id' and
> 'uint16_t queue_id',
> instead of current 'void *'.
> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
> function at return.
> This inline function will do all CB calls for that queue.
>
> To be more specific, let say we have some PMD: xyz with RX function:
>
> uint16_t
> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t
> nb_pkts)
> {
> struct xyz_rx_queue *rxq = rx_queue;
> uint16_t nb_rx = 0;
>
> /* do actual stuff here */
>
> return nb_rx;
> }
>
> It will be transformed to:
>
> uint16_t
> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> **rx_pkts, uint16_t nb_pkts)
> {
> struct xyz_rx_queue *rxq;
> uint16_t nb_rx;
>
> rxq = _rte_eth_rx_prolog(port_id, queue_id);
> if (rxq == NULL)
> return 0;
> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts,
> nb_pkts);
> }
>
> And somewhere in ethdev_private.h:
>
> static inline void *
> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> {
>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>
> #ifdef RTE_ETHDEV_DEBUG_RX
> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
>
> if (queue_id >= dev->data->nb_rx_queues) {
> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
> queue_id);
> return NULL;
> }
> #endif
> return dev->data->rx_queues[queue_id];
> }
>
> static inline uint16_t
> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> **rx_pkts, const uint16_t nb_pkts);
> {
> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>
> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> struct rte_eth_rxtx_callback *cb;
>
> /* __ATOMIC_RELEASE memory order was used when the
> * call back was inserted into the list.
> * Since there is a clear dependency between loading
> * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> * not required.
> */
> cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
> __ATOMIC_RELAXED);
>
> if (unlikely(cb != NULL)) {
> do {
> nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts,
> nb_rx,
> nb_pkts, cb->param);
> cb = cb->next;
> } while (cb != NULL);
> }
> #endif
>
> rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts,
> nb_rx);
> return nb_rx;
> }
That would make the compiler inline _rte_eth_rx_epilog() into the driver when
compiling the DPDK library. But RTE_ETHDEV_RXTX_CALLBACKS is a definition for
the application developer to use when compiling the DPDK application.
>
> Now, as you said above, in rte_ethdev.h we will keep only a flat array
> with pointers to 'fast' functions:
> struct {
> eth_rx_burst_t rx_pkt_burst
> eth_tx_burst_t tx_pkt_burst;
> eth_tx_prep_t tx_pkt_prepare;
> .
> } rte_eth_dev_burst[];
>
> And rte_eth_rx_burst() will look like:
>
> static inline uint16_t
> rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id,
> struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
> {
> if (port_id >= RTE_MAX_ETHPORTS)
> return 0;
>return rte_eth_dev_burst[port_id](port_id, queue_id, rx_pkts,
> nb_pkts);
> }
>
> Yes, it will require changes in *all* PMDs, but as I said before the
> changes will be a mechanic ones.
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
>
> > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> > Konstantin
> >
> > > > How can we hide the callbacks since they are used by inline burst
> > functions.
> > >
> > > I probably I owe a better explanation to what I meant in first mail.
> > > Otherwise it sounds confusing.
> > > I'll try to write a more detailed one in next few days.
> >
> > Actually I gave it another thought over weekend, and might be we can
> > hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> > an example, but the same principle applies to other 'fast' functions.
> >
> > 1. Needed changes for PMDs rx_pkt_burst():
> > a) change function prototype to accept 'uint16_t port_id' and
> > 'uint16_t queue_id',
> > instead of current 'void *'.
> > b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
> > function at return.
> > This inline function will do all CB calls for that queue.
> >
> > To be more specific, let say we have some PMD: xyz with RX function:
> >
> > uint16_t
> > xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t
> > nb_pkts)
> > {
> > struct xyz_rx_queue *rxq = rx_queue;
> > uint16_t nb_rx = 0;
> >
> > /* do actual stuff here */
> >
> > return nb_rx;
> > }
> >
> > It will be transformed to:
> >
> > uint16_t
> > xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> > **rx_pkts, uint16_t nb_pkts)
> > {
> > struct xyz_rx_queue *rxq;
> > uint16_t nb_rx;
> >
> > rxq = _rte_eth_rx_prolog(port_id, queue_id);
> > if (rxq == NULL)
> > return 0;
> > nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> > return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts,
> > nb_pkts);
> > }
> >
> > And somewhere in ethdev_private.h:
> >
> > static inline void *
> > _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> > {
> >struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >
> > #ifdef RTE_ETHDEV_DEBUG_RX
> > RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> > RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
> >
> > if (queue_id >= dev->data->nb_rx_queues) {
> > RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
> > queue_id);
> > return NULL;
> > }
> > #endif
> > return dev->data->rx_queues[queue_id];
> > }
> >
> > static inline uint16_t
> > _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> > **rx_pkts, const uint16_t nb_pkts);
> > {
> > struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >
> > #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> > struct rte_eth_rxtx_callback *cb;
> >
> > /* __ATOMIC_RELEASE memory order was used when the
> > * call back was inserted into the list.
> > * Since there is a clear dependency between loading
> > * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> > * not required.
> > */
> > cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
> > __ATOMIC_RELAXED);
> >
> > if (unlikely(cb != NULL)) {
> > do {
> > nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts,
> > nb_rx,
> > nb_pkts, cb->param);
> > cb = cb->next;
> > } while (cb != NULL);
> > }
> > #endif
> >
> > rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts,
> > nb_rx);
> > return nb_rx;
> > }
>
> That would make the compiler inline _rte_eth_rx_epilog() into the driver when
> compiling the DPDK library. But
> RTE_ETHDEV_RXTX_CALLBACKS is a definition for the application developer to
> use when compiling the DPDK application.
I believe it is for both - user app and DPDK drivers.
AFAIK, they both have to use the same rte_config.h, otherwise things will be
broken.
If let say RTE_ETHDEV_RXTX_CALLBACKS is not enabled in ethdev, then
user wouldn't be able to add a callback at first place.
BTW, such change will allow us to make RTE_ETHDEV_RXTX_CALLBACKS
internal for ethdev/PMD layer, which is a good thing from my perspective.
>
> >
> > Now, as you said above, in rte_ethdev.h we will keep only a flat array
> > with pointers to 'fast' functions:
> > struct {
> > eth_rx_burst_t rx_pkt_burst
> > eth_tx_burst_t tx_pkt_burst;
> > eth_tx_prep_t tx_pkt_prepare;
> > .
> > } rte_eth_dev_burst[];
> >
> > And rte_eth_rx_burst() will look like:
> >
> > static inline uint16_t
> > rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id,
> > struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
> > {
> > if (port_id >= RTE_MAX_ETHPORTS)
> > return 0;
> >return rte_eth_dev_burst[port_id](port_id, queue_id, rx_pkts,
> > nb_pkts);
> > }
> >
> > Yes, it will require changes in *all* PMDs, but as I said before the
> >
Re: [dpdk-dev] [dpdk-stable] [PATCH] app/test: fix IPv6 header initialization
On Mon, Jun 21, 2021 at 2:41 PM Lance Richardson wrote: > > On Tue, May 11, 2021 at 10:42 AM Lance Richardson > wrote: > > > > On Tue, May 11, 2021 at 10:31 AM David Marchand > > wrote: > > > > > > On Fri, Mar 26, 2021 at 5:37 PM Lance Richardson > > > wrote: > > > > > > > > Fix two issues found when writing PMD unit tests for HW ptype and > > > > L4 checksum offload: > > > > > > Would those unit tests be interesting to other pmd driver writers? > > > > > I think so, although some adjustments would be needed to account > > for differences in hardware capabilities. The tests I've written so far > > are still very much a work in progress, but I hope to have something > > ready for RFC in the near future. > > What is the current status of this patch? I wanted feedback from bonding guys, but I'll get it in v21.08 now. Thanks for the heads up. -- David Marchand
Re: [dpdk-dev] [PATCH v1 1/7] power_intrinsics: allow monitor checks inversion
Hi Anatoly,
> Previously, the semantics of power monitor were such that we were
> checking current value against the expected value, and if they matched,
> then the sleep was aborted. This is somewhat inflexible, because it only
> allowed us to check for a specific value.
>
> This commit adds an option to reverse the check, so that we can have
> monitor sleep aborted if the expected value *doesn't* match what's in
> memory. This allows us to both implement all currently implemented
> driver code, as well as support more use cases which don't easily map to
> previous semantics (such as waiting on writes to AF_XDP counter value).
>
> Since the old behavior is the default, no need to adjust existing
> implementations.
>
> Signed-off-by: Anatoly Burakov
> ---
> lib/eal/include/generic/rte_power_intrinsics.h | 4
> lib/eal/x86/rte_power_intrinsics.c | 5 -
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/lib/eal/include/generic/rte_power_intrinsics.h
> b/lib/eal/include/generic/rte_power_intrinsics.h
> index dddca3d41c..1006c2edfc 100644
> --- a/lib/eal/include/generic/rte_power_intrinsics.h
> +++ b/lib/eal/include/generic/rte_power_intrinsics.h
> @@ -31,6 +31,10 @@ struct rte_power_monitor_cond {
> * 4, or 8. Supplying any other value will result in
> * an error.
> */
> + uint8_t invert; /**< Invert check for expected value (e.g. instead of
> + * checking if `val` matches something, check if
> + * `val` *doesn't* match a particular value)
> + */
> };
>
> /**
> diff --git a/lib/eal/x86/rte_power_intrinsics.c
> b/lib/eal/x86/rte_power_intrinsics.c
> index 39ea9fdecd..5d944e9aa4 100644
> --- a/lib/eal/x86/rte_power_intrinsics.c
> +++ b/lib/eal/x86/rte_power_intrinsics.c
> @@ -117,7 +117,10 @@ rte_power_monitor(const struct rte_power_monitor_cond
> *pmc,
> const uint64_t masked = cur_value & pmc->mask;
>
> /* if the masked value is already matching, abort */
> - if (masked == pmc->val)
> + if (!pmc->invert && masked == pmc->val)
> + goto end;
> + /* same, but for inverse check */
> + if (pmc->invert && masked != pmc->val)
> goto end;
> }
>
Hmm..., such approach looks too 'patchy'...
Can we at least replace 'inver' with something like:
enum rte_power_monitor_cond_op {
_EQ, NEQ,...
};
Then at least new comparions ops can be added in future.
Even better I think would be to just leave to PMD to provide a comparison
callback.
Will make things really simple and generic:
struct rte_power_monitor_cond {
volatile void *addr;
int (*cmp)(uint64_t val);
uint8_t size;
};
And then in rte_power_monitor(...):
const uint64_t cur_value = __get_umwait_val(pmc->addr, pmc->size);
if (pmc->cmp(cur_value) != 0)
goto end;
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> Konstantin
>
> >
> > > From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> > > Konstantin
> > >
> > > > > How can we hide the callbacks since they are used by inline
> burst
> > > functions.
> > > >
> > > > I probably I owe a better explanation to what I meant in first
> mail.
> > > > Otherwise it sounds confusing.
> > > > I'll try to write a more detailed one in next few days.
> > >
> > > Actually I gave it another thought over weekend, and might be we
> can
> > > hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst()
> as
> > > an example, but the same principle applies to other 'fast'
> functions.
> > >
> > > 1. Needed changes for PMDs rx_pkt_burst():
> > > a) change function prototype to accept 'uint16_t port_id' and
> > > 'uint16_t queue_id',
> > > instead of current 'void *'.
> > > b) Each PMD rx_pkt_burst() will have to call
> rte_eth_rx_epilog()
> > > function at return.
> > > This inline function will do all CB calls for that queue.
> > >
> > > To be more specific, let say we have some PMD: xyz with RX
> function:
> > >
> > > uint16_t
> > > xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t
> > > nb_pkts)
> > > {
> > > struct xyz_rx_queue *rxq = rx_queue;
> > > uint16_t nb_rx = 0;
> > >
> > > /* do actual stuff here */
> > >
> > > return nb_rx;
> > > }
> > >
> > > It will be transformed to:
> > >
> > > uint16_t
> > > xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> > > **rx_pkts, uint16_t nb_pkts)
> > > {
> > > struct xyz_rx_queue *rxq;
> > > uint16_t nb_rx;
> > >
> > > rxq = _rte_eth_rx_prolog(port_id, queue_id);
> > > if (rxq == NULL)
> > > return 0;
> > > nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> > > return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts,
> > > nb_pkts);
> > > }
> > >
> > > And somewhere in ethdev_private.h:
> > >
> > > static inline void *
> > > _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> > > {
> > >struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> > >
> > > #ifdef RTE_ETHDEV_DEBUG_RX
> > > RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> > > RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
> > >
> > > if (queue_id >= dev->data->nb_rx_queues) {
> > > RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
> > > queue_id);
> > > return NULL;
> > > }
> > > #endif
> > > return dev->data->rx_queues[queue_id];
> > > }
> > >
> > > static inline uint16_t
> > > _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct
> rte_mbuf
> > > **rx_pkts, const uint16_t nb_pkts);
> > > {
> > > struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> > >
> > > #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> > > struct rte_eth_rxtx_callback *cb;
> > >
> > > /* __ATOMIC_RELEASE memory order was used when the
> > > * call back was inserted into the list.
> > > * Since there is a clear dependency between loading
> > > * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> > > * not required.
> > > */
> > > cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
> > > __ATOMIC_RELAXED);
> > >
> > > if (unlikely(cb != NULL)) {
> > > do {
> > > nb_rx = cb->fn.rx(port_id, queue_id,
> rx_pkts,
> > > nb_rx,
> > > nb_pkts, cb-
> >param);
> > > cb = cb->next;
> > > } while (cb != NULL);
> > > }
> > > #endif
> > >
> > > rte_ethdev_trace_rx_burst(port_id, queue_id, (void
> **)rx_pkts,
> > > nb_rx);
> > > return nb_rx;
> > > }
> >
> > That would make the compiler inline _rte_eth_rx_epilog() into the
> driver when compiling the DPDK library. But
> > RTE_ETHDEV_RXTX_CALLBACKS is a definition for the application
> developer to use when compiling the DPDK application.
>
> I believe it is for both - user app and DPDK drivers.
> AFAIK, they both have to use the same rte_config.h, otherwise things
> will be broken.
> If let say RTE_ETHDEV_RXTX_CALLBACKS is not enabled in ethdev, then
> user wouldn't be able to add a callback at first place.
In the case of RTE_ETHDEV_RXTX_CALLBACKS, it is independent:
If it is not compiled with the DPDK library, attempts to install callbacks from
the application will fail with ENOTSUP.
If it is not compiled with the DPDK application, no time will be spent trying
to determine if any there are any callbacks to call.
> BTW, such change will allow us to make RTE_ETHDEV_RXTX_CALLBACKS
> internal for ethdev/PMD layer, which is a good thing from my
> perspective.
If it can be done without degrading performance for applications not using
callbacks.
[dpdk-dev] [PATCH v3] lib/rte_rib6: fix stack buffer overflow
From: Owen Hilyard
ASAN found a stack buffer overflow in lib/rib/rte_rib6.c:get_dir.
The fix for the stack buffer overflow was to make sure depth
was always < 128, since when depth = 128 it caused the index
into the ip address to be 16, which read off the end of the array.
While trying to solve the buffer overflow, I noticed that a few
changes could be made to remove the for loop entirely.
Fixes: f7e861e21c ("rib: support IPv6")
Signed-off-by: Owen Hilyard
---
lib/rib/rte_rib6.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/lib/rib/rte_rib6.c b/lib/rib/rte_rib6.c
index f6c55ee45..96424e9c9 100644
--- a/lib/rib/rte_rib6.c
+++ b/lib/rib/rte_rib6.c
@@ -79,20 +79,33 @@ is_covered(const uint8_t ip1[RTE_RIB6_IPV6_ADDR_SIZE],
static inline int
get_dir(const uint8_t ip[RTE_RIB6_IPV6_ADDR_SIZE], uint8_t depth)
{
- int i = 0;
- uint8_t p_depth, msk;
-
- for (p_depth = depth; p_depth >= 8; p_depth -= 8)
- i++;
-
- msk = 1 << (7 - p_depth);
- return (ip[i] & msk) != 0;
+ uint8_t index, msk;
+
+ /*
+* depth & 127 clamps depth to values that will not
+* read off the end of ip.
+* depth is the number of bits deep into ip to traverse, and
+* is incremented in blocks of 8 (1 byte). This means the last
+* 3 bits are irrelevant to what the index of ip should be.
+*/
+ index = (depth & (UINT8_MAX - 1)) / CHAR_BIT;
+
+ /*
+* msk is the bitmask used to extract the bit used to decide the
+* direction of the next step of the binary search.
+*/
+ msk = 1 << (7 - (depth & 7));
+
+ return (ip[index] & msk) != 0;
}
static inline struct rte_rib6_node *
get_nxt_node(struct rte_rib6_node *node,
const uint8_t ip[RTE_RIB6_IPV6_ADDR_SIZE])
{
+ if (node->depth == RIB6_MAXDEPTH)
+ return NULL;
+
return (get_dir(ip, node->depth)) ? node->right : node->left;
}
--
2.30.2
Re: [dpdk-dev] [PATCH v3 00/62] Marvell CNXK Ethdev Driver
On Fri, Jun 18, 2021 at 4:09 PM Nithin Dabilpuram wrote: > > This patchset adds support for Marvell CN106XX SoC based on 'common/cnxk' > driver. In future, CN9K a.k.a octeontx2 will also be supported by same > driver when code is ready and 'net/octeontx2' will be deprecated. Looks good to me in general, a couple of final comments 1) Build issue with RHEL 7 (gcc 4.8) http://mails.dpdk.org/archives/test-report/2021-June/199620.html 2) Shorten git subject messages( for explicit "add" etc) Example: From: net/cnxk: add DMAC filter support to: net/cnxk: support DMAC filter 3) Add Cc: sta...@dpdk.org for following patch common/cnxk: fix batch alloc completion poll logic 4) Fix following camel case CHECK:CAMELCASE: Avoid CamelCase: #92: FILE: drivers/net/cnxk/cnxk_ethdev.c:122: + if (roc_model_is_cn96_Ax() && 5) Replace INTERNAL in drivers/net/cnxk/version.map 6) Add [rte_flow items] and [rte_flow actions] in doc/guides/nics/features/cnxk_vec.ini and doc/guides/nics/features/cnxk_vf.ini
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
On 6/21/2021 12:06 PM, Ananyev, Konstantin wrote:
>
> Hi everyone,
>
>> One more thought here - if we are talking about rte_ethdev[] in
>> particular, I think we can:
>> 1. move public function pointers (rx_pkt_burst(), etc.) from rte_ethdev
>> into a separate flat array.
>> We can keep it public to still use inline functions for 'fast' calls
>> rte_eth_rx_burst(), etc. to avoid
>> any regressions.
>> That could still be flat array with max_size specified at application
>> startup.
>> 2. Hide rest of rte_ethdev struct in .c.
>> That will allow us to change the struct itself and the whole
>> rte_ethdev[] table in a way we like
>> (flat array, vector, hash, linked list) without ABI/API breakages.
>>
>> Yes, it would require all PMDs to change prototype for pkt_rx_burst()
>> function
>> (to accept port_id, queue_id instead of queue pointer), but the change
>> is mechanical one.
>> Probably some macro can be provided to simplify it.
>>
>
> We are already planning some tasks for ABI stability for v21.11, I think
> splitting 'struct rte_eth_dev' can be part of that task, it enables
> hiding more
> internal data.
Ok, sounds good.
>
>> The only significant complication I can foresee with implementing that
>> approach -
>> we'll need a an array of 'fast' function pointers per queue, not per
>> device as we have now
>> (to avoid extra indirection for callback implementation).
>> Though as a bonus we'll have ability to use different RX/TX funcions per
>> queue.
>>
>
> What do you think split Rx/Tx callback into its own struct too?
>
> Overall 'rte_eth_dev' can be split into three as:
> 1. rte_eth_dev
> 2. rte_eth_dev_burst
> 3. rte_eth_dev_cb
>
> And we can hide 1 from applications even with the inline functions.
As discussed off-line, I think:
it is possible.
My absolute preference would be to have just 1/2 (with CB hidden).
>>>
>>> How can we hide the callbacks since they are used by inline burst functions.
>>
>> I probably I owe a better explanation to what I meant in first mail.
>> Otherwise it sounds confusing.
>> I'll try to write a more detailed one in next few days.
>
> Actually I gave it another thought over weekend, and might be we can
> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> an example, but the same principle applies to other 'fast' functions.
>
> 1. Needed changes for PMDs rx_pkt_burst():
> a) change function prototype to accept 'uint16_t port_id' and 'uint16_t
> queue_id',
> instead of current 'void *'.
> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog() function
> at return.
> This inline function will do all CB calls for that queue.
>
> To be more specific, let say we have some PMD: xyz with RX function:
>
> uint16_t
> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
> {
> struct xyz_rx_queue *rxq = rx_queue;
> uint16_t nb_rx = 0;
>
> /* do actual stuff here */
>
> return nb_rx;
> }
>
> It will be transformed to:
>
> uint16_t
> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf **rx_pkts,
> uint16_t nb_pkts)
> {
> struct xyz_rx_queue *rxq;
> uint16_t nb_rx;
>
> rxq = _rte_eth_rx_prolog(port_id, queue_id);
> if (rxq == NULL)
> return 0;
> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts, nb_pkts);
> }
>
> And somewhere in ethdev_private.h:
>
> static inline void *
> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> {
>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>
> #ifdef RTE_ETHDEV_DEBUG_RX
> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
>
> if (queue_id >= dev->data->nb_rx_queues) {
> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
> return NULL;
> }
> #endif
> return dev->data->rx_queues[queue_id];
> }
>
> static inline uint16_t
> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> **rx_pkts, const uint16_t nb_pkts);
> {
> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>
> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> struct rte_eth_rxtx_callback *cb;
>
> /* __ATOMIC_RELEASE memory order was used when the
> * call back was inserted into the list.
> * Since there is a clear dependency between loading
> * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> * not required.
> */
> cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
> __ATOMIC_RELAXED);
>
> if (unlikely(cb != NULL)) {
> do {
>
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
On 6/21/2021 1:30 PM, Ananyev, Konstantin wrote:
>
>>
>>> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
>>> Konstantin
>>>
> How can we hide the callbacks since they are used by inline burst
>>> functions.
I probably I owe a better explanation to what I meant in first mail.
Otherwise it sounds confusing.
I'll try to write a more detailed one in next few days.
>>>
>>> Actually I gave it another thought over weekend, and might be we can
>>> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
>>> an example, but the same principle applies to other 'fast' functions.
>>>
>>> 1. Needed changes for PMDs rx_pkt_burst():
>>> a) change function prototype to accept 'uint16_t port_id' and
>>> 'uint16_t queue_id',
>>> instead of current 'void *'.
>>> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
>>> function at return.
>>> This inline function will do all CB calls for that queue.
>>>
>>> To be more specific, let say we have some PMD: xyz with RX function:
>>>
>>> uint16_t
>>> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t
>>> nb_pkts)
>>> {
>>> struct xyz_rx_queue *rxq = rx_queue;
>>> uint16_t nb_rx = 0;
>>>
>>> /* do actual stuff here */
>>>
>>> return nb_rx;
>>> }
>>>
>>> It will be transformed to:
>>>
>>> uint16_t
>>> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
>>> **rx_pkts, uint16_t nb_pkts)
>>> {
>>> struct xyz_rx_queue *rxq;
>>> uint16_t nb_rx;
>>>
>>> rxq = _rte_eth_rx_prolog(port_id, queue_id);
>>> if (rxq == NULL)
>>> return 0;
>>> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
>>> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts,
>>> nb_pkts);
>>> }
>>>
>>> And somewhere in ethdev_private.h:
>>>
>>> static inline void *
>>> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
>>> {
>>>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>
>>> #ifdef RTE_ETHDEV_DEBUG_RX
>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
>>>
>>> if (queue_id >= dev->data->nb_rx_queues) {
>>> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
>>> queue_id);
>>> return NULL;
>>> }
>>> #endif
>>> return dev->data->rx_queues[queue_id];
>>> }
>>>
>>> static inline uint16_t
>>> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
>>> **rx_pkts, const uint16_t nb_pkts);
>>> {
>>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>
>>> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
>>> struct rte_eth_rxtx_callback *cb;
>>>
>>> /* __ATOMIC_RELEASE memory order was used when the
>>> * call back was inserted into the list.
>>> * Since there is a clear dependency between loading
>>> * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
>>> * not required.
>>> */
>>> cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
>>> __ATOMIC_RELAXED);
>>>
>>> if (unlikely(cb != NULL)) {
>>> do {
>>> nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts,
>>> nb_rx,
>>> nb_pkts, cb->param);
>>> cb = cb->next;
>>> } while (cb != NULL);
>>> }
>>> #endif
>>>
>>> rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts,
>>> nb_rx);
>>> return nb_rx;
>>> }
>>
>> That would make the compiler inline _rte_eth_rx_epilog() into the driver
>> when compiling the DPDK library. But
>> RTE_ETHDEV_RXTX_CALLBACKS is a definition for the application developer to
>> use when compiling the DPDK application.
>
> I believe it is for both - user app and DPDK drivers.
> AFAIK, they both have to use the same rte_config.h, otherwise things will be
> broken.
> If let say RTE_ETHDEV_RXTX_CALLBACKS is not enabled in ethdev, then
> user wouldn't be able to add a callback at first place.
> BTW, such change will allow us to make RTE_ETHDEV_RXTX_CALLBACKS
> internal for ethdev/PMD layer, which is a good thing from my perspective.
>
It is possible to use binary drivers (.so) as plugin. Currently application can
decide to use or not use Rx/Tx callbacks even with binary drivers, but this
change adds a complexity to this usecase.
>>
>>>
>>> Now, as you said above, in rte_ethdev.h we will keep only a flat array
>>> with pointers to 'fast' functions:
>>> struct {
>>> eth_rx_burst_t rx_pkt_burst
>>> eth_tx_burst_t tx_pkt_burst;
>>> eth_tx_prep_t tx_pkt_prepare;
>>> .
>>> } rte_eth_dev_burst[];
>>>
>>> And rte_eth_rx_burst() will look like:
>>>
>>> static inline uint16_t
>>> rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id,
>>> struct rte_mbuf **rx_pkts,
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
>
> On 6/21/2021 1:30 PM, Ananyev, Konstantin wrote:
> >
> >>
> >>> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Ananyev,
> >>> Konstantin
> >>>
> > How can we hide the callbacks since they are used by inline burst
> >>> functions.
>
> I probably I owe a better explanation to what I meant in first mail.
> Otherwise it sounds confusing.
> I'll try to write a more detailed one in next few days.
> >>>
> >>> Actually I gave it another thought over weekend, and might be we can
> >>> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> >>> an example, but the same principle applies to other 'fast' functions.
> >>>
> >>> 1. Needed changes for PMDs rx_pkt_burst():
> >>> a) change function prototype to accept 'uint16_t port_id' and
> >>> 'uint16_t queue_id',
> >>> instead of current 'void *'.
> >>> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
> >>> function at return.
> >>> This inline function will do all CB calls for that queue.
> >>>
> >>> To be more specific, let say we have some PMD: xyz with RX function:
> >>>
> >>> uint16_t
> >>> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t
> >>> nb_pkts)
> >>> {
> >>> struct xyz_rx_queue *rxq = rx_queue;
> >>> uint16_t nb_rx = 0;
> >>>
> >>> /* do actual stuff here */
> >>>
> >>> return nb_rx;
> >>> }
> >>>
> >>> It will be transformed to:
> >>>
> >>> uint16_t
> >>> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> >>> **rx_pkts, uint16_t nb_pkts)
> >>> {
> >>> struct xyz_rx_queue *rxq;
> >>> uint16_t nb_rx;
> >>>
> >>> rxq = _rte_eth_rx_prolog(port_id, queue_id);
> >>> if (rxq == NULL)
> >>> return 0;
> >>> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> >>> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts,
> >>> nb_pkts);
> >>> }
> >>>
> >>> And somewhere in ethdev_private.h:
> >>>
> >>> static inline void *
> >>> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> >>> {
> >>>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >>>
> >>> #ifdef RTE_ETHDEV_DEBUG_RX
> >>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> >>> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
> >>>
> >>> if (queue_id >= dev->data->nb_rx_queues) {
> >>> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n",
> >>> queue_id);
> >>> return NULL;
> >>> }
> >>> #endif
> >>> return dev->data->rx_queues[queue_id];
> >>> }
> >>>
> >>> static inline uint16_t
> >>> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> >>> **rx_pkts, const uint16_t nb_pkts);
> >>> {
> >>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >>>
> >>> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> >>> struct rte_eth_rxtx_callback *cb;
> >>>
> >>> /* __ATOMIC_RELEASE memory order was used when the
> >>> * call back was inserted into the list.
> >>> * Since there is a clear dependency between loading
> >>> * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> >>> * not required.
> >>> */
> >>> cb = __atomic_load_n(&dev->post_rx_burst_cbs[queue_id],
> >>> __ATOMIC_RELAXED);
> >>>
> >>> if (unlikely(cb != NULL)) {
> >>> do {
> >>> nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts,
> >>> nb_rx,
> >>> nb_pkts, cb->param);
> >>> cb = cb->next;
> >>> } while (cb != NULL);
> >>> }
> >>> #endif
> >>>
> >>> rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts,
> >>> nb_rx);
> >>> return nb_rx;
> >>> }
> >>
> >> That would make the compiler inline _rte_eth_rx_epilog() into the driver
> >> when compiling the DPDK library. But
> >> RTE_ETHDEV_RXTX_CALLBACKS is a definition for the application developer to
> >> use when compiling the DPDK application.
> >
> > I believe it is for both - user app and DPDK drivers.
> > AFAIK, they both have to use the same rte_config.h, otherwise things will
> > be broken.
> > If let say RTE_ETHDEV_RXTX_CALLBACKS is not enabled in ethdev, then
> > user wouldn't be able to add a callback at first place.
> > BTW, such change will allow us to make RTE_ETHDEV_RXTX_CALLBACKS
> > internal for ethdev/PMD layer, which is a good thing from my perspective.
> >
>
> It is possible to use binary drivers (.so) as plugin. Currently application
> can
> decide to use or not use Rx/Tx callbacks even with binary drivers, but this
> change adds a complexity to this usecase.
Not sure I understand you here...
Can you explain a bit more what do you mean?
>
> >>
> >>>
> >>> Now, as you said above, in rte_ethdev.h we will keep only a flat array
> >>> with pointers to 'fast' functions:
> >>> struct {
> >>> eth_rx_burst_t
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
> >> One more thought here - if we are talking about rte_ethdev[] in
> >> particular, I think we can:
> >> 1. move public function pointers (rx_pkt_burst(), etc.) from
> >> rte_ethdev into a separate flat array.
> >> We can keep it public to still use inline functions for 'fast' calls
> >> rte_eth_rx_burst(), etc. to avoid
> >> any regressions.
> >> That could still be flat array with max_size specified at application
> >> startup.
> >> 2. Hide rest of rte_ethdev struct in .c.
> >> That will allow us to change the struct itself and the whole
> >> rte_ethdev[] table in a way we like
> >> (flat array, vector, hash, linked list) without ABI/API breakages.
> >>
> >> Yes, it would require all PMDs to change prototype for pkt_rx_burst()
> >> function
> >> (to accept port_id, queue_id instead of queue pointer), but the change
> >> is mechanical one.
> >> Probably some macro can be provided to simplify it.
> >>
> >
> > We are already planning some tasks for ABI stability for v21.11, I think
> > splitting 'struct rte_eth_dev' can be part of that task, it enables
> > hiding more
> > internal data.
>
> Ok, sounds good.
>
> >
> >> The only significant complication I can foresee with implementing that
> >> approach -
> >> we'll need a an array of 'fast' function pointers per queue, not per
> >> device as we have now
> >> (to avoid extra indirection for callback implementation).
> >> Though as a bonus we'll have ability to use different RX/TX funcions
> >> per queue.
> >>
> >
> > What do you think split Rx/Tx callback into its own struct too?
> >
> > Overall 'rte_eth_dev' can be split into three as:
> > 1. rte_eth_dev
> > 2. rte_eth_dev_burst
> > 3. rte_eth_dev_cb
> >
> > And we can hide 1 from applications even with the inline functions.
>
> As discussed off-line, I think:
> it is possible.
> My absolute preference would be to have just 1/2 (with CB hidden).
> >>>
> >>> How can we hide the callbacks since they are used by inline burst
> >>> functions.
> >>
> >> I probably I owe a better explanation to what I meant in first mail.
> >> Otherwise it sounds confusing.
> >> I'll try to write a more detailed one in next few days.
> >
> > Actually I gave it another thought over weekend, and might be we can
> > hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> > an example, but the same principle applies to other 'fast' functions.
> >
> > 1. Needed changes for PMDs rx_pkt_burst():
> > a) change function prototype to accept 'uint16_t port_id' and 'uint16_t
> > queue_id',
> > instead of current 'void *'.
> > b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
> > function at return.
> > This inline function will do all CB calls for that queue.
> >
> > To be more specific, let say we have some PMD: xyz with RX function:
> >
> > uint16_t
> > xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
> > {
> > struct xyz_rx_queue *rxq = rx_queue;
> > uint16_t nb_rx = 0;
> >
> > /* do actual stuff here */
> >
> > return nb_rx;
> > }
> >
> > It will be transformed to:
> >
> > uint16_t
> > xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> > **rx_pkts, uint16_t nb_pkts)
> > {
> > struct xyz_rx_queue *rxq;
> > uint16_t nb_rx;
> >
> > rxq = _rte_eth_rx_prolog(port_id, queue_id);
> > if (rxq == NULL)
> > return 0;
> > nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> > return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts, nb_pkts);
> > }
> >
> > And somewhere in ethdev_private.h:
> >
> > static inline void *
> > _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> > {
> >struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >
> > #ifdef RTE_ETHDEV_DEBUG_RX
> > RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> > RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
> >
> > if (queue_id >= dev->data->nb_rx_queues) {
> > RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
> > return NULL;
> > }
> > #endif
> > return dev->data->rx_queues[queue_id];
> > }
> >
> > static inline uint16_t
> > _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> > **rx_pkts, const uint16_t nb_pkts);
> > {
> > struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >
> > #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> > struct rte_eth_rxtx_callback *cb;
> >
> > /* __ATOMIC_RELEASE memory order was used when the
> > * call back was inserted into the list.
> > * Since there is a clear dependency between loading
> > * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
> > * not required.
> > */
> >
[dpdk-dev] [PATCH 2/4] net/ice/base: remove firmware log
Remove firmware log related code.
Signed-off-by: Anirudh Venkataramanan
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 52 ---
1 file changed, 52 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index 3805fc9c5c..b45ad3d34c 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2793,50 +2793,6 @@ struct ice_aqc_clear_health_status {
__le32 reserved[4];
};
-/* Set FW Logging configuration (indirect 0xFF30)
- * Register for FW Logging (indirect 0xFF31)
- * Query FW Logging (indirect 0xFF32)
- * FW Log Event (indirect 0xFF33)
- * Get FW Log (indirect 0xFF34)
- * Clear FW Log (indirect 0xFF35)
- */
-
-struct ice_aqc_fw_log {
- u8 cmd_flags;
-#define ICE_AQC_FW_LOG_CONF_UART_ENBIT(0)
-#define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1)
-#define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3)
-#define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0)
-#define ICE_AQC_FW_LOG_AQ_QUERYBIT(2)
-#define ICE_AQC_FW_LOG_PERSISTENT BIT(0)
- u8 rsp_flag;
-#define ICE_AQC_FW_LOG_MORE_DATA BIT(1)
- __le16 fw_rt_msb;
- union {
- struct {
- __le32 fw_rt_lsb;
- } sync;
- struct {
- __le16 log_resolution;
-#define ICE_AQC_FW_LOG_MIN_RESOLUTION (1)
-#define ICE_AQC_FW_LOG_MAX_RESOLUTION (128)
- __le16 mdl_cnt;
- } cfg;
- } ops;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-/* Response Buffer for:
- *Set Firmware Logging Configuration (0xFF30)
- *Query FW Logging (0xFF32)
- */
-struct ice_aqc_fw_log_cfg_resp {
- __le16 module_identifier;
- u8 log_level;
- u8 rsvd0;
-};
-
/**
* struct ice_aq_desc - Admin Queue (AQ) descriptor
* @flags: ICE_AQ_FLAG_* flags
@@ -3207,14 +3163,6 @@ enum ice_adminq_opc {
ice_aqc_opc_get_supported_health_status_codes = 0xFF21,
ice_aqc_opc_get_health_status = 0xFF22,
ice_aqc_opc_clear_health_status = 0xFF23,
-
- /* FW Logging Commands */
- ice_aqc_opc_fw_logs_config = 0xFF30,
- ice_aqc_opc_fw_logs_register= 0xFF31,
- ice_aqc_opc_fw_logs_query = 0xFF32,
- ice_aqc_opc_fw_logs_event = 0xFF33,
- ice_aqc_opc_fw_logs_get = 0xFF34,
- ice_aqc_opc_fw_logs_clear = 0xFF35
};
#endif /* _ICE_ADMINQ_CMD_H_ */
--
2.26.2
[dpdk-dev] [PATCH 4/4] net/ice/base: remove unncessary code
Remove unnecessary jumbo frame configure. Signed-off-by: Fabio Pricoco Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index cf0a7d4e7f..51fca7b166 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -830,10 +830,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw) status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL); ice_free(hw, mac_buf); - if (status) - goto err_unroll_fltr_mgmt_struct; - /* enable jumbo frame support at MAC level */ - status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); if (status) goto err_unroll_fltr_mgmt_struct; /* Obtain counter base index which would be used by flow director */ -- 2.26.2
[dpdk-dev] [PATCH 3/4] net/ice/base: remove VSI info from previous aggregator
remove the VSI info from previous aggregator after moving the VSI to a
new aggregator.
Signed-off-by: Victor Raj
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_adminq_cmd.h | 1 +
drivers/net/ice/base/ice_sched.c | 24 ++--
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index b45ad3d34c..861f5a39b6 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -1670,6 +1670,7 @@ struct ice_aqc_link_topo_addr {
struct ice_aqc_get_link_topo {
struct ice_aqc_link_topo_addr addr;
u8 node_part_num;
+#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
u8 rsvd[9];
};
diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c
index be3f56cdf6..544648cb84 100644
--- a/drivers/net/ice/base/ice_sched.c
+++ b/drivers/net/ice/base/ice_sched.c
@@ -2841,8 +2841,8 @@ static enum ice_status
ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id,
u16 vsi_handle, ice_bitmap_t *tc_bitmap)
{
- struct ice_sched_agg_vsi_info *agg_vsi_info;
- struct ice_sched_agg_info *agg_info;
+ struct ice_sched_agg_vsi_info *agg_vsi_info, *old_agg_vsi_info = NULL;
+ struct ice_sched_agg_info *agg_info, *old_agg_info;
enum ice_status status = ICE_SUCCESS;
struct ice_hw *hw = pi->hw;
u8 tc;
@@ -2852,6 +2852,20 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32
agg_id,
agg_info = ice_get_agg_info(hw, agg_id);
if (!agg_info)
return ICE_ERR_PARAM;
+ /* If the vsi is already part of another aggregator then update
+* its vsi info list
+*/
+ old_agg_info = ice_get_vsi_agg_info(hw, vsi_handle);
+ if (old_agg_info && old_agg_info != agg_info) {
+ struct ice_sched_agg_vsi_info *vtmp;
+
+ LIST_FOR_EACH_ENTRY_SAFE(old_agg_vsi_info, vtmp,
+&old_agg_info->agg_vsi_list,
+ice_sched_agg_vsi_info, list_entry)
+ if (old_agg_vsi_info->vsi_handle == vsi_handle)
+ break;
+ }
+
/* check if entry already exist */
agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle);
if (!agg_vsi_info) {
@@ -2876,6 +2890,12 @@ ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32
agg_id,
break;
ice_set_bit(tc, agg_vsi_info->tc_bitmap);
+ if (old_agg_vsi_info)
+ ice_clear_bit(tc, old_agg_vsi_info->tc_bitmap);
+ }
+ if (old_agg_vsi_info && !old_agg_vsi_info->tc_bitmap[0]) {
+ LIST_DEL(&old_agg_vsi_info->list_entry);
+ ice_free(pi->hw, old_agg_vsi_info);
}
return status;
}
--
2.26.2
[dpdk-dev] [PATCH 0/4] ice base code update
Qi Zhang (4): net/ice/base: add function for DSCP configure net/ice/base: remove firmware log net/ice/base: remove VSI info from previous aggregator net/ice/base: remove unncessary code drivers/net/ice/base/ice_adminq_cmd.h | 53 +-- drivers/net/ice/base/ice_common.c | 4 -- drivers/net/ice/base/ice_dcb.c| 41 + drivers/net/ice/base/ice_dcb.h| 2 + drivers/net/ice/base/ice_sched.c | 24 +++- 5 files changed, 66 insertions(+), 58 deletions(-) -- 2.26.2
[dpdk-dev] [PATCH 1/4] net/ice/base: add function for DSCP configure
ice_aq_set_pfc_mode is used to configure DSCP.
Signed-off-by: Anirudh Venkataramanan
Signed-off-by: Qi Zhang
---
drivers/net/ice/base/ice_dcb.c | 41 ++
drivers/net/ice/base/ice_dcb.h | 2 ++
2 files changed, 43 insertions(+)
diff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c
index 0aaa5ae8c1..c73fc095ff 100644
--- a/drivers/net/ice/base/ice_dcb.c
+++ b/drivers/net/ice/base/ice_dcb.c
@@ -735,6 +735,47 @@ ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
return ice_aq_send_cmd(hw, &desc, (void *)buff, sizeof(*buff), cd);
}
+/**
+ * ice_aq_set_pfc_mode - Set PFC mode
+ * @hw: pointer to the HW struct
+ * @pfc_mode: value of PFC mode to set
+ * @cd: pointer to command details structure or NULL
+ *
+ * This AQ call configures the PFC mdoe to DSCP-based PFC mode or VLAN
+ * -based PFC (0x0303)
+ */
+enum ice_status
+ice_aq_set_pfc_mode(struct ice_hw *hw, u8 pfc_mode, struct ice_sq_cd *cd)
+{
+ struct ice_aqc_set_query_pfc_mode *cmd;
+ struct ice_aq_desc desc;
+ enum ice_status status;
+
+ if (pfc_mode > ICE_AQC_PFC_DSCP_BASED_PFC)
+ return ICE_ERR_PARAM;
+
+ cmd = &desc.params.set_query_pfc_mode;
+
+ ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_pfc_mode);
+
+ cmd->pfc_mode = pfc_mode;
+
+ status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
+ if (status)
+ return status;
+
+ /* The spec isn't clear about whether the FW will return an error code
+* if the PFC mode requested by the driver was not set. The spec just
+* says that the FW will write the PFC mode set back into cmd->pfc_mode,
+* so after the AQ has been executed, check if cmd->pfc_mode is what was
+* requested.
+*/
+ if (cmd->pfc_mode != pfc_mode)
+ return ICE_ERR_NOT_SUPPORTED;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_cee_to_dcb_cfg
* @cee_cfg: pointer to CEE configuration struct
diff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h
index a053adbb30..24c8da2dc8 100644
--- a/drivers/net/ice/base/ice_dcb.h
+++ b/drivers/net/ice/base/ice_dcb.h
@@ -196,6 +196,8 @@ enum ice_status
ice_aq_get_cee_dcb_cfg(struct ice_hw *hw,
struct ice_aqc_get_cee_dcb_cfg_resp *buff,
struct ice_sq_cd *cd);
+enum ice_status
+ice_aq_set_pfc_mode(struct ice_hw *hw, u8 pfc_mode, struct ice_sq_cd *cd);
enum ice_status ice_lldp_to_dcb_cfg(u8 *lldpmib, struct ice_dcbx_cfg *dcbcfg);
u8 ice_get_dcbx_status(struct ice_hw *hw);
enum ice_status
--
2.26.2
[dpdk-dev] [PATCH v3 00/32] add support for baseband phy
This series adds initial support for baseband PHY available on SOCs belonging to Fusion family. BPHY is a hardware block comprising accelerators and DSPs specifically tailored for 5G/LTE inline usecases. This series introduces two rawdev PMDs along with low level common code. CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to BPHY via standard enqueue/dequeue operations. BPHY PMD provides an out-of-band access to PCI device BARs and a set of experimental APIs allowing one to setup custom IRQs handlers. This functionality is backed by kernel module using ioctl() mechanism. Series has nothing to do with 5G/LTE baseband protocol processing. v3: - append pmd to list of cnxk drivers (cnxk.rst) - fix typo - fix line length so it is under 80 characters - shorten release notes v2: - change some errors to more relevant ones (-EINVAL/-ENODEV) - fix MAINTAINERS styling issues - fix dpdk-devbind.py - fix meson.build styling issues - fix warning related to possibly uninitialized scr0 variable - fix warning related to unused function - improve documentation - improve enums items naming - spread documentation across relevant patches Tomasz Duszynski (32): common/cnxk: add bphy cgx/rpm initialization and cleanup common/cnxk: support for communication with atf common/cnxk: support for getting link information common/cnxk: support for changing internal loopback common/cnxk: support for changing ptp mode common/cnxk: support for setting link mode common/cnxk: support for changing link state common/cnxk: support for lmac start/stop raw/cnxk_bphy: add bphy cgx/rpm skeleton driver raw/cnxk_bphy: support for reading queue configuration raw/cnxk_bphy: support for reading queue count raw/cnxk_bphy: support for enqueue operation raw/cnxk_bphy: support for dequeue operation raw/cnxk_bphy: support for performing selftest common/cnxk: support for device init and fini common/cnxk: support for baseband PHY irq setup common/cnxk: support for checking irq availability common/cnxk: support for retrieving irq stack common/cnxk: support for removing irq stack common/cnxk: support for setting bphy irq handler common/cnxk: support for clearing bphy irq handler common/cnxk: support for registering bphy irq raw/cnxk_bphy: add baseband PHY skeleton driver raw/cnxk_bphy: support for reading bphy queue configuration raw/cnxk_bphy: support for reading bphy queue count raw/cnxk_bphy: support for bphy enqueue operation raw/cnxk_bphy: support for bphy dequeue operation raw/cnxk_bphy: support for interrupt init and cleanup raw/cnxk_bphy: support for reading number of bphy irqs raw/cnxk_bphy: support for retrieving bphy device memory raw/cnxk_bphy: support for registering bphy irq handlers raw/cnxk_bphy: support for bphy selftest MAINTAINERS| 7 +- doc/guides/platform/cnxk.rst | 3 + doc/guides/rawdevs/cnxk_bphy.rst | 154 doc/guides/rawdevs/index.rst | 1 + doc/guides/rel_notes/release_21_08.rst | 7 + drivers/common/cnxk/meson.build| 3 + drivers/common/cnxk/roc_api.h | 7 + drivers/common/cnxk/roc_bphy.c | 40 ++ drivers/common/cnxk/roc_bphy.h | 17 + drivers/common/cnxk/roc_bphy_cgx.c | 397 +++ drivers/common/cnxk/roc_bphy_cgx.h | 120 ++ drivers/common/cnxk/roc_bphy_cgx_priv.h| 131 +++ drivers/common/cnxk/roc_bphy_irq.c | 422 + drivers/common/cnxk/roc_bphy_irq.h | 49 +++ drivers/common/cnxk/roc_idev.c | 1 + drivers/common/cnxk/roc_idev_priv.h| 2 + drivers/common/cnxk/roc_io.h | 9 + drivers/common/cnxk/roc_io_generic.h | 5 + drivers/common/cnxk/roc_priv.h | 3 + drivers/common/cnxk/version.map| 22 ++ drivers/raw/cnxk_bphy/cnxk_bphy.c | 329 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 321 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h | 10 + drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 100 + drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 41 ++ drivers/raw/cnxk_bphy/meson.build | 12 + drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 233 drivers/raw/cnxk_bphy/version.map | 3 + drivers/raw/meson.build| 1 + usertools/dpdk-devbind.py | 6 +- 31 files changed, 2660 insertions(+), 2 deletions(-) create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst create mode 100644 drivers/common/cnxk/roc_bphy.c create mode 100644 drivers/common/cnxk/roc_bphy.h create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h create mode 100644 drivers/common/cnxk/roc_bphy_irq.c create mode
[dpdk-dev] [PATCH v3 02/32] common/cnxk: support for communication with atf
Messages can be exchanged between userspace software and firmware
via set of two dedicated registers, namely scratch1 and scratch0.
scratch1 acts as a command register i.e message is sent to firmware,
while scratch0 holds response to previously sent message.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 146
drivers/common/cnxk/roc_bphy_cgx.h | 4 +
drivers/common/cnxk/roc_bphy_cgx_priv.h | 54 +
drivers/common/cnxk/roc_priv.h | 3 +
4 files changed, 207 insertions(+)
create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 029d4102e..7fedf5462 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -2,8 +2,13 @@
* Copyright(C) 2021 Marvell.
*/
+#include
+
#include "roc_api.h"
+#include "roc_priv.h"
+#define CGX_CMRX_INT 0x40
+#define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
/*
* CN10K stores number of lmacs in 4 bit filed
* in contraty to CN9K which uses only 3 bits.
@@ -15,6 +20,8 @@
*/
#define CGX_CMRX_RX_LMACS 0x128
#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+#define CGX_CMRX_SCRATCH0 0x1050
+#define CGX_CMRX_SCRATCH1 0x1058
static uint64_t
roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
@@ -25,6 +32,138 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t
lmac, uint64_t offset)
return plt_read64(base + (lmac << shift) + offset);
}
+static void
+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t
offset,
+ uint64_t value)
+{
+ int shift = roc_model_is_cn10k() ? 20 : 18;
+ uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+ plt_write64(value, base + (lmac << shift) + offset);
+}
+
+static void
+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+uint64_t *scr0)
+{
+ uint64_t val;
+
+ /* clear interrupt */
+ val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
+ val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
+ roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
+
+ /* ack fw response */
+ *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
+ roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
+}
+
+static int
+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int
lmac,
+ uint64_t *scr0)
+{
+ int tries = 5000;
+ uint64_t scr1;
+
+ do {
+ *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+ scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+ if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+ FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
+ break;
+
+ /* clear async events if any */
+ if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
+ ETH_EVT_ASYNC &&
+ FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+ roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+ plt_delay_ms(1);
+ } while (--tries);
+
+ return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ uint64_t *scr0)
+{
+ int tries = 5000;
+ uint64_t scr1;
+
+ do {
+ *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+ scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+ if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+ FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+ break;
+
+ plt_delay_ms(1);
+ } while (--tries);
+
+ return tries ? 0 : -ETIMEDOUT;
+}
+
+static int __rte_unused
+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ uint64_t scr1, uint64_t *scr0)
+{
+ uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
+ int ret;
+
+ pthread_mutex_lock(&roc_cgx->lock);
+
+ /* wait for ownership */
+ ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
+ if (ret) {
+ plt_err("timed out waiting for ownership");
+ goto out;
+ }
+
+ /* write command */
+ scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
+ roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
+
+ /* wait for command ack */
+ ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
+ if (ret) {
+ plt_err("timed out waiting for response");
+ goto out;
+ }
+
+ if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
+ goto out;
+
+ if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_
[dpdk-dev] [PATCH v3 01/32] common/cnxk: add bphy cgx/rpm initialization and cleanup
Add support for low level initialization and cleanup of baseband
phy cgx/rpm blocks.
Initialization and cleanup are related hence are in the same patch.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/meson.build| 1 +
drivers/common/cnxk/roc_api.h | 3 ++
drivers/common/cnxk/roc_bphy_cgx.c | 62 ++
drivers/common/cnxk/roc_bphy_cgx.h | 20 ++
drivers/common/cnxk/version.map| 2 +
5 files changed, 88 insertions(+)
create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7ab..59975fd34 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
deps = ['eal', 'pci', 'bus_pci', 'mbuf']
sources = files(
+'roc_bphy_cgx.c',
'roc_dev.c',
'roc_idev.c',
'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13f0..256d8c68d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -100,4 +100,7 @@
/* Idev */
#include "roc_idev.h"
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
#endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644
index 0..029d4102e
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS 0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+ int shift = roc_model_is_cn10k() ? 20 : 18;
+ uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+ return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+ uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+GENMASK_ULL(25, 24);
+
+ return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+ uint64_t val;
+
+ if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+ return -EINVAL;
+
+ val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+ val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+ if (roc_model_is_cn9k())
+ val = GENMASK_ULL(val - 1, 0);
+ roc_cgx->lmac_bmap = val;
+ roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+ return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+ if (!roc_cgx)
+ return -EINVAL;
+
+ return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644
index 0..aac2c262c
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+ uint64_t bar0_pa;
+ void *bar0_va;
+ uint64_t lmac_bmap;
+ unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83a6..1db4d104a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -9,6 +9,8 @@ INTERNAL {
cnxk_logtype_sso;
cnxk_logtype_tim;
cnxk_logtype_tm;
+ roc_bphy_cgx_dev_fini;
+ roc_bphy_cgx_dev_init;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 03/32] common/cnxk: support for getting link information
Add support for retrieving link information.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 40 +-
drivers/common/cnxk/roc_bphy_cgx.h | 70 +
drivers/common/cnxk/roc_bphy_cgx_priv.h | 9
drivers/common/cnxk/version.map | 1 +
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 7fedf5462..807bb1492 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -106,7 +106,7 @@ roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return tries ? 0 : -ETIMEDOUT;
}
-static int __rte_unused
+static int
roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
uint64_t scr1, uint64_t *scr0)
{
@@ -206,3 +206,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
return 0;
}
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return (lmac < MAX_LMACS_PER_CGX) &&
+ (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ struct roc_bphy_cgx_link_info *info)
+{
+ uint64_t scr1, scr0;
+ int ret;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ if (!info)
+ return -EINVAL;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+ ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+ if (ret)
+ return ret;
+
+ info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+ info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+ info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+ info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+ info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+ info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+ return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index 37b5c2742..641650d66 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -9,6 +9,8 @@
#include "roc_api.h"
+#define MAX_LMACS_PER_CGX 4
+
struct roc_bphy_cgx {
uint64_t bar0_pa;
void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
pthread_mutex_t lock;
} __plt_cache_aligned;
+enum roc_bphy_cgx_eth_link_speed {
+ ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+ ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+ __ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+ ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+ ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+ ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+ __ROC_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+ ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+ ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+ __ROC_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct roc_bphy_cgx_link_info {
+ bool link_up;
+ bool full_duplex;
+ enum roc_bphy_cgx_eth_link_speed speed;
+ bool
[dpdk-dev] [PATCH v3 04/32] common/cnxk: support for changing internal loopback
Add support for enabling or disabling internal loopback.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 30 +
drivers/common/cnxk/roc_bphy_cgx.h | 4
drivers/common/cnxk/roc_bphy_cgx_priv.h | 4
drivers/common/cnxk/version.map | 2 ++
4 files changed, 40 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 807bb1492..9fac3667f 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -214,6 +214,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac)
(roc_cgx->lmac_bmap & BIT_ULL(lmac));
}
+static int
+roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ bool enable)
+{
+ uint64_t scr1, scr0;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
+ FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+ return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
int
roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
struct roc_bphy_cgx_link_info *info)
@@ -244,3 +262,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return 0;
}
+
+int
+roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index 641650d66..970122845 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx
*roc_cgx);
__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
+__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c0550ae87..cb59cac09 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -8,6 +8,7 @@
/* REQUEST ID types. Input to firmware */
enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
+ ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_INTF_SHUTDOWN = 12,
};
@@ -58,6 +59,9 @@ enum eth_cmd_own {
/* struct eth_cmd */
#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
+/* struct eth_ctl_args */
+#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
+
#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
#endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 466207f9d..71437a6c5 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -12,6 +12,8 @@ INTERNAL {
roc_bphy_cgx_dev_fini;
roc_bphy_cgx_dev_init;
roc_bphy_cgx_get_linkinfo;
+ roc_bphy_cgx_intlbk_disable;
+ roc_bphy_cgx_intlbk_enable;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 05/32] common/cnxk: support for changing ptp mode
Add support for enabling or disablig ptp mode.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 33 +
drivers/common/cnxk/roc_bphy_cgx.h | 5
drivers/common/cnxk/roc_bphy_cgx_priv.h | 1 +
drivers/common/cnxk/version.map | 2 ++
4 files changed, 41 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 9fac3667f..a2da80284 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -232,6 +232,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
}
+static int
+roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ bool enable)
+{
+ uint64_t scr1, scr0;
+
+ if (roc_model_is_cn10k())
+ return -ENOTSUP;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
+ FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+ return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
int
roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
struct roc_bphy_cgx_link_info *info)
@@ -274,3 +295,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac)
{
return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
}
+
+int
+roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index 970122845..992e2d3ed 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx
*roc_cgx,
unsigned int lmac);
__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
+
#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cb59cac09..4e86ae4ea 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -10,6 +10,7 @@ enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_INTF_SHUTDOWN = 12,
+ ETH_CMD_SET_PTP_MODE = 34,
};
/* event types - cause of interrupt */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 71437a6c5..205a0602b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -14,6 +14,8 @@ INTERNAL {
roc_bphy_cgx_get_linkinfo;
roc_bphy_cgx_intlbk_disable;
roc_bphy_cgx_intlbk_enable;
+ roc_bphy_cgx_ptp_rx_disable;
+ roc_bphy_cgx_ptp_rx_enable;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 06/32] common/cnxk: support for setting link mode
Add support for setting link mode.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 28
drivers/common/cnxk/roc_bphy_cgx.h | 11 +
drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +
drivers/common/cnxk/version.map | 1 +
4 files changed, 101 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index a2da80284..09d988b1b 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -284,6 +284,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return 0;
}
+int
+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ struct roc_bphy_cgx_link_mode *mode)
+{
+ uint64_t scr1, scr0;
+
+ if (roc_model_is_cn10k())
+ return -ENOTSUP;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ if (!mode)
+ return -EINVAL;
+
+ scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
+ FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
+ FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
+ FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
+ FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+ FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
+
+ return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
int
roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
{
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index 992e2d3ed..b9a6e0be0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
};
+struct roc_bphy_cgx_link_mode {
+ bool full_duplex;
+ bool an;
+ unsigned int port;
+ enum roc_bphy_cgx_eth_link_speed speed;
+ enum roc_bphy_cgx_eth_link_mode mode;
+};
+
struct roc_bphy_cgx_link_info {
bool link_up;
bool full_duplex;
@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx
*roc_cgx);
__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac,
+struct roc_bphy_cgx_link_mode *mode);
__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac);
__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 4e86ae4ea..ee7578423 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -5,10 +5,64 @@
#ifndef _ROC_BPHY_CGX_PRIV_H_
#define _ROC_BPHY_CGX_PRIV_H_
+/* LINK speed types */
+enum eth_link_speed {
+ ETH_LINK_NONE,
+ ETH_LINK_10M,
+ ETH_LINK_100M,
+ ETH_LINK_1G,
+ ETH_LINK_2HG, /* 2.5 Gbps */
+ ETH_LINK_5G,
+ ETH_LINK_10G,
+ ETH_LINK_20G,
+ ETH_LINK_25G,
+ ETH_LINK_40G,
+ ETH_LINK_50G,
+ ETH_LINK_80G,
+ ETH_LINK_100G,
+ ETH_LINK_MAX,
+};
+
+/* Supported LINK MODE enums
+ * Each link mode is a bit mask of these
+ * enums which are represented as bits
+ */
+enum eth_mode {
+ ETH_MODE_SGMII_BIT = 0,
+ ETH_MODE_1000_BASEX_BIT,
+ ETH_MODE_QSGMII_BIT,
+ ETH_MODE_10G_C2C_BIT,
+ ETH_MODE_10G_C2M_BIT,
+ ETH_MODE_10G_KR_BIT, /* = 5 */
+ ETH_MODE_20G_C2C_BIT,
+ ETH_MODE_25G_C2C_BIT,
+ ETH_MODE_25G_C2M_BIT,
+ ETH_MODE_25G_2_C2C_BIT,
+ ETH_MODE_25G_CR_BIT, /* = 10 */
+ ETH_MODE_25G_KR_BIT,
+ ETH_MODE_40G_C2C_BIT,
+ ETH_MODE_40G_C2M_BIT,
+ ETH_MODE_40G_CR4_BIT,
+ ETH_MODE_40G_KR4_BIT, /* = 15 */
+ ETH_MODE_40GAUI_C2C_BIT,
+ ETH_MODE_50G_C2C_BIT,
+ ETH_MODE_50G_C2M_BIT,
+ ETH_MODE_50G_4_C2C_BIT,
+ ETH_MODE_50G_CR_BIT, /* = 20 */
+ ETH_MODE_50G_KR_BIT,
+ ETH_MODE_80GAUI_C2C_BIT,
+ ETH_MODE_100G_C2C_BIT,
+ ETH_MODE_100G_C2M_BIT,
+ ETH_MODE_100G_CR4_BIT, /* = 25 */
+ ETH_MODE_100G_KR4_BIT,
+ ETH_MODE_MAX_BIT /* = 27 */
+};
+
/* REQUEST ID types. Input to firmware */
enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
ETH_CMD_INTERNAL_LBK = 7,
+ ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
ETH_CMD_I
[dpdk-dev] [PATCH v3 08/32] common/cnxk: support for lmac start/stop
Add support for starting or stopping specific lmac. Start enables rx/tx
traffic while stop does the opposite.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 42 ++
drivers/common/cnxk/roc_bphy_cgx.h | 4 +++
drivers/common/cnxk/version.map| 2 ++
3 files changed, 48 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 978dbda82..056a3db47 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -7,6 +7,9 @@
#include "roc_api.h"
#include "roc_priv.h"
+#define CGX_CMRX_CONFIG 0x00
+#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
+#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
#define CGX_CMRX_INT 0x40
#define CGX_CMRX_INT_OVERFLW BIT_ULL(1)
/*
@@ -214,6 +217,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac)
(roc_cgx->lmac_bmap & BIT_ULL(lmac));
}
+static int
+roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+bool start)
+{
+ uint64_t val;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ pthread_mutex_lock(&roc_cgx->lock);
+ val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
+ val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
+CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
+
+ if (start)
+ val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
+ FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
+
+ roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
+ pthread_mutex_unlock(&roc_cgx->lock);
+
+ return 0;
+}
+
static int
roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
bool enable)
@@ -253,6 +283,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
}
+int
+roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+ return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
+}
+
int
roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
bool state)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index ab6239202..49c35a1e6 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info {
__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac);
+__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
+unsigned int lmac);
__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac, bool state);
__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7766f52e0..0ad805dba 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,8 @@ INTERNAL {
roc_bphy_cgx_ptp_rx_enable;
roc_bphy_cgx_set_link_mode;
roc_bphy_cgx_set_link_state;
+ roc_bphy_cgx_start_rxtx;
+ roc_bphy_cgx_stop_rxtx;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 07/32] common/cnxk: support for changing link state
Add support for setting link up or down.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_cgx.c | 18 ++
drivers/common/cnxk/roc_bphy_cgx.h | 2 ++
drivers/common/cnxk/roc_bphy_cgx_priv.h | 2 ++
drivers/common/cnxk/version.map | 1 +
4 files changed, 23 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c
b/drivers/common/cnxk/roc_bphy_cgx.c
index 09d988b1b..978dbda82 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -253,6 +253,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
}
+int
+roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+ bool state)
+{
+ uint64_t scr1, scr0;
+
+ if (!roc_cgx)
+ return -EINVAL;
+
+ if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+ return -ENODEV;
+
+ scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
+ FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
+
+ return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
int
roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
struct roc_bphy_cgx_link_info *info)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h
b/drivers/common/cnxk/roc_bphy_cgx.h
index b9a6e0be0..ab6239202 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info {
__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
+ unsigned int lmac, bool state);
__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
unsigned int lmac,
struct roc_bphy_cgx_link_info *info);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h
b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index ee7578423..71a277fff 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -61,6 +61,8 @@ enum eth_mode {
/* REQUEST ID types. Input to firmware */
enum eth_cmd_id {
ETH_CMD_GET_LINK_STS = 4,
+ ETH_CMD_LINK_BRING_UP = 5,
+ ETH_CMD_LINK_BRING_DOWN = 6,
ETH_CMD_INTERNAL_LBK = 7,
ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
ETH_CMD_INTF_SHUTDOWN = 12,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 15a6d3a3b..7766f52e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,7 @@ INTERNAL {
roc_bphy_cgx_ptp_rx_disable;
roc_bphy_cgx_ptp_rx_enable;
roc_bphy_cgx_set_link_mode;
+ roc_bphy_cgx_set_link_state;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 10/32] raw/cnxk_bphy: support for reading queue configuration
Add support for reading queue configuration. Single queue represents
a logical mac available on rpm/cgx.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index e537888f9..016f9f02c 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len,
pci_dev->addr.devid, pci_dev->addr.function);
}
+static int
+cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+rte_rawdev_obj_t queue_conf,
+size_t queue_conf_size)
+{
+ unsigned int *conf;
+
+ RTE_SET_USED(dev);
+ RTE_SET_USED(queue_id);
+
+ if (queue_conf_size != sizeof(*conf))
+ return -EINVAL;
+
+ conf = (unsigned int *)queue_conf;
+ *conf = 1;
+
+ return 0;
+}
+
static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+ .queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
};
static void
--
2.25.1
[dpdk-dev] [PATCH v3 09/32] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
Add baseband phy cgx/rpm skeleton driver which merely probes a matching
device. CGX/RPM are Ethernet MACs hardwired to baseband subsystem.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
MAINTAINERS| 7 +-
doc/guides/platform/cnxk.rst | 3 +
doc/guides/rawdevs/cnxk_bphy.rst | 23
doc/guides/rawdevs/index.rst | 1 +
doc/guides/rel_notes/release_21_08.rst | 7 ++
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 +
drivers/raw/cnxk_bphy/meson.build | 8 ++
drivers/raw/cnxk_bphy/version.map | 3 +
drivers/raw/meson.build| 1 +
usertools/dpdk-devbind.py | 4 +-
10 files changed, 206 insertions(+), 2 deletions(-)
create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
create mode 100644 drivers/raw/cnxk_bphy/meson.build
create mode 100644 drivers/raw/cnxk_bphy/version.map
diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a1697..4f533fcdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1287,6 +1287,12 @@ M: Nipun Gupta
F: drivers/raw/dpaa2_cmdif/
F: doc/guides/rawdevs/dpaa2_cmdif.rst
+Marvell CNXK BPHY
+M: Jakub Palider
+M: Tomasz Duszynski
+F: doc/guides/rawdevs/cnxk_bphy.rst
+F: drivers/raw/cnxk_bphy/
+
Marvell OCTEON TX2 DMA
M: Radha Mohan Chintakuntla
M: Veerasenareddy Burru
@@ -1307,7 +1313,6 @@ F: doc/guides/rawdevs/ntb.rst
F: examples/ntb/
F: doc/guides/sample_app_ug/ntb.rst
-
Packet processing
-
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index cebb3d08a..a6ba42249 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -145,6 +145,9 @@ This section lists dataplane H/W block(s) available in cnxk
SoC.
#. **Mempool Driver**
See :doc:`../mempool/cnxk` for NPA mempool driver information.
+#. **Baseband PHY Driver**
+ See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.
+
Procedure to Setup Platform
---
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
new file mode 100644
index 0..96ab68435
--- /dev/null
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -0,0 +1,23 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2021 Marvell.
+
+Marvell CNXK BPHY Driver
+
+
+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
+set of hardware accelerators for performing baseband related operations.
+Connectivity to the outside world happens through a block called RFOE which is
+backed by ethernet I/O block called CGX or RPM (depending on the chip version).
+RFOE stands for Radio Frequency Over Ethernet and provides support for
+IEEE 1904.3 (RoE) standard.
+
+Device Setup
+
+
+The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for
+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
+view the state of the devices and to bind them to a suitable DPDK-supported
+kernel driver. When querying the status of the devices, they will appear under
+the category of "Misc (rawdev) devices", i.e. the command
+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
+devices alone.
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index f64ec4427..7fbae40ea 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -11,6 +11,7 @@ application through rawdev API.
:maxdepth: 2
:numbered:
+cnxk_bphy
dpaa2_cmdif
dpaa2_qdma
ifpga
diff --git a/doc/guides/rel_notes/release_21_08.rst
b/doc/guides/rel_notes/release_21_08.rst
index a6ecfdf3c..d3f4d6847 100644
--- a/doc/guides/rel_notes/release_21_08.rst
+++ b/doc/guides/rel_notes/release_21_08.rst
@@ -55,6 +55,13 @@ New Features
Also, make sure to start the actual text at the margin.
===
+* **Added Baseband phy CNXK PMD.**
+
+ Added Baseband phy PMD which allows to configure BPHY hardware block
+ comprising accelerators and DSPs specifically tailored for 5G/LTE inline
+ usecases. Configuration happens via standard rawdev enq/deq operations. See
+ the :doc:`../rawdevs/cnxk_bphy` rawdev guide for more details on this driver.
+
Removed Items
-
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
new file mode 100644
index 0..e537888f9
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include
+#include
+#include
+
+#include
+
+struct cnxk_bphy_cgx_queue {
+ unsigned int lmac;
+ /* queue holds up to one response */
+ void *rsp;
+};
+
+struct cnxk_bphy_cgx {
+ struct roc_bphy_cgx *rcgx;
+ struct cnxk_bphy_cgx_queue queues
[dpdk-dev] [PATCH v3 11/32] raw/cnxk_bphy: support for reading queue count
Add support for reading number of available queues i.e number
of available logical macs (LMACs).
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 4
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +
2 files changed, 13 insertions(+)
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 96ab68435..d6803e527 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -21,3 +21,7 @@ kernel driver. When querying the status of the devices, they
will appear under
the category of "Misc (rawdev) devices", i.e. the command
``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
devices alone.
+
+Before performing actual data transfer one needs to first retrieve number of
+available queues with ``rte_rawdev_queue_count()`` and capacity of each
+using ``rte_rawdev_queue_conf_get()``.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 016f9f02c..da4372642 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev,
uint16_t queue_id,
return 0;
}
+static uint16_t
+cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
+{
+ struct cnxk_bphy_cgx *cgx = dev->dev_private;
+
+ return cgx->num_queues;
+}
+
static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+ .queue_count = cnxk_bphy_cgx_queue_count,
};
static void
--
2.25.1
[dpdk-dev] [PATCH v3 12/32] raw/cnxk_bphy: support for enqueue operation
Add support for enqueueing messages.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 68
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++
drivers/raw/cnxk_bphy/meson.build | 1 +
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 104
4 files changed, 285 insertions(+)
create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index d6803e527..0d842a831 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -11,6 +11,13 @@ backed by ethernet I/O block called CGX or RPM (depending on
the chip version).
RFOE stands for Radio Frequency Over Ethernet and provides support for
IEEE 1904.3 (RoE) standard.
+Features
+
+
+The BPHY CGX/RPM implements following features in the rawdev API:
+
+- Access to BPHY CGX/RPM via a set of predefined messages
+
Device Setup
@@ -25,3 +32,64 @@ devices alone.
Before performing actual data transfer one needs to first retrieve number of
available queues with ``rte_rawdev_queue_count()`` and capacity of each
using ``rte_rawdev_queue_conf_get()``.
+
+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
+responses hence dequeueing is not always necessary.
+
+BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by
type and payload.
+Message types along with description are listed below.
+
+Get link information
+
+
+Message is used to get information about link state.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO``. In
response one will
+get message containing payload i.e ``struct cnxk_bphy_cgx_msg_link_info``
filled with information
+about current link state.
+
+Change internal loopback state
+~~
+
+Message is used to enable or disable internal loopback.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal
loopback while the latter
+will do the opposite.
+
+Change PTP RX state
+~~~
+
+Message is used to enable or disable PTP mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE``. Former will enable PTP while the
latter will do the
+opposite.
+
+Set link mode
+~
+
+Message is used to change link mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE``. Prior
to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_link_mode`` needs to be filled
with relevant
+information.
+
+Change link state
+~
+
+Message is used to set link up or down.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE``. Prior
to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_set_link_state`` needs to be
filled with relevant
+information.
+
+Start or stop RX/TX
+~~~
+
+Message is used to start or stop accepting traffic.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
+``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the
latter will
+do the opposite.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(C) 2021 Marvell.
*/
+#include
+
#include
#include
#include
#include
+#include "rte_pmd_bphy.h"
+
struct cnxk_bphy_cgx_queue {
unsigned int lmac;
/* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev,
uint16_t queue_id,
return 0;
}
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+ struct rte_rawdev_buf *buf)
+{
+ struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+ struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+ struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+ struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+ struct cnxk_bphy_cgx_msg_link_info *link_info;
+ struct roc_bphy_cgx_link_info rlink_info;
+ struct roc_bphy_cgx_link_mode rlink_mode;
+ unsigned int lmac = qp->lmac;
+ void *rsp = NULL;
+ int ret;
+
+ switch (msg->type) {
+ case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+ memset(&rlink_info, 0, sizeof(rlink_info));
+ ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+ if (ret)
+ break;
+
+ link_info = rte_zmalloc(NULL, sizeof(*link_info
[dpdk-dev] [PATCH v3 13/32] raw/cnxk_bphy: support for dequeue operation
Add support for dequeueing responses to previously
enqueued messages.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 637514406..a8eafae1b 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
return 1;
}
+static int
+cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev,
+ struct rte_rawdev_buf **buffers, unsigned int count,
+ rte_rawdev_obj_t context)
+{
+ struct cnxk_bphy_cgx *cgx = dev->dev_private;
+ unsigned int queue = (size_t)context;
+ struct cnxk_bphy_cgx_queue *qp;
+
+ if (queue >= cgx->num_queues)
+ return -EINVAL;
+
+ if (count == 0)
+ return 0;
+
+ qp = &cgx->queues[queue];
+ if (qp->rsp) {
+ buffers[0]->buf_addr = qp->rsp;
+ qp->rsp = NULL;
+
+ return 1;
+ }
+
+ return 0;
+}
+
static uint16_t
cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
{
@@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
+ .dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
.queue_count = cnxk_bphy_cgx_queue_count,
};
--
2.25.1
[dpdk-dev] [PATCH v3 14/32] raw/cnxk_bphy: support for performing selftest
Add support for performing selftest operation.
Signed-off-by: Tomasz Duszynski
Signed-off-by: Jakub Palider
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 19 +-
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 2 +
drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h | 10 +
drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +
drivers/raw/cnxk_bphy/meson.build | 1 +
5 files changed, 237 insertions(+), 1 deletion(-)
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 0d842a831..120f953fb 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -38,7 +38,8 @@ To perform data transfer use standard
``rte_rawdev_enqueue_buffers()`` and
responses hence dequeueing is not always necessary.
BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by
type and payload.
-Message types along with description are listed below.
+Message types along with description are listed below. As for the usage
examples please refer to
+``cnxk_bphy_cgx_dev_selftest()``.
Get link information
@@ -93,3 +94,19 @@ Message is used to start or stop accepting traffic.
Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the
latter will
do the opposite.
+
+Self test
+-
+
+On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+the raw devices. The rawdev ID of the device can be obtained using invocation
+of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
+
+- NAME is the desired subsystem: use "BPHY_CGX" for
+ RFOE module,
+- x is the device's bus id specified in "bus:device.func" (BDF) format.
+
+Use this identifier for further rawdev function calls.
+
+The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
+functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index a8eafae1b..3da224414 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -9,6 +9,7 @@
#include
+#include "cnxk_bphy_cgx.h"
#include "rte_pmd_bphy.h"
struct cnxk_bphy_cgx_queue {
@@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops
= {
.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
.queue_count = cnxk_bphy_cgx_queue_count,
+ .dev_selftest = cnxk_bphy_cgx_dev_selftest,
};
static void
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
new file mode 100644
index 0..fb6b31bf4
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_CGX_H_
+#define _CNXK_BPHY_CGX_H_
+
+int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id);
+
+#endif /* _CNXK_BPHY_CGX_H_ */
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
new file mode 100644
index 0..cb4dd4b22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include
+
+#include
+#include
+#include
+#include
+
+#include "cnxk_bphy_cgx.h"
+#include "rte_pmd_bphy.h"
+
+static int
+cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg)
+{
+ struct rte_rawdev_buf *bufs[1];
+ struct rte_rawdev_buf buf;
+ void *q;
+ int ret;
+
+ q = (void *)(size_t)queue;
+ buf.buf_addr = msg;
+ bufs[0] = &buf;
+
+ ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ return 0;
+}
+
+static int
+cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg)
+{
+ struct rte_rawdev_buf *bufs[1];
+ struct rte_rawdev_buf buf;
+ void *q;
+ int ret;
+
+ q = (void *)(size_t)queue;
+ bufs[0] = &buf;
+
+ ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q);
+ if (ret < 0)
+ return ret;
+ if (ret != 1)
+ return -EIO;
+
+ *msg = buf.buf_addr;
+
+ return 0;
+}
+
+static int
+cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond)
+{
+ int tries = 10, ret;
+
+ do {
+ struct cnxk_bphy_cgx_msg_link_info *link_info = NULL;
+ struct cnxk_bphy_cgx_msg msg;
+
+ msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO;
+ ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg);
+ if (ret)
+ return ret;
+
+ ret = cnxk_bphy_
[dpdk-dev] [PATCH v3 15/32] common/cnxk: support for device init and fini
Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/meson.build | 1 +
drivers/common/cnxk/roc_api.h | 4 +++
drivers/common/cnxk/roc_bphy.c | 40 +
drivers/common/cnxk/roc_bphy.h | 17
drivers/common/cnxk/roc_idev.c | 1 +
drivers/common/cnxk/roc_idev_priv.h | 2 ++
drivers/common/cnxk/version.map | 2 ++
7 files changed, 67 insertions(+)
create mode 100644 drivers/common/cnxk/roc_bphy.c
create mode 100644 drivers/common/cnxk/roc_bphy.h
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 59975fd34..946b98f46 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
deps = ['eal', 'pci', 'bus_pci', 'mbuf']
sources = files(
+'roc_bphy.c',
'roc_bphy_cgx.c',
'roc_dev.c',
'roc_idev.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 256d8c68d..dd0047873 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -50,6 +50,7 @@
#define PCI_DEVID_CNXK_EP_VF 0xB203
#define PCI_DEVID_CNXK_RVU_SDP_PF 0xA0f6
#define PCI_DEVID_CNXK_RVU_SDP_VF 0xA0f7
+#define PCI_DEVID_CNXK_BPHY 0xA089
#define PCI_DEVID_CN9K_CGX 0xA059
#define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
/* Baseband phy cgx */
#include "roc_bphy_cgx.h"
+/* Baseband phy */
+#include "roc_bphy.h"
+
#endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c
new file mode 100644
index 0..77606d646
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (!idev)
+ return -ENODEV;
+
+ if (!roc_bphy || !roc_bphy->pci_dev)
+ return -EINVAL;
+
+ idev->bphy = roc_bphy;
+
+ return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+ struct idev_cfg *idev;
+
+ idev = idev_get_cfg();
+ if (!idev)
+ return -ENODEV;
+
+ if (!roc_bphy)
+ return -EINVAL;
+
+ idev->bphy = NULL;
+
+ return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h
new file mode 100644
index 0..0579c6c44
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+ struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc04044..4d7b53422 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
idev->lmt_pf_func = 0;
idev->lmt_base_addr = 0;
idev->num_lmtlines = 0;
+ idev->bphy = NULL;
__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
}
diff --git a/drivers/common/cnxk/roc_idev_priv.h
b/drivers/common/cnxk/roc_idev_priv.h
index ff10a905c..384f667ea 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
/* Intra device related functions */
struct npa_lf;
+struct roc_bphy;
struct idev_cfg {
uint16_t sso_pf_func;
uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
uint16_t lmt_pf_func;
uint16_t num_lmtlines;
uint64_t lmt_base_addr;
+ struct roc_bphy *bphy;
};
/* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0ad805dba..25083d9d4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -20,6 +20,8 @@ INTERNAL {
roc_bphy_cgx_set_link_state;
roc_bphy_cgx_start_rxtx;
roc_bphy_cgx_stop_rxtx;
+ roc_bphy_dev_fini;
+ roc_bphy_dev_init;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 16/32] common/cnxk: support for baseband PHY irq setup
Add support for initializing baseband phy irqs. While at it
also add support for reverting back to the default state.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/meson.build| 1 +
drivers/common/cnxk/roc_bphy_irq.c | 96 ++
drivers/common/cnxk/roc_bphy_irq.h | 27 +
drivers/common/cnxk/version.map| 2 +
4 files changed, 126 insertions(+)
create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 946b98f46..c0ec54932 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf']
sources = files(
'roc_bphy.c',
'roc_bphy_cgx.c',
+'roc_bphy_irq.c',
'roc_dev.c',
'roc_idev.c',
'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
new file mode 100644
index 0..c57506542
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include
+#include
+#include
+
+#include "roc_api.h"
+#include "roc_bphy_irq.h"
+
+#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
+#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
+
+#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
+#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+
+struct roc_bphy_irq_chip *
+roc_bphy_intr_init(void)
+{
+ struct roc_bphy_irq_chip *irq_chip;
+ uint64_t max_irq, i, avail_irqs;
+ int fd, ret;
+
+ fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
+ if (fd < 0) {
+ plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
+ return NULL;
+ }
+
+ ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
+ if (ret < 0) {
+ plt_err("Failed to get max irq number via ioctl");
+ goto err_ioctl;
+ }
+
+ ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
+ if (ret < 0) {
+ plt_err("Failed to get available irqs bitmask via ioctl");
+ goto err_ioctl;
+ }
+
+ irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
+ if (irq_chip == NULL) {
+ plt_err("Failed to alloc irq_chip");
+ goto err_alloc_chip;
+ }
+
+ irq_chip->intfd = fd;
+ irq_chip->max_irq = max_irq;
+ irq_chip->avail_irq_bmask = avail_irqs;
+ irq_chip->irq_vecs =
+ plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
+ if (irq_chip->irq_vecs == NULL) {
+ plt_err("Failed to alloc irq_chip irq_vecs");
+ goto err_alloc_irq;
+ }
+
+ irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
+ if (irq_chip->mz_name == NULL) {
+ plt_err("Failed to alloc irq_chip name");
+ goto err_alloc_name;
+ }
+ plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
+ strlen(ROC_BPHY_MEMZONE_NAME) + 1);
+
+ for (i = 0; i < irq_chip->max_irq; i++) {
+ irq_chip->irq_vecs[i].fd = -1;
+ irq_chip->irq_vecs[i].handler_cpu = -1;
+ }
+
+ return irq_chip;
+
+err_alloc_name:
+ plt_free(irq_chip->irq_vecs);
+
+err_alloc_irq:
+ plt_free(irq_chip);
+
+err_ioctl:
+err_alloc_chip:
+ close(fd);
+ return NULL;
+}
+
+void
+roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
+{
+ if (irq_chip == NULL)
+ return;
+
+ close(irq_chip->intfd);
+ plt_free(irq_chip->mz_name);
+ plt_free(irq_chip->irq_vecs);
+ plt_free(irq_chip);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
new file mode 100644
index 0..b5200786b
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_IRQ_
+#define _ROC_BPHY_IRQ_
+
+struct roc_bphy_irq_vec {
+ int fd;
+ int handler_cpu;
+ void (*handler)(int irq_num, void *isr_data);
+ void *isr_data;
+};
+
+struct roc_bphy_irq_chip {
+ struct roc_bphy_irq_vec *irq_vecs;
+ uint64_t max_irq;
+ uint64_t avail_irq_bmask;
+ int intfd;
+ int n_handlers;
+ char *mz_name;
+};
+
+__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
+__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+
+#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 25083d9d4..483e52018 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6
[dpdk-dev] [PATCH v3 17/32] common/cnxk: support for checking irq availability
Add support for checking whether given irq is available.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 9 +
drivers/common/cnxk/roc_bphy_irq.h | 2 ++
drivers/common/cnxk/version.map| 1 +
3 files changed, 12 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index c57506542..bea2b7f73 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip->irq_vecs);
plt_free(irq_chip);
}
+
+bool
+roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
+{
+ if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
+ return false;
+
+ return irq_chip->avail_irq_bmask & BIT(irq_num);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
index b5200786b..f481f4456 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,5 +23,7 @@ struct roc_bphy_irq_chip {
__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
+ int irq_num);
#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 483e52018..427321c41 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
roc_bphy_cgx_stop_rxtx;
roc_bphy_dev_fini;
roc_bphy_dev_init;
+ roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_init;
roc_clk_freq_get;
--
2.25.1
[dpdk-dev] [PATCH v3 18/32] common/cnxk: support for retrieving irq stack
Add support for retrieving irq stack. If stack does not exist
then it gets created.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 62 ++
drivers/common/cnxk/roc_bphy_irq.h | 1 +
drivers/common/cnxk/version.map| 1 +
3 files changed, 64 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index bea2b7f73..04ad129ac 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -2,12 +2,21 @@
* Copyright(C) 2021 Marvell.
*/
#include
+#include
#include
+#include
#include
#include "roc_api.h"
#include "roc_bphy_irq.h"
+struct roc_bphy_irq_stack {
+ STAILQ_ENTRY(roc_bphy_irq_stack) entries;
+ void *sp_buffer;
+ int cpu;
+ int inuse;
+};
+
#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
@@ -15,6 +24,12 @@
#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
+ irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
+
+/* Note: it is assumed that as for now there is no multiprocess support */
+static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
+
struct roc_bphy_irq_chip *
roc_bphy_intr_init(void)
{
@@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip);
}
+void *
+roc_bphy_irq_stack_get(int cpu)
+{
+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
+#define IRQ_ISR_STACK_SIZE 0x20
+
+ struct roc_bphy_irq_stack *curr_stack;
+ void *retval = NULL;
+
+ if (pthread_mutex_lock(&stacks_mutex))
+ return NULL;
+
+ STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+ if (curr_stack->cpu == cpu) {
+ curr_stack->inuse++;
+ retval = ((char *)curr_stack->sp_buffer) +
+IRQ_ISR_STACK_SIZE;
+ goto found_stack;
+ }
+ }
+
+ curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
+ if (curr_stack == NULL)
+ goto err_stack;
+
+ curr_stack->sp_buffer =
+ plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
+ if (curr_stack->sp_buffer == NULL)
+ goto err_buffer;
+
+ curr_stack->cpu = cpu;
+ curr_stack->inuse = 0;
+ STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
+ retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
+
+found_stack:
+ pthread_mutex_unlock(&stacks_mutex);
+ return retval;
+
+err_buffer:
+ plt_free(curr_stack);
+
+err_stack:
+ pthread_mutex_unlock(&stacks_mutex);
+ return NULL;
+}
+
bool
roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
{
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
index f481f4456..e66b2aa7c 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void *roc_bphy_irq_stack_get(int cpu);
__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 427321c41..542364926 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -25,6 +25,7 @@ INTERNAL {
roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_init;
+ roc_bphy_irq_stack_get;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 19/32] common/cnxk: support for removing irq stack
Add support for removing existing irq stack.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 30 ++
drivers/common/cnxk/roc_bphy_irq.h | 1 +
drivers/common/cnxk/version.map| 1 +
3 files changed, 32 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index 04ad129ac..a90c055ff 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
plt_free(irq_chip);
}
+void
+roc_bphy_irq_stack_remove(int cpu)
+{
+ struct roc_bphy_irq_stack *curr_stack;
+
+ if (pthread_mutex_lock(&stacks_mutex))
+ return;
+
+ STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+ if (curr_stack->cpu == cpu)
+ break;
+ }
+
+ if (curr_stack == NULL)
+ goto leave;
+
+ if (curr_stack->inuse > 0)
+ curr_stack->inuse--;
+
+ if (curr_stack->inuse == 0) {
+ STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
+ entries);
+ plt_free(curr_stack->sp_buffer);
+ plt_free(curr_stack);
+ }
+
+leave:
+ pthread_mutex_unlock(&stacks_mutex);
+}
+
void *
roc_bphy_irq_stack_get(int cpu)
{
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
index e66b2aa7c..549a84a7d 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void roc_bphy_irq_stack_remove(int cpu);
__roc_api void *roc_bphy_irq_stack_get(int cpu);
__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 542364926..78601fe31 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -26,6 +26,7 @@ INTERNAL {
roc_bphy_intr_fini;
roc_bphy_intr_init;
roc_bphy_irq_stack_get;
+ roc_bphy_irq_stack_remove;
roc_clk_freq_get;
roc_error_msg_get;
roc_idev_lmt_base_addr_get;
--
2.25.1
[dpdk-dev] [PATCH v3 20/32] common/cnxk: support for setting bphy irq handler
Add support for setting custom baseband phy irq handler.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 121 +++
drivers/common/cnxk/roc_bphy_irq.h | 5 ++
drivers/common/cnxk/roc_io.h | 9 ++
drivers/common/cnxk/roc_io_generic.h | 5 ++
drivers/common/cnxk/version.map | 2 +
5 files changed, 142 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index a90c055ff..f988abf51 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -4,12 +4,22 @@
#include
#include
#include
+#include
#include
#include
#include "roc_api.h"
#include "roc_bphy_irq.h"
+#define roc_cpuset_t cpu_set_t
+
+struct roc_bphy_irq_usr_data {
+ uint64_t isr_base;
+ uint64_t sp;
+ uint64_t cpu;
+ uint64_t irq_num;
+};
+
struct roc_bphy_irq_stack {
STAILQ_ENTRY(roc_bphy_irq_stack) entries;
void *sp_buffer;
@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {
#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_SET_BPHY_HANDLER
\
+ _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)
return NULL;
}
+void
+roc_bphy_intr_handler(unsigned int irq_num)
+{
+ struct roc_bphy_irq_chip *irq_chip;
+ const struct plt_memzone *mz;
+
+ mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
+ if (mz == NULL)
+ return;
+
+ irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
+ if (irq_chip == NULL)
+ return;
+
+ if (irq_chip->irq_vecs[irq_num].handler != NULL)
+ irq_chip->irq_vecs[irq_num].handler(
+ (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
+
+ roc_atf_ret();
+}
+
+int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+void (*isr)(int irq_num, void *isr_data),
+void *isr_data)
+{
+ roc_cpuset_t orig_cpuset, intr_cpuset;
+ struct roc_bphy_irq_usr_data irq_usr;
+ const struct plt_memzone *mz;
+ int i, retval, curr_cpu, rc;
+ char *env;
+
+ mz = plt_memzone_lookup(chip->mz_name);
+ if (mz == NULL) {
+ /* what we want is just a pointer to chip, not object itself */
+ mz = plt_memzone_reserve_cache_align(chip->mz_name,
+sizeof(chip));
+ if (mz == NULL)
+ return -ENOMEM;
+ }
+
+ if (chip->irq_vecs[irq_num].handler != NULL)
+ return -EINVAL;
+
+ rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (rc < 0) {
+ plt_err("Failed to get affinity mask");
+ return rc;
+ }
+
+ for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
+ if (CPU_ISSET(i, &orig_cpuset))
+ curr_cpu = i;
+ if (curr_cpu < 0)
+ return -ENOENT;
+
+ CPU_ZERO(&intr_cpuset);
+ CPU_SET(curr_cpu, &intr_cpuset);
+ retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+ &intr_cpuset);
+ if (rc < 0) {
+ plt_err("Failed to set affinity mask");
+ return rc;
+ }
+
+ irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
+ irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
+ irq_usr.cpu = curr_cpu;
+ if (irq_usr.sp == 0) {
+ rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (rc < 0)
+ plt_err("Failed to restore affinity mask");
+ return rc;
+ }
+
+ /* On simulator memory locking operation takes much time. We want
+* to skip this when running in such an environment.
+*/
+ env = getenv("BPHY_INTR_MLOCK_DISABLE");
+ if (env == NULL) {
+ rc = mlockall(MCL_CURRENT | MCL_FUTURE);
+ if (rc < 0)
+ plt_warn("Failed to lock memory into RAM");
+ }
+
+ *((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
+ irq_usr.irq_num = irq_num;
+ chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
+ chip->irq_vecs[irq_num].handler = isr;
+ chip->irq_vecs[irq_num].isr_data = isr_data;
+ retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
+ if (retval != 0) {
+ roc_bphy_irq_stack_r
[dpdk-dev] [PATCH v3 21/32] common/cnxk: support for clearing bphy irq handler
Add support for clearing previously register baseband phy irq handler.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 66 ++
drivers/common/cnxk/roc_bphy_irq.h | 2 +
drivers/common/cnxk/version.map| 1 +
3 files changed, 69 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index f988abf51..4b87fc801 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -33,6 +33,7 @@ struct roc_bphy_irq_stack {
#define ROC_BPHY_IOC_MAGIC 0xF3
#define ROC_BPHY_IOC_SET_BPHY_HANDLER
\
_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
+#define ROC_BPHY_IOC_CLR_BPHY_HANDLER _IO(ROC_BPHY_IOC_MAGIC, 2)
#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
@@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip
*irq_chip, int irq_num)
return irq_chip->avail_irq_bmask & BIT(irq_num);
}
+
+int
+roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+{
+ roc_cpuset_t orig_cpuset, intr_cpuset;
+ const struct plt_memzone *mz;
+ int retval;
+
+ if (chip == NULL)
+ return -EINVAL;
+ if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
+ return -EINVAL;
+ if (!roc_bphy_intr_available(chip, irq_num))
+ return -ENOTSUP;
+ if (chip->irq_vecs[irq_num].handler == NULL)
+ return -EINVAL;
+ mz = plt_memzone_lookup(chip->mz_name);
+ if (mz == NULL)
+ return -ENXIO;
+
+ retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (retval < 0) {
+ plt_warn("Failed to get affinity mask");
+ CPU_ZERO(&orig_cpuset);
+ CPU_SET(0, &orig_cpuset);
+ }
+
+ CPU_ZERO(&intr_cpuset);
+ CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
+ retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+ &intr_cpuset);
+ if (retval < 0) {
+ plt_warn("Failed to set affinity mask");
+ CPU_ZERO(&orig_cpuset);
+ CPU_SET(0, &orig_cpuset);
+ }
+
+ retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
+ if (retval == 0) {
+ roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
+ chip->n_handlers--;
+ chip->irq_vecs[irq_num].isr_data = NULL;
+ chip->irq_vecs[irq_num].handler = NULL;
+ chip->irq_vecs[irq_num].handler_cpu = -1;
+ if (chip->n_handlers == 0) {
+ retval = plt_memzone_free(mz);
+ if (retval < 0)
+ plt_err("Failed to free memzone: irq %d",
+ irq_num);
+ }
+ } else {
+ plt_err("Failed to clear bphy interrupt handler");
+ }
+
+ retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (retval < 0) {
+ plt_warn("Failed to restore affinity mask");
+ CPU_ZERO(&orig_cpuset);
+ CPU_SET(0, &orig_cpuset);
+ }
+
+ return retval;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
index 7dd23f4ab..778764f68 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int
irq_num,
void *isr_data);
__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
int irq_num);
+__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
+int irq_num);
#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 861a97cc0..941055ba0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
roc_bphy_cgx_stop_rxtx;
roc_bphy_dev_fini;
roc_bphy_dev_init;
+ roc_bphy_handler_clear;
roc_bphy_intr_available;
roc_bphy_intr_fini;
roc_bphy_intr_handler;
--
2.25.1
[dpdk-dev] [PATCH v3 23/32] raw/cnxk_bphy: add baseband PHY skeleton driver
Add baseband phy skeleton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks. Note this driver isn't involved into
any sort baseband protocol processing. Instead it just provides means
for configuring hardware.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy.c | 113 ++
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 23 ++
drivers/raw/cnxk_bphy/meson.build | 1 +
usertools/dpdk-devbind.py | 4 +-
4 files changed, 140 insertions(+), 1 deletion(-)
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 0..cd26b9717
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+ {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+ {
+ .vendor_id = 0,
+ },
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+ snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+pci_dev->addr.bus, pci_dev->addr.devid,
+pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+ struct rte_pci_device *pci_dev)
+{
+ struct bphy_device *bphy_dev = NULL;
+ char name[RTE_RAWDEV_NAME_MAX_LEN];
+ struct rte_rawdev *bphy_rawdev;
+ int ret;
+
+ RTE_SET_USED(pci_drv);
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ if (!pci_dev->mem_resource[0].addr) {
+ plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+ pci_dev->mem_resource[0].addr,
+ pci_dev->mem_resource[2].addr);
+ return -ENODEV;
+ }
+
+ ret = roc_plt_init();
+ if (ret)
+ return ret;
+
+ bphy_rawdev_get_name(name, pci_dev);
+ bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+ rte_socket_id());
+ if (bphy_rawdev == NULL) {
+ plt_err("Failed to allocate rawdev");
+ return -ENOMEM;
+ }
+
+ bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+ bphy_rawdev->device = &pci_dev->device;
+ bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+ bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+ bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+ bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+ return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+ char name[RTE_RAWDEV_NAME_MAX_LEN];
+ struct rte_rawdev *rawdev;
+
+ if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+ return 0;
+
+ if (pci_dev == NULL) {
+ plt_err("invalid pci_dev");
+ return -EINVAL;
+ }
+
+ rawdev = rte_rawdev_pmd_get_named_dev(name);
+ if (rawdev == NULL) {
+ plt_err("invalid device name (%s)", name);
+ return -EINVAL;
+ }
+
+ bphy_rawdev_get_name(name, pci_dev);
+
+ return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+ .id_table = pci_bphy_map,
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+ .probe = bphy_rawdev_probe,
+ .remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
new file mode 100644
index 0..77169b1b7
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include
+#include
+
+#include
+
+struct bphy_mem {
+ struct rte_mem_resource res0;
+ struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+ struct roc_bphy_irq_chip *irq_chip;
+ struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build
b/drivers/raw/cnxk_bphy/meson.build
index dc5558ee8..f2868fd68 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -4,6 +4,7 @@
deps += ['bus_pci', 'common_cnxk', 'rawdev']
sour
[dpdk-dev] [PATCH v3 22/32] common/cnxk: support for registering bphy irq
Add support for registering user supplied baseband phy irq handler.
Signed-off-by: Jakib Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/common/cnxk/roc_bphy_irq.c | 38 ++
drivers/common/cnxk/roc_bphy_irq.h | 11 +
drivers/common/cnxk/version.map| 1 +
3 files changed, 50 insertions(+)
diff --git a/drivers/common/cnxk/roc_bphy_irq.c
b/drivers/common/cnxk/roc_bphy_irq.c
index 4b87fc801..882066ef3 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int
irq_num)
return retval;
}
+
+int
+roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+ struct roc_bphy_intr *intr)
+{
+ roc_cpuset_t orig_cpuset, intr_cpuset;
+ int retval;
+ int ret;
+
+ if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
+ return -ENOTSUP;
+
+ retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (retval < 0) {
+ plt_err("Failed to get affinity mask");
+ return retval;
+ }
+
+ CPU_ZERO(&intr_cpuset);
+ CPU_SET(intr->cpu, &intr_cpuset);
+ retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+ &intr_cpuset);
+ if (retval < 0) {
+ plt_err("Failed to set affinity mask");
+ return retval;
+ }
+
+ ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
+ intr->intr_handler, intr->isr_data);
+
+ retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+ &orig_cpuset);
+ if (retval < 0)
+ plt_warn("Failed to restore affinity mask");
+
+ return ret;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h
b/drivers/common/cnxk/roc_bphy_irq.h
index 778764f68..19ec5fdc4 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -21,6 +21,15 @@ struct roc_bphy_irq_chip {
char *mz_name;
};
+struct roc_bphy_intr {
+ int irq_num;
+ void (*intr_handler)(int irq_num, void *isr_data);
+ void *isr_data;
+ int cpu;
+ /* stack for this interrupt, not supplied by a user */
+ uint8_t *sp;
+};
+
__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
__roc_api void roc_bphy_irq_stack_remove(int cpu);
@@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct
roc_bphy_irq_chip *irq_chip,
int irq_num);
__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
int irq_num);
+__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+struct roc_bphy_intr *intr);
#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 941055ba0..e24766c05 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -27,6 +27,7 @@ INTERNAL {
roc_bphy_intr_fini;
roc_bphy_intr_handler;
roc_bphy_intr_init;
+ roc_bphy_intr_register;
roc_bphy_irq_handler_set;
roc_bphy_irq_stack_get;
roc_bphy_irq_stack_remove;
--
2.25.1
[dpdk-dev] [PATCH v3 24/32] raw/cnxk_bphy: support for reading bphy queue configuration
Add support for reading baseband phy queue configuration.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index cd26b9717..00b6c5035 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,7 +29,24 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device
*pci_dev)
pci_dev->addr.function);
}
+static int
+cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+rte_rawdev_obj_t queue_conf,
+size_t queue_conf_size)
+{
+ RTE_SET_USED(dev);
+ RTE_SET_USED(queue_id);
+
+ if (queue_conf_size != sizeof(unsigned int))
+ return -EINVAL;
+
+ *(unsigned int *)queue_conf = 1;
+
+ return 0;
+}
+
static const struct rte_rawdev_ops bphy_rawdev_ops = {
+ .queue_def_conf = cnxk_bphy_irq_queue_def_conf,
};
static int
--
2.25.1
[dpdk-dev] [PATCH v3 25/32] raw/cnxk_bphy: support for reading bphy queue count
Add support for reading number of available queues from baseband
phy. Currently only single queue is supported.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy.c | 9 +
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 7 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 00b6c5035..04e822586 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,6 +29,14 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device
*pci_dev)
pci_dev->addr.function);
}
+static uint16_t
+cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
+{
+ struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+
+ return RTE_DIM(bphy_dev->queues);
+}
+
static int
cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
rte_rawdev_obj_t queue_conf,
@@ -47,6 +55,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t
queue_id,
static const struct rte_rawdev_ops bphy_rawdev_ops = {
.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+ .queue_count = cnxk_bphy_irq_queue_count,
};
static int
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 77169b1b7..16243efc9 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -15,9 +15,16 @@ struct bphy_mem {
struct rte_mem_resource res2;
};
+struct bphy_irq_queue {
+ /* queue holds up to one response */
+ void *rsp;
+};
+
struct bphy_device {
struct roc_bphy_irq_chip *irq_chip;
struct bphy_mem mem;
+ /* bphy irq interface supports single queue only */
+ struct bphy_irq_queue queues[1];
};
#endif /* _CNXK_BPHY_IRQ_ */
--
2.25.1
[dpdk-dev] [PATCH v3 26/32] raw/cnxk_bphy: support for bphy enqueue operation
Add preliminary support for enqueue operation.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy.c| 26 ++
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 13 +
2 files changed, 39 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 04e822586..2949bf02a 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -13,6 +13,7 @@
#include
#include "cnxk_bphy_irq.h"
+#include "rte_pmd_bphy.h"
static const struct rte_pci_id pci_bphy_map[] = {
{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
@@ -29,6 +30,30 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device
*pci_dev)
pci_dev->addr.function);
}
+static int
+cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
+ struct rte_rawdev_buf **buffers, unsigned int count,
+ rte_rawdev_obj_t context)
+{
+ struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+ struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
+ unsigned int queue = (size_t)context;
+ int ret = 0;
+
+ if (queue >= RTE_DIM(bphy_dev->queues))
+ return -EINVAL;
+
+ if (count == 0)
+ return 0;
+
+ switch (msg->type) {
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
static uint16_t
cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
{
@@ -55,6 +80,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t
queue_id,
static const struct rte_rawdev_ops bphy_rawdev_ops = {
.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+ .enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
.queue_count = cnxk_bphy_irq_queue_count,
};
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index fed7916fe..eb39654f1 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -101,4 +101,17 @@ struct cnxk_bphy_cgx_msg {
void *data;
};
+enum cnxk_bphy_irq_msg_type {
+ CNXK_BPHY_IRQ_MSG_TYPE_INIT,
+ CNXK_BPHY_IRQ_MSG_TYPE_FINI,
+ CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
+ CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
+ CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+};
+
+struct cnxk_bphy_irq_msg {
+ enum cnxk_bphy_irq_msg_type type;
+ void *data;
+};
+
#endif /* _CNXK_BPHY_H_ */
--
2.25.1
[dpdk-dev] [PATCH v3 27/32] raw/cnxk_bphy: support for bphy dequeue operation
Add support for dequeueing responses to previously
enqueued messages.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2949bf02a..7e541bac4 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -54,6 +54,25 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
return ret;
}
+static int
+cnxk_bphy_irq_dequeue_bufs(struct rte_rawdev *dev,
+ struct rte_rawdev_buf **buffers, unsigned int count,
+ rte_rawdev_obj_t context)
+{
+ struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+ unsigned int queue = (size_t)context;
+
+ if (queue >= RTE_DIM(bphy_dev->queues))
+ return -EINVAL;
+
+ if (count == 0)
+ return 0;
+
+ buffers[0]->buf_addr = bphy_dev->queues[queue].rsp;
+
+ return 0;
+}
+
static uint16_t
cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
{
@@ -81,6 +100,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev,
uint16_t queue_id,
static const struct rte_rawdev_ops bphy_rawdev_ops = {
.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
+ .dequeue_bufs = cnxk_bphy_irq_dequeue_bufs,
.queue_count = cnxk_bphy_irq_queue_count,
};
--
2.25.1
[dpdk-dev] [PATCH v3 28/32] raw/cnxk_bphy: support for interrupt init and cleanup
Add support for interrupt initialization and cleanup. Internally
interrupt initialization performs low level setup that allows
custom interrupt handler registration later on.
Interrupt initialization and cleanup are related hence they
are in the same patch.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 20
drivers/raw/cnxk_bphy/cnxk_bphy.c | 6
drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 5 +++
drivers/raw/cnxk_bphy/meson.build | 1 +
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 41 +++
6 files changed, 120 insertions(+)
create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 120f953fb..b69c5f39a 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -37,6 +37,9 @@ To perform data transfer use standard
``rte_rawdev_enqueue_buffers()`` and
``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
responses hence dequeueing is not always necessary.
+BPHY CGX/RPM PMD
+
+
BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by
type and payload.
Message types along with description are listed below. As for the usage
examples please refer to
``cnxk_bphy_cgx_dev_selftest()``.
@@ -95,6 +98,23 @@ Message must have type set to
``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the
latter will
do the opposite.
+BPHY PMD
+
+
+BPHY PMD accepts ``struct cnxk_bphy_irq_msg`` messages which differ by type
and payload.
+Message types along with description are listed below. For some usage examples
please refer to
+``bphy_rawdev_selftest()``.
+
+Initialize or finalize interrupt handling
+~
+
+Message is used to setup low level interrupt handling.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_INIT`` or
``CNXK_BPHY_IRQ_MSG_TYPE_FINI``.
+The former will setup low level interrupt handling while the latter will tear
everything down. There
+are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
+``rte_pmd_bphy_intr_fini()`` that take care of all details.
+
Self test
-
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 7e541bac4..3f8679534 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -47,6 +47,12 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
return 0;
switch (msg->type) {
+ case CNXK_BPHY_IRQ_MSG_TYPE_INIT:
+ ret = cnxk_bphy_intr_init(dev->dev_id);
+ break;
+ case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
+ cnxk_bphy_intr_fini(dev->dev_id);
+ break;
default:
ret = -EINVAL;
}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
new file mode 100644
index 0..c4df539cd
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "cnxk_bphy_irq.h"
+
+static struct bphy_device *
+cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
+{
+ struct rte_rawdev *rawdev;
+
+ if (!rte_rawdev_pmd_is_valid_dev(dev_id))
+ return NULL;
+
+ rawdev = &rte_rawdevs[dev_id];
+
+ return (struct bphy_device *)rawdev->dev_private;
+}
+
+int
+cnxk_bphy_intr_init(uint16_t dev_id)
+{
+ struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+ bphy_dev->irq_chip = roc_bphy_intr_init();
+ if (bphy_dev->irq_chip == NULL)
+ return -ENOMEM;
+
+ return 0;
+}
+
+void
+cnxk_bphy_intr_fini(uint16_t dev_id)
+{
+ struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+ struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+ roc_bphy_intr_fini(irq_chip);
+ bphy_dev->irq_chip = NULL;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 16243efc9..3acc47fe8 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -10,6 +10,8 @@
#include
+typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
+
struct bphy_mem {
struct rte_mem_resource res0;
struct rte_mem_resource res2;
@@ -27,4 +29,7 @@ struct bphy_device {
struct bphy_irq_queue queues[1];
};
+int cnxk_bphy_intr_init(uint16_t dev_id);
+void cnxk_bphy_intr_fini(uint16_t dev_id);
+
#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build
b/drivers/raw/cnxk_bphy/meson.build
i
[dpdk-dev] [PATCH v3 29/32] raw/cnxk_bphy: support for reading number of bphy irqs
Add support for retrieving maximum number of interrupts.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index c4df539cd..991c2d7ab 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
return (struct bphy_device *)rawdev->dev_private;
}
+uint64_t
+cnxk_bphy_irq_max_get(uint16_t dev_id)
+{
+ struct roc_bphy_irq_chip *irq_chip;
+ struct bphy_device *bphy_dev;
+
+ bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+ irq_chip = bphy_dev->irq_chip;
+
+ return irq_chip->max_irq;
+}
+
int
cnxk_bphy_intr_init(uint16_t dev_id)
{
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 3acc47fe8..6b59218af 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,5 +31,6 @@ struct bphy_device {
int cnxk_bphy_intr_init(uint16_t dev_id);
void cnxk_bphy_intr_fini(uint16_t dev_id);
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
#endif /* _CNXK_BPHY_IRQ_ */
--
2.25.1
[dpdk-dev] [PATCH v3 30/32] raw/cnxk_bphy: support for retrieving bphy device memory
Allow user to retrieve baseband phy memory resources.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 10 +
drivers/raw/cnxk_bphy/cnxk_bphy.c | 3 +++
drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 8 +++
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 1 +
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 30 +++
5 files changed, 52 insertions(+)
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index b69c5f39a..16195d2ee 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,7 @@ Features
The BPHY CGX/RPM implements following features in the rawdev API:
- Access to BPHY CGX/RPM via a set of predefined messages
+- Access to BPHY memory
Device Setup
@@ -115,6 +116,15 @@ The former will setup low level interrupt handling while
the latter will tear ev
are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
``rte_pmd_bphy_intr_fini()`` that take care of all details.
+
+Get device memory
+~
+
+Message is used to read device MMIO address.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a
convenience function
+``rte_pmd_bphy_intr_mem_get()`` available that takes care of retrieving that
address.
+
Self test
-
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 3f8679534..278e26af0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -53,6 +53,9 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
cnxk_bphy_intr_fini(dev->dev_id);
break;
+ case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
+ bphy_dev->queues[queue].rsp = &bphy_dev->mem;
+ break;
default:
ret = -EINVAL;
}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 991c2d7ab..13a0d8ad1 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
roc_bphy_intr_fini(irq_chip);
bphy_dev->irq_chip = NULL;
}
+
+struct bphy_mem *
+cnxk_bphy_mem_get(uint16_t dev_id)
+{
+ struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+ return &bphy_dev->mem;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 6b59218af..5f87143a0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,6 +31,7 @@ struct bphy_device {
int cnxk_bphy_intr_init(uint16_t dev_id);
void cnxk_bphy_intr_fini(uint16_t dev_id);
+struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index c667d984e..d08b14b57 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -103,6 +103,7 @@ struct cnxk_bphy_cgx_msg {
void *data;
};
+#define cnxk_bphy_mem bphy_mem
#define CNXK_BPHY_DEF_QUEUE 0
enum cnxk_bphy_irq_msg_type {
@@ -115,6 +116,11 @@ enum cnxk_bphy_irq_msg_type {
struct cnxk_bphy_irq_msg {
enum cnxk_bphy_irq_msg_type type;
+ /*
+* The data field, depending on message type, may point to
+* - (deq) struct cnxk_bphy_mem for memory range request response
+* - (xxx) NULL
+*/
void *data;
};
@@ -155,4 +161,28 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
}
+static __rte_always_inline struct cnxk_bphy_mem *
+rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
+{
+ struct cnxk_bphy_irq_msg msg = {
+ .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+ };
+ struct rte_rawdev_buf *bufs[1];
+ struct rte_rawdev_buf buf;
+ int ret;
+
+ buf.buf_addr = &msg;
+ bufs[0] = &buf;
+
+ ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+ if (ret)
+ return NULL;
+
+ ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+ if (ret)
+ return NULL;
+
+ return buf.buf_addr;
+}
+
#endif /* _CNXK_BPHY_H_ */
--
2.25.1
[dpdk-dev] [PATCH v3 31/32] raw/cnxk_bphy: support for registering bphy irq handlers
Custom irq handlers may be registered/removed on demand.
Since registration and removal are related they are in the
same patch.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 13
drivers/raw/cnxk_bphy/cnxk_bphy.c | 11 +++
drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33
drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 4 +++
drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 45 +++
5 files changed, 106 insertions(+)
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 16195d2ee..1e17d6071 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -18,6 +18,7 @@ The BPHY CGX/RPM implements following features in the rawdev
API:
- Access to BPHY CGX/RPM via a set of predefined messages
- Access to BPHY memory
+- Custom interrupt handlers
Device Setup
@@ -117,6 +118,18 @@ are also two convenience functions namely
``rte_pmd_bphy_intr_init()`` and
``rte_pmd_bphy_intr_fini()`` that take care of all details.
+Register or remove interrupt handler
+
+
+Message is used setup custom interrupt handler.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_REGISTER`` or
+``CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER``. The former will register an interrupt
handler while the
+latter will remove it. Prior sending actual message payload i.e ``struct
cnxk_bphy_irq_info`` needs
+to be filled with relevant information. There are also two convenience
functions namely
+``rte_pmd_bphy_intr_register()`` and ``rte_pmd_bphy_intr_unregister()`` that
take care of all
+details.
+
Get device memory
~
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 278e26af0..2a516ae73 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -38,6 +38,7 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
unsigned int queue = (size_t)context;
+ struct cnxk_bphy_irq_info *info;
int ret = 0;
if (queue >= RTE_DIM(bphy_dev->queues))
@@ -53,6 +54,16 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
cnxk_bphy_intr_fini(dev->dev_id);
break;
+ case CNXK_BPHY_IRQ_MSG_TYPE_REGISTER:
+ info = (struct cnxk_bphy_irq_info *)msg->data;
+ ret = cnxk_bphy_intr_register(dev->dev_id, info->irq_num,
+ info->handler, info->data,
+ info->cpu);
+ break;
+ case CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER:
+ info = (struct cnxk_bphy_irq_info *)msg->data;
+ cnxk_bphy_intr_unregister(dev->dev_id, info->irq_num);
+ break;
case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
bphy_dev->queues[queue].rsp = &bphy_dev->mem;
break;
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 13a0d8ad1..bbcc285a7 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
bphy_dev->irq_chip = NULL;
}
+int
+cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+ cnxk_bphy_intr_handler_t handler, void *data, int cpu)
+{
+ struct roc_bphy_intr intr = {
+ .irq_num = irq_num,
+ .intr_handler = handler,
+ .isr_data = data,
+ .cpu = cpu
+ };
+
+ struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+ struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+ if (!irq_chip)
+ return -ENODEV;
+ if (!handler || !data)
+ return -EINVAL;
+
+ return roc_bphy_intr_register(irq_chip, &intr);
+}
+
+void
+cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+ struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+ if (bphy_dev->irq_chip)
+ roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num);
+ else
+ plt_err("Missing irq chip");
+}
+
struct bphy_mem *
cnxk_bphy_mem_get(uint16_t dev_id)
{
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 5f87143a0..b55147b93 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -32,6 +32,10 @@ struct bphy_device {
int cnxk_bphy_intr_init(uint16_t dev_id);
void cnxk_bphy_intr_fini(uint16_t dev_id);
struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
+int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+
[dpdk-dev] [PATCH v3 32/32] raw/cnxk_bphy: support for bphy selftest
Add support for performing selftest.
Signed-off-by: Jakub Palider
Signed-off-by: Tomasz Duszynski
Reviewed-by: Jerin Jacob
---
doc/guides/rawdevs/cnxk_bphy.rst | 7 +-
drivers/raw/cnxk_bphy/cnxk_bphy.c | 124 ++
2 files changed, 127 insertions(+), 4 deletions(-)
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 1e17d6071..bf7c00e6b 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -141,15 +141,14 @@ Message must have type set to
``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a conv
Self test
-
-On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+On EAL initialization BPHY and BPHY CGX/RPM devices will be probed and
populated into
the raw devices. The rawdev ID of the device can be obtained using invocation
of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
RFOE module,
- x is the device's bus id specified in "bus:device.func" (BDF) format.
Use this identifier for further rawdev function calls.
-The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
-functionality.
+Selftest rawdev API can be used to verify the BPHY and BPHY CGX/RPM
functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c
b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2a516ae73..9cb3f8d33 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -11,6 +11,7 @@
#include
#include
+#include
#include "cnxk_bphy_irq.h"
#include "rte_pmd_bphy.h"
@@ -22,6 +23,128 @@ static const struct rte_pci_id pci_bphy_map[] = {
},
};
+struct bphy_test {
+ int irq_num;
+ cnxk_bphy_intr_handler_t handler;
+ void *data;
+ int cpu;
+ bool handled_intr;
+ int handled_data;
+ int test_data;
+};
+
+static struct bphy_test *test;
+
+static void
+bphy_test_handler_fn(int irq_num, void *isr_data)
+{
+ test[irq_num].handled_intr = true;
+ test[irq_num].handled_data = *((int *)isr_data);
+}
+
+static int
+bphy_rawdev_selftest(uint16_t dev_id)
+{
+ unsigned int i, queues, descs;
+ uint64_t max_irq;
+ int ret;
+
+ queues = rte_rawdev_queue_count(dev_id);
+ if (queues == 0)
+ return -ENODEV;
+
+ ret = rte_rawdev_start(dev_id);
+ if (ret)
+ return ret;
+
+ ret = rte_rawdev_queue_conf_get(dev_id, CNXK_BPHY_DEF_QUEUE, &descs,
+ sizeof(descs));
+ if (ret)
+ goto err_desc;
+ if (descs != 1) {
+ ret = -ENODEV;
+ plt_err("Wrong number of descs reported\n");
+ goto err_desc;
+ }
+
+ ret = rte_pmd_bphy_intr_init(dev_id);
+ if (ret) {
+ plt_err("intr init failed");
+ return ret;
+ }
+
+ max_irq = cnxk_bphy_irq_max_get(dev_id);
+
+ test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0);
+ if (test == NULL) {
+ plt_err("intr alloc failed");
+ goto err_alloc;
+ }
+
+ for (i = 0; i < max_irq; i++) {
+ test[i].test_data = i;
+ test[i].irq_num = i;
+ test[i].handler = bphy_test_handler_fn;
+ test[i].data = &test[i].test_data;
+ }
+
+ for (i = 0; i < max_irq; i++) {
+ ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num,
+test[i].handler, test[i].data,
+0);
+ if (ret == -ENOTSUP) {
+ /* In the test we iterate over all irq numbers
+* so if some of them are not supported by given
+* platform we treat respective results as valid
+* ones. This way they have no impact on overall
+* test results.
+*/
+ test[i].handled_intr = true;
+ test[i].handled_data = test[i].test_data;
+ ret = 0;
+ continue;
+ }
+
+ if (ret) {
+ plt_err("intr register failed at irq %d", i);
+ goto err_register;
+ }
+ }
+
+ for (i = 0; i < max_irq; i++)
+ roc_bphy_intr_handler(i);
+
+ for (i = 0; i < max_irq; i++) {
+ if (!test[i].handled_intr) {
+ plt_err("intr %u not handled", i);
+ ret = -1;
+ break;
+ }
+ if (test[i].handled_data != test[i].test_data) {
+ plt_err("intr %u has wrong handler", i);
+ ret = -1;
+
[dpdk-dev] [PATCH] devtools: script to track map symbols
Script to track growth of stable and experimental symbols
over releases since v19.11.
Signed-off-by: Ray Kinsella
---
devtools/count_symbols.py | 230 ++
1 file changed, 230 insertions(+)
create mode 100755 devtools/count_symbols.py
diff --git a/devtools/count_symbols.py b/devtools/count_symbols.py
new file mode 100755
index 00..7b29651044
--- /dev/null
+++ b/devtools/count_symbols.py
@@ -0,0 +1,230 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2021 Intel Corporation
+from pathlib import Path
+import sys, os
+import subprocess
+import argparse
+import re
+import datetime
+
+try:
+from parsley import makeGrammar
+except ImportError:
+print('This script uses the package Parsley to parse C Mapfiles.\n'
+ 'This can be installed with \"pip install parsley".')
+exit()
+
+symbolMapGrammar = r"""
+
+ws = (' ' | '\r' | '\n' | '\t')*
+
+ABI_VER = ({})
+DPDK_VER = ('DPDK_' ABI_VER)
+ABI_NAME = ('INTERNAL' | 'EXPERIMENTAL' | DPDK_VER)
+comment = '#' (~'\n' anything)+ '\n'
+symbol = (~(';' | '}}' | '#') anything )+:c ';' -> ''.join(c)
+global = 'global:'
+local = 'local: *;'
+symbols = comment* symbol:s ws comment* -> s
+
+abi = (abi_section+):m -> dict(m)
+abi_section = (ws ABI_NAME:e ws '{{' ws global* (~local ws symbols)*:s ws
local* ws '}}' ws DPDK_VER* ';' ws) -> (e,s)
+"""
+
+#abi_ver = ['21', '20.0.1', '20.0', '20']
+
+def get_abi_versions():
+year = datetime.date.today().year - 2000
+s=" |".join(['\'{}\''.format(i) for i in reversed(range(21, year + 1)) ])
+s = s + ' | \'20.0.1\' | \'20.0\' | \'20\''
+
+return s
+
+def get_dpdk_releases():
+year = datetime.date.today().year - 2000
+s="|".join("{}".format(i) for i in range(19,year + 1))
+pattern = re.compile('^\"v(' + s + ')\.\d{2}\"$')
+
+cmd = ['git', 'for-each-ref', '--sort=taggerdate', '--format', '"%(tag)"']
+result = subprocess.run(cmd, \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE)
+if result.stderr.startswith(b'fatal'):
+result = None
+
+tags = result.stdout.decode('utf-8').split('\n')
+
+# find the non-rcs between now and v19.11
+tags = [ tag.replace('\"','') \
+ for tag in reversed(tags) \
+ if pattern.match(tag) ][:-3]
+
+return tags
+
+
+def get_terminal_rows():
+rows, _ = os.popen('stty size', 'r').read().split()
+return int(rows)
+
+def fix_directory_name(path):
+mapfilepath1 = str(path.parent.name)
+mapfilepath2 = str(path.parents[1])
+mapfilepath = mapfilepath2 + '/librte_' + mapfilepath1
+
+return mapfilepath
+
+# fix removal of the librte_ from the directory names
+def directory_renamed(path, rel):
+mapfilepath = fix_directory_name(path)
+tagfile = '{}:{}/{}'.format(rel, mapfilepath, path.name)
+
+result = subprocess.run(['git', 'show', tagfile], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE)
+if result.stderr.startswith(b'fatal'):
+result = None
+
+return result
+
+# fix renaming of map files
+def mapfile_renamed(path, rel):
+newfile = None
+
+result = subprocess.run(['git', 'ls-tree', \
+ rel, str(path.parent) + '/'], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE)
+dentries = result.stdout.decode('utf-8')
+dentries = dentries.split('\n')
+
+# filter entries looking for the map file
+dentries = [dentry for dentry in dentries if dentry.endswith('.map')]
+if len(dentries) > 1 or len(dentries) == 0:
+return None
+
+dparts = dentries[0].split('/')
+newfile = dparts[len(dparts) - 1]
+
+if(newfile is not None):
+tagfile = '{}:{}/{}'.format(rel, path.parent, newfile)
+
+result = subprocess.run(['git', 'show', tagfile], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE)
+if result.stderr.startswith(b'fatal'):
+result = None
+
+else:
+result = None
+
+return result
+
+# renaming of the map file & renaming of directory
+def mapfile_and_directory_renamed(path, rel):
+mapfilepath = Path("{}/{}".format(fix_directory_name(path),path.name))
+
+return mapfile_renamed(mapfilepath, rel)
+
+fix_strategies = [directory_renamed, \
+ mapfile_renamed, \
+ mapfile_and_directory_renamed]
+
+fmt = col_fmt = ""
+
+def set_terminal_output(dpdk_rel):
+global fmt, col_fmt
+
+fmt = '{:<50}'
+col_fmt = fmt
+for rel in dpdk_rel:
+fmt += '{:<6}{:<6}'
+col_fmt += '{:<12}'
+
+def set_csv_output(dpdk_rel):
+global fmt, col_fmt
+
+fmt = '{},'
+col_fmt = fmt
+for rel in dpdk_rel:
+fmt += '{},{},'
+col_fmt += '{},,'
+
+output_formats = { Non
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
On 6/21/2021 3:42 PM, Ananyev, Konstantin wrote:
>
One more thought here - if we are talking about rte_ethdev[] in
particular, I think we can:
1. move public function pointers (rx_pkt_burst(), etc.) from
rte_ethdev into a separate flat array.
We can keep it public to still use inline functions for 'fast' calls
rte_eth_rx_burst(), etc. to avoid
any regressions.
That could still be flat array with max_size specified at application
startup.
2. Hide rest of rte_ethdev struct in .c.
That will allow us to change the struct itself and the whole
rte_ethdev[] table in a way we like
(flat array, vector, hash, linked list) without ABI/API breakages.
Yes, it would require all PMDs to change prototype for pkt_rx_burst()
function
(to accept port_id, queue_id instead of queue pointer), but the change
is mechanical one.
Probably some macro can be provided to simplify it.
>>>
>>> We are already planning some tasks for ABI stability for v21.11, I think
>>> splitting 'struct rte_eth_dev' can be part of that task, it enables
>>> hiding more
>>> internal data.
>>
>> Ok, sounds good.
>>
>>>
The only significant complication I can foresee with implementing that
approach -
we'll need a an array of 'fast' function pointers per queue, not per
device as we have now
(to avoid extra indirection for callback implementation).
Though as a bonus we'll have ability to use different RX/TX funcions
per queue.
>>>
>>> What do you think split Rx/Tx callback into its own struct too?
>>>
>>> Overall 'rte_eth_dev' can be split into three as:
>>> 1. rte_eth_dev
>>> 2. rte_eth_dev_burst
>>> 3. rte_eth_dev_cb
>>>
>>> And we can hide 1 from applications even with the inline functions.
>>
>> As discussed off-line, I think:
>> it is possible.
>> My absolute preference would be to have just 1/2 (with CB hidden).
>
> How can we hide the callbacks since they are used by inline burst
> functions.
I probably I owe a better explanation to what I meant in first mail.
Otherwise it sounds confusing.
I'll try to write a more detailed one in next few days.
>>>
>>> Actually I gave it another thought over weekend, and might be we can
>>> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
>>> an example, but the same principle applies to other 'fast' functions.
>>>
>>> 1. Needed changes for PMDs rx_pkt_burst():
>>> a) change function prototype to accept 'uint16_t port_id' and 'uint16_t
>>> queue_id',
>>> instead of current 'void *'.
>>> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
>>> function at return.
>>> This inline function will do all CB calls for that queue.
>>>
>>> To be more specific, let say we have some PMD: xyz with RX function:
>>>
>>> uint16_t
>>> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
>>> {
>>> struct xyz_rx_queue *rxq = rx_queue;
>>> uint16_t nb_rx = 0;
>>>
>>> /* do actual stuff here */
>>>
>>> return nb_rx;
>>> }
>>>
>>> It will be transformed to:
>>>
>>> uint16_t
>>> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
>>> **rx_pkts, uint16_t nb_pkts)
>>> {
>>> struct xyz_rx_queue *rxq;
>>> uint16_t nb_rx;
>>>
>>> rxq = _rte_eth_rx_prolog(port_id, queue_id);
>>> if (rxq == NULL)
>>> return 0;
>>> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
>>> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts, nb_pkts);
>>> }
>>>
>>> And somewhere in ethdev_private.h:
>>>
>>> static inline void *
>>> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
>>> {
>>>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>
>>> #ifdef RTE_ETHDEV_DEBUG_RX
>>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
>>> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
>>>
>>> if (queue_id >= dev->data->nb_rx_queues) {
>>> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
>>> return NULL;
>>> }
>>> #endif
>>> return dev->data->rx_queues[queue_id];
>>> }
>>>
>>> static inline uint16_t
>>> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
>>> **rx_pkts, const uint16_t nb_pkts);
>>> {
>>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
>>>
>>> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
>>> struct rte_eth_rxtx_callback *cb;
>>>
>>> /* __ATOMIC_RELEASE memory order was used when the
>>> * call back was inserted into the list.
>>> * Since there is a clear dependency between loading
>>> * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order i
[dpdk-dev] [PATCH v3] devtools: script to track map symbols
Script to track growth of stable and experimental symbols
over releases since v19.11.
Signed-off-by: Ray Kinsella
---
v2: reworked to fix pylint errors
v3: sent with the current in-reply-to
devtools/count_symbols.py | 262 ++
1 file changed, 262 insertions(+)
create mode 100755 devtools/count_symbols.py
diff --git a/devtools/count_symbols.py b/devtools/count_symbols.py
new file mode 100755
index 00..30be09754f
--- /dev/null
+++ b/devtools/count_symbols.py
@@ -0,0 +1,262 @@
+#!/usr/bin/env python3
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2021 Intel Corporation
+'''Tool to count the number of symbols in each DPDK release'''
+from pathlib import Path
+import sys
+import os
+import subprocess
+import argparse
+import re
+import datetime
+
+try:
+from parsley import makeGrammar
+except ImportError:
+print('This script uses the package Parsley to parse C Mapfiles.\n'
+ 'This can be installed with \"pip install parsley".')
+sys.exit()
+
+MAP_GRAMMAR = r"""
+
+ws = (' ' | '\r' | '\n' | '\t')*
+
+ABI_VER = ({})
+DPDK_VER = ('DPDK_' ABI_VER)
+ABI_NAME = ('INTERNAL' | 'EXPERIMENTAL' | DPDK_VER)
+comment = '#' (~'\n' anything)+ '\n'
+symbol = (~(';' | '}}' | '#') anything )+:c ';' -> ''.join(c)
+global = 'global:'
+local = 'local: *;'
+symbols = comment* symbol:s ws comment* -> s
+
+abi = (abi_section+):m -> dict(m)
+abi_section = (ws ABI_NAME:e ws '{{' ws global* (~local ws symbols)*:s ws
local* ws '}}' ws DPDK_VER* ';' ws) -> (e,s)
+"""
+
+def get_abi_versions():
+'''Returns a string of possible dpdk abi versions'''
+
+year = datetime.date.today().year - 2000
+tags = " |".join(['\'{}\''.format(i) \
+ for i in reversed(range(21, year + 1)) ])
+tags = tags + ' | \'20.0.1\' | \'20.0\' | \'20\''
+
+return tags
+
+def get_dpdk_releases():
+'''Returns a list of dpdk release tags names since v19.11'''
+
+year = datetime.date.today().year - 2000
+year_range = "|".join("{}".format(i) for i in range(19,year + 1))
+pattern = re.compile(r'^\"v(' + year_range + r')\.\d{2}\"$')
+
+cmd = ['git', 'for-each-ref', '--sort=taggerdate', '--format', '"%(tag)"']
+try:
+result = subprocess.run(cmd, \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE,
+check=True)
+except subprocess.CalledProcessError:
+print("Failed to interogate git for release tags")
+sys.exit()
+
+tags = result.stdout.decode('utf-8').split('\n')
+
+# find the non-rcs between now and v19.11
+tags = [ tag.replace('\"','') \
+ for tag in reversed(tags) \
+ if pattern.match(tag) ][:-3]
+
+return tags
+
+def fix_directory_name(path):
+'''Prepend librte to the source directory name'''
+mapfilepath1 = str(path.parent.name)
+mapfilepath2 = str(path.parents[1])
+mapfilepath = mapfilepath2 + '/librte_' + mapfilepath1
+
+return mapfilepath
+
+def directory_renamed(path, rel):
+'''Fix removal of the librte_ from the directory names'''
+
+mapfilepath = fix_directory_name(path)
+tagfile = '{}:{}/{}'.format(rel, mapfilepath, path.name)
+
+try:
+result = subprocess.run(['git', 'show', tagfile], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE,
+check=True)
+except subprocess.CalledProcessError:
+result = None
+
+return result
+
+def mapfile_renamed(path, rel):
+'''Fix renaming of map files'''
+newfile = None
+
+result = subprocess.run(['git', 'ls-tree', \
+ rel, str(path.parent) + '/'], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE,
+check=True)
+dentries = result.stdout.decode('utf-8')
+dentries = dentries.split('\n')
+
+# filter entries looking for the map file
+dentries = [dentry for dentry in dentries if dentry.endswith('.map')]
+if len(dentries) > 1 or len(dentries) == 0:
+return None
+
+dparts = dentries[0].split('/')
+newfile = dparts[len(dparts) - 1]
+
+if newfile is not None:
+tagfile = '{}:{}/{}'.format(rel, path.parent, newfile)
+
+try:
+result = subprocess.run(['git', 'show', tagfile], \
+stdout=subprocess.PIPE, \
+stderr=subprocess.PIPE,
+check=True)
+except subprocess.CalledProcessError:
+result = None
+
+else:
+result = None
+
+return result
+
+def mapfile_and_directory_renamed(path, rel):
+'''Fix renaming of the map file & the source directory'''
+mapfilepath = Path("{}/{}".format(fix_directory_name(path),path.name))
+
+return mapfile_renamed(mapfil
Re: [dpdk-dev] [PATCH] parray: introduce internal API for dynamic arrays
>
> On 6/21/2021 3:42 PM, Ananyev, Konstantin wrote:
> >
> One more thought here - if we are talking about rte_ethdev[] in
> particular, I think we can:
> 1. move public function pointers (rx_pkt_burst(), etc.) from
> rte_ethdev into a separate flat array.
> We can keep it public to still use inline functions for 'fast' calls
> rte_eth_rx_burst(), etc. to avoid
> any regressions.
> That could still be flat array with max_size specified at
> application startup.
> 2. Hide rest of rte_ethdev struct in .c.
> That will allow us to change the struct itself and the whole
> rte_ethdev[] table in a way we like
> (flat array, vector, hash, linked list) without ABI/API breakages.
>
> Yes, it would require all PMDs to change prototype for
> pkt_rx_burst() function
> (to accept port_id, queue_id instead of queue pointer), but the
> change is mechanical one.
> Probably some macro can be provided to simplify it.
>
> >>>
> >>> We are already planning some tasks for ABI stability for v21.11, I
> >>> think
> >>> splitting 'struct rte_eth_dev' can be part of that task, it enables
> >>> hiding more
> >>> internal data.
> >>
> >> Ok, sounds good.
> >>
> >>>
> The only significant complication I can foresee with implementing
> that approach -
> we'll need a an array of 'fast' function pointers per queue, not per
> device as we have now
> (to avoid extra indirection for callback implementation).
> Though as a bonus we'll have ability to use different RX/TX funcions
> per queue.
>
> >>>
> >>> What do you think split Rx/Tx callback into its own struct too?
> >>>
> >>> Overall 'rte_eth_dev' can be split into three as:
> >>> 1. rte_eth_dev
> >>> 2. rte_eth_dev_burst
> >>> 3. rte_eth_dev_cb
> >>>
> >>> And we can hide 1 from applications even with the inline functions.
> >>
> >> As discussed off-line, I think:
> >> it is possible.
> >> My absolute preference would be to have just 1/2 (with CB hidden).
> >
> > How can we hide the callbacks since they are used by inline burst
> > functions.
>
> I probably I owe a better explanation to what I meant in first mail.
> Otherwise it sounds confusing.
> I'll try to write a more detailed one in next few days.
> >>>
> >>> Actually I gave it another thought over weekend, and might be we can
> >>> hide rte_eth_dev_cb even in a simpler way. I'd use eth_rx_burst() as
> >>> an example, but the same principle applies to other 'fast' functions.
> >>>
> >>> 1. Needed changes for PMDs rx_pkt_burst():
> >>> a) change function prototype to accept 'uint16_t port_id' and
> >>> 'uint16_t queue_id',
> >>> instead of current 'void *'.
> >>> b) Each PMD rx_pkt_burst() will have to call rte_eth_rx_epilog()
> >>> function at return.
> >>> This inline function will do all CB calls for that queue.
> >>>
> >>> To be more specific, let say we have some PMD: xyz with RX function:
> >>>
> >>> uint16_t
> >>> xyz_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
> >>> {
> >>> struct xyz_rx_queue *rxq = rx_queue;
> >>> uint16_t nb_rx = 0;
> >>>
> >>> /* do actual stuff here */
> >>>
> >>> return nb_rx;
> >>> }
> >>>
> >>> It will be transformed to:
> >>>
> >>> uint16_t
> >>> xyz_recv_pkts(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> >>> **rx_pkts, uint16_t nb_pkts)
> >>> {
> >>> struct xyz_rx_queue *rxq;
> >>> uint16_t nb_rx;
> >>>
> >>> rxq = _rte_eth_rx_prolog(port_id, queue_id);
> >>> if (rxq == NULL)
> >>> return 0;
> >>> nb_rx = _xyz_real_recv_pkts(rxq, rx_pkts, nb_pkts);
> >>> return _rte_eth_rx_epilog(port_id, queue_id, rx_pkts, nb_pkts);
> >>> }
> >>>
> >>> And somewhere in ethdev_private.h:
> >>>
> >>> static inline void *
> >>> _rte_eth_rx_prolog(uint16_t port_id, uint16_t queue_id);
> >>> {
> >>>struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >>>
> >>> #ifdef RTE_ETHDEV_DEBUG_RX
> >>> RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
> >>> RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, NULL);
> >>>
> >>> if (queue_id >= dev->data->nb_rx_queues) {
> >>> RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
> >>> return NULL;
> >>> }
> >>> #endif
> >>> return dev->data->rx_queues[queue_id];
> >>> }
> >>>
> >>> static inline uint16_t
> >>> _rte_eth_rx_epilog(uint16_t port_id, uint16_t queue_id, struct rte_mbuf
> >>> **rx_pkts, const uint16_t nb_pkts);
> >>> {
> >>> struct rte_eth_dev *dev = &rte_eth_devices[port_id];
> >>>
> >>> #ifdef RTE_ETHDEV_RXTX_CALLBACKS
> >>> struct rte_eth_rxtx
