[dpdk-dev] [PATCH] crypto/openssl: fix inproper freeing of asymmetric crypto keys in rsa

[Arek Kusztal]

In case big number need to be freed, data it contains should be cleared
before especially if it is critical data like private keys.

Fixes: 3e9d6bd447fb ("crypto/openssl: add RSA and mod asym operations")

Signed-off-by: Arek Kusztal 
---
 config/common_base   |  4 ++--
 drivers/crypto/openssl/rte_openssl_pmd_ops.c | 16 
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/config/common_base b/config/common_base
index 6b96e0e..a3d8e17 100644
--- a/config/common_base
+++ b/config/common_base
@@ -573,7 +573,7 @@ CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
 #
 CONFIG_RTE_LIBRTE_PMD_QAT=y
 CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
-CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
+CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=y
 #
 # Max. number of QuickAssist devices, which can be detected and attached
 #
@@ -597,7 +597,7 @@ CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n
 #
 # Compile PMD for Software backed device
 #
-CONFIG_RTE_LIBRTE_PMD_OPENSSL=n
+CONFIG_RTE_LIBRTE_PMD_OPENSSL=y
 
 #
 # Compile PMD for AESNI GCM device
diff --git a/drivers/crypto/openssl/rte_openssl_pmd_ops.c 
b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
index 40217cf..a307c91 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd_ops.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd_ops.c
@@ -912,14 +912,14 @@ static int openssl_set_asym_session_parameters(
asym_session->xfrm_type = RTE_CRYPTO_ASYM_XFORM_RSA;
break;
 err_rsa:
-   BN_free(n);
-   BN_free(e);
-   BN_free(d);
-   BN_free(p);
-   BN_free(q);
-   BN_free(dmp1);
-   BN_free(dmq1);
-   BN_free(iqmp);
+   BN_clear_free(n);
+   BN_clear_free(e);
+   BN_clear_free(d);
+   BN_clear_free(p);
+   BN_clear_free(q);
+   BN_clear_free(dmp1);
+   BN_clear_free(dmq1);
+   BN_clear_free(iqmp);
 
return -1;
}
-- 
2.1.0

[dpdk-dev] [PATCH] crypto/openssl: fix usage of non constant time memcmp for mac and signature

[Arek Kusztal]

ANSI C memcmp is not constant time function per spec so it should
be avoided in cryptography usage.

Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library")

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/openssl/rte_openssl_pmd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c 
b/drivers/crypto/openssl/rte_openssl_pmd.c
index 6504959..73ce383 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd.c
@@ -1529,7 +1529,7 @@ process_openssl_auth_op(struct openssl_qp *qp, struct 
rte_crypto_op *op,
}
 
if (sess->auth.operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
-   if (memcmp(dst, op->sym->auth.digest.data,
+   if (CRYPTO_memcmp(dst, op->sym->auth.digest.data,
sess->auth.digest_length) != 0) {
op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
}
@@ -1914,7 +1914,7 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
"Length of public_decrypt %d "
"length of message %zd\n",
ret, op->rsa.message.length);
-   if ((ret <= 0) || (memcmp(tmp, op->rsa.message.data,
+   if ((ret <= 0) || (CRYPTO_memcmp(tmp, op->rsa.message.data,
op->rsa.message.length))) {
OPENSSL_LOG(ERR, "RSA sign Verification failed");
cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
-- 
2.1.0

Re: [dpdk-dev] [PATCH v4 3/3] rxtx_callbacks: Add support for HW timestamp

[Ferruh Yigit]

On 5/2/2019 1:11 PM, Tom Barbette wrote:
> Use rxtx callback to demonstrate a way to use rte_eth_read_clock to
> convert the hardware timestamps to an amount of cycles.
> 
> This allows to get the amount of time the packet spent since its entry
> in the device. While the regular latency only shows the latency from
> when it entered the software stack.
> 
> Signed-off-by: Tom Barbette 

Reviewed-by: Ferruh Yigit 

Re: [dpdk-dev] [PATCH v4 0/3] Add rte_eth_read_clock API

[Ferruh Yigit]

On 5/2/2019 1:11 PM, Tom Barbette wrote:
> Some NICs allow to timestamp packets, but do not support the full
> PTP synchronization process. Hence, the value set in the mbuf
> timestamp field is only the raw value of an internal clock.
> 
> To make sense of this value, one at least needs to be able to query
> the current hardware clock value. This patch series adds a new API to do
> so, rte_eth_read_clock. As with the TSC, from there
> a frequency can be derieved by querying multiple time the current value of the
> internal clock with some known delay between the queries (example
> provided in the API doc).
> 
> This patch series adds support of read_clock for MLX5.
> 
> An example app is provided in the rxtx_callback application.
> It has been updated to display, on top of the software latency
> in cycles, the total latency since the packet was received in hardware.
> The API is used to compute a delta in the Tx callback. The raw amount of
> ticks is converted to cycles using a variation of the technique describe 
> above.
> 
> Aside from offloading timestamping, which relieve the
> software from a few operations, this allows to get much more precision
> when studying the source of the latency in a system.
> Eg. in our 100G, CX5 setup the rxtx callback application shows
> SW latency is around 74 cycles (TSC is 3.2Ghz), but the latency
> including NIC processing, PCIe, and queuing is around 196 cycles.
> 
> One may think at first this API is overlapping with te_eth_timesync_read_time.
> rte_eth_timesync_read_time is clearly identified as part of a set of functions
> to use PTP synchronization.
> The device raw clock is not "sync" in any way. More importantly, the returned
> value is not a timeval, but an amount of ticks. We could have a cast-based
> solution, but on top of being an ugly solution, some people seeing the timeval
> type of rte_eth_timesync_read_time could use it blindly.
> 
> Change in v2:
>   - Rebase on current master
> 
> Change in v3:
>   - Address comments from Ferruh Yigit
> 
> Changes in v4:
>   - Address comments from Keith Wiles and Andrew Rybchenko
>   - Use "clock" as argunment name everywhere.
>   - Expand the API description to make clear that read_clock gives an
> amount in ticks, and that it has no unit.
> 
> Tom Barbette (3):
>   rte_ethdev: Add API function to read dev clock
>   mlx5: Implement support for read_clock
>   rxtx_callbacks: Add support for HW timestamp

Series applied to dpdk-next-net/master, thanks.

Re: [dpdk-dev] [PATCH v10] net/memif: introduce memory interface (memif) PMD

[Ye Xiaolong]

Minor nit, this should be a V1 instead of V10 after your RFC.

On 05/31, Jakub Grajciar wrote:
>Memory interface (memif), provides high performance
>packet transfer over shared memory.

It'd be better to have more descrition of this new PMD in the commit log, 
something 
like you have in memif.rst

Thanks,
Xiaolong

Re: [dpdk-dev] [PATCH] app/test: add unit test cases for mbuf library APIs

[Pattan, Reshma]

> -Original Message-
> From: Govindarajan, LavanyaX
> Sent: Monday, April 15, 2019 1:40 PM
> To: dev@dpdk.org
> Cc: Pattan, Reshma ; olivier.m...@6wind.com;
> Richardson, Bruce ; Govindarajan, LavanyaX
> 
> Subject: [PATCH] app/test: add unit test cases for mbuf library APIs
> 



> __func__);
> + if (rte_pktmbuf_data_len(pkt_seg) !=
> + MBUF_TEST_SEG_SIZE)
> + GOTO_FAIL("%s: Bad data length\n",
> __func__);
> + memset(data, (seg + nb_pkt + 0xaa) % 0x0ff,
> + MBUF_TEST_SEG_SIZE);
> +

Also nb_pkt+0xaa is common for all segments, so  doing the addition for each 
segments waste of cycles, so move to addition out for segments for loop.

Other than that, please keep reviewed-by in next versions.

Reviewed-By: Reshma Pattan 

Thanks,
Reshma

[dpdk-dev] [PATCH] usertools: Fix clearing any old data

[Timothy Redaelli]

Currently clear_data (dpdk-devbind.py) doesn't work as expected since
"global devices" is missing and so "devices" is considered a local variable.

This commit changes "clear_data" function in order to really clear
devices by adding "global devices".

CC: sta...@dpdk.org

Signed-off-by: Timothy Redaelli 
---
 usertools/dpdk-devbind.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 9e79f0d28..e6b551d33 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -210,6 +210,7 @@ def get_pci_device_details(dev_id, probe_lspci):
 
 def clear_data():
 '''This function clears any old data'''
+global devices
 devices = {}
 
 def get_device_details(devices_type):
-- 
2.21.0

Re: [dpdk-dev] [PATCH] lib/telemetry: fix memory leak

[Laatz, Kevin]

On 29/05/2019 13:43, Reshma Pattan wrote:

Free the `values` pointer before returning
from rte_telemetry_command_ports_all_stat_values()
to avoid memory leak.

Fixes: c12cefa379 ("telemetry: fix mapping of statistics")
CC: sta...@dpdk.org
CC: bruce.richard...@intel.com

Signed-off-by: Reshma Pattan 
---
  lib/librte_telemetry/rte_telemetry_parser.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/lib/librte_telemetry/rte_telemetry_parser.c 
b/lib/librte_telemetry/rte_telemetry_parser.c
index 9bc16eef4..e9297021a 100644
--- a/lib/librte_telemetry/rte_telemetry_parser.c
+++ b/lib/librte_telemetry/rte_telemetry_parser.c
@@ -342,6 +342,7 @@ rte_telemetry_command_ports_all_stat_values(struct 
telemetry_impl *telemetry,
goto fail;
}
  
+	free(values);

return 0;
  
  fail:


Acked-by: Kevin Laatz 

Re: [dpdk-dev] [PATCH] lib/telemetry: add support to fetch global metrics

[Laatz, Kevin]

On 17/05/2019 17:07, Reshma Pattan wrote:

telemetry has support for fetching port based stats
from metrics library.

Metrics library also has global stats which are
not fetched by telemetry, so extend telemetry to
fetch the global metrics.

Signed-off-by: Reshma Pattan 
---
  doc/guides/howto/telemetry.rst|   9 +-
  doc/guides/rel_notes/release_19_08.rst|   5 +
  lib/librte_telemetry/rte_telemetry.c  | 119 
  lib/librte_telemetry/rte_telemetry_internal.h |  31 -
  lib/librte_telemetry/rte_telemetry_parser.c   | 130 +++---
  usertools/dpdk-telemetry-client.py|  13 +-
  6 files changed, 253 insertions(+), 54 deletions(-)


Looks good to me, thanks!


Acked-by: Kevin Laatz 

Re: [dpdk-dev] [dpdk-stable] [PATCH] usertools: Fix clearing any old data

[Luca Boccassi]

On Fri, 2019-05-31 at 13:11 +0200, Timothy Redaelli wrote:
> Currently clear_data (dpdk-devbind.py) doesn't work as expected since
> "global devices" is missing and so "devices" is considered a local
> variable.
> 
> This commit changes "clear_data" function in order to really clear
> devices by adding "global devices".
> 
> CC: 
> sta...@dpdk.org
> 
> 
> Signed-off-by: Timothy Redaelli <
> tredae...@redhat.com
> >
> ---
>  usertools/dpdk-devbind.py | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
> index 9e79f0d28..e6b551d33 100755
> --- a/usertools/dpdk-devbind.py
> +++ b/usertools/dpdk-devbind.py
> @@ -210,6 +210,7 @@ def get_pci_device_details(dev_id, probe_lspci):
>  
>  def clear_data():
>  '''This function clears any old data'''
> +global devices
>  devices = {}
>  
>  def get_device_details(devices_type):
> 

Acked-by: Luca Boccassi 

-- 
Kind regards,
Luca Boccassi

[dpdk-dev] [PATCH 0/3] Rework API for RSA algorithm in asymmetric crypto

[Arek Kusztal]

Major changes:
- Cipher field was introduced
- Padding struct was created
- PKCS1-v1_5 Block type 0 was removed
- Fixed comments about prime numbers, etc.

Arek Kusztal (3):
  cryptodev: rework api of rsa algorithm
  crypto/openssl: rework openssl rsa implementation
  test: rework rsa test implementation

 app/test/test_cryptodev_asym.c   |  11 ++-
 drivers/crypto/openssl/rte_openssl_pmd.c |  14 ++-
 lib/librte_cryptodev/rte_crypto_asym.h   | 149 +++
 3 files changed, 127 insertions(+), 47 deletions(-)

-- 
2.1.0

[dpdk-dev] [PATCH 1/3] cryptodev: rework api of rsa algorithm

[Arek Kusztal]

This patch reworks API of RSA algorithm.
Major changes:
- Cipher field was introduced
- Padding struct was created
- PKCS1-v1_5 Block type 0 was removed
- Fixed comments about prime numbers

Signed-off-by: Arek Kusztal 
---
 lib/librte_cryptodev/rte_crypto_asym.h | 149 +
 1 file changed, 114 insertions(+), 35 deletions(-)

diff --git a/lib/librte_cryptodev/rte_crypto_asym.h 
b/lib/librte_cryptodev/rte_crypto_asym.h
index 8672f21..bb94fa5 100644
--- a/lib/librte_cryptodev/rte_crypto_asym.h
+++ b/lib/librte_cryptodev/rte_crypto_asym.h
@@ -111,23 +111,33 @@ enum rte_crypto_asym_op_type {
  */
 enum rte_crypto_rsa_padding_type {
RTE_CRYPTO_RSA_PADDING_NONE = 0,
-   /**< RSA no padding scheme */
-   RTE_CRYPTO_RSA_PKCS1_V1_5_BT0,
-   /**< RSA PKCS#1 V1.5 Block Type 0 padding scheme
-* as described in rfc2313
-*/
-   RTE_CRYPTO_RSA_PKCS1_V1_5_BT1,
-   /**< RSA PKCS#1 V1.5 Block Type 01 padding scheme
-* as described in rfc2313
-*/
-   RTE_CRYPTO_RSA_PKCS1_V1_5_BT2,
-   /**< RSA PKCS#1 V1.5 Block Type 02 padding scheme
-* as described in rfc2313
+   /**< RSA no padding scheme.
+* In this case user is responsible for providing and verification
+* of padding.
+* In case RTE_CRYPTO_ASYM_OP_VERIFY op type is used if no
+* problems in public key 'encryption' detected driver SHALL return
+* RTE_CRYPTO_OP_STATUS_SUCCESS. But it is USER RESPONSABILITY to
+* remove padding and verify signature.
+*/
+   RTE_CRYPTO_RSA_PADDING_PKCS1,
+   /**< RSA PKCS#1 PKCS1-v1_5 padding scheme. For signatures block type 01,
+* for encryption block type 02 are used.
+*
+* In case RTE_CRYPTO_ASYM_OP_VERIFY op type is used crypto op status
+* is set to RTE_CRYPTO_OP_STATUS_SUCCESS when signature is properly
+* verified, RTE_CRYPTO_OP_STATUS_ERROR when it failed.
 */
RTE_CRYPTO_RSA_PADDING_OAEP,
-   /**< RSA PKCS#1 OAEP padding scheme */
+   /**< RSA PKCS#1 OAEP padding scheme, can be used only for encryption/
+* decryption.
+*/
RTE_CRYPTO_RSA_PADDING_PSS,
-   /**< RSA PKCS#1 PSS padding scheme */
+   /**< RSA PKCS#1 PSS padding scheme, can be used only for signatures.
+*
+* Crypto op status is set to RTE_CRYPTO_OP_STATUS_SUCCESS
+* when signature is properly verified, RTE_CRYPTO_OP_STATUS_ERROR
+* when it failed.
+*/
RTE_CRYPTO_RSA_PADDING_TYPE_LIST_END
 };
 
@@ -199,8 +209,8 @@ struct rte_crypto_rsa_priv_key_qt {
  */
 struct rte_crypto_rsa_xform {
rte_crypto_param n;
-   /**< n - Prime modulus
-* Prime modulus data of RSA operation in Octet-string network
+   /**< n - Modulus
+* Modulus data of RSA operation in Octet-string network
 * byte order format.
 */
 
@@ -397,11 +407,23 @@ struct rte_crypto_rsa_op_param {
/**<
 * Pointer to data
 * - to be encrypted for RSA public encrypt.
-* - to be decrypted for RSA private decrypt.
 * - to be signed for RSA sign generation.
 * - to be authenticated for RSA sign verification.
 */
 
+   rte_crypto_param cipher;
+   /**<
+* Pointer to data
+* - to be decrypted for RSA private decrypt.
+*
+* When RTE_CRYPTO_ASYM_OP_ENCRYPT op_type used size in bytes
+* of this field need to be equal to the size of corresponding
+* RSA key. Returned data is in Big-Endian format which means
+* that Least-Significant byte will be placed at top byte of an array
+* (at message.data[message.length - 1]), cipher.length SHALL
+* therefore remain unchanged.
+*/
+
rte_crypto_param sign;
/**<
 * Pointer to RSA signature data. If operation is RSA
@@ -410,25 +432,82 @@ struct rte_crypto_rsa_op_param {
 *
 * Length of the signature data will be equal to the
 * RSA prime modulus length.
-*/
-
-   enum rte_crypto_rsa_padding_type pad;
-   /**< RSA padding scheme to be used for transform */
-
-   enum rte_crypto_auth_algorithm md;
-   /**< Hash algorithm to be used for data hash if padding
-* scheme is either OAEP or PSS. Valid hash algorithms
-* are:
-* MD5, SHA1, SHA224, SHA256, SHA384, SHA512
-*/
-
-   enum rte_crypto_auth_algorithm mgf1md;
+*
+* Returned data is in Big-Endian format which means
+* that Least-Significant byte will be placed at top byte of an array
+* (at message.data[message.length - 1]), sign.length SHALL
+* therefore remain unchanged.
+*/
+
+   struct {
+   enum rte_crypto_rsa_padding_type type;
+   /**<
+* In case RTE_CRYPTO_RSA_PADDING_PKCS1 is selected,
+* driver will distinguish between block 

[dpdk-dev] [PATCH 2/3] crypto/openssl: rework openssl rsa implementation

[Arek Kusztal]

This commit reworks implementation of RSA algorithm
in OPENSSL PMD to be conformant to API changes.

Signed-off-by: Arek Kusztal 
---
 drivers/crypto/openssl/rte_openssl_pmd.c | 14 ++
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c 
b/drivers/crypto/openssl/rte_openssl_pmd.c
index 73ce383..b0a8ea2 100644
--- a/drivers/crypto/openssl/rte_openssl_pmd.c
+++ b/drivers/crypto/openssl/rte_openssl_pmd.c
@@ -1842,15 +1842,13 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
int ret = 0;
struct rte_crypto_asym_op *op = cop->asym;
RSA *rsa = sess->u.r.rsa;
-   uint32_t pad = (op->rsa.pad);
+   uint32_t pad = (op->rsa.padding.type);
uint8_t *tmp;
 
cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 
switch (pad) {
-   case RTE_CRYPTO_RSA_PKCS1_V1_5_BT0:
-   case RTE_CRYPTO_RSA_PKCS1_V1_5_BT1:
-   case RTE_CRYPTO_RSA_PKCS1_V1_5_BT2:
+   case RTE_CRYPTO_RSA_PADDING_PKCS1:
pad = RSA_PKCS1_PADDING;
break;
case RTE_CRYPTO_RSA_PADDING_NONE:
@@ -1867,19 +1865,19 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
case RTE_CRYPTO_ASYM_OP_ENCRYPT:
ret = RSA_public_encrypt(op->rsa.message.length,
op->rsa.message.data,
-   op->rsa.message.data,
+   op->rsa.cipher.data,
rsa,
pad);
 
if (ret > 0)
-   op->rsa.message.length = ret;
+   op->rsa.cipher.length = ret;
OPENSSL_LOG(DEBUG,
"length of encrypted text %d\n", ret);
break;
 
case RTE_CRYPTO_ASYM_OP_DECRYPT:
-   ret = RSA_private_decrypt(op->rsa.message.length,
-   op->rsa.message.data,
+   ret = RSA_private_decrypt(op->rsa.cipher.length,
+   op->rsa.cipher.data,
op->rsa.message.data,
rsa,
pad);
-- 
2.1.0

[dpdk-dev] [PATCH 3/3] test: rework rsa test implementation

[Arek Kusztal]

This commit reworks rsa test implementation to be conformant
to the RSA API.

Signed-off-by: Arek Kusztal 
---
 app/test/test_cryptodev_asym.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c
index fc92d3d..ea786ba 100644
--- a/app/test/test_cryptodev_asym.c
+++ b/app/test/test_cryptodev_asym.c
@@ -402,7 +402,7 @@ test_rsa_sign_verify(void)
asym_op->rsa.message.data = input_buf;
asym_op->rsa.message.length = rsaplaintext.len;
asym_op->rsa.sign.data = output_buf;
-   asym_op->rsa.pad = RTE_CRYPTO_RSA_PKCS1_V1_5_BT1;
+   asym_op->rsa.padding.type = RTE_CRYPTO_RSA_PADDING_PKCS1;
 
debug_hexdump(stdout, "message", asym_op->rsa.message.data,
asym_op->rsa.message.length);
@@ -437,7 +437,7 @@ test_rsa_sign_verify(void)
 
/* Verify sign */
asym_op->rsa.op_type = RTE_CRYPTO_ASYM_OP_VERIFY;
-   asym_op->rsa.pad = RTE_CRYPTO_RSA_PKCS1_V1_5_BT2;
+   asym_op->rsa.padding.type = RTE_CRYPTO_RSA_PADDING_PKCS1;
 
/* Process crypto operation */
if (rte_cryptodev_enqueue_burst(dev_id, 0, &op, 1) != 1) {
@@ -495,6 +495,7 @@ test_rsa_enc_dec(void)
struct rte_cryptodev_asym_session *sess = NULL;
int status = TEST_SUCCESS;
uint8_t input_buf[TEST_DATA_SIZE] = {0};
+   uint8_t cipher_buf[TEST_DATA_SIZE] = {0};
 
/* test case supports op with exponent key only,
 * Check in PMD feature flag for RSA exponent key type support.
@@ -547,7 +548,9 @@ test_rsa_enc_dec(void)
rsaplaintext.len);
asym_op->rsa.message.data = input_buf;
asym_op->rsa.message.length = rsaplaintext.len;
-   asym_op->rsa.pad = RTE_CRYPTO_RSA_PKCS1_V1_5_BT2;
+   asym_op->rsa.cipher.data = cipher_buf;
+   asym_op->rsa.cipher.length = 0;
+   asym_op->rsa.padding.type = RTE_CRYPTO_RSA_PADDING_PKCS1;
 
debug_hexdump(stdout, "message", asym_op->rsa.message.data,
asym_op->rsa.message.length);
@@ -581,7 +584,7 @@ test_rsa_enc_dec(void)
/* Use the resulted output as decryption Input vector*/
asym_op = result_op->asym;
asym_op->rsa.op_type = RTE_CRYPTO_ASYM_OP_DECRYPT;
-   asym_op->rsa.pad = RTE_CRYPTO_RSA_PKCS1_V1_5_BT1;
+   asym_op->rsa.padding.type = RTE_CRYPTO_RSA_PADDING_PKCS1;
 
/* Process crypto operation */
if (rte_cryptodev_enqueue_burst(dev_id, 0, &op, 1) != 1) {
-- 
2.1.0

Re: [dpdk-dev] [PATCH v2] net/avp: remove resources when port is closed

[Peters, Matt]

> -Original Message-
> From: Legacy, Allain
> Sent: Monday, May 27, 2019 1:03 PM
> To: tho...@monjalon.net
> Cc: dev@dpdk.org; ferruh.yi...@intel.com; Peters, Matt
> Subject: [PATCH v2] net/avp: remove resources when port is closed
> 
> The rte_eth_dev_close() function now handles freeing resources for
> devices (e.g., mac_addrs).  To conform with the new close() behaviour we
> are asserting the RTE_ETH_DEV_CLOSE_REMOVE flag so that
> rte_eth_dev_close() releases all device level dynamic memory.
> 
> Second level memory allocated to each individual rx/tx queue is now
> freed as part of the close() operation therefore making it safe for the
> rte_eth_dev_close() function to free the device private data without
> orphaning the rx/tx queue pointers.
> 
> Cc: Matt Peters 
> Signed-off-by: Allain Legacy 
> ---
Acked-by: Matt Peters 

Re: [dpdk-dev] [PATCH] net/softnic: fix pipeline time calculation

[Singh, Jasvinder]

> -Original Message-
> From: Wang, Xiao W
> Sent: Wednesday, May 15, 2019 2:59 PM
> To: Singh, Jasvinder 
> Cc: dev@dpdk.org; Dumitrescu, Cristian ;
> Wang, Xiao W ; sta...@dpdk.org
> Subject: [PATCH] net/softnic: fix pipeline time calculation
> 
> When a new pipeline is added to a thread, the "time_next_min" value may
> need update, otherwise this pipeline won't get served timely.
> 
> Fixes: 70709c78fda6 ("net/softnic: add command to enable/disable pipeline")
> Cc: sta...@dpdk.org
> 
> Signed-off-by: Xiao Wang 
> ---
>  drivers/net/softnic/rte_eth_softnic_thread.c | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/net/softnic/rte_eth_softnic_thread.c
> b/drivers/net/softnic/rte_eth_softnic_thread.c
> index 855408e98..2b482117d 100644
> --- a/drivers/net/softnic/rte_eth_softnic_thread.c
> +++ b/drivers/net/softnic/rte_eth_softnic_thread.c
> @@ -337,6 +337,9 @@ softnic_thread_pipeline_enable(struct pmd_internals
> *softnic,
>   tdp->timer_period = (rte_get_tsc_hz() * p->timer_period_ms) /
> 1000;
>   tdp->time_next = rte_get_tsc_cycles() + tdp->timer_period;
> 
> + if (tdp->time_next < td->time_next_min)
> + td->time_next_min = tdp->time_next;
> +
>   td->n_pipelines++;
> 
>   /* Pipeline */
> @@ -522,6 +525,9 @@ thread_msg_handle_pipeline_enable(struct
> softnic_thread_data *t,
>   (rte_get_tsc_hz() * req->pipeline_enable.timer_period_ms) /
> 1000;
>   p->time_next = rte_get_tsc_cycles() + p->timer_period;
> 
> + if (p->time_next < t->time_next_min)
> + t->time_next_min = p->time_next;
> +
>   t->n_pipelines++;
> 
>   /* Response */
> --
> 2.15.1


Hi Wang, 

Timer values for pipelines and thread level message handlers are already 
adjusted in runtime function rte_pmd_softnic_run_internal(). In runtime 
function, the values of t->time_next_min is updated as well. IMO, above changes 
not needed. Could you help with the case where timer adjustments in runtime not 
working?

Thanks,
Jasvinder
 

Re: [dpdk-dev] [PATCH] crypto/openssl: fix usage of non constant time memcmp for mac and signature

[Trahe, Fiona]

> -Original Message-
> From: Kusztal, ArkadiuszX
> Sent: Friday, May 31, 2019 7:59 AM
> To: dev@dpdk.org
> Cc: akhil.go...@nxp.com; Trahe, Fiona ; Doherty, Declan
> ; Kusztal, ArkadiuszX 
> Subject: [PATCH] crypto/openssl: fix usage of non constant time memcmp for 
> mac and signature
> 
> ANSI C memcmp is not constant time function per spec so it should
> be avoided in cryptography usage.
> 
> Fixes: d61f70b4c918 ("crypto/libcrypto: add driver for OpenSSL library")
> 
> Signed-off-by: Arek Kusztal 
> ---
>  drivers/crypto/openssl/rte_openssl_pmd.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/crypto/openssl/rte_openssl_pmd.c 
> b/drivers/crypto/openssl/rte_openssl_pmd.c
> index 6504959..73ce383 100644
> --- a/drivers/crypto/openssl/rte_openssl_pmd.c
> +++ b/drivers/crypto/openssl/rte_openssl_pmd.c
> @@ -1529,7 +1529,7 @@ process_openssl_auth_op(struct openssl_qp *qp, struct 
> rte_crypto_op *op,
>   }
> 
>   if (sess->auth.operation == RTE_CRYPTO_AUTH_OP_VERIFY) {
> - if (memcmp(dst, op->sym->auth.digest.data,
> + if (CRYPTO_memcmp(dst, op->sym->auth.digest.data,
>   sess->auth.digest_length) != 0) {
>   op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
>   }
> @@ -1914,7 +1914,7 @@ process_openssl_rsa_op(struct rte_crypto_op *cop,
>   "Length of public_decrypt %d "
>   "length of message %zd\n",
>   ret, op->rsa.message.length);
> - if ((ret <= 0) || (memcmp(tmp, op->rsa.message.data,
> + if ((ret <= 0) || (CRYPTO_memcmp(tmp, op->rsa.message.data,
>   op->rsa.message.length))) {
>   OPENSSL_LOG(ERR, "RSA sign Verification failed");
>   cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
> --
> 2.1.0
Hadn't heard of that time const fn before so just read up on it - interesting.
Acked-by: Fiona Trahe 

Re: [dpdk-dev] [PATCH v2] net/avp: remove resources when port is closed

[Ye Xiaolong]

On 05/27, Allain Legacy wrote:
>The rte_eth_dev_close() function now handles freeing resources for
>devices (e.g., mac_addrs).  To conform with the new close() behaviour we
>are asserting the RTE_ETH_DEV_CLOSE_REMOVE flag so that
>rte_eth_dev_close() releases all device level dynamic memory.
>
>Second level memory allocated to each individual rx/tx queue is now
>freed as part of the close() operation therefore making it safe for the
>rte_eth_dev_close() function to free the device private data without
>orphaning the rx/tx queue pointers.
>
>Cc: Matt Peters 
>Signed-off-by: Allain Legacy 

Reviewed-by: Xiaolong Ye 

[dpdk-dev] [PATCH v5 1/5] eal: use unsigned int in lcore API prototypes

[David Marchand]

From: Stephen Hemminger 

Purely cosmetic change, use unsigned int instead of unsigned alone.

Signed-off-by: Stephen Hemminger 
Signed-off-by: David Marchand 
---
 lib/librte_eal/common/include/rte_lcore.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

Changelog since v3:
- updated title

diff --git a/lib/librte_eal/common/include/rte_lcore.h 
b/lib/librte_eal/common/include/rte_lcore.h
index be757a3..705594a 100644
--- a/lib/librte_eal/common/include/rte_lcore.h
+++ b/lib/librte_eal/common/include/rte_lcore.h
@@ -137,7 +137,7 @@ struct lcore_config {
  * @return
  *   the ID of current lcoreid's physical socket
  */
-unsigned rte_socket_id(void);
+unsigned int rte_socket_id(void);
 
 /**
  * Return number of physical sockets detected on the system.
@@ -177,8 +177,8 @@ struct lcore_config {
  * @return
  *   the ID of lcoreid's physical socket
  */
-static inline unsigned
-rte_lcore_to_socket_id(unsigned lcore_id)
+static inline unsigned int
+rte_lcore_to_socket_id(unsigned int lcore_id)
 {
return lcore_config[lcore_id].socket_id;
 }
@@ -193,7 +193,7 @@ struct lcore_config {
  *   True if the given lcore is enabled; false otherwise.
  */
 static inline int
-rte_lcore_is_enabled(unsigned lcore_id)
+rte_lcore_is_enabled(unsigned int lcore_id)
 {
struct rte_config *cfg = rte_eal_get_configuration();
if (lcore_id >= RTE_MAX_LCORE)
@@ -214,8 +214,8 @@ struct lcore_config {
  * @return
  *   The next lcore_id or RTE_MAX_LCORE if not found.
  */
-static inline unsigned
-rte_get_next_lcore(unsigned i, int skip_master, int wrap)
+static inline unsigned int
+rte_get_next_lcore(unsigned int i, int skip_master, int wrap)
 {
i++;
if (wrap)
-- 
1.8.3.1

[dpdk-dev] [PATCH v5 2/5] eal: add lcore accessors

[David Marchand]

From: Stephen Hemminger 

The fields of the internal EAL core configuration are currently
laid bare as part of the API. This is not good practice and limits
fixing issues with layout and sizes.

Make new accessor functions for the fields used by current drivers
and examples.

Signed-off-by: Stephen Hemminger 
Signed-off-by: David Marchand 
---
 lib/librte_eal/common/eal_common_lcore.c  | 33 +++
 lib/librte_eal/common/include/rte_lcore.h | 44 +--
 lib/librte_eal/rte_eal_version.map| 12 +
 3 files changed, 75 insertions(+), 14 deletions(-)

---
Changelog since v4:
- marked rte_lcore_to_cpu_id and rte_lcore_cpuset as experimental

Changelog since v3:
- updated title
- rebased on master
- removed doc update
- removed unneeded rte_lcore_return_code

diff --git a/lib/librte_eal/common/eal_common_lcore.c 
b/lib/librte_eal/common/eal_common_lcore.c
index 8c2744f..38af260 100644
--- a/lib/librte_eal/common/eal_common_lcore.c
+++ b/lib/librte_eal/common/eal_common_lcore.c
@@ -16,6 +16,39 @@
 #include "eal_private.h"
 #include "eal_thread.h"
 
+int rte_lcore_index(int lcore_id)
+{
+   if (unlikely(lcore_id >= RTE_MAX_LCORE))
+   return -1;
+
+   if (lcore_id < 0)
+   lcore_id = (int)rte_lcore_id();
+
+   return lcore_config[lcore_id].core_index;
+}
+
+int rte_lcore_to_cpu_id(int lcore_id)
+{
+   if (unlikely(lcore_id >= RTE_MAX_LCORE))
+   return -1;
+
+   if (lcore_id < 0)
+   lcore_id = (int)rte_lcore_id();
+
+   return lcore_config[lcore_id].core_id;
+}
+
+rte_cpuset_t rte_lcore_cpuset(unsigned int lcore_id)
+{
+   return lcore_config[lcore_id].cpuset;
+}
+
+unsigned int
+rte_lcore_to_socket_id(unsigned int lcore_id)
+{
+   return lcore_config[lcore_id].socket_id;
+}
+
 static int
 socket_id_cmp(const void *a, const void *b)
 {
diff --git a/lib/librte_eal/common/include/rte_lcore.h 
b/lib/librte_eal/common/include/rte_lcore.h
index 705594a..1e3c887 100644
--- a/lib/librte_eal/common/include/rte_lcore.h
+++ b/lib/librte_eal/common/include/rte_lcore.h
@@ -121,15 +121,7 @@ struct lcore_config {
  * @return
  *   The relative index, or -1 if not enabled.
  */
-static inline int
-rte_lcore_index(int lcore_id)
-{
-   if (lcore_id >= RTE_MAX_LCORE)
-   return -1;
-   if (lcore_id < 0)
-   lcore_id = (int)rte_lcore_id();
-   return lcore_config[lcore_id].core_index;
-}
+int rte_lcore_index(int lcore_id);
 
 /**
  * Return the ID of the physical socket of the logical core we are
@@ -177,11 +169,35 @@ struct lcore_config {
  * @return
  *   the ID of lcoreid's physical socket
  */
-static inline unsigned int
-rte_lcore_to_socket_id(unsigned int lcore_id)
-{
-   return lcore_config[lcore_id].socket_id;
-}
+unsigned int
+rte_lcore_to_socket_id(unsigned int lcore_id);
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Return the id of the lcore on a socket starting from zero.
+ *
+ * @param lcore_id
+ *   The targeted lcore, or -1 for the current one.
+ * @return
+ *   The relative index, or -1 if not enabled.
+ */
+__rte_experimental int
+rte_lcore_to_cpu_id(int lcore_id);
+
+/**
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice.
+ *
+ * Return the cpuset for a given lcore.
+ * @param lcore_id
+ *   the targeted lcore, which MUST be between 0 and RTE_MAX_LCORE-1.
+ * @return
+ *   The cpuset of that lcore
+ */
+__rte_experimental rte_cpuset_t
+rte_lcore_cpuset(unsigned int lcore_id);
 
 /**
  * Test if an lcore is enabled.
diff --git a/lib/librte_eal/rte_eal_version.map 
b/lib/librte_eal/rte_eal_version.map
index 2454934..824edf0 100644
--- a/lib/librte_eal/rte_eal_version.map
+++ b/lib/librte_eal/rte_eal_version.map
@@ -287,6 +287,14 @@ DPDK_19.05 {
 
 } DPDK_18.11;
 
+DPDK_19.08 {
+   global:
+
+   rte_lcore_index;
+   rte_lcore_to_socket_id;
+
+} DPDK_19.05;
+
 EXPERIMENTAL {
global:
 
@@ -378,4 +386,8 @@ EXPERIMENTAL {
rte_service_lcore_attr_get;
rte_service_lcore_attr_reset_all;
rte_service_may_be_active;
+
+   # added in 19.08
+   rte_lcore_cpuset;
+   rte_lcore_to_cpu_id;
 };
-- 
1.8.3.1

[dpdk-dev] [PATCH v5 0/5] make lcore_config internal

[David Marchand]

This set of patches makes the lcore_config structure less visible
as part of the ABI.  This version does not break the ABI (yet)
follow on patch moves lcore_config into eal_private.h

Changelog since v4:
The only change is in patch 2: marked new apis as experimental.

Changelog since v3:
I took the liberty of taking over Stephen series.
I rebased and did some adjustments following [1] cleanups.
As stated before, we will still need a deprecation notice when hiding
lcore_config but this series does not break API nor ABI.

Changelog since v2:
 - new patch to use unsigned int in lcore.h first
 - incorporate feedback from David
 - don't include last patch to make it private
(to avoid accidental early merge)

1: http://patchwork.dpdk.org/patch/53621/

-- 
David Marchand

Stephen Hemminger (5):
  eal: use unsigned int in lcore API prototypes
  eal: add lcore accessors
  drivers/bus: use lcore accessors
  examples/bond: use lcore accessors
  test: use lcore accessors

 app/test/test_cryptodev.c |  2 +-
 app/test/test_ring_perf.c | 22 +++--
 app/test/test_stack_perf.c| 20 ++--
 drivers/bus/dpaa/dpaa_bus.c   |  6 ++--
 drivers/bus/fslmc/portal/dpaa2_hw_dpio.c  |  4 ++-
 examples/bond/main.c  | 13 
 lib/librte_eal/common/eal_common_lcore.c  | 33 
 lib/librte_eal/common/include/rte_lcore.h | 52 ---
 lib/librte_eal/rte_eal_version.map| 12 +++
 9 files changed, 116 insertions(+), 48 deletions(-)

-- 
1.8.3.1

[dpdk-dev] [PATCH v5 3/5] drivers/bus: use lcore accessors

[David Marchand]

From: Stephen Hemminger 

The lcore_config structure will be hidden in future release.

Signed-off-by: Stephen Hemminger 
Signed-off-by: David Marchand 
---
 drivers/bus/dpaa/dpaa_bus.c  | 6 --
 drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 4 +++-
 2 files changed, 7 insertions(+), 3 deletions(-)

---
Changelog since v3:
- updated title

diff --git a/drivers/bus/dpaa/dpaa_bus.c b/drivers/bus/dpaa/dpaa_bus.c
index ac20ecc..08c8227 100644
--- a/drivers/bus/dpaa/dpaa_bus.c
+++ b/drivers/bus/dpaa/dpaa_bus.c
@@ -254,6 +254,7 @@ int rte_dpaa_portal_init(void *arg)
unsigned int cpu, lcore = rte_lcore_id();
int ret;
struct dpaa_portal *dpaa_io_portal;
+   rte_cpuset_t cpuset;
 
BUS_INIT_FUNC_TRACE();
 
@@ -263,12 +264,13 @@ int rte_dpaa_portal_init(void *arg)
if (lcore >= RTE_MAX_LCORE)
return -1;
 
-   cpu = lcore_config[lcore].core_id;
+   cpu = rte_lcore_to_cpu_id(lcore);
 
/* Set CPU affinity for this thread.*/
id = pthread_self();
+   cpuset = rte_lcore_cpuset(lcore);
ret = pthread_setaffinity_np(id, sizeof(cpu_set_t),
-   &lcore_config[lcore].cpuset);
+&cpuset);
if (ret) {
DPAA_BUS_LOG(ERR, "pthread_setaffinity_np failed on core :%u"
 " (lcore=%u) with ret: %d", cpu, lcore, ret);
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c 
b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
index 7bcbde8..8efb24a 100644
--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c
@@ -366,7 +366,9 @@ static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int 
lcoreid)
 
for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
for (i = 0; i < RTE_MAX_LCORE; i++) {
-   if (CPU_ISSET(i, &lcore_config[lcore_id].cpuset)) {
+   rte_cpuset_t cpuset = rte_lcore_cpuset(lcore_id);
+
+   if (CPU_ISSET(i, &cpuset)) {
RTE_LOG(DEBUG, EAL, "lcore id = %u cpu=%u\n",
lcore_id, i);
if (dpaa2_cpu[lcore_id] != 0x) {
-- 
1.8.3.1

[dpdk-dev] [PATCH v5 4/5] examples/bond: use lcore accessors

[David Marchand]

From: Stephen Hemminger 

Referring to lcore_config directly is no longer recommended.
Also remove unnecessary assignment of slave_core_id.

Signed-off-by: Stephen Hemminger 
Signed-off-by: David Marchand 
---
 examples/bond/main.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

---
Changelog since v3:
- updated title

diff --git a/examples/bond/main.c b/examples/bond/main.c
index 9b9ed56..4c650ef 100644
--- a/examples/bond/main.c
+++ b/examples/bond/main.c
@@ -531,8 +531,9 @@ static void cmd_start_parsed(__attribute__((unused)) void 
*parsed_result,
int slave_core_id = rte_lcore_id();
 
rte_spinlock_trylock(&global_flag_stru_p->lock);
-   if (global_flag_stru_p->LcoreMainIsRunning == 0){
-   if (lcore_config[global_flag_stru_p->LcoreMainCore].state != 
WAIT)  {
+   if (global_flag_stru_p->LcoreMainIsRunning == 0) {
+   if (rte_eal_get_lcore_state(global_flag_stru_p->LcoreMainCore)
+   != WAIT) {
rte_spinlock_unlock(&global_flag_stru_p->lock);
return;
}
@@ -765,7 +766,7 @@ static void prompt(__attribute__((unused)) void *arg1)
 int
 main(int argc, char *argv[])
 {
-   int ret;
+   int ret, slave_core_id;
uint16_t nb_ports, i;
 
/* init EAL */
@@ -797,13 +798,13 @@ static void prompt(__attribute__((unused)) void *arg1)
bond_port_init(mbuf_pool);
 
rte_spinlock_init(&global_flag_stru_p->lock);
-   int slave_core_id = rte_lcore_id();
 
/* check state of lcores */
RTE_LCORE_FOREACH_SLAVE(slave_core_id) {
-   if (lcore_config[slave_core_id].state != WAIT)
-   return -EBUSY;
+   if (rte_eal_get_lcore_state(slave_core_id) != WAIT)
+   return -EBUSY;
}
+
/* start lcore main on core != master_core - ARP response thread */
slave_core_id = rte_get_next_lcore(rte_lcore_id(), 1, 0);
if ((slave_core_id >= RTE_MAX_LCORE) || (slave_core_id == 0))
-- 
1.8.3.1

[dpdk-dev] [PATCH v5 5/5] test: use lcore accessors

[David Marchand]

From: Stephen Hemminger 

Don't refer to lcore_config directly.

Signed-off-by: Stephen Hemminger 
Signed-off-by: David Marchand 
---
 app/test/test_cryptodev.c  |  2 +-
 app/test/test_ring_perf.c  | 22 --
 app/test/test_stack_perf.c | 20 ++--
 3 files changed, 23 insertions(+), 21 deletions(-)

---
Changelog since v3:
- updated title
- removed parts on test_hash_readwrite_lf

diff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c
index 9f31aaa..eca6d3d 100644
--- a/app/test/test_cryptodev.c
+++ b/app/test/test_cryptodev.c
@@ -378,7 +378,7 @@ struct crypto_unittest_params {
strcpy(temp_str, vdev_args);
strlcat(temp_str, ";", sizeof(temp_str));
slave_core_count++;
-   socket_id = lcore_config[i].socket_id;
+   socket_id = rte_lcore_to_socket_id(i);
}
if (slave_core_count != 2) {
RTE_LOG(ERR, USER1,
diff --git a/app/test/test_ring_perf.c b/app/test/test_ring_perf.c
index ebb3939..6ef 100644
--- a/app/test/test_ring_perf.c
+++ b/app/test/test_ring_perf.c
@@ -52,10 +52,11 @@ struct lcore_pair {
RTE_LCORE_FOREACH(id2) {
if (id1 == id2)
continue;
-   c1 = lcore_config[id1].core_id;
-   c2 = lcore_config[id2].core_id;
-   s1 = lcore_config[id1].socket_id;
-   s2 = lcore_config[id2].socket_id;
+
+   c1 = rte_lcore_to_cpu_id(id1);
+   c2 = rte_lcore_to_cpu_id(id2);
+   s1 = rte_lcore_to_socket_id(id1);
+   s2 = rte_lcore_to_socket_id(id2);
if ((c1 == c2) && (s1 == s2)){
lcp->c1 = id1;
lcp->c2 = id2;
@@ -75,10 +76,11 @@ struct lcore_pair {
RTE_LCORE_FOREACH(id2) {
if (id1 == id2)
continue;
-   c1 = lcore_config[id1].core_id;
-   c2 = lcore_config[id2].core_id;
-   s1 = lcore_config[id1].socket_id;
-   s2 = lcore_config[id2].socket_id;
+
+   c1 = rte_lcore_to_cpu_id(id1);
+   c2 = rte_lcore_to_cpu_id(id2);
+   s1 = rte_lcore_to_socket_id(id1);
+   s2 = rte_lcore_to_socket_id(id2);
if ((c1 != c2) && (s1 == s2)){
lcp->c1 = id1;
lcp->c2 = id2;
@@ -98,8 +100,8 @@ struct lcore_pair {
RTE_LCORE_FOREACH(id2) {
if (id1 == id2)
continue;
-   s1 = lcore_config[id1].socket_id;
-   s2 = lcore_config[id2].socket_id;
+   s1 = rte_lcore_to_socket_id(id1);
+   s2 = rte_lcore_to_socket_id(id2);
if (s1 != s2){
lcp->c1 = id1;
lcp->c2 = id2;
diff --git a/app/test/test_stack_perf.c b/app/test/test_stack_perf.c
index ba27fbf..70561fe 100644
--- a/app/test/test_stack_perf.c
+++ b/app/test/test_stack_perf.c
@@ -44,10 +44,10 @@ struct lcore_pair {
RTE_LCORE_FOREACH(id[1]) {
if (id[0] == id[1])
continue;
-   core[0] = lcore_config[id[0]].core_id;
-   core[1] = lcore_config[id[1]].core_id;
-   socket[0] = lcore_config[id[0]].socket_id;
-   socket[1] = lcore_config[id[1]].socket_id;
+   core[0] = rte_lcore_to_cpu_id(id[0]);
+   core[1] = rte_lcore_to_cpu_id(id[1]);
+   socket[0] = rte_lcore_to_socket_id(id[0]);
+   socket[1] = rte_lcore_to_socket_id(id[1]);
if ((core[0] == core[1]) && (socket[0] == socket[1])) {
lcp->c1 = id[0];
lcp->c2 = id[1];
@@ -70,10 +70,10 @@ struct lcore_pair {
RTE_LCORE_FOREACH(id[1]) {
if (id[0] == id[1])
continue;
-   core[0] = lcore_config[id[0]].core_id;
-   core[1] = lcore_config[id[1]].core_id;
-   socket[0] = lcore_config[id[0]].socket_id;
-   socket[1] = lcore_config[id[1]].socket_id;
+   core[0] = rte_lcore_to_cpu_id(id[0]);
+   core[1] = rte_lcore_to_cpu_id(id[1]);
+   socket[0] = rte_lcore_to_socket_id(id[0]);
+   socket[1] = rte_lcore_to_socket_id(id[1]);
if ((core

Re: [dpdk-dev] [PATCH v2] ipsec: include high order bytes of esn in pkt len

[Lukas Bartosik]

Hi Konstantin

On 30.05.2019 18:51, Ananyev, Konstantin wrote:
> Hi Lukasz,
> 
>> diff --git a/lib/librte_ipsec/esp_outb.c b/lib/librte_ipsec/esp_outb.c
>> index c798bc4..ed5974b 100644
>> --- a/lib/librte_ipsec/esp_outb.c
>> +++ b/lib/librte_ipsec/esp_outb.c
>> @@ -126,11 +126,11 @@ outb_tun_pkt_prepare(struct rte_ipsec_sa *sa, 
>> rte_be64_t sqc,
>>
>>  /* pad length + esp tail */
>>  pdlen = clen - plen;
>> -tlen = pdlen + sa->icv_len;
>> +tlen = pdlen + sa->icv_len + sa->sqh_len;
> 
> We probably don't want to increase pkt_len by  sa->sqh_len for inline case.
> That's why I suggested to pass sqh_len as parameter to that function.
> Then for inline we can just pass 0.
> Do you see any obstacles with that approach?
> Same thought for transport mode.
> Konstantin
> 

I agree this is incorrect. I have missed inline case.
I will send revised patch.

Thanks,
Lukasz

>>
>>  /* do append and prepend */
>>  ml = rte_pktmbuf_lastseg(mb);
>> -if (tlen + sa->sqh_len + sa->aad_len > rte_pktmbuf_tailroom(ml))
>> +if (tlen + sa->aad_len > rte_pktmbuf_tailroom(ml))
>>  return -ENOSPC;
>>
>>  /* prepend header */
>> @@ -152,8 +152,8 @@ outb_tun_pkt_prepare(struct rte_ipsec_sa *sa, rte_be64_t 
>> sqc,
>>  rte_memcpy(ph, sa->hdr, sa->hdr_len);
>>
>>  /* update original and new ip header fields */
>> -update_tun_l3hdr(sa, ph + sa->hdr_l3_off, mb->pkt_len, sa->hdr_l3_off,
>> -sqn_low16(sqc));
>> +update_tun_l3hdr(sa, ph + sa->hdr_l3_off, mb->pkt_len - sa->sqh_len,
>> +sa->hdr_l3_off, sqn_low16(sqc));
>>
>>  /* update spi, seqn and iv */
>>  esph = (struct esp_hdr *)(ph + sa->hdr_len);
>> @@ -292,11 +292,11 @@ outb_trs_pkt_prepare(struct rte_ipsec_sa *sa, 
>> rte_be64_t sqc,
>>
>>  /* pad length + esp tail */
>>  pdlen = clen - plen;
>> -tlen = pdlen + sa->icv_len;
>> +tlen = pdlen + sa->icv_len + sa->sqh_len;
>>
>>  /* do append and insert */
>>  ml = rte_pktmbuf_lastseg(mb);
>> -if (tlen + sa->sqh_len + sa->aad_len > rte_pktmbuf_tailroom(ml))
>> +if (tlen + sa->aad_len > rte_pktmbuf_tailroom(ml))
>>  return -ENOSPC;
>>
>>  /* prepend space for ESP header */
>> @@ -314,8 +314,8 @@ outb_trs_pkt_prepare(struct rte_ipsec_sa *sa, rte_be64_t 
>> sqc,
>>  insert_esph(ph, ph + hlen, uhlen);
>>
>>  /* update ip  header fields */
>> -np = update_trs_l3hdr(sa, ph + l2len, mb->pkt_len, l2len, l3len,
>> -IPPROTO_ESP);
>> +np = update_trs_l3hdr(sa, ph + l2len, mb->pkt_len - sa->sqh_len, l2len,
>> +l3len, IPPROTO_ESP);
>>
>>  /* update spi, seqn and iv */
>>  esph = (struct esp_hdr *)(ph + uhlen);
>> @@ -425,6 +425,9 @@ esp_outb_sqh_process(const struct rte_ipsec_session *ss, 
>> struct rte_mbuf *mb[],
>>  for (i = 0; i != num; i++) {
>>  if ((mb[i]->ol_flags & PKT_RX_SEC_OFFLOAD_FAILED) == 0) {
>>  ml = rte_pktmbuf_lastseg(mb[i]);
>> +/* remove high-order 32 bits of esn from packet len */
>> +mb[i]->pkt_len -= sa->sqh_len;
>> +ml->data_len -= sa->sqh_len;
>>  icv = rte_pktmbuf_mtod_offset(ml, void *,
>>  ml->data_len - icv_len);
>>  remove_sqh(icv, icv_len);

[dpdk-dev] [Bug 289] mlx5: 100G interface capability not recognized

[bugzilla]

https://bugs.dpdk.org/show_bug.cgi?id=289

Bug ID: 289
   Summary: mlx5: 100G interface capability not recognized
   Product: DPDK
   Version: 17.11
  Hardware: All
OS: All
Status: CONFIRMED
  Severity: normal
  Priority: Normal
 Component: ethdev
  Assignee: dev@dpdk.org
  Reporter: srinivas.nara...@att.com
  Target Milestone: ---

mlx5_link_update uses the newer ethtool command ETHTOOL_GLINKSETTINGS to
determine interface capabilities but falls back to the older (deprecated)
ETHTOOL_GSET command if the new method fails for any reason. The older method
only supports reporting of capabilities up to 40G.

However, mlx5_link_update_unlocked_gs can return a failure for a number of
reasons (including the link being down). Using the older method in cases of
transient failure of the method can result in reporting of reduced capabilities
to the application.

The older method (mlx5_link_update_unlocked_gset) should only be invoked if the
newer method returns EOPNOTSUPP.

-- 
You are receiving this mail because:
You are the assignee for the bug.

[dpdk-dev] [RFC 1/5] security: MACSEC infrastructure data declarations

[Igor Russkikh]

This RFC suggest possible API to implement generic MACSEC HW
offload in DPDK infrastructure.

Right now two PMDs implementing MACSEC hw offload via private
API: ixgbe (Intel) and atlantic (Aquantia).

During that private API discussion it was decided to go further
with well defined public API, based most probably on rte_security
infrastructure.

Here is that previous discussion:

http://inbox.dpdk.org/dev/20190416101145.nVecHKp3w14Ptd_hne-DqHhKyzbre88PwNI-OAowXJM@z/

Declaring macsec API via rte_security gives a good data-centric view on 
parameters
and operations macsec supports. Old, pure functional API (basically ixbe only 
API)
presented function calls with big argument lists which is hard to extend and 
analyse.

However, I'd like to note rte_security has to be used via explicitly created
mempools - this hardens abit the usage.
It also may be hard to extend the structures in the ABI compatible way.

One of the problems with MACSEC is that internally implementation and hardware
support could be either very simple, doing only endpoint encryption with a 
single
TX SC (Secure Connection), or quite complex, capable to do flexible filtering
and SC matching based on mac, vlan, ethertype and other.

Different macsec hardware supports some custom features and from our experience
users would like to configure these as well. Therefore there will probably be
needed a number of PMD specific macsec operators support.

Examples include: custom in-the-clear tag (matched by vlan id or mask),
configurable internal logic to allow both secure and unsecure traffic,
bypass filters on specific ethertypes.
To support such extensions, suggest use rte_security_macsec_op enum with
vendor specific operation codes.

In context of rte_security, MACSEC operations should normally be based on
security session create and update calls.

Session create is used to setup overall session. Thats equivalent of old
`macsec enable` operation.

Session update is used to update security connections and associations.
Here xform->op contains the required operation: rx/tx session/association
add/update/removal.

This RFC contains:
- patch 1 is rte_security data structures declaration
- patches 2-4 is a draft on how testpmd based invocations of rte_security
  API will look like
- patch 5 is a draft on how PMD driver will implement security infrastructure

To be done/decide:
- testpmd macsec command layout changes: encryption and repl protection
  are properties of SC, not the overall connection.
- add missing documentation and comments to all the structures
- full testpmd macsec API adoption
- ixgbe api adoptation
- atlantic api adiptation
- decide on how to declare SA (Security Associations) auto rollover and
  some other important features.
- interrupt event callback detalization of possible macsec events.
  Notice that it is not a part of rte_security, but a part of rte_ethdev.
- macsec statistics is now part of xstats list. Alternatively it could be
  moved to rte_security statistics. The hard thing is that stats are
  often available per SC/SA, a special API is required to fetch that.

Signed-off-by: Igor Russkikh 
---
 lib/librte_security/meson.build|   2 +-
 lib/librte_security/rte_security.h | 115 -
 2 files changed, 113 insertions(+), 4 deletions(-)

diff --git a/lib/librte_security/meson.build b/lib/librte_security/meson.build
index a5130d2f6d1e..10877d3ae544 100644
--- a/lib/librte_security/meson.build
+++ b/lib/librte_security/meson.build
@@ -4,4 +4,4 @@
 version = 2
 sources = files('rte_security.c')
 headers = files('rte_security.h', 'rte_security_driver.h')
-deps += ['mempool', 'cryptodev']
+deps += ['mempool', 'cryptodev', 'net']
diff --git a/lib/librte_security/rte_security.h 
b/lib/librte_security/rte_security.h
index 76f54e0e05bb..a3a9204fb62d 100644
--- a/lib/librte_security/rte_security.h
+++ b/lib/librte_security/rte_security.h
@@ -29,6 +29,7 @@ extern "C" {
 #include 
 #include 
 #include 
+#include 
 
 /** IPSec protocol mode */
 enum rte_security_ipsec_sa_mode {
@@ -197,12 +198,87 @@ struct rte_security_ipsec_xform {
/**< ESN for which the overflow event need to be raised */
 };
 
+/**
+ * MACSEC global configuration parameters
+ *
+ */
+struct rte_security_macsec_param {
+   uint8_t enabled;
+};
+
+/**
+ * MACSEC SC (Secure Connection) parameters
+ *
+ */
+struct rte_security_macsec_txsc_param {
+   struct ether_addr s_mac;
+   /**< local side mac address */
+   struct ether_addr d_mac;
+   /**< remote side mac address */
+   uint32_t sci;
+   uint32_t tci;
+   uint8_t encrypt;
+   uint8_t protect;
+};
+
+struct rte_security_macsec_rxsc_param {
+   struct ether_addr s_mac, d_mac;
+   /**< remote side mac address */
+   uint8_t replay_protection;
+   /**< replay protection */
+   uint32_t anti_replay_window;
+   /**< anti replay window */
+   uint16_t port_ident;
+   /**< remote side port identifier */
+   uint8_t 

[dpdk-dev] [RFC 2/5] app/testpmd: macsec on command draft via security context

[Igor Russkikh]

Here we create/get security mempool, get sec_ctx, and then
request session creation with macsec specific session configuration.

encrypt and replay_protection parameters are really not a global macsec
attributes, they are related to tx and rx security connection properties.

But we keep testpmd commands structure the same for now and will redesign
it in later commits.

Signed-off-by: Igor Russkikh 
---
 app/test-pmd/cmdline.c | 54 +++---
 1 file changed, 46 insertions(+), 8 deletions(-)

diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index c1042dd98214..dbee3d958c2e 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -46,6 +46,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -13991,6 +13992,12 @@ struct cmd_macsec_offload_on_result {
cmdline_fixed_string_t rp_on_off;
 };
 
+/* Temporary static storage until testpmd macsec commands get reformatted */
+int macsec_encrypt;
+int macsec_replay_protection;
+struct rte_security_session_conf macsec_conf;
+struct rte_security_session *macsec_session;
+
 /* Common CLI fields for MACsec offload disable */
 cmdline_parse_token_string_t cmd_macsec_offload_on_set =
TOKEN_STRING_INITIALIZER
@@ -14029,6 +14036,23 @@ cmdline_parse_token_string_t 
cmd_macsec_offload_on_rp_on_off =
(struct cmd_macsec_offload_on_result,
 rp_on_off, "on#off");
 
+static struct rte_mempool *get_security_pool()
+{
+   struct rte_mempool *pool = rte_mempool_lookup("testpmd_security_pool");
+   int session_size = 256;
+
+   if (!pool) {
+   pool = rte_mempool_create("testpmd_security_pool",
+   256,
+   session_size,
+   256,
+   0, NULL, NULL, NULL,
+   NULL, SOCKET_ID_ANY,
+   0);
+   }
+   return pool;
+}
+
 static void
 cmd_set_macsec_offload_on_parsed(
void *parsed_result,
@@ -14036,11 +14060,13 @@ cmd_set_macsec_offload_on_parsed(
__attribute__((unused)) void *data)
 {
struct cmd_macsec_offload_on_result *res = parsed_result;
-   int ret = -ENOTSUP;
+   int ret = 0;
+   struct rte_security_ctx *ctx;
portid_t port_id = res->port_id;
int en = (strcmp(res->en_on_off, "on") == 0) ? 1 : 0;
int rp = (strcmp(res->rp_on_off, "on") == 0) ? 1 : 0;
struct rte_eth_dev_info dev_info;
+   struct rte_security_session_conf macsec_conf;
 
if (port_id_is_invalid(port_id, ENABLED_WARN))
return;
@@ -14049,17 +14075,29 @@ cmd_set_macsec_offload_on_parsed(
return;
}
 
-   rte_eth_dev_info_get(port_id, &dev_info);
-   if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MACSEC_INSERT) {
-#ifdef RTE_LIBRTE_IXGBE_PMD
-   ret = rte_pmd_ixgbe_macsec_enable(port_id, en, rp);
-#endif
+   ctx = rte_eth_dev_get_sec_ctx(port_id);
+   if (!ctx) {
+   ret = ENOTSUP;
+   goto done;
+   }
+
+   macsec_conf.action_type = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL;
+   macsec_conf.protocol = RTE_SECURITY_PROTOCOL_MACSEC;
+   /** should be moved to SC properties */
+   macsec_encrypt = en;
+   macsec_replay_protection = rp;
+
+   /* Use of the same mempool for session header and private data */
+   macsec_session = rte_security_session_create(ctx, &macsec_conf, 
get_security_pool());
+
+   if (macsec_session == NULL) {
+   ret = -ENOTSUP;
}
-   RTE_SET_USED(en);
-   RTE_SET_USED(rp);
 
+done:
switch (ret) {
case 0:
+   /* TBD: To delete? */
ports[port_id].dev_conf.txmode.offloads |=
DEV_TX_OFFLOAD_MACSEC_INSERT;
cmd_reconfig_device_queue(port_id, 1, 1);
-- 
2.17.1

[dpdk-dev] [RFC 3/5] app/testpmd: macsec off command

[Igor Russkikh]

draft on how macsec off command will looks like

Signed-off-by: Igor Russkikh 
---
 app/test-pmd/cmdline.c | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index dbee3d958c2e..af7c2853fd2c 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -14173,6 +14173,8 @@ cmd_set_macsec_offload_off_parsed(
int ret = -ENOTSUP;
struct rte_eth_dev_info dev_info;
portid_t port_id = res->port_id;
+   struct rte_security_ctx *ctx;
+   struct rte_eth_dev_info dev_info;
 
if (port_id_is_invalid(port_id, ENABLED_WARN))
return;
@@ -14181,14 +14183,24 @@ cmd_set_macsec_offload_off_parsed(
return;
}
 
-   rte_eth_dev_info_get(port_id, &dev_info);
-   if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MACSEC_INSERT) {
-#ifdef RTE_LIBRTE_IXGBE_PMD
-   ret = rte_pmd_ixgbe_macsec_disable(port_id);
-#endif
+   if (!macsec_session) {
+   printf("MACsec is not active\n", port_id);
+   return;
+   }
+
+   ctx = rte_eth_dev_get_sec_ctx(port_id);
+   if (!ctx) {
+   ret = -ENOTSUP;
+   goto done;
}
+
+   /* Use of the same mempool for session header and private data */
+   ret = rte_security_session_destroy(ctx, macsec_session);
+
+done:
switch (ret) {
case 0:
+   /* TBD: Remove this offload bit? */
ports[port_id].dev_conf.txmode.offloads &=
~DEV_TX_OFFLOAD_MACSEC_INSERT;
cmd_reconfig_device_queue(port_id, 1, 1);
-- 
2.17.1

[dpdk-dev] [RFC 4/5] app/testpmd: macsec: update set sc command with new interface

[Igor Russkikh]

---
 app/test-pmd/cmdline.c | 40 
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/app/test-pmd/cmdline.c b/app/test-pmd/cmdline.c
index af7c2853fd2c..1bcf63e31ee3 100644
--- a/app/test-pmd/cmdline.c
+++ b/app/test-pmd/cmdline.c
@@ -14083,6 +14083,7 @@ cmd_set_macsec_offload_on_parsed(
 
macsec_conf.action_type = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL;
macsec_conf.protocol = RTE_SECURITY_PROTOCOL_MACSEC;
+   macsec_conf.macsec.
/** should be moved to SC properties */
macsec_encrypt = en;
macsec_replay_protection = rp;
@@ -14280,15 +14281,38 @@ cmd_set_macsec_sc_parsed(
struct cmd_macsec_sc_result *res = parsed_result;
int ret = -ENOTSUP;
int is_tx = (strcmp(res->tx_rx, "tx") == 0) ? 1 : 0;
+   struct rte_security_ctx *ctx;
+   struct rte_eth_dev_info dev_info;
+   struct rte_security_session_conf conf = {};
 
-#ifdef RTE_LIBRTE_IXGBE_PMD
-   ret = is_tx ?
-   rte_pmd_ixgbe_macsec_config_txsc(res->port_id,
-   res->mac.addr_bytes) :
-   rte_pmd_ixgbe_macsec_config_rxsc(res->port_id,
-   res->mac.addr_bytes, res->pi);
-#endif
-   RTE_SET_USED(is_tx);
+   ctx = rte_eth_dev_get_sec_ctx(port_id);
+   if (!ctx) {
+   ret = ENOTSUP;
+   goto done;
+   }
+
+   if (is_tx) {
+   conf.macsec.op = RTE_SECURITY_MACSEC_OP_ADD_TXSC;
+
+   rte_memcpy(&conf.macsec.txsc_options.s_mac, res->mac.addr_bytes,
+   sizeof(struct ether_addr));
+   conf.macsec.txsc_options.encrypt = macsec_encrypt;
+   conf.macsec.txsc_options.protect = 1;
+
+   ret = rte_security_session_update(ctx, macsec_session, &conf);
+   } else {
+   conf.macsec.op = RTE_SECURITY_MACSEC_OP_ADD_RXSC;
+
+   rte_memcpy(&conf.macsec.rxsc_options.s_mac, res->mac.addr_bytes,
+   sizeof(struct ether_addr));
+   /* Default */
+   conf.macsec.rxsc_options.anti_replay_window = 0;
+   conf.macsec.rxsc_options.replay_protection = 
macsec_replay_protection;
+   conf.macsec.rxsc_options.auto_rollover_enabled = true;
+
+   ret = rte_security_session_update(ctx, macsec_session, &conf);
+
+   }
 
switch (ret) {
case 0:
-- 
2.17.1

[dpdk-dev] [RFC 5/5] net/atlantic: macsec security context draft

[Igor Russkikh]

---
 drivers/net/atlantic/atl_ethdev.c | 116 ++
 drivers/net/atlantic/meson.build  |   1 +
 2 files changed, 117 insertions(+)

diff --git a/drivers/net/atlantic/atl_ethdev.c 
b/drivers/net/atlantic/atl_ethdev.c
index c9c1795a1639..b6fcf36f0f27 100644
--- a/drivers/net/atlantic/atl_ethdev.c
+++ b/drivers/net/atlantic/atl_ethdev.c
@@ -5,6 +5,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 #include "atl_ethdev.h"
 #include "atl_common.h"
@@ -122,6 +125,7 @@ static int eth_atl_pci_remove(struct rte_pci_device 
*pci_dev);
 
 static void atl_dev_info_get(struct rte_eth_dev *dev,
struct rte_eth_dev_info *dev_info);
+static int atl_macsec_ctx_create(struct rte_eth_dev *dev);
 
 int atl_logtype_init;
 int atl_logtype_driver;
@@ -412,6 +416,10 @@ eth_atl_dev_init(struct rte_eth_dev *eth_dev)
 
hw->aq_nic_cfg = &adapter->hw_cfg;
 
+   /* Initialize security_ctx only for primary process*/
+   if (atl_macsec_ctx_create(eth_dev))
+   return -ENOMEM;
+
/* disable interrupt */
atl_disable_intr(hw);
 
@@ -475,6 +483,8 @@ eth_atl_dev_uninit(struct rte_eth_dev *eth_dev)
rte_free(eth_dev->data->mac_addrs);
eth_dev->data->mac_addrs = NULL;
 
+   rte_free(eth_dev->security_ctx);
+
return 0;
 }
 
@@ -1872,6 +1882,112 @@ atl_rss_hash_conf_get(struct rte_eth_dev *dev,
return 0;
 }
 
+static const struct rte_security_capability *
+atl_crypto_capabilities_get(void *device __rte_unused)
+{
+   static const struct rte_cryptodev_capabilities
+   aes_gcm_gmac_crypto_capabilities[] = {
+   {   /* AES GMAC (128-bit) */
+   .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
+   {.sym = {
+   .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
+   {.auth = {
+   .algo = RTE_CRYPTO_AUTH_AES_GMAC,
+   .block_size = 16,
+   .key_size = {
+   .min = 16,
+   .max = 16,
+   .increment = 0
+   },
+   }, }
+   }, }
+   },
+   };
+
+   static const struct rte_security_capability
+   alt_security_capabilities[] = {
+   {
+   .action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,
+   .protocol = RTE_SECURITY_PROTOCOL_MACSEC,
+   {.macsec = {
+   /*
+   .proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,
+   .mode = RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT,
+   .options = { 0 }
+   */
+   } },
+   .crypto_capabilities = aes_gcm_gmac_crypto_capabilities,
+   .ol_flags = 0
+   },
+   {
+   .action = RTE_SECURITY_ACTION_TYPE_NONE
+   }
+   };
+
+   return alt_security_capabilities;
+}
+
+static int atl_macsec_create_session(void *device,
+   struct rte_security_session_conf *conf,
+   struct rte_security_session *sess,
+   struct rte_mempool *mp)
+{
+
+}
+
+static int atl_macsec_update_session(void *device,
+   struct rte_security_session *sess,
+   struct rte_security_session_conf *conf)
+{
+   
+}
+
+static unsigned int atl_macsec_session_get_size(void *device)
+{
+
+}
+
+static int atl_macsec_destroy_session(void *device,
+   struct rte_security_session *sess)
+{
+
+}
+
+static const struct rte_security_capability *atl_macsec_capabilities_get(
+   void *device)
+{
+
+}
+
+static struct rte_security_ops atl_security_ops = {
+   .session_create = atl_macsec_create_session,
+   .session_update = atl_macsec_update_session,
+   .session_get_size = atl_macsec_session_get_size,
+   .session_stats_get = NULL,
+   .session_destroy = atl_macsec_destroy_session,
+   .set_pkt_metadata = NULL,
+   .capabilities_get = atl_macsec_capabilities_get,
+};
+
+static int
+atl_macsec_ctx_create(struct rte_eth_dev *dev)
+{
+   struct rte_security_ctx *ctx = NULL;
+
+   ctx = rte_malloc("rte_security_instances_ops",
+   sizeof(struct rte_security_ctx), 0);
+   if (ctx) {
+   ctx->device = (void *)dev;
+   ctx->ops = &atl_security_ops;
+   ctx->sess_cnt = 0;
+   dev->security_ctx = ctx;
+   } else {
+   return -ENOMEM;
+   }
+   return 0;
+}
+
+
 static bool
 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
 {
diff --gi

[dpdk-dev] [PATCH] net/af_xdp: fix failure on rte_dev_remove

[William Tu]

When users call rte_eth_dev_close() and rte_dev_remove(), the af_xdp
pmd return -1 (EPERM) due to eth_dev == NULL.

Since the af_xdp pmd driver advertises RTE_ETH_DEV_CLOSE_REMOVE, all
the resources are freed on rte_eth_dev_close().  rte_dev_remove() tries
to detach device and subsequently calls rte_pmd_af_xdp_remove() that tries
to free already freed resources and fails. Fix it by return success.

Fixes: f1debd77efaf6 ("net/af_xdp: introduce AF_XDP PMD")
Reported-at: https://patchwork.ozlabs.org/patch/1106528/
Signed-off-by: William Tu 
Suggested-by: Ilya Maximets 
---
 drivers/net/af_xdp/rte_eth_af_xdp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/af_xdp/rte_eth_af_xdp.c 
b/drivers/net/af_xdp/rte_eth_af_xdp.c
index 35c72272c919..3dcc3628c5d0 100644
--- a/drivers/net/af_xdp/rte_eth_af_xdp.c
+++ b/drivers/net/af_xdp/rte_eth_af_xdp.c
@@ -944,7 +944,7 @@ rte_pmd_af_xdp_remove(struct rte_vdev_device *dev)
/* find the ethdev entry */
eth_dev = rte_eth_dev_allocated(rte_vdev_device_name(dev));
if (eth_dev == NULL)
-   return -1;
+   return 0;
 
eth_dev_close(eth_dev);
rte_eth_dev_release_port(eth_dev);
-- 
2.7.4

[dpdk-dev] [PATCH] net/i40e: add flow mark support to sse path

[Harry van Haaren]

This commit enables the "FD ID" or flow-director mark
capability with the SSE vector PMD for 32 byte descriptors.

Suggested-by: Mesut Ergin 
Signed-off-by: Harry van Haaren 

---

Hey Folks,

This v1 is expected to have some performance impact due to adding stores
to the data path. These can be reduced by blending the data into the register
which is later stored - however this would require larger code changes, and
be more difficult to review. As a v1 patch, this achieves the same goal.

Please review the concept, and I'll rework the implementation to be more
performant for the v2 by adding the required blending for ol_flags.

Cheers, -Harry

---

 drivers/net/i40e/i40e_rxtx.c |  6 -
 drivers/net/i40e/i40e_rxtx.h |  7 ++
 drivers/net/i40e/i40e_rxtx_vec_sse.c | 37 
 3 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c
index 7618153e2..6190ddd07 100644
--- a/drivers/net/i40e/i40e_rxtx.c
+++ b/drivers/net/i40e/i40e_rxtx.c
@@ -172,12 +172,6 @@ i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t 
qword)
 }
 #endif
 
-#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
-#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
-#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
-#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
-#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
-
 static inline uint64_t
 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 {
diff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h
index 3fc619af9..23de35e42 100644
--- a/drivers/net/i40e/i40e_rxtx.h
+++ b/drivers/net/i40e/i40e_rxtx.h
@@ -32,6 +32,13 @@
 
 #define I40E_TX_MIN_PKT_LEN 17
 
+/* Shared FDIR masks between scalar / vector drivers */
+#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
+#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
+#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
+#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
+#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
+
 #undef container_of
 #define container_of(ptr, type, member) ({ \
typeof(((type *)0)->member)(*__mptr) = (ptr); \
diff --git a/drivers/net/i40e/i40e_rxtx_vec_sse.c 
b/drivers/net/i40e/i40e_rxtx_vec_sse.c
index 3b22588c5..180d00b79 100644
--- a/drivers/net/i40e/i40e_rxtx_vec_sse.c
+++ b/drivers/net/i40e/i40e_rxtx_vec_sse.c
@@ -206,6 +206,31 @@ desc_to_ptype_v(__m128i descs[4], struct rte_mbuf 
**rx_pkts,
rx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 8)];
 }
 
+/* Reads the FDIR ID flags from the 32B descriptors' extended status,
+ * and if FDIR_ID mark is set, pushes the data to the mbuf->hash.fdir.hi.
+ */
+static inline void
+desc_to_fdir_mark(__m128i v_desc_qw23, struct rte_mbuf *rx_pkt)
+{
+   /* Extract the extended status */
+   uint32_t ext_sts = _mm_extract_epi16(v_desc_qw23, 0);
+   uint32_t fdir_data = rte_le_to_cpu_32(
+   _mm_extract_epi32(v_desc_qw23, 3));
+
+   /* Check for FD ID mark valid */
+   uint32_t flexbh = (rte_le_to_cpu_32(ext_sts) >>
+   I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
+   I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
+
+   /* Branch-free generation of mask for data */
+   uint32_t fd_id_valid = (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID);
+   uint64_t use_data_mask = (!fd_id_valid) - 1;
+
+   /* Always store, mask will zero out if not valid */
+   rx_pkt->hash.fdir.hi = (use_data_mask & fdir_data);
+   rx_pkt->ol_flags |= (PKT_RX_FDIR_ID & use_data_mask);
+}
+
  /*
  * Notice:
  * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
@@ -441,6 +466,18 @@ _recv_raw_pkts_vec(struct i40e_rx_queue *rxq, struct 
rte_mbuf **rx_pkts,
_mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 pkt_mb1);
desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
+
+   /* Extract FDIR ID from 2nd half of descriptor, update mbuf */
+   __m128i descs_qw23;
+   descs_qw23 = _mm_loadu_si128((__m128i*)&(rxdp + 0)->wb.qword2);
+   desc_to_fdir_mark(descs_qw23, rx_pkts[pos + 0]);
+   descs_qw23 = _mm_loadu_si128((__m128i*)&(rxdp + 1)->wb.qword2);
+   desc_to_fdir_mark(descs_qw23, rx_pkts[pos + 1]);
+   descs_qw23 = _mm_loadu_si128((__m128i*)&(rxdp + 2)->wb.qword2);
+   desc_to_fdir_mark(descs_qw23, rx_pkts[pos + 2]);
+   descs_qw23 = _mm_loadu_si128((__m128i*)&(rxdp + 3)->wb.qword2);
+   desc_to_fdir_mark(descs_qw23, rx_pkts[pos + 3]);
+
/* C.4 calc avaialbe number of desc */
var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
nb_pkts_recd += var;
-- 
2.17.1

[dpdk-dev] [PATCH] test/hash: rectify slaveid to point to valid cores

[Dharmik Thakkar]

This patch rectifies slave_id passed to rte_eal_wait_lcore()
to point to valid cores in read-write lock-free concurrency test.

It also replaces a 'for' loop with RTE_LCORE_FOREACH API.

Fixes: dfd9d5537e876 ("test/hash: use existing lcore API")
Cc: sta...@dpdk.org

Signed-off-by: Dharmik Thakkar 
Reviewed-by: Ruifeng Wang 
---
 app/test/test_hash_readwrite_lf.c | 24 +++-
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/app/test/test_hash_readwrite_lf.c 
b/app/test/test_hash_readwrite_lf.c
index 343a338b4ea8..af1ee9c34394 100644
--- a/app/test/test_hash_readwrite_lf.c
+++ b/app/test/test_hash_readwrite_lf.c
@@ -126,11 +126,9 @@ get_enabled_cores_list(void)
uint32_t i = 0;
uint16_t core_id;
uint32_t max_cores = rte_lcore_count();
-   for (core_id = 0; core_id < RTE_MAX_LCORE && i < max_cores; core_id++) {
-   if (rte_lcore_is_enabled(core_id)) {
-   enabled_core_ids[i] = core_id;
-   i++;
-   }
+   RTE_LCORE_FOREACH(core_id) {
+   enabled_core_ids[i] = core_id;
+   i++;
}
 
if (i != max_cores) {
@@ -738,7 +736,7 @@ test_hash_add_no_ks_lookup_hit(struct rwc_perf 
*rwc_perf_results, int rwc_lf,
enabled_core_ids[i]);
 
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -810,7 +808,7 @@ test_hash_add_no_ks_lookup_miss(struct rwc_perf 
*rwc_perf_results, int rwc_lf,
if (ret < 0)
goto err;
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -886,7 +884,7 @@ test_hash_add_ks_lookup_hit_non_sp(struct rwc_perf 
*rwc_perf_results,
if (ret < 0)
goto err;
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -962,7 +960,7 @@ test_hash_add_ks_lookup_hit_sp(struct rwc_perf 
*rwc_perf_results, int rwc_lf,
if (ret < 0)
goto err;
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -1037,7 +1035,7 @@ test_hash_add_ks_lookup_miss(struct rwc_perf 
*rwc_perf_results, int rwc_lf, int
if (ret < 0)
goto err;
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -1132,12 +1130,12 @@ test_hash_multi_add_lookup(struct rwc_perf 
*rwc_perf_results, int rwc_lf,
for (i = rwc_core_cnt[n] + 1;
 i <= rwc_core_cnt[m] + rwc_core_cnt[n];
 i++)
-   rte_eal_wait_lcore(i);
+   rte_eal_wait_lcore(enabled_core_ids[i]);
 
writer_done = 1;
 
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if 
(rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
@@ -1221,7 +1219,7 @@ test_hash_add_ks_lookup_hit_extbkt(struct rwc_perf 
*rwc_perf_results,
writer_done = 1;
 
for (i = 1; i <= rwc_core_cnt[n]; i++)
-   if (rte_eal_wait_lcore(i) < 0)
+   if (rte_eal_wait_lcore(enabled_core_ids[i]) < 0)
goto err;
 
unsigned long long cycles_per_lookup =
-- 
2.17.1

[dpdk-dev] [PATCH v2 00/27] OCTEON TX2 common and mempool driver

[jerinj]

From: Jerin Jacob 

This patch set adds initial driver support for OCTEON TX2 SoC.

OCTEON TX2 is an armv8.2 SoC with integrated HW based mempool, ethdev,
cryptodev, compressdev, and eventdev devices.

This patch set adds common driver and mempool device driver for OCTEON TX2 SoC.
There will be three more patch series in this release
to support ethdev, eventdev and cryptodev devices

More details about the OCTEON TX2 platform may found in
[PATCH 15/27] doc: add Marvell OCTEON TX2 platform guide
under doc/guides/platform/octeontx2.rst file.

This patches series also available at https://github.com/jerinjacobk/dpdk.git
for quick download and review.

# Note on check patch issues
1) The mailbox prototype is the same as Linux kernel.
https://elixir.bootlin.com/linux/latest/source/drivers/net/ethernet/marvell/octeontx2/af/mbox.h#L123
In order to keep the base code intact, mailbox prototype expressed as
macros with warnings
2) There are a few warnings from tooling about expected to add new
symbols in the EXPERIMENTAL
section. Since these API will be called only by octeontx2 client drivers
and prototype are not exported to the application, those warnings are
not relevant, Discussion at http://patches.dpdk.org/patch/53590/

v2:

1) Added CONFIG_RTE_MAX_VFIO_GROUPS for octeontx2 config in patch 1
2) Rebased to master to accommodate latest rename like ETHER_ADDR_LEN to 
RTE_ETHER_ADDR_LEN
3) Added pmd.raw.octeontx2.dpi log message in patch 5
4) Update platform guide with debugfs documentation in patch 15
5) Fix arm64 build issue with patch 25(Aaron Conole)
"mempool/octeontx2: add optimized dequeue operation for arm64"

Jerin Jacob (22):
  common/octeontx2: add build infrastructure and HW definition
  common/octeontx2: add IO handling APIs
  common/octeontx2: add mbox request and response definition
  common/octeontx2: add mailbox base support infra
  common/octeontx2: add runtime log infra
  common/octeontx2: add mailbox send and receive support
  common/octeontx2: introduce common device class
  common/octeontx2: introduce irq handling functions
  common/octeontx2: handle intra device operations
  common/octeontx2: add VF mailbox IRQ and msg handler
  doc: add Marvell OCTEON TX2 platform guide
  mempool/octeontx2: add build infra and device probe
  drivers: add init and fini on octeontx2 NPA object
  mempool/octeontx2: add NPA HW operations
  mempool/octeontx2: add NPA IRQ handler
  mempool/octeontx2: add context dump support
  mempool/octeontx2: add mempool alloc op
  mempool/octeontx2: add mempool free op
  mempool/octeontx2: add remaining slow path ops
  mempool/octeontx2: add fast path mempool ops
  mempool/octeontx2: add devargs for max pool selection
  doc: add Marvell OCTEON TX2 mempool documentation

Nithin Dabilpuram (4):
  common/octeontx2: add AF to PF mailbox IRQ and msg handlers
  common/octeontx2: add PF to VF mailbox IRQ and msg handlers
  common/octeontx2: add uplink message support
  common/octeontx2: add FLR IRQ handler

Pavan Nikhilesh (1):
  mempool/octeontx2: add optimized dequeue operation for arm64

 MAINTAINERS   |   10 +
 config/common_base|5 +
 config/defconfig_arm64-octeontx2-linuxapp-gcc |3 +
 doc/guides/mempool/index.rst  |1 +
 doc/guides/mempool/octeontx2.rst  |   90 +
 .../octeontx2_packet_flow_hw_accelerators.svg | 2804 +
 .../img/octeontx2_resource_virtualization.svg | 2418 ++
 doc/guides/platform/index.rst |1 +
 doc/guides/platform/octeontx2.rst |  496 +++
 doc/guides/rel_notes/release_19_08.rst|2 +
 drivers/common/Makefile   |5 +
 drivers/common/meson.build|2 +-
 drivers/common/octeontx2/Makefile |   37 +
 drivers/common/octeontx2/hw/otx2_nix.h| 1376 
 drivers/common/octeontx2/hw/otx2_npa.h|  305 ++
 drivers/common/octeontx2/hw/otx2_npc.h|  467 +++
 drivers/common/octeontx2/hw/otx2_rvu.h|  212 ++
 drivers/common/octeontx2/hw/otx2_sso.h|  209 ++
 drivers/common/octeontx2/hw/otx2_ssow.h   |   56 +
 drivers/common/octeontx2/hw/otx2_tim.h|   34 +
 drivers/common/octeontx2/meson.build  |   25 +
 drivers/common/octeontx2/otx2_common.c|  248 ++
 drivers/common/octeontx2/otx2_common.h|  121 +
 drivers/common/octeontx2/otx2_dev.c   | 1052 +++
 drivers/common/octeontx2/otx2_dev.h   |   97 +
 drivers/common/octeontx2/otx2_io_arm64.h  |   95 +
 drivers/common/octeontx2/otx2_io_generic.h|   63 +
 drivers/common/octeontx2/otx2_irq.c   |  254 ++
 drivers/common/octeontx2/otx2_irq.h   |   25 +
 drivers/common/octeontx2/otx2_mbox.c  |  416 +++
 drivers/common/octeontx2/otx2_mbox.h  | 1483 +
 .../rte_common_octeontx2_version.map  |   39 +
 drivers/mempool/Makefile  |1 +
 drivers/mempool/mes

[dpdk-dev] [PATCH v2 01/27] common/octeontx2: add build infrastructure and HW definition

[jerinj]

From: Jerin Jacob 

Add the make and meson based build infrastructure along with
HW definition header file.

This patch adds skeleton otx2_mbox.c file to make sure
all header files are intact, subsequent patches add content
to otx2_mbox.c

This patch also updates CONFIG_RTE_MAX_VFIO_GROUPS
value to 128 as the system can have up to 128 PFs/VFs.
For octeontx2 meson build target, CONFIG_RTE_MAX_VFIO_GROUPS
defined as 128 so no additional changes required.

Signed-off-by: Jerin Jacob 
Signed-off-by: Pavan Nikhilesh 
---
 config/defconfig_arm64-octeontx2-linuxapp-gcc |3 +
 drivers/common/Makefile   |2 +
 drivers/common/meson.build|2 +-
 drivers/common/octeontx2/Makefile |   32 +
 drivers/common/octeontx2/hw/otx2_nix.h| 1376 +
 drivers/common/octeontx2/hw/otx2_npa.h|  305 
 drivers/common/octeontx2/hw/otx2_npc.h|  467 ++
 drivers/common/octeontx2/hw/otx2_rvu.h|  212 +++
 drivers/common/octeontx2/hw/otx2_sso.h|  209 +++
 drivers/common/octeontx2/hw/otx2_ssow.h   |   56 +
 drivers/common/octeontx2/hw/otx2_tim.h|   34 +
 drivers/common/octeontx2/meson.build  |   23 +
 drivers/common/octeontx2/otx2_common.h|   34 +
 drivers/common/octeontx2/otx2_mbox.c  |5 +
 drivers/common/octeontx2/otx2_mbox.h  |   10 +
 .../rte_common_octeontx2_version.map  |4 +
 mk/rte.app.mk |2 +
 17 files changed, 2775 insertions(+), 1 deletion(-)
 create mode 100644 drivers/common/octeontx2/Makefile
 create mode 100644 drivers/common/octeontx2/hw/otx2_nix.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_npa.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_npc.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_rvu.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_sso.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_ssow.h
 create mode 100644 drivers/common/octeontx2/hw/otx2_tim.h
 create mode 100644 drivers/common/octeontx2/meson.build
 create mode 100644 drivers/common/octeontx2/otx2_common.h
 create mode 100644 drivers/common/octeontx2/otx2_mbox.c
 create mode 100644 drivers/common/octeontx2/otx2_mbox.h
 create mode 100644 drivers/common/octeontx2/rte_common_octeontx2_version.map

diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc 
b/config/defconfig_arm64-octeontx2-linuxapp-gcc
index 9eae84538..f20da2442 100644
--- a/config/defconfig_arm64-octeontx2-linuxapp-gcc
+++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
@@ -16,3 +16,6 @@ CONFIG_RTE_LIBRTE_VHOST_NUMA=n
 
 # Recommend to use VFIO as co-processors needs SMMU/IOMMU
 CONFIG_RTE_EAL_IGB_UIO=n
+
+# Max supported NIX LFs
+CONFIG_RTE_MAX_VFIO_GROUPS=128
diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index 87b8a59a4..e7abe210e 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -23,4 +23,6 @@ ifeq ($(CONFIG_RTE_LIBRTE_COMMON_DPAAX),y)
 DIRS-y += dpaax
 endif
 
+DIRS-y += octeontx2
+
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/common/meson.build b/drivers/common/meson.build
index a50934108..7b5e566f3 100644
--- a/drivers/common/meson.build
+++ b/drivers/common/meson.build
@@ -2,6 +2,6 @@
 # Copyright(c) 2018 Cavium, Inc
 
 std_deps = ['eal']
-drivers = ['cpt', 'dpaax', 'mvep', 'octeontx', 'qat']
+drivers = ['cpt', 'dpaax', 'mvep', 'octeontx', 'octeontx2', 'qat']
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 driver_name_fmt = 'rte_common_@0@'
diff --git a/drivers/common/octeontx2/Makefile 
b/drivers/common/octeontx2/Makefile
new file mode 100644
index 0..e5737532a
--- /dev/null
+++ b/drivers/common/octeontx2/Makefile
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_common_octeontx2.a
+
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+
+ifneq ($(CONFIG_RTE_ARCH_64),y)
+CFLAGS += -Wno-int-to-pointer-cast
+CFLAGS += -Wno-pointer-to-int-cast
+endif
+
+EXPORT_MAP := rte_common_octeontx2_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-y += otx2_mbox.c
+
+LDLIBS += -lrte_eal
+LDLIBS += -lrte_ethdev
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/common/octeontx2/hw/otx2_nix.h 
b/drivers/common/octeontx2/hw/otx2_nix.h
new file mode 100644
index 0..e7d32a6b3
--- /dev/null
+++ b/drivers/common/octeontx2/hw/otx2_nix.h
@@ -0,0 +1,1376 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef __OTX2_NIX_HW_H__
+#define __OTX2_NIX_HW_H__
+
+/* Register offsets */
+
+#define NIX_AF_CFG  (0x0ull)
+#define NIX_AF_STATUS   (0x10ull)
+#define NIX_AF_NDC_CFG  (0x18ull)
+#define NIX_AF_CONST(0x20ull)
+#define NIX_AF_CONST1

[dpdk-dev] [PATCH v2 03/27] common/octeontx2: add mbox request and response definition

[jerinj]

From: Jerin Jacob 

The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.

This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.

Signed-off-by: Jerin Jacob 
Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Pavan Nikhilesh 
Signed-off-by: Kiran Kumar K 
Signed-off-by: Vamsi Attunuru 
Signed-off-by: Vivek Sharma 
Signed-off-by: Harman Kalra 
Signed-off-by: Sunil Kumar Kori 
Signed-off-by: Krzysztof Kanas 
Signed-off-by: Zyta Szpak 
---
 drivers/common/octeontx2/otx2_mbox.h | 1326 ++
 1 file changed, 1326 insertions(+)

diff --git a/drivers/common/octeontx2/otx2_mbox.h 
b/drivers/common/octeontx2/otx2_mbox.h
index 6d7b77ed9..e2d79c070 100644
--- a/drivers/common/octeontx2/otx2_mbox.h
+++ b/drivers/common/octeontx2/otx2_mbox.h
@@ -5,6 +5,1332 @@
 #ifndef __OTX2_MBOX_H__
 #define __OTX2_MBOX_H__
 
+#include 
+#include 
+
+#include 
+#include 
+
 #include 
 
+#define SZ_64K (64 * 1024)
+#define SZ_1K  (1 * 1024)
+#define MBOX_SIZE  SZ_64K
+
+/* AF/PF: PF initiated, PF/VF VF initiated */
+#define MBOX_DOWN_RX_START 0
+#define MBOX_DOWN_RX_SIZE  (46 * SZ_1K)
+#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
+#define MBOX_DOWN_TX_SIZE  (16 * SZ_1K)
+/* AF/PF: AF initiated, PF/VF PF initiated */
+#define MBOX_UP_RX_START   (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
+#define MBOX_UP_RX_SIZESZ_1K
+#define MBOX_UP_TX_START   (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
+#define MBOX_UP_TX_SIZESZ_1K
+
+#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
+# error "Incorrect mailbox area sizes"
+#endif
+
+#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
+
+#define MBOX_RSP_TIMEOUT   3000 /* Time to wait for mbox response in ms */
+
+#define MBOX_MSG_ALIGN 16  /* Align mbox msg start to 16bytes */
+
+/* Mailbox directions */
+#define MBOX_DIR_AFPF  0  /* AF replies to PF */
+#define MBOX_DIR_PFAF  1  /* PF sends messages to AF */
+#define MBOX_DIR_PFVF  2  /* PF replies to VF */
+#define MBOX_DIR_VFPF  3  /* VF sends messages to PF */
+#define MBOX_DIR_AFPF_UP   4  /* AF sends messages to PF */
+#define MBOX_DIR_PFAF_UP   5  /* PF replies to AF */
+#define MBOX_DIR_PFVF_UP   6  /* PF sends messages to VF */
+#define MBOX_DIR_VFPF_UP   7  /* VF replies to PF */
+
+/* Device memory does not support unaligned access, instruct compiler to
+ * not optimize the memory access when working with mailbox memory.
+ */
+#define __otx2_io volatile
+
+struct otx2_mbox_dev {
+   void*mbase;   /* This dev's mbox region */
+   rte_spinlock_t  mbox_lock;
+   uint16_t msg_size; /* Total msg size to be sent */
+   uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
+   uint16_t num_msgs; /* No of msgs sent or waiting for response */
+   uint16_t msgs_acked; /* No of msgs for which response is received */
+};
+
+struct otx2_mbox {
+   uintptr_t hwbase;  /* Mbox region advertised by HW */
+   uintptr_t reg_base;/* CSR base for this dev */
+   uint64_t trigger;  /* Trigger mbox notification */
+   uint16_t tr_shift; /* Mbox trigger shift */
+   uint64_t rx_start; /* Offset of Rx region in mbox memory */
+   uint64_t tx_start; /* Offset of Tx region in mbox memory */
+   uint16_t rx_size;  /* Size of Rx region */
+   uint16_t tx_size;  /* Size of Tx region */
+   uint16_t ndevs;/* The number of peers */
+   struct otx2_mbox_dev *dev;
+};
+
+/* Header which precedes all mbox messages */
+struct mbox_hdr {
+   uint64_t __otx2_io msg_size;   /* Total msgs size embedded */
+   uint16_t __otx2_io num_msgs;   /* No of msgs embedded */
+};
+
+/* Header which precedes every msg and is also part of it */
+struct mbox_msghdr {
+   uint16_t __otx2_io pcifunc; /* Who's sending this msg */
+   uint16_t __otx2_io id;  /* Mbox message ID */
+#define OTX2_MBOX_REQ_SIG (0xdead)
+#define OTX2_MBOX_RSP_SIG (0xbeef)
+   /* Signature, for validating corrupted msgs */
+   uint16_t __otx2_io sig;
+#define OTX2_MBOX_VERSION (0x0001)
+   /* Version of msg's structure for this ID */
+   uint16_t __otx2_io ver;
+   /* Offset of next msg within mailbox region */
+   uint16_t __otx2_io next_msgoff;
+   int __otx2_io rc; /* Msg processed response code */
+};
+
+/* Mailbox message types */
+#define MBOX_MSG_MASK  0x
+#define MBOX_MSG_INVALID   0xFFFE
+#define MBOX_MSG_MAX   0x
+
+#define MBOX_MESSAGES  \
+/* Generic mbox IDs (range 0x000 - 0x1FF) */   \
+M(READY,  

[dpdk-dev] [PATCH v2 04/27] common/octeontx2: add mailbox base support infra

[jerinj]

From: Jerin Jacob 

This patch adds mailbox init and fini support.
Each RVU device has a dedicated 64KB mailbox region
shared with its peer for communication. RVU AF has
a separate mailbox region shared with each of RVU PFs
and an RVU PF has a separate region shared with
each of it's VF.

Signed-off-by: Jerin Jacob 
Signed-off-by: Vamsi Attunuru 
Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/octeontx2/otx2_mbox.c | 133 +++
 drivers/common/octeontx2/otx2_mbox.h |   5 +
 2 files changed, 138 insertions(+)

diff --git a/drivers/common/octeontx2/otx2_mbox.c 
b/drivers/common/octeontx2/otx2_mbox.c
index c9cdbdbbc..cb03f6503 100644
--- a/drivers/common/octeontx2/otx2_mbox.c
+++ b/drivers/common/octeontx2/otx2_mbox.c
@@ -2,4 +2,137 @@
  * Copyright(C) 2019 Marvell International Ltd.
  */
 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
 #include "otx2_mbox.h"
+
+#define RVU_AF_AFPF_MBOX0  (0x02000)
+#define RVU_AF_AFPF_MBOX1  (0x02008)
+
+#define RVU_PF_PFAF_MBOX0  (0xC00)
+#define RVU_PF_PFAF_MBOX1  (0xC08)
+
+#define RVU_PF_VFX_PFVF_MBOX0  (0x)
+#define RVU_PF_VFX_PFVF_MBOX1  (0x0008)
+
+#defineRVU_VF_VFPF_MBOX0   (0x)
+#defineRVU_VF_VFPF_MBOX1   (0x0008)
+
+void
+otx2_mbox_fini(struct otx2_mbox *mbox)
+{
+   mbox->reg_base = 0;
+   mbox->hwbase = 0;
+   free(mbox->dev);
+   mbox->dev = NULL;
+}
+
+void
+otx2_mbox_reset(struct otx2_mbox *mbox, int devid)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[devid];
+   struct mbox_hdr *tx_hdr =
+   (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);
+   struct mbox_hdr *rx_hdr =
+   (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+
+   rte_spinlock_lock(&mdev->mbox_lock);
+   mdev->msg_size = 0;
+   mdev->rsp_size = 0;
+   tx_hdr->msg_size = 0;
+   tx_hdr->num_msgs = 0;
+   rx_hdr->msg_size = 0;
+   rx_hdr->num_msgs = 0;
+   rte_spinlock_unlock(&mdev->mbox_lock);
+}
+
+int
+otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,
+  uintptr_t reg_base, int direction, int ndevs)
+{
+   struct otx2_mbox_dev *mdev;
+   int devid;
+
+   mbox->reg_base = reg_base;
+   mbox->hwbase = hwbase;
+
+   switch (direction) {
+   case MBOX_DIR_AFPF:
+   case MBOX_DIR_PFVF:
+   mbox->tx_start = MBOX_DOWN_TX_START;
+   mbox->rx_start = MBOX_DOWN_RX_START;
+   mbox->tx_size  = MBOX_DOWN_TX_SIZE;
+   mbox->rx_size  = MBOX_DOWN_RX_SIZE;
+   break;
+   case MBOX_DIR_PFAF:
+   case MBOX_DIR_VFPF:
+   mbox->tx_start = MBOX_DOWN_RX_START;
+   mbox->rx_start = MBOX_DOWN_TX_START;
+   mbox->tx_size  = MBOX_DOWN_RX_SIZE;
+   mbox->rx_size  = MBOX_DOWN_TX_SIZE;
+   break;
+   case MBOX_DIR_AFPF_UP:
+   case MBOX_DIR_PFVF_UP:
+   mbox->tx_start = MBOX_UP_TX_START;
+   mbox->rx_start = MBOX_UP_RX_START;
+   mbox->tx_size  = MBOX_UP_TX_SIZE;
+   mbox->rx_size  = MBOX_UP_RX_SIZE;
+   break;
+   case MBOX_DIR_PFAF_UP:
+   case MBOX_DIR_VFPF_UP:
+   mbox->tx_start = MBOX_UP_RX_START;
+   mbox->rx_start = MBOX_UP_TX_START;
+   mbox->tx_size  = MBOX_UP_RX_SIZE;
+   mbox->rx_size  = MBOX_UP_TX_SIZE;
+   break;
+   default:
+   return -ENODEV;
+   }
+
+   switch (direction) {
+   case MBOX_DIR_AFPF:
+   case MBOX_DIR_AFPF_UP:
+   mbox->trigger = RVU_AF_AFPF_MBOX0;
+   mbox->tr_shift = 4;
+   break;
+   case MBOX_DIR_PFAF:
+   case MBOX_DIR_PFAF_UP:
+   mbox->trigger = RVU_PF_PFAF_MBOX1;
+   mbox->tr_shift = 0;
+   break;
+   case MBOX_DIR_PFVF:
+   case MBOX_DIR_PFVF_UP:
+   mbox->trigger = RVU_PF_VFX_PFVF_MBOX0;
+   mbox->tr_shift = 12;
+   break;
+   case MBOX_DIR_VFPF:
+   case MBOX_DIR_VFPF_UP:
+   mbox->trigger = RVU_VF_VFPF_MBOX1;
+   mbox->tr_shift = 0;
+   break;
+   default:
+   return -ENODEV;
+   }
+
+   mbox->dev = malloc(ndevs * sizeof(struct otx2_mbox_dev));
+   if (!mbox->dev) {
+   otx2_mbox_fini(mbox);
+   return -ENOMEM;
+   }
+   mbox->ndevs = ndevs;
+   for (devid = 0; devid < ndevs; devid++) {
+   mdev = &mbox->dev[devid];
+   mdev->mbase = (void *)(mbox->hwbase + (devid * MBOX_SIZE));
+   rte_spinlock_init(&mdev->mbox_lock);
+   /* Init header to reset value */
+   otx2_mbox_reset(mbox, devid);
+   }
+
+   return 0;
+}
diff --git a/drivers/common/octeontx2/otx2_mbox.h 
b/drivers/common/octeontx2/otx2_mbox.h
index e2d79c070..ac7de788f 100644
--- a/drive

[dpdk-dev] [PATCH v2 02/27] common/octeontx2: add IO handling APIs

[jerinj]

From: Jerin Jacob 

Various octeontx2 drivers use IO handling API, added octeontx2
specific IO handling routines in the common code.

Since some of those implementations are based on arm64 instructions
added the stub to compile the code on non arm64 ISA.
The non arm64 ISA stub is possible due to the fact that
it is an integrated controller i.e runs only on Marvell HW.

Signed-off-by: Jerin Jacob 
Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Pavan Nikhilesh 
---
 drivers/common/octeontx2/otx2_common.h | 12 +++
 drivers/common/octeontx2/otx2_io_arm64.h   | 95 ++
 drivers/common/octeontx2/otx2_io_generic.h | 63 ++
 3 files changed, 170 insertions(+)
 create mode 100644 drivers/common/octeontx2/otx2_io_arm64.h
 create mode 100644 drivers/common/octeontx2/otx2_io_generic.h

diff --git a/drivers/common/octeontx2/otx2_common.h 
b/drivers/common/octeontx2/otx2_common.h
index b4e008b14..b0c19266b 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -6,6 +6,8 @@
 #define _OTX2_COMMON_H_
 
 #include 
+#include 
+#include 
 
 #include "hw/otx2_rvu.h"
 #include "hw/otx2_nix.h"
@@ -31,4 +33,14 @@
 #define __hot   __attribute__((hot))
 #endif
 
+/* IO Access */
+#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
+#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
+
+#if defined(RTE_ARCH_ARM64)
+#include "otx2_io_arm64.h"
+#else
+#include "otx2_io_generic.h"
+#endif
+
 #endif /* _OTX2_COMMON_H_ */
diff --git a/drivers/common/octeontx2/otx2_io_arm64.h 
b/drivers/common/octeontx2/otx2_io_arm64.h
new file mode 100644
index 0..468243c04
--- /dev/null
+++ b/drivers/common/octeontx2/otx2_io_arm64.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_IO_ARM64_H_
+#define _OTX2_IO_ARM64_H_
+
+#define otx2_load_pair(val0, val1, addr) ({\
+   asm volatile(   \
+   "ldp %x[x0], %x[x1], [%x[p1]]"  \
+   :[x0]"=r"(val0), [x1]"=r"(val1) \
+   :[p1]"r"(addr)  \
+   ); })
+
+#define otx2_store_pair(val0, val1, addr) ({   \
+   asm volatile(   \
+   "stp %x[x0], %x[x1], [%x[p1]]"  \
+   ::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr)   \
+   ); })
+
+#define otx2_prefetch_store_keep(ptr) ({\
+   asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (ptr)); })
+
+static __rte_always_inline uint64_t
+otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)
+{
+   uint64_t result;
+
+   /* Atomic add with no ordering */
+   asm volatile (
+   ".cpu  generic+lse\n"
+   "ldadd %x[i], %x[r], [%[b]]"
+   : [r] "=r" (result), "+m" (*ptr)
+   : [i] "r" (incr), [b] "r" (ptr)
+   : "memory");
+   return result;
+}
+
+static __rte_always_inline uint64_t
+otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)
+{
+   uint64_t result;
+
+   /* Atomic add with ordering */
+   asm volatile (
+   ".cpu  generic+lse\n"
+   "ldadda %x[i], %x[r], [%[b]]"
+   : [r] "=r" (result), "+m" (*ptr)
+   : [i] "r" (incr), [b] "r" (ptr)
+   : "memory");
+   return result;
+}
+
+static __rte_always_inline uint64_t
+otx2_lmt_submit(rte_iova_t io_address)
+{
+   uint64_t result;
+
+   asm volatile (
+   ".cpu  generic+lse\n"
+   "ldeor xzr,%x[rf],[%[rs]]" :
+[rf] "=r"(result): [rs] "r"(io_address));
+   return result;
+}
+
+static __rte_always_inline void
+otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)
+{
+   volatile const __uint128_t *src128 = (const __uint128_t *)in;
+   volatile __uint128_t *dst128 = (__uint128_t *)out;
+   dst128[0] = src128[0];
+   dst128[1] = src128[1];
+   /* lmtext receives following value:
+* 1: NIX_SUBDC_EXT needed i.e. tx vlan case
+* 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case
+*/
+   if (lmtext) {
+   dst128[2] = src128[2];
+   if (lmtext > 1)
+   dst128[3] = src128[3];
+   }
+}
+
+static __rte_always_inline void
+otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)
+{
+   volatile const __uint128_t *src128 = (const __uint128_t *)in;
+   volatile __uint128_t *dst128 = (__uint128_t *)out;
+   uint8_t i;
+
+   for (i = 0; i < segdw; i++)
+   dst128[i] = src128[i];
+}
+
+#endif /* _OTX2_IO_ARM64_H_ */
diff --git a/drivers/common/octeontx2/otx2_io_generic.h 
b/drivers/common/octeontx2/otx2_io_generic.h
new file mode 100644
index 0..b1d754008
--- /dev/null
+++ b/drivers/common/octeontx2/otx2_io_generic.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell Inter

[dpdk-dev] [PATCH v2 05/27] common/octeontx2: add runtime log infra

[jerinj]

From: Jerin Jacob 

Various consumers of this common code need runtime
logging infrastructure. This patch adds the same.

Signed-off-by: Jerin Jacob 
---
 drivers/common/octeontx2/Makefile |  1 +
 drivers/common/octeontx2/meson.build  |  1 +
 drivers/common/octeontx2/otx2_common.c| 85 +++
 drivers/common/octeontx2/otx2_common.h| 36 
 .../rte_common_octeontx2_version.map  | 11 +++
 5 files changed, 134 insertions(+)
 create mode 100644 drivers/common/octeontx2/otx2_common.c

diff --git a/drivers/common/octeontx2/Makefile 
b/drivers/common/octeontx2/Makefile
index e5737532a..3fd67f0ab 100644
--- a/drivers/common/octeontx2/Makefile
+++ b/drivers/common/octeontx2/Makefile
@@ -25,6 +25,7 @@ LIBABIVER := 1
 # all source are stored in SRCS-y
 #
 SRCS-y += otx2_mbox.c
+SRCS-y += otx2_common.c
 
 LDLIBS += -lrte_eal
 LDLIBS += -lrte_ethdev
diff --git a/drivers/common/octeontx2/meson.build 
b/drivers/common/octeontx2/meson.build
index 34f8aaea7..4771b1942 100644
--- a/drivers/common/octeontx2/meson.build
+++ b/drivers/common/octeontx2/meson.build
@@ -4,6 +4,7 @@
 
 sources= files(
'otx2_mbox.c',
+   'otx2_common.c',
   )
 
 extra_flags = []
diff --git a/drivers/common/octeontx2/otx2_common.c 
b/drivers/common/octeontx2/otx2_common.c
new file mode 100644
index 0..a4b91b4f1
--- /dev/null
+++ b/drivers/common/octeontx2/otx2_common.c
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+
+#include "otx2_common.h"
+
+/**
+ * @internal
+ */
+int otx2_logtype_base;
+/**
+ * @internal
+ */
+int otx2_logtype_mbox;
+/**
+ * @internal
+ */
+int otx2_logtype_npa;
+/**
+ * @internal
+ */
+int otx2_logtype_nix;
+/**
+ * @internal
+ */
+int otx2_logtype_npc;
+/**
+ * @internal
+ */
+int otx2_logtype_tm;
+/**
+ * @internal
+ */
+int otx2_logtype_sso;
+/**
+ * @internal
+ */
+int otx2_logtype_tim;
+/**
+ * @internal
+ */
+int otx2_logtype_dpi;
+
+RTE_INIT(otx2_log_init);
+static void
+otx2_log_init(void)
+{
+   otx2_logtype_base = rte_log_register("pmd.octeontx2.base");
+   if (otx2_logtype_base >= 0)
+   rte_log_set_level(otx2_logtype_base, RTE_LOG_NOTICE);
+
+   otx2_logtype_mbox = rte_log_register("pmd.octeontx2.mbox");
+   if (otx2_logtype_mbox >= 0)
+   rte_log_set_level(otx2_logtype_mbox, RTE_LOG_NOTICE);
+
+   otx2_logtype_npa = rte_log_register("pmd.mempool.octeontx2");
+   if (otx2_logtype_npa >= 0)
+   rte_log_set_level(otx2_logtype_npa, RTE_LOG_NOTICE);
+
+   otx2_logtype_nix = rte_log_register("pmd.net.octeontx2");
+   if (otx2_logtype_nix >= 0)
+   rte_log_set_level(otx2_logtype_nix, RTE_LOG_NOTICE);
+
+   otx2_logtype_npc = rte_log_register("pmd.net.octeontx2.flow");
+   if (otx2_logtype_npc >= 0)
+   rte_log_set_level(otx2_logtype_npc, RTE_LOG_NOTICE);
+
+   otx2_logtype_tm = rte_log_register("pmd.net.octeontx2.tm");
+   if (otx2_logtype_tm >= 0)
+   rte_log_set_level(otx2_logtype_tm, RTE_LOG_NOTICE);
+
+   otx2_logtype_sso = rte_log_register("pmd.event.octeontx2");
+   if (otx2_logtype_sso >= 0)
+   rte_log_set_level(otx2_logtype_sso, RTE_LOG_NOTICE);
+
+   otx2_logtype_tim = rte_log_register("pmd.event.octeontx2.timer");
+   if (otx2_logtype_tim >= 0)
+   rte_log_set_level(otx2_logtype_tim, RTE_LOG_NOTICE);
+
+   otx2_logtype_dpi = rte_log_register("pmd.raw.octeontx2.dpi");
+   if (otx2_logtype_dpi >= 0)
+   rte_log_set_level(otx2_logtype_dpi, RTE_LOG_NOTICE);
+}
diff --git a/drivers/common/octeontx2/otx2_common.h 
b/drivers/common/octeontx2/otx2_common.h
index b0c19266b..58fcf5a41 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -33,6 +33,42 @@
 #define __hot   __attribute__((hot))
 #endif
 
+/* Log */
+extern int otx2_logtype_base;
+extern int otx2_logtype_mbox;
+extern int otx2_logtype_npa;
+extern int otx2_logtype_nix;
+extern int otx2_logtype_sso;
+extern int otx2_logtype_npc;
+extern int otx2_logtype_tm;
+extern int otx2_logtype_tim;
+extern int otx2_logtype_dpi;
+
+#define OTX2_CLNRM  "\x1b[0m"
+#define OTX2_CLRED  "\x1b[31m"
+
+#define otx2_err(fmt, args...) \
+   RTE_LOG(ERR, PMD, ""OTX2_CLRED"%s():%u " fmt OTX2_CLNRM"\n",\
+   __func__, __LINE__, ## args)
+
+#define otx2_info(fmt, args...)
\
+   RTE_LOG(INFO, PMD, fmt"\n", ## args)
+
+#define otx2_dbg(subsystem, fmt, args...)  \
+   rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem,  \
+   "[%s] %s():%u " fmt "\n",   \
+#subsystem, __func__, __LINE__, ##args)
+
+#define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_

[dpdk-dev] [PATCH v2 06/27] common/octeontx2: add mailbox send and receive support

[jerinj]

From: Jerin Jacob 

Each RVU device has a dedicated 64KB mailbox region
shared with its peer for communication. RVU AF has
a separate mailbox region shared with each of RVU PFs
and an RVU PF has a separate region shared with each of
it's VF.

This patch add use 64KB memory and implemented mailbox
send and receive support.

These set of APIs are used by this driver (RVU AF) and
other RVU PF/VF drivers eg ethdev, cryptodev e.t.c.

Signed-off-by: Jerin Jacob 
Signed-off-by: Vamsi Attunuru 
Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/octeontx2/otx2_mbox.c  | 278 ++
 drivers/common/octeontx2/otx2_mbox.h  | 142 +
 .../rte_common_octeontx2_version.map  |   7 +
 3 files changed, 427 insertions(+)

diff --git a/drivers/common/octeontx2/otx2_mbox.c 
b/drivers/common/octeontx2/otx2_mbox.c
index cb03f6503..86559fa98 100644
--- a/drivers/common/octeontx2/otx2_mbox.c
+++ b/drivers/common/octeontx2/otx2_mbox.c
@@ -24,6 +24,12 @@
 #defineRVU_VF_VFPF_MBOX0   (0x)
 #defineRVU_VF_VFPF_MBOX1   (0x0008)
 
+static inline uint16_t
+msgs_offset(void)
+{
+   return RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+}
+
 void
 otx2_mbox_fini(struct otx2_mbox *mbox)
 {
@@ -136,3 +142,275 @@ otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,
 
return 0;
 }
+
+/**
+ * @internal
+ * Allocate a message response
+ */
+struct mbox_msghdr *
+otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, int size,
+   int size_rsp)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[devid];
+   struct mbox_msghdr *msghdr = NULL;
+
+   rte_spinlock_lock(&mdev->mbox_lock);
+   size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
+   size_rsp = RTE_ALIGN(size_rsp, MBOX_MSG_ALIGN);
+   /* Check if there is space in mailbox */
+   if ((mdev->msg_size + size) > mbox->tx_size - msgs_offset())
+   goto exit;
+   if ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset())
+   goto exit;
+   if (mdev->msg_size == 0)
+   mdev->num_msgs = 0;
+   mdev->num_msgs++;
+
+   msghdr = (struct mbox_msghdr *)(((uintptr_t)mdev->mbase +
+   mbox->tx_start + msgs_offset() + mdev->msg_size));
+
+   /* Clear the whole msg region */
+   otx2_mbox_memset(msghdr, 0, sizeof(*msghdr) + size);
+   /* Init message header with reset values */
+   msghdr->ver = OTX2_MBOX_VERSION;
+   mdev->msg_size += size;
+   mdev->rsp_size += size_rsp;
+   msghdr->next_msgoff = mdev->msg_size + msgs_offset();
+exit:
+   rte_spinlock_unlock(&mdev->mbox_lock);
+
+   return msghdr;
+}
+
+/**
+ * @internal
+ * Send a mailbox message
+ */
+void
+otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[devid];
+   struct mbox_hdr *tx_hdr =
+   (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);
+   struct mbox_hdr *rx_hdr =
+   (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+
+   /* Reset header for next messages */
+   tx_hdr->msg_size = mdev->msg_size;
+   mdev->msg_size = 0;
+   mdev->rsp_size = 0;
+   mdev->msgs_acked = 0;
+
+   /* num_msgs != 0 signals to the peer that the buffer has a number of
+* messages. So this should be written after copying txmem
+*/
+   tx_hdr->num_msgs = mdev->num_msgs;
+   rx_hdr->num_msgs = 0;
+
+   /* Sync mbox data into memory */
+   rte_wmb();
+
+   /* The interrupt should be fired after num_msgs is written
+* to the shared memory
+*/
+   rte_write64(1, (volatile void *)(mbox->reg_base +
+   (mbox->trigger | (devid << mbox->tr_shift;
+}
+
+/**
+ * @internal
+ * Wait and get mailbox response
+ */
+int
+otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[devid];
+   struct mbox_msghdr *msghdr;
+   uint64_t offset;
+   int rc;
+
+   rc = otx2_mbox_wait_for_rsp(mbox, devid);
+   if (rc != 1)
+   return -EIO;
+
+   rte_rmb();
+
+   offset = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+   msghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
+   if (msg != NULL)
+   *msg = msghdr;
+
+   return msghdr->rc;
+}
+
+/**
+ * @internal
+ * Wait and get mailbox response with timeout
+ */
+int
+otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
+ uint32_t tmo)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[devid];
+   struct mbox_msghdr *msghdr;
+   uint64_t offset;
+   int rc;
+
+   rc = otx2_mbox_wait_for_rsp_tmo(mbox, devid, tmo);
+   if (rc != 1)
+   return -EIO;
+
+   rte_rmb();
+
+   offset = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_

[dpdk-dev] [PATCH v2 08/27] common/octeontx2: introduce irq handling functions

[jerinj]

From: Jerin Jacob 

All PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,
needs to handle interrupt for mailbox and error handling.
Create a helper function over rte interrupt API to register,
unregister, disable interrupts.

Signed-off-by: Jerin Jacob 
Signed-off-by: Vamsi Attunuru 
Signed-off-by: Krzysztof Kanas 
---
 drivers/common/octeontx2/Makefile |   1 +
 drivers/common/octeontx2/meson.build  |   1 +
 drivers/common/octeontx2/otx2_irq.c   | 254 ++
 drivers/common/octeontx2/otx2_irq.h   |   6 +
 .../rte_common_octeontx2_version.map  |   4 +
 5 files changed, 266 insertions(+)
 create mode 100644 drivers/common/octeontx2/otx2_irq.c

diff --git a/drivers/common/octeontx2/Makefile 
b/drivers/common/octeontx2/Makefile
index a6f94553d..78243e555 100644
--- a/drivers/common/octeontx2/Makefile
+++ b/drivers/common/octeontx2/Makefile
@@ -26,6 +26,7 @@ LIBABIVER := 1
 # all source are stored in SRCS-y
 #
 SRCS-y += otx2_dev.c
+SRCS-y += otx2_irq.c
 SRCS-y += otx2_mbox.c
 SRCS-y += otx2_common.c
 
diff --git a/drivers/common/octeontx2/meson.build 
b/drivers/common/octeontx2/meson.build
index feaf75d92..44ac90085 100644
--- a/drivers/common/octeontx2/meson.build
+++ b/drivers/common/octeontx2/meson.build
@@ -3,6 +3,7 @@
 #
 
 sources= files('otx2_dev.c',
+   'otx2_irq.c',
'otx2_mbox.c',
'otx2_common.c',
   )
diff --git a/drivers/common/octeontx2/otx2_irq.c 
b/drivers/common/octeontx2/otx2_irq.c
new file mode 100644
index 0..fa3206af5
--- /dev/null
+++ b/drivers/common/octeontx2/otx2_irq.c
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "otx2_common.h"
+#include "otx2_irq.h"
+
+#ifdef RTE_EAL_VFIO
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
+#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \
+ sizeof(int) * (MAX_INTR_VEC_ID))
+
+static int
+irq_get_info(struct rte_intr_handle *intr_handle)
+{
+   struct vfio_irq_info irq = { .argsz = sizeof(irq) };
+   int rc;
+
+   irq.index = VFIO_PCI_MSIX_IRQ_INDEX;
+
+   rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);
+   if (rc < 0) {
+   otx2_err("Failed to get IRQ info rc=%d errno=%d", rc, errno);
+   return rc;
+   }
+
+   otx2_base_dbg("Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x",
+ irq.flags, irq.index, irq.count, MAX_INTR_VEC_ID);
+
+   if (irq.count > MAX_INTR_VEC_ID) {
+   otx2_err("HW max=%d > MAX_INTR_VEC_ID: %d",
+intr_handle->max_intr, MAX_INTR_VEC_ID);
+   intr_handle->max_intr = MAX_INTR_VEC_ID;
+   } else {
+   intr_handle->max_intr = irq.count;
+   }
+
+   return 0;
+}
+
+static int
+irq_config(struct rte_intr_handle *intr_handle, unsigned int vec)
+{
+   char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
+   struct vfio_irq_set *irq_set;
+   int32_t *fd_ptr;
+   int len, rc;
+
+   if (vec > intr_handle->max_intr) {
+   otx2_err("vector=%d greater than max_intr=%d", vec,
+   intr_handle->max_intr);
+   return -EINVAL;
+   }
+
+   len = sizeof(struct vfio_irq_set) + sizeof(int32_t);
+
+   irq_set = (struct vfio_irq_set *)irq_set_buf;
+   irq_set->argsz = len;
+
+   irq_set->start = vec;
+   irq_set->count = 1;
+   irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
+   VFIO_IRQ_SET_ACTION_TRIGGER;
+   irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
+
+   /* Use vec fd to set interrupt vectors */
+   fd_ptr = (int32_t *)&irq_set->data[0];
+   fd_ptr[0] = intr_handle->efds[vec];
+
+   rc = ioctl(intr_handle->vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);
+   if (rc)
+   otx2_err("Failed to set_irqs vector=0x%x rc=%d", vec, rc);
+
+   return rc;
+}
+
+static int
+irq_init(struct rte_intr_handle *intr_handle)
+{
+   char irq_set_buf[MSIX_IRQ_SET_BUF_LEN];
+   struct vfio_irq_set *irq_set;
+   int32_t *fd_ptr;
+   int len, rc;
+   uint32_t i;
+
+   if (intr_handle->max_intr > MAX_INTR_VEC_ID) {
+   otx2_err("Max_intr=%d greater than MAX_INTR_VEC_ID=%d",
+   intr_handle->max_intr, MAX_INTR_VEC_ID);
+   return -ERANGE;
+   }
+
+   len = sizeof(struct vfio_irq_set) +
+   sizeof(int32_t) * intr_handle->max_intr;
+
+   irq_set = (struct vfio_irq_set *)irq_set_buf;
+   irq_set->argsz = len;
+   irq_set->start = 0;
+   irq_set->count = intr_handle->max_intr;
+   irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
+   VFIO_IRQ_SET_ACTION_TRIGGER;
+   irq_set->index = VF

[dpdk-dev] [PATCH v2 10/27] common/octeontx2: add AF to PF mailbox IRQ and msg handlers

[jerinj]

From: Nithin Dabilpuram 

This patch adds support for AF to PF mailbox interrupt and message
handling. PF writes the message on mapped mailbox region
followed by writing the mailbox doorbell register. Upon receiving,
the mailbox request in AF(In Linux kernel), It processes the messages
and update the counter memory and update the AF mbox doorbell
register. That would trigger a VFIO interrupt to userspace and
otx2_process_msgs() will handle it.

Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Vamsi Attunuru 
---
 drivers/common/octeontx2/otx2_dev.c | 120 +++-
 1 file changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index 59bd988d1..ba4fd9547 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -14,6 +14,9 @@
 #include "otx2_dev.h"
 #include "otx2_mbox.h"
 
+#define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
+#define RVU_MAX_INT_RETRY  3
+
 /* PF/VF message handling timer */
 #define VF_PF_MBOX_TIMER_MS(20 * 1000)
 
@@ -47,6 +50,108 @@ mbox_mem_unmap(void *va, size_t size)
munmap(va, size);
 }
 
+static void
+otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)
+{
+   struct otx2_mbox_dev *mdev = &mbox->dev[0];
+   struct mbox_hdr *req_hdr;
+   struct mbox_msghdr *msg;
+   int msgs_acked = 0;
+   int offset;
+   uint16_t i;
+
+   req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+   if (req_hdr->num_msgs == 0)
+   return;
+
+   offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
+   for (i = 0; i < req_hdr->num_msgs; i++) {
+   msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
+
+   msgs_acked++;
+   otx2_base_dbg("Message 0x%x (%s) pf:%d/vf:%d",
+ msg->id, otx2_mbox_id2name(msg->id),
+ otx2_get_pf(msg->pcifunc),
+ otx2_get_vf(msg->pcifunc));
+
+   switch (msg->id) {
+   /* Add message id's that are handled here */
+   case MBOX_MSG_READY:
+   /* Get our identity */
+   dev->pf_func = msg->pcifunc;
+   break;
+
+   default:
+   if (msg->rc)
+   otx2_err("Message (%s) response has err=%d",
+otx2_mbox_id2name(msg->id), msg->rc);
+   break;
+   }
+   offset = mbox->rx_start + msg->next_msgoff;
+   }
+
+   otx2_mbox_reset(mbox, 0);
+   /* Update acked if someone is waiting a message */
+   mdev->msgs_acked = msgs_acked;
+   rte_wmb();
+}
+
+static void
+otx2_af_pf_mbox_irq(void *param)
+{
+   struct otx2_dev *dev = param;
+   uint64_t intr;
+
+   intr = otx2_read64(dev->bar2 + RVU_PF_INT);
+   if (intr == 0)
+   return;
+
+   otx2_write64(intr, dev->bar2 + RVU_PF_INT);
+
+   otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
+   if (intr)
+   /* First process all configuration messages */
+   otx2_process_msgs(dev, dev->mbox);
+}
+
+static int
+mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+   int rc;
+
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
+
+   dev->timer_set = 0;
+
+   /* MBOX interrupt AF <-> PF */
+   rc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,
+  dev, RVU_PF_INT_VEC_AFPF_MBOX);
+   if (rc) {
+   otx2_err("Fail to register AF<->PF mbox irq");
+   return rc;
+   }
+
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
+
+   return rc;
+}
+
+static void
+mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
+
+   dev->timer_set = 0;
+
+   /* MBOX interrupt AF <-> PF */
+   otx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,
+   RVU_PF_INT_VEC_AFPF_MBOX);
+}
+
 static void
 otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
 {
@@ -120,10 +225,15 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
if (rc)
goto error;
 
+   /* Register mbox interrupts */
+   rc = mbox_register_irq(pci_dev, dev);
+   if (rc)
+   goto mbox_fini;
+
/* Check the readiness of PF/VF */
rc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);
if (rc)
-   goto mbox_fini;
+   goto 

[dpdk-dev] [PATCH v2 09/27] common/octeontx2: handle intra device operations

[jerinj]

From: Jerin Jacob 

The mempool device(NPA) may be provisioned as a standalone device or
it can be part of ethdev/eventdev device. In order to address
mempool as standalone or integrated with ethdev/eventdev device,
An intra device structure being introduced.

When the _first_ ethdev/eventdev PCIe device or standalone mempool(NPA)
devices get probed by the eal PCI subsystem,
The NPA object(struct otx2_npa_lf) stored in otx2_dev base class.
Once it is accomplished, the other consumer drivers like
ethdev driver or eventdev driver use otx2_npa_* API to operate on
shared NPA object.

The similar concept followed for SSO object, Which needs to share between
PCIe devices.

Signed-off-by: Jerin Jacob 
Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Pavan Nikhilesh 
---
 drivers/common/octeontx2/otx2_common.c| 163 ++
 drivers/common/octeontx2/otx2_common.h|  32 +++-
 drivers/common/octeontx2/otx2_dev.c   |   6 +
 drivers/common/octeontx2/otx2_dev.h   |   1 +
 .../rte_common_octeontx2_version.map  |   9 +
 5 files changed, 210 insertions(+), 1 deletion(-)

diff --git a/drivers/common/octeontx2/otx2_common.c 
b/drivers/common/octeontx2/otx2_common.c
index a4b91b4f1..7e4536639 100644
--- a/drivers/common/octeontx2/otx2_common.c
+++ b/drivers/common/octeontx2/otx2_common.c
@@ -2,9 +2,172 @@
  * Copyright(C) 2019 Marvell International Ltd.
  */
 
+#include 
+#include 
 #include 
 
 #include "otx2_common.h"
+#include "otx2_dev.h"
+#include "otx2_mbox.h"
+
+/**
+ * @internal
+ * Set default NPA configuration.
+ */
+void
+otx2_npa_set_defaults(struct otx2_idev_cfg *idev)
+{
+   idev->npa_pf_func = 0;
+   rte_atomic16_set(&idev->npa_refcnt, 0);
+}
+
+/**
+ * @internal
+ * Get intra device config structure.
+ */
+struct otx2_idev_cfg *
+otx2_intra_dev_get_cfg(void)
+{
+   const char name[] = "octeontx2_intra_device_conf";
+   const struct rte_memzone *mz;
+   struct otx2_idev_cfg *idev;
+
+   mz = rte_memzone_lookup(name);
+   if (mz != NULL)
+   return mz->addr;
+
+   /* Request for the first time */
+   mz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_cfg),
+SOCKET_ID_ANY, 0, OTX2_ALIGN);
+   if (mz != NULL) {
+   idev = mz->addr;
+   idev->sso_pf_func = 0;
+   idev->npa_lf = NULL;
+   otx2_npa_set_defaults(idev);
+   return idev;
+   }
+   return NULL;
+}
+
+/**
+ * @internal
+ * Get SSO PF_FUNC.
+ */
+uint16_t
+otx2_sso_pf_func_get(void)
+{
+   struct otx2_idev_cfg *idev;
+   uint16_t sso_pf_func;
+
+   sso_pf_func = 0;
+   idev = otx2_intra_dev_get_cfg();
+
+   if (idev != NULL)
+   sso_pf_func = idev->sso_pf_func;
+
+   return sso_pf_func;
+}
+
+/**
+ * @internal
+ * Set SSO PF_FUNC.
+ */
+void
+otx2_sso_pf_func_set(uint16_t sso_pf_func)
+{
+   struct otx2_idev_cfg *idev;
+
+   idev = otx2_intra_dev_get_cfg();
+
+   if (idev != NULL) {
+   idev->sso_pf_func = sso_pf_func;
+   rte_smp_wmb();
+   }
+}
+
+/**
+ * @internal
+ * Get NPA PF_FUNC.
+ */
+uint16_t
+otx2_npa_pf_func_get(void)
+{
+   struct otx2_idev_cfg *idev;
+   uint16_t npa_pf_func;
+
+   npa_pf_func = 0;
+   idev = otx2_intra_dev_get_cfg();
+
+   if (idev != NULL)
+   npa_pf_func = idev->npa_pf_func;
+
+   return npa_pf_func;
+}
+
+/**
+ * @internal
+ * Get NPA lf object.
+ */
+struct otx2_npa_lf *
+otx2_npa_lf_obj_get(void)
+{
+   struct otx2_idev_cfg *idev;
+
+   idev = otx2_intra_dev_get_cfg();
+
+   if (idev != NULL && rte_atomic16_read(&idev->npa_refcnt))
+   return idev->npa_lf;
+
+   return NULL;
+}
+
+/**
+ * @internal
+ * Is NPA lf active for the given device?.
+ */
+int
+otx2_npa_lf_active(void *otx2_dev)
+{
+   struct otx2_dev *dev = otx2_dev;
+   struct otx2_idev_cfg *idev;
+
+   /* Check if npalf is actively used on this dev */
+   idev = otx2_intra_dev_get_cfg();
+   if (!idev || !idev->npa_lf || idev->npa_lf->mbox != dev->mbox)
+   return 0;
+
+   return rte_atomic16_read(&idev->npa_refcnt);
+}
+
+/*
+ * @internal
+ * Gets reference only to existing NPA LF object.
+ */
+int otx2_npa_lf_obj_ref(void)
+{
+   struct otx2_idev_cfg *idev;
+   uint16_t cnt;
+   int rc;
+
+   idev = otx2_intra_dev_get_cfg();
+
+   /* Check if ref not possible */
+   if (idev == NULL)
+   return -EINVAL;
+
+
+   /* Get ref only if > 0 */
+   cnt = rte_atomic16_read(&idev->npa_refcnt);
+   while (cnt != 0) {
+   rc = rte_atomic16_cmpset(&idev->npa_refcnt_u16, cnt, cnt + 1);
+   if (rc)
+   break;
+
+   cnt = rte_atomic16_read(&idev->npa_refcnt);
+   }
+
+   return cnt ? 0 : -EINVAL;
+}
 
 /**
  * @internal
diff --git a/drivers/common/octeontx2/otx2_common.h 

[dpdk-dev] [PATCH v2 11/27] common/octeontx2: add PF to VF mailbox IRQ and msg handlers

[jerinj]

From: Nithin Dabilpuram 

PF has additional responsibility being server for VF messages
and forward to AF and once AF process it then forward
the response back to VF.
otx2_vf_pf_mbox_irq() will process the VF mailbox request and
af_pf_wait_msg() will until getting a response back from AF.

Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Krzysztof Kanas 
---
 drivers/common/octeontx2/otx2_dev.c | 240 +++-
 1 file changed, 239 insertions(+), 1 deletion(-)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index ba4fd9547..09b551819 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 
+#include 
 #include 
 #include 
 #include 
@@ -50,6 +51,200 @@ mbox_mem_unmap(void *va, size_t size)
munmap(va, size);
 }
 
+static int
+af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)
+{
+   uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
+   struct otx2_mbox_dev *mdev = &mbox->dev[0];
+   volatile uint64_t int_status;
+   struct mbox_hdr *req_hdr;
+   struct mbox_msghdr *msg;
+   struct mbox_msghdr *rsp;
+   uint64_t offset;
+   size_t size;
+   int i;
+
+   /* We need to disable PF interrupts. We are in timer interrupt */
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
+
+   /* Send message */
+   otx2_mbox_msg_send(mbox, 0);
+
+   do {
+   rte_delay_ms(sleep);
+   timeout++;
+   if (timeout >= MBOX_RSP_TIMEOUT) {
+   otx2_err("Routed messages %d timeout: %dms",
+num_msg, MBOX_RSP_TIMEOUT);
+   break;
+   }
+   int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
+   } while ((int_status & 0x1) != 0x1);
+
+   /* Clear */
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
+
+   /* Enable interrupts */
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
+
+   rte_spinlock_lock(&mdev->mbox_lock);
+
+   req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+   if (req_hdr->num_msgs != num_msg)
+   otx2_err("Routed messages: %d received: %d", num_msg,
+req_hdr->num_msgs);
+
+   /* Get messages from mbox */
+   offset = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+   for (i = 0; i < req_hdr->num_msgs; i++) {
+   msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
+   size = mbox->rx_start + msg->next_msgoff - offset;
+
+   /* Reserve PF/VF mbox message */
+   size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
+   rsp = otx2_mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
+   otx2_mbox_rsp_init(msg->id, rsp);
+
+   /* Copy message from AF<->PF mbox to PF<->VF mbox */
+   otx2_mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
+(uint8_t *)msg + sizeof(struct mbox_msghdr),
+size - sizeof(struct mbox_msghdr));
+
+   /* Set status and sender pf_func data */
+   rsp->rc = msg->rc;
+   rsp->pcifunc = msg->pcifunc;
+
+   offset = mbox->rx_start + msg->next_msgoff;
+   }
+   rte_spinlock_unlock(&mdev->mbox_lock);
+
+   return req_hdr->num_msgs;
+}
+
+static int
+vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)
+{
+   int offset, routed = 0; struct otx2_mbox *mbox = &dev->mbox_vfpf;
+   struct otx2_mbox_dev *mdev = &mbox->dev[vf];
+   struct mbox_hdr *req_hdr;
+   struct mbox_msghdr *msg;
+   size_t size;
+   uint16_t i;
+
+   req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+   if (!req_hdr->num_msgs)
+   return 0;
+
+   offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
+
+   for (i = 0; i < req_hdr->num_msgs; i++) {
+
+   msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
+   size = mbox->rx_start + msg->next_msgoff - offset;
+
+   /* RVU_PF_FUNC_S */
+   msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
+
+   if (msg->id == MBOX_MSG_READY) {
+   struct ready_msg_rsp *rsp;
+   uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
+
+   /* Handle READY message in PF */
+   dev->active_vfs[vf / max_bits] |=
+   BIT_ULL(vf % max_bits);
+   rsp = (struct ready_msg_rsp *)
+  otx2_mbox_alloc_msg(mbox, vf, sizeof(*rsp));
+   otx2_mbox_rsp_init(msg->id, rsp);
+
+   /* PF/VF function ID */
+   rsp->hdr.pcifunc = ms

[dpdk-dev] [PATCH v2 12/27] common/octeontx2: add VF mailbox IRQ and msg handler

[jerinj]

From: Jerin Jacob 

This patch adds support for PF <-> VF mailbox interrupt
mailbox message interrupt handling.

Signed-off-by: Jerin Jacob 
---
 drivers/common/octeontx2/otx2_dev.c | 78 -
 1 file changed, 76 insertions(+), 2 deletions(-)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index 09b551819..fc6dca624 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -291,6 +291,24 @@ otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox 
*mbox)
rte_wmb();
 }
 
+static void
+otx2_pf_vf_mbox_irq(void *param)
+{
+   struct otx2_dev *dev = param;
+   uint64_t intr;
+
+   intr = otx2_read64(dev->bar2 + RVU_VF_INT);
+   if (intr == 0)
+   return;
+
+   otx2_write64(intr, dev->bar2 + RVU_VF_INT);
+   otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
+   if (intr)
+   /* First process all configuration messages */
+   otx2_process_msgs(dev, dev->mbox);
+
+}
+
 static void
 otx2_af_pf_mbox_irq(void *param)
 {
@@ -310,7 +328,7 @@ otx2_af_pf_mbox_irq(void *param)
 }
 
 static int
-mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+mbox_register_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
 {
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
int i, rc;
@@ -359,8 +377,41 @@ mbox_register_irq(struct rte_pci_device *pci_dev, struct 
otx2_dev *dev)
return rc;
 }
 
+static int
+mbox_register_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+   int rc;
+
+   /* Clear irq */
+   otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
+
+   /* MBOX interrupt PF <-> VF */
+   rc = otx2_register_irq(intr_handle, otx2_pf_vf_mbox_irq,
+  dev, RVU_VF_INT_VEC_MBOX);
+   if (rc) {
+   otx2_err("Fail to register PF<->VF mbox irq");
+   return rc;
+   }
+
+   /* HW enable intr */
+   otx2_write64(~0ull, dev->bar2 + RVU_VF_INT);
+   otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);
+
+   return rc;
+}
+
+static int
+mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   if (otx2_dev_is_vf(dev))
+   return mbox_register_vf_irq(pci_dev, dev);
+   else
+   return mbox_register_pf_irq(pci_dev, dev);
+}
+
 static void
-mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+mbox_unregister_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
 {
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
int i;
@@ -388,6 +439,29 @@ mbox_unregister_irq(struct rte_pci_device *pci_dev, struct 
otx2_dev *dev)
/* MBOX interrupt AF <-> PF */
otx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,
RVU_PF_INT_VEC_AFPF_MBOX);
+
+}
+
+static void
+mbox_unregister_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+
+   /* Clear irq */
+   otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
+
+   /* Unregister the interrupt handler */
+   otx2_unregister_irq(intr_handle, otx2_pf_vf_mbox_irq, dev,
+   RVU_VF_INT_VEC_MBOX);
+}
+
+static void
+mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   if (otx2_dev_is_vf(dev))
+   return mbox_unregister_vf_irq(pci_dev, dev);
+   else
+   return mbox_unregister_pf_irq(pci_dev, dev);
 }
 
 static void
-- 
2.21.0

[dpdk-dev] [PATCH v2 07/27] common/octeontx2: introduce common device class

[jerinj]

From: Jerin Jacob 

Introduce otx2_dev class to hold octeontx2 PCIe device specific
information and operations.

All PCIe drivers(ethdev, mempool, cryptodev and eventdev) in octeontx2,
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, etc of the PCIe device.

Signed-off-by: Jerin Jacob 
Signed-off-by: Nithin Dabilpuram 
---
 drivers/common/octeontx2/Makefile |   2 +
 drivers/common/octeontx2/meson.build  |   4 +-
 drivers/common/octeontx2/otx2_common.h|  14 ++
 drivers/common/octeontx2/otx2_dev.c   | 197 ++
 drivers/common/octeontx2/otx2_dev.h   |  84 
 drivers/common/octeontx2/otx2_irq.h   |  19 ++
 .../rte_common_octeontx2_version.map  |   3 +
 7 files changed, 321 insertions(+), 2 deletions(-)
 create mode 100644 drivers/common/octeontx2/otx2_dev.c
 create mode 100644 drivers/common/octeontx2/otx2_dev.h
 create mode 100644 drivers/common/octeontx2/otx2_irq.h

diff --git a/drivers/common/octeontx2/Makefile 
b/drivers/common/octeontx2/Makefile
index 3fd67f0ab..a6f94553d 100644
--- a/drivers/common/octeontx2/Makefile
+++ b/drivers/common/octeontx2/Makefile
@@ -11,6 +11,7 @@ LIB = librte_common_octeontx2.a
 
 CFLAGS += $(WERROR_FLAGS)
 CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
 
 ifneq ($(CONFIG_RTE_ARCH_64),y)
 CFLAGS += -Wno-int-to-pointer-cast
@@ -24,6 +25,7 @@ LIBABIVER := 1
 #
 # all source are stored in SRCS-y
 #
+SRCS-y += otx2_dev.c
 SRCS-y += otx2_mbox.c
 SRCS-y += otx2_common.c
 
diff --git a/drivers/common/octeontx2/meson.build 
b/drivers/common/octeontx2/meson.build
index 4771b1942..feaf75d92 100644
--- a/drivers/common/octeontx2/meson.build
+++ b/drivers/common/octeontx2/meson.build
@@ -2,7 +2,7 @@
 # Copyright(C) 2019 Marvell International Ltd.
 #
 
-sources= files(
+sources= files('otx2_dev.c',
'otx2_mbox.c',
'otx2_common.c',
   )
@@ -19,6 +19,6 @@ foreach flag: extra_flags
endif
 endforeach
 
-deps = ['eal', 'ethdev']
+deps = ['eal', 'pci', 'ethdev']
 includes += include_directories('../../common/octeontx2',
'../../bus/pci')
diff --git a/drivers/common/octeontx2/otx2_common.h 
b/drivers/common/octeontx2/otx2_common.h
index 58fcf5a41..b9e7a7f8d 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -69,6 +69,20 @@ extern int otx2_logtype_dpi;
 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
 
+/* PCI IDs */
+#define PCI_VENDOR_ID_CAVIUM   0x177D
+#define PCI_DEVID_OCTEONTX2_RVU_PF  0xA063
+#define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
+#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
+#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
+#define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
+#define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
+#define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
+#define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
+#define PCI_DEVID_OCTEONTX2_RVU_AF_VF  0xA0f8
+#define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
+
 /* IO Access */
 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
new file mode 100644
index 0..ccdb2df78
--- /dev/null
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include "otx2_dev.h"
+#include "otx2_mbox.h"
+
+/* PF/VF message handling timer */
+#define VF_PF_MBOX_TIMER_MS(20 * 1000)
+
+static void *
+mbox_mem_map(off_t off, size_t size)
+{
+   void *va = MAP_FAILED;
+   int mem_fd;
+
+   if (size <= 0)
+   goto error;
+
+   mem_fd = open("/dev/mem", O_RDWR);
+   if (mem_fd < 0)
+   goto error;
+
+   va = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, off);
+   close(mem_fd);
+
+   if (va == MAP_FAILED)
+   otx2_err("Failed to mmap sz=0x%zx, fd=%d, off=%ld",
+size, mem_fd, off);
+error:
+   return va;
+}
+
+static void
+mbox_mem_unmap(void *va, size_t size)
+{
+   if (va)
+   munmap(va, size);
+}
+
+static void
+otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   RTE_SET_USED(pci_dev);
+
+   /* Update this logic when we have A1 */
+   dev->hwcap |= OTX2_HWCAP_F_A0;
+}
+
+static void
+otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   dev->hwcap = 0;
+
+   switch (pci_dev->i

[dpdk-dev] [PATCH v2 16/27] mempool/octeontx2: add build infra and device probe

[jerinj]

From: Jerin Jacob 

Add the make and meson based build infrastructure along
with the mempool(NPA) device probe.

Signed-off-by: Jerin Jacob 
Signed-off-by: Pavan Nikhilesh 
---
 config/common_base|  5 ++
 drivers/common/Makefile   |  3 +
 drivers/mempool/Makefile  |  1 +
 drivers/mempool/meson.build   |  2 +-
 drivers/mempool/octeontx2/Makefile| 36 
 drivers/mempool/octeontx2/meson.build | 20 +++
 drivers/mempool/octeontx2/otx2_mempool.c  | 57 +++
 .../rte_mempool_octeontx2_version.map |  4 ++
 mk/rte.app.mk |  4 ++
 9 files changed, 131 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mempool/octeontx2/Makefile
 create mode 100644 drivers/mempool/octeontx2/meson.build
 create mode 100644 drivers/mempool/octeontx2/otx2_mempool.c
 create mode 100644 drivers/mempool/octeontx2/rte_mempool_octeontx2_version.map

diff --git a/config/common_base b/config/common_base
index 6f19ad5d2..4a3de0360 100644
--- a/config/common_base
+++ b/config/common_base
@@ -771,6 +771,11 @@ CONFIG_RTE_DRIVER_MEMPOOL_STACK=y
 #
 CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL=y
 
+#
+# Compile PMD for octeontx2 npa mempool device
+#
+CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL=y
+
 #
 # Compile librte_mbuf
 #
diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index e7abe210e..05d75568f 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -23,6 +23,9 @@ ifeq ($(CONFIG_RTE_LIBRTE_COMMON_DPAAX),y)
 DIRS-y += dpaax
 endif
 
+OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+ifeq ($(findstring y,$(OCTEONTX2-y)),y)
 DIRS-y += octeontx2
+endif
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/mempool/Makefile b/drivers/mempool/Makefile
index 28c2e8360..29ef73bf4 100644
--- a/drivers/mempool/Makefile
+++ b/drivers/mempool/Makefile
@@ -13,5 +13,6 @@ endif
 DIRS-$(CONFIG_RTE_DRIVER_MEMPOOL_RING) += ring
 DIRS-$(CONFIG_RTE_DRIVER_MEMPOOL_STACK) += stack
 DIRS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += octeontx
+DIRS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += octeontx2
 
 include $(RTE_SDK)/mk/rte.subdir.mk
diff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build
index 4527d9806..7520e489f 100644
--- a/drivers/mempool/meson.build
+++ b/drivers/mempool/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-drivers = ['bucket', 'dpaa', 'dpaa2', 'octeontx', 'ring', 'stack']
+drivers = ['bucket', 'dpaa', 'dpaa2', 'octeontx', 'octeontx2', 'ring', 'stack']
 std_deps = ['mempool']
 config_flag_fmt = 'RTE_LIBRTE_@0@_MEMPOOL'
 driver_name_fmt = 'rte_mempool_@0@'
diff --git a/drivers/mempool/octeontx2/Makefile 
b/drivers/mempool/octeontx2/Makefile
new file mode 100644
index 0..6fbb6e291
--- /dev/null
+++ b/drivers/mempool/octeontx2/Makefile
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_mempool_octeontx2.a
+
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+CFLAGS += -O3
+
+ifneq ($(CONFIG_RTE_ARCH_64),y)
+CFLAGS += -Wno-int-to-pointer-cast
+CFLAGS += -Wno-pointer-to-int-cast
+endif
+
+EXPORT_MAP := rte_mempool_octeontx2_version.map
+
+LIBABIVER := 1
+
+#
+# all source are stored in SRCS-y
+#
+SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \
+   otx2_mempool.c
+
+LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf
+LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/mempool/octeontx2/meson.build 
b/drivers/mempool/octeontx2/meson.build
new file mode 100644
index 0..ec3c59eef
--- /dev/null
+++ b/drivers/mempool/octeontx2/meson.build
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+#
+
+sources = files('otx2_mempool.c',
+   )
+
+extra_flags = []
+# This integrated controller runs only on a arm64 machine, remove 32bit 
warnings
+if not dpdk_conf.get('RTE_ARCH_64')
+   extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
+endif
+
+foreach flag: extra_flags
+   if cc.has_argument(flag)
+   cflags += flag
+   endif
+endforeach
+
+deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool']
diff --git a/drivers/mempool/octeontx2/otx2_mempool.c 
b/drivers/mempool/octeontx2/otx2_mempool.c
new file mode 100644
index 0..fd8e147f5
--- /dev/null
+++ b/drivers/mempool/octeontx2/otx2_mempool.c
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "otx2_common.h"
+
+static int
+npa_remove(struct rte_pci_device *pci_dev)
+{
+ 

[dpdk-dev] [PATCH v2 13/27] common/octeontx2: add uplink message support

[jerinj]

From: Nithin Dabilpuram 

The events like PHY link status change by AF or PHY configuration
change by PF would call for the uplink message.
The AF initiated uplink would land it in PF and PF would further
forward to VF(if it is intended for that specific VF)

The PF initiated uplink would be distributed to all active VFs.
This patch adds support for the same.

Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Harman Kalra 
---
 drivers/common/octeontx2/otx2_dev.c | 243 +++-
 drivers/common/octeontx2/otx2_dev.h |  11 ++
 2 files changed, 252 insertions(+), 2 deletions(-)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index fc6dca624..3522a1783 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -195,6 +195,57 @@ vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)
return i;
 }
 
+static int
+vf_pf_process_up_msgs(struct otx2_dev *dev, uint16_t vf)
+{
+   struct otx2_mbox *mbox = &dev->mbox_vfpf_up;
+   struct otx2_mbox_dev *mdev = &mbox->dev[vf];
+   struct mbox_hdr *req_hdr;
+   struct mbox_msghdr *msg;
+   int msgs_acked = 0;
+   int offset;
+   uint16_t i;
+
+   req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
+   if (req_hdr->num_msgs == 0)
+   return 0;
+
+   offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
+
+   for (i = 0; i < req_hdr->num_msgs; i++) {
+   msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
+
+   msgs_acked++;
+   /* RVU_PF_FUNC_S */
+   msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
+
+   switch (msg->id) {
+   case MBOX_MSG_CGX_LINK_EVENT:
+   otx2_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
+ msg->id, otx2_mbox_id2name(msg->id),
+ msg->pcifunc, otx2_get_pf(msg->pcifunc),
+ otx2_get_vf(msg->pcifunc));
+   break;
+   case MBOX_MSG_CGX_PTP_RX_INFO:
+   otx2_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
+ msg->id, otx2_mbox_id2name(msg->id),
+ msg->pcifunc, otx2_get_pf(msg->pcifunc),
+ otx2_get_vf(msg->pcifunc));
+   break;
+   default:
+   otx2_err("Not handled UP msg 0x%x (%s) func:0x%x",
+msg->id, otx2_mbox_id2name(msg->id),
+msg->pcifunc);
+   }
+   offset = mbox->rx_start + msg->next_msgoff;
+   }
+   otx2_mbox_reset(mbox, vf);
+   mdev->msgs_acked = msgs_acked;
+   rte_wmb();
+
+   return i;
+}
+
 static void
 otx2_vf_pf_mbox_handle_msg(void *param)
 {
@@ -209,6 +260,8 @@ otx2_vf_pf_mbox_handle_msg(void *param)
otx2_base_dbg("Process vf:%d request (pf:%d, vf:%d)",
   vf, dev->pf, dev->vf);
vf_pf_process_msgs(dev, vf);
+   /* UP messages */
+   vf_pf_process_up_msgs(dev, vf);
dev->intr.bits[vf/max_bits] &= ~(BIT_ULL(vf%max_bits));
}
}
@@ -291,6 +344,185 @@ otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox 
*mbox)
rte_wmb();
 }
 
+/* Copies the message received from AF and sends it to VF */
+static void
+pf_vf_mbox_send_up_msg(struct otx2_dev *dev, void *rec_msg)
+{
+   uint16_t max_bits = sizeof(dev->active_vfs[0]) * sizeof(uint64_t);
+   struct otx2_mbox *vf_mbox = &dev->mbox_vfpf_up;
+   struct msg_req *msg = rec_msg;
+   struct mbox_msghdr *vf_msg;
+   uint16_t vf;
+   size_t size;
+
+   size = RTE_ALIGN(otx2_mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN);
+   /* Send UP message to all VF's */
+   for (vf = 0; vf < vf_mbox->ndevs; vf++) {
+   /* VF active */
+   if (!(dev->active_vfs[vf / max_bits] & (BIT_ULL(vf
+   continue;
+
+   otx2_base_dbg("(%s) size: %zx to VF: %d",
+ otx2_mbox_id2name(msg->hdr.id), size, vf);
+
+   /* Reserve PF/VF mbox message */
+   vf_msg = otx2_mbox_alloc_msg(vf_mbox, vf, size);
+   if (!vf_msg) {
+   otx2_err("Failed to alloc VF%d UP message", vf);
+   continue;
+   }
+   otx2_mbox_req_init(msg->hdr.id, vf_msg);
+
+   /*
+* Copy message from AF<->PF UP mbox
+* to PF<->VF UP mbox
+*/
+   otx2_mbox_memcpy((uint8_t *)vf_msg +
+sizeof(struct mbox_msghdr), (uint8_t *)msg
++ s

[dpdk-dev] [PATCH v2 14/27] common/octeontx2: add FLR IRQ handler

[jerinj]

From: Nithin Dabilpuram 

Upon receiving FLR request from VF, It is PF responsibly
forward to AF and enable FLR for VFs.

This patch adds support for VF FLR support in PF.

This patch also add otx2_dev_active_vfs() API to find
the number of active VF for given PF.

Signed-off-by: Nithin Dabilpuram 
Signed-off-by: Harman Kalra 
---
 drivers/common/octeontx2/otx2_dev.c   | 180 ++
 .../rte_common_octeontx2_version.map  |   1 +
 2 files changed, 181 insertions(+)

diff --git a/drivers/common/octeontx2/otx2_dev.c 
b/drivers/common/octeontx2/otx2_dev.c
index 3522a1783..a75f79101 100644
--- a/drivers/common/octeontx2/otx2_dev.c
+++ b/drivers/common/octeontx2/otx2_dev.c
@@ -51,6 +51,52 @@ mbox_mem_unmap(void *va, size_t size)
munmap(va, size);
 }
 
+static int
+pf_af_sync_msg(struct otx2_dev *dev, struct mbox_msghdr **rsp)
+{
+   uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
+   struct otx2_mbox_dev *mdev = &mbox->dev[0];
+   volatile uint64_t int_status;
+   struct mbox_msghdr *msghdr;
+   uint64_t off;
+   int rc = 0;
+
+   /* We need to disable PF interrupts. We are in timer interrupt */
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
+
+   /* Send message */
+   otx2_mbox_msg_send(mbox, 0);
+
+   do {
+   rte_delay_ms(sleep);
+   timeout += sleep;
+   if (timeout >= MBOX_RSP_TIMEOUT) {
+   otx2_err("Message timeout: %dms", MBOX_RSP_TIMEOUT);
+   rc = -EIO;
+   break;
+   }
+   int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
+   } while ((int_status & 0x1) != 0x1);
+
+   /* Clear */
+   otx2_write64(int_status, dev->bar2 + RVU_PF_INT);
+
+   /* Enable interrupts */
+   otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
+
+   if (rc == 0) {
+   /* Get message */
+   off = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+   msghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);
+   if (rsp)
+   *rsp = msghdr;
+   rc = msghdr->rc;
+   }
+
+   return rc;
+}
+
 static int
 af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)
 {
@@ -703,6 +749,132 @@ mbox_unregister_irq(struct rte_pci_device *pci_dev, 
struct otx2_dev *dev)
return mbox_unregister_pf_irq(pci_dev, dev);
 }
 
+static int
+vf_flr_send_msg(struct otx2_dev *dev, uint16_t vf)
+{
+   struct otx2_mbox *mbox = dev->mbox;
+   struct msg_req *req;
+   int rc;
+
+   req = otx2_mbox_alloc_msg_vf_flr(mbox);
+   /* Overwrite pcifunc to indicate VF */
+   req->hdr.pcifunc = otx2_pfvf_func(dev->pf, vf);
+
+   /* Sync message in interrupt context */
+   rc = pf_af_sync_msg(dev, NULL);
+   if (rc)
+   otx2_err("Failed to send VF FLR mbox msg, rc=%d", rc);
+
+   return rc;
+}
+
+static void
+otx2_pf_vf_flr_irq(void *param)
+{
+   struct otx2_dev *dev = (struct otx2_dev *)param;
+   uint16_t max_vf = 64, vf;
+   uintptr_t bar2;
+   uint64_t intr;
+   int i;
+
+   max_vf = (dev->maxvf > 0) ? dev->maxvf : 64;
+   bar2 = dev->bar2;
+
+   otx2_base_dbg("FLR VF interrupt: max_vf: %d", max_vf);
+
+   for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
+   intr = otx2_read64(bar2 + RVU_PF_VFFLR_INTX(i));
+   if (!intr)
+   continue;
+
+   for (vf = 0; vf < max_vf; vf++) {
+   if (!(intr & (1ULL << vf)))
+   continue;
+
+   vf = 64 * i + vf;
+   otx2_base_dbg("FLR: i :%d intr: 0x%" PRIx64 ", vf-%d",
+ i, intr, vf);
+   /* Clear interrupt */
+   otx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));
+   /* Disable the interrupt */
+   otx2_write64(BIT_ULL(vf),
+bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
+   /* Inform AF about VF reset */
+   vf_flr_send_msg(dev, vf);
+
+   /* Signal FLR finish */
+   otx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));
+   /* Enable interrupt */
+   otx2_write64(~0ull,
+bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
+   }
+   }
+}
+
+static int
+vf_flr_unregister_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
+{
+   struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
+   int i;
+
+   otx2_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
+
+   /* HW clear irq */
+   for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
+   otx2_write64(

[dpdk-dev] [PATCH v2 18/27] mempool/octeontx2: add NPA HW operations

[jerinj]

From: Jerin Jacob 

Implement the low-level NPA HW operations such as
alloc, free memory, etc.

Signed-off-by: Jerin Jacob 
Signed-off-by: Kiran Kumar K 
---
 drivers/mempool/octeontx2/otx2_mempool.h | 146 +++
 1 file changed, 146 insertions(+)

diff --git a/drivers/mempool/octeontx2/otx2_mempool.h 
b/drivers/mempool/octeontx2/otx2_mempool.h
index e1c255c60..871b45870 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.h
+++ b/drivers/mempool/octeontx2/otx2_mempool.h
@@ -48,6 +48,152 @@ struct otx2_npa_lf {
 
 #define AURA_ID_MASK  (BIT_ULL(16) - 1)
 
+/*
+ * Generate 64bit handle to have optimized alloc and free aura operation.
+ * 0 - AURA_ID_MASK for storing the aura_id.
+ * AURA_ID_MASK+1 - (2^64 - 1) for storing the lf base address.
+ * This scheme is valid when OS can give AURA_ID_MASK
+ * aligned address for lf base address.
+ */
+static inline uint64_t
+npa_lf_aura_handle_gen(uint32_t aura_id, uintptr_t addr)
+{
+   uint64_t val;
+
+   val = aura_id & AURA_ID_MASK;
+   return (uint64_t)addr | val;
+}
+
+static inline uint64_t
+npa_lf_aura_handle_to_aura(uint64_t aura_handle)
+{
+   return aura_handle & AURA_ID_MASK;
+}
+
+static inline uintptr_t
+npa_lf_aura_handle_to_base(uint64_t aura_handle)
+{
+   return (uintptr_t)(aura_handle & ~AURA_ID_MASK);
+}
+
+static inline uint64_t
+npa_lf_aura_op_alloc(uint64_t aura_handle, const int drop)
+{
+   uint64_t wdata = npa_lf_aura_handle_to_aura(aura_handle);
+
+   if (drop)
+   wdata |= BIT_ULL(63); /* DROP */
+
+   return otx2_atomic64_add_nosync(wdata,
+   (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +
+   NPA_LF_AURA_OP_ALLOCX(0)));
+}
+
+static inline void
+npa_lf_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova)
+{
+   uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);
+
+   if (fabs)
+   reg |= BIT_ULL(63); /* FABS */
+
+   otx2_store_pair(iova, reg,
+   npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0);
+}
+
+static inline uint64_t
+npa_lf_aura_op_cnt_get(uint64_t aura_handle)
+{
+   uint64_t wdata;
+   uint64_t reg;
+
+   wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;
+
+   reg = otx2_atomic64_add_nosync(wdata,
+   (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +
+NPA_LF_AURA_OP_CNT));
+
+   if (reg & BIT_ULL(42) /* OP_ERR */)
+   return 0;
+   else
+   return reg & 0xF;
+}
+
+static inline void
+npa_lf_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)
+{
+   uint64_t reg = count & (BIT_ULL(36) - 1);
+
+   if (sign)
+   reg |= BIT_ULL(43); /* CNT_ADD */
+
+   reg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);
+
+   otx2_write64(reg,
+   npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT);
+}
+
+static inline uint64_t
+npa_lf_aura_op_limit_get(uint64_t aura_handle)
+{
+   uint64_t wdata;
+   uint64_t reg;
+
+   wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;
+
+   reg = otx2_atomic64_add_nosync(wdata,
+   (int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +
+NPA_LF_AURA_OP_LIMIT));
+
+   if (reg & BIT_ULL(42) /* OP_ERR */)
+   return 0;
+   else
+   return reg & 0xF;
+}
+
+static inline void
+npa_lf_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)
+{
+   uint64_t reg = limit & (BIT_ULL(36) - 1);
+
+   reg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);
+
+   otx2_write64(reg,
+   npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT);
+}
+
+static inline uint64_t
+npa_lf_aura_op_available(uint64_t aura_handle)
+{
+   uint64_t wdata;
+   uint64_t reg;
+
+   wdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;
+
+   reg = otx2_atomic64_add_nosync(wdata,
+   (int64_t *)(npa_lf_aura_handle_to_base(
+aura_handle) + NPA_LF_POOL_OP_AVAILABLE));
+
+   if (reg & BIT_ULL(42) /* OP_ERR */)
+   return 0;
+   else
+   return reg & 0xF;
+}
+
+static inline void
+npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,
+   uint64_t end_iova)
+{
+   uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);
+
+   otx2_store_pair(start_iova, reg,
+   npa_lf_aura_handle_to_base(aura_handle) +
+   NPA_LF_POOL_OP_PTR_START0);
+   otx2_store_pair(end_iova, reg,
+   npa_lf_aura_handle_to_base(aura_handle) +
+   NPA_LF_POOL_OP_PTR_END0);
+}
+
 /* NPA LF */
 int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);
 int otx2_npa_lf_fini(void);
-- 
2.21.0

[dpdk-dev] [PATCH v2 19/27] mempool/octeontx2: add NPA IRQ handler

[jerinj]

From: Jerin Jacob 

Register and implement NPA IRQ handler for RAS and all type of
error interrupts to get the fatal errors from HW.

Signed-off-by: Jerin Jacob 
Signed-off-by: Harman Kalra 
---
 drivers/mempool/octeontx2/Makefile   |   3 +-
 drivers/mempool/octeontx2/meson.build|   1 +
 drivers/mempool/octeontx2/otx2_mempool.c |   6 +
 drivers/mempool/octeontx2/otx2_mempool.h |   4 +
 drivers/mempool/octeontx2/otx2_mempool_irq.c | 307 +++
 5 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mempool/octeontx2/otx2_mempool_irq.c

diff --git a/drivers/mempool/octeontx2/Makefile 
b/drivers/mempool/octeontx2/Makefile
index 6fbb6e291..86950b270 100644
--- a/drivers/mempool/octeontx2/Makefile
+++ b/drivers/mempool/octeontx2/Makefile
@@ -28,7 +28,8 @@ LIBABIVER := 1
 # all source are stored in SRCS-y
 #
 SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \
-   otx2_mempool.c
+   otx2_mempool.c  \
+   otx2_mempool_irq.c
 
 LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf
 LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci
diff --git a/drivers/mempool/octeontx2/meson.build 
b/drivers/mempool/octeontx2/meson.build
index ec3c59eef..3f93b509d 100644
--- a/drivers/mempool/octeontx2/meson.build
+++ b/drivers/mempool/octeontx2/meson.build
@@ -3,6 +3,7 @@
 #
 
 sources = files('otx2_mempool.c',
+   'otx2_mempool_irq.c',
)
 
 extra_flags = []
diff --git a/drivers/mempool/octeontx2/otx2_mempool.c 
b/drivers/mempool/octeontx2/otx2_mempool.c
index fa74b7532..1bcb86cf4 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.c
+++ b/drivers/mempool/octeontx2/otx2_mempool.c
@@ -195,6 +195,7 @@ otx2_npa_lf_fini(void)
return -ENOMEM;
 
if (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {
+   otx2_npa_unregister_irqs(idev->npa_lf);
rc |= npa_lf_fini(idev->npa_lf);
rc |= npa_lf_detach(idev->npa_lf->mbox);
otx2_npa_set_defaults(idev);
@@ -251,6 +252,9 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
idev->npa_pf_func = dev->pf_func;
idev->npa_lf = lf;
rte_smp_wmb();
+   rc = otx2_npa_register_irqs(lf);
+   if (rc)
+   goto npa_fini;
 
rte_mbuf_set_platform_mempool_ops("octeontx2_npa");
otx2_npa_dbg("npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x",
@@ -259,6 +263,8 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
 
return 0;
 
+npa_fini:
+   npa_lf_fini(idev->npa_lf);
 npa_detach:
npa_lf_detach(dev->mbox);
 fail:
diff --git a/drivers/mempool/octeontx2/otx2_mempool.h 
b/drivers/mempool/octeontx2/otx2_mempool.h
index 871b45870..41542cf89 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.h
+++ b/drivers/mempool/octeontx2/otx2_mempool.h
@@ -198,4 +198,8 @@ npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t 
start_iova,
 int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);
 int otx2_npa_lf_fini(void);
 
+/* IRQ */
+int otx2_npa_register_irqs(struct otx2_npa_lf *lf);
+void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);
+
 #endif /* __OTX2_MEMPOOL_H__ */
diff --git a/drivers/mempool/octeontx2/otx2_mempool_irq.c 
b/drivers/mempool/octeontx2/otx2_mempool_irq.c
new file mode 100644
index 0..510d3e994
--- /dev/null
+++ b/drivers/mempool/octeontx2/otx2_mempool_irq.c
@@ -0,0 +1,307 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+
+#include 
+#include 
+
+#include "otx2_common.h"
+#include "otx2_irq.h"
+#include "otx2_mempool.h"
+
+static void
+npa_lf_err_irq(void *param)
+{
+   struct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;
+   uint64_t intr;
+
+   intr = otx2_read64(lf->base + NPA_LF_ERR_INT);
+   if (intr == 0)
+   return;
+
+   otx2_err("Err_intr=0x%" PRIx64 "", intr);
+
+   /* Clear interrupt */
+   otx2_write64(intr, lf->base + NPA_LF_ERR_INT);
+
+   abort();
+}
+
+static int
+npa_lf_register_err_irq(struct otx2_npa_lf *lf)
+{
+   struct rte_intr_handle *handle = lf->intr_handle;
+   int rc, vec;
+
+   vec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;
+
+   /* Clear err interrupt */
+   otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);
+   /* Register err interrupt vector */
+   rc = otx2_register_irq(handle, npa_lf_err_irq, lf, vec);
+
+   /* Enable hw interrupt */
+   otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S);
+
+   return rc;
+}
+
+static void
+npa_lf_unregister_err_irq(struct otx2_npa_lf *lf)
+{
+   struct rte_intr_handle *handle = lf->intr_handle;
+   int vec;
+
+   vec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;
+
+   /* Clear err interrupt */
+   otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);
+   otx2_unregister_irq(hand

[dpdk-dev] [PATCH v2 22/27] mempool/octeontx2: add mempool free op

[jerinj]

From: Jerin Jacob 

The DPDK mempool free operation frees HW AURA
and POOL reserved in alloc operation. In addition to that it free all
the memory resources allocated in mempool alloc operations.

Cc: Olivier Matz 

Signed-off-by: Jerin Jacob 
---
 drivers/mempool/octeontx2/otx2_mempool_ops.c | 104 +++
 1 file changed, 104 insertions(+)

diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c 
b/drivers/mempool/octeontx2/otx2_mempool_ops.c
index 0e7b7a77c..94570319a 100644
--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c
+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c
@@ -47,6 +47,62 @@ npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t 
aura_id,
return NPA_LF_ERR_AURA_POOL_INIT;
 }
 
+static int
+npa_lf_aura_pool_fini(struct otx2_mbox *mbox,
+ uint32_t aura_id,
+ uint64_t aura_handle)
+{
+   struct npa_aq_enq_req *aura_req, *pool_req;
+   struct npa_aq_enq_rsp *aura_rsp, *pool_rsp;
+   struct otx2_mbox_dev *mdev = &mbox->dev[0];
+   struct ndc_sync_op *ndc_req;
+   int rc, off;
+
+   /* Procedure for disabling an aura/pool */
+   rte_delay_us(10);
+   npa_lf_aura_op_alloc(aura_handle, 0);
+
+   pool_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
+   pool_req->aura_id = aura_id;
+   pool_req->ctype = NPA_AQ_CTYPE_POOL;
+   pool_req->op = NPA_AQ_INSTOP_WRITE;
+   pool_req->pool.ena = 0;
+   pool_req->pool_mask.ena = ~pool_req->pool_mask.ena;
+
+   aura_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
+   aura_req->aura_id = aura_id;
+   aura_req->ctype = NPA_AQ_CTYPE_AURA;
+   aura_req->op = NPA_AQ_INSTOP_WRITE;
+   aura_req->aura.ena = 0;
+   aura_req->aura_mask.ena = ~aura_req->aura_mask.ena;
+
+   otx2_mbox_msg_send(mbox, 0);
+   rc = otx2_mbox_wait_for_rsp(mbox, 0);
+   if (rc < 0)
+   return rc;
+
+   off = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+   pool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
+
+   off = mbox->rx_start + pool_rsp->hdr.next_msgoff;
+   aura_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
+
+   if (rc != 2 || aura_rsp->hdr.rc != 0 || pool_rsp->hdr.rc != 0)
+   return NPA_LF_ERR_AURA_POOL_FINI;
+
+   /* Sync NDC-NPA for LF */
+   ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
+   ndc_req->npa_lf_sync = 1;
+
+   rc = otx2_mbox_process(mbox);
+   if (rc) {
+   otx2_err("Error on NDC-NPA LF sync, rc %d", rc);
+   return NPA_LF_ERR_AURA_POOL_FINI;
+   }
+   return 0;
+}
+
 static inline char*
 npa_lf_stack_memzone_name(struct otx2_npa_lf *lf, int pool_id, char *name)
 {
@@ -65,6 +121,18 @@ npa_lf_stack_dma_alloc(struct otx2_npa_lf *lf, char *name,
RTE_MEMZONE_IOVA_CONTIG, OTX2_ALIGN);
 }
 
+static inline int
+npa_lf_stack_dma_free(struct otx2_npa_lf *lf, char *name, int pool_id)
+{
+   const struct rte_memzone *mz;
+
+   mz = rte_memzone_lookup(npa_lf_stack_memzone_name(lf, pool_id, name));
+   if (mz == NULL)
+   return -EINVAL;
+
+   return rte_memzone_free(mz);
+}
+
 static inline int
 bitmap_ctzll(uint64_t slab)
 {
@@ -179,6 +247,24 @@ npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const 
uint32_t block_size,
return rc;
 }
 
+static int
+npa_lf_aura_pool_pair_free(struct otx2_npa_lf *lf, uint64_t aura_handle)
+{
+   char name[RTE_MEMZONE_NAMESIZE];
+   int aura_id, pool_id, rc;
+
+   if (!lf || !aura_handle)
+   return NPA_LF_ERR_PARAM;
+
+   aura_id = pool_id = npa_lf_aura_handle_to_aura(aura_handle);
+   rc = npa_lf_aura_pool_fini(lf->mbox, aura_id, aura_handle);
+   rc |= npa_lf_stack_dma_free(lf, name, pool_id);
+
+   rte_bitmap_set(lf->npa_bmp, aura_id);
+
+   return rc;
+}
+
 static int
 otx2_npa_alloc(struct rte_mempool *mp)
 {
@@ -238,9 +324,27 @@ otx2_npa_alloc(struct rte_mempool *mp)
return rc;
 }
 
+static void
+otx2_npa_free(struct rte_mempool *mp)
+{
+   struct otx2_npa_lf *lf = otx2_npa_lf_obj_get();
+   int rc = 0;
+
+   otx2_npa_dbg("lf=%p aura_handle=0x%"PRIx64, lf, mp->pool_id);
+   if (lf != NULL)
+   rc = npa_lf_aura_pool_pair_free(lf, mp->pool_id);
+
+   if (rc)
+   otx2_err("Failed to free pool or aura rc=%d", rc);
+
+   /* Release the reference of npalf */
+   otx2_npa_lf_fini();
+}
+
 static struct rte_mempool_ops otx2_npa_ops = {
.name = "octeontx2_npa",
.alloc = otx2_npa_alloc,
+   .free = otx2_npa_free,
 };
 
 MEMPOOL_REGISTER_OPS(otx2_npa_ops);
-- 
2.21.0

[dpdk-dev] [PATCH v2 17/27] drivers: add init and fini on octeontx2 NPA object

[jerinj]

From: Jerin Jacob 

NPA object needs to initialize memory for queue interrupts context,
pool resource management, etc. This patch adds support for initializing
and finalizing the NPA object.

This patch also updates the otx2_npa_lf definition to meet the init/fini
requirements.

Signed-off-by: Jerin Jacob 
Signed-off-by: Vamsi Attunuru 
---
 drivers/common/octeontx2/Makefile |   1 +
 drivers/common/octeontx2/meson.build  |   2 +-
 drivers/common/octeontx2/otx2_common.h|   7 +-
 drivers/common/octeontx2/otx2_dev.h   |   1 +
 drivers/mempool/octeontx2/otx2_mempool.c  | 344 +-
 drivers/mempool/octeontx2/otx2_mempool.h  |  55 +++
 .../rte_mempool_octeontx2_version.map |   4 +
 7 files changed, 403 insertions(+), 11 deletions(-)
 create mode 100644 drivers/mempool/octeontx2/otx2_mempool.h

diff --git a/drivers/common/octeontx2/Makefile 
b/drivers/common/octeontx2/Makefile
index 78243e555..fabc32537 100644
--- a/drivers/common/octeontx2/Makefile
+++ b/drivers/common/octeontx2/Makefile
@@ -11,6 +11,7 @@ LIB = librte_common_octeontx2.a
 
 CFLAGS += $(WERROR_FLAGS)
 CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
 CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
 
 ifneq ($(CONFIG_RTE_ARCH_64),y)
diff --git a/drivers/common/octeontx2/meson.build 
b/drivers/common/octeontx2/meson.build
index 44ac90085..b79145788 100644
--- a/drivers/common/octeontx2/meson.build
+++ b/drivers/common/octeontx2/meson.build
@@ -22,4 +22,4 @@ endforeach
 
 deps = ['eal', 'pci', 'ethdev']
 includes += include_directories('../../common/octeontx2',
-   '../../bus/pci')
+   '../../mempool/octeontx2', '../../bus/pci')
diff --git a/drivers/common/octeontx2/otx2_common.h 
b/drivers/common/octeontx2/otx2_common.h
index cbc5c65a7..cdb25d9ed 100644
--- a/drivers/common/octeontx2/otx2_common.h
+++ b/drivers/common/octeontx2/otx2_common.h
@@ -37,12 +37,7 @@
 #endif
 
 /* Intra device related functions */
-struct otx2_npa_lf {
-   struct otx2_mbox *mbox;
-   struct rte_pci_device *pci_dev;
-   struct rte_intr_handle *intr_handle;
-};
-
+struct otx2_npa_lf;
 struct otx2_idev_cfg {
uint16_t sso_pf_func;
uint16_t npa_pf_func;
diff --git a/drivers/common/octeontx2/otx2_dev.h 
b/drivers/common/octeontx2/otx2_dev.h
index 8fa5f32d2..be862ad1b 100644
--- a/drivers/common/octeontx2/otx2_dev.h
+++ b/drivers/common/octeontx2/otx2_dev.h
@@ -10,6 +10,7 @@
 #include "otx2_common.h"
 #include "otx2_irq.h"
 #include "otx2_mbox.h"
+#include "otx2_mempool.h"
 
 /* Common HWCAP flags. Use from LSB bits */
 #define OTX2_HWCAP_F_VFBIT_ULL(0) /* VF device */
diff --git a/drivers/mempool/octeontx2/otx2_mempool.c 
b/drivers/mempool/octeontx2/otx2_mempool.c
index fd8e147f5..fa74b7532 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.c
+++ b/drivers/mempool/octeontx2/otx2_mempool.c
@@ -2,12 +2,350 @@
  * Copyright(C) 2019 Marvell International Ltd.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 #include 
 
 #include "otx2_common.h"
+#include "otx2_dev.h"
+#include "otx2_mempool.h"
+
+#define OTX2_NPA_DEV_NAME  RTE_STR(otx2_npa_dev_)
+#define OTX2_NPA_DEV_NAME_LEN  (sizeof(OTX2_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)
+
+static inline int
+npa_lf_alloc(struct otx2_npa_lf *lf)
+{
+   struct otx2_mbox *mbox = lf->mbox;
+   struct npa_lf_alloc_req *req;
+   struct npa_lf_alloc_rsp *rsp;
+   int rc;
+
+   req = otx2_mbox_alloc_msg_npa_lf_alloc(mbox);
+   req->aura_sz = lf->aura_sz;
+   req->nr_pools = lf->nr_pools;
+
+   rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
+   if (rc)
+   return NPA_LF_ERR_ALLOC;
+
+   lf->stack_pg_ptrs = rsp->stack_pg_ptrs;
+   lf->stack_pg_bytes = rsp->stack_pg_bytes;
+   lf->qints = rsp->qints;
+
+   return 0;
+}
+
+static int
+npa_lf_free(struct otx2_mbox *mbox)
+{
+   otx2_mbox_alloc_msg_npa_lf_free(mbox);
+
+   return otx2_mbox_process(mbox);
+}
+
+static int
+npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz,
+   uint32_t nr_pools, struct otx2_mbox *mbox)
+{
+   uint32_t i, bmp_sz;
+   int rc;
+
+   /* Sanity checks */
+   if (!lf || !base || !mbox || !nr_pools)
+   return NPA_LF_ERR_PARAM;
+
+   if (base & AURA_ID_MASK)
+   return NPA_LF_ERR_BASE_INVALID;
+
+   if (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)
+   return NPA_LF_ERR_PARAM;
+
+   memset(lf, 0x0, sizeof(*lf));
+   lf->base = base;
+   lf->aura_sz = aura_sz;
+   lf->nr_pools = nr_pools;
+   lf->mbox = mbox;
+
+   rc = npa_lf_alloc(lf);
+   if (rc)
+   goto exit;
+
+   bmp_sz = rte_bitmap_get_memory_footprint(nr_pools);
+
+   /* Allocate memory for bitmap */
+   lf->npa_bmp_mem = rte_zmalloc("npa_bmp_mem", bmp_sz,
+   RTE_

[dpdk-dev] [PATCH v2 23/27] mempool/octeontx2: add remaining slow path ops

[jerinj]

From: Jerin Jacob 

Add remaining get_count(), calc_mem_size() and populate() slow path
mempool operations.

Signed-off-by: Jerin Jacob 
Signed-off-by: Pavan Nikhilesh 
---
 drivers/mempool/octeontx2/otx2_mempool_ops.c | 62 
 1 file changed, 62 insertions(+)

diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c 
b/drivers/mempool/octeontx2/otx2_mempool_ops.c
index 94570319a..966b7d7f1 100644
--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c
+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c
@@ -7,6 +7,12 @@
 
 #include "otx2_mempool.h"
 
+static unsigned int
+otx2_npa_get_count(const struct rte_mempool *mp)
+{
+   return (unsigned int)npa_lf_aura_op_available(mp->pool_id);
+}
+
 static int
 npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id,
  struct npa_aura_s *aura, struct npa_pool_s *pool)
@@ -341,10 +347,66 @@ otx2_npa_free(struct rte_mempool *mp)
otx2_npa_lf_fini();
 }
 
+static ssize_t
+otx2_npa_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num,
+  uint32_t pg_shift, size_t *min_chunk_size, size_t *align)
+{
+   ssize_t mem_size;
+
+   /*
+* Simply need space for one more object to be able to
+* fulfill alignment requirements.
+*/
+   mem_size = rte_mempool_op_calc_mem_size_default(mp, obj_num + 1,
+   pg_shift,
+   min_chunk_size, align);
+   if (mem_size >= 0) {
+   /*
+* Memory area which contains objects must be physically
+* contiguous.
+*/
+   *min_chunk_size = mem_size;
+   }
+
+   return mem_size;
+}
+
+static int
+otx2_npa_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr,
+ rte_iova_t iova, size_t len,
+ rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg)
+{
+   size_t total_elt_sz;
+   size_t off;
+
+   if (iova == RTE_BAD_IOVA)
+   return -EINVAL;
+
+   total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;
+
+   /* Align object start address to a multiple of total_elt_sz */
+   off = total_elt_sz - ((uintptr_t)vaddr % total_elt_sz);
+
+   if (len < off)
+   return -EINVAL;
+
+   vaddr = (char *)vaddr + off;
+   iova += off;
+   len -= off;
+
+   npa_lf_aura_op_range_set(mp->pool_id, iova, iova + len);
+
+   return rte_mempool_op_populate_default(mp, max_objs, vaddr, iova, len,
+  obj_cb, obj_cb_arg);
+}
+
 static struct rte_mempool_ops otx2_npa_ops = {
.name = "octeontx2_npa",
.alloc = otx2_npa_alloc,
.free = otx2_npa_free,
+   .get_count = otx2_npa_get_count,
+   .calc_mem_size = otx2_npa_calc_mem_size,
+   .populate = otx2_npa_populate,
 };
 
 MEMPOOL_REGISTER_OPS(otx2_npa_ops);
-- 
2.21.0

[dpdk-dev] [PATCH v2 20/27] mempool/octeontx2: add context dump support

[jerinj]

From: Jerin Jacob 

Add a helper function to dump aura and pool context for NPA debugging.

Signed-off-by: Jerin Jacob 
Signed-off-by: Vivek Sharma 
---
 drivers/mempool/octeontx2/Makefile|   3 +-
 drivers/mempool/octeontx2/meson.build |   1 +
 drivers/mempool/octeontx2/otx2_mempool.h  |   3 +
 .../mempool/octeontx2/otx2_mempool_debug.c| 135 ++
 drivers/mempool/octeontx2/otx2_mempool_irq.c  |   1 +
 5 files changed, 142 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mempool/octeontx2/otx2_mempool_debug.c

diff --git a/drivers/mempool/octeontx2/Makefile 
b/drivers/mempool/octeontx2/Makefile
index 86950b270..b86d469f4 100644
--- a/drivers/mempool/octeontx2/Makefile
+++ b/drivers/mempool/octeontx2/Makefile
@@ -29,7 +29,8 @@ LIBABIVER := 1
 #
 SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \
otx2_mempool.c  \
-   otx2_mempool_irq.c
+   otx2_mempool_irq.c  \
+   otx2_mempool_debug.c
 
 LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf
 LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci
diff --git a/drivers/mempool/octeontx2/meson.build 
b/drivers/mempool/octeontx2/meson.build
index 3f93b509d..ab306b729 100644
--- a/drivers/mempool/octeontx2/meson.build
+++ b/drivers/mempool/octeontx2/meson.build
@@ -4,6 +4,7 @@
 
 sources = files('otx2_mempool.c',
'otx2_mempool_irq.c',
+   'otx2_mempool_debug.c'
)
 
 extra_flags = []
diff --git a/drivers/mempool/octeontx2/otx2_mempool.h 
b/drivers/mempool/octeontx2/otx2_mempool.h
index 41542cf89..efaa308b3 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.h
+++ b/drivers/mempool/octeontx2/otx2_mempool.h
@@ -202,4 +202,7 @@ int otx2_npa_lf_fini(void);
 int otx2_npa_register_irqs(struct otx2_npa_lf *lf);
 void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);
 
+/* Debug */
+int otx2_mempool_ctx_dump(struct otx2_npa_lf *lf);
+
 #endif /* __OTX2_MEMPOOL_H__ */
diff --git a/drivers/mempool/octeontx2/otx2_mempool_debug.c 
b/drivers/mempool/octeontx2/otx2_mempool_debug.c
new file mode 100644
index 0..eef61ef07
--- /dev/null
+++ b/drivers/mempool/octeontx2/otx2_mempool_debug.c
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include "otx2_mempool.h"
+
+#define npa_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
+
+static inline void
+npa_lf_pool_dump(struct npa_pool_s *pool)
+{
+   npa_dump("W0: Stack base\t\t0x%"PRIx64"", pool->stack_base);
+   npa_dump("W1: ena \t\t%d\nW1: nat_align \t\t%d\nW1: stack_caching \t%d",
+   pool->ena, pool->nat_align, pool->stack_caching);
+   npa_dump("W1: stack_way_mask\t%d\nW1: buf_offset\t\t%d",
+   pool->stack_way_mask, pool->buf_offset);
+   npa_dump("W1: buf_size \t\t%d", pool->buf_size);
+
+   npa_dump("W2: stack_max_pages \t%d\nW2: stack_pages\t\t%d",
+   pool->stack_max_pages, pool->stack_pages);
+
+   npa_dump("W3: op_pc \t\t0x%"PRIx64"", (uint64_t)pool->op_pc);
+
+   npa_dump("W4: stack_offset\t%d\nW4: shift\t\t%d\nW4: avg_level\t\t%d",
+   pool->stack_offset, pool->shift, pool->avg_level);
+   npa_dump("W4: avg_con \t\t%d\nW4: fc_ena\t\t%d\nW4: fc_stype\t\t%d",
+   pool->avg_con, pool->fc_ena, pool->fc_stype);
+   npa_dump("W4: fc_hyst_bits\t%d\nW4: fc_up_crossing\t%d",
+   pool->fc_hyst_bits, pool->fc_up_crossing);
+   npa_dump("W4: update_time\t\t%d\n", pool->update_time);
+
+   npa_dump("W5: fc_addr\t\t0x%"PRIx64"\n", pool->fc_addr);
+
+   npa_dump("W6: ptr_start\t\t0x%"PRIx64"\n", pool->ptr_start);
+
+   npa_dump("W7: ptr_end\t\t0x%"PRIx64"\n", pool->ptr_end);
+   npa_dump("W8: err_int\t\t%d\nW8: err_int_ena\t\t%d",
+   pool->err_int, pool->err_int_ena);
+   npa_dump("W8: thresh_int\t\t%d", pool->thresh_int);
+
+   npa_dump("W8: thresh_int_ena\t%d\nW8: thresh_up\t\t%d",
+   pool->thresh_int_ena, pool->thresh_up);
+   npa_dump("W8: thresh_qint_idx\t%d\nW8: err_qint_idx\t%d",
+   pool->thresh_qint_idx, pool->err_qint_idx);
+}
+
+static inline void
+npa_lf_aura_dump(struct npa_aura_s *aura)
+{
+   npa_dump("W0: Pool addr\t\t0x%"PRIx64"\n", aura->pool_addr);
+
+   npa_dump("W1: ena\t\t\t%d\nW1: pool caching\t%d\nW1: pool way mask\t%d",
+   aura->ena, aura->pool_caching, aura->pool_way_mask);
+   npa_dump("W1: avg con\t\t%d\nW1: pool drop ena\t%d",
+   aura->avg_con, aura->pool_drop_ena);
+   npa_dump("W1: aura drop ena\t%d", aura->aura_drop_ena);
+   npa_dump("W1: bp_ena\t\t%d\nW1: aura drop\t\t%d\nW1: aura shift\t\t%d",
+   aura->bp_ena, aura->aura_drop, aura->shift);
+   npa_dump("W1: avg_level\t\t%d\n", aura->avg_level);
+
+   npa_dump("W2: count\t\t%"PRIx64"\nW2: nix0_bpid\t\t%d",
+   (uint64_t)aura->count, aura->nix0_bpid);
+   npa_dump("W2: nix1_bpid\t\t%d", aura->nix

[dpdk-dev] [PATCH v2 21/27] mempool/octeontx2: add mempool alloc op

[jerinj]

From: Jerin Jacob 

The DPDK mempool allocation reserves a single HW AURA
and POOL in 1:1 map mode. Upon reservation, SW programs the slow path
operations such as allocate stack memory for DMA and
bunch HW configurations to respective HW blocks.

Cc: Olivier Matz 

Signed-off-by: Jerin Jacob 
---
 drivers/mempool/octeontx2/Makefile   |   1 +
 drivers/mempool/octeontx2/meson.build|   3 +-
 drivers/mempool/octeontx2/otx2_mempool_ops.c | 246 +++
 3 files changed, 249 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mempool/octeontx2/otx2_mempool_ops.c

diff --git a/drivers/mempool/octeontx2/Makefile 
b/drivers/mempool/octeontx2/Makefile
index b86d469f4..b3568443e 100644
--- a/drivers/mempool/octeontx2/Makefile
+++ b/drivers/mempool/octeontx2/Makefile
@@ -28,6 +28,7 @@ LIBABIVER := 1
 # all source are stored in SRCS-y
 #
 SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \
+   otx2_mempool_ops.c  \
otx2_mempool.c  \
otx2_mempool_irq.c  \
otx2_mempool_debug.c
diff --git a/drivers/mempool/octeontx2/meson.build 
b/drivers/mempool/octeontx2/meson.build
index ab306b729..9fde40f0e 100644
--- a/drivers/mempool/octeontx2/meson.build
+++ b/drivers/mempool/octeontx2/meson.build
@@ -2,7 +2,8 @@
 # Copyright(C) 2019 Marvell International Ltd.
 #
 
-sources = files('otx2_mempool.c',
+sources = files('otx2_mempool_ops.c',
+   'otx2_mempool.c',
'otx2_mempool_irq.c',
'otx2_mempool_debug.c'
)
diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c 
b/drivers/mempool/octeontx2/otx2_mempool_ops.c
new file mode 100644
index 0..0e7b7a77c
--- /dev/null
+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include 
+#include 
+
+#include "otx2_mempool.h"
+
+static int
+npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id,
+ struct npa_aura_s *aura, struct npa_pool_s *pool)
+{
+   struct npa_aq_enq_req *aura_init_req, *pool_init_req;
+   struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp;
+   struct otx2_mbox_dev *mdev = &mbox->dev[0];
+   int rc, off;
+
+   aura_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
+
+   aura_init_req->aura_id = aura_id;
+   aura_init_req->ctype = NPA_AQ_CTYPE_AURA;
+   aura_init_req->op = NPA_AQ_INSTOP_INIT;
+   memcpy(&aura_init_req->aura, aura, sizeof(*aura));
+
+   pool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);
+
+   pool_init_req->aura_id = aura_id;
+   pool_init_req->ctype = NPA_AQ_CTYPE_POOL;
+   pool_init_req->op = NPA_AQ_INSTOP_INIT;
+   memcpy(&pool_init_req->pool, pool, sizeof(*pool));
+
+   otx2_mbox_msg_send(mbox, 0);
+   rc = otx2_mbox_wait_for_rsp(mbox, 0);
+   if (rc < 0)
+   return rc;
+
+   off = mbox->rx_start +
+   RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
+   aura_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
+   off = mbox->rx_start + aura_init_rsp->hdr.next_msgoff;
+   pool_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
+
+   if (rc == 2 && aura_init_rsp->hdr.rc == 0 && pool_init_rsp->hdr.rc == 0)
+   return 0;
+   else
+   return NPA_LF_ERR_AURA_POOL_INIT;
+}
+
+static inline char*
+npa_lf_stack_memzone_name(struct otx2_npa_lf *lf, int pool_id, char *name)
+{
+   snprintf(name, RTE_MEMZONE_NAMESIZE, "otx2_npa_stack_%x_%d",
+   lf->pf_func, pool_id);
+
+   return name;
+}
+
+static inline const struct rte_memzone *
+npa_lf_stack_dma_alloc(struct otx2_npa_lf *lf, char *name,
+  int pool_id, size_t size)
+{
+   return rte_memzone_reserve_aligned(
+   npa_lf_stack_memzone_name(lf, pool_id, name), size, 0,
+   RTE_MEMZONE_IOVA_CONTIG, OTX2_ALIGN);
+}
+
+static inline int
+bitmap_ctzll(uint64_t slab)
+{
+   if (slab == 0)
+   return 0;
+
+   return __builtin_ctzll(slab);
+}
+
+static int
+npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const uint32_t block_size,
+   const uint32_t block_count, struct npa_aura_s *aura,
+   struct npa_pool_s *pool, uint64_t *aura_handle)
+{
+   int rc, aura_id, pool_id, stack_size, alloc_size;
+   char name[RTE_MEMZONE_NAMESIZE];
+   const struct rte_memzone *mz;
+   uint64_t slab;
+   uint32_t pos;
+
+   /* Sanity check */
+   if (!lf || !block_size || !block_count ||
+   !pool || !aura || !aura_handle)
+   return NPA_LF_ERR_PARAM;
+
+   /* Block size should be cache line aligned and in range of 128B-128KB */
+   if (block_size % OTX2_ALIGN || block_size < 128 ||
+   block_size > 128 * 1024)
+   return NPA_LF_ERR_INVALID_BLOCK_SZ;

[dpdk-dev] [PATCH v2 25/27] mempool/octeontx2: add optimized dequeue operation for arm64

[jerinj]

From: Pavan Nikhilesh 

This patch adds an optimized arm64 instruction based routine to leverage
CPU pipeline characteristics of octeontx2. The theme is to fill the
pipeline with CASP operations as much HW can do so that HW can do alloc()
HW ops in full throttle.

Cc: Olivier Matz 
Cc: Aaron Conole 

Signed-off-by: Pavan Nikhilesh 
Signed-off-by: Jerin Jacob 
Signed-off-by: Vamsi Attunuru 
---
 drivers/mempool/octeontx2/otx2_mempool_ops.c | 291 +++
 1 file changed, 291 insertions(+)

diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c 
b/drivers/mempool/octeontx2/otx2_mempool_ops.c
index c59bd73c0..e6737abda 100644
--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c
+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c
@@ -37,6 +37,293 @@ npa_lf_aura_op_alloc_one(const int64_t wdata, int64_t * 
const addr,
return -ENOENT;
 }
 
+#if defined(RTE_ARCH_ARM64)
+static __rte_noinline int
+npa_lf_aura_op_search_alloc(const int64_t wdata, int64_t * const addr,
+   void **obj_table, unsigned int n)
+{
+   uint8_t i;
+
+   for (i = 0; i < n; i++) {
+   if (obj_table[i] != NULL)
+   continue;
+   if (npa_lf_aura_op_alloc_one(wdata, addr, obj_table, i))
+   return -ENOENT;
+   }
+
+   return 0;
+}
+
+static  __attribute__((optimize("-O3"))) __rte_noinline int __hot
+npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,
+ unsigned int n, void **obj_table)
+{
+   const __uint128_t wdata128 = ((__uint128_t)wdata << 64) | wdata;
+   uint64x2_t failed = vdupq_n_u64(~0);
+
+   switch (n) {
+   case 32:
+   {
+   __uint128_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
+   __uint128_t t10, t11;
+
+   asm volatile (
+   ".cpu  generic+lse\n"
+   "casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t8], %H[t8], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t9], %H[t9], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t10], %H[t10], %[wdata], %H[wdata], [%[loc]]\n"
+   "casp %[t11], %H[t11], %[wdata], %H[wdata], [%[loc]]\n"
+   "fmov d16, %[t0]\n"
+   "fmov v16.D[1], %H[t0]\n"
+   "casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n"
+   "fmov d17, %[t1]\n"
+   "fmov v17.D[1], %H[t1]\n"
+   "casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\n"
+   "fmov d18, %[t2]\n"
+   "fmov v18.D[1], %H[t2]\n"
+   "casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\n"
+   "fmov d19, %[t3]\n"
+   "fmov v19.D[1], %H[t3]\n"
+   "casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\n"
+   "and %[failed].16B, %[failed].16B, v16.16B\n"
+   "and %[failed].16B, %[failed].16B, v17.16B\n"
+   "and %[failed].16B, %[failed].16B, v18.16B\n"
+   "and %[failed].16B, %[failed].16B, v19.16B\n"
+   "fmov d20, %[t4]\n"
+   "fmov v20.D[1], %H[t4]\n"
+   "fmov d21, %[t5]\n"
+   "fmov v21.D[1], %H[t5]\n"
+   "fmov d22, %[t6]\n"
+   "fmov v22.D[1], %H[t6]\n"
+   "fmov d23, %[t7]\n"
+   "fmov v23.D[1], %H[t7]\n"
+   "and %[failed].16B, %[failed].16B, v20.16B\n"
+   "and %[failed].16B, %[failed].16B, v21.16B\n"
+   "and %[failed].16B, %[failed].16B, v22.16B\n"
+   "and %[failed].16B, %[failed].16B, v23.16B\n"
+   "st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\n"
+   "st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\n"
+   "fmov d16, %[t8]\n"
+   "fmov v16.D[1], %H[t8]\n"
+   "fmov d17, %[t9]\n"
+   "fmov v17.D[1], %H[t9]\n"
+   "fmov d18, %[t10]\n"
+   "fmov v18.D[1], %H[t10]\n"
+   "fmov d19, %[t11]\n"
+   "fmov v19.D[1], %H[t11]\n"
+   "and %[failed].16B, %[failed].16B, v16.16B\n"
+   "and %[failed].16B, %[failed].16B, v17.16B\n"
+   "and %[failed].16B, %[failed].16B, v18.16B\n"
+   "and %[failed].16B, %[failed].16B, v19.16B\n"
+   "fmov d20, %[t0]\n"
+   "fmov v20.D[1], %H[t0]\n"
+   "fmov d21, %[t1]\n"
+   "fmov v21.D[1], %H[t1]\n"
+   "fmov

[dpdk-dev] [PATCH v2 24/27] mempool/octeontx2: add fast path mempool ops

[jerinj]

From: Jerin Jacob 

Add enqueue and dequeue mempool fastpath operations.

Cc: Olivier Matz 

Signed-off-by: Jerin Jacob 
Signed-off-by: Pavan Nikhilesh 
---
 drivers/mempool/octeontx2/otx2_mempool_ops.c | 57 
 1 file changed, 57 insertions(+)

diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c 
b/drivers/mempool/octeontx2/otx2_mempool_ops.c
index 966b7d7f1..c59bd73c0 100644
--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c
+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c
@@ -7,6 +7,61 @@
 
 #include "otx2_mempool.h"
 
+static int __hot
+otx2_npa_enq(struct rte_mempool *mp, void * const *obj_table, unsigned int n)
+{
+   unsigned int index; const uint64_t aura_handle = mp->pool_id;
+   const uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);
+   const uint64_t addr = npa_lf_aura_handle_to_base(aura_handle) +
+NPA_LF_AURA_OP_FREE0;
+
+   for (index = 0; index < n; index++)
+   otx2_store_pair((uint64_t)obj_table[index], reg, addr);
+
+   return 0;
+}
+
+static __rte_noinline int
+npa_lf_aura_op_alloc_one(const int64_t wdata, int64_t * const addr,
+void **obj_table, uint8_t i)
+{
+   uint8_t retry = 4;
+
+   do {
+   obj_table[i] = (void *)otx2_atomic64_add_nosync(wdata, addr);
+   if (obj_table[i] != NULL)
+   return 0;
+
+   } while (retry--);
+
+   return -ENOENT;
+}
+
+static inline int __hot
+otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)
+{
+   const int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);
+   unsigned int index;
+   uint64_t obj;
+
+   int64_t * const addr = (int64_t * const)
+   (npa_lf_aura_handle_to_base(mp->pool_id) +
+   NPA_LF_AURA_OP_ALLOCX(0));
+   for (index = 0; index < n; index++, obj_table++) {
+   obj = npa_lf_aura_op_alloc_one(wdata, addr, obj_table, 0);
+   if (obj == 0) {
+   for (; index > 0; index--) {
+   obj_table--;
+   otx2_npa_enq(mp, obj_table, 1);
+   }
+   return -ENOENT;
+   }
+   *obj_table = (void *)obj;
+   }
+
+   return 0;
+}
+
 static unsigned int
 otx2_npa_get_count(const struct rte_mempool *mp)
 {
@@ -404,9 +459,11 @@ static struct rte_mempool_ops otx2_npa_ops = {
.name = "octeontx2_npa",
.alloc = otx2_npa_alloc,
.free = otx2_npa_free,
+   .enqueue = otx2_npa_enq,
.get_count = otx2_npa_get_count,
.calc_mem_size = otx2_npa_calc_mem_size,
.populate = otx2_npa_populate,
+   .dequeue = otx2_npa_deq,
 };
 
 MEMPOOL_REGISTER_OPS(otx2_npa_ops);
-- 
2.21.0

[dpdk-dev] [PATCH v2 26/27] mempool/octeontx2: add devargs for max pool selection

[jerinj]

From: Jerin Jacob 

The maximum number of mempools per application needs to be configured
on HW during mempool driver initialization. HW can support up to 1M
mempools, Since each mempool costs set of HW resources, the max_pools
devargs parameter is being introduced to configure the number of
mempools required for the application.
For example:

-w 0002:02:00.0,max_pools=512

With the above configuration, the driver will set up only 512 mempools
for the given application to save HW resources.

Signed-off-by: Jerin Jacob 
Signed-off-by: Harman Kalra 
---
 drivers/mempool/octeontx2/otx2_mempool.c | 41 +++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/drivers/mempool/octeontx2/otx2_mempool.c 
b/drivers/mempool/octeontx2/otx2_mempool.c
index 1bcb86cf4..ff7fcac85 100644
--- a/drivers/mempool/octeontx2/otx2_mempool.c
+++ b/drivers/mempool/octeontx2/otx2_mempool.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -142,6 +143,42 @@ otx2_aura_size_to_u32(uint8_t val)
return 1 << (val + 6);
 }
 
+static int
+parse_max_pools(const char *key, const char *value, void *extra_args)
+{
+   RTE_SET_USED(key);
+   uint32_t val;
+
+   val = atoi(value);
+   if (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128))
+   val = 128;
+   if (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M))
+   val = BIT_ULL(20);
+
+   *(uint8_t *)extra_args = rte_log2_u32(val) - 6;
+   return 0;
+}
+
+#define OTX2_MAX_POOLS "max_pools"
+
+static uint8_t
+otx2_parse_aura_size(struct rte_devargs *devargs)
+{
+   uint8_t aura_sz = NPA_AURA_SZ_128;
+   struct rte_kvargs *kvlist;
+
+   if (devargs == NULL)
+   goto exit;
+   kvlist = rte_kvargs_parse(devargs->args, NULL);
+   if (kvlist == NULL)
+   goto exit;
+
+   rte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz);
+   rte_kvargs_free(kvlist);
+exit:
+   return aura_sz;
+}
+
 static inline int
 npa_lf_attach(struct otx2_mbox *mbox)
 {
@@ -234,7 +271,7 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void 
*otx2_dev)
if (rc)
goto npa_detach;
 
-   aura_sz = NPA_AURA_SZ_128;
+   aura_sz = otx2_parse_aura_size(pci_dev->device.devargs);
nr_pools = otx2_aura_size_to_u32(aura_sz);
 
lf = &dev->npalf;
@@ -397,3 +434,5 @@ static struct rte_pci_driver pci_npa = {
 RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);
 RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);
 RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, "vfio-pci");
+RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2,
+ OTX2_MAX_POOLS "=<128-1048576>");
-- 
2.21.0

[dpdk-dev] [PATCH v2 27/27] doc: add Marvell OCTEON TX2 mempool documentation

[jerinj]

From: Jerin Jacob 

Add Marvell OCTEON TX2 mempool documentation.

This patch also updates the MAINTAINERS file and
updates shared library versions in release_19_08.rst.

Cc: John McNamara 
Cc: Thomas Monjalon 

Signed-off-by: Jerin Jacob 
Signed-off-by: Vivek Sharma 
Signed-off-by: Vamsi Attunuru 
Signed-off-by: Nithin Dabilpuram 
---
 MAINTAINERS| 10 +++
 doc/guides/mempool/index.rst   |  1 +
 doc/guides/mempool/octeontx2.rst   | 90 ++
 doc/guides/platform/octeontx2.rst  |  2 +
 doc/guides/rel_notes/release_19_08.rst |  2 +
 5 files changed, 105 insertions(+)
 create mode 100644 doc/guides/mempool/octeontx2.rst

diff --git a/MAINTAINERS b/MAINTAINERS
index 15d0829c5..74ac6d41f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -444,6 +444,16 @@ M: Artem V. Andreev 
 M: Andrew Rybchenko 
 F: drivers/mempool/bucket/
 
+Marvell OCTEON TX2
+M: Jerin Jacob 
+M: Nithin Dabilpuram 
+M: Vamsi Attunuru 
+F: drivers/common/octeontx2/
+F: drivers/mempool/octeontx2/
+F: doc/guides/platform/img/octeontx2_*
+F: doc/guides/platform/octeontx2.rst
+F: doc/guides/mempool/octeontx2.rst
+
 
 Bus Drivers
 ---
diff --git a/doc/guides/mempool/index.rst b/doc/guides/mempool/index.rst
index 2ccf91633..756610264 100644
--- a/doc/guides/mempool/index.rst
+++ b/doc/guides/mempool/index.rst
@@ -12,3 +12,4 @@ application through the mempool API.
 :numbered:
 
 octeontx
+octeontx2
diff --git a/doc/guides/mempool/octeontx2.rst b/doc/guides/mempool/octeontx2.rst
new file mode 100644
index 0..2c9a0953b
--- /dev/null
+++ b/doc/guides/mempool/octeontx2.rst
@@ -0,0 +1,90 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+Copyright(c) 2019 Marvell International Ltd.
+
+OCTEON TX2 NPA Mempool Driver
+=
+
+The OCTEON TX2 NPA PMD (**librte_mempool_octeontx2**) provides mempool
+driver support for the integrated mempool device found in **Marvell OCTEON 
TX2** SoC family.
+
+More information about OCTEON TX2 SoC can be found at `Marvell Official Website
+`_.
+
+Features
+
+
+OCTEON TX2 NPA PMD supports:
+
+- Up to 128 NPA LFs
+- 1M Pools per LF
+- HW mempool manager
+- Ethdev Rx buffer allocation in HW to save CPU cycles in the Rx path.
+- Ethdev Tx buffer recycling in HW to save CPU cycles in the Tx path.
+
+Prerequisites and Compilation procedure
+---
+
+   See :doc:`../platform/octeontx2` for setup information.
+
+Pre-Installation Configuration
+--
+
+Compile time Config Options
+~~~
+
+The following option can be modified in the ``config`` file.
+
+- ``CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL`` (default ``y``)
+
+  Toggle compilation of the ``librte_mempool_octeontx2`` driver.
+
+Runtime Config Options
+~~
+
+- ``Maximum number of mempools per application`` (default ``128``)
+
+  The maximum number of mempools per application needs to be configured on
+  HW during mempool driver initialization. HW can support up to 1M mempools,
+  Since each mempool costs set of HW resources, the ``max_pools`` ``devargs``
+  parameter is being introduced to configure the number of mempools required
+  for the application.
+  For example::
+
+-w 0002:02:00.0,max_pools=512
+
+  With the above configuration, the driver will set up only 512 mempools for
+  the given application to save HW resources.
+
+.. note::
+
+   Since this configuration is per application, the end user needs to
+   provide ``max_pools`` parameter to the first PCIe device probed by the given
+   application.
+
+Debugging Options
+~
+
+.. _table_octeontx2_mempool_debug_options:
+
+.. table:: OCTEON TX2 mempool debug options
+
+   +---++---+
+   | # | Component  | EAL log command   |
+   +===++===+
+   | 1 | NPA| --log-level='pmd\.mempool.octeontx2,8'|
+   +---++---+
+
+Standalone mempool device
+~
+
+   The ``usertools/dpdk-devbind.py`` script shall enumerate all the mempool 
devices
+   available in the system. In order to avoid, the end user to bind the mempool
+   device prior to use ethdev and/or eventdev device, the respective driver
+   configures an NPA LF and attach to the first probed ethdev or eventdev 
device.
+   In case, if end user need to run mempool as a standalone device
+   (without ethdev or eventdev), end user needs to bind a mempool device using
+   ``usertools/dpdk-devbind.py``
+
+   Example command to run ``mempool_autotest`` test with standalone OCTEONTX2 
NPA device::
+
+ echo "mempool_autotest" | build/app/test -c 0xf0 
--mbuf-pool-ops-name="octeontx2_npa"
diff --git a/doc/gui