[coreboot] r3058 - in trunk/util: flashrom lxbios mptable

[svn]

Author: stepan
Date: 2008-01-18 17:17:44 +0100 (Fri, 18 Jan 2008)
New Revision: 3058

Added:
   trunk/util/flashrom/cbtable.c
   trunk/util/flashrom/coreboot_tables.h
   trunk/util/lxbios/coreboot_tables.h
Removed:
   trunk/util/flashrom/lbtable.c
   trunk/util/flashrom/linuxbios_tables.h
   trunk/util/lxbios/linuxbios_tables.h
Modified:
   trunk/util/flashrom/Makefile
   trunk/util/lxbios/Makefile
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/mptable/mptable.c
Log:
rename linuxbios_* files in utils repository.
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/Makefile
===
--- trunk/util/flashrom/Makefile2008-01-18 16:16:45 UTC (rev 3057)
+++ trunk/util/flashrom/Makefile2008-01-18 16:17:44 UTC (rev 3058)
@@ -23,7 +23,7 @@
 OBJS = chipset_enable.o board_enable.o udelay.o jedec.o sst28sf040.o \
am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
-   sst_fwhub.o layout.o lbtable.o flashchips.o flashrom.o \
+   sst_fwhub.o layout.o cbtable.o flashchips.o flashrom.o \
sharplhf00l04.o w29ee011.o spi.o
 
 all: pciutils dep $(PROGRAM)

Copied: trunk/util/flashrom/cbtable.c (from rev 3056, 
trunk/util/flashrom/lbtable.c)
===
--- trunk/util/flashrom/cbtable.c   (rev 0)
+++ trunk/util/flashrom/cbtable.c   2008-01-18 16:17:44 UTC (rev 3058)
@@ -0,0 +1,218 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2002 Steven James <[EMAIL PROTECTED]>
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <[EMAIL PROTECTED]> for Linux Networx)
+ * Copyright (C) 2006-2007 coresystems GmbH
+ * (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "flash.h"
+#include "coreboot_tables.h"
+
+char *lb_part = NULL, *lb_vendor = NULL;
+
+static unsigned long compute_checksum(void *addr, unsigned long length)
+{
+   uint8_t *ptr;
+   volatile union {
+   uint8_t byte[2];
+   uint16_t word;
+   } value;
+   unsigned long sum;
+   unsigned long i;
+
+   /* In the most straight forward way possible,
+* compute an ip style checksum.
+*/
+   sum = 0;
+   ptr = addr;
+   for (i = 0; i < length; i++) {
+   unsigned long value;
+   value = ptr[i];
+   if (i & 1) {
+   value <<= 8;
+   }
+   /* Add the new value */
+   sum += value;
+   /* Wrap around the carry */
+   if (sum > 0x) {
+   sum = (sum + (sum >> 16)) & 0x;
+   }
+   }
+   value.byte[0] = sum & 0xff;
+   value.byte[1] = (sum >> 8) & 0xff;
+
+   return (~value.word) & 0x;
+}
+
+#define for_each_lbrec(head, rec) \
+   for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
+   (((char *)rec) < (((char *)head) + sizeof(*head) + 
head->table_bytes))  && \
+   (rec->size >= 1) && \
+   char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) 
+ head->table_bytes)); \
+   rec = (struct lb_record *)(((char *)rec) + rec->size))
+
+static int count_lb_records(struct lb_header *head)
+{
+   struct lb_record *rec;
+   int count;
+
+   count = 0;
+   for_each_lbrec(head, rec) {
+   count++;
+   }
+
+   return count;
+}
+
+static struct lb_header *find_lb_table(void *base, unsigned long start,
+  unsigned long end)
+{
+   unsigned long addr;
+
+   /* For now be stupid */
+   for (addr = start; addr < end; addr += 16) {
+   struct lb_header *head =
+   (struct lb_header *)(((char *)base) + addr);
+   struct lb_record *recs =
+   (struct lb_record *)(((char *)base) + addr + sizeof(*head));
+  

[coreboot] r3056 - in trunk/util: getpir superiotool

[svn]

Author: stepan
Date: 2008-01-18 16:34:24 +0100 (Fri, 18 Jan 2008)
New Revision: 3056

Modified:
   trunk/util/getpir/README
   trunk/util/getpir/checkpir.c
   trunk/util/getpir/getpir.c
   trunk/util/superiotool/README
   trunk/util/superiotool/superiotool.8
Log:
util/ renames
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/getpir/README
===
--- trunk/util/getpir/README2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/README2008-01-18 15:34:24 UTC (rev 3056)
@@ -6,14 +6,14 @@
 
 INSTALL:
 
-edit Makefile, define the root to Linuxbios tree
+edit Makefile, define the root to coreboot tree
 make
 
 USAGE:
 
 ./getpir
 
-Will dump irq table to the file called irq_tables.c, ready to use with 
Linuxbios. Just move the 
+Will dump irq table to the file called irq_tables.c, ready to use with 
coreboot. Just move the 
 file to corresponding place in the linux bios tree.
 
 

Modified: trunk/util/getpir/checkpir.c
===
--- trunk/util/getpir/checkpir.c2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/checkpir.c2008-01-18 15:34:24 UTC (rev 3056)
@@ -1,5 +1,5 @@
 /* checkpir.c : This software is released under GPL
- * For LinuxBIOS use only
+ * For coreboot use only
  * Aug 26 2001 , Nikolai Vladychevski, <[EMAIL PROTECTED]>
  */
 
@@ -20,7 +20,7 @@
printf("(no other tests are done)\n");
 
if (!sum) {
-   printf("Checksum for IRQ Routing table is ok. You can use 
irq_tables.c in LinuxBIOS now.\n");
+   printf("Checksum for IRQ Routing table is ok. You can use 
irq_tables.c in coreboot now.\n");
} else {
newsum = rt->checksum - sum;
printf("BAD CHECKSUM for IRQ Routing table \n");

Modified: trunk/util/getpir/getpir.c
===
--- trunk/util/getpir/getpir.c  2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/getpir.c  2008-01-18 15:34:24 UTC (rev 3056)
@@ -1,5 +1,5 @@
 /* getpir.c : This software is released under GPL
- * For LinuxBIOS use only
+ * For coreboot use only
  * Aug 26 2001 , Nikolai Vladychevski, <[EMAIL PROTECTED]>
  * 2007.04.09 Jeremy Jackson <[EMAIL PROTECTED]>
  * updated for amd64 and general 64 bit portability
@@ -78,7 +78,7 @@
 
close(fd_mem);
 
-   printf("Done, you can move the file to the LinuxBIOS tree now.\n");
+   printf("Done, you can move the file to the coreboot tree now.\n");
 
return 0;
 }

Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/superiotool/README   2008-01-18 15:34:24 UTC (rev 3056)
@@ -11,14 +11,14 @@
  - dump all register contents of the Super I/O chip, together with the
default values as per datasheet (to make comparing the values easy).
 
-It is mainly used for LinuxBIOS development purposes (see linuxbios.org
-for details on LinuxBIOS), but it may also be useful for other things.
+It is mainly used for coreboot development purposes (see coreboot.org
+for details on coreboot), but it may also be useful for other things.
 
 
 Installation
 
 
- $ svn co svn://linuxbios.org/repos/trunk/util/superiotool
+ $ svn co svn://coreboot.org/repos/trunk/util/superiotool
 
  $ cd superiotool
 
@@ -54,21 +54,21 @@
 Supported Super I/O Chips
 -
 
-Please see http://linuxbios.org/Superiotool#Supported_devices.
+Please see http://coreboot.org/Superiotool#Supported_devices.
 
 There's also a collection of sample register dumps from various Super I/O
 chips on that page. Please send further register dumps (either from a
-proprietary BIOS and/or from LinuxBIOS) to the LinuxBIOS mailing list
-(http://linuxbios.org/Mailinglist).
+proprietary BIOS and/or from coreboot) to the coreboot mailing list
+(http://coreboot.org/Mailinglist).
 
 
 Website and Mailing List
 
 
-The main website is http://linuxbios.org/Superiotool.
+The main website is http://coreboot.org/Superiotool.
 
 For additional information, patches, and discussions, please join the
-LinuxBIOS mailing list at http://linuxbios.org/Mailinglist, where most
+coreboot mailing list at http://coreboot.org/Mailinglist, where most
 superiotool developers are subscribed.
 
 

Modified: trunk/util/superiotool/superiotool.8
===
--- trunk/util/superiotool/superiotool.82008-01-18 15:33:49 UTC (rev 
3055)
+++ trunk/util/superiotool/superiotool.82008-01-18 15:34:24 UTC (rev 
3056)
@@ -14,12 +14,12 @@
  * dump all register contents of the Super I/O chip, t

[coreboot] r3056 - in trunk/util: getpir superiotool

[svn]

Author: stepan
Date: 2008-01-18 16:34:24 +0100 (Fri, 18 Jan 2008)
New Revision: 3056

Modified:
   trunk/util/getpir/README
   trunk/util/getpir/checkpir.c
   trunk/util/getpir/getpir.c
   trunk/util/superiotool/README
   trunk/util/superiotool/superiotool.8
Log:
util/ renames
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/getpir/README
===
--- trunk/util/getpir/README2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/README2008-01-18 15:34:24 UTC (rev 3056)
@@ -6,14 +6,14 @@
 
 INSTALL:
 
-edit Makefile, define the root to Linuxbios tree
+edit Makefile, define the root to coreboot tree
 make
 
 USAGE:
 
 ./getpir
 
-Will dump irq table to the file called irq_tables.c, ready to use with 
Linuxbios. Just move the 
+Will dump irq table to the file called irq_tables.c, ready to use with 
coreboot. Just move the 
 file to corresponding place in the linux bios tree.
 
 

Modified: trunk/util/getpir/checkpir.c
===
--- trunk/util/getpir/checkpir.c2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/checkpir.c2008-01-18 15:34:24 UTC (rev 3056)
@@ -1,5 +1,5 @@
 /* checkpir.c : This software is released under GPL
- * For LinuxBIOS use only
+ * For coreboot use only
  * Aug 26 2001 , Nikolai Vladychevski, <[EMAIL PROTECTED]>
  */
 
@@ -20,7 +20,7 @@
printf("(no other tests are done)\n");
 
if (!sum) {
-   printf("Checksum for IRQ Routing table is ok. You can use 
irq_tables.c in LinuxBIOS now.\n");
+   printf("Checksum for IRQ Routing table is ok. You can use 
irq_tables.c in coreboot now.\n");
} else {
newsum = rt->checksum - sum;
printf("BAD CHECKSUM for IRQ Routing table \n");

Modified: trunk/util/getpir/getpir.c
===
--- trunk/util/getpir/getpir.c  2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/getpir/getpir.c  2008-01-18 15:34:24 UTC (rev 3056)
@@ -1,5 +1,5 @@
 /* getpir.c : This software is released under GPL
- * For LinuxBIOS use only
+ * For coreboot use only
  * Aug 26 2001 , Nikolai Vladychevski, <[EMAIL PROTECTED]>
  * 2007.04.09 Jeremy Jackson <[EMAIL PROTECTED]>
  * updated for amd64 and general 64 bit portability
@@ -78,7 +78,7 @@
 
close(fd_mem);
 
-   printf("Done, you can move the file to the LinuxBIOS tree now.\n");
+   printf("Done, you can move the file to the coreboot tree now.\n");
 
return 0;
 }

Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-18 15:33:49 UTC (rev 3055)
+++ trunk/util/superiotool/README   2008-01-18 15:34:24 UTC (rev 3056)
@@ -11,14 +11,14 @@
  - dump all register contents of the Super I/O chip, together with the
default values as per datasheet (to make comparing the values easy).
 
-It is mainly used for LinuxBIOS development purposes (see linuxbios.org
-for details on LinuxBIOS), but it may also be useful for other things.
+It is mainly used for coreboot development purposes (see coreboot.org
+for details on coreboot), but it may also be useful for other things.
 
 
 Installation
 
 
- $ svn co svn://linuxbios.org/repos/trunk/util/superiotool
+ $ svn co svn://coreboot.org/repos/trunk/util/superiotool
 
  $ cd superiotool
 
@@ -54,21 +54,21 @@
 Supported Super I/O Chips
 -
 
-Please see http://linuxbios.org/Superiotool#Supported_devices.
+Please see http://coreboot.org/Superiotool#Supported_devices.
 
 There's also a collection of sample register dumps from various Super I/O
 chips on that page. Please send further register dumps (either from a
-proprietary BIOS and/or from LinuxBIOS) to the LinuxBIOS mailing list
-(http://linuxbios.org/Mailinglist).
+proprietary BIOS and/or from coreboot) to the coreboot mailing list
+(http://coreboot.org/Mailinglist).
 
 
 Website and Mailing List
 
 
-The main website is http://linuxbios.org/Superiotool.
+The main website is http://coreboot.org/Superiotool.
 
 For additional information, patches, and discussions, please join the
-LinuxBIOS mailing list at http://linuxbios.org/Mailinglist, where most
+coreboot mailing list at http://coreboot.org/Mailinglist, where most
 superiotool developers are subscribed.
 
 

Modified: trunk/util/superiotool/superiotool.8
===
--- trunk/util/superiotool/superiotool.82008-01-18 15:33:49 UTC (rev 
3055)
+++ trunk/util/superiotool/superiotool.82008-01-18 15:34:24 UTC (rev 
3056)
@@ -14,12 +14,12 @@
  * dump all register contents of the Super I/O chip, t

[coreboot] r3054 - trunk/util/flashrom

[svn]

Author: stepan
Date: 2008-01-18 16:33:10 +0100 (Fri, 18 Jan 2008)
New Revision: 3054

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/board_enable.c
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
   trunk/util/flashrom/layout.c
   trunk/util/flashrom/lbtable.c
   trunk/util/flashrom/linuxbios_tables.h
   trunk/util/flashrom/m29f400bt.c
Log:
for some reasons the externals did not get committed.

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/README  2008-01-18 15:33:10 UTC (rev 3054)
@@ -2,7 +2,7 @@
 Flashrom README
 ---
 
-This is the universal (LinuxBIOS) flash utility.
+This is the universal (coreboot) flash utility.
 
 Build Requirements
 --
@@ -38,17 +38,17 @@
  is that flash info is dumped and the flash chip is set to writable.
 
 
-LinuxBIOS Table and Mainboard Identification
+coreboot Table and Mainboard Identification
 
 
-Flashrom reads the LinuxBIOS table to determine the current mainboard
-(parse DMI as well in future?). If no LinuxBIOS table could be read
+Flashrom reads the coreboot table to determine the current mainboard
+(parse DMI as well in future?). If no coreboot table could be read
 or if you want to override these values, you can specify -m, e.g.:
 
   flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom
 
 The following boards require the specification of the board name, if
-no LinuxBIOS table is found:
+no coreboot table is found:
 
 * IWILL DK8-HTX: use -m iwill:dk8_htx
 * Agami Aruma: use -m AGAMI:ARUMA

Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c  2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/board_enable.c  2008-01-18 15:33:10 UTC (rev 3054)
@@ -148,7 +148,7 @@
 /**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
- * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered 
there.
+ * We don't need to do this when using coreboot, GPIO15 is never lowered there.
  */
 static int board_via_epia_m(const char *name)
 {
@@ -368,7 +368,7 @@
uint16_t second_card_vendor;
uint16_t second_card_device;
 
-   /* The vendor / part name from the LinuxBIOS table. */
+   /* The vendor / part name from the coreboot table. */
const char *lb_vendor;
const char *lb_part;
 
@@ -407,10 +407,10 @@
 };
 
 /**
- * Match boards on LinuxBIOS table gathered vendor and part name.
+ * Match boards on coreboot table gathered vendor and part name.
  * Require main PCI IDs to match too as extra safety.
  */
-static struct board_pciid_enable *board_match_linuxbios_name(const char 
*vendor, const char *part)
+static struct board_pciid_enable *board_match_coreboot_name(const char 
*vendor, const char *part)
 {
struct board_pciid_enable *board = board_pciid_enables;
 
@@ -478,7 +478,7 @@
int ret = 0;
 
if (vendor && part)
-   board = board_match_linuxbios_name(vendor, part);
+   board = board_match_coreboot_name(vendor, part);
 
if (!board)
board = board_match_pci_card_ids();

Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/flash.h 2008-01-18 15:33:10 UTC (rev 3054)
@@ -286,7 +286,7 @@
 int handle_romentries(uint8_t *buffer, uint8_t *content);
 
 /* lbtable.c */
-int linuxbios_init(void);
+int coreboot_init(void);
 extern char *lb_part, *lb_vendor;
 
 /* spi.c */
@@ -329,7 +329,7 @@
 int block_erase_m29f400bt(volatile uint8_t *bios,
 volatile uint8_t *dst);
 int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
-int write_linuxbios_m29f400bt(struct flashchip *flash, uint8_t *buf);
+int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf);
 void toggle_ready_m29f400bt(volatile uint8_t *dst);
 void data_polling_m29f400bt(volatile uint8_t *dst, uint8_t data);
 void protect_m29f400bt(volatile uint8_t *bios);

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/flashchips.c2008-01-18 15:33:10 UTC (rev 3054)
@@ -47,7 +47,7 @@
{"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 102

[coreboot] r97 - buildrom-devel/packages

[svn]

Author: jcrouse
Date: 2008-01-18 18:01:03 +0100 (Fri, 18 Jan 2008)
New Revision: 97

Added:
   buildrom-devel/packages/coreboot-v2/
   buildrom-devel/packages/coreboot-v3/
Removed:
   buildrom-devel/packages/linuxbios/
   buildrom-devel/packages/linuxbiosv3/
Log:
Rename linuxbios and linuxbiosv3 to coreboot-v2 and coreboot-v3
respectively




-- 
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] r3058 - in trunk/util: flashrom lxbios mptable

[svn]

Author: stepan
Date: 2008-01-18 17:17:44 +0100 (Fri, 18 Jan 2008)
New Revision: 3058

Added:
   trunk/util/flashrom/cbtable.c
   trunk/util/flashrom/coreboot_tables.h
   trunk/util/lxbios/coreboot_tables.h
Removed:
   trunk/util/flashrom/lbtable.c
   trunk/util/flashrom/linuxbios_tables.h
   trunk/util/lxbios/linuxbios_tables.h
Modified:
   trunk/util/flashrom/Makefile
   trunk/util/lxbios/Makefile
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/mptable/mptable.c
Log:
rename linuxbios_* files in utils repository.
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/Makefile
===
--- trunk/util/flashrom/Makefile2008-01-18 16:16:45 UTC (rev 3057)
+++ trunk/util/flashrom/Makefile2008-01-18 16:17:44 UTC (rev 3058)
@@ -23,7 +23,7 @@
 OBJS = chipset_enable.o board_enable.o udelay.o jedec.o sst28sf040.o \
am29f040b.o mx29f002.o sst39sf020.o m29f400bt.o w49f002u.o \
82802ab.o msys_doc.o pm49fl004.o sst49lf040.o sst49lfxxxc.o \
-   sst_fwhub.o layout.o lbtable.o flashchips.o flashrom.o \
+   sst_fwhub.o layout.o cbtable.o flashchips.o flashrom.o \
sharplhf00l04.o w29ee011.o spi.o
 
 all: pciutils dep $(PROGRAM)

Copied: trunk/util/flashrom/cbtable.c (from rev 3056, 
trunk/util/flashrom/lbtable.c)
===
--- trunk/util/flashrom/cbtable.c   (rev 0)
+++ trunk/util/flashrom/cbtable.c   2008-01-18 16:17:44 UTC (rev 3058)
@@ -0,0 +1,218 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2002 Steven James <[EMAIL PROTECTED]>
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <[EMAIL PROTECTED]> for Linux Networx)
+ * Copyright (C) 2006-2007 coresystems GmbH
+ * (Written by Stefan Reinauer <[EMAIL PROTECTED]> for coresystems GmbH)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "flash.h"
+#include "coreboot_tables.h"
+
+char *lb_part = NULL, *lb_vendor = NULL;
+
+static unsigned long compute_checksum(void *addr, unsigned long length)
+{
+   uint8_t *ptr;
+   volatile union {
+   uint8_t byte[2];
+   uint16_t word;
+   } value;
+   unsigned long sum;
+   unsigned long i;
+
+   /* In the most straight forward way possible,
+* compute an ip style checksum.
+*/
+   sum = 0;
+   ptr = addr;
+   for (i = 0; i < length; i++) {
+   unsigned long value;
+   value = ptr[i];
+   if (i & 1) {
+   value <<= 8;
+   }
+   /* Add the new value */
+   sum += value;
+   /* Wrap around the carry */
+   if (sum > 0x) {
+   sum = (sum + (sum >> 16)) & 0x;
+   }
+   }
+   value.byte[0] = sum & 0xff;
+   value.byte[1] = (sum >> 8) & 0xff;
+
+   return (~value.word) & 0x;
+}
+
+#define for_each_lbrec(head, rec) \
+   for(rec = (struct lb_record *)(((char *)head) + sizeof(*head)); \
+   (((char *)rec) < (((char *)head) + sizeof(*head) + 
head->table_bytes))  && \
+   (rec->size >= 1) && \
+   char *)rec) + rec->size) <= (((char *)head) + sizeof(*head) 
+ head->table_bytes)); \
+   rec = (struct lb_record *)(((char *)rec) + rec->size))
+
+static int count_lb_records(struct lb_header *head)
+{
+   struct lb_record *rec;
+   int count;
+
+   count = 0;
+   for_each_lbrec(head, rec) {
+   count++;
+   }
+
+   return count;
+}
+
+static struct lb_header *find_lb_table(void *base, unsigned long start,
+  unsigned long end)
+{
+   unsigned long addr;
+
+   /* For now be stupid */
+   for (addr = start; addr < end; addr += 16) {
+   struct lb_header *head =
+   (struct lb_header *)(((char *)base) + addr);
+   struct lb_record *recs =
+   (struct lb_record *)(((char *)base) + addr + sizeof(*head));
+  

[coreboot] r98 - in buildrom-devel/packages: coreboot-v2 coreboot-v3

[svn]

Author: jcrouse
Date: 2008-01-18 18:06:48 +0100 (Fri, 18 Jan 2008)
New Revision: 98

Added:
   buildrom-devel/packages/coreboot-v2/alix1c.mk
   buildrom-devel/packages/coreboot-v2/coreboot.inc
   buildrom-devel/packages/coreboot-v2/ga-2761gxdk.mk
   buildrom-devel/packages/coreboot-v2/generic.mk
   buildrom-devel/packages/coreboot-v2/m57sli.mk
   buildrom-devel/packages/coreboot-v2/msm800sev.mk
   buildrom-devel/packages/coreboot-v2/norwich.mk
   buildrom-devel/packages/coreboot-v2/supermicro-h8dmr.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2882.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2891.mk
   buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
Removed:
   buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/ga-2761gxdk-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/generic-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/linuxbios.inc
   buildrom-devel/packages/coreboot-v2/m57sli-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/msm800sev-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/norwich-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/supermicro-h8dmr-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2882-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2891-linuxbios.mk
   buildrom-devel/packages/coreboot-v3/linuxbiosv3.mk
Log:
Hopefully, this is the last rename - testing will ensue



Deleted: buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk
===
--- buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk 2008-01-18 
17:01:03 UTC (rev 97)
+++ buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk 2008-01-18 
17:06:48 UTC (rev 98)
@@ -1,38 +0,0 @@
-# This is the Generic coreboot target
-
-ifeq ($(CONFIG_PLATFORM),y)
-ifeq ($(CBV2_TAG),)
-$(error You need to specify a version to pull in your platform config)
-endif
-endif
-
-CBV2_BASE_DIR=svn
-CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2
-CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz
-CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.elf
-VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/
-CBV2_VSA=lx_vsa.36k.bin
-TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom
-
-include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc
-
-$(SOURCE_DIR)/$(CBV2_VSA):
-   @ echo "Fetching the VSA code..."
-   wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz  -O $@
-
-$(SOURCE_DIR)/$(CBV2_TARBALL): 
-   @ echo "Fetching the coreboot code..."
-   @ mkdir -p $(SOURCE_DIR)/coreboot
-   @ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \
-   $(CBV2_TAG) $(SOURCE_DIR)/$(CBV2_TARBALL) \
-   > $(CBV2_FETCH_LOG) 2>&1
-
-# Special rule - append the VSA
-
-$(OUTPUT_DIR)/$(TARGET_ROM): $(CBV2_OUTPUT) $(SOURCE_DIR)/$(CBV2_VSA)
-   @ mkdir -p $(OUTPUT_DIR)
-   @ cat $(SOURCE_DIR)/$(CBV2_VSA) $(CBV2_OUTPUT) > $@
-   
-coreboot: $(OUTPUT_DIR)/$(TARGET_ROM)
-coreboot-clean: generic-coreboot-clean
-coreboot-distclean: generic-coreboot-distclean

Copied: buildrom-devel/packages/coreboot-v2/alix1c.mk (from rev 97, 
buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk)
===
--- buildrom-devel/packages/coreboot-v2/alix1c.mk   
(rev 0)
+++ buildrom-devel/packages/coreboot-v2/alix1c.mk   2008-01-18 17:06:48 UTC 
(rev 98)
@@ -0,0 +1,38 @@
+# This is the Generic coreboot target
+
+ifeq ($(CONFIG_PLATFORM),y)
+ifeq ($(CBV2_TAG),)
+$(error You need to specify a version to pull in your platform config)
+endif
+endif
+
+CBV2_BASE_DIR=svn
+CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2
+CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz
+CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.elf
+VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/
+CBV2_VSA=lx_vsa.36k.bin
+TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom
+
+include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc
+
+$(SOURCE_DIR)/$(CBV2_VSA):
+   @ echo "Fetching the VSA code..."
+   wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz  -O $@
+
+$(SOURCE_DIR)/$(CBV2_TARBALL): 
+   @ echo "Fetching the coreboot code..."
+   @ mkdir -p $(SOURCE_DIR)/coreboot
+   @ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \
+   $(CBV2_TAG) $(SOURCE_DIR)/$(CBV2_TARBALL) \
+   > $(CBV2_FETCH_LOG) 2>&1
+
+# Special rule - append the VSA
+
+$(OUTPUT_DIR)/$(TARGET_ROM): $(CBV2_OUTPUT) $(SOURCE_DIR)/$(CBV2_VSA)
+   @ mkdir -p $(OUTPUT_DIR)
+   @ cat $(SOURCE_DIR)/$(CBV2_VSA) $(CBV2_OUTPUT) > $@
+   
+coreboot: $(OUTPUT_DIR)/$(TARGET_ROM)
+coreboot-clean: generic-coreboot-clean
+coreboot-distclean: generic-coreboot-distclean

Copied: buildrom-devel/packages/coreboot-v2/coreboot.inc (from rev 97, 
buildrom-devel/packages/coreboot-v2/linuxbios.inc)
==

[coreboot] r3059 - trunk/util/flashrom

[svn]

Author: uwe
Date: 2008-01-18 18:48:51 +0100 (Fri, 18 Jan 2008)
New Revision: 3059

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/flashrom.8
Log:
Minor documentation improvements/fixes in the README and manpage (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-18 16:17:44 UTC (rev 3058)
+++ trunk/util/flashrom/README  2008-01-18 17:48:51 UTC (rev 3059)
@@ -2,8 +2,12 @@
 Flashrom README
 ---
 
-This is the universal (coreboot) flash utility.
+Flashrom is a universal flash programming utility for DIP, PLCC, or SPI
+flash ROM chips. It can be used to flash BIOS/coreboot/firmware images.
 
+(see http://coreboot.org for details on coreboot)
+
+
 Build Requirements
 --
 
@@ -64,7 +68,7 @@
 ROM Layout Support
 --
 
-Flashrom supports ROM layouts. This allows to flash certain parts of
+Flashrom supports ROM layouts. This allows you to flash certain parts of
 the flash chip only. A ROM layout file looks like follows:
 
   :8fff gfxrom
@@ -94,7 +98,7 @@
 Disk on Chip support
 
 
-Disk on Chip support is currently disabled since it is considered unstable. 
+Disk on Chip support is currently disabled since it is considered unstable.
 Change CFLAGS in the Makefile to enable it: Remove -DDISABLE_DOC from CFLAGS.
 
 

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-18 16:17:44 UTC (rev 3058)
+++ trunk/util/flashrom/flashrom.8  2008-01-18 17:48:51 UTC (rev 3059)
@@ -1,6 +1,6 @@
-.TH FLASHROM 8 "October 18, 2007"
+.TH FLASHROM 8 "January 18, 2008"
 .SH NAME
-flashrom \- a universal flash programming utility
+flashrom \- a universal BIOS/ROM/flash programming utility
 .SH SYNOPSIS
 .B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
  [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] 
[file]
@@ -8,33 +8,37 @@
 .B flashrom
 is a universal flash programming utility for DIP, PLCC, or SPI flash ROM
 chips. It can be used to flash BIOS/coreboot/firmware images, for example.
+
+(see
+.B http://coreboot.org
+for details on coreboot)
 .SH OPTIONS
 If no file is specified, then all that happens
 is that flash info is dumped and the flash chip is set to writable.
 .TP
 .B "\-r, \-\-read"
-Read flash ROM contents an save them into the given file.
+Read flash ROM contents and save them into the given file.
 .TP
 .B "\-w, \-\-write"
-Write file into flash (default when file is specified).
+Write file into flash ROM (default when file is specified).
 .TP
 .B "\-v, \-\-verify"
 Verify the flash ROM contents against the given file.
 .TP
 .B "\-E, \-\-erase"
-Erase the flash device.
+Erase the flash ROM device.
 .TP
 .B "\-V, \-\-verbose"
 More verbose output.
 .TP
 .B "\-c, \-\-chip" 
-Probe only for specified flash chip.
+Probe only for specified flash ROM chip.
 .TP
 .B "\-s, \-\-estart" 
-Exclude start position. (obsolete)
+Exclude start position (obsolete).
 .TP
 .B "\-e, \-\-eend"  
-Exclude end postion. (obsolete)
+Exclude end postion (obsolete).
 .TP
 .B "\-m, \-\-mainboard" 
 Override mainboard settings. This option is needed for some mainboards,
@@ -63,12 +67,13 @@
 .\".B "\-\-version"
 .\"Show version information and exit.
 .SH BUGS
-Please report any bugs at http://tracker.coreboot.org/trac/coreboot/,
-or on the coreboot mailing list (http://www.coreboot.org/Mailinglist).
+Please report any bugs at
+.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
+or on the coreboot mailing list
+.RB "(" http://coreboot.org/Mailinglist ")."
 .SH LICENCE
 .B flashrom
 is covered by the GNU General Public License (GPL), version 2 or later.
-.\" .SH SEE ALSO
 .SH COPYRIGHT
 2000 Silicon Integrated System Corporation
 .br
@@ -87,4 +92,4 @@
 some others 
 .PP
 This manual page was written by Uwe Hermann <[EMAIL PROTECTED]>.
-It is licensed under the terms of the GNU GPL (v2 or later).
+It is licensed under the terms of the GNU GPL (version 2 or later).


-- 
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] r3061 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-19 01:04:46 +0100 (Sat, 19 Jan 2008)
New Revision: 3061

Modified:
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
   trunk/util/flashrom/spi.c
Log:
Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
Super I/O performing LPC-to-SPI flash translation.

Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]>
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-18 18:04:28 UTC (rev 3060)
+++ trunk/util/flashrom/flash.h 2008-01-19 00:04:46 UTC (rev 3061)
@@ -234,7 +234,16 @@
 
 #define TI_ID  0x97/* Texas Instruments */
 
+/*
+ * W25X chips are SPI, first byte of device ID is memory type, second
+ * byte of device ID is related to log(bitsize).
+ */
 #define WINBOND_ID 0xDA/* Winbond */
+#define WINBOND_NEX_ID 0xEF/* Winbond (ex Nexcom) serial flash 
devices */
+#define W_25X100x3011
+#define W_25X200x3012
+#define W_25X400x3013
+#define W_25X800x3014
 #define W_29C011   0xC1
 #define W_29C020C  0x45
 #define W_29C040P  0x46
@@ -297,6 +306,7 @@
 void generic_spi_write_disable();
 int generic_spi_chip_erase_c7(struct flashchip *flash);
 int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf);
+int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf);
 
 /* 82802ab.c */
 int probe_82802ab(struct flashchip *flash);

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-18 18:04:28 UTC (rev 3060)
+++ trunk/util/flashrom/flashchips.c2008-01-19 00:04:46 UTC (rev 3061)
@@ -51,13 +51,13 @@
{"MX29F002",MX_ID,  MX_29F002,  256, 64 * 1024,
 probe_29f002,  erase_29f002,   write_29f002},
{"MX25L4005",   MX_ID,  MX_25L4005, 512, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L8005",   MX_ID,  MX_25L8005, 1024, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
-   probe_spi,  generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,
-   probe_spi,  generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST29EE020A", SST_ID, SST_29EE020A,   256, 128,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"SST28SF040A", SST_ID, SST_28SF040,512, 256,
@@ -122,6 +122,14 @@
 probe_jedec,   erase_chip_jedec, write_39sf020},
{"W39V080A",WINBOND_ID, W_39V080A,  1024, 64*1024,
 probe_jedec,   erase_chip_jedec, write_39sf020},
+   {"W25x10",  WINBOND_NEX_ID, W_25X10,128, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x20",  WINBOND_NEX_ID, W_25X20,256, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x40",  WINBOND_NEX_ID, W_25X40,512, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x80",  WINBOND_NEX_ID, W_25X80,1024, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"M29F002B",ST_ID,  ST_M29F002B,256, 64 * 1024,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"M50FW040",ST_ID,  ST_M50FW040,512, 64 * 1024,
@@ -151,23 +159,23 @@
{"M29F040B",ST_ID,  ST_M29F040B,512, 64 * 1024,
 probe_29f040b, erase_29f040b,  write_29f040b},
{"M25P05-A",ST_ID,  ST_M25P05A, 64, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"M25P10-A",ST_ID,  ST_M25P10A, 128,256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_

[coreboot] r3061 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-19 01:04:46 +0100 (Sat, 19 Jan 2008)
New Revision: 3061

Modified:
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
   trunk/util/flashrom/spi.c
Log:
Support SPI flash chips bigger than 512 kByte sitting behind IT8716F
Super I/O performing LPC-to-SPI flash translation.

Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]>
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-18 18:04:28 UTC (rev 3060)
+++ trunk/util/flashrom/flash.h 2008-01-19 00:04:46 UTC (rev 3061)
@@ -234,7 +234,16 @@
 
 #define TI_ID  0x97/* Texas Instruments */
 
+/*
+ * W25X chips are SPI, first byte of device ID is memory type, second
+ * byte of device ID is related to log(bitsize).
+ */
 #define WINBOND_ID 0xDA/* Winbond */
+#define WINBOND_NEX_ID 0xEF/* Winbond (ex Nexcom) serial flash 
devices */
+#define W_25X100x3011
+#define W_25X200x3012
+#define W_25X400x3013
+#define W_25X800x3014
 #define W_29C011   0xC1
 #define W_29C020C  0x45
 #define W_29C040P  0x46
@@ -297,6 +306,7 @@
 void generic_spi_write_disable();
 int generic_spi_chip_erase_c7(struct flashchip *flash);
 int generic_spi_chip_write(struct flashchip *flash, uint8_t *buf);
+int generic_spi_chip_read(struct flashchip *flash, uint8_t *buf);
 
 /* 82802ab.c */
 int probe_82802ab(struct flashchip *flash);

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-18 18:04:28 UTC (rev 3060)
+++ trunk/util/flashrom/flashchips.c2008-01-19 00:04:46 UTC (rev 3061)
@@ -51,13 +51,13 @@
{"MX29F002",MX_ID,  MX_29F002,  256, 64 * 1024,
 probe_29f002,  erase_29f002,   write_29f002},
{"MX25L4005",   MX_ID,  MX_25L4005, 512, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L8005",   MX_ID,  MX_25L8005, 1024, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
-   probe_spi,  generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,
-   probe_spi,  generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST29EE020A", SST_ID, SST_29EE020A,   256, 128,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"SST28SF040A", SST_ID, SST_28SF040,512, 256,
@@ -122,6 +122,14 @@
 probe_jedec,   erase_chip_jedec, write_39sf020},
{"W39V080A",WINBOND_ID, W_39V080A,  1024, 64*1024,
 probe_jedec,   erase_chip_jedec, write_39sf020},
+   {"W25x10",  WINBOND_NEX_ID, W_25X10,128, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x20",  WINBOND_NEX_ID, W_25X20,256, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x40",  WINBOND_NEX_ID, W_25X40,512, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"W25x80",  WINBOND_NEX_ID, W_25X80,1024, 256, 
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"M29F002B",ST_ID,  ST_M29F002B,256, 64 * 1024,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"M50FW040",ST_ID,  ST_M50FW040,512, 64 * 1024,
@@ -151,23 +159,23 @@
{"M29F040B",ST_ID,  ST_M29F040B,512, 64 * 1024,
 probe_29f040b, erase_29f040b,  write_29f040b},
{"M25P05-A",ST_ID,  ST_M25P05A, 64, 256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"M25P10-A",ST_ID,  ST_M25P10A, 128,256,
-probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write},
+probe_spi, generic_spi_

[coreboot] r3062 - trunk/util/superiotool

[svn]

Author: hailfinger
Date: 2008-01-19 01:32:07 +0100 (Sat, 19 Jan 2008)
New Revision: 3062

Modified:
   trunk/util/superiotool/winbond.c
Log:
This patch is for winbond w83627DHG superio support in superiotool.
I have test that on my board, it works ;)

Signed-off-by: Bingxun Shi <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/superiotool/winbond.c
===
--- trunk/util/superiotool/winbond.c2008-01-19 00:04:46 UTC (rev 3061)
+++ trunk/util/superiotool/winbond.c2008-01-19 00:32:07 UTC (rev 3062)
@@ -143,6 +143,57 @@
{EOT}}},
 #endif
{0xa02, "W83627DHG", {
+   {NOLDN, NULL,
+   {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
+0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+   {0x00,0xa0,NANA,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
+0x00,0x00,RSVD,0xe2,0x21,0x00,0x00,EOT}},
+   {0x0, "Floppy",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,
+EOT},
+   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00,
+EOT}},
+   {0x1, "Parallel port",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+   {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
+   {0x2, "COM1",
+   {0x30,0x60,0x61,0x70,0xf0,EOT},
+   {0x01,0x03,0xf8,0x04,0x00,EOT}},
+   {0x3, "COM2",
+   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+   {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
+   {0x5, "Keyboard",
+   {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
+   {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}},
+   {0x6, "Serial peripheral interface",
+   {0x30,0x62,0x63,EOT},
+   {0x00,0x00,0x00,EOT}},
+   {0x7, "GPIO 6",
+   {0x30,0xf4,0xf5,0xf6,0xf7,EOT},
+   {0x00,0xff,0x00,0x00,0x00,EOT}},
+   {0x8, "WDTO#, PLED",
+   {0x30,0xf5,0xf6,0xf7,EOT},
+   {0x00,0x00,0x00,0x00,EOT}},
+   {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5",
+   {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
+0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xfe,
+EOT},
+   {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,
+0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,
+EOT}},
+   {0xa, "ACPI",
+   {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
+0xe8,0xe9,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT},
+   {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x1c,0x00,
+RSVD,RSVD,0x7c,0x00,0x00,0x00,0x00,0x00,EOT}},
+   {0xb, "Hardware monitor",
+   {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT},
+   {0x00,0x00,0x00,0x00,0x81,0x00,0x00,EOT}},
+   {0xc, "PECI, SST",
+   {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe8,0xf1,0xfe,0xff,
+EOT},
+   {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00,
+EOT}},
{EOT}}},
{0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */
{NOLDN, NULL,


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[coreboot] r3062 - trunk/util/superiotool

[svn]

Author: hailfinger
Date: 2008-01-19 01:32:07 +0100 (Sat, 19 Jan 2008)
New Revision: 3062

Modified:
   trunk/util/superiotool/winbond.c
Log:
This patch is for winbond w83627DHG superio support in superiotool.
I have test that on my board, it works ;)

Signed-off-by: Bingxun Shi <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/superiotool/winbond.c
===
--- trunk/util/superiotool/winbond.c2008-01-19 00:04:46 UTC (rev 3061)
+++ trunk/util/superiotool/winbond.c2008-01-19 00:32:07 UTC (rev 3062)
@@ -143,6 +143,57 @@
{EOT}}},
 #endif
{0xa02, "W83627DHG", {
+   {NOLDN, NULL,
+   {0x02,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
+0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+   {0x00,0xa0,NANA,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
+0x00,0x00,RSVD,0xe2,0x21,0x00,0x00,EOT}},
+   {0x0, "Floppy",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,0xf5,
+EOT},
+   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,0x00,
+EOT}},
+   {0x1, "Parallel port",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
+   {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
+   {0x2, "COM1",
+   {0x30,0x60,0x61,0x70,0xf0,EOT},
+   {0x01,0x03,0xf8,0x04,0x00,EOT}},
+   {0x3, "COM2",
+   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
+   {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
+   {0x5, "Keyboard",
+   {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
+   {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}},
+   {0x6, "Serial peripheral interface",
+   {0x30,0x62,0x63,EOT},
+   {0x00,0x00,0x00,EOT}},
+   {0x7, "GPIO 6",
+   {0x30,0xf4,0xf5,0xf6,0xf7,EOT},
+   {0x00,0xff,0x00,0x00,0x00,EOT}},
+   {0x8, "WDTO#, PLED",
+   {0x30,0xf5,0xf6,0xf7,EOT},
+   {0x00,0x00,0x00,0x00,EOT}},
+   {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5",
+   {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8,
+0xe9,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xfe,
+EOT},
+   {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0x00,0x00,0x00,
+0x00,0xff,0x00,0x00,0x00,0xff,0x00,0x00,0x00,0x00,
+EOT}},
+   {0xa, "ACPI",
+   {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
+0xe8,0xe9,0xf2,0xf3,0xf4,0xf6,0xf7,0xfe,EOT},
+   {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x1c,0x00,
+RSVD,RSVD,0x7c,0x00,0x00,0x00,0x00,0x00,EOT}},
+   {0xb, "Hardware monitor",
+   {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT},
+   {0x00,0x00,0x00,0x00,0x81,0x00,0x00,EOT}},
+   {0xc, "PECI, SST",
+   {0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe8,0xf1,0xfe,0xff,
+EOT},
+   {0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00,
+EOT}},
{EOT}}},
{0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */
{NOLDN, NULL,


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[coreboot] r3055 - trunk/util/lxbios

[svn]

Author: stepan
Date: 2008-01-18 16:33:49 +0100 (Fri, 18 Jan 2008)
New Revision: 3055

Modified:
   trunk/util/lxbios/ChangeLog
   trunk/util/lxbios/DISCLAIMER
   trunk/util/lxbios/README
   trunk/util/lxbios/cmos_lowlevel.c
   trunk/util/lxbios/cmos_lowlevel.h
   trunk/util/lxbios/cmos_ops.c
   trunk/util/lxbios/cmos_ops.h
   trunk/util/lxbios/common.c
   trunk/util/lxbios/common.h
   trunk/util/lxbios/compute_ip_checksum.c
   trunk/util/lxbios/input_file.c
   trunk/util/lxbios/input_file.h
   trunk/util/lxbios/ip_checksum.h
   trunk/util/lxbios/layout.c
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.c
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/lxbios/lbtable.h
   trunk/util/lxbios/linuxbios_tables.h
   trunk/util/lxbios/lxbios.1
   trunk/util/lxbios/lxbios.c
   trunk/util/lxbios/lxbios.spec
   trunk/util/lxbios/opts.c
   trunk/util/lxbios/opts.h
   trunk/util/lxbios/reg_expr.c
   trunk/util/lxbios/reg_expr.h
Log:
rename linuxbios -> coreboot
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/lxbios/ChangeLog
===
--- trunk/util/lxbios/ChangeLog 2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/ChangeLog 2008-01-18 15:33:49 UTC (rev 3055)
@@ -54,7 +54,7 @@
 
* Merge patch from Stefan Reinauer <[EMAIL PROTECTED]> that makes
  lxbios recognize the LB_TAG_OPTION_CHECKSUM entry placed in the
- LinuxBIOS table by newer versions of LinuxBIOS.
+ coreboot table by newer versions of LinuxBIOS.
 
* Tweak formatting of code to facilitate merging future patches.
 
@@ -121,11 +121,11 @@
 
Version 1.1.0.
 
-   * Added -l option for displaying entries from LinuxBIOS table.
+   * Added -l option for displaying entries from coreboot table.
 
-   * Added -d option for low-level dump of LinuxBIOS table.
+   * Added -d option for low-level dump of coreboot table.
 
-   * Improved code that searches for LinuxBIOS table.
+   * Improved code that searches for coreboot table.
 
 Wed Nov  6 09:30:00 PST 2002  David S. Peterson ([EMAIL PROTECTED])
 

Modified: trunk/util/lxbios/DISCLAIMER
===
--- trunk/util/lxbios/DISCLAIMER2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/DISCLAIMER2008-01-18 15:33:49 UTC (rev 3055)
@@ -8,8 +8,8 @@
 UCRL-CODE-2003-012
 All rights reserved.
 
-This file is part of lxbios, a utility for reading/writing LinuxBIOS
-parameters and displaying information from the LinuxBIOS table.
+This file is part of lxbios, a utility for reading/writing coreboot
+parameters and displaying information from the coreboot table.
 For details, see .
 
 This program is free software; you can redistribute it and/or modify it

Modified: trunk/util/lxbios/README
===
--- trunk/util/lxbios/README2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/README2008-01-18 15:33:49 UTC (rev 3055)
@@ -2,17 +2,17 @@
 
 Summary of Operation
 
-lxbios is a utility for reading/writing LinuxBIOS parameters and
-displaying information from the LinuxBIOS table.  It is intended for x86-based
-systems (both 32-bit and 64-bit) that use LinuxBIOS.
+lxbios is a utility for reading/writing coreboot parameters and
+displaying information from the coreboot table.  It is intended for x86-based
+systems (both 32-bit and 64-bit) that use coreboot.
 
-The LinuxBIOS table resides in low physical memory, and may be accessed
-through the /dev/mem interface.  It is created at boot time by LinuxBIOS, and
+The coreboot table resides in low physical memory, and may be accessed
+through the /dev/mem interface.  It is created at boot time by coreboot, and
 contains various system information such as the type of mainboard in use.  It
-specifies locations in the CMOS (nonvolatile RAM) where the LinuxBIOS
+specifies locations in the CMOS (nonvolatile RAM) where the coreboot
 parameters are stored.
 
-For information about LinuxBIOS, see http://www.linuxbios.org/.
+For information about coreboot, see http://www.coreboot.org/.
 
 Ideas for Future Improvements
 -

Modified: trunk/util/lxbios/cmos_lowlevel.c
===
--- trunk/util/lxbios/cmos_lowlevel.c   2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/cmos_lowlevel.c   2008-01-18 15:33:49 UTC (rev 3055)
@@ -8,8 +8,8 @@
  *  UCRL-CODE-2003-012
  *  All rights reserved.
  *
- *  This file is part of lxbios, a utility for reading/writing LinuxBIOS
- *  parameters and displaying information from the LinuxBIOS table.
+ *  This file is part of lxbios, a utility for reading/writing coreboot
+ *  parameters and displaying information from the coreboot table.
  

[coreboot] r3054 - trunk/util/flashrom

[svn]

Author: stepan
Date: 2008-01-18 16:33:10 +0100 (Fri, 18 Jan 2008)
New Revision: 3054

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/board_enable.c
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
   trunk/util/flashrom/layout.c
   trunk/util/flashrom/lbtable.c
   trunk/util/flashrom/linuxbios_tables.h
   trunk/util/flashrom/m29f400bt.c
Log:
for some reasons the externals did not get committed.

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/README  2008-01-18 15:33:10 UTC (rev 3054)
@@ -2,7 +2,7 @@
 Flashrom README
 ---
 
-This is the universal (LinuxBIOS) flash utility.
+This is the universal (coreboot) flash utility.
 
 Build Requirements
 --
@@ -38,17 +38,17 @@
  is that flash info is dumped and the flash chip is set to writable.
 
 
-LinuxBIOS Table and Mainboard Identification
+coreboot Table and Mainboard Identification
 
 
-Flashrom reads the LinuxBIOS table to determine the current mainboard
-(parse DMI as well in future?). If no LinuxBIOS table could be read
+Flashrom reads the coreboot table to determine the current mainboard
+(parse DMI as well in future?). If no coreboot table could be read
 or if you want to override these values, you can specify -m, e.g.:
 
   flashrom -w --mainboard AGAMI:ARUMA agami_aruma.rom
 
 The following boards require the specification of the board name, if
-no LinuxBIOS table is found:
+no coreboot table is found:
 
 * IWILL DK8-HTX: use -m iwill:dk8_htx
 * Agami Aruma: use -m AGAMI:ARUMA

Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c  2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/board_enable.c  2008-01-18 15:33:10 UTC (rev 3054)
@@ -148,7 +148,7 @@
 /**
  * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
  *
- * We don't need to do this when using LinuxBIOS, GPIO15 is never lowered 
there.
+ * We don't need to do this when using coreboot, GPIO15 is never lowered there.
  */
 static int board_via_epia_m(const char *name)
 {
@@ -368,7 +368,7 @@
uint16_t second_card_vendor;
uint16_t second_card_device;
 
-   /* The vendor / part name from the LinuxBIOS table. */
+   /* The vendor / part name from the coreboot table. */
const char *lb_vendor;
const char *lb_part;
 
@@ -407,10 +407,10 @@
 };
 
 /**
- * Match boards on LinuxBIOS table gathered vendor and part name.
+ * Match boards on coreboot table gathered vendor and part name.
  * Require main PCI IDs to match too as extra safety.
  */
-static struct board_pciid_enable *board_match_linuxbios_name(const char 
*vendor, const char *part)
+static struct board_pciid_enable *board_match_coreboot_name(const char 
*vendor, const char *part)
 {
struct board_pciid_enable *board = board_pciid_enables;
 
@@ -478,7 +478,7 @@
int ret = 0;
 
if (vendor && part)
-   board = board_match_linuxbios_name(vendor, part);
+   board = board_match_coreboot_name(vendor, part);
 
if (!board)
board = board_match_pci_card_ids();

Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/flash.h 2008-01-18 15:33:10 UTC (rev 3054)
@@ -286,7 +286,7 @@
 int handle_romentries(uint8_t *buffer, uint8_t *content);
 
 /* lbtable.c */
-int linuxbios_init(void);
+int coreboot_init(void);
 extern char *lb_part, *lb_vendor;
 
 /* spi.c */
@@ -329,7 +329,7 @@
 int block_erase_m29f400bt(volatile uint8_t *bios,
 volatile uint8_t *dst);
 int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
-int write_linuxbios_m29f400bt(struct flashchip *flash, uint8_t *buf);
+int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf);
 void toggle_ready_m29f400bt(volatile uint8_t *dst);
 void data_polling_m29f400bt(volatile uint8_t *dst, uint8_t data);
 void protect_m29f400bt(volatile uint8_t *bios);

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-18 15:08:58 UTC (rev 3053)
+++ trunk/util/flashrom/flashchips.c2008-01-18 15:33:10 UTC (rev 3054)
@@ -47,7 +47,7 @@
{"EN29F002(A)(N)B", EON_ID, EN_29F002B, 256, 256,
 probe_jedec,   erase_chip_jedec, write_jedec},
{"MBM29F400TC", FUJITSU_ID, MBM29F400TC_STRANGE,512, 64 * 102

[coreboot] r98 - in buildrom-devel/packages: coreboot-v2 coreboot-v3

[svn]

Author: jcrouse
Date: 2008-01-18 18:06:48 +0100 (Fri, 18 Jan 2008)
New Revision: 98

Added:
   buildrom-devel/packages/coreboot-v2/alix1c.mk
   buildrom-devel/packages/coreboot-v2/coreboot.inc
   buildrom-devel/packages/coreboot-v2/ga-2761gxdk.mk
   buildrom-devel/packages/coreboot-v2/generic.mk
   buildrom-devel/packages/coreboot-v2/m57sli.mk
   buildrom-devel/packages/coreboot-v2/msm800sev.mk
   buildrom-devel/packages/coreboot-v2/norwich.mk
   buildrom-devel/packages/coreboot-v2/supermicro-h8dmr.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2882.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2891.mk
   buildrom-devel/packages/coreboot-v3/coreboot-v3.mk
Removed:
   buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/ga-2761gxdk-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/generic-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/linuxbios.inc
   buildrom-devel/packages/coreboot-v2/m57sli-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/msm800sev-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/norwich-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/supermicro-h8dmr-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2882-linuxbios.mk
   buildrom-devel/packages/coreboot-v2/tyan-s2891-linuxbios.mk
   buildrom-devel/packages/coreboot-v3/linuxbiosv3.mk
Log:
Hopefully, this is the last rename - testing will ensue



Deleted: buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk
===
--- buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk 2008-01-18 
17:01:03 UTC (rev 97)
+++ buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk 2008-01-18 
17:06:48 UTC (rev 98)
@@ -1,38 +0,0 @@
-# This is the Generic coreboot target
-
-ifeq ($(CONFIG_PLATFORM),y)
-ifeq ($(CBV2_TAG),)
-$(error You need to specify a version to pull in your platform config)
-endif
-endif
-
-CBV2_BASE_DIR=svn
-CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2
-CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz
-CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.elf
-VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/
-CBV2_VSA=lx_vsa.36k.bin
-TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom
-
-include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc
-
-$(SOURCE_DIR)/$(CBV2_VSA):
-   @ echo "Fetching the VSA code..."
-   wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz  -O $@
-
-$(SOURCE_DIR)/$(CBV2_TARBALL): 
-   @ echo "Fetching the coreboot code..."
-   @ mkdir -p $(SOURCE_DIR)/coreboot
-   @ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \
-   $(CBV2_TAG) $(SOURCE_DIR)/$(CBV2_TARBALL) \
-   > $(CBV2_FETCH_LOG) 2>&1
-
-# Special rule - append the VSA
-
-$(OUTPUT_DIR)/$(TARGET_ROM): $(CBV2_OUTPUT) $(SOURCE_DIR)/$(CBV2_VSA)
-   @ mkdir -p $(OUTPUT_DIR)
-   @ cat $(SOURCE_DIR)/$(CBV2_VSA) $(CBV2_OUTPUT) > $@
-   
-coreboot: $(OUTPUT_DIR)/$(TARGET_ROM)
-coreboot-clean: generic-coreboot-clean
-coreboot-distclean: generic-coreboot-distclean

Copied: buildrom-devel/packages/coreboot-v2/alix1c.mk (from rev 97, 
buildrom-devel/packages/coreboot-v2/alix1c-linuxbios.mk)
===
--- buildrom-devel/packages/coreboot-v2/alix1c.mk   
(rev 0)
+++ buildrom-devel/packages/coreboot-v2/alix1c.mk   2008-01-18 17:06:48 UTC 
(rev 98)
@@ -0,0 +1,38 @@
+# This is the Generic coreboot target
+
+ifeq ($(CONFIG_PLATFORM),y)
+ifeq ($(CBV2_TAG),)
+$(error You need to specify a version to pull in your platform config)
+endif
+endif
+
+CBV2_BASE_DIR=svn
+CBV2_URL=svn://coreboot.org/repos/trunk/coreboot-v2
+CBV2_TARBALL=coreboot-svn-$(CBV2_TAG).tar.gz
+CBV2_PAYLOAD_TARGET=$(CBV2_BUILD_DIR)/payload.elf
+VSA_URL=http://www.amd.com/files/connectivitysolutions/geode/geode_lx/
+CBV2_VSA=lx_vsa.36k.bin
+TARGET_ROM = $(COREBOOT_VENDOR)-$(COREBOOT_BOARD).rom
+
+include $(PACKAGE_DIR)/coreboot-v2/coreboot.inc
+
+$(SOURCE_DIR)/$(CBV2_VSA):
+   @ echo "Fetching the VSA code..."
+   wget -P $(SOURCE_DIR) $(VSA_URL)/$(CBV2_VSA).gz  -O $@
+
+$(SOURCE_DIR)/$(CBV2_TARBALL): 
+   @ echo "Fetching the coreboot code..."
+   @ mkdir -p $(SOURCE_DIR)/coreboot
+   @ $(BIN_DIR)/fetchsvn.sh $(CBV2_URL) $(SOURCE_DIR)/coreboot \
+   $(CBV2_TAG) $(SOURCE_DIR)/$(CBV2_TARBALL) \
+   > $(CBV2_FETCH_LOG) 2>&1
+
+# Special rule - append the VSA
+
+$(OUTPUT_DIR)/$(TARGET_ROM): $(CBV2_OUTPUT) $(SOURCE_DIR)/$(CBV2_VSA)
+   @ mkdir -p $(OUTPUT_DIR)
+   @ cat $(SOURCE_DIR)/$(CBV2_VSA) $(CBV2_OUTPUT) > $@
+   
+coreboot: $(OUTPUT_DIR)/$(TARGET_ROM)
+coreboot-clean: generic-coreboot-clean
+coreboot-distclean: generic-coreboot-distclean

Copied: buildrom-devel/packages/coreboot-v2/coreboot.inc (from rev 97, 
buildrom-devel/packages/coreboot-v2/linuxbios.inc)
==

[coreboot] r3060 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-18 19:04:28 +0100 (Fri, 18 Jan 2008)
New Revision: 3060

Modified:
   trunk/util/superiotool/README
   trunk/util/superiotool/superiotool.8
Log:
Document the --list-supported option. Various small fixes (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-18 17:48:51 UTC (rev 3059)
+++ trunk/util/superiotool/README   2008-01-18 18:04:28 UTC (rev 3060)
@@ -30,9 +30,10 @@
 Usage
 -
 
- $ superiotool [-d] [-V] [-v] [-h]
+ $ superiotool [-d] [-l] [-V] [-v] [-h]
 
  -d | --dumpDump Super I/O register contents
+ -l | --list-supported  Show the list of supported Super I/O chips
  -V | --verbose Verbose mode
  -v | --version Show the superiotool version
  -h | --helpShow a short help text
@@ -54,10 +55,12 @@
 Supported Super I/O Chips
 -
 
-Please see http://coreboot.org/Superiotool#Supported_devices.
+Please see http://coreboot.org/Superiotool#Supported_devices, or type
 
+ $ superiotool -l
+
 There's also a collection of sample register dumps from various Super I/O
-chips on that page. Please send further register dumps (either from a
+chips on that web page. Please send further register dumps (either from a
 proprietary BIOS and/or from coreboot) to the coreboot mailing list
 (http://coreboot.org/Mailinglist).
 
@@ -79,7 +82,7 @@
 refer to the respective source code files for details.
 
 It is licensed under the terms of the GNU General Public License (GPL),
-either version 2 of the License, or (at your option) any later version.
+either version 2 of the license, or (at your option) any later version.
 
 
 Contributors

Modified: trunk/util/superiotool/superiotool.8
===
--- trunk/util/superiotool/superiotool.82008-01-18 17:48:51 UTC (rev 
3059)
+++ trunk/util/superiotool/superiotool.82008-01-18 18:04:28 UTC (rev 
3060)
@@ -1,4 +1,4 @@
-.TH SUPERIOTOOL 8 "January 13, 2008"
+.TH SUPERIOTOOL 8 "January 18, 2008"
 .SH NAME
 superiotool \- Super I/O detection tool
 .SH SYNOPSIS
@@ -17,9 +17,10 @@
 It is mainly used for coreboot development purposes (see coreboot.org
 for details on coreboot), but it may also be useful for other things.
 .PP
-The list of supported Super I/O chips is available at:
-.br
-.B http://coreboot.org/Superiotool#Supported_devices
+The list of supported Super I/O chips is available at
+.BR http://coreboot.org/Superiotool#Supported_devices ","
+but it can also be viewed by running
+.BR "superiotool -l" "."
 .SH OPTIONS
 If no command line option is specified,
 .B superiotool
@@ -35,7 +36,7 @@
 .B "\-\-dump"
 option for this chip). The output will look something like this:
 .sp
-.B "$ ./superiotool -d"
+.B "$ superiotool -d"
 .br
 Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0
 .br
@@ -75,7 +76,7 @@
 .B "\-l, \-\-list-supported"
 List all Super I/O chips recognized by
 .BR superiotool ". The phrase"
-.BR (dump available)
+.BR "(dump available)"
 following a chip name indicates that
 .B superiotool
 supports the
@@ -98,8 +99,10 @@
 .B "\-h, \-\-help"
 Show a help text and exit.
 .SH BUGS
-Please report any bugs at http://tracker.coreboot.org/trac/coreboot/
-or on the coreboot mailing list (http://coreboot.org/Mailinglist).
+Please report any bugs at
+.B http://tracker.coreboot.org/trac/coreboot/newticket
+or on the coreboot mailing list
+.RB "(" http://coreboot.org/Mailinglist ")."
 .SH AUTHORS
 Please see the individual source code files and/or the README file.
 .SH LICENCE


-- 
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http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] r99 - buildrom-devel/config/platforms

[svn]

Author: myles
Date: 2008-01-18 19:33:20 +0100 (Fri, 18 Jan 2008)
New Revision: 99

Modified:
   buildrom-devel/config/platforms/alix1c.conf
   buildrom-devel/config/platforms/db800.conf
   buildrom-devel/config/platforms/dbe61.conf
   buildrom-devel/config/platforms/m57sli.conf
   buildrom-devel/config/platforms/msm800sev.conf
   buildrom-devel/config/platforms/norwich.conf
   buildrom-devel/config/platforms/qemu.conf
   buildrom-devel/config/platforms/serengeti_cheetah.conf
   buildrom-devel/config/platforms/supermicro-h8dmr.conf
   buildrom-devel/config/platforms/tyan-s2882.conf
   buildrom-devel/config/platforms/tyan-s2891.conf
Log:
This patch changes board.conf files so that we can use BOARD_NAME.mk
instead of BOARD_NAME-kernel.mk for every board.

It also removes an unused variable in qemu.conf and regroups another.

This patch needs to be followed with an svn mv
packages/kernel/*-kernel.mk packages/kernel/*.mk

Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked by: Jordan Crouse <[EMAIL PROTECTED]>


Modified: buildrom-devel/config/platforms/alix1c.conf
===
--- buildrom-devel/config/platforms/alix1c.conf 2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/alix1c.conf 2008-01-18 18:33:20 UTC (rev 99)
@@ -11,7 +11,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/alix1c-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/alix1c.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/alix1c.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/db800.conf
===
--- buildrom-devel/config/platforms/db800.conf  2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/db800.conf  2008-01-18 18:33:20 UTC (rev 99)
@@ -13,7 +13,7 @@
 # Targets
 # Use the same settings as the Norwich platform
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/dbe61.conf
===
--- buildrom-devel/config/platforms/dbe61.conf  2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/dbe61.conf  2008-01-18 18:33:20 UTC (rev 99)
@@ -13,7 +13,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/m57sli.conf
===
--- buildrom-devel/config/platforms/m57sli.conf 2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/m57sli.conf 2008-01-18 18:33:20 UTC (rev 99)
@@ -16,7 +16,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/m57sli-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/m57sli.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/m57sli.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/msm800sev.conf
===
--- buildrom-devel/config/platforms/msm800sev.conf  2008-01-18 17:06:48 UTC 
(rev 98)
+++ buildrom-devel/config/platforms/msm800sev.conf  2008-01-18 18:33:20 UTC 
(rev 99)
@@ -12,7 +12,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/msm800sev-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/msm800sev.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/msm800sev.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/norwich.conf
===
--- buildrom-devel/config/platforms/norwich.conf2008-01-18 17:06:48 UTC 
(rev 98)
+++ buildrom-devel/config/platforms/norwich.conf2008-01-18 18:33:20 UTC 
(rev 99)
@@ -12,7 +12,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/qemu.conf
===
--- buildrom-devel/config/platforms/qemu.conf   2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/qemu.conf   2008-01-18 18:33:20 UTC (rev 99)
@@ -11,7 +11,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/qemu.mk
 
 # kernel configuration (for LAB)
@@ -26,14 +26,13 @@
 # coreboot-v2 configuration
 CBV2_TAG=2950
 CBV2_CONFIG=Config.lb
-COREBOOT_ROM_NAME=qemu.rom
 CBV2_TDIR=qemu-i386
 
 # coreboot v3 configuration
 CBV3_CONFIG=qemu-i386-defconfig
 CBV3_TAG=HEAD
-CBV3_ROM_NAME=linuxbios.rom
 
+COREBOOT_ROM_NAME=qemu.rom
 COREBOOT_VENDOR=emulation
 COREBOOT_BOARD=qemu-i386
 

Modified: buildrom-devel/config/platforms/serengeti_

[coreboot] r3059 - trunk/util/flashrom

[svn]

Author: uwe
Date: 2008-01-18 18:48:51 +0100 (Fri, 18 Jan 2008)
New Revision: 3059

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/flashrom.8
Log:
Minor documentation improvements/fixes in the README and manpage (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-18 16:17:44 UTC (rev 3058)
+++ trunk/util/flashrom/README  2008-01-18 17:48:51 UTC (rev 3059)
@@ -2,8 +2,12 @@
 Flashrom README
 ---
 
-This is the universal (coreboot) flash utility.
+Flashrom is a universal flash programming utility for DIP, PLCC, or SPI
+flash ROM chips. It can be used to flash BIOS/coreboot/firmware images.
 
+(see http://coreboot.org for details on coreboot)
+
+
 Build Requirements
 --
 
@@ -64,7 +68,7 @@
 ROM Layout Support
 --
 
-Flashrom supports ROM layouts. This allows to flash certain parts of
+Flashrom supports ROM layouts. This allows you to flash certain parts of
 the flash chip only. A ROM layout file looks like follows:
 
   :8fff gfxrom
@@ -94,7 +98,7 @@
 Disk on Chip support
 
 
-Disk on Chip support is currently disabled since it is considered unstable. 
+Disk on Chip support is currently disabled since it is considered unstable.
 Change CFLAGS in the Makefile to enable it: Remove -DDISABLE_DOC from CFLAGS.
 
 

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-18 16:17:44 UTC (rev 3058)
+++ trunk/util/flashrom/flashrom.8  2008-01-18 17:48:51 UTC (rev 3059)
@@ -1,6 +1,6 @@
-.TH FLASHROM 8 "October 18, 2007"
+.TH FLASHROM 8 "January 18, 2008"
 .SH NAME
-flashrom \- a universal flash programming utility
+flashrom \- a universal BIOS/ROM/flash programming utility
 .SH SYNOPSIS
 .B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
  [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] 
[file]
@@ -8,33 +8,37 @@
 .B flashrom
 is a universal flash programming utility for DIP, PLCC, or SPI flash ROM
 chips. It can be used to flash BIOS/coreboot/firmware images, for example.
+
+(see
+.B http://coreboot.org
+for details on coreboot)
 .SH OPTIONS
 If no file is specified, then all that happens
 is that flash info is dumped and the flash chip is set to writable.
 .TP
 .B "\-r, \-\-read"
-Read flash ROM contents an save them into the given file.
+Read flash ROM contents and save them into the given file.
 .TP
 .B "\-w, \-\-write"
-Write file into flash (default when file is specified).
+Write file into flash ROM (default when file is specified).
 .TP
 .B "\-v, \-\-verify"
 Verify the flash ROM contents against the given file.
 .TP
 .B "\-E, \-\-erase"
-Erase the flash device.
+Erase the flash ROM device.
 .TP
 .B "\-V, \-\-verbose"
 More verbose output.
 .TP
 .B "\-c, \-\-chip" 
-Probe only for specified flash chip.
+Probe only for specified flash ROM chip.
 .TP
 .B "\-s, \-\-estart" 
-Exclude start position. (obsolete)
+Exclude start position (obsolete).
 .TP
 .B "\-e, \-\-eend"  
-Exclude end postion. (obsolete)
+Exclude end postion (obsolete).
 .TP
 .B "\-m, \-\-mainboard" 
 Override mainboard settings. This option is needed for some mainboards,
@@ -63,12 +67,13 @@
 .\".B "\-\-version"
 .\"Show version information and exit.
 .SH BUGS
-Please report any bugs at http://tracker.coreboot.org/trac/coreboot/,
-or on the coreboot mailing list (http://www.coreboot.org/Mailinglist).
+Please report any bugs at
+.BR http://tracker.coreboot.org/trac/coreboot/newticket ","
+or on the coreboot mailing list
+.RB "(" http://coreboot.org/Mailinglist ")."
 .SH LICENCE
 .B flashrom
 is covered by the GNU General Public License (GPL), version 2 or later.
-.\" .SH SEE ALSO
 .SH COPYRIGHT
 2000 Silicon Integrated System Corporation
 .br
@@ -87,4 +92,4 @@
 some others 
 .PP
 This manual page was written by Uwe Hermann <[EMAIL PROTECTED]>.
-It is licensed under the terms of the GNU GPL (v2 or later).
+It is licensed under the terms of the GNU GPL (version 2 or later).


-- 
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[coreboot] r97 - buildrom-devel/packages

[svn]

Author: jcrouse
Date: 2008-01-18 18:01:03 +0100 (Fri, 18 Jan 2008)
New Revision: 97

Added:
   buildrom-devel/packages/coreboot-v2/
   buildrom-devel/packages/coreboot-v3/
Removed:
   buildrom-devel/packages/linuxbios/
   buildrom-devel/packages/linuxbiosv3/
Log:
Rename linuxbios and linuxbiosv3 to coreboot-v2 and coreboot-v3
respectively




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[coreboot] r3055 - trunk/util/lxbios

[svn]

Author: stepan
Date: 2008-01-18 16:33:49 +0100 (Fri, 18 Jan 2008)
New Revision: 3055

Modified:
   trunk/util/lxbios/ChangeLog
   trunk/util/lxbios/DISCLAIMER
   trunk/util/lxbios/README
   trunk/util/lxbios/cmos_lowlevel.c
   trunk/util/lxbios/cmos_lowlevel.h
   trunk/util/lxbios/cmos_ops.c
   trunk/util/lxbios/cmos_ops.h
   trunk/util/lxbios/common.c
   trunk/util/lxbios/common.h
   trunk/util/lxbios/compute_ip_checksum.c
   trunk/util/lxbios/input_file.c
   trunk/util/lxbios/input_file.h
   trunk/util/lxbios/ip_checksum.h
   trunk/util/lxbios/layout.c
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.c
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/lxbios/lbtable.h
   trunk/util/lxbios/linuxbios_tables.h
   trunk/util/lxbios/lxbios.1
   trunk/util/lxbios/lxbios.c
   trunk/util/lxbios/lxbios.spec
   trunk/util/lxbios/opts.c
   trunk/util/lxbios/opts.h
   trunk/util/lxbios/reg_expr.c
   trunk/util/lxbios/reg_expr.h
Log:
rename linuxbios -> coreboot
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/util/lxbios/ChangeLog
===
--- trunk/util/lxbios/ChangeLog 2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/ChangeLog 2008-01-18 15:33:49 UTC (rev 3055)
@@ -54,7 +54,7 @@
 
* Merge patch from Stefan Reinauer <[EMAIL PROTECTED]> that makes
  lxbios recognize the LB_TAG_OPTION_CHECKSUM entry placed in the
- LinuxBIOS table by newer versions of LinuxBIOS.
+ coreboot table by newer versions of LinuxBIOS.
 
* Tweak formatting of code to facilitate merging future patches.
 
@@ -121,11 +121,11 @@
 
Version 1.1.0.
 
-   * Added -l option for displaying entries from LinuxBIOS table.
+   * Added -l option for displaying entries from coreboot table.
 
-   * Added -d option for low-level dump of LinuxBIOS table.
+   * Added -d option for low-level dump of coreboot table.
 
-   * Improved code that searches for LinuxBIOS table.
+   * Improved code that searches for coreboot table.
 
 Wed Nov  6 09:30:00 PST 2002  David S. Peterson ([EMAIL PROTECTED])
 

Modified: trunk/util/lxbios/DISCLAIMER
===
--- trunk/util/lxbios/DISCLAIMER2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/DISCLAIMER2008-01-18 15:33:49 UTC (rev 3055)
@@ -8,8 +8,8 @@
 UCRL-CODE-2003-012
 All rights reserved.
 
-This file is part of lxbios, a utility for reading/writing LinuxBIOS
-parameters and displaying information from the LinuxBIOS table.
+This file is part of lxbios, a utility for reading/writing coreboot
+parameters and displaying information from the coreboot table.
 For details, see .
 
 This program is free software; you can redistribute it and/or modify it

Modified: trunk/util/lxbios/README
===
--- trunk/util/lxbios/README2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/README2008-01-18 15:33:49 UTC (rev 3055)
@@ -2,17 +2,17 @@
 
 Summary of Operation
 
-lxbios is a utility for reading/writing LinuxBIOS parameters and
-displaying information from the LinuxBIOS table.  It is intended for x86-based
-systems (both 32-bit and 64-bit) that use LinuxBIOS.
+lxbios is a utility for reading/writing coreboot parameters and
+displaying information from the coreboot table.  It is intended for x86-based
+systems (both 32-bit and 64-bit) that use coreboot.
 
-The LinuxBIOS table resides in low physical memory, and may be accessed
-through the /dev/mem interface.  It is created at boot time by LinuxBIOS, and
+The coreboot table resides in low physical memory, and may be accessed
+through the /dev/mem interface.  It is created at boot time by coreboot, and
 contains various system information such as the type of mainboard in use.  It
-specifies locations in the CMOS (nonvolatile RAM) where the LinuxBIOS
+specifies locations in the CMOS (nonvolatile RAM) where the coreboot
 parameters are stored.
 
-For information about LinuxBIOS, see http://www.linuxbios.org/.
+For information about coreboot, see http://www.coreboot.org/.
 
 Ideas for Future Improvements
 -

Modified: trunk/util/lxbios/cmos_lowlevel.c
===
--- trunk/util/lxbios/cmos_lowlevel.c   2008-01-18 15:33:10 UTC (rev 3054)
+++ trunk/util/lxbios/cmos_lowlevel.c   2008-01-18 15:33:49 UTC (rev 3055)
@@ -8,8 +8,8 @@
  *  UCRL-CODE-2003-012
  *  All rights reserved.
  *
- *  This file is part of lxbios, a utility for reading/writing LinuxBIOS
- *  parameters and displaying information from the LinuxBIOS table.
+ *  This file is part of lxbios, a utility for reading/writing coreboot
+ *  parameters and displaying information from the coreboot table.
  

[coreboot] r3060 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-18 19:04:28 +0100 (Fri, 18 Jan 2008)
New Revision: 3060

Modified:
   trunk/util/superiotool/README
   trunk/util/superiotool/superiotool.8
Log:
Document the --list-supported option. Various small fixes (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-18 17:48:51 UTC (rev 3059)
+++ trunk/util/superiotool/README   2008-01-18 18:04:28 UTC (rev 3060)
@@ -30,9 +30,10 @@
 Usage
 -
 
- $ superiotool [-d] [-V] [-v] [-h]
+ $ superiotool [-d] [-l] [-V] [-v] [-h]
 
  -d | --dumpDump Super I/O register contents
+ -l | --list-supported  Show the list of supported Super I/O chips
  -V | --verbose Verbose mode
  -v | --version Show the superiotool version
  -h | --helpShow a short help text
@@ -54,10 +55,12 @@
 Supported Super I/O Chips
 -
 
-Please see http://coreboot.org/Superiotool#Supported_devices.
+Please see http://coreboot.org/Superiotool#Supported_devices, or type
 
+ $ superiotool -l
+
 There's also a collection of sample register dumps from various Super I/O
-chips on that page. Please send further register dumps (either from a
+chips on that web page. Please send further register dumps (either from a
 proprietary BIOS and/or from coreboot) to the coreboot mailing list
 (http://coreboot.org/Mailinglist).
 
@@ -79,7 +82,7 @@
 refer to the respective source code files for details.
 
 It is licensed under the terms of the GNU General Public License (GPL),
-either version 2 of the License, or (at your option) any later version.
+either version 2 of the license, or (at your option) any later version.
 
 
 Contributors

Modified: trunk/util/superiotool/superiotool.8
===
--- trunk/util/superiotool/superiotool.82008-01-18 17:48:51 UTC (rev 
3059)
+++ trunk/util/superiotool/superiotool.82008-01-18 18:04:28 UTC (rev 
3060)
@@ -1,4 +1,4 @@
-.TH SUPERIOTOOL 8 "January 13, 2008"
+.TH SUPERIOTOOL 8 "January 18, 2008"
 .SH NAME
 superiotool \- Super I/O detection tool
 .SH SYNOPSIS
@@ -17,9 +17,10 @@
 It is mainly used for coreboot development purposes (see coreboot.org
 for details on coreboot), but it may also be useful for other things.
 .PP
-The list of supported Super I/O chips is available at:
-.br
-.B http://coreboot.org/Superiotool#Supported_devices
+The list of supported Super I/O chips is available at
+.BR http://coreboot.org/Superiotool#Supported_devices ","
+but it can also be viewed by running
+.BR "superiotool -l" "."
 .SH OPTIONS
 If no command line option is specified,
 .B superiotool
@@ -35,7 +36,7 @@
 .B "\-\-dump"
 option for this chip). The output will look something like this:
 .sp
-.B "$ ./superiotool -d"
+.B "$ superiotool -d"
 .br
 Found SMSC FDC37N769 (id=0x28, rev=0x01) at 0x3f0
 .br
@@ -75,7 +76,7 @@
 .B "\-l, \-\-list-supported"
 List all Super I/O chips recognized by
 .BR superiotool ". The phrase"
-.BR (dump available)
+.BR "(dump available)"
 following a chip name indicates that
 .B superiotool
 supports the
@@ -98,8 +99,10 @@
 .B "\-h, \-\-help"
 Show a help text and exit.
 .SH BUGS
-Please report any bugs at http://tracker.coreboot.org/trac/coreboot/
-or on the coreboot mailing list (http://coreboot.org/Mailinglist).
+Please report any bugs at
+.B http://tracker.coreboot.org/trac/coreboot/newticket
+or on the coreboot mailing list
+.RB "(" http://coreboot.org/Mailinglist ")."
 .SH AUTHORS
 Please see the individual source code files and/or the README file.
 .SH LICENCE


-- 
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] r100 - buildrom-devel/packages/kernel

[svn]

Author: myles
Date: 2008-01-18 19:39:21 +0100 (Fri, 18 Jan 2008)
New Revision: 100

Added:
   buildrom-devel/packages/kernel/alix1c.mk
   buildrom-devel/packages/kernel/m57sli.mk
   buildrom-devel/packages/kernel/msm800sev.mk
   buildrom-devel/packages/kernel/norwich.mk
   buildrom-devel/packages/kernel/olpc.mk
   buildrom-devel/packages/kernel/qemu.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-x86_64.mk
   buildrom-devel/packages/kernel/serengeti_cheetah.mk
   buildrom-devel/packages/kernel/supermicro-h8dmr.mk
   buildrom-devel/packages/kernel/tyan-s2882.mk
   buildrom-devel/packages/kernel/tyan-s2891.mk
Removed:
   buildrom-devel/packages/kernel/alix1c-kernel.mk
   buildrom-devel/packages/kernel/m57sli-kernel.mk
   buildrom-devel/packages/kernel/msm800sev-kernel.mk
   buildrom-devel/packages/kernel/norwich-kernel.mk
   buildrom-devel/packages/kernel/olpc-kernel.mk
   buildrom-devel/packages/kernel/qemu-kernel.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-kernel-x86_64.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-kernel.mk
   buildrom-devel/packages/kernel/supermicro-h8dmr-kernel.mk
   buildrom-devel/packages/kernel/tyan-s2882-kernel.mk
   buildrom-devel/packages/kernel/tyan-s2891-kernel.mk
Log:
This is the svn mv needed by the last change
svn mv packages/kernel/*-kernel.mk packages/kernel/*.mk

Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked by: Jordan Crouse <[EMAIL PROTECTED]>


Deleted: buildrom-devel/packages/kernel/alix1c-kernel.mk
===
--- buildrom-devel/packages/kernel/alix1c-kernel.mk 2008-01-18 18:33:20 UTC 
(rev 99)
+++ buildrom-devel/packages/kernel/alix1c-kernel.mk 2008-01-18 18:39:21 UTC 
(rev 100)
@@ -1,19 +0,0 @@
-# Build file for the PC Engines ALIX1.C LAB kernel
-
-KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
-KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
-KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-alix1c
-
-#TINY_DIR=$(PACKAGE_DIR)/kernel/patches/tiny
-#KERNEL_PATCHES += $(shell ls $(TINY_DIR)/*.patch)
-
-
-$(SOURCE_DIR)/$(KERNEL_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
-
-include $(PACKAGE_DIR)/kernel/kernel.inc
-
-kernel: generic-kernel
-kernel-clean: generic-kernel-clean
-kernel-distclean: generic-kernel-distclean

Copied: buildrom-devel/packages/kernel/alix1c.mk (from rev 98, 
buildrom-devel/packages/kernel/alix1c-kernel.mk)
===
--- buildrom-devel/packages/kernel/alix1c.mk(rev 0)
+++ buildrom-devel/packages/kernel/alix1c.mk2008-01-18 18:39:21 UTC (rev 
100)
@@ -0,0 +1,19 @@
+# Build file for the PC Engines ALIX1.C LAB kernel
+
+KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
+KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
+KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-alix1c
+
+#TINY_DIR=$(PACKAGE_DIR)/kernel/patches/tiny
+#KERNEL_PATCHES += $(shell ls $(TINY_DIR)/*.patch)
+
+
+$(SOURCE_DIR)/$(KERNEL_SOURCE):
+   @ mkdir -p $(SOURCE_DIR)
+   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
+
+include $(PACKAGE_DIR)/kernel/kernel.inc
+
+kernel: generic-kernel
+kernel-clean: generic-kernel-clean
+kernel-distclean: generic-kernel-distclean

Deleted: buildrom-devel/packages/kernel/m57sli-kernel.mk
===
--- buildrom-devel/packages/kernel/m57sli-kernel.mk 2008-01-18 18:33:20 UTC 
(rev 99)
+++ buildrom-devel/packages/kernel/m57sli-kernel.mk 2008-01-18 18:39:21 UTC 
(rev 100)
@@ -1,26 +0,0 @@
-# Build file for the GIGABYTE GA-M57SLI-S4 LAB kernel
-
-KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
-KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
-
-# KERNEL_CONFIG is defined in the platform configuration
-
-TINY_URL=http://elinux.org/images/0/0e/
-TINY_SOURCE=Tiny-quilt-2.6.22.1-1.tar.gz
-TINY_DIR=$(KERNEL_DIR)/tiny/patches
-
-KERNEL_PATCHES += $(TINY_DIR)
-
-$(SOURCE_DIR)/$(KERNEL_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
-
-$(SOURCE_DIR)/$(TINY_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(TINY_URL)/$(TINY_SOURCE)
-
-include $(PACKAGE_DIR)/kernel/kernel.inc
-
-kernel: generic-kernel
-kernel-clean: generic-kernel-clean
-kernel-distclean: generic-kernel-distclean

Copied: buildrom-devel/packages/kernel/m57sli.mk (from rev 98, 
buildrom-devel/packages/kernel/m57sli-kernel.mk)
===
--- buildrom-devel/packages/kernel/m57sli.mk(rev 0)
+++ buildrom-devel/packages/kernel/m57sli.mk2008-01-18 18:39:21 UTC (rev 
100)
@@ -0,0 +1,26 @@
+# Build file for the GIGABYTE GA-M57SLI-S4 LAB kernel
+
+KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
+KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
+
+# KERNEL_CONFIG is defined in the platform c

[coreboot] r100 - buildrom-devel/packages/kernel

[svn]

Author: myles
Date: 2008-01-18 19:39:21 +0100 (Fri, 18 Jan 2008)
New Revision: 100

Added:
   buildrom-devel/packages/kernel/alix1c.mk
   buildrom-devel/packages/kernel/m57sli.mk
   buildrom-devel/packages/kernel/msm800sev.mk
   buildrom-devel/packages/kernel/norwich.mk
   buildrom-devel/packages/kernel/olpc.mk
   buildrom-devel/packages/kernel/qemu.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-x86_64.mk
   buildrom-devel/packages/kernel/serengeti_cheetah.mk
   buildrom-devel/packages/kernel/supermicro-h8dmr.mk
   buildrom-devel/packages/kernel/tyan-s2882.mk
   buildrom-devel/packages/kernel/tyan-s2891.mk
Removed:
   buildrom-devel/packages/kernel/alix1c-kernel.mk
   buildrom-devel/packages/kernel/m57sli-kernel.mk
   buildrom-devel/packages/kernel/msm800sev-kernel.mk
   buildrom-devel/packages/kernel/norwich-kernel.mk
   buildrom-devel/packages/kernel/olpc-kernel.mk
   buildrom-devel/packages/kernel/qemu-kernel.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-kernel-x86_64.mk
   buildrom-devel/packages/kernel/serengeti_cheetah-kernel.mk
   buildrom-devel/packages/kernel/supermicro-h8dmr-kernel.mk
   buildrom-devel/packages/kernel/tyan-s2882-kernel.mk
   buildrom-devel/packages/kernel/tyan-s2891-kernel.mk
Log:
This is the svn mv needed by the last change
svn mv packages/kernel/*-kernel.mk packages/kernel/*.mk

Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked by: Jordan Crouse <[EMAIL PROTECTED]>


Deleted: buildrom-devel/packages/kernel/alix1c-kernel.mk
===
--- buildrom-devel/packages/kernel/alix1c-kernel.mk 2008-01-18 18:33:20 UTC 
(rev 99)
+++ buildrom-devel/packages/kernel/alix1c-kernel.mk 2008-01-18 18:39:21 UTC 
(rev 100)
@@ -1,19 +0,0 @@
-# Build file for the PC Engines ALIX1.C LAB kernel
-
-KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
-KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
-KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-alix1c
-
-#TINY_DIR=$(PACKAGE_DIR)/kernel/patches/tiny
-#KERNEL_PATCHES += $(shell ls $(TINY_DIR)/*.patch)
-
-
-$(SOURCE_DIR)/$(KERNEL_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
-
-include $(PACKAGE_DIR)/kernel/kernel.inc
-
-kernel: generic-kernel
-kernel-clean: generic-kernel-clean
-kernel-distclean: generic-kernel-distclean

Copied: buildrom-devel/packages/kernel/alix1c.mk (from rev 98, 
buildrom-devel/packages/kernel/alix1c-kernel.mk)
===
--- buildrom-devel/packages/kernel/alix1c.mk(rev 0)
+++ buildrom-devel/packages/kernel/alix1c.mk2008-01-18 18:39:21 UTC (rev 
100)
@@ -0,0 +1,19 @@
+# Build file for the PC Engines ALIX1.C LAB kernel
+
+KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
+KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
+KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-alix1c
+
+#TINY_DIR=$(PACKAGE_DIR)/kernel/patches/tiny
+#KERNEL_PATCHES += $(shell ls $(TINY_DIR)/*.patch)
+
+
+$(SOURCE_DIR)/$(KERNEL_SOURCE):
+   @ mkdir -p $(SOURCE_DIR)
+   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
+
+include $(PACKAGE_DIR)/kernel/kernel.inc
+
+kernel: generic-kernel
+kernel-clean: generic-kernel-clean
+kernel-distclean: generic-kernel-distclean

Deleted: buildrom-devel/packages/kernel/m57sli-kernel.mk
===
--- buildrom-devel/packages/kernel/m57sli-kernel.mk 2008-01-18 18:33:20 UTC 
(rev 99)
+++ buildrom-devel/packages/kernel/m57sli-kernel.mk 2008-01-18 18:39:21 UTC 
(rev 100)
@@ -1,26 +0,0 @@
-# Build file for the GIGABYTE GA-M57SLI-S4 LAB kernel
-
-KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
-KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
-
-# KERNEL_CONFIG is defined in the platform configuration
-
-TINY_URL=http://elinux.org/images/0/0e/
-TINY_SOURCE=Tiny-quilt-2.6.22.1-1.tar.gz
-TINY_DIR=$(KERNEL_DIR)/tiny/patches
-
-KERNEL_PATCHES += $(TINY_DIR)
-
-$(SOURCE_DIR)/$(KERNEL_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(KERNEL_URL)/$(KERNEL_SOURCE)
-
-$(SOURCE_DIR)/$(TINY_SOURCE):
-   @ mkdir -p $(SOURCE_DIR)
-   @ wget -P $(SOURCE_DIR) $(TINY_URL)/$(TINY_SOURCE)
-
-include $(PACKAGE_DIR)/kernel/kernel.inc
-
-kernel: generic-kernel
-kernel-clean: generic-kernel-clean
-kernel-distclean: generic-kernel-distclean

Copied: buildrom-devel/packages/kernel/m57sli.mk (from rev 98, 
buildrom-devel/packages/kernel/m57sli-kernel.mk)
===
--- buildrom-devel/packages/kernel/m57sli.mk(rev 0)
+++ buildrom-devel/packages/kernel/m57sli.mk2008-01-18 18:39:21 UTC (rev 
100)
@@ -0,0 +1,26 @@
+# Build file for the GIGABYTE GA-M57SLI-S4 LAB kernel
+
+KERNEL_URL=http://kernel.org/pub/linux/kernel/v2.6/
+KERNEL_SOURCE=linux-$(KERNEL_VERSION).tar.bz2
+
+# KERNEL_CONFIG is defined in the platform c

[coreboot] r99 - buildrom-devel/config/platforms

[svn]

Author: myles
Date: 2008-01-18 19:33:20 +0100 (Fri, 18 Jan 2008)
New Revision: 99

Modified:
   buildrom-devel/config/platforms/alix1c.conf
   buildrom-devel/config/platforms/db800.conf
   buildrom-devel/config/platforms/dbe61.conf
   buildrom-devel/config/platforms/m57sli.conf
   buildrom-devel/config/platforms/msm800sev.conf
   buildrom-devel/config/platforms/norwich.conf
   buildrom-devel/config/platforms/qemu.conf
   buildrom-devel/config/platforms/serengeti_cheetah.conf
   buildrom-devel/config/platforms/supermicro-h8dmr.conf
   buildrom-devel/config/platforms/tyan-s2882.conf
   buildrom-devel/config/platforms/tyan-s2891.conf
Log:
This patch changes board.conf files so that we can use BOARD_NAME.mk
instead of BOARD_NAME-kernel.mk for every board.

It also removes an unused variable in qemu.conf and regroups another.

This patch needs to be followed with an svn mv
packages/kernel/*-kernel.mk packages/kernel/*.mk

Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked by: Jordan Crouse <[EMAIL PROTECTED]>


Modified: buildrom-devel/config/platforms/alix1c.conf
===
--- buildrom-devel/config/platforms/alix1c.conf 2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/alix1c.conf 2008-01-18 18:33:20 UTC (rev 99)
@@ -11,7 +11,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/alix1c-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/alix1c.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/alix1c.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/db800.conf
===
--- buildrom-devel/config/platforms/db800.conf  2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/db800.conf  2008-01-18 18:33:20 UTC (rev 99)
@@ -13,7 +13,7 @@
 # Targets
 # Use the same settings as the Norwich platform
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/dbe61.conf
===
--- buildrom-devel/config/platforms/dbe61.conf  2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/dbe61.conf  2008-01-18 18:33:20 UTC (rev 99)
@@ -13,7 +13,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/m57sli.conf
===
--- buildrom-devel/config/platforms/m57sli.conf 2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/m57sli.conf 2008-01-18 18:33:20 UTC (rev 99)
@@ -16,7 +16,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/m57sli-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/m57sli.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/m57sli.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/msm800sev.conf
===
--- buildrom-devel/config/platforms/msm800sev.conf  2008-01-18 17:06:48 UTC 
(rev 98)
+++ buildrom-devel/config/platforms/msm800sev.conf  2008-01-18 18:33:20 UTC 
(rev 99)
@@ -12,7 +12,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/msm800sev-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/msm800sev.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/msm800sev.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/norwich.conf
===
--- buildrom-devel/config/platforms/norwich.conf2008-01-18 17:06:48 UTC 
(rev 98)
+++ buildrom-devel/config/platforms/norwich.conf2008-01-18 18:33:20 UTC 
(rev 99)
@@ -12,7 +12,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/norwich.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/norwich.mk
 
 # kernel configuration (for LAB)

Modified: buildrom-devel/config/platforms/qemu.conf
===
--- buildrom-devel/config/platforms/qemu.conf   2008-01-18 17:06:48 UTC (rev 98)
+++ buildrom-devel/config/platforms/qemu.conf   2008-01-18 18:33:20 UTC (rev 99)
@@ -11,7 +11,7 @@
 
 # Targets
 
-KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu-kernel.mk
+KERNEL_MK=$(PACKAGE_DIR)/kernel/qemu.mk
 CBV2_MK=$(PACKAGE_DIR)/coreboot-v2/qemu.mk
 
 # kernel configuration (for LAB)
@@ -26,14 +26,13 @@
 # coreboot-v2 configuration
 CBV2_TAG=2950
 CBV2_CONFIG=Config.lb
-COREBOOT_ROM_NAME=qemu.rom
 CBV2_TDIR=qemu-i386
 
 # coreboot v3 configuration
 CBV3_CONFIG=qemu-i386-defconfig
 CBV3_TAG=HEAD
-CBV3_ROM_NAME=linuxbios.rom
 
+COREBOOT_ROM_NAME=qemu.rom
 COREBOOT_VENDOR=emulation
 COREBOOT_BOARD=qemu-i386
 

Modified: buildrom-devel/config/platforms/serengeti_

[coreboot] r557 - in coreboot-v3: device include/device util/dtc

[svn]

Author: rminnich
Date: 2008-01-19 07:29:14 +0100 (Sat, 19 Jan 2008)
New Revision: 557

Modified:
   coreboot-v3/device/device.c
   coreboot-v3/include/device/device.h
   coreboot-v3/include/device/pci.h
   coreboot-v3/util/dtc/flattree.c
Log:
include/device/device.h:
Change the ID constants so they are more useful for debugging. 
Instead of simple 1,2,3 they now are a 4-byte value which can be more
useful when looking at memory with a debugger. Lots of variables can be 
'1', but fewer variables will match to 'PCID'. 

include/device/pci.h: 
Include pci_ids.h in pci.h

device/device.c: remove silly comment. Change memcpy to struct assign, this 
makes it possible 
for the C compiler to do type checking. Add assign for the dev->id. 

flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. 
These IDs will be assigned
to the static tree device struct. In conjunction with the earlier patch, this 
change removes the need
for users to assign the ops struct member in the dts by hand, as it is done in 
the qemu port today. 
The ops struct member will automatically be assigned by the dev_init function, 
which is run 
in stage2 before any actual device code is run. (This change to dev_init was in 
the previous patch). 
Added two comments that document what is going on. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: coreboot-v3/device/device.c
===
--- coreboot-v3/device/device.c 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/device/device.c 2008-01-19 06:29:14 UTC (rev 557)
@@ -209,11 +209,12 @@
}
 
dev = new_device();
-   if (!dev) /* Please don't do this at home */
+   if (!dev)
goto out;
 
memset(dev, 0, sizeof(*dev));
-   memcpy(&dev->path, path, sizeof(*path));
+   dev->path = *path;
+   dev->id = *devid;
 
/* Initialize the back pointers in the link fields. */
for (link = 0; link < MAX_LINKS; link++) {

Modified: coreboot-v3/include/device/device.h
===
--- coreboot-v3/include/device/device.h 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/include/device/device.h 2008-01-19 06:29:14 UTC (rev 557)
@@ -25,18 +25,28 @@
 #include 
 #include 
 
+/**
+ * Create a 32-bit value from four characters. This is better
+ * than the usual enum values when using (JTAG) debuggers.
+ * It also makes it harder for accidentally assigned type values
+ * to be mistaken for a real value -- e.g. it is more likely in the event
+ * of a programming error that a '1' is somehow assigned
+ * to the type field, whereas these values are more complex. 
+ * Thus errors may be easier to find. 
+ */
+#define TYPENAME(a,b,c,d) ((a<<24)|(b<<16)|(c<<8)|(d))
 #define DEVICE_ID_MAX 64
 enum device_id_type {
-   DEVICE_ID_NONE = 0,
-   DEVICE_ID_ROOT,
-   DEVICE_ID_PCI,
-   DEVICE_ID_PNP,
-   DEVICE_ID_I2C,
-   DEVICE_ID_APIC,
-   DEVICE_ID_PCI_DOMAIN,
-   DEVICE_ID_APIC_CLUSTER,
-   DEVICE_ID_CPU,
-   DEVICE_ID_CPU_BUS,
+   DEVICE_ID_NONE  = 0,
+   DEVICE_ID_ROOT  = TYPENAME('R','O','O','T'),
+   DEVICE_ID_PCI   = TYPENAME(' ','P','C','I'),
+   DEVICE_ID_PNP   = TYPENAME(' ','P','N','P'),
+   DEVICE_ID_I2C   = TYPENAME(' ','I','2','C'),
+   DEVICE_ID_APIC  = TYPENAME('A','P','I','C'),
+   DEVICE_ID_PCI_DOMAIN = TYPENAME('P','C','I','D'),
+   DEVICE_ID_APIC_CLUSTER = TYPENAME('A','P','C','C'),
+   DEVICE_ID_CPU = TYPENAME(' ','C','P','U'),
+   DEVICE_ID_CPU_BUS =  TYPENAME(' ','B','U','S'),
 };
 
 struct device;

Modified: coreboot-v3/include/device/pci.h
===
--- coreboot-v3/include/device/pci.h2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/include/device/pci.h2008-01-19 06:29:14 UTC (rev 557)
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * For more information, please consult the following manuals (look at

Modified: coreboot-v3/util/dtc/flattree.c
===
--- coreboot-v3/util/dtc/flattree.c 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/util/dtc/flattree.c 2008-01-19 06:29:14 UTC (rev 557)
@@ -532,7 +532,33 @@
if (tree->config){
configname = clean(tree->label, 0);
printf("\t.device_configuration = &%s,\n", configname);
+   /* The config property list for a device is derived from the
+* device dts, e.g. northbridge/intel/i440bx/dts, not the
+* mainboard dts. 
+* Almost all of these properties are specific to the device. 
+* Some, such as the device id, are part of the common
+* device struct. Check the config properties and 
+* pull out those properties that are

[coreboot] r557 - in coreboot-v3: device include/device util/dtc

[svn]

Author: rminnich
Date: 2008-01-19 07:29:14 +0100 (Sat, 19 Jan 2008)
New Revision: 557

Modified:
   coreboot-v3/device/device.c
   coreboot-v3/include/device/device.h
   coreboot-v3/include/device/pci.h
   coreboot-v3/util/dtc/flattree.c
Log:
include/device/device.h:
Change the ID constants so they are more useful for debugging. 
Instead of simple 1,2,3 they now are a 4-byte value which can be more
useful when looking at memory with a debugger. Lots of variables can be 
'1', but fewer variables will match to 'PCID'. 

include/device/pci.h: 
Include pci_ids.h in pci.h

device/device.c: remove silly comment. Change memcpy to struct assign, this 
makes it possible 
for the C compiler to do type checking. Add assign for the dev->id. 

flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. 
These IDs will be assigned
to the static tree device struct. In conjunction with the earlier patch, this 
change removes the need
for users to assign the ops struct member in the dts by hand, as it is done in 
the qemu port today. 
The ops struct member will automatically be assigned by the dev_init function, 
which is run 
in stage2 before any actual device code is run. (This change to dev_init was in 
the previous patch). 
Added two comments that document what is going on. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: coreboot-v3/device/device.c
===
--- coreboot-v3/device/device.c 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/device/device.c 2008-01-19 06:29:14 UTC (rev 557)
@@ -209,11 +209,12 @@
}
 
dev = new_device();
-   if (!dev) /* Please don't do this at home */
+   if (!dev)
goto out;
 
memset(dev, 0, sizeof(*dev));
-   memcpy(&dev->path, path, sizeof(*path));
+   dev->path = *path;
+   dev->id = *devid;
 
/* Initialize the back pointers in the link fields. */
for (link = 0; link < MAX_LINKS; link++) {

Modified: coreboot-v3/include/device/device.h
===
--- coreboot-v3/include/device/device.h 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/include/device/device.h 2008-01-19 06:29:14 UTC (rev 557)
@@ -25,18 +25,28 @@
 #include 
 #include 
 
+/**
+ * Create a 32-bit value from four characters. This is better
+ * than the usual enum values when using (JTAG) debuggers.
+ * It also makes it harder for accidentally assigned type values
+ * to be mistaken for a real value -- e.g. it is more likely in the event
+ * of a programming error that a '1' is somehow assigned
+ * to the type field, whereas these values are more complex. 
+ * Thus errors may be easier to find. 
+ */
+#define TYPENAME(a,b,c,d) ((a<<24)|(b<<16)|(c<<8)|(d))
 #define DEVICE_ID_MAX 64
 enum device_id_type {
-   DEVICE_ID_NONE = 0,
-   DEVICE_ID_ROOT,
-   DEVICE_ID_PCI,
-   DEVICE_ID_PNP,
-   DEVICE_ID_I2C,
-   DEVICE_ID_APIC,
-   DEVICE_ID_PCI_DOMAIN,
-   DEVICE_ID_APIC_CLUSTER,
-   DEVICE_ID_CPU,
-   DEVICE_ID_CPU_BUS,
+   DEVICE_ID_NONE  = 0,
+   DEVICE_ID_ROOT  = TYPENAME('R','O','O','T'),
+   DEVICE_ID_PCI   = TYPENAME(' ','P','C','I'),
+   DEVICE_ID_PNP   = TYPENAME(' ','P','N','P'),
+   DEVICE_ID_I2C   = TYPENAME(' ','I','2','C'),
+   DEVICE_ID_APIC  = TYPENAME('A','P','I','C'),
+   DEVICE_ID_PCI_DOMAIN = TYPENAME('P','C','I','D'),
+   DEVICE_ID_APIC_CLUSTER = TYPENAME('A','P','C','C'),
+   DEVICE_ID_CPU = TYPENAME(' ','C','P','U'),
+   DEVICE_ID_CPU_BUS =  TYPENAME(' ','B','U','S'),
 };
 
 struct device;

Modified: coreboot-v3/include/device/pci.h
===
--- coreboot-v3/include/device/pci.h2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/include/device/pci.h2008-01-19 06:29:14 UTC (rev 557)
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /*
  * For more information, please consult the following manuals (look at

Modified: coreboot-v3/util/dtc/flattree.c
===
--- coreboot-v3/util/dtc/flattree.c 2008-01-17 16:32:12 UTC (rev 556)
+++ coreboot-v3/util/dtc/flattree.c 2008-01-19 06:29:14 UTC (rev 557)
@@ -532,7 +532,33 @@
if (tree->config){
configname = clean(tree->label, 0);
printf("\t.device_configuration = &%s,\n", configname);
+   /* The config property list for a device is derived from the
+* device dts, e.g. northbridge/intel/i440bx/dts, not the
+* mainboard dts. 
+* Almost all of these properties are specific to the device. 
+* Some, such as the device id, are part of the common
+* device struct. Check the config properties and 
+* pull out those properties that are

[coreboot] r3063 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-19 10:40:17 +0100 (Sat, 19 Jan 2008)
New Revision: 3063

Modified:
   trunk/util/superiotool/winbond.c
Log:
Small superiotool fix to detect more Winbond W83627EHF chips. The
patch is tested on actual hardware.

As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).

So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/winbond.c
===
--- trunk/util/superiotool/winbond.c2008-01-19 00:32:07 UTC (rev 3062)
+++ trunk/util/superiotool/winbond.c2008-01-19 09:40:17 UTC (rev 3063)
@@ -195,54 +195,6 @@
{0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00,
 EOT}},
{EOT}}},
-   {0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */
-   {NOLDN, NULL,
-   {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
-0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
-   {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
-0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}},
-   {0x0, "Floppy",
-   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
-0xf5,EOT},
-   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,
-0x00,EOT}},
-   {0x1, "Parallel port",
-   {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
-   {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
-   {0x2, "COM1",
-   {0x30,0x60,0x61,0x70,0xf0,EOT},
-   {0x01,0x03,0xf8,0x04,0x00,EOT}},
-   {0x3, "COM2",
-   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
-   {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
-   {0x5, "Keyboard",
-   {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
-   {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}},
-   {0x6, "Serial flash interface",
-   {0x30,0x62,0x63,EOT},
-   {0x00,0x00,0x00,EOT}},
-   {0x7, "GPIO 1, GPIO 6, game port, MIDI port",
-   {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
-0xf4,0xf5,0xf6,0xf7,EOT},
-   {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,0x00,
-0xff,0x00,0x00,0x00,EOT}},
-   {0x8, "WDTO#, PLED",
-   {0x30,0xf5,0xf6,0xf7,EOT},
-   {0x00,0x00,0x00,0x00,EOT}},
-   {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED",
-   {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xf0,0xf1,0xf2,
-0xf3,0xf4,0xf5,0xf6,0xf7,EOT},
-   {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,
-0x00,0xff,0x00,0x00,0x00,EOT}},
-   {0xa, "ACPI",
-   {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
-0xe8,0xf2,0xf3,0xf4,0xf6,0xf7,EOT},
-   {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x00,0x00,
-RSVD,0x7c,0x00,0x00,0x00,0x00,EOT}},
-   {0xb, "Hardware monitor",
-   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
-   {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}},
-   {EOT}}},
{0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */
{EOT}}},
 
@@ -412,6 +364,61 @@
{0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT},
{0x00,0x00,0x00,0xff,0x00,0x00,EOT}},
{EOT}}},
+   {0x88, "W83627EHF/EF/EHG/EG", {
+   /*
+* As per datasheet the ID should be 0x886? here.
+* Not mentioned in the datasheet, but sensors-detect says
+* 0x8853 is also possible. Also, the ASUS A8V-E Deluxe
+* (W83627EHF) has an ID of 0x8854 (verified on hardware).
+* So we now assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
+*/
+   {NOLDN, NULL,
+   {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
+0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+   {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
+0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}},
+   {0x0, "Floppy",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
+0xf5,EOT},
+   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,
+0x00,EOT}},
+  

[coreboot] r3063 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-19 10:40:17 +0100 (Sat, 19 Jan 2008)
New Revision: 3063

Modified:
   trunk/util/superiotool/winbond.c
Log:
Small superiotool fix to detect more Winbond W83627EHF chips. The
patch is tested on actual hardware.

As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).

So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/winbond.c
===
--- trunk/util/superiotool/winbond.c2008-01-19 00:32:07 UTC (rev 3062)
+++ trunk/util/superiotool/winbond.c2008-01-19 09:40:17 UTC (rev 3063)
@@ -195,54 +195,6 @@
{0x00,0x48,0x48,0x48,0x48,0x00,0x00,0x48,0x00,0x00,
 EOT}},
{EOT}}},
-   {0x886, "W83627EHF/EF/EHG/EG", { /* sensors-detect: 0x8853 possible */
-   {NOLDN, NULL,
-   {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
-0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
-   {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
-0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}},
-   {0x0, "Floppy",
-   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
-0xf5,EOT},
-   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,
-0x00,EOT}},
-   {0x1, "Parallel port",
-   {0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
-   {0x01,0x03,0x78,0x07,0x04,0x3f,EOT}},
-   {0x2, "COM1",
-   {0x30,0x60,0x61,0x70,0xf0,EOT},
-   {0x01,0x03,0xf8,0x04,0x00,EOT}},
-   {0x3, "COM2",
-   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
-   {0x01,0x02,0xf8,0x03,0x00,0x00,EOT}},
-   {0x5, "Keyboard",
-   {0x30,0x60,0x61,0x62,0x63,0x70,0x72,0xf0,EOT},
-   {0x01,0x00,0x60,0x00,0x64,0x01,0x0c,0x83,EOT}},
-   {0x6, "Serial flash interface",
-   {0x30,0x62,0x63,EOT},
-   {0x00,0x00,0x00,EOT}},
-   {0x7, "GPIO 1, GPIO 6, game port, MIDI port",
-   {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,0xf3,
-0xf4,0xf5,0xf6,0xf7,EOT},
-   {0x00,0x02,0x01,0x03,0x30,0x09,0xff,0x00,0x00,0x00,
-0xff,0x00,0x00,0x00,EOT}},
-   {0x8, "WDTO#, PLED",
-   {0x30,0xf5,0xf6,0xf7,EOT},
-   {0x00,0x00,0x00,0x00,EOT}},
-   {0x9, "GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED",
-   {0x30,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xf0,0xf1,0xf2,
-0xf3,0xf4,0xf5,0xf6,0xf7,EOT},
-   {0x00,0xff,0x00,0x00,0xff,0x00,0x00,0xff,0x00,0x00,
-0x00,0xff,0x00,0x00,0x00,EOT}},
-   {0xa, "ACPI",
-   {0x30,0x70,0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,
-0xe8,0xf2,0xf3,0xf4,0xf6,0xf7,EOT},
-   {0x00,0x00,0x01,0x00,0xff,0x08,0x00,RSVD,0x00,0x00,
-RSVD,0x7c,0x00,0x00,0x00,0x00,EOT}},
-   {0xb, "Hardware monitor",
-   {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
-   {0x00,0x00,0x00,0x00,0xc1,0x00,EOT}},
-   {EOT}}},
{0xa23, "W83627UHG", {/* TODO: Not yet in sensors-detect */
{EOT}}},
 
@@ -412,6 +364,61 @@
{0x30,0x60,0x61,0xf0,0xf1,0xf2,EOT},
{0x00,0x00,0x00,0xff,0x00,0x00,EOT}},
{EOT}}},
+   {0x88, "W83627EHF/EF/EHG/EG", {
+   /*
+* As per datasheet the ID should be 0x886? here.
+* Not mentioned in the datasheet, but sensors-detect says
+* 0x8853 is also possible. Also, the ASUS A8V-E Deluxe
+* (W83627EHF) has an ID of 0x8854 (verified on hardware).
+* So we now assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
+*/
+   {NOLDN, NULL,
+   {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,
+0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},
+   {0x88,MISC,0xff,0x00,MISC,0x00,MISC,RSVD,0x50,
+0x04,0x00,RSVD,0x00,0x21,0x00,0x00,EOT}},
+   {0x0, "Floppy",
+   {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4,
+0xf5,EOT},
+   {0x01,0x03,0xf0,0x06,0x02,0x8e,0x00,0xff,0x00,
+0x00,EOT}},
+  

[coreboot] r3064 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-19 10:43:48 +0100 (Sat, 19 Jan 2008)
New Revision: 3064

Modified:
   trunk/util/superiotool/README
Log:
Add Bingxun Shi <[EMAIL PROTECTED]> to the list of contributors (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-19 09:40:17 UTC (rev 3063)
+++ trunk/util/superiotool/README   2008-01-19 09:43:48 UTC (rev 3064)
@@ -88,6 +88,7 @@
 Contributors
 
 
+Bingxun Shi <[EMAIL PROTECTED]>
 Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
 David Hendricks <[EMAIL PROTECTED]>
 Frieder Ferlemann <[EMAIL PROTECTED]>


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[coreboot] r3064 - trunk/util/superiotool

[svn]

Author: uwe
Date: 2008-01-19 10:43:48 +0100 (Sat, 19 Jan 2008)
New Revision: 3064

Modified:
   trunk/util/superiotool/README
Log:
Add Bingxun Shi <[EMAIL PROTECTED]> to the list of contributors (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/superiotool/README
===
--- trunk/util/superiotool/README   2008-01-19 09:40:17 UTC (rev 3063)
+++ trunk/util/superiotool/README   2008-01-19 09:43:48 UTC (rev 3064)
@@ -88,6 +88,7 @@
 Contributors
 
 
+Bingxun Shi <[EMAIL PROTECTED]>
 Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
 David Hendricks <[EMAIL PROTECTED]>
 Frieder Ferlemann <[EMAIL PROTECTED]>


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[coreboot] r42 - trunk/filo-0.5

[svn]

Author: uwe
Date: 2008-01-19 22:08:06 +0100 (Sat, 19 Jan 2008)
New Revision: 42

Modified:
   trunk/filo-0.5/Makefile
Log:
Properly cleanup null.o and builtin.o upon 'make clean'.

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>



Modified: trunk/filo-0.5/Makefile
===
--- trunk/filo-0.5/Makefile 2008-01-16 14:40:04 UTC (rev 41)
+++ trunk/filo-0.5/Makefile 2008-01-19 21:08:06 UTC (rev 42)
@@ -60,7 +60,7 @@
+$(MAKE) -C $(patsubst _clean_%,%,$@) clean
 
 clean: $(SUBDIRS_CLEAN)
-   rm -f filo.elf filo config.h filo.iso
+   rm -f filo.elf filo config.h filo.iso null.o builtin.o
 
 distclean: clean
rm -f Config Config.bak include/arch


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[coreboot] r42 - trunk/filo-0.5

[svn]

Author: uwe
Date: 2008-01-19 22:08:06 +0100 (Sat, 19 Jan 2008)
New Revision: 42

Modified:
   trunk/filo-0.5/Makefile
Log:
Properly cleanup null.o and builtin.o upon 'make clean'.

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>



Modified: trunk/filo-0.5/Makefile
===
--- trunk/filo-0.5/Makefile 2008-01-16 14:40:04 UTC (rev 41)
+++ trunk/filo-0.5/Makefile 2008-01-19 21:08:06 UTC (rev 42)
@@ -60,7 +60,7 @@
+$(MAKE) -C $(patsubst _clean_%,%,$@) clean
 
 clean: $(SUBDIRS_CLEAN)
-   rm -f filo.elf filo config.h filo.iso
+   rm -f filo.elf filo config.h filo.iso null.o builtin.o
 
 distclean: clean
rm -f Config Config.bak include/arch


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[coreboot] r3065 - trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10

[svn]

Author: stepan
Date: 2008-01-20 01:24:23 +0100 (Sun, 20 Jan 2008)
New Revision: 3065

Modified:
   trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
Log:
give it 2k more space for abuild. let's look into this anyways, but get rid of
the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===
--- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-19 09:43:48 UTC (rev 3064)
+++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 00:24:23 UTC (rev 3065)
@@ -13,7 +13,7 @@
 
 romimage "fallback" 
option USE_FALLBACK_IMAGE=1
-   option ROM_IMAGE_SIZE=0x2
+   option ROM_IMAGE_SIZE=0x20800
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
 end
@@ -26,4 +26,4 @@
option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
\ No newline at end of file
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"


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[coreboot] r3065 - trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10

[svn]

Author: stepan
Date: 2008-01-20 01:24:23 +0100 (Sun, 20 Jan 2008)
New Revision: 3065

Modified:
   trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
Log:
give it 2k more space for abuild. let's look into this anyways, but get rid of
the impression that the cheetah on fam10 is broken just because we're using a
too new compiler for abuild. (trivial)

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===
--- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-19 09:43:48 UTC (rev 3064)
+++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 00:24:23 UTC (rev 3065)
@@ -13,7 +13,7 @@
 
 romimage "fallback" 
option USE_FALLBACK_IMAGE=1
-   option ROM_IMAGE_SIZE=0x2
+   option ROM_IMAGE_SIZE=0x20800
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
 end
@@ -26,4 +26,4 @@
option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
\ No newline at end of file
+buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"


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[coreboot] r3066 - trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10

[svn]

Author: stepan
Date: 2008-01-20 02:59:43 +0100 (Sun, 20 Jan 2008)
New Revision: 3066

Modified:
   trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
Log:
last try i hope. Building with a payload changes the result of the rom
image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===
--- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 00:24:23 UTC (rev 3065)
+++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 01:59:43 UTC (rev 3066)
@@ -13,7 +13,7 @@
 
 romimage "fallback" 
option USE_FALLBACK_IMAGE=1
-   option ROM_IMAGE_SIZE=0x20800
+   option ROM_IMAGE_SIZE=0x21000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
 end


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[coreboot] r3066 - trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10

[svn]

Author: stepan
Date: 2008-01-20 02:59:43 +0100 (Sun, 20 Jan 2008)
New Revision: 3066

Modified:
   trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
Log:
last try i hope. Building with a payload changes the result of the rom
image. Even if the rom image size is not changed, it can make the linking fail.
It's almost a heisen-bug, only there if you don't watch.

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
===
--- trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 00:24:23 UTC (rev 3065)
+++ trunk/coreboot-v2/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb  
2008-01-20 01:59:43 UTC (rev 3066)
@@ -13,7 +13,7 @@
 
 romimage "fallback" 
option USE_FALLBACK_IMAGE=1
-   option ROM_IMAGE_SIZE=0x20800
+   option ROM_IMAGE_SIZE=0x21000
option COREBOOT_EXTRA_VERSION=".0-fallback"
payload __PAYLOAD__
 end


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[coreboot] r558 - in coreboot-v3: device include/device northbridge/amd/geodelx southbridge/amd/cs5536 util/x86emu

[svn]

Author: hailfinger
Date: 2008-01-21 00:03:40 +0100 (Mon, 21 Jan 2008)
New Revision: 558

Modified:
   coreboot-v3/device/device_util.c
   coreboot-v3/device/pci_device.c
   coreboot-v3/device/pci_rom.c
   coreboot-v3/include/device/device.h
   coreboot-v3/northbridge/amd/geodelx/dts
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
   coreboot-v3/southbridge/amd/cs5536/dts
   coreboot-v3/util/x86emu/vm86.c
Log:
include/device/device.h
Remove old vendor,device struct members since we are now using the
device_id struct. 
Change declaration of dev_find_device to use device_id struct. 

device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users. 

device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id. 
Change prints of dev->vendor, dev->device to use the 
dev_id_string function. 

device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id. 

southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device

southbridge/amd/cs5536/dts
Add pciid of the cs5536

northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge. 

util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device

With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time. 
We are still failing in "Finding PCI configuration type"

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/device/device_util.c
===
--- coreboot-v3/device/device_util.c2008-01-19 06:29:14 UTC (rev 557)
+++ coreboot-v3/device/device_util.c2008-01-20 23:03:40 UTC (rev 558)
@@ -115,27 +115,52 @@
 /**
  * Find a device of a given vendor and type.
  *
- * @param vendor Vendor ID (e.g. 0x8086 for Intel)
- * @param device Device ID
+ * @param devid Pointer to device_id struct 
  * @param from Pointer to the device structure, used as a starting point
  * in the linked list of all_devices, which can be 0 to start
  * at the head of the list (i.e. all_devices).
  * @return Pointer to the device struct.
  */
-struct device *dev_find_device(unsigned int vendor, unsigned int device,
-  struct device *from)
+struct device *dev_find_device(struct device_id *devid, struct device *from)
 {
+   printk(BIOS_SPEW, "%s: find %s\n", __FUNCTION__, dev_id_string(devid));
+
if (!from)
from = all_devices;
else
from = from->next;
-   while (from && (from->vendor != vendor || from->device != device)) {
-   from = from->next;
+   for(;from;from = from->next){
+   printk(BIOS_SPEW, "Check %s\n", dev_id_string(&from->id));
+   if (id_eq(devid, &from->id))
+   break;
}
+   printk(BIOS_SPEW, "%sfound\n", from ? "" : "not ");
return from;
 }
 
 /**
+ * Find a PCI device of a given vendor and type.
+ * This is a convenience function since PCI device searches
+ * are by far the most common. 
+ *
+ * @param vendor vendor number
+ * @param device device number
+ * @param from Pointer to the device structure, used as a starting point
+ * in the linked list of all_devices, which can be 0 to start
+ * at the head of the list (i.e. all_devices).
+ * @return Pointer to the device struct.
+ */
+struct device *dev_find_pci_device(u16 vendor, u16 device, struct device *from)
+{
+   struct device_id id;
+
+   id.type = DEVICE_ID_PCI;
+   id.u.pci.vendor = vendor;
+   id.u.pci.device = device;
+   return dev_find_device(&id, from);
+}
+
+/**
  * Find a device of a given class.
  *
  * @param class Class of the device.

Modified: coreboot-v3/device/pci_device.c
===
--- coreboot-v3/device/pci_device.c 2008-01-19 06:29:14 UTC (rev 557)
+++ coreboot-v3/device/pci_device.c 2008-01-20 23:03:40 UTC (rev 558)
@@ -824,7 +824,7 @@
 static void set_pci_ops(struct device *dev)
 {
struct constructor *c;
-   struct device_id id = {.type = DEVICE_ID_PCI };
+   struct device_id id;
 
if (dev->ops) {
printk(BIOS_SPEW, "%s: dev %p(%s) already has ops %p\n",
@@ -832,9 +832,7 @@
return;
}
 
-   /* We need to make the ID in the device a device_id type. */
-   id.u.pci.vendor = dev->vendor;
-   id.u.pci.device = dev->device;
+   id  = dev->id;
 
/* Look through the list of setup drivers and find one for
 * this PCI device.
@@ -842,9 +840,9 @@
c = find_constructor(&id);
if (c) {
dev->ops = c->ops;
-   printk(BIOS_S

[coreboot] r558 - in coreboot-v3: device include/device northbridge/amd/geodelx southbridge/amd/cs5536 util/x86emu

[svn]

Author: hailfinger
Date: 2008-01-21 00:03:40 +0100 (Mon, 21 Jan 2008)
New Revision: 558

Modified:
   coreboot-v3/device/device_util.c
   coreboot-v3/device/pci_device.c
   coreboot-v3/device/pci_rom.c
   coreboot-v3/include/device/device.h
   coreboot-v3/northbridge/amd/geodelx/dts
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
   coreboot-v3/southbridge/amd/cs5536/dts
   coreboot-v3/util/x86emu/vm86.c
Log:
include/device/device.h
Remove old vendor,device struct members since we are now using the
device_id struct. 
Change declaration of dev_find_device to use device_id struct. 

device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users. 

device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id. 
Change prints of dev->vendor, dev->device to use the 
dev_id_string function. 

device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id. 

southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device

southbridge/amd/cs5536/dts
Add pciid of the cs5536

northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge. 

util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device

With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time. 
We are still failing in "Finding PCI configuration type"

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/device/device_util.c
===
--- coreboot-v3/device/device_util.c2008-01-19 06:29:14 UTC (rev 557)
+++ coreboot-v3/device/device_util.c2008-01-20 23:03:40 UTC (rev 558)
@@ -115,27 +115,52 @@
 /**
  * Find a device of a given vendor and type.
  *
- * @param vendor Vendor ID (e.g. 0x8086 for Intel)
- * @param device Device ID
+ * @param devid Pointer to device_id struct 
  * @param from Pointer to the device structure, used as a starting point
  * in the linked list of all_devices, which can be 0 to start
  * at the head of the list (i.e. all_devices).
  * @return Pointer to the device struct.
  */
-struct device *dev_find_device(unsigned int vendor, unsigned int device,
-  struct device *from)
+struct device *dev_find_device(struct device_id *devid, struct device *from)
 {
+   printk(BIOS_SPEW, "%s: find %s\n", __FUNCTION__, dev_id_string(devid));
+
if (!from)
from = all_devices;
else
from = from->next;
-   while (from && (from->vendor != vendor || from->device != device)) {
-   from = from->next;
+   for(;from;from = from->next){
+   printk(BIOS_SPEW, "Check %s\n", dev_id_string(&from->id));
+   if (id_eq(devid, &from->id))
+   break;
}
+   printk(BIOS_SPEW, "%sfound\n", from ? "" : "not ");
return from;
 }
 
 /**
+ * Find a PCI device of a given vendor and type.
+ * This is a convenience function since PCI device searches
+ * are by far the most common. 
+ *
+ * @param vendor vendor number
+ * @param device device number
+ * @param from Pointer to the device structure, used as a starting point
+ * in the linked list of all_devices, which can be 0 to start
+ * at the head of the list (i.e. all_devices).
+ * @return Pointer to the device struct.
+ */
+struct device *dev_find_pci_device(u16 vendor, u16 device, struct device *from)
+{
+   struct device_id id;
+
+   id.type = DEVICE_ID_PCI;
+   id.u.pci.vendor = vendor;
+   id.u.pci.device = device;
+   return dev_find_device(&id, from);
+}
+
+/**
  * Find a device of a given class.
  *
  * @param class Class of the device.

Modified: coreboot-v3/device/pci_device.c
===
--- coreboot-v3/device/pci_device.c 2008-01-19 06:29:14 UTC (rev 557)
+++ coreboot-v3/device/pci_device.c 2008-01-20 23:03:40 UTC (rev 558)
@@ -824,7 +824,7 @@
 static void set_pci_ops(struct device *dev)
 {
struct constructor *c;
-   struct device_id id = {.type = DEVICE_ID_PCI };
+   struct device_id id;
 
if (dev->ops) {
printk(BIOS_SPEW, "%s: dev %p(%s) already has ops %p\n",
@@ -832,9 +832,7 @@
return;
}
 
-   /* We need to make the ID in the device a device_id type. */
-   id.u.pci.vendor = dev->vendor;
-   id.u.pci.device = dev->device;
+   id  = dev->id;
 
/* Look through the list of setup drivers and find one for
 * this PCI device.
@@ -842,9 +840,9 @@
c = find_constructor(&id);
if (c) {
dev->ops = c->ops;
-   printk(BIOS_S

[coreboot] r559 - coreboot-v3/device

[svn]

Author: hailfinger
Date: 2008-01-21 03:39:45 +0100 (Mon, 21 Jan 2008)
New Revision: 559

Modified:
   coreboot-v3/device/device.c
Log:
Fix a compile warning in device/device.c

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/device/device.c
===
--- coreboot-v3/device/device.c 2008-01-20 23:03:40 UTC (rev 558)
+++ coreboot-v3/device/device.c 2008-01-21 02:39:45 UTC (rev 559)
@@ -737,7 +737,7 @@
printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname);
printk(BIOS_SPEW, "%s: ops %p ops->phase2_setup_scan_bus %p\n",
__FUNCTION__, dev->ops, 
-   dev->ops? dev->ops->phase2_setup_scan_bus : "None");
+   dev->ops? dev->ops->phase2_setup_scan_bus : NULL);
if (dev->ops && dev->ops->phase2_setup_scan_bus) {
printk(BIOS_SPEW,
   "Calling phase2 phase2_setup_scan_bus...");


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[coreboot] r559 - coreboot-v3/device

[svn]

Author: hailfinger
Date: 2008-01-21 03:39:45 +0100 (Mon, 21 Jan 2008)
New Revision: 559

Modified:
   coreboot-v3/device/device.c
Log:
Fix a compile warning in device/device.c

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/device/device.c
===
--- coreboot-v3/device/device.c 2008-01-20 23:03:40 UTC (rev 558)
+++ coreboot-v3/device/device.c 2008-01-21 02:39:45 UTC (rev 559)
@@ -737,7 +737,7 @@
printk(BIOS_SPEW, "%s: dev %s: ", __FUNCTION__, dev->dtsname);
printk(BIOS_SPEW, "%s: ops %p ops->phase2_setup_scan_bus %p\n",
__FUNCTION__, dev->ops, 
-   dev->ops? dev->ops->phase2_setup_scan_bus : "None");
+   dev->ops? dev->ops->phase2_setup_scan_bus : NULL);
if (dev->ops && dev->ops->phase2_setup_scan_bus) {
printk(BIOS_SPEW,
   "Calling phase2 phase2_setup_scan_bus...");


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[coreboot] r3067 - trunk/util/flashrom

[svn]

Author: uwe
Date: 2008-01-21 16:24:22 +0100 (Mon, 21 Jan 2008)
New Revision: 3067

Modified:
   trunk/util/flashrom/Makefile
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
Log:
This patch adds version information to flashrom. Because 'v' and 'V'
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.

Signed-off-by: Bernhard Walle <[EMAIL PROTECTED]>
Acked-by: Ulf Jordan <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/Makefile
===
--- trunk/util/flashrom/Makefile2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/Makefile2008-01-21 15:24:22 UTC (rev 3067)
@@ -28,6 +28,12 @@
 
 all: pciutils dep $(PROGRAM)
 
+# Set the flashrom version string from the highest revision number
+# of the checked out flashrom files.
+SVNDEF := -D'FLASHROM_VERSION="$(shell svnversion -cn . \
+  | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
+CFLAGS += $(SVNDEF)
+
 $(PROGRAM): $(OBJS)
$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
$(STRIP) $(STRIP_ARGS) $(PROGRAM)

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/flashrom.8  2008-01-21 15:24:22 UTC (rev 3067)
@@ -2,7 +2,7 @@
 .SH NAME
 flashrom \- a universal BIOS/ROM/flash programming utility
 .SH SYNOPSIS
-.B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
+.B flashrom \fR[\fB\-rwvEVfhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
  [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] 
[file]
 .SH DESCRIPTION
 .B flashrom
@@ -63,9 +63,9 @@
 .TP
 .B "\-h, \-\-help"
 Show a help text and exit.
-.\".TP
-.\".B "\-\-version"
-.\"Show version information and exit.
+.TP
+.B "\-R, \-\-version"
+Show version information and exit.
 .SH BUGS
 Please report any bugs at
 .BR http://tracker.coreboot.org/trac/coreboot/newticket ","

Modified: trunk/util/flashrom/flashrom.c
===
--- trunk/util/flashrom/flashrom.c  2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/flashrom.c  2008-01-21 15:24:22 UTC (rev 3067)
@@ -191,7 +191,7 @@
 
 void usage(const char *name)
 {
-   printf("usage: %s [-rwvEVfh] [-c chipname] [-s exclude_start]\n", name);
+   printf("usage: %s [-rwvEVfhR] [-c chipname] [-s exclude_start]\n", 
name);
printf("   [-e exclude_end] [-m vendor:part] [-l file.layout] [-i 
imagename] [file]\n");
printf
("   -r | --read:read flash and save into 
file\n"
@@ -206,11 +206,17 @@
 "   -f | --force:   force write without checking 
image\n"
 "   -l | --layout :read rom layout from file\n"
 "   -i | --image :only flash image name from 
flash layout\n"
+"   -R | --version: print the version (release)\n"
 "\n" " If no file is specified, then all that happens"
 " is that flash info is dumped.\n\n");
exit(1);
 }
 
+void print_version(void)
+{
+   printf("flashrom r%s\n", FLASHROM_VERSION);
+}
+
 int main(int argc, char *argv[])
 {
uint8_t *buf;
@@ -236,6 +242,7 @@
{"layout", 1, 0, 'l'},
{"image", 1, 0, 'i'},
{"help", 0, 0, 'h'},
+   {"version", 0, 0, 'R'},
{0, 0, 0, 0}
};
 
@@ -253,7 +260,7 @@
}
 
setbuf(stdout, NULL);
-   while ((opt = getopt_long(argc, argv, "rwvVEfc:s:e:m:l:i:h",
+   while ((opt = getopt_long(argc, argv, "rRwvVEfc:s:e:m:l:i:h",
  long_options, &option_index)) != EOF) {
switch (opt) {
case 'r':
@@ -306,6 +313,10 @@
tempstr = strdup(optarg);
find_romentry(tempstr);
break;
+   case 'R':
+   print_version();
+   exit(0);
+   break;
case 'h':
default:
usage(argv[0]);


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[coreboot] r3067 - trunk/util/flashrom

[svn]

Author: uwe
Date: 2008-01-21 16:24:22 +0100 (Mon, 21 Jan 2008)
New Revision: 3067

Modified:
   trunk/util/flashrom/Makefile
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
Log:
This patch adds version information to flashrom. Because 'v' and 'V'
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.

Signed-off-by: Bernhard Walle <[EMAIL PROTECTED]>
Acked-by: Ulf Jordan <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/Makefile
===
--- trunk/util/flashrom/Makefile2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/Makefile2008-01-21 15:24:22 UTC (rev 3067)
@@ -28,6 +28,12 @@
 
 all: pciutils dep $(PROGRAM)
 
+# Set the flashrom version string from the highest revision number
+# of the checked out flashrom files.
+SVNDEF := -D'FLASHROM_VERSION="$(shell svnversion -cn . \
+  | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/")"'
+CFLAGS += $(SVNDEF)
+
 $(PROGRAM): $(OBJS)
$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
$(STRIP) $(STRIP_ARGS) $(PROGRAM)

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/flashrom.8  2008-01-21 15:24:22 UTC (rev 3067)
@@ -2,7 +2,7 @@
 .SH NAME
 flashrom \- a universal BIOS/ROM/flash programming utility
 .SH SYNOPSIS
-.B flashrom \fR[\fB\-rwvEVfh\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
+.B flashrom \fR[\fB\-rwvEVfhR\fR] [\fB\-c\fR chipname] [\fB\-s\fR 
exclude_start] [\fB\-e\fR exclude_end]
  [\fB-m\fR vendor:part] [\fB-l\fR file.layout] [\fB-i\fR image_name] 
[file]
 .SH DESCRIPTION
 .B flashrom
@@ -63,9 +63,9 @@
 .TP
 .B "\-h, \-\-help"
 Show a help text and exit.
-.\".TP
-.\".B "\-\-version"
-.\"Show version information and exit.
+.TP
+.B "\-R, \-\-version"
+Show version information and exit.
 .SH BUGS
 Please report any bugs at
 .BR http://tracker.coreboot.org/trac/coreboot/newticket ","

Modified: trunk/util/flashrom/flashrom.c
===
--- trunk/util/flashrom/flashrom.c  2008-01-20 01:59:43 UTC (rev 3066)
+++ trunk/util/flashrom/flashrom.c  2008-01-21 15:24:22 UTC (rev 3067)
@@ -191,7 +191,7 @@
 
 void usage(const char *name)
 {
-   printf("usage: %s [-rwvEVfh] [-c chipname] [-s exclude_start]\n", name);
+   printf("usage: %s [-rwvEVfhR] [-c chipname] [-s exclude_start]\n", 
name);
printf("   [-e exclude_end] [-m vendor:part] [-l file.layout] [-i 
imagename] [file]\n");
printf
("   -r | --read:read flash and save into 
file\n"
@@ -206,11 +206,17 @@
 "   -f | --force:   force write without checking 
image\n"
 "   -l | --layout :read rom layout from file\n"
 "   -i | --image :only flash image name from 
flash layout\n"
+"   -R | --version: print the version (release)\n"
 "\n" " If no file is specified, then all that happens"
 " is that flash info is dumped.\n\n");
exit(1);
 }
 
+void print_version(void)
+{
+   printf("flashrom r%s\n", FLASHROM_VERSION);
+}
+
 int main(int argc, char *argv[])
 {
uint8_t *buf;
@@ -236,6 +242,7 @@
{"layout", 1, 0, 'l'},
{"image", 1, 0, 'i'},
{"help", 0, 0, 'h'},
+   {"version", 0, 0, 'R'},
{0, 0, 0, 0}
};
 
@@ -253,7 +260,7 @@
}
 
setbuf(stdout, NULL);
-   while ((opt = getopt_long(argc, argv, "rwvVEfc:s:e:m:l:i:h",
+   while ((opt = getopt_long(argc, argv, "rRwvVEfc:s:e:m:l:i:h",
  long_options, &option_index)) != EOF) {
switch (opt) {
case 'r':
@@ -306,6 +313,10 @@
tempstr = strdup(optarg);
find_romentry(tempstr);
break;
+   case 'R':
+   print_version();
+   exit(0);
+   break;
case 'h':
default:
usage(argv[0]);


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[coreboot] r3068 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 00:55:08 +0100 (Tue, 22 Jan 2008)
New Revision: 3068

Modified:
   trunk/util/flashrom/spi.c
Log:
Omitting the wait for SPI ready when there is no data to be read, e.g.
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.

Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c   2008-01-21 15:24:22 UTC (rev 3067)
+++ trunk/util/flashrom/spi.c   2008-01-21 23:55:08 UTC (rev 3068)
@@ -227,12 +227,15 @@
 * We can't use writecnt directly, but have to use a strange encoding.
 */ 
outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | 
(writeenc), port);
-   do {
-   busy = inb(port) & 0x80;
-   } while (busy);
 
-   for (i = 0; i < readcnt; i++) {
-   readarr[i] = inb(port + 5 + i);
+   if (readcnt > 0) {
+   do {
+   busy = inb(port) & 0x80;
+   } while (busy);
+
+   for (i = 0; i < readcnt; i++) {
+   readarr[i] = inb(port + 5 + i);
+   }
}
 
return 0;


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[coreboot] r3068 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 00:55:08 +0100 (Tue, 22 Jan 2008)
New Revision: 3068

Modified:
   trunk/util/flashrom/spi.c
Log:
Omitting the wait for SPI ready when there is no data to be read, e.g.
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.

Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c   2008-01-21 15:24:22 UTC (rev 3067)
+++ trunk/util/flashrom/spi.c   2008-01-21 23:55:08 UTC (rev 3068)
@@ -227,12 +227,15 @@
 * We can't use writecnt directly, but have to use a strange encoding.
 */ 
outb(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | 
(writeenc), port);
-   do {
-   busy = inb(port) & 0x80;
-   } while (busy);
 
-   for (i = 0; i < readcnt; i++) {
-   readarr[i] = inb(port + 5 + i);
+   if (readcnt > 0) {
+   do {
+   busy = inb(port) & 0x80;
+   } while (busy);
+
+   for (i = 0; i < readcnt; i++) {
+   readarr[i] = inb(port + 5 + i);
+   }
}
 
return 0;


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[coreboot] r3069 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 15:37:31 +0100 (Tue, 22 Jan 2008)
New Revision: 3069

Modified:
   trunk/util/flashrom/spi.c
Log:
Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Harald Gutmann <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c   2008-01-21 23:55:08 UTC (rev 3068)
+++ trunk/util/flashrom/spi.c   2008-01-22 14:37:31 UTC (rev 3069)
@@ -94,7 +94,7 @@
 
 uint16_t it8716f_flashport = 0;
 /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
-int fast_spi=1;
+int fast_spi = 1;
 
 void spi_prettyprint_status_register(struct flashchip *flash);
 void spi_disable_blockprotect(void);
@@ -155,7 +155,7 @@
0xFFF8, 0xFFFE, (tmp & 1 << 3) ? "en" : "dis");
printf("LPC write to serial flash %sabled\n",
(tmp & 1 << 4) ? "en" : "dis");
-   printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
+   printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
regwrite(port, 0x07, 0x7);
flashport = regval(port, 0x64) << 8;
@@ -348,14 +348,14 @@
  */
 void spi_prettyprint_status_register_sst25vf016(uint8_t status)
 {
-   const char *bpt[]={
+   const char *bpt[] = {
"none",
"1FH-1FH",
"1EH-1FH",
"1CH-1FH",
"18H-1FH",
"10H-1FH",
-   "all","all"
+   "all", "all"
};
printf_debug("Chip status register: Block Protect Write Disable "
"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
@@ -449,7 +449,7 @@
 
generic_spi_write_enable();
outb(0x06 , it8716f_flashport + 1);
-   outb(((2+(fast_spi?1:0)) << 4), it8716f_flashport);
+   outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
for (i = 0; i < 256; i++) {
bios[256 * block + i] = buf[256 * block + i];
}
@@ -513,18 +513,14 @@
 {
int total_size = 1024 * flash->total_size;
int i;
-   fast_spi=0;
+   fast_spi = 0;
 
spi_disable_blockprotect();
-   for (i=0; i>16)&0xff,
-   (address>>8)&0xff,
-   (address>>0)&0xff,
+   (address >> 16) & 0xff,
+   (address >> 8) & 0xff,
+   (address >> 0) & 0xff,
};
 
/* Send Read */
@@ -551,13 +547,14 @@
 {
int total_size = 1024 * flash->total_size;
int i;
-   fast_spi=0;
+   fast_spi = 0;
 
if (total_size > 512 * 1024) {
-   for (i = 0; i < total_size; i+=3) {
-   int toread=3;
-   if (total_size-i < toread) toread=total_size-i;
-   spi_3byte_read(i, buf+i, toread);
+   for (i = 0; i < total_size; i += 3) {
+   int toread = 3;
+   if (total_size - i < toread)
+   toread = total_size - i;
+   spi_3byte_read(i, buf + i, toread);
}
} else {
memcpy(buf, (const char *)flash->virtual_memory, total_size);


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[coreboot] r3069 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 15:37:31 +0100 (Tue, 22 Jan 2008)
New Revision: 3069

Modified:
   trunk/util/flashrom/spi.c
Log:
Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Harald Gutmann <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/spi.c
===
--- trunk/util/flashrom/spi.c   2008-01-21 23:55:08 UTC (rev 3068)
+++ trunk/util/flashrom/spi.c   2008-01-22 14:37:31 UTC (rev 3069)
@@ -94,7 +94,7 @@
 
 uint16_t it8716f_flashport = 0;
 /* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
-int fast_spi=1;
+int fast_spi = 1;
 
 void spi_prettyprint_status_register(struct flashchip *flash);
 void spi_disable_blockprotect(void);
@@ -155,7 +155,7 @@
0xFFF8, 0xFFFE, (tmp & 1 << 3) ? "en" : "dis");
printf("LPC write to serial flash %sabled\n",
(tmp & 1 << 4) ? "en" : "dis");
-   printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
+   printf("serial flash pin %i\n", (tmp & 1 << 5) ? 87 : 29);
/* LDN 0x7, reg 0x64/0x65 */
regwrite(port, 0x07, 0x7);
flashport = regval(port, 0x64) << 8;
@@ -348,14 +348,14 @@
  */
 void spi_prettyprint_status_register_sst25vf016(uint8_t status)
 {
-   const char *bpt[]={
+   const char *bpt[] = {
"none",
"1FH-1FH",
"1EH-1FH",
"1CH-1FH",
"18H-1FH",
"10H-1FH",
-   "all","all"
+   "all", "all"
};
printf_debug("Chip status register: Block Protect Write Disable "
"(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
@@ -449,7 +449,7 @@
 
generic_spi_write_enable();
outb(0x06 , it8716f_flashport + 1);
-   outb(((2+(fast_spi?1:0)) << 4), it8716f_flashport);
+   outb(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
for (i = 0; i < 256; i++) {
bios[256 * block + i] = buf[256 * block + i];
}
@@ -513,18 +513,14 @@
 {
int total_size = 1024 * flash->total_size;
int i;
-   fast_spi=0;
+   fast_spi = 0;
 
spi_disable_blockprotect();
-   for (i=0; i>16)&0xff,
-   (address>>8)&0xff,
-   (address>>0)&0xff,
+   (address >> 16) & 0xff,
+   (address >> 8) & 0xff,
+   (address >> 0) & 0xff,
};
 
/* Send Read */
@@ -551,13 +547,14 @@
 {
int total_size = 1024 * flash->total_size;
int i;
-   fast_spi=0;
+   fast_spi = 0;
 
if (total_size > 512 * 1024) {
-   for (i = 0; i < total_size; i+=3) {
-   int toread=3;
-   if (total_size-i < toread) toread=total_size-i;
-   spi_3byte_read(i, buf+i, toread);
+   for (i = 0; i < total_size; i += 3) {
+   int toread = 3;
+   if (total_size - i < toread)
+   toread = total_size - i;
+   spi_3byte_read(i, buf + i, toread);
}
} else {
memcpy(buf, (const char *)flash->virtual_memory, total_size);


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[coreboot] r3070 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 16:19:01 +0100 (Tue, 22 Jan 2008)
New Revision: 3070

Modified:
   trunk/util/flashrom/flashrom.c
Log:
Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.

This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.

"MX25L8005 found at physical address 0xfff0.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Harald Gutmann <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flashrom.c
===
--- trunk/util/flashrom/flashrom.c  2008-01-22 14:37:31 UTC (rev 3069)
+++ trunk/util/flashrom/flashrom.c  2008-01-22 15:19:01 UTC (rev 3070)
@@ -159,7 +159,11 @@
 {
int idx;
int total_size = flash->total_size * 1024;
-   volatile uint8_t *bios = flash->virtual_memory;
+   uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char));
+   if (flash->read == NULL)
+   memcpy(buf2, (const char *)flash->virtual_memory, total_size);
+   else
+   flash->read(flash, buf2);
 
printf("Verifying flash... ");
 
@@ -170,7 +174,7 @@
if (verbose && ((idx & 0xfff) == 0xfff))
printf("0x%08x", idx);
 
-   if (*(bios + idx) != *(buf + idx)) {
+   if (*(buf2 + idx) != *(buf + idx)) {
if (verbose) {
printf("0x%08x ", idx);
}


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[coreboot] r3070 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 16:19:01 +0100 (Tue, 22 Jan 2008)
New Revision: 3070

Modified:
   trunk/util/flashrom/flashrom.c
Log:
Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.

This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.

"MX25L8005 found at physical address 0xfff0.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."

Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Harald Gutmann <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flashrom.c
===
--- trunk/util/flashrom/flashrom.c  2008-01-22 14:37:31 UTC (rev 3069)
+++ trunk/util/flashrom/flashrom.c  2008-01-22 15:19:01 UTC (rev 3070)
@@ -159,7 +159,11 @@
 {
int idx;
int total_size = flash->total_size * 1024;
-   volatile uint8_t *bios = flash->virtual_memory;
+   uint8_t *buf2 = (uint8_t *) calloc(total_size, sizeof(char));
+   if (flash->read == NULL)
+   memcpy(buf2, (const char *)flash->virtual_memory, total_size);
+   else
+   flash->read(flash, buf2);
 
printf("Verifying flash... ");
 
@@ -170,7 +174,7 @@
if (verbose && ((idx & 0xfff) == 0xfff))
printf("0x%08x", idx);
 
-   if (*(bios + idx) != *(buf + idx)) {
+   if (*(buf2 + idx) != *(buf + idx)) {
if (verbose) {
printf("0x%08x ", idx);
}


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[coreboot] r3072 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 17:03:19 +0100 (Tue, 22 Jan 2008)
New Revision: 3072

Modified:
   trunk/util/flashrom/flashchips.c
Log:
Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe-0x enabled
Serial flash segment 0x000e-0x000f enabled
Serial flash segment 0xffee-0xffef disabled
Serial flash segment 0xfff8-0xfffe enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc0.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-22 16:00:46 UTC (rev 3071)
+++ trunk/util/flashrom/flashchips.c2008-01-22 16:03:19 UTC (rev 3072)
@@ -54,6 +54,8 @@
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L8005",   MX_ID,  MX_25L8005, 1024, 256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"MX25L3205",   MX_ID,  MX_25L3205, 4096, 256,
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,


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[coreboot] r3073 - in trunk/coreboot-v2: src/config targets

[svn]

Author: hailfinger
Date: 2008-01-22 17:09:36 +0100 (Tue, 22 Jan 2008)
New Revision: 3073

Modified:
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/targets/buildtarget
Log:
Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.

Signed-off-by: Marc Karasek <[EMAIL PROTECTED]> 
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Joseph Smith <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/config/Config.lb
===
--- trunk/coreboot-v2/src/config/Config.lb  2008-01-22 16:03:19 UTC (rev 
3072)
+++ trunk/coreboot-v2/src/config/Config.lb  2008-01-22 16:09:36 UTC (rev 
3073)
@@ -8,7 +8,7 @@
 makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne 
"s/install: \(.*\)/\1include/gp")
 
 makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include 
-I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib 
-fno-builtin  -Wall
+makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc 
-nostdlib -fno-builtin  -Wall
 
 makedefine HOSTCFLAGS:= -Os -Wall
 
@@ -38,14 +38,15 @@
 action  "ar cr coreboot.a $(OBJECTS)"
 end
 
+
 makerule coreboot_ram.o
depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
-   action  "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a 
$(LIBGCC_FILE_NAME)"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o $(DRIVER) 
coreboot.a $(LIBGCC_FILE_NAME)"
 end
 
 makerule coreboot_ram
depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" 
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T 
$(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ 
-T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
action  "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
 end
 
@@ -83,12 +84,12 @@
 
makerule coreboot_apc.o
depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
-action  "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a 
$(LIBGCC_FILE_NAME)"
+action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o 
coreboot_apc.a $(LIBGCC_FILE_NAME)"
end
 
makerule coreboot_apc
depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld 
ldoptions"
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T 
$(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static 
-o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
action  "$(CROSS_COMPILE)nm -n coreboot_apc | sort > 
coreboot_apc.map"
end
 
@@ -121,7 +122,7 @@
 
 makerule coreboot   
depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) 
ldscript.ld"
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld 
crt0.o $(INIT-OBJECTS)"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ 
-T ldscript.ld crt0.o $(INIT-OBJECTS)"
action  "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
 end
 

Modified: trunk/coreboot-v2/targets/buildtarget
===
--- trunk/coreboot-v2/targets/buildtarget   2008-01-22 16:03:19 UTC (rev 
3072)
+++ trunk/coreboot-v2/targets/buildtarget   2008-01-22 16:09:36 UTC (rev 
3073)
@@ -69,9 +69,16 @@
 
 rm -rf .$$.tmp
 
+ld --help | awk '{for (i=1;i<=NF;i++) if ($i ~ /build-id/){n++} }; END {exit 
n}' 
+build_id=$?
+if [ $build_id -ge 1 ] ; then
+   EXTRA_LFLAGS+=" -Wl,--build-id=none"
+fi
+
 for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings
 do
-   echo CFLAGS+=$EXTRA_CFLAGS >>$i
+   echo DISTRO_CFLAGS+=$EXTRA_CFLAGS >>$i
+   echo DISTRO_LFLAGS+=$EXTRA_LFLAGS >>$i
 done
 
 exit $?


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[coreboot] r3071 - trunk/coreboot-v2/util

[svn]

Author: uwe
Date: 2008-01-22 17:00:46 +0100 (Tue, 22 Jan 2008)
New Revision: 3071

Modified:
   trunk/coreboot-v2/util/
Log:
Change svn:externals to use new coreboot.org domain (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>




Property changes on: trunk/coreboot-v2/util
___
Name: svn:externals
   - flashrom svn://linuxbios.org/repos/trunk/util/flashrom
lxbios svn://linuxbios.org/repos/trunk/util/lxbios
superiotool svn://linuxbios.org/repos/trunk/util/superiotool
getpir svn://linuxbios.org/repos/trunk/util/getpir
mptable svn://linuxbios.org/repos/trunk/util/mptable

   + flashrom svn://coreboot.org/repos/trunk/util/flashrom
lxbios svn://coreboot.org/repos/trunk/util/lxbios
superiotool svn://coreboot.org/repos/trunk/util/superiotool
getpir svn://coreboot.org/repos/trunk/util/getpir
mptable svn://coreboot.org/repos/trunk/util/mptable



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[coreboot] r3072 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-22 17:03:19 +0100 (Tue, 22 Jan 2008)
New Revision: 3072

Modified:
   trunk/util/flashrom/flashchips.c
Log:
Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying. 

"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write... 
Serial flash segment 0xfffe-0x enabled
Serial flash segment 0x000e-0x000f enabled
Serial flash segment 0xffee-0xffef disabled
Serial flash segment 0xfff8-0xfffe enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc0.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb

Signed-off-by: Harald Gutmann <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-22 16:00:46 UTC (rev 3071)
+++ trunk/util/flashrom/flashchips.c2008-01-22 16:03:19 UTC (rev 3072)
@@ -54,6 +54,8 @@
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L8005",   MX_ID,  MX_25L8005, 1024, 256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"MX25L3205",   MX_ID,  MX_25L3205, 4096, 256,
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,


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[coreboot] r3071 - trunk/coreboot-v2/util

[svn]

Author: uwe
Date: 2008-01-22 17:00:46 +0100 (Tue, 22 Jan 2008)
New Revision: 3071

Modified:
   trunk/coreboot-v2/util/
Log:
Change svn:externals to use new coreboot.org domain (trivial).

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>




Property changes on: trunk/coreboot-v2/util
___
Name: svn:externals
   - flashrom svn://linuxbios.org/repos/trunk/util/flashrom
lxbios svn://linuxbios.org/repos/trunk/util/lxbios
superiotool svn://linuxbios.org/repos/trunk/util/superiotool
getpir svn://linuxbios.org/repos/trunk/util/getpir
mptable svn://linuxbios.org/repos/trunk/util/mptable

   + flashrom svn://coreboot.org/repos/trunk/util/flashrom
lxbios svn://coreboot.org/repos/trunk/util/lxbios
superiotool svn://coreboot.org/repos/trunk/util/superiotool
getpir svn://coreboot.org/repos/trunk/util/getpir
mptable svn://coreboot.org/repos/trunk/util/mptable



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[coreboot] r3073 - in trunk/coreboot-v2: src/config targets

[svn]

Author: hailfinger
Date: 2008-01-22 17:09:36 +0100 (Tue, 22 Jan 2008)
New Revision: 3073

Modified:
   trunk/coreboot-v2/src/config/Config.lb
   trunk/coreboot-v2/targets/buildtarget
Log:
Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.

Signed-off-by: Marc Karasek <[EMAIL PROTECTED]> 
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Joseph Smith <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/config/Config.lb
===
--- trunk/coreboot-v2/src/config/Config.lb  2008-01-22 16:03:19 UTC (rev 
3072)
+++ trunk/coreboot-v2/src/config/Config.lb  2008-01-22 16:09:36 UTC (rev 
3073)
@@ -8,7 +8,7 @@
 makedefine GCC_INC_DIR := $(shell LC_ALL=C $(CC) -print-search-dirs | sed -ne 
"s/install: \(.*\)/\1include/gp")
 
 makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include 
-I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS := $(CPU_OPT) $(CPPFLAGS) -Os -nostdinc -nostdlib 
-fno-builtin  -Wall
+makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc 
-nostdlib -fno-builtin  -Wall
 
 makedefine HOSTCFLAGS:= -Os -Wall
 
@@ -38,14 +38,15 @@
 action  "ar cr coreboot.a $(OBJECTS)"
 end
 
+
 makerule coreboot_ram.o
depends "$(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
-   action  "$(CC) -nostdlib -r -o $@ c_start.o $(DRIVER) coreboot.a 
$(LIBGCC_FILE_NAME)"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o $(DRIVER) 
coreboot.a $(LIBGCC_FILE_NAME)"
 end
 
 makerule coreboot_ram
depends "coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" 
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T 
$(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ 
-T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
action  "$(CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
 end
 
@@ -83,12 +84,12 @@
 
makerule coreboot_apc.o
depends "coreboot_apc.a c_start.o $(LIBGCC_FILE_NAME)"
-action  "$(CC) -nostdlib -r -o $@ c_start.o coreboot_apc.a 
$(LIBGCC_FILE_NAME)"
+action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ c_start.o 
coreboot_apc.a $(LIBGCC_FILE_NAME)"
end
 
makerule coreboot_apc
depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld 
ldoptions"
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T 
$(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static 
-o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
action  "$(CROSS_COMPILE)nm -n coreboot_apc | sort > 
coreboot_apc.map"
end
 
@@ -121,7 +122,7 @@
 
 makerule coreboot   
depends "crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) 
ldscript.ld"
-   action  "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld 
crt0.o $(INIT-OBJECTS)"
+   action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ 
-T ldscript.ld crt0.o $(INIT-OBJECTS)"
action  "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
 end
 

Modified: trunk/coreboot-v2/targets/buildtarget
===
--- trunk/coreboot-v2/targets/buildtarget   2008-01-22 16:03:19 UTC (rev 
3072)
+++ trunk/coreboot-v2/targets/buildtarget   2008-01-22 16:09:36 UTC (rev 
3073)
@@ -69,9 +69,16 @@
 
 rm -rf .$$.tmp
 
+ld --help | awk '{for (i=1;i<=NF;i++) if ($i ~ /build-id/){n++} }; END {exit 
n}' 
+build_id=$?
+if [ $build_id -ge 1 ] ; then
+   EXTRA_LFLAGS+=" -Wl,--build-id=none"
+fi
+
 for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings
 do
-   echo CFLAGS+=$EXTRA_CFLAGS >>$i
+   echo DISTRO_CFLAGS+=$EXTRA_CFLAGS >>$i
+   echo DISTRO_LFLAGS+=$EXTRA_LFLAGS >>$i
 done
 
 exit $?


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[coreboot] r560 - in coreboot-v3: northbridge/amd/geodelx util/x86emu

[svn]

Author: rminnich
Date: 2008-01-24 22:54:22 +0100 (Thu, 24 Jan 2008)
New Revision: 560

Added:
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Modified:
   coreboot-v3/northbridge/amd/geodelx/Makefile
   coreboot-v3/util/x86emu/vm86.c
Log:

This is a first cut at the implementation of VSM support. What has do be
done, long term, 
is to remove almost all of the vsmsetup.c file and use functions in the
vm86.c file.
 

The barrier to achieving that goal is the specialized nature of the vga
bios support code vs. the vsm bios support code. 
There are a few issues to resolve but what I'd like
to do is get VSA working first, then work out how to merge the rest of
the code. 

I have already done some merging at this point. 

This code does not yet work. But the board does not work either, and I 
want to get the code into the repo in case my hard drive dies.

Makefile: add vmsetup.o 

vsmsetup.c: Add this file from v2. Fix copyright and includes. 
Remove almost all assembly code in favor of code in vm86.c. 
In future, almost all code will be removed and the vm86.c code used
instead. 

vm86.c: make some assembly symbols .globl so that vsmsetup.c can use
them. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>

Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/northbridge/amd/geodelx/Makefile
===
--- coreboot-v3/northbridge/amd/geodelx/Makefile2008-01-21 02:39:45 UTC 
(rev 559)
+++ coreboot-v3/northbridge/amd/geodelx/Makefile2008-01-24 21:54:22 UTC 
(rev 560)
@@ -22,6 +22,7 @@
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
 STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
- $(obj)/northbridge/amd/geodelx/geodelxinit.o
+ $(obj)/northbridge/amd/geodelx/geodelxinit.o \
+ $(obj)/northbridge/amd/geodelx/vsmsetup.o
 
 endif

Added: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  
(rev 0)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-24 21:54:22 UTC 
(rev 560)
@@ -0,0 +1,303 @@
+/*
+ *  Copyright (C) 2000 Erik Arjan Hendriks
+ *  Copyright (C) 2000 Scyld Computing Corporation
+ *  Copyright (C) 2001 University of California.  LA-CC Number 01-67.
+ *  Copyright (C) 2005 [EMAIL PROTECTED]
+ *  Copyright (C) 2007 coresystems GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * LA-CC is the Los Alamos Control and Compliance Number, see also:
+ * http://supply.lanl.gov/property/customs/eximguide/default.shtml
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VSA2_BUFFER0x6
+#define VSA2_ENTRY_POINT   0x60020
+
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */
+static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
+{
+   u16 entryHi = (VSA2_ENTRY_POINT & 0x) >> 4;
+   u16 entryLo = (VSA2_ENTRY_POINT & 0x);
+
+   __asm__ __volatile__(
+   // paranoia -- does ecx get saved? not sure. This is
+   // the easiest safe thing to do.
+   "   pushal  \n"
+   /* save the stack */
+   "   mov %%esp, __stack  \n"
+   "   jmp 1f  \n"
+   "__stack: .long 0   \n" 
+   "1:\n"
+   /* get devfn into %%ecx */
+   "   movl%%esp, %%ebp\n"
+   /* Get the smm and sysm args into ecx and edx */
+   "   movl%0, %%ecx   \n"
+   "   movl%1, %%edx   \n"
+   /* load 'our' gdt */
+   "   lgdt%%cs:__mygdtaddr\n"
+   /*  This configures CS properly for real mode. */
+   "   ljmp$0x28, $__rms_16bit\n"
+   "__rms_16bit:   \n"
+   "   .code16 \n"
+   /* 16 bit code from here on... */
+   /* Load the segment registers w/ properly configured segment
+* descriptors.  They will retai

[coreboot] r560 - in coreboot-v3: northbridge/amd/geodelx util/x86emu

[svn]

Author: rminnich
Date: 2008-01-24 22:54:22 +0100 (Thu, 24 Jan 2008)
New Revision: 560

Added:
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Modified:
   coreboot-v3/northbridge/amd/geodelx/Makefile
   coreboot-v3/util/x86emu/vm86.c
Log:

This is a first cut at the implementation of VSM support. What has do be
done, long term, 
is to remove almost all of the vsmsetup.c file and use functions in the
vm86.c file.
 

The barrier to achieving that goal is the specialized nature of the vga
bios support code vs. the vsm bios support code. 
There are a few issues to resolve but what I'd like
to do is get VSA working first, then work out how to merge the rest of
the code. 

I have already done some merging at this point. 

This code does not yet work. But the board does not work either, and I 
want to get the code into the repo in case my hard drive dies.

Makefile: add vmsetup.o 

vsmsetup.c: Add this file from v2. Fix copyright and includes. 
Remove almost all assembly code in favor of code in vm86.c. 
In future, almost all code will be removed and the vm86.c code used
instead. 

vm86.c: make some assembly symbols .globl so that vsmsetup.c can use
them. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>

Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: coreboot-v3/northbridge/amd/geodelx/Makefile
===
--- coreboot-v3/northbridge/amd/geodelx/Makefile2008-01-21 02:39:45 UTC 
(rev 559)
+++ coreboot-v3/northbridge/amd/geodelx/Makefile2008-01-24 21:54:22 UTC 
(rev 560)
@@ -22,6 +22,7 @@
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
 STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
- $(obj)/northbridge/amd/geodelx/geodelxinit.o
+ $(obj)/northbridge/amd/geodelx/geodelxinit.o \
+ $(obj)/northbridge/amd/geodelx/vsmsetup.o
 
 endif

Added: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  
(rev 0)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-24 21:54:22 UTC 
(rev 560)
@@ -0,0 +1,303 @@
+/*
+ *  Copyright (C) 2000 Erik Arjan Hendriks
+ *  Copyright (C) 2000 Scyld Computing Corporation
+ *  Copyright (C) 2001 University of California.  LA-CC Number 01-67.
+ *  Copyright (C) 2005 [EMAIL PROTECTED]
+ *  Copyright (C) 2007 coresystems GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * LA-CC is the Los Alamos Control and Compliance Number, see also:
+ * http://supply.lanl.gov/property/customs/eximguide/default.shtml
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define VSA2_BUFFER0x6
+#define VSA2_ENTRY_POINT   0x60020
+
+
+/* The address arguments to this function are PHYSICAL ADDRESSES */
+static void real_mode_switch_call_vsm(unsigned long smm, unsigned long sysm)
+{
+   u16 entryHi = (VSA2_ENTRY_POINT & 0x) >> 4;
+   u16 entryLo = (VSA2_ENTRY_POINT & 0x);
+
+   __asm__ __volatile__(
+   // paranoia -- does ecx get saved? not sure. This is
+   // the easiest safe thing to do.
+   "   pushal  \n"
+   /* save the stack */
+   "   mov %%esp, __stack  \n"
+   "   jmp 1f  \n"
+   "__stack: .long 0   \n" 
+   "1:\n"
+   /* get devfn into %%ecx */
+   "   movl%%esp, %%ebp\n"
+   /* Get the smm and sysm args into ecx and edx */
+   "   movl%0, %%ecx   \n"
+   "   movl%1, %%edx   \n"
+   /* load 'our' gdt */
+   "   lgdt%%cs:__mygdtaddr\n"
+   /*  This configures CS properly for real mode. */
+   "   ljmp$0x28, $__rms_16bit\n"
+   "__rms_16bit:   \n"
+   "   .code16 \n"
+   /* 16 bit code from here on... */
+   /* Load the segment registers w/ properly configured segment
+* descriptors.  They will retai

[coreboot] r3074 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-25 02:52:45 +0100 (Fri, 25 Jan 2008)
New Revision: 3074

Modified:
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
Log:
Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-22 16:09:36 UTC (rev 3073)
+++ trunk/util/flashrom/flash.h 2008-01-25 01:52:45 UTC (rev 3074)
@@ -166,6 +166,14 @@
 #define SHARP_LHF00L04 0xCF
 
 /*
+ * Spansion was previously a joint venture of AMD and Fujitsu.
+ * S25 chips are SPI. The first device ID byte is memory type and
+ * the second device ID byte is memory capacity.
+ */
+#define SPANSION_ID0x01/* Spansion */
+#define SPANSION_S25FL016A 0x0214
+
+/*
  * SST25 chips are SPI, first byte of device ID is memory type, second
  * byte of device ID is related to log(bitsize) at least for some chips.
  */

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-22 16:09:36 UTC (rev 3073)
+++ trunk/util/flashrom/flashchips.c2008-01-25 01:52:45 UTC (rev 3074)
@@ -56,6 +56,8 @@
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L3205",   MX_ID,  MX_25L3205, 4096, 256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"S25FL016A",   SPANSION_ID,SPANSION_S25FL016A, 2048, 256,
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,


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[coreboot] r3074 - trunk/util/flashrom

[svn]

Author: hailfinger
Date: 2008-01-25 02:52:45 +0100 (Fri, 25 Jan 2008)
New Revision: 3074

Modified:
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashchips.c
Log:
Add ids and chip entry for Spansion S25FL016A to flashrom, tested,
working.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/flash.h
===
--- trunk/util/flashrom/flash.h 2008-01-22 16:09:36 UTC (rev 3073)
+++ trunk/util/flashrom/flash.h 2008-01-25 01:52:45 UTC (rev 3074)
@@ -166,6 +166,14 @@
 #define SHARP_LHF00L04 0xCF
 
 /*
+ * Spansion was previously a joint venture of AMD and Fujitsu.
+ * S25 chips are SPI. The first device ID byte is memory type and
+ * the second device ID byte is memory capacity.
+ */
+#define SPANSION_ID0x01/* Spansion */
+#define SPANSION_S25FL016A 0x0214
+
+/*
  * SST25 chips are SPI, first byte of device ID is memory type, second
  * byte of device ID is related to log(bitsize) at least for some chips.
  */

Modified: trunk/util/flashrom/flashchips.c
===
--- trunk/util/flashrom/flashchips.c2008-01-22 16:09:36 UTC (rev 3073)
+++ trunk/util/flashrom/flashchips.c2008-01-25 01:52:45 UTC (rev 3074)
@@ -56,6 +56,8 @@
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"MX25L3205",   MX_ID,  MX_25L3205, 4096, 256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
+   {"S25FL016A",   SPANSION_ID,SPANSION_S25FL016A, 2048, 256,
+probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF040B", SST_ID, SST_25VF040B,   512,256,
 probe_spi, generic_spi_chip_erase_c7,  generic_spi_chip_write, 
generic_spi_chip_read},
{"SST25VF016B", SST_ID, SST_25VF016B,   2048,   256,


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[coreboot] r563 - coreboot-v3/northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 05:07:14 +0100 (Sat, 26 Jan 2008)
New Revision: 563

Modified:
   coreboot-v3/northbridge/amd/geodelx/geodelx.c
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
I hope I am not overstepping the boundaries here, but I feel this is a
cosmetic comment as well. 

We just did lots of coding work to make sure we could call vsmbios. 

So let's actually call it!

P.S. If this is NOT considered a cosmetic comment, feel free to yell at
me :-)

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c   2008-01-26 03:45:13 UTC 
(rev 562)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c   2008-01-26 04:07:14 UTC 
(rev 563)
@@ -313,6 +313,8 @@
  */
 static void geodelx_pci_domain_phase2(struct device *dev)
 {
+   void do_vsmbios(void);
+
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
northbridge_init_early();
@@ -322,9 +324,8 @@
 
printk(BIOS_SPEW, "Before VSA:\n");
/* print_conf(); */
-#warning Not doing vsm bios -- linux will fail.
/* Do the magic stuff here, so prepare your tambourine ;) */
-   /* do_vsmbios(); */
+   do_vsmbios(); 
printk(BIOS_SPEW, "After VSA:\n");
/* print_conf(); */
 

Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:45:13 UTC 
(rev 562)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 04:07:14 UTC 
(rev 563)
@@ -168,7 +168,7 @@
return eax;
 }
 
-void do_vsmbios(void *bios)
+void do_vsmbios(void)
 {
unsigned char *buf;
int i;


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[coreboot] r562 - coreboot-v3/northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 04:45:13 +0100 (Sat, 26 Jan 2008)
New Revision: 562

Modified:
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
This is a cosmetic change. LAR names don't start with /
.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:40:00 UTC 
(rev 561)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:45:13 UTC 
(rev 562)
@@ -182,7 +182,7 @@
}
init_archive(&archive);
 
-   if (find_file(&archive, "/blob/vsa", &file)){
+   if (find_file(&archive, "blob/vsa", &file)){
printk(BIOS_ERR, "NO VSA found!\n");
return;
}


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[coreboot] r563 - coreboot-v3/northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 05:07:14 +0100 (Sat, 26 Jan 2008)
New Revision: 563

Modified:
   coreboot-v3/northbridge/amd/geodelx/geodelx.c
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
I hope I am not overstepping the boundaries here, but I feel this is a
cosmetic comment as well. 

We just did lots of coding work to make sure we could call vsmbios. 

So let's actually call it!

P.S. If this is NOT considered a cosmetic comment, feel free to yell at
me :-)

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c   2008-01-26 03:45:13 UTC 
(rev 562)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c   2008-01-26 04:07:14 UTC 
(rev 563)
@@ -313,6 +313,8 @@
  */
 static void geodelx_pci_domain_phase2(struct device *dev)
 {
+   void do_vsmbios(void);
+
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
 
northbridge_init_early();
@@ -322,9 +324,8 @@
 
printk(BIOS_SPEW, "Before VSA:\n");
/* print_conf(); */
-#warning Not doing vsm bios -- linux will fail.
/* Do the magic stuff here, so prepare your tambourine ;) */
-   /* do_vsmbios(); */
+   do_vsmbios(); 
printk(BIOS_SPEW, "After VSA:\n");
/* print_conf(); */
 

Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:45:13 UTC 
(rev 562)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 04:07:14 UTC 
(rev 563)
@@ -168,7 +168,7 @@
return eax;
 }
 
-void do_vsmbios(void *bios)
+void do_vsmbios(void)
 {
unsigned char *buf;
int i;


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[coreboot] r562 - coreboot-v3/northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 04:45:13 +0100 (Sat, 26 Jan 2008)
New Revision: 562

Modified:
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
This is a cosmetic change. LAR names don't start with /
.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:40:00 UTC 
(rev 561)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:45:13 UTC 
(rev 562)
@@ -182,7 +182,7 @@
}
init_archive(&archive);
 
-   if (find_file(&archive, "/blob/vsa", &file)){
+   if (find_file(&archive, "blob/vsa", &file)){
printk(BIOS_ERR, "NO VSA found!\n");
return;
}


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[coreboot] r561 - in coreboot-v3: arch/x86 include lib northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 04:40:00 +0100 (Sat, 26 Jan 2008)
New Revision: 561

Modified:
   coreboot-v3/arch/x86/stage1.c
   coreboot-v3/include/lar.h
   coreboot-v3/lib/lar.c
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
This change will support stage2 running LAR files. The initial example
is running the VSA in the geode lx northbridge.

It builds but is not tested.

lar.h: make LAR functions SHARED
lar.c: make process_file non-static (i.e. global)
vsmsetup.c: modify to use LAR functions.
stage1.c: new function, init_archive, which is SHARED and will set up
the initial archive struct.

Note that some work remains. The use of unsigned longs and unsigned
shorts should be changed to u32/u16 as Carl-Daniel has pointed out,
Because this change requires changes elsewhere I am not including them
in this patch. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: coreboot-v3/arch/x86/stage1.c
===
--- coreboot-v3/arch/x86/stage1.c   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/arch/x86/stage1.c   2008-01-26 03:40:00 UTC (rev 561)
@@ -50,7 +50,21 @@
post_code(POST_STAGE1_ENABLE_ROM);
 }
 
+void init_archive(struct mem_file *archive)
+{
+   // FIXME this should be defined in the VPD area
+   // but NOT IN THE CODE.
 
+   /* The len field starts behind the reset vector on x86.
+* The start is not correct for all platforms. sc520 will
+* need some hands on here.
+*/
+   archive->len = *(u32 *)0xfff4;
+   archive->start =(void *)(0UL-archive->len);
+
+   // FIXME check integrity
+
+}
 /* until we get rid of elf */
 int legacy(struct mem_file *archive, char *name, void *where, struct lb_memory 
*mem)
 {
@@ -121,19 +135,8 @@
 
// location and size of image.
 
-   // FIXME this should be defined in the VPD area
-   // but NOT IN THE CODE.
+   init_archive(&archive);
 
-   /* The len field starts behind the reset vector on x86.
-* The start is not correct for all platforms. sc520 will
-* need some hands on here.
-*/
-   archive.len = *(u32 *)0xfff4;
-   archive.start =(void *)(0UL-archive.len);
-
-   // FIXME check integrity
-
-
// find first initram
if (check_normal_boot_flag()) {
printk(BIOS_DEBUG, "Choosing normal boot.\n");

Modified: coreboot-v3/include/lar.h
===
--- coreboot-v3/include/lar.h   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/include/lar.h   2008-01-26 03:40:00 UTC (rev 561)
@@ -51,6 +51,7 @@
 #define LAR_H
 
 #include 
+#include 
 
 #define MAGIC "LARCHIVE"
 #define MAX_PATHLEN 1024
@@ -82,11 +83,15 @@
 };
 
 /* Prototypes. */
-int find_file(const struct mem_file *archive, const char *filename, struct 
mem_file *result);
-int copy_file(const struct mem_file *archive, const char *filename, void 
*where);
-int run_file(const struct mem_file *archive, const char *filename, void 
*where);
-int execute_in_place(const struct mem_file *archive, const char *filename);
-int run_address(void *f);
-void *load_file(const struct mem_file *archive, const char *filename);
-void *load_file_segments(const struct mem_file *archive, const char *filename);
+/* architecture-defined */
+SHARED(init_archive, void, struct mem_file *);
+/* architecture-independent */
+SHARED(find_file, int, const struct mem_file *archive, const char *filename, 
struct mem_file *result);
+SHARED(copy_file, int, const struct mem_file *archive, const char *filename, 
void *where);
+SHARED(run_file, int, const struct mem_file *archive, const char *filename, 
void *where);
+SHARED(execute_in_place, int, const struct mem_file *archive, const char 
*filename);
+SHARED(run_address, int, void *f);
+SHARED(load_file, void *, const struct mem_file *archive, const char 
*filename);
+SHARED(load_file_segments, void *, const struct mem_file *archive, const char 
*filename);
+SHARED(process_file, int, const struct mem_file *archive, void *where);
 #endif /* LAR_H */

Modified: coreboot-v3/lib/lar.c
===
--- coreboot-v3/lib/lar.c   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/lib/lar.c   2008-01-26 03:40:00 UTC (rev 561)
@@ -145,7 +145,7 @@
return 1;
 }
 
-static int process_file(const struct mem_file *archive, void *where)
+int process_file(const struct mem_file *archive, void *where)
 {
printk(BIOS_SPEW, "LAR: Compression algorithm #%i used\n", 
archive->compression);
/* no compression */

Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-24 21:54:22 UTC 
(rev 560)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:40:00 UTC 

[coreboot] r561 - in coreboot-v3: arch/x86 include lib northbridge/amd/geodelx

[svn]

Author: rminnich
Date: 2008-01-26 04:40:00 +0100 (Sat, 26 Jan 2008)
New Revision: 561

Modified:
   coreboot-v3/arch/x86/stage1.c
   coreboot-v3/include/lar.h
   coreboot-v3/lib/lar.c
   coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
Log:
This change will support stage2 running LAR files. The initial example
is running the VSA in the geode lx northbridge.

It builds but is not tested.

lar.h: make LAR functions SHARED
lar.c: make process_file non-static (i.e. global)
vsmsetup.c: modify to use LAR functions.
stage1.c: new function, init_archive, which is SHARED and will set up
the initial archive struct.

Note that some work remains. The use of unsigned longs and unsigned
shorts should be changed to u32/u16 as Carl-Daniel has pointed out,
Because this change requires changes elsewhere I am not including them
in this patch. 

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>



Modified: coreboot-v3/arch/x86/stage1.c
===
--- coreboot-v3/arch/x86/stage1.c   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/arch/x86/stage1.c   2008-01-26 03:40:00 UTC (rev 561)
@@ -50,7 +50,21 @@
post_code(POST_STAGE1_ENABLE_ROM);
 }
 
+void init_archive(struct mem_file *archive)
+{
+   // FIXME this should be defined in the VPD area
+   // but NOT IN THE CODE.
 
+   /* The len field starts behind the reset vector on x86.
+* The start is not correct for all platforms. sc520 will
+* need some hands on here.
+*/
+   archive->len = *(u32 *)0xfff4;
+   archive->start =(void *)(0UL-archive->len);
+
+   // FIXME check integrity
+
+}
 /* until we get rid of elf */
 int legacy(struct mem_file *archive, char *name, void *where, struct lb_memory 
*mem)
 {
@@ -121,19 +135,8 @@
 
// location and size of image.
 
-   // FIXME this should be defined in the VPD area
-   // but NOT IN THE CODE.
+   init_archive(&archive);
 
-   /* The len field starts behind the reset vector on x86.
-* The start is not correct for all platforms. sc520 will
-* need some hands on here.
-*/
-   archive.len = *(u32 *)0xfff4;
-   archive.start =(void *)(0UL-archive.len);
-
-   // FIXME check integrity
-
-
// find first initram
if (check_normal_boot_flag()) {
printk(BIOS_DEBUG, "Choosing normal boot.\n");

Modified: coreboot-v3/include/lar.h
===
--- coreboot-v3/include/lar.h   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/include/lar.h   2008-01-26 03:40:00 UTC (rev 561)
@@ -51,6 +51,7 @@
 #define LAR_H
 
 #include 
+#include 
 
 #define MAGIC "LARCHIVE"
 #define MAX_PATHLEN 1024
@@ -82,11 +83,15 @@
 };
 
 /* Prototypes. */
-int find_file(const struct mem_file *archive, const char *filename, struct 
mem_file *result);
-int copy_file(const struct mem_file *archive, const char *filename, void 
*where);
-int run_file(const struct mem_file *archive, const char *filename, void 
*where);
-int execute_in_place(const struct mem_file *archive, const char *filename);
-int run_address(void *f);
-void *load_file(const struct mem_file *archive, const char *filename);
-void *load_file_segments(const struct mem_file *archive, const char *filename);
+/* architecture-defined */
+SHARED(init_archive, void, struct mem_file *);
+/* architecture-independent */
+SHARED(find_file, int, const struct mem_file *archive, const char *filename, 
struct mem_file *result);
+SHARED(copy_file, int, const struct mem_file *archive, const char *filename, 
void *where);
+SHARED(run_file, int, const struct mem_file *archive, const char *filename, 
void *where);
+SHARED(execute_in_place, int, const struct mem_file *archive, const char 
*filename);
+SHARED(run_address, int, void *f);
+SHARED(load_file, void *, const struct mem_file *archive, const char 
*filename);
+SHARED(load_file_segments, void *, const struct mem_file *archive, const char 
*filename);
+SHARED(process_file, int, const struct mem_file *archive, void *where);
 #endif /* LAR_H */

Modified: coreboot-v3/lib/lar.c
===
--- coreboot-v3/lib/lar.c   2008-01-24 21:54:22 UTC (rev 560)
+++ coreboot-v3/lib/lar.c   2008-01-26 03:40:00 UTC (rev 561)
@@ -145,7 +145,7 @@
return 1;
 }
 
-static int process_file(const struct mem_file *archive, void *where)
+int process_file(const struct mem_file *archive, void *where)
 {
printk(BIOS_SPEW, "LAR: Compression algorithm #%i used\n", 
archive->compression);
/* no compression */

Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-24 21:54:22 UTC 
(rev 560)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c  2008-01-26 03:40:00 UTC 

[coreboot] r3078 - trunk/util/flashrom

[svn]

Author: rminnich
Date: 2008-01-26 08:35:47 +0100 (Sat, 26 Jan 2008)
New Revision: 3078

Modified:
   trunk/util/flashrom/chipset_enable.c
Log:
Correctly disable the ROM area Write Protect bit in the Geode LX.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/chipset_enable.c
===
--- trunk/util/flashrom/chipset_enable.c2008-01-25 19:31:26 UTC (rev 
3077)
+++ trunk/util/flashrom/chipset_enable.c2008-01-26 07:35:47 UTC (rev 
3078)
@@ -256,7 +256,7 @@
close(fd_msr);
if (buf[7] != 0x22) {
printf("Enabling Geode MSR to write to flash.\n");
-   buf[7] = 0x22;
+   buf[7] &= 0xFB;
fd_msr = open("/dev/cpu/0/msr", O_WRONLY);
if (!fd_msr) {
perror("open msr");


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[coreboot] r3078 - trunk/util/flashrom

[svn]

Author: rminnich
Date: 2008-01-26 08:35:47 +0100 (Sat, 26 Jan 2008)
New Revision: 3078

Modified:
   trunk/util/flashrom/chipset_enable.c
Log:
Correctly disable the ROM area Write Protect bit in the Geode LX.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>

Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: trunk/util/flashrom/chipset_enable.c
===
--- trunk/util/flashrom/chipset_enable.c2008-01-25 19:31:26 UTC (rev 
3077)
+++ trunk/util/flashrom/chipset_enable.c2008-01-26 07:35:47 UTC (rev 
3078)
@@ -256,7 +256,7 @@
close(fd_msr);
if (buf[7] != 0x22) {
printf("Enabling Geode MSR to write to flash.\n");
-   buf[7] = 0x22;
+   buf[7] &= 0xFB;
fd_msr = open("/dev/cpu/0/msr", O_WRONLY);
if (!fd_msr) {
perror("open msr");


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[coreboot] r3076 - in trunk/coreboot-v2/src: arch/i386/boot include/boot

[svn]

Author: oxygene
Date: 2008-01-25 19:28:18 +0100 (Fri, 25 Jan 2008)
New Revision: 3076

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/include/boot/coreboot_tables.h
Log:
This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-25 
15:08:37 UTC (rev 3075)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-25 
18:28:18 UTC (rev 3076)
@@ -74,6 +74,22 @@
return mem;
 }
 
+struct lb_serial *lb_serial(struct lb_header *header)
+{
+#if defined(TTYS0_BASE)
+   struct lb_record *rec;
+   struct lb_serial *serial;
+   rec = lb_new_record(header);
+   serial = (struct lb_serial *)rec;
+   serial->tag = LB_TAG_SERIAL;
+   serial->size = sizeof(*serial);
+   serial->ioport = TTYS0_BASE;
+   return serial;
+#else
+   return header;
+#endif
+}
+
 struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
struct lb_record *rec;
@@ -406,8 +422,10 @@
 * size of the coreboot table.
 */
 
-   /* Record our motheboard */
+   /* Record our motherboard */
lb_mainboard(head);
+   /* Record the serial port, if present */
+   lb_serial(head);
/* Record our various random string information */
lb_strings(head);
 

Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h
===
--- trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-25 
15:08:37 UTC (rev 3075)
+++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-25 
18:28:18 UTC (rev 3076)
@@ -138,6 +138,13 @@
uint8_t  string[0];
 };
 
+#define LB_TAG_SERIAL  0x000f
+struct lb_serial {
+   uint32_t tag;
+   uint32_t size;
+   uint16_t ioport;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */


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[coreboot] r3075 - trunk/util/lxbios

[svn]

Author: uwe
Date: 2008-01-25 16:08:37 +0100 (Fri, 25 Jan 2008)
New Revision: 3075

Modified:
   trunk/util/lxbios/COPYING
   trunk/util/lxbios/ChangeLog
   trunk/util/lxbios/DISCLAIMER
   trunk/util/lxbios/Makefile
   trunk/util/lxbios/README
   trunk/util/lxbios/cmos_lowlevel.c
   trunk/util/lxbios/cmos_lowlevel.h
   trunk/util/lxbios/cmos_ops.c
   trunk/util/lxbios/cmos_ops.h
   trunk/util/lxbios/common.c
   trunk/util/lxbios/common.h
   trunk/util/lxbios/compute_ip_checksum.c
   trunk/util/lxbios/coreboot_tables.h
   trunk/util/lxbios/hexdump.c
   trunk/util/lxbios/hexdump.h
   trunk/util/lxbios/input_file.c
   trunk/util/lxbios/input_file.h
   trunk/util/lxbios/ip_checksum.h
   trunk/util/lxbios/layout.c
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.c
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/lxbios/lbtable.h
   trunk/util/lxbios/lxbios.1
   trunk/util/lxbios/lxbios.c
   trunk/util/lxbios/lxbios.spec
   trunk/util/lxbios/opts.c
   trunk/util/lxbios/opts.h
   trunk/util/lxbios/reg_expr.c
   trunk/util/lxbios/reg_expr.h
Log:
Various small fixes and updates for lxbios (trivial).

 - Update website URL to http://coreboot.org/Lxbios.

 - Use svn:keywords property to actually expand the $Id$ entries.

 - Update COPYING to the latest version from
   http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/lxbios/COPYING
===
--- trunk/util/lxbios/COPYING   2008-01-25 01:52:45 UTC (rev 3074)
+++ trunk/util/lxbios/COPYING   2008-01-25 15:08:37 UTC (rev 3075)
@@ -1,8 +1,8 @@
GNU GENERAL PUBLIC LICENSE
   Version 2, June 1991
 
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-  675 Mass Ave, Cambridge, MA 02139, USA
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -15,7 +15,7 @@
 General Public License applies to most of the Free Software
 Foundation's software and to any other program whose authors commit to
 using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
+the GNU Lesser General Public License instead.)  You can apply it to
 your programs, too.
 
   When we speak of free software, we are referring to freedom, not
@@ -55,7 +55,7 @@
 
   The precise terms and conditions for copying, distribution and
 modification follow.
-
+
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
 
@@ -110,7 +110,7 @@
 License.  (Exception: if the Program itself is interactive but
 does not normally print such an announcement, your work based on
 the Program is not required to print an announcement.)
-
+
 These requirements apply to the modified work as a whole.  If
 identifiable sections of that work are not derived from the Program,
 and can be reasonably considered independent and separate works in
@@ -168,7 +168,7 @@
 access to copy the source code from the same place counts as
 distribution of the source code, even though third parties are not
 compelled to copy the source along with the object code.
-
+
   4. You may not copy, modify, sublicense, or distribute the Program
 except as expressly provided under this License.  Any attempt
 otherwise to copy, modify, sublicense or distribute the Program is
@@ -225,7 +225,7 @@
 
 This section is intended to make thoroughly clear what is believed to
 be a consequence of the rest of this License.
-
+
   8. If the distribution and/or use of the Program is restricted in
 certain countries either by patents or by copyrighted interfaces, the
 original copyright holder who places the Program under this License
@@ -278,9 +278,9 @@
 POSSIBILITY OF SUCH DAMAGES.
 
 END OF TERMS AND CONDITIONS
-
-   Appendix: How to Apply These Terms to Your New Programs
 
+   How to Apply These Terms to Your New Programs
+
   If you develop a new program, and you want it to be of the greatest
 possible use to the public, the best way to achieve this is to make it
 free software which everyone can redistribute and change under these terms.
@@ -291,7 +291,7 @@
 the "copyright" line and a pointer to where the full notice is found.
 
 
-Copyright (C) 19yy  
+Copyright (C)   
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -303,16 +303,16 @@
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU Ge

[coreboot] r3077 - trunk/coreboot-v2/targets

[svn]

Author: oxygene
Date: 2008-01-25 20:31:26 +0100 (Fri, 25 Jan 2008)
New Revision: 3077

Modified:
   trunk/coreboot-v2/targets/buildtarget
Log:
bsh/ksh-clone and make(1)-syntax don't go well together
(unlike 5 lines later where make syntax is emitted into a file)

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/targets/buildtarget
===
--- trunk/coreboot-v2/targets/buildtarget   2008-01-25 18:28:18 UTC (rev 
3076)
+++ trunk/coreboot-v2/targets/buildtarget   2008-01-25 19:31:26 UTC (rev 
3077)
@@ -72,7 +72,7 @@
 ld --help | awk '{for (i=1;i<=NF;i++) if ($i ~ /build-id/){n++} }; END {exit 
n}' 
 build_id=$?
 if [ $build_id -ge 1 ] ; then
-   EXTRA_LFLAGS+=" -Wl,--build-id=none"
+   EXTRA_LFLAGS="$EXTRA_LFLAGS -Wl,--build-id=none"
 fi
 
 for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings


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[coreboot] r3076 - in trunk/coreboot-v2/src: arch/i386/boot include/boot

[svn]

Author: oxygene
Date: 2008-01-25 19:28:18 +0100 (Fri, 25 Jan 2008)
New Revision: 3076

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/include/boot/coreboot_tables.h
Log:
This patch adds a new record type for lbtable to provide information
about a serial port. If a port is defined in the board configuration,
add it to lbtable.

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-25 
15:08:37 UTC (rev 3075)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-25 
18:28:18 UTC (rev 3076)
@@ -74,6 +74,22 @@
return mem;
 }
 
+struct lb_serial *lb_serial(struct lb_header *header)
+{
+#if defined(TTYS0_BASE)
+   struct lb_record *rec;
+   struct lb_serial *serial;
+   rec = lb_new_record(header);
+   serial = (struct lb_serial *)rec;
+   serial->tag = LB_TAG_SERIAL;
+   serial->size = sizeof(*serial);
+   serial->ioport = TTYS0_BASE;
+   return serial;
+#else
+   return header;
+#endif
+}
+
 struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
struct lb_record *rec;
@@ -406,8 +422,10 @@
 * size of the coreboot table.
 */
 
-   /* Record our motheboard */
+   /* Record our motherboard */
lb_mainboard(head);
+   /* Record the serial port, if present */
+   lb_serial(head);
/* Record our various random string information */
lb_strings(head);
 

Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h
===
--- trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-25 
15:08:37 UTC (rev 3075)
+++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-25 
18:28:18 UTC (rev 3076)
@@ -138,6 +138,13 @@
uint8_t  string[0];
 };
 
+#define LB_TAG_SERIAL  0x000f
+struct lb_serial {
+   uint32_t tag;
+   uint32_t size;
+   uint16_t ioport;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */


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[coreboot] r3075 - trunk/util/lxbios

[svn]

Author: uwe
Date: 2008-01-25 16:08:37 +0100 (Fri, 25 Jan 2008)
New Revision: 3075

Modified:
   trunk/util/lxbios/COPYING
   trunk/util/lxbios/ChangeLog
   trunk/util/lxbios/DISCLAIMER
   trunk/util/lxbios/Makefile
   trunk/util/lxbios/README
   trunk/util/lxbios/cmos_lowlevel.c
   trunk/util/lxbios/cmos_lowlevel.h
   trunk/util/lxbios/cmos_ops.c
   trunk/util/lxbios/cmos_ops.h
   trunk/util/lxbios/common.c
   trunk/util/lxbios/common.h
   trunk/util/lxbios/compute_ip_checksum.c
   trunk/util/lxbios/coreboot_tables.h
   trunk/util/lxbios/hexdump.c
   trunk/util/lxbios/hexdump.h
   trunk/util/lxbios/input_file.c
   trunk/util/lxbios/input_file.h
   trunk/util/lxbios/ip_checksum.h
   trunk/util/lxbios/layout.c
   trunk/util/lxbios/layout.h
   trunk/util/lxbios/layout_file.c
   trunk/util/lxbios/layout_file.h
   trunk/util/lxbios/lbtable.c
   trunk/util/lxbios/lbtable.h
   trunk/util/lxbios/lxbios.1
   trunk/util/lxbios/lxbios.c
   trunk/util/lxbios/lxbios.spec
   trunk/util/lxbios/opts.c
   trunk/util/lxbios/opts.h
   trunk/util/lxbios/reg_expr.c
   trunk/util/lxbios/reg_expr.h
Log:
Various small fixes and updates for lxbios (trivial).

 - Update website URL to http://coreboot.org/Lxbios.

 - Use svn:keywords property to actually expand the $Id$ entries.

 - Update COPYING to the latest version from
   http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>



Modified: trunk/util/lxbios/COPYING
===
--- trunk/util/lxbios/COPYING   2008-01-25 01:52:45 UTC (rev 3074)
+++ trunk/util/lxbios/COPYING   2008-01-25 15:08:37 UTC (rev 3075)
@@ -1,8 +1,8 @@
GNU GENERAL PUBLIC LICENSE
   Version 2, June 1991
 
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-  675 Mass Ave, Cambridge, MA 02139, USA
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -15,7 +15,7 @@
 General Public License applies to most of the Free Software
 Foundation's software and to any other program whose authors commit to
 using it.  (Some other Free Software Foundation software is covered by
-the GNU Library General Public License instead.)  You can apply it to
+the GNU Lesser General Public License instead.)  You can apply it to
 your programs, too.
 
   When we speak of free software, we are referring to freedom, not
@@ -55,7 +55,7 @@
 
   The precise terms and conditions for copying, distribution and
 modification follow.
-
+
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
 
@@ -110,7 +110,7 @@
 License.  (Exception: if the Program itself is interactive but
 does not normally print such an announcement, your work based on
 the Program is not required to print an announcement.)
-
+
 These requirements apply to the modified work as a whole.  If
 identifiable sections of that work are not derived from the Program,
 and can be reasonably considered independent and separate works in
@@ -168,7 +168,7 @@
 access to copy the source code from the same place counts as
 distribution of the source code, even though third parties are not
 compelled to copy the source along with the object code.
-
+
   4. You may not copy, modify, sublicense, or distribute the Program
 except as expressly provided under this License.  Any attempt
 otherwise to copy, modify, sublicense or distribute the Program is
@@ -225,7 +225,7 @@
 
 This section is intended to make thoroughly clear what is believed to
 be a consequence of the rest of this License.
-
+
   8. If the distribution and/or use of the Program is restricted in
 certain countries either by patents or by copyrighted interfaces, the
 original copyright holder who places the Program under this License
@@ -278,9 +278,9 @@
 POSSIBILITY OF SUCH DAMAGES.
 
 END OF TERMS AND CONDITIONS
-
-   Appendix: How to Apply These Terms to Your New Programs
 
+   How to Apply These Terms to Your New Programs
+
   If you develop a new program, and you want it to be of the greatest
 possible use to the public, the best way to achieve this is to make it
 free software which everyone can redistribute and change under these terms.
@@ -291,7 +291,7 @@
 the "copyright" line and a pointer to where the full notice is found.
 
 
-Copyright (C) 19yy  
+Copyright (C)   
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
@@ -303,16 +303,16 @@
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU Ge

[coreboot] r3077 - trunk/coreboot-v2/targets

[svn]

Author: oxygene
Date: 2008-01-25 20:31:26 +0100 (Fri, 25 Jan 2008)
New Revision: 3077

Modified:
   trunk/coreboot-v2/targets/buildtarget
Log:
bsh/ksh-clone and make(1)-syntax don't go well together
(unlike 5 lines later where make syntax is emitted into a file)

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/targets/buildtarget
===
--- trunk/coreboot-v2/targets/buildtarget   2008-01-25 18:28:18 UTC (rev 
3076)
+++ trunk/coreboot-v2/targets/buildtarget   2008-01-25 19:31:26 UTC (rev 
3077)
@@ -72,7 +72,7 @@
 ld --help | awk '{for (i=1;i<=NF;i++) if ($i ~ /build-id/){n++} }; END {exit 
n}' 
 build_id=$?
 if [ $build_id -ge 1 ] ; then
-   EXTRA_LFLAGS+=" -Wl,--build-id=none"
+   EXTRA_LFLAGS="$EXTRA_LFLAGS -Wl,--build-id=none"
 fi
 
 for i in $build_dir/Makefile.settings $build_dir/*/Makefile.settings


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[coreboot] r3079 - in trunk/coreboot-v2/src/mainboard: agami/aruma amd/db800 amd/norwich amd/serengeti_cheetah arima/hdama artecgroup/dbe61 asus/a8n_e asus/a8v-e_se broadcom/blast digitallogic/msm800s

[svn]

Author: ward
Date: 2008-01-26 17:57:03 +0100 (Sat, 26 Jan 2008)
New Revision: 3079

Modified:
   trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
   trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
Log:

This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS 
were not being
included on the CC line for cache_as_ram_auto.c

Tested on ubuntu, where formerly it failed.

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb   2008-01-26 
07:35:47 UTC (rev 3078)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb   2008-01-26 
16:57:03 UTC (rev 3079)
@@ -106,14 +106,14 @@
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-o cache_as_ram_auto.o" 
+   action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib 
-fno-builtin -Wall -c -o cache_as_ram_auto.o" 
end
 
else   
#compile cache_as_ram.c to auto.inc 
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-S -o $@" 
+   action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib 
-fno-builtin -Wall -c -S -o $@" 
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-26 07:35:47 UTC 
(rev 3078)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-26 16:57:03 UTC 
(rev 3079)
@@ -54,7 +54,7 @@
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-S -o $@"
+   action "$(CC) $(DISTRO_CFLAGS) -I$(T

[coreboot] r3079 - in trunk/coreboot-v2/src/mainboard: agami/aruma amd/db800 amd/norwich amd/serengeti_cheetah arima/hdama artecgroup/dbe61 asus/a8n_e asus/a8v-e_se broadcom/blast digitallogic/msm800s

[svn]

Author: ward
Date: 2008-01-26 17:57:03 +0100 (Sat, 26 Jan 2008)
New Revision: 3079

Modified:
   trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
   trunk/coreboot-v2/src/mainboard/arima/hdama/Config.lb
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
   trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e325/Config.lb
   trunk/coreboot-v2/src/mainboard/ibm/e326/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/Config.lb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/Config.lb
   trunk/coreboot-v2/src/mainboard/newisys/khepri/Config.lb
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
   trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/Config.lb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/Config.lb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/Config.lb
Log:

This patch fixes the remaining stack protector problem on v2. The DISTRO_CFLAGS 
were not being
included on the CC line for cache_as_ram_auto.c

Tested on ubuntu, where formerly it failed.

Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb   2008-01-26 
07:35:47 UTC (rev 3078)
+++ trunk/coreboot-v2/src/mainboard/agami/aruma/Config.lb   2008-01-26 
16:57:03 UTC (rev 3079)
@@ -106,14 +106,14 @@
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-o cache_as_ram_auto.o" 
+   action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib 
-fno-builtin -Wall -c -o cache_as_ram_auto.o" 
end
 
else   
#compile cache_as_ram.c to auto.inc 
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-S -o $@" 
+   action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib 
-fno-builtin -Wall -c -S -o $@" 
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end

Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-26 07:35:47 UTC 
(rev 3078)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2008-01-26 16:57:03 UTC 
(rev 3079)
@@ -54,7 +54,7 @@
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c 
-S -o $@"
+   action "$(CC) $(DISTRO_CFLAGS) -I$(T

[coreboot] r3080 - trunk/util/flashrom

[svn]

Author: stuge
Date: 2008-01-27 08:17:14 +0100 (Sun, 27 Jan 2008)
New Revision: 3080

Modified:
   trunk/util/flashrom/README
Log:
Forgot to add Spansion S25FL016A to README, trivial.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-26 16:57:03 UTC (rev 3079)
+++ trunk/util/flashrom/README  2008-01-27 07:17:14 UTC (rev 3080)
@@ -118,6 +118,7 @@
 PMC PMC-49FL002
 PMC PMC-49FL004
 Sharp LHF-00L04
+Spansion S25FL016A
 SST SST-29EE020A
 SST SST-28SF040A
 SST SST-39SF010A


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[coreboot] r3080 - trunk/util/flashrom

[svn]

Author: stuge
Date: 2008-01-27 08:17:14 +0100 (Sun, 27 Jan 2008)
New Revision: 3080

Modified:
   trunk/util/flashrom/README
Log:
Forgot to add Spansion S25FL016A to README, trivial.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-26 16:57:03 UTC (rev 3079)
+++ trunk/util/flashrom/README  2008-01-27 07:17:14 UTC (rev 3080)
@@ -118,6 +118,7 @@
 PMC PMC-49FL002
 PMC PMC-49FL004
 Sharp LHF-00L04
+Spansion S25FL016A
 SST SST-29EE020A
 SST SST-28SF040A
 SST SST-39SF010A


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[coreboot] r3081 - in trunk/coreboot-v2/src: arch/i386/boot include/boot

[svn]

Author: oxygene
Date: 2008-01-27 15:12:54 +0100 (Sun, 27 Jan 2008)
New Revision: 3081

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/include/boot/coreboot_tables.h
Log:
Add a new record type "console" for lbtable, and insert one record
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-27 
07:17:14 UTC (rev 3080)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-27 
14:12:54 UTC (rev 3081)
@@ -90,6 +90,39 @@
 #endif
 }
 
+void add_console(struct lb_header *header, u16 consoletype)
+{
+   struct lb_record *rec;
+   struct lb_console *console;
+   rec = lb_new_record(header);
+   console = (struct lb_console *)lb_new_record(header);
+   console->tag = LB_TAG_CONSOLE;
+   console->size = sizeof(*console);
+   console->type = consoletype;
+}
+
+void lb_console(struct lb_header *header)
+{
+#ifdef CONFIG_CONSOLE_SERIAL8250
+   add_console(header, LB_TAG_CONSOLE_SERIAL8250);
+#endif
+#ifdef CONFIG_CONSOLE_VGA
+   add_console(header, LB_TAG_CONSOLE_VGA);
+#endif
+#ifdef CONFIG_CONSOLE_BTEXT
+   add_console(header, LB_TAG_CONSOLE_BTEXT);
+#endif
+#ifdef CONFIG_CONSOLE_LOGBUF
+   add_console(header, LB_TAG_CONSOLE_LOGBUF);
+#endif
+#ifdef CONFIG_CONSOLE_SROM
+   add_console(header, LB_TAG_CONSOLE_SROM);
+#endif
+#ifdef CONFIG_USBDEBUG_DIRECT
+   add_console(header, LB_TAG_CONSOLE_EHCI);
+#endif
+}
+
 struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
struct lb_record *rec;
@@ -426,6 +459,8 @@
lb_mainboard(head);
/* Record the serial port, if present */
lb_serial(head);
+   /* Record our console setup */
+   lb_console(head);
/* Record our various random string information */
lb_strings(head);
 

Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h
===
--- trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-27 
07:17:14 UTC (rev 3080)
+++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-27 
14:12:54 UTC (rev 3081)
@@ -138,6 +138,8 @@
uint8_t  string[0];
 };
 
+/* 0xe is taken by v3 */
+
 #define LB_TAG_SERIAL  0x000f
 struct lb_serial {
uint32_t tag;
@@ -145,6 +147,20 @@
uint16_t ioport;
 };
 
+#define LB_TAG_CONSOLE 0x0010
+struct lb_console {
+   uint32_t tag;
+   uint32_t size;
+   uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250  0
+#define LB_TAG_CONSOLE_VGA 1
+#define LB_TAG_CONSOLE_BTEXT   2
+#define LB_TAG_CONSOLE_LOGBUF  3
+#define LB_TAG_CONSOLE_SROM4
+#define LB_TAG_CONSOLE_EHCI5
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */


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[coreboot] r3081 - in trunk/coreboot-v2/src: arch/i386/boot include/boot

[svn]

Author: oxygene
Date: 2008-01-27 15:12:54 +0100 (Sun, 27 Jan 2008)
New Revision: 3081

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/include/boot/coreboot_tables.h
Log:
Add a new record type "console" for lbtable, and insert one record
for each output device we support, so the payload can figure out
where to find consoles that the user cares about.

Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-27 
07:17:14 UTC (rev 3080)
+++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c   2008-01-27 
14:12:54 UTC (rev 3081)
@@ -90,6 +90,39 @@
 #endif
 }
 
+void add_console(struct lb_header *header, u16 consoletype)
+{
+   struct lb_record *rec;
+   struct lb_console *console;
+   rec = lb_new_record(header);
+   console = (struct lb_console *)lb_new_record(header);
+   console->tag = LB_TAG_CONSOLE;
+   console->size = sizeof(*console);
+   console->type = consoletype;
+}
+
+void lb_console(struct lb_header *header)
+{
+#ifdef CONFIG_CONSOLE_SERIAL8250
+   add_console(header, LB_TAG_CONSOLE_SERIAL8250);
+#endif
+#ifdef CONFIG_CONSOLE_VGA
+   add_console(header, LB_TAG_CONSOLE_VGA);
+#endif
+#ifdef CONFIG_CONSOLE_BTEXT
+   add_console(header, LB_TAG_CONSOLE_BTEXT);
+#endif
+#ifdef CONFIG_CONSOLE_LOGBUF
+   add_console(header, LB_TAG_CONSOLE_LOGBUF);
+#endif
+#ifdef CONFIG_CONSOLE_SROM
+   add_console(header, LB_TAG_CONSOLE_SROM);
+#endif
+#ifdef CONFIG_USBDEBUG_DIRECT
+   add_console(header, LB_TAG_CONSOLE_EHCI);
+#endif
+}
+
 struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
struct lb_record *rec;
@@ -426,6 +459,8 @@
lb_mainboard(head);
/* Record the serial port, if present */
lb_serial(head);
+   /* Record our console setup */
+   lb_console(head);
/* Record our various random string information */
lb_strings(head);
 

Modified: trunk/coreboot-v2/src/include/boot/coreboot_tables.h
===
--- trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-27 
07:17:14 UTC (rev 3080)
+++ trunk/coreboot-v2/src/include/boot/coreboot_tables.h2008-01-27 
14:12:54 UTC (rev 3081)
@@ -138,6 +138,8 @@
uint8_t  string[0];
 };
 
+/* 0xe is taken by v3 */
+
 #define LB_TAG_SERIAL  0x000f
 struct lb_serial {
uint32_t tag;
@@ -145,6 +147,20 @@
uint16_t ioport;
 };
 
+#define LB_TAG_CONSOLE 0x0010
+struct lb_console {
+   uint32_t tag;
+   uint32_t size;
+   uint16_t type;
+};
+
+#define LB_TAG_CONSOLE_SERIAL8250  0
+#define LB_TAG_CONSOLE_VGA 1
+#define LB_TAG_CONSOLE_BTEXT   2
+#define LB_TAG_CONSOLE_LOGBUF  3
+#define LB_TAG_CONSOLE_SROM4
+#define LB_TAG_CONSOLE_EHCI5
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */


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[coreboot] r3082 - trunk/util/flashrom

[svn]

Author: stuge
Date: 2008-01-27 17:21:21 +0100 (Sun, 27 Jan 2008)
New Revision: 3082

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/board_enable.c
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
Log:
Make the vendor name optional in the -m flashrom parameter when there's only
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/README  2008-01-27 16:21:21 UTC (rev 3082)
@@ -23,20 +23,20 @@
 -
 
  $ flashrom [-rwvEVfh] [-c chipname] [-s exclude_start] [-e exclude_end]
-[-m vendor:part] [-l file.layout] [-i imagename] [file]
-   -r | --read:read flash and save into file
-   -w | --write:   write file into flash (default when
-   file is specified)
-   -v | --verify:  verify flash against file
-   -E | --erase:   erase flash device
-   -V | --verbose: more verbose output
-   -c | --chip : probe only for specified flash chip
-   -s | --estart :   exclude start position
-   -e | --eend : exclude end postion
-   -m | --mainboard : override mainboard settings
-   -f | --force:   force write without checking image
-   -l | --layout :read rom layout from file
-   -i | --image :only flash image name from flash layout
+[-m [vendor:]part] [-l file.layout] [-i imagename] [file]
+   -r | --read:  read flash and save into file
+   -w | --write: write file into flash (default when
+ file is specified)
+   -v | --verify:verify flash against file
+   -E | --erase: erase flash device
+   -V | --verbose:   more verbose output
+   -c | --chip :   probe only for specified flash chip
+   -s | --estart : exclude start position
+   -e | --eend :   exclude end postion
+   -m | --mainboard <[vendor:]part>: override mainboard settings
+   -f | --force: force write without checking image
+   -l | --layout :  read rom layout from file
+   -i | --image :  only flash image name from flash layout
 
  If no file is specified, then all that happens
  is that flash info is dumped and the flash chip is set to writable.

Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/board_enable.c  2008-01-27 16:21:21 UTC (rev 3082)
@@ -413,9 +413,10 @@
 static struct board_pciid_enable *board_match_coreboot_name(const char 
*vendor, const char *part)
 {
struct board_pciid_enable *board = board_pciid_enables;
+   struct board_pciid_enable *partmatch = NULL;
 
for (; board->name; board++) {
-   if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
+   if (vendor && (!board->lb_vendor || strcmp(board->lb_vendor, 
vendor)))
continue;
 
if (!board->lb_part || strcmp(board->lb_part, part))
@@ -427,9 +428,24 @@
if (board->second_vendor &&
!pci_dev_find(board->second_vendor, 
board->second_device))
continue;
-   return board;
+
+   if (vendor)
+   return board;
+
+   if (partmatch) {
+   /* a second entry has a matching part name */
+   printf("AMBIGUOUS BOARD NAME: %s\n", part);
+   printf("At least vendors '%s' and '%s' match.\n",
+   partmatch->lb_vendor, board->lb_vendor);
+   printf("Please use the full -m vendor:part syntax.\n");
+   return NULL;
+   }
+   partmatch = board;
}
 
+   if (partmatch)
+   return partmatch;
+
printf("NOT FOUND %s:%s\n", vendor, part);
 
return NULL;
@@ -477,7 +493,7 @@
struct board_pciid_enable *board = NULL;
int ret = 0;
 
-   if (vendor && part)
+   if (part)
board = board_match_coreboot_name(vendor, part);
 
if (!board)

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/flashrom.8  2008-01-27 16:21:21 UTC (rev 3082)
@@ -40,11 +40,11 @@
 .B "\-e, \-\-eend"  
 Exclude end postion (o

[coreboot] r3082 - trunk/util/flashrom

[svn]

Author: stuge
Date: 2008-01-27 17:21:21 +0100 (Sun, 27 Jan 2008)
New Revision: 3082

Modified:
   trunk/util/flashrom/README
   trunk/util/flashrom/board_enable.c
   trunk/util/flashrom/flashrom.8
   trunk/util/flashrom/flashrom.c
Log:
Make the vendor name optional in the -m flashrom parameter when there's only
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.

Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/README
===
--- trunk/util/flashrom/README  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/README  2008-01-27 16:21:21 UTC (rev 3082)
@@ -23,20 +23,20 @@
 -
 
  $ flashrom [-rwvEVfh] [-c chipname] [-s exclude_start] [-e exclude_end]
-[-m vendor:part] [-l file.layout] [-i imagename] [file]
-   -r | --read:read flash and save into file
-   -w | --write:   write file into flash (default when
-   file is specified)
-   -v | --verify:  verify flash against file
-   -E | --erase:   erase flash device
-   -V | --verbose: more verbose output
-   -c | --chip : probe only for specified flash chip
-   -s | --estart :   exclude start position
-   -e | --eend : exclude end postion
-   -m | --mainboard : override mainboard settings
-   -f | --force:   force write without checking image
-   -l | --layout :read rom layout from file
-   -i | --image :only flash image name from flash layout
+[-m [vendor:]part] [-l file.layout] [-i imagename] [file]
+   -r | --read:  read flash and save into file
+   -w | --write: write file into flash (default when
+ file is specified)
+   -v | --verify:verify flash against file
+   -E | --erase: erase flash device
+   -V | --verbose:   more verbose output
+   -c | --chip :   probe only for specified flash chip
+   -s | --estart : exclude start position
+   -e | --eend :   exclude end postion
+   -m | --mainboard <[vendor:]part>: override mainboard settings
+   -f | --force: force write without checking image
+   -l | --layout :  read rom layout from file
+   -i | --image :  only flash image name from flash layout
 
  If no file is specified, then all that happens
  is that flash info is dumped and the flash chip is set to writable.

Modified: trunk/util/flashrom/board_enable.c
===
--- trunk/util/flashrom/board_enable.c  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/board_enable.c  2008-01-27 16:21:21 UTC (rev 3082)
@@ -413,9 +413,10 @@
 static struct board_pciid_enable *board_match_coreboot_name(const char 
*vendor, const char *part)
 {
struct board_pciid_enable *board = board_pciid_enables;
+   struct board_pciid_enable *partmatch = NULL;
 
for (; board->name; board++) {
-   if (!board->lb_vendor || strcmp(board->lb_vendor, vendor))
+   if (vendor && (!board->lb_vendor || strcmp(board->lb_vendor, 
vendor)))
continue;
 
if (!board->lb_part || strcmp(board->lb_part, part))
@@ -427,9 +428,24 @@
if (board->second_vendor &&
!pci_dev_find(board->second_vendor, 
board->second_device))
continue;
-   return board;
+
+   if (vendor)
+   return board;
+
+   if (partmatch) {
+   /* a second entry has a matching part name */
+   printf("AMBIGUOUS BOARD NAME: %s\n", part);
+   printf("At least vendors '%s' and '%s' match.\n",
+   partmatch->lb_vendor, board->lb_vendor);
+   printf("Please use the full -m vendor:part syntax.\n");
+   return NULL;
+   }
+   partmatch = board;
}
 
+   if (partmatch)
+   return partmatch;
+
printf("NOT FOUND %s:%s\n", vendor, part);
 
return NULL;
@@ -477,7 +493,7 @@
struct board_pciid_enable *board = NULL;
int ret = 0;
 
-   if (vendor && part)
+   if (part)
board = board_match_coreboot_name(vendor, part);
 
if (!board)

Modified: trunk/util/flashrom/flashrom.8
===
--- trunk/util/flashrom/flashrom.8  2008-01-27 14:12:54 UTC (rev 3081)
+++ trunk/util/flashrom/flashrom.8  2008-01-27 16:21:21 UTC (rev 3082)
@@ -40,11 +40,11 @@
 .B "\-e, \-\-eend"  
 Exclude end postion (o

[coreboot] r3083 - in trunk/coreboot-v2: src/mainboard src/mainboard/abit src/mainboard/abit/be6-ii_v2_0 targets targets/abit targets/abit/be6-ii_v2_0

[svn]

Author: uwe
Date: 2008-01-27 18:25:49 +0100 (Sun, 27 Jan 2008)
New Revision: 3083

Added:
   trunk/coreboot-v2/src/mainboard/abit/
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/chip.h
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/mainboard.c
   trunk/coreboot-v2/targets/abit/
   trunk/coreboot-v2/targets/abit/be6-ii_v2_0/
   trunk/coreboot-v2/targets/abit/be6-ii_v2_0/Config.lb
Log:
Add support for the Abit BE6-II V2.0 board.
Tested on actual hardware by Sergei Antonov <[EMAIL PROTECTED]>. 

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Sergei Antonov <[EMAIL PROTECTED]>



Added: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb  
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb  2008-01-27 
17:25:49 UTC (rev 3083)
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+   default ROM_SECTION_SIZE = FALLBACK_SIZE
+   default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+   default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+   default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0x - ROM_SIZE
+   + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE
+   object irq_tables.o
+end
+makerule ./failover.E
+   depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+   action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+   depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+   action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+   # depends   "$(MAINBOARD)/auto.c option_table.h ./romcc"
+   depends "$(MAINBOARD)/auto.c ./romcc"
+   action  "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c 
-o $@"
+end
+makerule ./auto.inc
+   # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+   depends "$(MAINBOARD)/auto.c ./romcc"
+   action  "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o 
$@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+   mainboardinit cpu/x86/16bit/reset16.inc
+   ldscript /cpu/x86/16bit/reset16.lds
+else
+   mainboardinit cpu/x86/32bit/reset32.inc
+   ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+   ldscript /arch/i386/lib/failover.lds
+   mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i440bx  # Northbridge
+  device apic_cluster 0 on # APIC cluster
+chip cpu/intel/slot_2  # CPU (FIXME: It's slot 1, actually)
+  device apic 0 on end # APIC
+end
+  end
+  device pci_domain 0 on   # PCI domain
+device pci 0.0 on end  # Host bridge
+device pci 1.0 on end  # PCI/AGP bridge
+chip southbridge/intel/i82371eb# Southbridge
+  device pci 7.0 on# 

[coreboot] r3083 - in trunk/coreboot-v2: src/mainboard src/mainboard/abit src/mainboard/abit/be6-ii_v2_0 targets targets/abit targets/abit/be6-ii_v2_0

[svn]

Author: uwe
Date: 2008-01-27 18:25:49 +0100 (Sun, 27 Jan 2008)
New Revision: 3083

Added:
   trunk/coreboot-v2/src/mainboard/abit/
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Options.lb
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/auto.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/chip.h
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/irq_tables.c
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/mainboard.c
   trunk/coreboot-v2/targets/abit/
   trunk/coreboot-v2/targets/abit/be6-ii_v2_0/
   trunk/coreboot-v2/targets/abit/be6-ii_v2_0/Config.lb
Log:
Add support for the Abit BE6-II V2.0 board.
Tested on actual hardware by Sergei Antonov <[EMAIL PROTECTED]>. 

Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Sergei Antonov <[EMAIL PROTECTED]>



Added: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb  
(rev 0)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/Config.lb  2008-01-27 
17:25:49 UTC (rev 3083)
@@ -0,0 +1,141 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+   default ROM_SECTION_SIZE = FALLBACK_SIZE
+   default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+   default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+   default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0x - ROM_SIZE
+   + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE
+   object irq_tables.o
+end
+makerule ./failover.E
+   depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+   action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. 
$(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+   depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+   action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+   # depends   "$(MAINBOARD)/auto.c option_table.h ./romcc"
+   depends "$(MAINBOARD)/auto.c ./romcc"
+   action  "./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c 
-o $@"
+end
+makerule ./auto.inc
+   # depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+   depends "$(MAINBOARD)/auto.c ./romcc"
+   action  "./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o 
$@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+   mainboardinit cpu/x86/16bit/reset16.inc
+   ldscript /cpu/x86/16bit/reset16.lds
+else
+   mainboardinit cpu/x86/32bit/reset32.inc
+   ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+   ldscript /arch/i386/lib/failover.lds
+   mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i440bx  # Northbridge
+  device apic_cluster 0 on # APIC cluster
+chip cpu/intel/slot_2  # CPU (FIXME: It's slot 1, actually)
+  device apic 0 on end # APIC
+end
+  end
+  device pci_domain 0 on   # PCI domain
+device pci 0.0 on end  # Host bridge
+device pci 1.0 on end  # PCI/AGP bridge
+chip southbridge/intel/i82371eb# Southbridge
+  device pci 7.0 on# 

[coreboot] r3084 - trunk/util/mptable

[svn]

Author: cozzie
Date: 2008-01-28 01:04:23 +0100 (Mon, 28 Jan 2008)
New Revision: 3084

Modified:
   trunk/util/mptable/mptable.c
Log:
Fix mptable util so the output will compile

Signed-off-by: Jon Dufresne <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>



Modified: trunk/util/mptable/mptable.c
===
--- trunk/util/mptable/mptable.c2008-01-27 17:25:49 UTC (rev 3083)
+++ trunk/util/mptable/mptable.c2008-01-28 00:04:23 UTC (rev 3084)
@@ -302,10 +302,10 @@
 /* preamble to the mptable. This is fixed for all coreboots */
  
 char *preamble[] = {
+"#include ",
 "#include ",
+"#include ",
 "#include ",
-"#include ",
-"#include ",
 "#include ",
 "",
 "void *smp_write_config_table(void *v)",
@@ -361,31 +361,35 @@
 char *ioapic_code[] = {
 "  smp_write_ioapic(mc, 2, 0x20, 0xfec0);",
 "  {",
-"  struct pci_dev *dev;",
-"  uint32_t base;",
-"  dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));",
+"  device_t dev;",
+"  struct resource *res;",
+"  dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));",
 "  if (dev) {",
-"  pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);",
-"  base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"  smp_write_ioapic(mc, 3, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 3, 0x20, res->base);",
+"  }",
 "  }",
-"  dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));",
+"  dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));",
 "  if (dev) {",
-"  pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);",
-"  base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"  smp_write_ioapic(mc, 4, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 4, 0x20, res->base);",
+"  }",
 "  }",
-"dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));",
+"dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));",
 "if (dev) {",
-"pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, 
&base);",
-"base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"smp_write_ioapic(mc, 5, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 5, 0x20, res->base);",
+"  }",
 "}",
-"dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));",
+"dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));",
 "if (dev) {",
-"pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, 
&base);",
-"base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"smp_write_ioapic(mc, 8, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 8, 0x20, res->base);",
+"  }",
 "}",
 "  }",
 0
@@ -1122,10 +1126,10 @@
 };
 
 char* polarityMode[] = {
-"conforms", "MP_IRQ_POLARITY_HIGH", "reserved", "MP_IRQ_POLARITY_LOW"
+"MP_IRQ_POLARITY_DEFAULT", "MP_IRQ_POLARITY_HIGH", "reserved", 
"MP_IRQ_POLARITY_LOW"
 };
 char* triggerMode[] = {
-"conforms", "MP_IRQ_TRIGGER_EDGE", "reserved", "MP_IRQ_TRIGGER_LEVEL"
+"MP_IRQ_TRIGGER_DEFAULT", "MP_IRQ_TRIGGER_EDGE", "reserved", 
"MP_IRQ_TRIGGER_LEVEL"
 };
 
 static void


-- 
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[coreboot] r3084 - trunk/util/mptable

[svn]

Author: cozzie
Date: 2008-01-28 01:04:23 +0100 (Mon, 28 Jan 2008)
New Revision: 3084

Modified:
   trunk/util/mptable/mptable.c
Log:
Fix mptable util so the output will compile

Signed-off-by: Jon Dufresne <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>



Modified: trunk/util/mptable/mptable.c
===
--- trunk/util/mptable/mptable.c2008-01-27 17:25:49 UTC (rev 3083)
+++ trunk/util/mptable/mptable.c2008-01-28 00:04:23 UTC (rev 3084)
@@ -302,10 +302,10 @@
 /* preamble to the mptable. This is fixed for all coreboots */
  
 char *preamble[] = {
+"#include ",
 "#include ",
+"#include ",
 "#include ",
-"#include ",
-"#include ",
 "#include ",
 "",
 "void *smp_write_config_table(void *v)",
@@ -361,31 +361,35 @@
 char *ioapic_code[] = {
 "  smp_write_ioapic(mc, 2, 0x20, 0xfec0);",
 "  {",
-"  struct pci_dev *dev;",
-"  uint32_t base;",
-"  dev = pci_find_slot(1, PCI_DEVFN(0x1e,0));",
+"  device_t dev;",
+"  struct resource *res;",
+"  dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));",
 "  if (dev) {",
-"  pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);",
-"  base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"  smp_write_ioapic(mc, 3, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 3, 0x20, res->base);",
+"  }",
 "  }",
-"  dev = pci_find_slot(1, PCI_DEVFN(0x1c,0));",
+"  dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));",
 "  if (dev) {",
-"  pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &base);",
-"  base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"  smp_write_ioapic(mc, 4, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 4, 0x20, res->base);",
+"  }",
 "  }",
-"dev = pci_find_slot(4, PCI_DEVFN(0x1e,0));",
+"dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));",
 "if (dev) {",
-"pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, 
&base);",
-"base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"smp_write_ioapic(mc, 5, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 5, 0x20, res->base);",
+"  }",
 "}",
-"dev = pci_find_slot(4, PCI_DEVFN(0x1c,0));",
+"dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));",
 "if (dev) {",
-"pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, 
&base);",
-"base &= PCI_BASE_ADDRESS_MEM_MASK;",
-"smp_write_ioapic(mc, 8, 0x20, base);",
+"  res = find_resource(dev, PCI_BASE_ADDRESS_0);",
+"  if (res) {",
+"  smp_write_ioapic(mc, 8, 0x20, res->base);",
+"  }",
 "}",
 "  }",
 0
@@ -1122,10 +1126,10 @@
 };
 
 char* polarityMode[] = {
-"conforms", "MP_IRQ_POLARITY_HIGH", "reserved", "MP_IRQ_POLARITY_LOW"
+"MP_IRQ_POLARITY_DEFAULT", "MP_IRQ_POLARITY_HIGH", "reserved", 
"MP_IRQ_POLARITY_LOW"
 };
 char* triggerMode[] = {
-"conforms", "MP_IRQ_TRIGGER_EDGE", "reserved", "MP_IRQ_TRIGGER_LEVEL"
+"MP_IRQ_TRIGGER_DEFAULT", "MP_IRQ_TRIGGER_EDGE", "reserved", 
"MP_IRQ_TRIGGER_LEVEL"
 };
 
 static void


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[coreboot] r565 - coreboot-v3/arch/x86

[svn]

Author: stepan
Date: 2008-01-28 18:50:56 +0100 (Mon, 28 Jan 2008)
New Revision: 565

Added:
   coreboot-v3/arch/x86/coreboot_table.c
Removed:
   coreboot-v3/arch/x86/linuxbios_table.c
Log:
rename linuxbios_table.c

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Copied: coreboot-v3/arch/x86/coreboot_table.c (from rev 564, 
coreboot-v3/arch/x86/linuxbios_table.c)
===
--- coreboot-v3/arch/x86/coreboot_table.c   (rev 0)
+++ coreboot-v3/arch/x86/coreboot_table.c   2008-01-28 17:50:56 UTC (rev 
565)
@@ -0,0 +1,466 @@
+/*
+ * table management code for coreboot tables
+ *
+ * Copyright (C) 2002 Eric Biederman, Linux NetworX
+ * Copyright (C) 2007 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+//#include 
+//#include 
+//#include 
+//#include 
+
+struct lb_header *lb_table_init(unsigned long addr)
+{
+   struct lb_header *header;
+
+   /* 16 byte align the address */
+   addr += 15;
+   addr &= ~15;
+
+   header = (void *)addr;
+   header->signature[0] = 'L';
+   header->signature[1] = 'B';
+   header->signature[2] = 'I';
+   header->signature[3] = 'O';
+   header->header_bytes = sizeof(*header);
+   header->header_checksum = 0;
+   header->table_bytes = 0;
+   header->table_checksum = 0;
+   header->table_entries = 0;
+   return header;
+}
+
+struct lb_record *lb_first_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = (void *)(((char *)header) + sizeof(*header));
+   return rec;
+}
+
+struct lb_record *lb_last_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = (void *)(((char *)header) + sizeof(*header) + 
header->table_bytes);
+   return rec;
+}
+
+struct lb_record *lb_next_record(struct lb_record *rec)
+{
+   rec = (void *)(((char *)rec) + rec->size);  
+   return rec;
+}
+
+struct lb_record *lb_new_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = lb_last_record(header);
+   if (header->table_entries) {
+   header->table_bytes += rec->size;
+   }
+   rec = lb_last_record(header);
+   header->table_entries++;
+   rec->tag = LB_TAG_UNUSED;
+   rec->size = sizeof(*rec);
+   return rec;
+}
+
+
+struct lb_memory *lb_memory(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct lb_memory *mem;
+   rec = lb_new_record(header);
+   mem = (struct lb_memory *)rec;
+   mem->tag = LB_TAG_MEMORY;
+   mem->size = sizeof(*mem);
+   return mem;
+}
+
+struct lb_mainboard *lb_mainboard(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct lb_mainboard *mainboard;
+   extern char *mainboard_vendor, *mainboard_part_number;
+   rec = lb_new_record(header);
+   mainboard = (struct lb_mainboard *)rec;
+   mainboard->tag = LB_TAG_MAINBOARD;
+
+   mainboard->size = (sizeof(*mainboard) +
+   strlen(mainboard_vendor) + 1 + 
+   strlen(mainboard_part_number) + 1 +
+   3) & ~3;
+
+   mainboard->vendor_idx = 0;
+   mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
+
+   memcpy(mainboard->strings + mainboard->vendor_idx,
+   mainboard_vendor,  strlen(mainboard_vendor) + 1);
+   memcpy(mainboard->strings + mainboard->part_number_idx,
+   mainboard_part_number, strlen(mainboard_part_number) + 1);
+
+   return mainboard;
+}
+
+struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct cmos_checksum *cmos_checksum;
+   rec = lb_new_record(header);
+   cmos_checksum = (struct cmos_checksum *)rec;
+   cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
+
+   cmos_checksum->size = (sizeof(*cmos_checksum));
+
+   cmos_checksum->range_start = CB_CKS_RANGE_START * 8;
+   cmos_checksum->range_end = ( CB_CKS_RANGE_END * 8 ) + 7;
+   cmos_checksum->location = CB_CKS_LOC * 8;
+
+   cmos_checksum->type = CHECKSUM_PCBIOS;
+
+   return cmos_checksum;
+}
+
+void lb_strings(struct lb_header *header)
+{
+   static const struc

[coreboot] r3085 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10

[svn]

Author: jcrouse
Date: 2008-01-28 20:22:29 +0100 (Mon, 28 Jan 2008)
New Revision: 3085

Modified:
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
Log:
[V2]:  Add CFLAGS to targets to suck in any passed in flags

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb   
2008-01-28 00:04:23 UTC (rev 3084)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb   
2008-01-28 19:22:29 UTC (rev 3085)
@@ -136,14 +136,14 @@
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -o $@"
end
 
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -S -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
@@ -156,7 +156,7 @@
 if CONFIG_AP_CODE_IN_CAR
 makerule ./apc_auto.o
 depends "$(MAINBOARD)/apc_auto.c option_table.h"
-action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 end
 ldscript /arch/i386/init/ldscript_apc.lb
 end


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[coreboot] r3085 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10

[svn]

Author: jcrouse
Date: 2008-01-28 20:22:29 +0100 (Mon, 28 Jan 2008)
New Revision: 3085

Modified:
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
Log:
[V2]:  Add CFLAGS to targets to suck in any passed in flags

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>



Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb   
2008-01-28 00:04:23 UTC (rev 3084)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb   
2008-01-28 19:22:29 UTC (rev 3085)
@@ -136,14 +136,14 @@
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -o $@"
end
 
else
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) 
option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -S -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall 
-c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
@@ -156,7 +156,7 @@
 if CONFIG_AP_CODE_IN_CAR
 makerule ./apc_auto.o
 depends "$(MAINBOARD)/apc_auto.c option_table.h"
-action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 end
 ldscript /arch/i386/init/ldscript_apc.lb
 end


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[coreboot] r3086 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah

[svn]

Author: jcrouse
Date: 2008-01-28 23:55:47 +0100 (Mon, 28 Jan 2008)
New Revision: 3086

Modified:
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
Log:
v2:  Fix Serengeti-Cheetah flags too

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 
2008-01-28 19:22:29 UTC (rev 3085)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 
2008-01-28 22:55:47 UTC (rev 3086)
@@ -147,7 +147,7 @@
 if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(DISTRO_CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
 end


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[coreboot] r3086 - trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah

[svn]

Author: jcrouse
Date: 2008-01-28 23:55:47 +0100 (Mon, 28 Jan 2008)
New Revision: 3086

Modified:
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
Log:
v2:  Fix Serengeti-Cheetah flags too

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>


Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
===
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 
2008-01-28 19:22:29 UTC (rev 3085)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 
2008-01-28 22:55:47 UTC (rev 3086)
@@ -147,7 +147,7 @@
 if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h"
-   action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+   action "$(CC) -I$(TOP)/src -I. $(DISTRO_CFLAGS) $(CPPFLAGS) 
$(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
 end


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[coreboot] r565 - coreboot-v3/arch/x86

[svn]

Author: stepan
Date: 2008-01-28 18:50:56 +0100 (Mon, 28 Jan 2008)
New Revision: 565

Added:
   coreboot-v3/arch/x86/coreboot_table.c
Removed:
   coreboot-v3/arch/x86/linuxbios_table.c
Log:
rename linuxbios_table.c

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Copied: coreboot-v3/arch/x86/coreboot_table.c (from rev 564, 
coreboot-v3/arch/x86/linuxbios_table.c)
===
--- coreboot-v3/arch/x86/coreboot_table.c   (rev 0)
+++ coreboot-v3/arch/x86/coreboot_table.c   2008-01-28 17:50:56 UTC (rev 
565)
@@ -0,0 +1,466 @@
+/*
+ * table management code for coreboot tables
+ *
+ * Copyright (C) 2002 Eric Biederman, Linux NetworX
+ * Copyright (C) 2007 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+//#include 
+//#include 
+//#include 
+//#include 
+
+struct lb_header *lb_table_init(unsigned long addr)
+{
+   struct lb_header *header;
+
+   /* 16 byte align the address */
+   addr += 15;
+   addr &= ~15;
+
+   header = (void *)addr;
+   header->signature[0] = 'L';
+   header->signature[1] = 'B';
+   header->signature[2] = 'I';
+   header->signature[3] = 'O';
+   header->header_bytes = sizeof(*header);
+   header->header_checksum = 0;
+   header->table_bytes = 0;
+   header->table_checksum = 0;
+   header->table_entries = 0;
+   return header;
+}
+
+struct lb_record *lb_first_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = (void *)(((char *)header) + sizeof(*header));
+   return rec;
+}
+
+struct lb_record *lb_last_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = (void *)(((char *)header) + sizeof(*header) + 
header->table_bytes);
+   return rec;
+}
+
+struct lb_record *lb_next_record(struct lb_record *rec)
+{
+   rec = (void *)(((char *)rec) + rec->size);  
+   return rec;
+}
+
+struct lb_record *lb_new_record(struct lb_header *header)
+{
+   struct lb_record *rec;
+   rec = lb_last_record(header);
+   if (header->table_entries) {
+   header->table_bytes += rec->size;
+   }
+   rec = lb_last_record(header);
+   header->table_entries++;
+   rec->tag = LB_TAG_UNUSED;
+   rec->size = sizeof(*rec);
+   return rec;
+}
+
+
+struct lb_memory *lb_memory(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct lb_memory *mem;
+   rec = lb_new_record(header);
+   mem = (struct lb_memory *)rec;
+   mem->tag = LB_TAG_MEMORY;
+   mem->size = sizeof(*mem);
+   return mem;
+}
+
+struct lb_mainboard *lb_mainboard(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct lb_mainboard *mainboard;
+   extern char *mainboard_vendor, *mainboard_part_number;
+   rec = lb_new_record(header);
+   mainboard = (struct lb_mainboard *)rec;
+   mainboard->tag = LB_TAG_MAINBOARD;
+
+   mainboard->size = (sizeof(*mainboard) +
+   strlen(mainboard_vendor) + 1 + 
+   strlen(mainboard_part_number) + 1 +
+   3) & ~3;
+
+   mainboard->vendor_idx = 0;
+   mainboard->part_number_idx = strlen(mainboard_vendor) + 1;
+
+   memcpy(mainboard->strings + mainboard->vendor_idx,
+   mainboard_vendor,  strlen(mainboard_vendor) + 1);
+   memcpy(mainboard->strings + mainboard->part_number_idx,
+   mainboard_part_number, strlen(mainboard_part_number) + 1);
+
+   return mainboard;
+}
+
+struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
+{
+   struct lb_record *rec;
+   struct cmos_checksum *cmos_checksum;
+   rec = lb_new_record(header);
+   cmos_checksum = (struct cmos_checksum *)rec;
+   cmos_checksum->tag = LB_TAG_OPTION_CHECKSUM;
+
+   cmos_checksum->size = (sizeof(*cmos_checksum));
+
+   cmos_checksum->range_start = CB_CKS_RANGE_START * 8;
+   cmos_checksum->range_end = ( CB_CKS_RANGE_END * 8 ) + 7;
+   cmos_checksum->location = CB_CKS_LOC * 8;
+
+   cmos_checksum->type = CHECKSUM_PCBIOS;
+
+   return cmos_checksum;
+}
+
+void lb_strings(struct lb_header *header)
+{
+   static const struc

[coreboot] r101 - in buildrom-devel: . config/platforms packages/coreboot-v2/patches

[svn]

Author: jcrouse
Date: 2008-01-29 16:53:02 +0100 (Tue, 29 Jan 2008)
New Revision: 101

Modified:
   buildrom-devel/Makefile
   buildrom-devel/config/platforms/alix1c.conf
   buildrom-devel/config/platforms/db800.conf
   buildrom-devel/config/platforms/dbe61.conf
   buildrom-devel/config/platforms/ga-2761gxdk.conf
   buildrom-devel/config/platforms/m57sli.conf
   buildrom-devel/config/platforms/msm800sev.conf
   buildrom-devel/config/platforms/norwich.conf
   buildrom-devel/config/platforms/qemu.conf
   buildrom-devel/config/platforms/serengeti_cheetah.conf
   buildrom-devel/config/platforms/supermicro-h8dmr.conf
   buildrom-devel/config/platforms/tyan-s2882.conf
   buildrom-devel/config/platforms/tyan-s2891.conf
   buildrom-devel/packages/coreboot-v2/patches/2761gxdk-fix-target.patch
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-filo-and-etherboot-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/qemu-payload.patch
   buildrom-devel/packages/coreboot-v2/patches/serengeti_cheetah-lab.patch
   buildrom-devel/packages/coreboot-v2/patches/serengeti_cheetah-payload.patch
   
buildrom-devel/packages/coreboot-v2/patches/supermicro-h8dmr-filo-and-etherboot-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/supermicro-h8dmr-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/tyan-s2882-filo-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/tyan-s2882-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/tyan-s2891-filo-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/tyan-s2891-kernel-and-lab-Config.lb.patch
Log:
[BUILDROM]:  Fixup all of the coreboot SVN revisions

Bump all platforms to newer versions of the coreboot SVN to take into
account the renaming and bug fixes.

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>



Modified: buildrom-devel/Makefile
===
--- buildrom-devel/Makefile 2008-01-18 18:39:21 UTC (rev 100)
+++ buildrom-devel/Makefile 2008-01-29 15:53:02 UTC (rev 101)
@@ -43,7 +43,7 @@
 # TARGET_ROM is what we are ultimately building - this should be
 # specified by the platform files
 
-TARGET_ROM ?= linuxbios.rom
+TARGET_ROM ?= coreboot.rom
 TARGET_ROM_FILE=$(OUTPUT_DIR)/$(TARGET_ROM)
 
 # Choose the version of coreboot to build - this might be better

Modified: buildrom-devel/config/platforms/alix1c.conf
===
--- buildrom-devel/config/platforms/alix1c.conf 2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/alix1c.conf 2008-01-29 15:53:02 UTC (rev 
101)
@@ -29,8 +29,8 @@
 COREBOOT_BOARD=alix1c
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=alix1c
-CBV2_TAG=3047
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/db800.conf
===
--- buildrom-devel/config/platforms/db800.conf  2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/db800.conf  2008-01-29 15:53:02 UTC (rev 
101)
@@ -32,7 +32,7 @@
 COREBOOT_BOARD=db800
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=db800
-CBV2_TAG=2810
+CBV2_TAG=3079
 COREBOOT_ROM_NAME=db800.rom
 
 # FILO configuration

Modified: buildrom-devel/config/platforms/dbe61.conf
===
--- buildrom-devel/config/platforms/dbe61.conf  2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/dbe61.conf  2008-01-29 15:53:02 UTC (rev 
101)
@@ -31,7 +31,7 @@
 COREBOOT_BOARD=dbe61
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=dbe61
-CBV2_TAG=2728
+CBV2_TAG=3079
 COREBOOT_ROM_NAME=dbe61.rom
 
 # FILO configuration

Modified: buildrom-devel/config/platforms/ga-2761gxdk.conf
===
--- buildrom-devel/config/platforms/ga-2761gxdk.conf2008-01-18 18:39:21 UTC 
(rev 100)
+++ buildrom-devel/config/platforms/ga-2761gxdk.conf2008-01-29 15:53:02 UTC 
(rev 101)
@@ -36,8 +36,8 @@
 COREBOOT_BOARD=ga_2761gxdk
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=ga_2761gxdk
-CBV2_TAG=2908
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/m57sli.conf
===
--- buildrom-devel/config/platforms/m57sli.conf 2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/m57sli.conf 2008-01-29 15:53:02 UTC (rev 
101)
@@ -40,8 +40,8 @@
 COREBOOT_BOARD=m57sli
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=m57sli
-CBV2_TAG=2958
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/ms

[coreboot] r101 - in buildrom-devel: . config/platforms packages/coreboot-v2/patches

[svn]

Author: jcrouse
Date: 2008-01-29 16:53:02 +0100 (Tue, 29 Jan 2008)
New Revision: 101

Modified:
   buildrom-devel/Makefile
   buildrom-devel/config/platforms/alix1c.conf
   buildrom-devel/config/platforms/db800.conf
   buildrom-devel/config/platforms/dbe61.conf
   buildrom-devel/config/platforms/ga-2761gxdk.conf
   buildrom-devel/config/platforms/m57sli.conf
   buildrom-devel/config/platforms/msm800sev.conf
   buildrom-devel/config/platforms/norwich.conf
   buildrom-devel/config/platforms/qemu.conf
   buildrom-devel/config/platforms/serengeti_cheetah.conf
   buildrom-devel/config/platforms/supermicro-h8dmr.conf
   buildrom-devel/config/platforms/tyan-s2882.conf
   buildrom-devel/config/platforms/tyan-s2891.conf
   buildrom-devel/packages/coreboot-v2/patches/2761gxdk-fix-target.patch
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-filo-and-etherboot-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/qemu-payload.patch
   buildrom-devel/packages/coreboot-v2/patches/serengeti_cheetah-lab.patch
   buildrom-devel/packages/coreboot-v2/patches/serengeti_cheetah-payload.patch
   
buildrom-devel/packages/coreboot-v2/patches/supermicro-h8dmr-filo-and-etherboot-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/supermicro-h8dmr-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/tyan-s2882-filo-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/tyan-s2882-kernel-and-lab-Config.lb.patch
   buildrom-devel/packages/coreboot-v2/patches/tyan-s2891-filo-Config.lb.patch
   
buildrom-devel/packages/coreboot-v2/patches/tyan-s2891-kernel-and-lab-Config.lb.patch
Log:
[BUILDROM]:  Fixup all of the coreboot SVN revisions

Bump all platforms to newer versions of the coreboot SVN to take into
account the renaming and bug fixes.

Signed-off-by: Jordan Crouse <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>



Modified: buildrom-devel/Makefile
===
--- buildrom-devel/Makefile 2008-01-18 18:39:21 UTC (rev 100)
+++ buildrom-devel/Makefile 2008-01-29 15:53:02 UTC (rev 101)
@@ -43,7 +43,7 @@
 # TARGET_ROM is what we are ultimately building - this should be
 # specified by the platform files
 
-TARGET_ROM ?= linuxbios.rom
+TARGET_ROM ?= coreboot.rom
 TARGET_ROM_FILE=$(OUTPUT_DIR)/$(TARGET_ROM)
 
 # Choose the version of coreboot to build - this might be better

Modified: buildrom-devel/config/platforms/alix1c.conf
===
--- buildrom-devel/config/platforms/alix1c.conf 2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/alix1c.conf 2008-01-29 15:53:02 UTC (rev 
101)
@@ -29,8 +29,8 @@
 COREBOOT_BOARD=alix1c
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=alix1c
-CBV2_TAG=3047
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/db800.conf
===
--- buildrom-devel/config/platforms/db800.conf  2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/db800.conf  2008-01-29 15:53:02 UTC (rev 
101)
@@ -32,7 +32,7 @@
 COREBOOT_BOARD=db800
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=db800
-CBV2_TAG=2810
+CBV2_TAG=3079
 COREBOOT_ROM_NAME=db800.rom
 
 # FILO configuration

Modified: buildrom-devel/config/platforms/dbe61.conf
===
--- buildrom-devel/config/platforms/dbe61.conf  2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/dbe61.conf  2008-01-29 15:53:02 UTC (rev 
101)
@@ -31,7 +31,7 @@
 COREBOOT_BOARD=dbe61
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=dbe61
-CBV2_TAG=2728
+CBV2_TAG=3079
 COREBOOT_ROM_NAME=dbe61.rom
 
 # FILO configuration

Modified: buildrom-devel/config/platforms/ga-2761gxdk.conf
===
--- buildrom-devel/config/platforms/ga-2761gxdk.conf2008-01-18 18:39:21 UTC 
(rev 100)
+++ buildrom-devel/config/platforms/ga-2761gxdk.conf2008-01-29 15:53:02 UTC 
(rev 101)
@@ -36,8 +36,8 @@
 COREBOOT_BOARD=ga_2761gxdk
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=ga_2761gxdk
-CBV2_TAG=2908
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/m57sli.conf
===
--- buildrom-devel/config/platforms/m57sli.conf 2008-01-18 18:39:21 UTC (rev 
100)
+++ buildrom-devel/config/platforms/m57sli.conf 2008-01-29 15:53:02 UTC (rev 
101)
@@ -40,8 +40,8 @@
 COREBOOT_BOARD=m57sli
 CBV2_CONFIG=Config.lb
 CBV2_TDIR=m57sli
-CBV2_TAG=2958
-COREBOOT_ROM_NAME=linuxbios.rom
+CBV2_TAG=3079
+COREBOOT_ROM_NAME=coreboot.rom
 
 # FILO configuration
 

Modified: buildrom-devel/config/platforms/ms

[coreboot] r566 - in coreboot-v3: southbridge/amd/cs5536 util/dtc

[svn]

Author: rminnich
Date: 2008-01-29 18:48:10 +0100 (Tue, 29 Jan 2008)
New Revision: 566

Modified:
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
   coreboot-v3/util/dtc/dtc-parser.y
   coreboot-v3/util/dtc/dtc.c
   coreboot-v3/util/dtc/dtc.h
Log:
In the current version of dtc, if one has the line:
/config/ = "northbridge/amd/geodelx";

Then the file northbridge/amd/geodelx/dts is read in and processed. 
Magic(TM) appends the name "/dts" to the path. 

This hack is fine with chips that only do one thing. 
But some (all) northbridge parts play several roles: APIC cluster, PCI domain
device, and PCI device. The result is a need for more than one dts, since
there are three possible devices, with three types of IDs, and so on. 

To keep things sane, I am proposing to enable multiple dts files in a
directory, names (e.g., nothing required here):
domaindts
pcidts
apicdts

(of course these names can be anything, this is just an example).
This change will require a change to the dtc, since we can no longer
assume just one dts file, and hence need a way to name these different 
files. 

The proposed change is very simple. We now require the full path name 
for the file, and eliminate the Magic(TM).

So, 
/config/ = "northbridge/amd/geodelx/pcidts";

will open the pcidts file. 
/config/ = "northbridge/amd/geodelx/domaindts";
will open the domain dts. 

Maybe we should just call it domain and pci and apic? works for me.
/config/ = "northbridge/amd/geodelx/domain";
/config/ = "northbridge/amd/geodelx/pcibridge";
/config/ = "northbridge/amd/geodelx/apic";

Changes: 
dtc.c: create a new function, fopenfile, that will only open a path if it 
really is a file. Modify dtc_open_file to use this function. fopenfile
assumes "-" means stdin; should it, or should I move that assumption back
to dtc_open_file?
dtc.h: add prototypes
dtc-parser.y: Given a config path, open the path.
southbridge/amd/cs5536/cs5536.c: example of how C code changes


Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>

Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>

Please see the comments below, but they do not have to be addressed for
this commit, just keep them in mind for future commits in that area.



Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-28 17:50:56 UTC (rev 
565)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-29 17:48:10 UTC (rev 
566)
@@ -172,7 +172,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void lpc_init(struct southbridge_amd_cs5536_config *sb)
+static void lpc_init(struct southbridge_amd_cs5536_dts_config *sb)
 {
struct msr msr;
 
@@ -220,7 +220,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void uarts_init(struct southbridge_amd_cs5536_config *sb)
+static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
 {
struct msr msr;
u16 addr = 0;
@@ -383,7 +383,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
+static void enable_USB_port4(struct southbridge_amd_cs5536_dts_config *sb)
 {
u32 *bar;
struct msr msr;
@@ -475,7 +475,7 @@
 {
struct device *dev;
struct msr msr;
-   struct southbridge_amd_cs5536_config *sb;
+   struct southbridge_amd_cs5536_dts_config *sb;
const struct msrinit *csi;
 
post_code(P80_CHIPSET_INIT);
@@ -486,7 +486,7 @@
   __FUNCTION__);
return;
}
-   sb = (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+   sb = (struct southbridge_amd_cs5536_dts_config 
*)dev->device_configuration;
 
 #if 0
if (!IsS3Resume())
@@ -548,8 +548,8 @@
  */
 static void southbridge_init(struct device *dev)
 {
-   struct southbridge_amd_cs5536_config *sb =
-   (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+   struct southbridge_amd_cs5536_dts_config *sb =
+   (struct southbridge_amd_cs5536_dts_config 
*)dev->device_configuration;
 
/*
 * struct device *gpiodev;

Modified: coreboot-v3/util/dtc/dtc-parser.y
===
--- coreboot-v3/util/dtc/dtc-parser.y   2008-01-28 17:50:56 UTC (rev 565)
+++ coreboot-v3/util/dtc/dtc-parser.y   2008-01-29 17:48:10 UTC (rev 566)
@@ -121,17 +121,16 @@
 config:DT_CONFIG '(' 
includepath {
void switchin(FILE *f);
-
-   /* switch ... */
-   char path[1024];
FILE *f;
+   /* The need for a cast here is silly */
+   char *name = (char *)$3.val;
+
/* TODO: keep track of which of these we have read in. 
If we have already done it, then 
  * don't do it twice. 
 

[coreboot] r566 - in coreboot-v3: southbridge/amd/cs5536 util/dtc

[svn]

Author: rminnich
Date: 2008-01-29 18:48:10 +0100 (Tue, 29 Jan 2008)
New Revision: 566

Modified:
   coreboot-v3/southbridge/amd/cs5536/cs5536.c
   coreboot-v3/util/dtc/dtc-parser.y
   coreboot-v3/util/dtc/dtc.c
   coreboot-v3/util/dtc/dtc.h
Log:
In the current version of dtc, if one has the line:
/config/ = "northbridge/amd/geodelx";

Then the file northbridge/amd/geodelx/dts is read in and processed. 
Magic(TM) appends the name "/dts" to the path. 

This hack is fine with chips that only do one thing. 
But some (all) northbridge parts play several roles: APIC cluster, PCI domain
device, and PCI device. The result is a need for more than one dts, since
there are three possible devices, with three types of IDs, and so on. 

To keep things sane, I am proposing to enable multiple dts files in a
directory, names (e.g., nothing required here):
domaindts
pcidts
apicdts

(of course these names can be anything, this is just an example).
This change will require a change to the dtc, since we can no longer
assume just one dts file, and hence need a way to name these different 
files. 

The proposed change is very simple. We now require the full path name 
for the file, and eliminate the Magic(TM).

So, 
/config/ = "northbridge/amd/geodelx/pcidts";

will open the pcidts file. 
/config/ = "northbridge/amd/geodelx/domaindts";
will open the domain dts. 

Maybe we should just call it domain and pci and apic? works for me.
/config/ = "northbridge/amd/geodelx/domain";
/config/ = "northbridge/amd/geodelx/pcibridge";
/config/ = "northbridge/amd/geodelx/apic";

Changes: 
dtc.c: create a new function, fopenfile, that will only open a path if it 
really is a file. Modify dtc_open_file to use this function. fopenfile
assumes "-" means stdin; should it, or should I move that assumption back
to dtc_open_file?
dtc.h: add prototypes
dtc-parser.y: Given a config path, open the path.
southbridge/amd/cs5536/cs5536.c: example of how C code changes


Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>

Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>

Please see the comments below, but they do not have to be addressed for
this commit, just keep them in mind for future commits in that area.



Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-28 17:50:56 UTC (rev 
565)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-01-29 17:48:10 UTC (rev 
566)
@@ -172,7 +172,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void lpc_init(struct southbridge_amd_cs5536_config *sb)
+static void lpc_init(struct southbridge_amd_cs5536_dts_config *sb)
 {
struct msr msr;
 
@@ -220,7 +220,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void uarts_init(struct southbridge_amd_cs5536_config *sb)
+static void uarts_init(struct southbridge_amd_cs5536_dts_config *sb)
 {
struct msr msr;
u16 addr = 0;
@@ -383,7 +383,7 @@
  *
  * @param sb Southbridge config structure.
  */
-static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
+static void enable_USB_port4(struct southbridge_amd_cs5536_dts_config *sb)
 {
u32 *bar;
struct msr msr;
@@ -475,7 +475,7 @@
 {
struct device *dev;
struct msr msr;
-   struct southbridge_amd_cs5536_config *sb;
+   struct southbridge_amd_cs5536_dts_config *sb;
const struct msrinit *csi;
 
post_code(P80_CHIPSET_INIT);
@@ -486,7 +486,7 @@
   __FUNCTION__);
return;
}
-   sb = (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+   sb = (struct southbridge_amd_cs5536_dts_config 
*)dev->device_configuration;
 
 #if 0
if (!IsS3Resume())
@@ -548,8 +548,8 @@
  */
 static void southbridge_init(struct device *dev)
 {
-   struct southbridge_amd_cs5536_config *sb =
-   (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+   struct southbridge_amd_cs5536_dts_config *sb =
+   (struct southbridge_amd_cs5536_dts_config 
*)dev->device_configuration;
 
/*
 * struct device *gpiodev;

Modified: coreboot-v3/util/dtc/dtc-parser.y
===
--- coreboot-v3/util/dtc/dtc-parser.y   2008-01-28 17:50:56 UTC (rev 565)
+++ coreboot-v3/util/dtc/dtc-parser.y   2008-01-29 17:48:10 UTC (rev 566)
@@ -121,17 +121,16 @@
 config:DT_CONFIG '(' 
includepath {
void switchin(FILE *f);
-
-   /* switch ... */
-   char path[1024];
FILE *f;
+   /* The need for a cast here is silly */
+   char *name = (char *)$3.val;
+
/* TODO: keep track of which of these we have read in. 
If we have already done it, then 
  * don't do it twice. 
 

[coreboot] r568 - coreboot-v3/include

[svn]

Author: mjones
Date: 2008-01-30 01:48:41 +0100 (Wed, 30 Jan 2008)
New Revision: 568

Modified:
   coreboot-v3/include/lib.h
Log:
V3 compilation errors:
Clean up lib.h prototypes.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: coreboot-v3/include/lib.h
===
--- coreboot-v3/include/lib.h   2008-01-30 00:46:41 UTC (rev 567)
+++ coreboot-v3/include/lib.h   2008-01-30 00:48:41 UTC (rev 568)
@@ -36,11 +36,4 @@
 void beep_short(void);
 void beep_long(void);
 
-/* smbus functions */
-int smbus_read_byte(unsigned device, unsigned address);
-
-/* dram functions */
-void ram_failure(const char *why);
-void ram_initialize(int controllers, void *ctrl);
-
 #endif /* LIB_H */


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[coreboot] r568 - coreboot-v3/include

[svn]

Author: mjones
Date: 2008-01-30 01:48:41 +0100 (Wed, 30 Jan 2008)
New Revision: 568

Modified:
   coreboot-v3/include/lib.h
Log:
V3 compilation errors:
Clean up lib.h prototypes.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: coreboot-v3/include/lib.h
===
--- coreboot-v3/include/lib.h   2008-01-30 00:46:41 UTC (rev 567)
+++ coreboot-v3/include/lib.h   2008-01-30 00:48:41 UTC (rev 568)
@@ -36,11 +36,4 @@
 void beep_short(void);
 void beep_long(void);
 
-/* smbus functions */
-int smbus_read_byte(unsigned device, unsigned address);
-
-/* dram functions */
-void ram_failure(const char *why);
-void ram_initialize(int controllers, void *ctrl);
-
 #endif /* LIB_H */


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[coreboot] r567 - coreboot-v3/southbridge/amd/cs5536

[svn]

Author: mjones
Date: 2008-01-30 01:46:41 +0100 (Wed, 30 Jan 2008)
New Revision: 567

Modified:
   coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
Log:
V3 compilation errors:
Fix spd_read_byte prototype.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
===
--- coreboot-v3/southbridge/amd/cs5536/smbus_initram.c  2008-01-29 17:48:10 UTC 
(rev 566)
+++ coreboot-v3/southbridge/amd/cs5536/smbus_initram.c  2008-01-30 00:46:41 UTC 
(rev 567)
@@ -343,7 +343,7 @@
  * @param address The address.
  * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
  */
-int spd_read_byte(u16 device, u8 address)
+u8 spd_read_byte(u16 device, u8 address)
 {
return smbus_read_byte(device, address);
 }


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[coreboot] r567 - coreboot-v3/southbridge/amd/cs5536

[svn]

Author: mjones
Date: 2008-01-30 01:46:41 +0100 (Wed, 30 Jan 2008)
New Revision: 567

Modified:
   coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
Log:
V3 compilation errors:
Fix spd_read_byte prototype.

Signed-off-by: Marc Jones <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: coreboot-v3/southbridge/amd/cs5536/smbus_initram.c
===
--- coreboot-v3/southbridge/amd/cs5536/smbus_initram.c  2008-01-29 17:48:10 UTC 
(rev 566)
+++ coreboot-v3/southbridge/amd/cs5536/smbus_initram.c  2008-01-30 00:46:41 UTC 
(rev 567)
@@ -343,7 +343,7 @@
  * @param address The address.
  * @return The data from the SMBus packet area or an error of 0xff (i.e. -1).
  */
-int spd_read_byte(u16 device, u8 address)
+u8 spd_read_byte(u16 device, u8 address)
 {
return smbus_read_byte(device, address);
 }


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[coreboot] r102 - buildrom-devel/packages/coreboot-v2/patches

[svn]

Author: ward
Date: 2008-01-31 00:27:53 +0100 (Thu, 31 Jan 2008)
New Revision: 102

Modified:
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
Log:

This patch still had one LINUXBIOS string in it, which broke the LAB build for 
the m57sli. 

This is a trivial patch.

Signed-off-by: Ward Vandewege <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>



Modified: 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
===
--- 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   2008-01-29 15:53:02 UTC (rev 101)
+++ 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   2008-01-30 23:27:53 UTC (rev 102)
@@ -26,7 +26,7 @@
 -  option ROM_IMAGE_SIZE=0x2
 -# option ROM_IMAGE_SIZE=0x15800
 -  option XIP_ROM_SIZE=0x4
--  option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 -#   payload ../../../payloads/tg3--ide_disk.zelf
 -#payload ../../../payloads/filo.elf
 -#payload ../../../payloads/filo_mem.elf
@@ -60,7 +60,7 @@
 +  option CONFIG_PRECOMPRESSED_PAYLOAD=1
 +  option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x4
-   option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+   option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 -#   payload ../../../payloads/tg3--ide_disk.zelf
 -#payload ../../../payloads/filo.elf
 -#payload ../../../payloads/filo_mem.elf
@@ -92,7 +92,7 @@
  option USE_FALLBACK_IMAGE=0
  option ROM_IMAGE_SIZE=FAILOVER_SIZE
  option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
  end
  
 -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"


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[coreboot] r102 - buildrom-devel/packages/coreboot-v2/patches

[svn]

Author: ward
Date: 2008-01-31 00:27:53 +0100 (Thu, 31 Jan 2008)
New Revision: 102

Modified:
   
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
Log:

This patch still had one LINUXBIOS string in it, which broke the LAB build for 
the m57sli. 

This is a trivial patch.

Signed-off-by: Ward Vandewege <[EMAIL PROTECTED]>
Acked-by: Ward Vandewege <[EMAIL PROTECTED]>



Modified: 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
===
--- 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   2008-01-29 15:53:02 UTC (rev 101)
+++ 
buildrom-devel/packages/coreboot-v2/patches/m57sli-kernel-and-lab-Config.lb.patch
   2008-01-30 23:27:53 UTC (rev 102)
@@ -26,7 +26,7 @@
 -  option ROM_IMAGE_SIZE=0x2
 -# option ROM_IMAGE_SIZE=0x15800
 -  option XIP_ROM_SIZE=0x4
--  option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+-  option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 -#   payload ../../../payloads/tg3--ide_disk.zelf
 -#payload ../../../payloads/filo.elf
 -#payload ../../../payloads/filo_mem.elf
@@ -60,7 +60,7 @@
 +  option CONFIG_PRECOMPRESSED_PAYLOAD=1
 +  option ROM_IMAGE_SIZE=0x17000
option XIP_ROM_SIZE=0x4
-   option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+   option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 -#   payload ../../../payloads/tg3--ide_disk.zelf
 -#payload ../../../payloads/filo.elf
 -#payload ../../../payloads/filo_mem.elf
@@ -92,7 +92,7 @@
  option USE_FALLBACK_IMAGE=0
  option ROM_IMAGE_SIZE=FAILOVER_SIZE
  option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+ option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
  end
  
 -#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"


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