from:"coby via Phabricator via cfe\-commits"

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-29 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL314494: [X86][MS-InlineAsm] Extended support for variables / 
identifiers on memory /… (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D37413?vs=115564&id=117095#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  cfe/trunk/include/clang/Parse/Parser.h
  cfe/trunk/include/clang/Sema/Sema.h
  cfe/trunk/lib/Parse/ParseStmtAsm.cpp
  cfe/trunk/lib/Sema/SemaStmtAsm.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm-variables.c

Index: cfe/trunk/include/clang/Sema/Sema.h
===
--- cfe/trunk/include/clang/Sema/Sema.h
+++ cfe/trunk/include/clang/Sema/Sema.h
@@ -3788,15 +3788,15 @@
  Expr *AsmString, MultiExprArg Clobbers,
  SourceLocation RParenLoc);
 
+  void FillInlineAsmIdentifierInfo(Expr *Res,
+   llvm::InlineAsmIdentifierInfo &Info);
   ExprResult LookupInlineAsmIdentifier(CXXScopeSpec &SS,
SourceLocation TemplateKWLoc,
UnqualifiedId &Id,
-   llvm::InlineAsmIdentifierInfo &Info,
bool IsUnevaluatedContext);
   bool LookupInlineAsmField(StringRef Base, StringRef Member,
 unsigned &Offset, SourceLocation AsmLoc);
   ExprResult LookupInlineAsmVarDeclField(Expr *RefExpr, StringRef Member,
- llvm::InlineAsmIdentifierInfo &Info,
  SourceLocation AsmLoc);
   StmtResult ActOnMSAsmStmt(SourceLocation AsmLoc, SourceLocation LBraceLoc,
 ArrayRef AsmToks,
Index: cfe/trunk/include/clang/Parse/Parser.h
===
--- cfe/trunk/include/clang/Parse/Parser.h
+++ cfe/trunk/include/clang/Parse/Parser.h
@@ -1474,7 +1474,6 @@
 
   ExprResult ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
   unsigned &NumLineToksConsumed,
-  void *Info,
   bool IsUnevaluated);
 
 private:
Index: cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
@@ -0,0 +1,35 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - | FileCheck %s
+
+int gVar;
+void t1() {
+  // CHECK: add eax, dword ptr gVar[eax]
+  __asm add eax, dword ptr gVar[eax]
+  // CHECK: add dword ptr gVar[eax], eax
+  __asm add dword ptr [eax+gVar], eax
+  // CHECK: add ebx, dword ptr gVar[ebx + $$270]
+  __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
+  // CHECK: add dword ptr gVar[ebx + $$828], ebx
+  __asm add dword ptr [ebx + gVar + 828], ebx
+  // CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
+  __asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
+  // CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
+  __asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
+  // CHECK: add gVar[ecx + ebx + $$7], eax
+  __asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
+}
+
+void t2() {
+  int lVar;
+  // CHECK: mov eax, dword ptr ${{[0-9]}}[eax]
+  __asm mov eax, dword ptr lVar[eax]
+  // CHECK: mov dword ptr ${{[0-9]}}[eax], eax
+  __asm mov dword ptr [eax+lVar], eax
+  // CHECK: mov ebx, dword ptr ${{[0-9]}}[ebx + $$270]
+  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
+  // CHECK: mov dword ptr ${{[0-9]}}[ebx + $$828], ebx
+  __asm mov dword ptr [ebx + lVar + 828], ebx
+  // CHECK: mov ${{[0-9]}}[ebx + $$47], eax
+  __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
+}
+
Index: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
+++ cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
@@ -0,0 +1,55 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - | FileCheck %s
+
+namespace x {
+  enum { A = 12 };
+  struct y_t {
+enum { A = 17 };
+int r;
+  } y;
+}
+
+// CHECK-LABEL: t1
+void t1() {
+  enum { A = 1 };
+  // CHECK: call void asm
+  // CHECK-SAME: mov eax, $$12
+  __asm mov eax, x::A
+  // CHECK-SAME: mov eax, $$17
+  __asm mov eax, x::y_t::A
+  // CHECK-NEXT: call void asm
+  // CHECK-SAME: mov eax, $$1
+  __asm {mov eax, A}
+}
+
+// CHECK-LABEL: t2
+void t2() {
+  enum { A = 1, B };
+  // CHECK: call void asm
+  // CHECK-SAME: mov eax, $$21
+  __asm mov eax, (A + 9) * 2 + A
+  // CHECK-SAME: mov eax, $$4
+  __asm mov eax, A << 2
+  // CHECK-SAME: mov eax, $$2
+  __asm mov eax, B & 3
+  // CH

[PATCH] D38445: [x86][inlin-asm] allow recognition of MPX regs inside ms inline-asm blob

2017-10-01 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Repository:
  rL LLVM

https://reviews.llvm.org/D38445

Files:
  lib/Basic/Targets/X86.cpp
  test/CodeGen/ms-inline-asm.c


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -60,6 +60,7 @@
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 "dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
+"bnd0",  "bnd1",  "bnd2",  "bnd3",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -661,6 +661,17 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47() {
+  // CHECK-LABEL: define void @t47
+  __asm {
+bndmk bnd0, dword ptr [eax]
+bndmk bnd1, dword ptr [ebx]
+bndmk bnd2, dword ptr [ecx]
+bndmk bnd3, dword ptr [edx]
+  }
+  // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr 
[eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr 
[ecx]\0A\09bndmk bnd3, dword ptr [edx]", 
"~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
   // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -60,6 +60,7 @@
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 "dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
+"bnd0",  "bnd1",  "bnd2",  "bnd3",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -661,6 +661,17 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47() {
+  // CHECK-LABEL: define void @t47
+  __asm {
+bndmk bnd0, dword ptr [eax]
+bndmk bnd1, dword ptr [ebx]
+bndmk bnd2, dword ptr [ecx]
+bndmk bnd3, dword ptr [edx]
+  }
+  // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr [eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr [ecx]\0A\09bndmk bnd3, dword ptr [edx]", "~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
   // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
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[PATCH] D37466: D37461: fixups for existing InlineAsm tests + adding new ones

2017-10-01 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: test/CodeGen/ms-inline-asm.cpp:37-38
-  int lvar = 10;
-  __asm mov eax, offset Foo::ptr
-  __asm mov eax, offset Foo::Bar::ptr
-// CHECK-LABEL: define void @_Z2t2v()

rnk wrote:
> These don't seem tested anywhere now
I've tested them against msvc, and they are seem to be unsupported there as 
well, so I don't see any value in keeping this one around :\


Repository:
  rL LLVM

https://reviews.llvm.org/D37466



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[PATCH] D32638: [x86][inline-asm][clang]Amend size directive deduction mechanism of unsized memory operands

2017-06-26 Thread coby via Phabricator via cfe-commits

coby abandoned this revision.
coby added a comment.

superseded by https://reviews.llvm.org/rL302179


Repository:
  rL LLVM

https://reviews.llvm.org/D32638



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[PATCH] D41557: [x86][icelake][vbmi2]

2017-12-23 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added subscribers: cfe-commits, mgorny.

added intrinsics support for (while of) vbmi2 instructions, matching a similar 
work on the backend


Repository:
  rC Clang

https://reviews.llvm.org/D41557

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vbmi2intrin.h
  lib/Headers/avx512vlvbmi2intrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/avx512vbmi2-builtins.c
  test/CodeGen/avx512vlvbmi2-builtins.c
  test/Driver/x86-target-features.c

Index: lib/Headers/avx512vbmi2intrin.h
===
--- lib/Headers/avx512vbmi2intrin.h
+++ lib/Headers/avx512vbmi2intrin.h
@@ -0,0 +1,391 @@
+/*===- avx512vbmi2intrin.h - VBMI2 intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __AVX512VBMI2INTRIN_H
+#define __AVX512VBMI2INTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2")))
+
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
+  (__v32hi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
+  (__v32hi) _mm512_setzero_hi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
+  (__v64qi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
+  (__v64qi) _mm512_setzero_qi(),
+  __U);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS
+_mm512_mask_compressstoreu_epi16(void *__P, __mmask32 __U, __m512i __D)
+{
+  __builtin_ia32_compressstorehi512_mask ((__v32hi *) __P, (__v32hi) __D,
+  __U);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS
+_mm512_mask_compressstoreu_epi8(void *__P, __mmask64 __U, __m512i __D)
+{
+  __builtin_ia32_compressstoreqi512_mask ((__v64qi *) __P, (__v64qi) __D,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
+  (__v32hi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
+  (__v32hi) _mm512_setzero_hi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
+  (__v64qi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_expand_epi8(__mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
+  (__v64qi) _mm512_setzero_qi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expandloadu_epi16(__m512i __S, __mmask32 __U, void const *__P)
+{
+  return (__m512i) __builtin_ia32_expandloadhi512_mask ((c

[PATCH] D41558: [x86][icelake][vbmi2]

2017-12-23 Thread coby via Phabricator via cfe-commits

coby created this revision.
coby added a reviewer: craig.topper.
Herald added a subscriber: mgorny.

added intrinsics support for VNNI instructions, matching a similar work on the 
backend (https://reviews.llvm.org/D40208)


Repository:
  rC Clang

https://reviews.llvm.org/D41558

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vlvnniintrin.h
  lib/Headers/avx512vnniintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/avx512vlvnni-builtins.c
  test/CodeGen/avx512vnni-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -22,6 +22,8 @@
   avx512vldqintrin.h
   avx512vlintrin.h
   avx512vpopcntdqvlintrin.h
+  avx512vnniintrin.h
+  avx512vlvnniintrin.h
   avxintrin.h
   bmi2intrin.h
   bmiintrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -159,6 +159,15 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512VNNI__)
+#include 
+#endif
+
+#if !defined(_MSC_VER) || __has_feature(modules) || \
+(defined(__AVX512VL__) && defined(__AVX512VNNI__))
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512DQ__)
 #include 
 #endif
Index: lib/Headers/avx512vnniintrin.h
===
--- lib/Headers/avx512vnniintrin.h
+++ lib/Headers/avx512vnniintrin.h
@@ -0,0 +1,146 @@
+/*===- avx512vnniintrin.h - VNNI intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __AVX512VNNIINTRIN_H
+#define __AVX512VNNIINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vnni")))
+
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_dpbusd_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusd512_mask ((__v16si) __S,
+  (__v16si) __A,
+  (__v16si) __B,
+  (__mmask16) __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_dpbusd_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusd512_maskz ((__v16si) __S,
+  (__v16si) __A,
+  (__v16si) __B,
+  (__mmask16) __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_dpbusd_epi32(__m512i __S, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusd512_mask ((__v16si) __S,
+  (__v16si) __A,
+  (__v16si) __B,
+  (__mmask16) -1);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_dpbusds_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusds512_mask ((__v16si) __S,
+  (__v16si) __A,
+  (__v16si) __B,
+  (__mmask16) __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_dpbusds_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusds512_maskz ((__v16si) __S,
+  (__v16si) __A,
+  (__v16si) __B,
+  (__mmask16) __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_dpbusds_epi32(__m512i __S, __m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_vpdpbusds512_mask

[PATCH] D41564: [x86][icelake][bitalg]

2017-12-24 Thread coby via Phabricator via cfe-commits

coby created this revision.
coby added a reviewer: craig.topper.
Herald added a subscriber: mgorny.

added intrinsics support for bitalg instructions, matching a similar work on 
the backend (https://reviews.llvm.org/D40222)


Repository:
  rC Clang

https://reviews.llvm.org/D41564

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/CGBuiltin.cpp
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512bitalgintrin.h
  lib/Headers/avx512vlbitalgintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/avx512bitalg-builtins.c
  test/CodeGen/avx512vlbitalg-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -7,6 +7,8 @@
   arm64intr.h
   avx2intrin.h
   avx512bwintrin.h
+  avx512bitalgintrin.h
+  avx512vlbitalgintrin.h
   avx512cdintrin.h
   avx512vpopcntdqintrin.h
   avx512dqintrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -146,6 +146,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512BITALG__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512CD__)
 #include 
 #endif
@@ -164,6 +168,11 @@
 #endif
 
 #if !defined(_MSC_VER) || __has_feature(modules) || \
+(defined(__AVX512VL__) && defined(__AVX512BITALG__))
+#include 
+#endif
+
+#if !defined(_MSC_VER) || __has_feature(modules) || \
 (defined(__AVX512VL__) && defined(__AVX512BW__))
 #include 
 #endif
Index: lib/Headers/avx512bitalgintrin.h
===
--- lib/Headers/avx512bitalgintrin.h
+++ lib/Headers/avx512bitalgintrin.h
@@ -0,0 +1,97 @@
+/*===- avx512bitalgintrin.h - BITALG intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __AVX512BITALGINTRIN_H
+#define __AVX512BITALGINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512bitalg")))
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_popcnt_epi16(__m512i __A)
+{
+  return (__m512i) __builtin_ia32_vpopcntw_512((__v32hi) __A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_popcnt_epi16(__m512i __A, __mmask32 __U, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_selectw_512((__mmask32) __U,
+  (__v32hi) _mm512_popcnt_epi16(__B),
+  (__v32hi) __A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_popcnt_epi16(__mmask32 __U, __m512i __B)
+{
+  return _mm512_mask_popcnt_epi16((__m512i) _mm512_setzero_hi(),
+  __U,
+  __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_popcnt_epi8(__m512i __A)
+{
+  return (__m512i) __builtin_ia32_vpopcntb_512((__v64qi) __A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_popcnt_epi8(__m512i __A, __mmask64 __U, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_selectb_512((__mmask64) __U,
+  (__v64qi) _mm512_popcnt_epi8(__B),
+  (__v64qi) __A);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __B)
+{
+  return _mm512_mask_popcnt_epi8((__m512i) _mm512_setzero_qi(),
+  __U,
+  __B);
+}
+
+static __inline__ __mmask64 __DEFAULT_FN_ATTRS
+_mm512_mask_bitshuffle_epi64_mask(__mmask64 __U, __m

[PATCH] D41573: [x86][icelake][vpclmulqdq]

2017-12-25 Thread coby via Phabricator via cfe-commits

coby created this revision.
coby added a reviewer: craig.topper.
Herald added a subscriber: mgorny.

added intrinsics support for vpclmulqdq instructions, matching a similar work 
on the backend (https://reviews.llvm.org/D40101)


Repository:
  rC Clang

https://reviews.llvm.org/D41573

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  lib/Headers/vpclmulqdqintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/vpclmulqdq-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -84,6 +84,7 @@
   vadefs.h
   varargs.h
   vecintrin.h
+  vpclmulqdqintrin.h
   wmmintrin.h
   __wmmintrin_aes.h
   __wmmintrin_pclmul.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -118,6 +118,10 @@
 }
 #endif /* __AVX2__ */
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VPCLMULQDQ__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__BMI__)
 #include 
 #endif
Index: lib/Headers/vpclmulqdqintrin.h
===
--- lib/Headers/vpclmulqdqintrin.h
+++ lib/Headers/vpclmulqdqintrin.h
@@ -0,0 +1,48 @@
+/*=== vpclmulqdqintrin.h - VPCLMULQDQ intrinsics ---===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __VPCLMULQDQINTRIN_H
+#define __VPCLMULQDQINTRIN_H
+
+#if defined(__VPCLMULQDQ__)
+
+#define _mm256_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m256i)__builtin_ia32_pclmulqdq256((__v4di)(__m256i)(A),  \
+   (__v4di)(__m256i)(B),  \
+   (char)(I)); })
+
+#if defined(__AVX512F__)
+
+#define _mm512_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m512i)__builtin_ia32_pclmulqdq512((__v8di)(__m512i)(A),  \
+   (__v8di)(__m512i)(B),  \
+   (char)(I)); })
+
+#endif // defined(__AVX512__)
+#endif // defined(__VPCLMULQDQ__)
+#endif // __VPCLMULQDQINTRIN_H
+
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -132,6 +132,7 @@
 break;
 
   case CK_Icelake:
+setFeatureEnabledImpl(Features, "vpclmulqdq", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -460,7 +461,7 @@
 LLVM_FALLTHROUGH;
   case AVX:
 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
-Features["xsaveopt"] = false;
+Features["xsaveopt"] = Features["vpclmulqdq"] = false;
 setXOPLevel(Features, FMA4, false);
 LLVM_FALLTHROUGH;
   case AVX2:
@@ -575,6 +576,11 @@
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+  } else if (Name == "vpclmulqdq") {
+if (Enabled) {
+  setSSELevel(Features, AVX, Enabled);
+  Features["pclmul"] = true;
+}
   } else if (Name == "avx") {
 setSSELevel(Features, AVX, Enabled);
   } else if (Name == "avx2") {
@@ -638,6 +644,8 @@
   HasAES = true;
 } else if (Feature == "+pclmul") {
   HasPCLMUL = true;
+} else if (Feature == "+vpclmulqdq") {
+  HasVPCLMULQDQ = true;
 } else if (Feature == "+lzcnt") {
   HasLZCNT = true;
 } else if (Feature == "+rdrnd") {
@@ -937,

[PATCH] D41573: [x86][icelake][vpclmulqdq]

2017-12-25 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128139.
coby added a comment.

removing guards to allow better diags


Repository:
  rC Clang

https://reviews.llvm.org/D41573

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  lib/Headers/vpclmulqdqintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/vpclmulqdq-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -84,6 +84,7 @@
   vadefs.h
   varargs.h
   vecintrin.h
+  vpclmulqdqintrin.h
   wmmintrin.h
   __wmmintrin_aes.h
   __wmmintrin_pclmul.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -118,6 +118,10 @@
 }
 #endif /* __AVX2__ */
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VPCLMULQDQ__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__BMI__)
 #include 
 #endif
Index: lib/Headers/vpclmulqdqintrin.h
===
--- lib/Headers/vpclmulqdqintrin.h
+++ lib/Headers/vpclmulqdqintrin.h
@@ -0,0 +1,42 @@
+/*=== vpclmulqdqintrin.h - VPCLMULQDQ intrinsics ---===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __VPCLMULQDQINTRIN_H
+#define __VPCLMULQDQINTRIN_H
+
+#define _mm256_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m256i)__builtin_ia32_pclmulqdq256((__v4di)(__m256i)(A),  \
+   (__v4di)(__m256i)(B),  \
+   (char)(I)); })
+
+#define _mm512_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m512i)__builtin_ia32_pclmulqdq512((__v8di)(__m512i)(A),  \
+   (__v8di)(__m512i)(B),  \
+   (char)(I)); })
+
+#endif // __VPCLMULQDQINTRIN_H
+
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -132,6 +132,7 @@
 break;
 
   case CK_Icelake:
+setFeatureEnabledImpl(Features, "vpclmulqdq", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -460,7 +461,7 @@
 LLVM_FALLTHROUGH;
   case AVX:
 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
-Features["xsaveopt"] = false;
+Features["xsaveopt"] = Features["vpclmulqdq"] = false;
 setXOPLevel(Features, FMA4, false);
 LLVM_FALLTHROUGH;
   case AVX2:
@@ -575,6 +576,11 @@
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+  } else if (Name == "vpclmulqdq") {
+if (Enabled) {
+  setSSELevel(Features, AVX, Enabled);
+  Features["pclmul"] = true;
+}
   } else if (Name == "avx") {
 setSSELevel(Features, AVX, Enabled);
   } else if (Name == "avx2") {
@@ -638,6 +644,8 @@
   HasAES = true;
 } else if (Feature == "+pclmul") {
   HasPCLMUL = true;
+} else if (Feature == "+vpclmulqdq") {
+  HasVPCLMULQDQ = true;
 } else if (Feature == "+lzcnt") {
   HasLZCNT = true;
 } else if (Feature == "+rdrnd") {
@@ -937,6 +945,9 @@
   if (HasPCLMUL)
 Builder.defineMacro("__PCLMUL__");
 
+  if (HasVPCLMULQDQ)
+Builder.defineMacro("__VPCLMULQDQ__");
+
   if (HasLZCNT)
 Builder.defineMacro("__LZCNT__");
 
@@ -1185,6 +1196,7 @@
   .Case("sse4.2", true)

[PATCH] D41582: [x86][icelake][gfni]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby created this revision.
coby added a reviewer: craig.topper.
Herald added a subscriber: mgorny.

added intrinsics support for gfni instructions, matching a similar work on the 
backend (https://reviews.llvm.org/D40373)


Repository:
  rC Clang

https://reviews.llvm.org/D41582

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/gfniintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/gfni-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -42,6 +42,7 @@
   fma4intrin.h
   fmaintrin.h
   fxsrintrin.h
+  gfniintrin.h
   htmintrin.h
   htmxlintrin.h
   ia32intrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -208,6 +208,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__GFNI__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
 _rdrand16_step(unsigned short *__p)
Index: lib/Headers/gfniintrin.h
===
--- lib/Headers/gfniintrin.h
+++ lib/Headers/gfniintrin.h
@@ -0,0 +1,197 @@
+/*===- gfniintrin.h - GFNI intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __GFNIINTRIN_H
+#define __GFNIINTRIN_H
+
+
+#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({   \
+  (__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A),  \
+  (__v16qi)(__m128i)(B),  \
+  (char)(I)); })
+
+#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({\
+  (__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
+(__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I),  \
+(__v16qi)(__m128i)(S)); })
+
+
+#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({  \
+  (__m128i)_mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(),   \
+U, A, B, I); })
+
+
+#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({\
+  (__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A),  \
+  (__v32qi)(__m256i)(B),  \
+  (char)(I)); })
+
+#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
+   (__m256i)__builtin_ia32_selectb_256((__mmask32)(U),\
+(__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I),   \
+(__v32qi)(__m256i)(S)); })
+
+#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({   \
+  (__m256i)_mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \
+U, A, B, I); })
+
+
+#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({\
+  (__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A),  \
+  (__v64qi)(__m512i)(B),  \
+  (char)(I)); })

[PATCH] D41582: [x86][icelake][gfni]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128168.
coby added a comment.

add forgotten undef[s]


Repository:
  rC Clang

https://reviews.llvm.org/D41582

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/gfniintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/gfni-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -42,6 +42,7 @@
   fma4intrin.h
   fmaintrin.h
   fxsrintrin.h
+  gfniintrin.h
   htmintrin.h
   htmxlintrin.h
   ia32intrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -208,6 +208,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__GFNI__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
 _rdrand16_step(unsigned short *__p)
Index: lib/Headers/gfniintrin.h
===
--- lib/Headers/gfniintrin.h
+++ lib/Headers/gfniintrin.h
@@ -0,0 +1,202 @@
+/*===- gfniintrin.h - GFNI intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __GFNIINTRIN_H
+#define __GFNIINTRIN_H
+
+
+#define _mm_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({   \
+  (__m128i)__builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A),  \
+  (__v16qi)(__m128i)(B),  \
+  (char)(I)); })
+
+#define _mm_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({\
+  (__m128i)__builtin_ia32_selectb_128((__mmask16)(U), \
+(__v16qi)_mm_gf2p8affineinv_epi64_epi8(A, B, I),  \
+(__v16qi)(__m128i)(S)); })
+
+
+#define _mm_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({  \
+  (__m128i)_mm_mask_gf2p8affineinv_epi64_epi8((__m128i)_mm_setzero_si128(),   \
+U, A, B, I); })
+
+
+#define _mm256_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({\
+  (__m256i)__builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A),  \
+  (__v32qi)(__m256i)(B),  \
+  (char)(I)); })
+
+#define _mm256_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
+   (__m256i)__builtin_ia32_selectb_256((__mmask32)(U),\
+(__v32qi)_mm256_gf2p8affineinv_epi64_epi8(A, B, I),   \
+(__v32qi)(__m256i)(S)); })
+
+#define _mm256_maskz_gf2p8affineinv_epi64_epi8(U, A, B, I) __extension__ ({   \
+  (__m256i)_mm256_mask_gf2p8affineinv_epi64_epi8((__m256i)_mm256_setzero_si256(), \
+U, A, B, I); })
+
+
+#define _mm512_gf2p8affineinv_epi64_epi8(A, B, I) __extension__ ({\
+  (__m512i)__builtin_ia32_vgf2p8affineinvqb_v64qi((__v64qi)(__m512i)(A),  \
+  (__v64qi)(__m512i)(B),  \
+  (char)(I)); })
+
+#define _mm512_mask_gf2p8affineinv_epi64_epi8(S, U, A, B, I) __extension__ ({ \
+   (__m512i)__builtin_ia32_selectb_512((__mmas

[PATCH] D41583: [x86][icelake][vaes]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby created this revision.
coby added a reviewer: craig.topper.
Herald added a subscriber: mgorny.

added intrinsics support for vaes instructions, matching a similar work on the 
backend (https://reviews.llvm.org/D40078)


Repository:
  rC Clang

https://reviews.llvm.org/D41583

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  lib/Headers/vaesintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/vaes-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/vaesintrin.h
===
--- lib/Headers/vaesintrin.h
+++ lib/Headers/vaesintrin.h
@@ -0,0 +1,98 @@
+/*===-- vaesintrin.h - VAES intrinsics -===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __VAESINTRIN_H
+#define __VAESINTRIN_H
+
+/* Default attributes for YMM forms. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("vaes")))
+
+/* Default attributes for ZMM forms. */
+#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512f,vaes")))
+
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesenc_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesenc256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesenc_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesenc512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesdec_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesdec256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesdec_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesdec512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesenclast_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesenclast256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesenclast_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesenclast512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesdeclast_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesdeclast256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesdeclast_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesdeclast512((__v8di) __A,
+  (__v8di) __B);
+}
+
+
+#undef __DEFAULT_FN_ATTRS
+#undef __DEFAULT_FN_ATTRS_F
+
+#endif
Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -82,6 +82,7 @@
   tmmintrin.h
   unwind.h
   vadefs.h
+  vaesintrin.h
   varargs.h
   vecintrin.h
   wmmintrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -208,6 +208,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VAES__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
 _rdrand16_step(unsigned short *__p)
Index: lib/Basic/Targets/X86.cpp
==

[PATCH] D41557: [x86][icelake][vbmi2]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby marked 2 inline comments as done.
coby added inline comments.



Comment at: lib/Basic/Targets/X86.cpp:589
+// Enable BWI instruction if VBMI/VBMI2 is being enabled.
+if (Name.startswith("avx512vbmi") && Enabled)
   Features["avx512bw"] = true;

craig.topper wrote:
> Do two equality checks ORed together. I think bad target attributes on 
> functions only issue a warning and are discarded in codegen. So strings like 
> avx512vbmifoo can get here and we should ignore them.
conditions on 582 .. 585 see that only "avx512vbmi" and "avx512vbmi2" will be 
candidates to the added check at 589, so we should be fine


Repository:
  rC Clang

https://reviews.llvm.org/D41557



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[PATCH] D41557: [x86][icelake][vbmi2]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128171.
coby added a comment.

addressed comments


Repository:
  rC Clang

https://reviews.llvm.org/D41557

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -17,6 +17,8 @@
   avx512pfintrin.h
   avx512vbmiintrin.h
   avx512vbmivlintrin.h
+  avx512vbmi2intrin.h
+  avx512vlvbmi2intrin.h
   avx512vlbwintrin.h
   avx512vlcdintrin.h
   avx512vldqintrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -200,6 +200,15 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512VBMI2__)
+#include 
+#endif
+
+#if !defined(_MSC_VER) || __has_feature(modules) || \
+(defined(__AVX512VBMI2__) && defined(__AVX512VL__))
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__AVX512PF__)
 #include 
 #endif
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -133,6 +133,7 @@
 
   case CK_Icelake:
 // TODO: Add icelake features here.
+setFeatureEnabledImpl(Features, "avx512vbmi2", true);
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
 setFeatureEnabledImpl(Features, "avx512ifma", true);
@@ -470,7 +471,8 @@
 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
 Features["avx512vl"] = Features["avx512vbmi"] =
-Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
+Features["avx512ifma"] = Features["avx512vpopcntdq"] =
+Features["avx512vbmi2"] = false;
 break;
   }
 }
@@ -584,15 +586,15 @@
   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
  Name == "avx512vbmi" || Name == "avx512ifma" ||
- Name == "avx512vpopcntdq") {
+ Name == "avx512vpopcntdq" || Name == "avx512vbmi2") {
 if (Enabled)
   setSSELevel(Features, AVX512F, Enabled);
-// Enable BWI instruction if VBMI is being enabled.
-if (Name == "avx512vbmi" && Enabled)
+// Enable BWI instruction if VBMI/VBMI2 is being enabled.
+if (Name.startswith("avx512vbmi") && Enabled)
   Features["avx512bw"] = true;
-// Also disable VBMI if BWI is being disabled.
+// Also disable VBMI/VBMI2 if BWI is being disabled.
 if (Name == "avx512bw" && !Enabled)
-  Features["avx512vbmi"] = false;
+  Features["avx512vbmi"] = Features["avx512vbmi2"] = false;
   } else if (Name == "fma") {
 if (Enabled)
   setSSELevel(Features, AVX, Enabled);
@@ -682,6 +684,8 @@
   HasAVX512VL = true;
 } else if (Feature == "+avx512vbmi") {
   HasAVX512VBMI = true;
+} else if (Feature == "+avx512vbmi2") {
+  HasAVX512VBMI2 = true;
 } else if (Feature == "+avx512ifma") {
   HasAVX512IFMA = true;
 } else if (Feature == "+sha") {
@@ -1012,6 +1016,8 @@
 Builder.defineMacro("__AVX512VL__");
   if (HasAVX512VBMI)
 Builder.defineMacro("__AVX512VBMI__");
+  if (HasAVX512VBMI2)
+Builder.defineMacro("__AVX512VBMI2__");
   if (HasAVX512IFMA)
 Builder.defineMacro("__AVX512IFMA__");
 
@@ -1147,6 +1153,7 @@
   .Case("avx512bw", true)
   .Case("avx512vl", true)
   .Case("avx512vbmi", true)
+  .Case("avx512vbmi2", true)
   .Case("avx512ifma", true)
   .Case("bmi", true)
   .Case("bmi2", true)
@@ -1209,6 +1216,7 @@
   .Case("avx512bw", HasAVX512BW)
   .Case("avx512vl", HasAVX512VL)
   .Case("avx512vbmi", HasAVX512VBMI)
+  .Case("avx512vbmi2", HasAVX512VBMI2)
   .Case("avx512ifma", HasAVX512IFMA)
   .Case("bmi", HasBMI)
   .Case("bmi2", HasBMI2)
Index: lib/Basic/Targets/X86.h
===
--- lib/Basic/Targets/X86.h
+++ lib/Basic/Targets/X86.h
@@ -71,6 +71,7 @@
   bool HasAVX512BW = false;
   bool HasAVX512VL = false;
   bool HasAVX512VBMI = false;
+  bool HasAVX512VBMI2 = false;
   bool HasAVX512IFMA = false;
   bool HasSHA = false;
   bool HasMPX = false;
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.td
+++ include/clang/Driver/Options.td
@@ -2481,6 +2481,8 @@
 def mno_avx512pf : Flag<["-"], "mno-avx512pf">, Group;
 def mavx512vbmi : Fl

[PATCH] D41557: [x86][icelake][vbmi2]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128172.
coby added a comment.

tests


Repository:
  rC Clang

https://reviews.llvm.org/D41557

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/avx512vbmi2intrin.h
  lib/Headers/avx512vlvbmi2intrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/avx512vbmi2-builtins.c
  test/CodeGen/avx512vlvbmi2-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/avx512vbmi2intrin.h
===
--- lib/Headers/avx512vbmi2intrin.h
+++ lib/Headers/avx512vbmi2intrin.h
@@ -0,0 +1,391 @@
+/*===- avx512vbmi2intrin.h - VBMI2 intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __AVX512VBMI2INTRIN_H
+#define __AVX512VBMI2INTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2")))
+
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
+  (__v32hi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
+  (__v32hi) _mm512_setzero_hi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
+  (__v64qi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
+  (__v64qi) _mm512_setzero_qi(),
+  __U);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS
+_mm512_mask_compressstoreu_epi16(void *__P, __mmask32 __U, __m512i __D)
+{
+  __builtin_ia32_compressstorehi512_mask ((__v32hi *) __P, (__v32hi) __D,
+  __U);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS
+_mm512_mask_compressstoreu_epi8(void *__P, __mmask64 __U, __m512i __D)
+{
+  __builtin_ia32_compressstoreqi512_mask ((__v64qi *) __P, (__v64qi) __D,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
+  (__v32hi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
+  (__v32hi) _mm512_setzero_hi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
+  (__v64qi) __S,
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_maskz_expand_epi8(__mmask64 __U, __m512i __D)
+{
+  return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
+  (__v64qi) _mm512_setzero_qi(),
+  __U);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS
+_mm512_mask_expandloadu_epi16(__m512i __S, __mmask32 __U, void const *__P)
+{
+  return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *)__

[PATCH] D41583: [x86][icelake][vaes]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: lib/Basic/Targets/X86.cpp:573
 setMMXLevel(Features, AMD3DNowAthlon, Enabled);
   } else if (Name == "aes") {
 if (Enabled)

craig.topper wrote:
> Shouldn't -aes imply -vaes?
how come? perhaps i'm missing here something?
why would the first imply the latter?
following this road an atom z8XXX should be capable of supporting vaes, for 
example (where it lacks avx, for example, 
https://www.intel.com/content/www/us/en/processors/atom/atom-z8000-datasheet-vol-1.html)
also, in that sense, pclmul is implying vpclmulqdq


Repository:
  rC Clang

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[PATCH] D41573: [x86][icelake][vpclmulqdq]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: lib/Basic/Targets/X86.cpp:577
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);

craig.topper wrote:
> I think we should disable vpclmulqdq when pclmul is being disabled.
agreed


Repository:
  rC Clang

https://reviews.llvm.org/D41573



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[PATCH] D41573: [x86][icelake][vpclmulqdq]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128183.
coby added a comment.

turning off pclmul forbids enabling vpclmulqdq


Repository:
  rC Clang

https://reviews.llvm.org/D41573

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  lib/Headers/vpclmulqdqintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/vpclmulqdq-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -84,6 +84,7 @@
   vadefs.h
   varargs.h
   vecintrin.h
+  vpclmulqdqintrin.h
   wmmintrin.h
   __wmmintrin_aes.h
   __wmmintrin_pclmul.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -118,6 +118,10 @@
 }
 #endif /* __AVX2__ */
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VPCLMULQDQ__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__BMI__)
 #include 
 #endif
Index: lib/Headers/vpclmulqdqintrin.h
===
--- lib/Headers/vpclmulqdqintrin.h
+++ lib/Headers/vpclmulqdqintrin.h
@@ -0,0 +1,42 @@
+/*=== vpclmulqdqintrin.h - VPCLMULQDQ intrinsics ---===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __VPCLMULQDQINTRIN_H
+#define __VPCLMULQDQINTRIN_H
+
+#define _mm256_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m256i)__builtin_ia32_pclmulqdq256((__v4di)(__m256i)(A),  \
+   (__v4di)(__m256i)(B),  \
+   (char)(I)); })
+
+#define _mm512_clmulepi64_epi128(A, B, I) __extension__ ({\
+  (__m512i)__builtin_ia32_pclmulqdq512((__v8di)(__m512i)(A),  \
+   (__v8di)(__m512i)(B),  \
+   (char)(I)); })
+
+#endif // __VPCLMULQDQINTRIN_H
+
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -132,6 +132,7 @@
 break;
 
   case CK_Icelake:
+setFeatureEnabledImpl(Features, "vpclmulqdq", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -460,7 +461,7 @@
 LLVM_FALLTHROUGH;
   case AVX:
 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
-Features["xsaveopt"] = false;
+Features["xsaveopt"] = Features["vpclmulqdq"] = false;
 setXOPLevel(Features, FMA4, false);
 LLVM_FALLTHROUGH;
   case AVX2:
@@ -575,6 +576,13 @@
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+else
+  Features["vpclmulqdq"] = false;
+  } else if (Name == "vpclmulqdq") {
+if (Enabled) {
+  setSSELevel(Features, AVX, Enabled);
+  Features["pclmul"] = true;
+}
   } else if (Name == "avx") {
 setSSELevel(Features, AVX, Enabled);
   } else if (Name == "avx2") {
@@ -638,6 +646,8 @@
   HasAES = true;
 } else if (Feature == "+pclmul") {
   HasPCLMUL = true;
+} else if (Feature == "+vpclmulqdq") {
+  HasVPCLMULQDQ = true;
 } else if (Feature == "+lzcnt") {
   HasLZCNT = true;
 } else if (Feature == "+rdrnd") {
@@ -937,6 +947,9 @@
   if (HasPCLMUL)
 Builder.defineMacro("__PCLMUL__");
 
+  if (HasVPCLMULQDQ)
+Builder.defineMacro("__VPCLMULQDQ__");
+
   if (HasLZCNT)
 Builder.defineMacro("__LZCNT__

[PATCH] D41583: [x86][icelake][vaes]

2017-12-26 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 128185.
coby added a comment.

turning aes off forbids enabling vaes


Repository:
  rC Clang

https://reviews.llvm.org/D41583

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/immintrin.h
  lib/Headers/vaesintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/vaes-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Headers/vaesintrin.h
===
--- lib/Headers/vaesintrin.h
+++ lib/Headers/vaesintrin.h
@@ -0,0 +1,98 @@
+/*===-- vaesintrin.h - VAES intrinsics -===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===---===
+ */
+#ifndef __IMMINTRIN_H
+#error "Never use  directly; include  instead."
+#endif
+
+#ifndef __VAESINTRIN_H
+#define __VAESINTRIN_H
+
+/* Default attributes for YMM forms. */
+#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("vaes")))
+
+/* Default attributes for ZMM forms. */
+#define __DEFAULT_FN_ATTRS_F __attribute__((__always_inline__, __nodebug__, __target__("avx512f,vaes")))
+
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesenc_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesenc256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesenc_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesenc512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesdec_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesdec256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesdec_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesdec512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesenclast_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesenclast256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesenclast_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesenclast512((__v8di) __A,
+  (__v8di) __B);
+}
+
+static __inline__ __m256i __DEFAULT_FN_ATTRS
+ _mm256_aesdeclast_epi128(__m256i __A, __m256i __B)
+{
+  return (__m256i) __builtin_ia32_aesdeclast256((__v4di) __A,
+  (__v4di) __B);
+}
+
+static __inline__ __m512i __DEFAULT_FN_ATTRS_F
+ _mm512_aesdeclast_epi128(__m512i __A, __m512i __B)
+{
+  return (__m512i) __builtin_ia32_aesdeclast512((__v8di) __A,
+  (__v8di) __B);
+}
+
+
+#undef __DEFAULT_FN_ATTRS
+#undef __DEFAULT_FN_ATTRS_F
+
+#endif
Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -82,6 +82,7 @@
   tmmintrin.h
   unwind.h
   vadefs.h
+  vaesintrin.h
   varargs.h
   vecintrin.h
   wmmintrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -208,6 +208,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__VAES__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
 _rdrand16_step(unsigned short *__p)
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X

[PATCH] D41582: [x86][icelake][gfni]

2017-12-27 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rC321477: [x86][icelake][gfni] (authored by coby, committed by 
).

Changed prior to commit:
  https://reviews.llvm.org/D41582?vs=128168&id=128207#toc

Repository:
  rC Clang

https://reviews.llvm.org/D41582

Files:
  include/clang/Basic/BuiltinsX86.def
  include/clang/Driver/Options.td
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/Headers/CMakeLists.txt
  lib/Headers/gfniintrin.h
  lib/Headers/immintrin.h
  test/CodeGen/attr-target-x86.c
  test/CodeGen/gfni-builtins.c
  test/Driver/x86-target-features.c
  test/Preprocessor/predefined-arch-macros.c
  test/Preprocessor/x86_target_features.c

Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -133,6 +133,7 @@
 
   case CK_Icelake:
 setFeatureEnabledImpl(Features, "vaes", true);
+setFeatureEnabledImpl(Features, "gfni", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -444,7 +445,7 @@
 LLVM_FALLTHROUGH;
   case SSE2:
 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
-false;
+Features["gfni"] = false;
 LLVM_FALLTHROUGH;
   case SSE3:
 Features["sse3"] = false;
@@ -583,6 +584,9 @@
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+  } else if (Name == "gfni") {
+ if (Enabled)
+  setSSELevel(Features, SSE2, Enabled);
   } else if (Name == "avx") {
 setSSELevel(Features, AVX, Enabled);
   } else if (Name == "avx2") {
@@ -676,6 +680,8 @@
   HasFMA = true;
 } else if (Feature == "+f16c") {
   HasF16C = true;
+} else if (Feature == "+gfni") {
+  HasGFNI = true;
 } else if (Feature == "+avx512cd") {
   HasAVX512CD = true;
 } else if (Feature == "+avx512vpopcntdq") {
@@ -1009,6 +1015,9 @@
   if (HasF16C)
 Builder.defineMacro("__F16C__");
 
+  if (HasGFNI)
+Builder.defineMacro("__GFNI__");
+
   if (HasAVX512CD)
 Builder.defineMacro("__AVX512CD__");
   if (HasAVX512VPOPCNTDQ)
@@ -1172,6 +1181,7 @@
   .Case("fma4", true)
   .Case("fsgsbase", true)
   .Case("fxsr", true)
+  .Case("gfni", true)
   .Case("lwp", true)
   .Case("lzcnt", true)
   .Case("mmx", true)
@@ -1235,6 +1245,7 @@
   .Case("fma4", XOPLevel >= FMA4)
   .Case("fsgsbase", HasFSGSBASE)
   .Case("fxsr", HasFXSR)
+  .Case("gfni", HasGFNI)
   .Case("ibt", HasIBT)
   .Case("lwp", HasLWP)
   .Case("lzcnt", HasLZCNT)
Index: lib/Basic/Targets/X86.h
===
--- lib/Basic/Targets/X86.h
+++ lib/Basic/Targets/X86.h
@@ -50,6 +50,7 @@
   bool HasAES = false;
   bool HasVAES = false;
   bool HasPCLMUL = false;
+  bool HasGFNI = false;
   bool HasLZCNT = false;
   bool HasRDRND = false;
   bool HasFSGSBASE = false;
Index: lib/Headers/CMakeLists.txt
===
--- lib/Headers/CMakeLists.txt
+++ lib/Headers/CMakeLists.txt
@@ -42,6 +42,7 @@
   fma4intrin.h
   fmaintrin.h
   fxsrintrin.h
+  gfniintrin.h
   htmintrin.h
   htmxlintrin.h
   ia32intrin.h
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -212,6 +212,10 @@
 #include 
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__GFNI__)
+#include 
+#endif
+
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__RDRND__)
 static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
 _rdrand16_step(unsigned short *__p)
Index: lib/Headers/gfniintrin.h
===
--- lib/Headers/gfniintrin.h
+++ lib/Headers/gfniintrin.h
@@ -0,0 +1,202 @@
+/*===- gfniintrin.h - GFNI intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT

[PATCH] D41583: [x86][icelake][vaes]

2017-12-27 Thread coby via Phabricator via cfe-commits

coby closed this revision.
coby added a comment.

closed by commit https://reviews.llvm.org/rC321474 
(https://reviews.llvm.org/rL321474)


Repository:
  rC Clang

https://reviews.llvm.org/D41583



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[PATCH] D41573: [x86][icelake][vpclmulqdq]

2017-12-27 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321480: [x86][icelake][vpclmulqdq] (authored by coby, 
committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41573?vs=128183&id=128210#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41573

Files:
  cfe/trunk/include/clang/Basic/BuiltinsX86.def
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/lib/Basic/Targets/X86.h
  cfe/trunk/lib/Headers/CMakeLists.txt
  cfe/trunk/lib/Headers/immintrin.h
  cfe/trunk/lib/Headers/vpclmulqdqintrin.h
  cfe/trunk/test/CodeGen/attr-target-x86.c
  cfe/trunk/test/CodeGen/vpclmulqdq-builtins.c
  cfe/trunk/test/Driver/x86-target-features.c
  cfe/trunk/test/Preprocessor/predefined-arch-macros.c
  cfe/trunk/test/Preprocessor/x86_target_features.c

Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -2547,6 +2547,8 @@
 def mno_tbm : Flag<["-"], "mno-tbm">, Group;
 def mvaes : Flag<["-"], "mvaes">, Group;
 def mno_vaes : Flag<["-"], "mno-vaes">, Group;
+def mvpclmulqdq : Flag<["-"], "mvpclmulqdq">, Group;
+def mno_vpclmulqdq : Flag<["-"], "mno-vpclmulqdq">, Group;
 def mxop : Flag<["-"], "mxop">, Group;
 def mno_xop : Flag<["-"], "mno-xop">, Group;
 def mxsave : Flag<["-"], "mxsave">, Group;
Index: cfe/trunk/include/clang/Basic/BuiltinsX86.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def
@@ -453,6 +453,10 @@
 // CLMUL
 TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
 
+// VPCLMULQDQ
+TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4LLiV4LLiV4LLiIc", "", "vpclmulqdq")
+TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8LLiV8LLiV8LLiIc", "", "avx512f,vpclmulqdq")
+
 // AVX
 TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "", "avx")
 TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "", "avx")
Index: cfe/trunk/test/Driver/x86-target-features.c
===
--- cfe/trunk/test/Driver/x86-target-features.c
+++ cfe/trunk/test/Driver/x86-target-features.c
@@ -102,6 +102,17 @@
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mgfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=GFNI %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-gfni %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-GFNI %s
+<<<
 // GFNI: "-target-feature" "+gfni"
 // NO-GFNI: "-target-feature" "-gfni
 
+===
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-clzero %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-CLZERO %s
+// CLZERO: "-target-feature" "+clzero"
+// NO-CLZERO: "-target-feature" "-clzero"
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mvpclmulqdq %s -### -o %t.o 2>&1 | FileCheck -check-prefix=VPCLMULQDQ %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vpclmulqdq %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VPCLMULQDQ %s
+// VPCLMULQDQ: "-target-feature" "+vpclmulqdq"
+// NO-VPCLMULQDQ: "-target-feature" "-vpclmulqdq"
+>>>
Index: cfe/trunk/test/CodeGen/attr-target-x86.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86.c
+++ cfe/trunk/test/CodeGen/attr-target-x86.c
@@ -38,9 +38,9 @@
 // CHECK: lake{{.*}} #7
 // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
 // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-xop,-xsave,-xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
 // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-xop,-xsave,-xsaveopt"
+// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1

[PATCH] D41564: [x86][icelake][bitalg]

2017-12-27 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321483: [x86][icelake][bitalg] (authored by coby, committed 
by ).

Changed prior to commit:
  https://reviews.llvm.org/D41564?vs=128109&id=128213#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41564

Files:
  cfe/trunk/include/clang/Basic/BuiltinsX86.def
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/lib/Basic/Targets/X86.h
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/lib/Headers/CMakeLists.txt
  cfe/trunk/lib/Headers/avx512bitalgintrin.h
  cfe/trunk/lib/Headers/avx512vlbitalgintrin.h
  cfe/trunk/lib/Headers/immintrin.h
  cfe/trunk/test/CodeGen/attr-target-x86.c
  cfe/trunk/test/CodeGen/avx512bitalg-builtins.c
  cfe/trunk/test/CodeGen/avx512vlbitalg-builtins.c
  cfe/trunk/test/Driver/x86-target-features.c
  cfe/trunk/test/Preprocessor/predefined-arch-macros.c
  cfe/trunk/test/Preprocessor/x86_target_features.c

Index: cfe/trunk/lib/Basic/Targets/X86.h
===
--- cfe/trunk/lib/Basic/Targets/X86.h
+++ cfe/trunk/lib/Basic/Targets/X86.h
@@ -71,6 +71,7 @@
   bool HasAVX512ER = false;
   bool HasAVX512PF = false;
   bool HasAVX512DQ = false;
+  bool HasAVX512BITALG = false;
   bool HasAVX512BW = false;
   bool HasAVX512VL = false;
   bool HasAVX512VBMI = false;
Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -135,6 +135,7 @@
 setFeatureEnabledImpl(Features, "vaes", true);
 setFeatureEnabledImpl(Features, "gfni", true);
 setFeatureEnabledImpl(Features, "vpclmulqdq", true);
+setFeatureEnabledImpl(Features, "avx512bitalg", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -473,7 +474,8 @@
 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
 Features["avx512vl"] = Features["avx512vbmi"] =
-Features["avx512ifma"] = Features["avx512vpopcntdq"] = false;
+Features["avx512ifma"] = Features["avx512vpopcntdq"] =
+Features["avx512bitalg"] = false;
 break;
   }
 }
@@ -604,15 +606,15 @@
   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" ||
  Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" ||
  Name == "avx512vbmi" || Name == "avx512ifma" ||
- Name == "avx512vpopcntdq") {
+ Name == "avx512vpopcntdq" || Name == "avx512bitalg") {
 if (Enabled)
   setSSELevel(Features, AVX512F, Enabled);
-// Enable BWI instruction if VBMI is being enabled.
-if (Name == "avx512vbmi" && Enabled)
+// Enable BWI instruction if VBMI / BITALG is being enabled.
+if ((Name == "avx512vbmi" || Name == "avx512bitalg") && Enabled)
   Features["avx512bw"] = true;
-// Also disable VBMI if BWI is being disabled.
+// Also disable VBMI / BITALG if BWI is being disabled.
 if (Name == "avx512bw" && !Enabled)
-  Features["avx512vbmi"] = false;
+  Features["avx512vbmi"] = Features["avx512bitalg"] = false;
   } else if (Name == "fma") {
 if (Enabled)
   setSSELevel(Features, AVX, Enabled);
@@ -702,6 +704,8 @@
   HasAVX512PF = true;
 } else if (Feature == "+avx512dq") {
   HasAVX512DQ = true;
+} else if (Feature == "+avx512bitalg") {
+  HasAVX512BITALG = true;
 } else if (Feature == "+avx512bw") {
   HasAVX512BW = true;
 } else if (Feature == "+avx512vl") {
@@ -1041,6 +1045,8 @@
 Builder.defineMacro("__AVX512PF__");
   if (HasAVX512DQ)
 Builder.defineMacro("__AVX512DQ__");
+  if (HasAVX512BITALG)
+Builder.defineMacro("__AVX512BITALG__");
   if (HasAVX512BW)
 Builder.defineMacro("__AVX512BW__");
   if (HasAVX512VL)
@@ -1179,6 +1185,7 @@
   .Case("avx512er", true)
   .Case("avx512pf", true)
   .Case("avx512dq", true)
+  .Case("avx512bitalg", true)
   .Case("avx512bw", true)
   .Case("avx512vl", true)
   .Case("avx512vbmi", true)
@@ -1244,6 +1251,7 @@
   .Case("avx512er", HasAVX512ER)
   .Case("avx512pf", HasAVX512PF)
   .Case("avx512dq", HasAVX512DQ)
+  .Case("avx512bitalg", HasAVX512BITALG)
   .Case("avx512bw", HasAVX512BW)
   .Case("avx512vl", HasAVX512VL)
   .Case("avx512vbmi", HasAVX512VBMI)
Index: cfe/trunk/lib/Headers/avx512bitalgintrin.h
===
--- cfe/trunk/lib/Headers/avx512bitalgintrin.h
+++ cfe/trunk/lib/Headers/avx512bitalgintrin.h
@@ -0,0 +1,97 @@
+/*===- avx512bitalgintrin.h - BITALG intrinsics --===
+ *
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the

[PATCH] D41558: [x86][icelake][vnni]

2017-12-27 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321484: [x86][icelake][vnni] (authored by coby, committed by 
).

Changed prior to commit:
  https://reviews.llvm.org/D41558?vs=128099&id=128216#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41558

Files:
  cfe/trunk/include/clang/Basic/BuiltinsX86.def
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/lib/Basic/Targets/X86.h
  cfe/trunk/lib/Headers/CMakeLists.txt
  cfe/trunk/lib/Headers/avx512vlvnniintrin.h
  cfe/trunk/lib/Headers/avx512vnniintrin.h
  cfe/trunk/lib/Headers/immintrin.h
  cfe/trunk/test/CodeGen/attr-target-x86.c
  cfe/trunk/test/CodeGen/avx512vlvnni-builtins.c
  cfe/trunk/test/CodeGen/avx512vnni-builtins.c
  cfe/trunk/test/Driver/x86-target-features.c
  cfe/trunk/test/Preprocessor/predefined-arch-macros.c

Index: cfe/trunk/include/clang/Basic/BuiltinsX86.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def
@@ -979,6 +979,31 @@
 TARGET_BUILTIN(__builtin_ia32_vpermt2varps512_mask, "V16fV16iV16fV16fUs", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "", "avx512f")
 
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd128_mask, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd256_mask, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd512_mask, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds128_mask, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds256_mask, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds512_mask, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd128_mask, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd256_mask, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd512_mask, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds128_mask, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds256_mask, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds512_mask, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd128_maskz, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd256_maskz, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd512_maskz, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds128_maskz, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds256_maskz, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds512_maskz, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd128_maskz, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd256_maskz, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd512_maskz, "V16iV16iV16iV16iUs", "", "avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds128_maskz, "V4iV4iV4iV4iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds256_maskz, "V8iV8iV8iV8iUc", "", "avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds512_maskz, "V16iV16iV16iV16iUs", "", "avx512vnni")
+
 TARGET_BUILTIN(__builtin_ia32_gather3div2df, "V2dV2ddC*V2LLiUcIi","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_gather3div2di, "V2LLiV2LLiLLiC*V2LLiUcIi","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_gather3div4df, "V4dV4ddC*V4LLiUcIi","","avx512vl")
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -2485,6 +2485,8 @@
 def mno_avx512vbmi : Flag<["-"], "mno-avx512vbmi">, Group;
 def mavx512vl : Flag<["-"], "mavx512vl">, Group;
 def mno_avx512vl : Flag<["-"], "mno-avx512vl">, Group;
+def mavx512vnni : Flag<["-"], "mavx512vnni">, Group;
+def mno_avx512vnni : Flag<["-"], "mno-avx512vnni">, Group;
 def mavx512vpopcntdq : Flag<["-"], "mavx512vpopcntdq">, Group;
 def mno_avx512vpopcntdq : Flag<["-"], "mno-avx512vpopcntdq">, Group;
 def madx : Flag<["-"], "madx">, Group;
Index: cfe/trunk/test/CodeGen/avx512vlvnni-builtins.c
===
--- cfe/trunk/test/CodeGen/avx512vlvnni-builtins.c
+++ cfe/trunk/test/CodeGen/avx512vlvnni-builtins.c
@@ -0,0 +1,148 @@
+//  RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512vnni -target-feature +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include 
+
+__m256i test_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B) {
+  //

[PATCH] D41557: [x86][icelake][vbmi2]

2017-12-27 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321487: [x86][icelake][vbmi2] (authored by coby, committed 
by ).

Changed prior to commit:
  https://reviews.llvm.org/D41557?vs=128172&id=128221#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41557

Files:
  cfe/trunk/include/clang/Basic/BuiltinsX86.def
  cfe/trunk/include/clang/Driver/Options.td
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/lib/Basic/Targets/X86.h
  cfe/trunk/lib/Headers/CMakeLists.txt
  cfe/trunk/lib/Headers/avx512vbmi2intrin.h
  cfe/trunk/lib/Headers/avx512vlvbmi2intrin.h
  cfe/trunk/lib/Headers/immintrin.h
  cfe/trunk/test/CodeGen/attr-target-x86.c
  cfe/trunk/test/CodeGen/avx512vbmi2-builtins.c
  cfe/trunk/test/CodeGen/avx512vlvbmi2-builtins.c
  cfe/trunk/test/Driver/x86-target-features.c
  cfe/trunk/test/Preprocessor/predefined-arch-macros.c
  cfe/trunk/test/Preprocessor/x86_target_features.c

Index: cfe/trunk/test/Preprocessor/predefined-arch-macros.c
===
--- cfe/trunk/test/Preprocessor/predefined-arch-macros.c
+++ cfe/trunk/test/Preprocessor/predefined-arch-macros.c
@@ -1056,6 +1056,7 @@
 // CHECK_ICL_M32: #define __AVX512DQ__ 1
 // CHECK_ICL_M32: #define __AVX512F__ 1
 // CHECK_ICL_M32: #define __AVX512IFMA__ 1
+// CHECK_ICL_M32: #define __AVX512VBMI2__ 1
 // CHECK_ICL_M32: #define __AVX512VBMI__ 1
 // CHECK_ICL_M32: #define __AVX512VL__ 1
 // CHECK_ICL_M32: #define __AVX512VNNI__ 1
@@ -1106,6 +1107,7 @@
 // CHECK_ICL_M64: #define __AVX512DQ__ 1
 // CHECK_ICL_M64: #define __AVX512F__ 1
 // CHECK_ICL_M64: #define __AVX512IFMA__ 1
+// CHECK_ICL_M64: #define __AVX512VBMI2__ 1
 // CHECK_ICL_M64: #define __AVX512VBMI__ 1
 // CHECK_ICL_M64: #define __AVX512VL__ 1
 // CHECK_ICL_M64: #define __AVX512VNNI__ 1
Index: cfe/trunk/test/Preprocessor/x86_target_features.c
===
--- cfe/trunk/test/Preprocessor/x86_target_features.c
+++ cfe/trunk/test/Preprocessor/x86_target_features.c
@@ -231,6 +231,27 @@
 // AVX512VBMINOAVX512BW-NOT: #define __AVX512BW__ 1
 // AVX512VBMINOAVX512BW-NOT: #define __AVX512VBMI__ 1
 
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI2 %s
+
+// AVX512VBMI2: #define __AVX2__ 1
+// AVX512VBMI2: #define __AVX512BW__ 1
+// AVX512VBMI2: #define __AVX512F__ 1
+// AVX512VBMI2: #define __AVX512VBMI2__ 1
+// AVX512VBMI2: #define __AVX__ 1
+// AVX512VBMI2: #define __SSE2_MATH__ 1
+// AVX512VBMI2: #define __SSE2__ 1
+// AVX512VBMI2: #define __SSE3__ 1
+// AVX512VBMI2: #define __SSE4_1__ 1
+// AVX512VBMI2: #define __SSE4_2__ 1
+// AVX512VBMI2: #define __SSE_MATH__ 1
+// AVX512VBMI2: #define __SSE__ 1
+// AVX512VBMI2: #define __SSSE3__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi2 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI2NOAVX512BW %s
+
+// AVX512VBMI2NOAVX512BW-NOT: #define __AVX512BW__ 1
+// AVX512VBMI2NOAVX512BW-NOT: #define __AVX512VBMI2__ 1
+
 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALGNOAVX512BW %s
 
 // AVX512BITALGNOAVX512BW-NOT: #define __AVX512BITALG__ 1
Index: cfe/trunk/test/CodeGen/attr-target-x86.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86.c
+++ cfe/trunk/test/CodeGen/attr-target-x86.c
@@ -38,9 +38,9 @@
 // CHECK: lake{{.*}} #7
 // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+x87"
 // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+aes,+avx,+cx16,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vnni,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-aes,-avx,-avx2,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vpopcntdq,-f16c,-fma,-fma4,-gfni,-pclmul,-sha,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
 // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+x87,-avx,-avx2,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vl,-avx512vnni,-avx512vpopcntdq,-f16c,-fma,-fma4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop,-xsave,-xsaveopt"
+// CHECK: #4 = {{.*}}"target-

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-01 Thread coby via Phabricator via cfe-commits

coby created this revision.

Allow the proper recognition of Enum values and global variables inside ms 
inline-asm memory / immediate expressions, as they require some additional 
overhead and treated incorrect if doesn't early recognized.
supersedes https://reviews.llvm.org/D33277, https://reviews.llvm.org/D35774


Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  include/clang/Parse/Parser.h
  include/clang/Sema/Sema.h
  lib/Parse/ParseStmtAsm.cpp
  lib/Sema/SemaStmtAsm.cpp

Index: lib/Parse/ParseStmtAsm.cpp
===
--- lib/Parse/ParseStmtAsm.cpp
+++ lib/Parse/ParseStmtAsm.cpp
@@ -54,17 +54,17 @@
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
 findTokensForString(LineBuf, LineToks, FirstOrigToken);
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -183,11 +184,7 @@
 ///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
 unsigned &NumLineToksConsumed,
-void *CastInfo,
 bool IsUnevaluatedContext) {
-  llvm::InlineAsmIdentifierInfo &Info =
-  *(llvm::InlineAsmIdentifierInfo *)CastInfo;
-
   // Push a fake token on the end so that we don't overrun the token
   // stream.  We use ';' because it expression-parsing should never
   // overrun it.
@@ -227,7 +224,7 @@
  /*AllowDeductionGuide=*/false,
  /*ObjectType=*/nullptr, TemplateKWLoc, Id);
 // Perform the lookup.
-Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id, Info,
+Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id,
IsUnevaluatedContext);
   }
   // While the next two tokens are 'period' 'identifier', repeatedly parse it as
@@ -241,7 +238,7 @@
 IdentifierInfo *Id = Tok.getIdentifierInfo();
 ConsumeToken(); // Consume the identifier.
 Result = Actions.LookupInlineAsmVarDeclField(Result.get(), Id->getName(),
- Info, Tok.getLocation());
+ Tok.getLocation());
   }
 
   // Figure out how many tokens we are into LineToks.
Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -48,10 +48,10 @@
   if (E != E2 && E2->isLValue()) {
 if (!S.getLangOpts().HeinousExtensions)
   S.Diag(E2->getLocStart(), diag::err_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 else
   S.Diag(E2->getLocStart(), diag::warn_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 // Accept, even if we emitted an error diagnostic.
 return false;
   }
@@ -62,11 +62,13 @@
 
 /// isOperandMentioned - Return true if the specified operand # is mentioned
 /// anywhere in the decomposed asm string.
-static bool isOperandMentioned(unsigned OpNo,
- ArrayRef AsmStrPieces) {
+static bool
+isOperandMentioned(unsigned OpNo,
+   ArrayRef AsmStrPieces) {
   for (unsigned p = 0, e = AsmStrPieces.size(); p != e; ++p) {
 const GCCAsmStmt::AsmStringPiece &Piece = AsmStrPieces[p];
-if (!Piece.isOperand()) continue;
+if (!Piece.isOperand())
+  continue;
 
 // If this is a reference to the input and if the input was the smaller
 // one, then we have to reject this asm.
@@ -605,23 +607,32 @@
   return NS;
 }
 
-static void fillInlineAsmTypeInfo(const ASTContext &Context, QualType T,
-

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-02 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 113659.

Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  include/clang/Parse/Parser.h
  include/clang/Sema/Sema.h
  lib/Parse/ParseStmtAsm.cpp
  lib/Sema/SemaStmtAsm.cpp

Index: lib/Parse/ParseStmtAsm.cpp
===
--- lib/Parse/ParseStmtAsm.cpp
+++ lib/Parse/ParseStmtAsm.cpp
@@ -54,17 +54,17 @@
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
 findTokensForString(LineBuf, LineToks, FirstOrigToken);
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -178,16 +179,9 @@
 }
 
 /// Parse an identifier in an MS-style inline assembly block.
-///
-/// \param CastInfo - a void* so that we don't have to teach Parser.h
-///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
 unsigned &NumLineToksConsumed,
-void *CastInfo,
 bool IsUnevaluatedContext) {
-  llvm::InlineAsmIdentifierInfo &Info =
-  *(llvm::InlineAsmIdentifierInfo *)CastInfo;
-
   // Push a fake token on the end so that we don't overrun the token
   // stream.  We use ';' because it expression-parsing should never
   // overrun it.
@@ -227,7 +221,7 @@
  /*AllowDeductionGuide=*/false,
  /*ObjectType=*/nullptr, TemplateKWLoc, Id);
 // Perform the lookup.
-Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id, Info,
+Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id,
IsUnevaluatedContext);
   }
   // While the next two tokens are 'period' 'identifier', repeatedly parse it as
@@ -241,7 +235,7 @@
 IdentifierInfo *Id = Tok.getIdentifierInfo();
 ConsumeToken(); // Consume the identifier.
 Result = Actions.LookupInlineAsmVarDeclField(Result.get(), Id->getName(),
- Info, Tok.getLocation());
+ Tok.getLocation());
   }
 
   // Figure out how many tokens we are into LineToks.
Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -48,10 +48,10 @@
   if (E != E2 && E2->isLValue()) {
 if (!S.getLangOpts().HeinousExtensions)
   S.Diag(E2->getLocStart(), diag::err_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 else
   S.Diag(E2->getLocStart(), diag::warn_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 // Accept, even if we emitted an error diagnostic.
 return false;
   }
@@ -62,11 +62,13 @@
 
 /// isOperandMentioned - Return true if the specified operand # is mentioned
 /// anywhere in the decomposed asm string.
-static bool isOperandMentioned(unsigned OpNo,
- ArrayRef AsmStrPieces) {
+static bool
+isOperandMentioned(unsigned OpNo,
+   ArrayRef AsmStrPieces) {
   for (unsigned p = 0, e = AsmStrPieces.size(); p != e; ++p) {
 const GCCAsmStmt::AsmStringPiece &Piece = AsmStrPieces[p];
-if (!Piece.isOperand()) continue;
+if (!Piece.isOperand())
+  continue;
 
 // If this is a reference to the input and if the input was the smaller
 // one, then we have to reject this asm.
@@ -605,23 +607,32 @@
   return NS;
 }
 
-static void fillInlineAsmTypeInfo(const ASTContext &Context, QualType T,
-  llvm::InlineAsmIdentifierInfo &Info) {
-  // Compute the type size (and array length if applicable

[PATCH] D35775: [x86][inline-asm]Extend support for memory reference expression

2017-09-03 Thread coby via Phabricator via cfe-commits

coby abandoned this revision.
coby added a comment.

superseded by https://reviews.llvm.org/D37412


Repository:
  rL LLVM

https://reviews.llvm.org/D35775



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[PATCH] D37466: D37461: fixups for existing InlineAsm tests + adding new ones

2017-09-05 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Repository:
  rL LLVM

https://reviews.llvm.org/D37466

Files:
  test/CodeGen/ms-inline-asm-64.c
  test/CodeGen/ms-inline-asm-offset-err.cpp
  test/CodeGen/ms-inline-asm-offset.c
  test/CodeGen/ms-inline-asm.c
  test/CodeGen/ms-inline-asm.cpp

Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -180,25 +180,14 @@
 // CHECK: call void asm sideeffect inteldialect ".if 1\0A\09mov eax, $0\0A\09.else\0A\09mov ebx, j\0A\09.endif", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
-int gvar = 10;
 void t15() {
 // CHECK: t15
   int lvar = 10;
   __asm mov eax, lvar; eax = 10
 // CHECK: mov eax, $0
-  __asm mov eax, offset lvar ; eax = address of lvar
-// CHECK: mov eax, $1
-  __asm mov eax, offset gvar ; eax = address of gvar
-// CHECK: mov eax, $2
-// CHECK: "*m,r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* @{{.*}})
+// CHECK-SAME: "*m,~{eax},~{dirflag},~{fpsr},~{flags}"
 }
 
-void t16() {
-  int var = 10;
-  __asm mov [eax], offset var
-// CHECK: t16
-// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
-}
 
 void t17() {
 // CHECK: t17
Index: test/CodeGen/ms-inline-asm-64.c
===
--- test/CodeGen/ms-inline-asm-64.c
+++ test/CodeGen/ms-inline-asm-64.c
@@ -1,46 +1,28 @@
 // REQUIRES: x86-registered-target
 // RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s
 
-void t1() {
-  int var = 10;
-  __asm mov rax, offset var ; rax = address of myvar
-// CHECK: t1
-// CHECK: call void asm sideeffect inteldialect
-// CHECK-SAME: mov rax, $0
-// CHECK-SAME: "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
-}
-
-void t2() {
-  int var = 10;
-  __asm mov [eax], offset var
-// CHECK: t2
-// CHECK: call void asm sideeffect inteldialect
-// CHECK-SAME: mov [eax], $0
-// CHECK-SAME: "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
-}
-
-struct t3_type { int a, b; };
+struct t1_type { int a, b; };
 
-int t3() {
-  struct t3_type foo;
+int t1() {
+  struct t1_type foo;
   foo.a = 1;
   foo.b = 2;
   __asm {
  lea ebx, foo
  mov eax, [ebx].0
  mov [ebx].4, ecx
   }
   return foo.b;
-// CHECK: t3
+// CHECK: t1
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: lea ebx, $0
 // CHECK-SAME: mov eax, [ebx]
 // CHECK-SAME: mov [ebx + $$4], ecx
-// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
+// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t1_type* %{{.*}})
 }
 
-int t4() {
-  struct t3_type foo;
+int t2() {
+  struct t1_type foo;
   foo.a = 1;
   foo.b = 2;
   __asm {
@@ -51,10 +33,10 @@
  mov [ebx].foo.b, ecx
   }
   return foo.b;
-// CHECK: t4
+// CHECK: t2
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: lea ebx, $0
 // CHECK-SAME: mov eax, [ebx]
 // CHECK-SAME: mov [ebx + $$4], ecx
-// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
+// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t1_type* %{{.*}})
 }
Index: test/CodeGen/ms-inline-asm.cpp
===
--- test/CodeGen/ms-inline-asm.cpp
+++ test/CodeGen/ms-inline-asm.cpp
@@ -31,18 +31,6 @@
   __asm mov eax, dword ptr [Foo :: ptr]
 }
 
-int gvar = 10;
-void t2() {
-  int lvar = 10;
-  __asm mov eax, offset Foo::ptr
-  __asm mov eax, offset Foo::Bar::ptr
-// CHECK-LABEL: define void @_Z2t2v()
-// CHECK: call void asm sideeffect inteldialect
-// CHECK-SAME: mov eax, $0
-// CHECK-SAME: mov eax, $1
-// CHECK-SAME: "r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE)
-}
-
 // CHECK-LABEL: define void @_Z2t3v()
 void t3() {
   __asm mov eax, LENGTH Foo::ptr
Index: test/CodeGen/ms-inline-asm-offset.c
===
--- test/CodeGen/ms-inline-asm-offset.c
+++ test/CodeGen/ms-inline-asm-offset.c
@@ -0,0 +1,29 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s
+
+int gVar;
+void t1() {
+  __asm mov rax, 0xFF + offset gVar - 0xFE * 1
+  // CHECK: t1
+  // CHECK: mov rax, offset gVar + $$1
+}
+
+void t2() {
+  __asm mov edx, offset t2
+  // CHECK: t2
+  // CHECK: mov edx, offset t2
+}
+
+void t3() {
+  __asm _t3: mov eax, offset _t3
+  // CHECK: t3
+  // CHECK: {{.*}}__MSASMLABEL_.${:uid}___t3:
+  // CHECK: mov eax, offset {{.*}}__MSASMLABEL_.${:uid}___t3
+}
+
+void t4() {
+  __asm mov rbx, qword ptr 0x128[rax + offset t4 + rcx * 2]
+  // CHECK: t4
+  // CHECK: mov rbx, qword ptr [rax + rcx * $$2 + offset t4 + $$296]
+}
+
Index: test/CodeGen/ms-inline-asm-offset-err.cpp
==

[PATCH] D37448: Fix cast assertion on MS inline assembly with vector spills (PR34021)

2017-09-05 Thread coby via Phabricator via cfe-commits

coby added a comment.

might be a bit unrelated - but do we've got a hint regarding why is this even 
an issue?
by all means - it doesn't seems right for an empty ms inline-asm statement to 
affect successful compilation, without even mentioning the involvement of the 
encapsulating function's return type.
Another semi-adopted MS legacy issue?


Repository:
  rL LLVM

https://reviews.llvm.org/D37448



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[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-10 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 114520.
coby added a comment.
Herald added a subscriber: eraman.

addressed Simon's comments


Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  include/clang/Parse/Parser.h
  include/clang/Sema/Sema.h
  lib/Parse/ParseStmtAsm.cpp
  lib/Sema/SemaStmtAsm.cpp
  test/CodeGen/ms-inline-asm-enums.cpp
  test/CodeGen/ms-inline-asm-variables.c

Index: lib/Parse/ParseStmtAsm.cpp
===
--- lib/Parse/ParseStmtAsm.cpp
+++ lib/Parse/ParseStmtAsm.cpp
@@ -54,17 +54,17 @@
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
 findTokensForString(LineBuf, LineToks, FirstOrigToken);
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -178,16 +179,9 @@
 }
 
 /// Parse an identifier in an MS-style inline assembly block.
-///
-/// \param CastInfo - a void* so that we don't have to teach Parser.h
-///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
 unsigned &NumLineToksConsumed,
-void *CastInfo,
 bool IsUnevaluatedContext) {
-  llvm::InlineAsmIdentifierInfo &Info =
-  *(llvm::InlineAsmIdentifierInfo *)CastInfo;
-
   // Push a fake token on the end so that we don't overrun the token
   // stream.  We use ';' because it expression-parsing should never
   // overrun it.
@@ -227,7 +221,7 @@
  /*AllowDeductionGuide=*/false,
  /*ObjectType=*/nullptr, TemplateKWLoc, Id);
 // Perform the lookup.
-Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id, Info,
+Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id,
IsUnevaluatedContext);
   }
   // While the next two tokens are 'period' 'identifier', repeatedly parse it as
@@ -241,7 +235,7 @@
 IdentifierInfo *Id = Tok.getIdentifierInfo();
 ConsumeToken(); // Consume the identifier.
 Result = Actions.LookupInlineAsmVarDeclField(Result.get(), Id->getName(),
- Info, Tok.getLocation());
+ Tok.getLocation());
   }
 
   // Figure out how many tokens we are into LineToks.
Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -48,10 +48,10 @@
   if (E != E2 && E2->isLValue()) {
 if (!S.getLangOpts().HeinousExtensions)
   S.Diag(E2->getLocStart(), diag::err_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 else
   S.Diag(E2->getLocStart(), diag::warn_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 // Accept, even if we emitted an error diagnostic.
 return false;
   }
@@ -607,23 +607,32 @@
   return NS;
 }
 
-static void fillInlineAsmTypeInfo(const ASTContext &Context, QualType T,
-  llvm::InlineAsmIdentifierInfo &Info) {
-  // Compute the type size (and array length if applicable?).
-  Info.Type = Info.Size = Context.getTypeSizeInChars(T).getQuantity();
-  if (T->isArrayType()) {
-const ArrayType *ATy = Context.getAsArrayType(T);
-Info.Type = Context.getTypeSizeInChars(ATy->getElementType()).getQuantity();
-Info.Length = Info.Size / Info.Type;
-  }
+void Sema::FillInlineAsmIdentifierInfo(Expr *Res,
+   llvm::InlineAsmIdentifierInfo &Info) {
+  QualType T = Res->getType();
+  Expr::EvalResult Eval;
+  if (T->isFunctionType() || T-

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-11 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 114536.
coby added reviewers: myatsina, m_zuckerman.

Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  include/clang/Parse/Parser.h
  include/clang/Sema/Sema.h
  lib/Parse/ParseStmtAsm.cpp
  lib/Sema/SemaStmtAsm.cpp
  test/CodeGen/ms-inline-asm-enums.cpp
  test/CodeGen/ms-inline-asm-variables.c

Index: lib/Parse/ParseStmtAsm.cpp
===
--- lib/Parse/ParseStmtAsm.cpp
+++ lib/Parse/ParseStmtAsm.cpp
@@ -54,17 +54,17 @@
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
 findTokensForString(LineBuf, LineToks, FirstOrigToken);
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -178,16 +179,9 @@
 }
 
 /// Parse an identifier in an MS-style inline assembly block.
-///
-/// \param CastInfo - a void* so that we don't have to teach Parser.h
-///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
 unsigned &NumLineToksConsumed,
-void *CastInfo,
 bool IsUnevaluatedContext) {
-  llvm::InlineAsmIdentifierInfo &Info =
-  *(llvm::InlineAsmIdentifierInfo *)CastInfo;
-
   // Push a fake token on the end so that we don't overrun the token
   // stream.  We use ';' because it expression-parsing should never
   // overrun it.
@@ -227,7 +221,7 @@
  /*AllowDeductionGuide=*/false,
  /*ObjectType=*/nullptr, TemplateKWLoc, Id);
 // Perform the lookup.
-Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id, Info,
+Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id,
IsUnevaluatedContext);
   }
   // While the next two tokens are 'period' 'identifier', repeatedly parse it as
@@ -241,7 +235,7 @@
 IdentifierInfo *Id = Tok.getIdentifierInfo();
 ConsumeToken(); // Consume the identifier.
 Result = Actions.LookupInlineAsmVarDeclField(Result.get(), Id->getName(),
- Info, Tok.getLocation());
+ Tok.getLocation());
   }
 
   // Figure out how many tokens we are into LineToks.
Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -48,10 +48,10 @@
   if (E != E2 && E2->isLValue()) {
 if (!S.getLangOpts().HeinousExtensions)
   S.Diag(E2->getLocStart(), diag::err_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 else
   S.Diag(E2->getLocStart(), diag::warn_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 // Accept, even if we emitted an error diagnostic.
 return false;
   }
@@ -607,23 +607,33 @@
   return NS;
 }
 
-static void fillInlineAsmTypeInfo(const ASTContext &Context, QualType T,
-  llvm::InlineAsmIdentifierInfo &Info) {
-  // Compute the type size (and array length if applicable?).
-  Info.Type = Info.Size = Context.getTypeSizeInChars(T).getQuantity();
-  if (T->isArrayType()) {
-const ArrayType *ATy = Context.getAsArrayType(T);
-Info.Type = Context.getTypeSizeInChars(ATy->getElementType()).getQuantity();
-Info.Length = Info.Size / Info.Type;
-  }
+void Sema::FillInlineAsmIdentifierInfo(Expr *Res,
+   llvm::InlineAsmIdentifierInfo &Info) {
+  QualType T = Res->getType();
+  Expr::EvalResult Eval;
+  if (T->isFunctionType() || T->isDependentType()) {
+Info.setLabel(

[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-12 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: lib/Sema/SemaStmtAsm.cpp:617
+return;
+  } else if (Res->isRValue()) {
+bool Enum = isa(T) && Res->EvaluateAsRValue(Eval, 
Context);

rnk wrote:
> RKSimon wrote:
> > (style) Split these instead of an if-elseif chain
> LLVM suggests early returns: 
> https://llvm.org/docs/CodingStandards.html#use-early-exits-and-continue-to-simplify-code
> 
> I don't particularly care here, up to you. I personally like to abuse the 
> ability of C++ to return void to write things like this and skip braces, but 
> maybe *I'm* too clever for my own good:
>   if (T->isFunctionType() || T->isDependentType())
> return Info.setLabel(Res);
>   if (Res->isRValue()) {
> if (isa(T) && Res->EvaluateAsRValue(Eval, Context))
>   return Info.setEnum(Eval.Val.getInt().getSExtValue());
> return Info.setLabel(Res);
>   }
brilliant. was holding myself from emitting such **//returns//**, as i had the 
impression such kind of things are considered taboo. hate redundant bracs. will 
happily address that.
Anything else?



Comment at: lib/Sema/SemaStmtAsm.cpp:620
+bool Enum = isa(T) && Res->EvaluateAsRValue(Eval, 
Context);
+Enum ? Info.setEnum(Eval.Val.getInt().getSExtValue()) : Info.setLabel(Res);
+return;

rnk wrote:
> This conditional expression is a bit too cute, I'd rather use a regular if.
ah.. can't blame me for trying :)


Repository:
  rL LLVM

https://reviews.llvm.org/D37413



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[PATCH] D37466: D37461: fixups for existing InlineAsm tests + adding new ones

2017-09-17 Thread coby via Phabricator via cfe-commits

coby added a comment.

ping


Repository:
  rL LLVM

https://reviews.llvm.org/D37466



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[PATCH] D37413: [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-17 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 115564.
coby added a comment.

addressed @rnk 's suggestions:
cuteness out
c++ mischief in


Repository:
  rL LLVM

https://reviews.llvm.org/D37413

Files:
  include/clang/Parse/Parser.h
  include/clang/Sema/Sema.h
  lib/Parse/ParseStmtAsm.cpp
  lib/Sema/SemaStmtAsm.cpp
  test/CodeGen/ms-inline-asm-enums.cpp
  test/CodeGen/ms-inline-asm-variables.c

Index: lib/Parse/ParseStmtAsm.cpp
===
--- lib/Parse/ParseStmtAsm.cpp
+++ lib/Parse/ParseStmtAsm.cpp
@@ -54,17 +54,17 @@
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
 findTokensForString(LineBuf, LineToks, FirstOrigToken);
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -178,16 +179,9 @@
 }
 
 /// Parse an identifier in an MS-style inline assembly block.
-///
-/// \param CastInfo - a void* so that we don't have to teach Parser.h
-///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
 unsigned &NumLineToksConsumed,
-void *CastInfo,
 bool IsUnevaluatedContext) {
-  llvm::InlineAsmIdentifierInfo &Info =
-  *(llvm::InlineAsmIdentifierInfo *)CastInfo;
-
   // Push a fake token on the end so that we don't overrun the token
   // stream.  We use ';' because it expression-parsing should never
   // overrun it.
@@ -227,7 +221,7 @@
  /*AllowDeductionGuide=*/false,
  /*ObjectType=*/nullptr, TemplateKWLoc, Id);
 // Perform the lookup.
-Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id, Info,
+Result = Actions.LookupInlineAsmIdentifier(SS, TemplateKWLoc, Id,
IsUnevaluatedContext);
   }
   // While the next two tokens are 'period' 'identifier', repeatedly parse it as
@@ -241,7 +235,7 @@
 IdentifierInfo *Id = Tok.getIdentifierInfo();
 ConsumeToken(); // Consume the identifier.
 Result = Actions.LookupInlineAsmVarDeclField(Result.get(), Id->getName(),
- Info, Tok.getLocation());
+ Tok.getLocation());
   }
 
   // Figure out how many tokens we are into LineToks.
Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -48,10 +48,10 @@
   if (E != E2 && E2->isLValue()) {
 if (!S.getLangOpts().HeinousExtensions)
   S.Diag(E2->getLocStart(), diag::err_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 else
   S.Diag(E2->getLocStart(), diag::warn_invalid_asm_cast_lvalue)
-<< E->getSourceRange();
+  << E->getSourceRange();
 // Accept, even if we emitted an error diagnostic.
 return false;
   }
@@ -607,23 +607,31 @@
   return NS;
 }
 
-static void fillInlineAsmTypeInfo(const ASTContext &Context, QualType T,
-  llvm::InlineAsmIdentifierInfo &Info) {
-  // Compute the type size (and array length if applicable?).
-  Info.Type = Info.Size = Context.getTypeSizeInChars(T).getQuantity();
-  if (T->isArrayType()) {
-const ArrayType *ATy = Context.getAsArrayType(T);
-Info.Type = Context.getTypeSizeInChars(ATy->getElementType()).getQuantity();
-Info.Length = Info.Size / Info.Type;
-  }
+void Sema::FillInlineAsmIdentifierInfo(Expr *Res,
+   llvm::InlineAsmIdentifierInfo &Info) {
+  QualType T = Res->getType();
+  Expr::EvalResult Eval;
+  if (T->isFunctionType() || T->i

[PATCH] D35903: [x86][inline-asm]Allow a pack of Control Regs to be properly picked

2017-07-30 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL309508: [x86][inline-asm]Allow a pack of Control Regs to be 
properly picked (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D35903?vs=108317&id=108825#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D35903

Files:
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -58,6 +58,7 @@
 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
+"cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -627,6 +627,17 @@
 // CHECK: call void asm sideeffect inteldialect "mov eax, $0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
+void t44() {
+  // CHECK-LABEL: define void @t44
+  __asm {
+mov cr0, eax
+mov cr2, ebx
+mov cr3, ecx
+mov cr4, edx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -58,6 +58,7 @@
 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
+"cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -627,6 +627,17 @@
 // CHECK: call void asm sideeffect inteldialect "mov eax, $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
+void t44() {
+  // CHECK-LABEL: define void @t44
+  __asm {
+mov cr0, eax
+mov cr2, ebx
+mov cr3, ecx
+mov cr4, edx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", "~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
___
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[PATCH] D36074: [x86][inline-asm]Allow a pack of Control Debug to be properly picked

2017-07-31 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Allows the incorporation of legit (x86) Debug Regs within inline asm stataements


Repository:
  rL LLVM

https://reviews.llvm.org/D36074

Files:
  lib/Basic/Targets/X86.cpp
  test/CodeGen/ms-inline-asm.c


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -59,6 +59,7 @@
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
+"dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -638,6 +638,19 @@
   // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t45() {
+  // CHECK-LABEL: define void @t45
+  __asm {
+mov dr0, eax
+mov dr1, ebx
+mov dr2, ebx
+mov dr3, ecx
+mov dr6, edx
+mov dr7, ecx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -59,6 +59,7 @@
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
+"dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -638,6 +638,19 @@
   // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", "~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t45() {
+  // CHECK-LABEL: define void @t45
+  __asm {
+mov dr0, eax
+mov dr1, ebx
+mov dr2, ebx
+mov dr3, ecx
+mov dr6, edx
+mov dr7, ecx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", "~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
___
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[PATCH] D36074: [x86][inline-asm]Allow a pack of Control Debug to be properly picked

2017-08-01 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL309672: [x86][inline-asm]Allow a pack of Control Debug to be 
properly picked (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D36074?vs=108872&id=109073#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36074

Files:
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -638,6 +638,19 @@
   // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t45() {
+  // CHECK-LABEL: define void @t45
+  __asm {
+mov dr0, eax
+mov dr1, ebx
+mov dr2, ebx
+mov dr3, ecx
+mov dr6, edx
+mov dr7, ecx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}
Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -59,6 +59,7 @@
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
+"dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -638,6 +638,19 @@
   // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", "~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t45() {
+  // CHECK-LABEL: define void @t45
+  __asm {
+mov dr0, eax
+mov dr1, ebx
+mov dr2, ebx
+mov dr3, ecx
+mov dr6, edx
+mov dr7, ecx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", "~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -59,6 +59,7 @@
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
+"dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
___
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[PATCH] D36230: [X86][Asm] Allow negative immediate to appear before bracketed expression

2017-08-02 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Currently, only non-negative immediate is allowed prior to a brac expression 
(memory reference).
MASM / GAS does not have any problem cope with the left side of the real line, 
so we should be able to as well.

llvm: https://reviews.llvm.org/D36229


Repository:
  rL LLVM

https://reviews.llvm.org/D36230

Files:
  test/CodeGen/ms-inline-asm.c


Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -484,13 +484,13 @@
   __asm mov eax, (4 + 4) * 16
 // CHECK: mov eax, $$128
   __asm mov eax, 4 + 8 * -16
-// CHECK: mov eax, $$4294967172
+// CHECK: mov eax, $$-124
   __asm mov eax, 4 + 16 / -8
 // CHECK: mov eax, $$2
   __asm mov eax, (16 + 16) / -8
-// CHECK: mov eax, $$4294967292
+// CHECK: mov eax, $$-4
   __asm mov eax, ~15
-// CHECK: mov eax, $$4294967280
+// CHECK: mov eax, $$-16
   __asm mov eax, 6 ^ 3
 // CHECK: mov eax, $$5
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -651,6 +651,12 @@
   // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t46() {
+  // CHECK-LABEL: define void @t46
+  __asm add eax, -128[eax]
+  // CHECK: call void asm sideeffect inteldialect "add eax, $$-128[eax]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -484,13 +484,13 @@
   __asm mov eax, (4 + 4) * 16
 // CHECK: mov eax, $$128
   __asm mov eax, 4 + 8 * -16
-// CHECK: mov eax, $$4294967172
+// CHECK: mov eax, $$-124
   __asm mov eax, 4 + 16 / -8
 // CHECK: mov eax, $$2
   __asm mov eax, (16 + 16) / -8
-// CHECK: mov eax, $$4294967292
+// CHECK: mov eax, $$-4
   __asm mov eax, ~15
-// CHECK: mov eax, $$4294967280
+// CHECK: mov eax, $$-16
   __asm mov eax, 6 ^ 3
 // CHECK: mov eax, $$5
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -651,6 +651,12 @@
   // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", "~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t46() {
+  // CHECK-LABEL: define void @t46
+  __asm add eax, -128[eax]
+  // CHECK: call void asm sideeffect inteldialect "add eax, $$-128[eax]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
___
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[PATCH] D36371: [Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

2017-08-06 Thread coby via Phabricator via cfe-commits

coby created this revision.

This patch is intended to enable the use of basic double letter constraints 
used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes https://reviews.llvm.org/D32505
llvm counterpart: https://reviews.llvm.org/D36369


Repository:
  rL LLVM

https://reviews.llvm.org/D36371

Files:
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/TargetInfo.cpp


Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -865,7 +866,10 @@
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
   StringRef Constraint,
   llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch(Constraint)
+ .Cases("y", "&y", "^Ym", true)
+ .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
 if (cast(Ty)->getBitWidth() != 64) {
   // Invalid MMX constraint
   return nullptr;
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -1346,7 +1346,9 @@
 switch (*Name) {
 default:
   return false;
+case 'z':
 case '0': // First SSE register.
+case '2':
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1435,12 +1437,19 @@
   return Size <= 64;
 case 'i':
 case 't':
-  // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
+case '2':
+  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
+  // Any SSE register when SSE2 and up is available
   if (SSELevel >= AVX512F)
 return Size <= 512U;
   else if (SSELevel >= AVX)
 return Size <= 256U;
   return SSELevel >= SSE2 && Size <= 128U;
+case 'z':
+case '0':
+  // XMM0
+  if (SSELevel >= SSE1)
+return Size <= 128U;
 }
   }
 
@@ -1475,6 +1484,12 @@
   // the return string.
   break;
 case 'k':
+case 'm':
+case 'i':
+case 't':
+case 'z':
+case '0':
+case '2':
   // "^" hints llvm that this is a 2 letter constraint.
   // "Constraint++" is used to promote the string iterator
   // to the next constraint.
Index: lib/Basic/Targets/X86.h
===
--- lib/Basic/Targets/X86.h
+++ lib/Basic/Targets/X86.h
@@ -435,9 +435,12 @@
 // In case the constraint is 'r' we need to return Expression
 case 'r':
   return Expression;
+// Double letters Y constraints
+case 'Y':
+  if ((++I != E) && ((*I == '0') || (*I == 'z')))
+return "xmm0";
 default:
-  // Default value if there is no constraint for the register
-  return "";
+  LLVM_FALLTHROUGH;
 }
 return "";
   }


Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -865,7 +866,10 @@
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
   StringRef Constraint,
   llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch(Constraint)
+ .Cases("y", "&y", "^Ym", true)
+ .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
 if (cast(Ty)->getBitWidth() != 64) {
   // Invalid MMX constraint
   return nullptr;
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -1346,7 +1346,9 @@
 switch (*Name) {
 default:
   return false;
+case 'z':
 case '0': // First SSE register.
+case '2':
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1435,12 +1437,19 @@
   return Size <= 64;
 case 'i':
 case 't':
-

[PATCH] D36450: [X86][Ms-InlineAsm] Extend MS Dot operator to accept "this" + struct/class pointers aliases

2017-08-08 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

MS InlineAsm Dot operator accepts "Bases" such as "this" (cpp) and class/struct 
pointer typedef.
This patch enhance its implementation with this behavior.


Repository:
  rL LLVM

https://reviews.llvm.org/D36450

Files:
  lib/Sema/SemaStmtAsm.cpp
  test/CodeGen/ms-inline-asm.c
  test/CodeGen/ms-inline-asm.cpp

Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -677,22 +677,32 @@
   SmallVector Members;
   Member.split(Members, ".");
 
-  LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
-  LookupOrdinaryName);
+  NamedDecl *FoundDecl = nullptr;
 
-  if (!LookupName(BaseResult, getCurScope()))
-return true;
-  
-  if(!BaseResult.isSingleResult())
+  // MS InlineAsm uses 'this' as a base
+  if (getLangOpts().CPlusPlus && Base.equals("this")) {
+if (const Type *PT = getCurrentThisType().getTypePtrOrNull())
+  FoundDecl = PT->getPointeeType()->getAsTagDecl();
+  } else {
+LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
+LookupOrdinaryName);
+if (LookupName(BaseResult, getCurScope()) && BaseResult.isSingleResult())
+  FoundDecl = BaseResult.getFoundDecl();
+  }
+
+  if (!FoundDecl)
 return true;
-  NamedDecl *FoundDecl = BaseResult.getFoundDecl();
+
   for (StringRef NextMember : Members) {
 const RecordType *RT = nullptr;
 if (VarDecl *VD = dyn_cast(FoundDecl))
   RT = VD->getType()->getAs();
 else if (TypedefNameDecl *TD = dyn_cast(FoundDecl)) {
   MarkAnyDeclReferenced(TD->getLocation(), TD, /*OdrUse=*/false);
-  RT = TD->getUnderlyingType()->getAs();
+  // MS InlineAsm often uses struct pointer aliases as a base
+  const QualType QT = TD->getUnderlyingType();
+  RT = isa(QT) ? QT->getPointeeType()->getAs() :
+  QT->getAs();
 } else if (TypeDecl *TD = dyn_cast(FoundDecl))
   RT = TD->getTypeForDecl()->getAs();
 else if (FieldDecl *TD = dyn_cast(FoundDecl))
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -527,7 +527,7 @@
 typedef struct {
   int a;
   int b;
-} A;
+} A, *pA;
 
 typedef struct {
   int b1;
@@ -539,14 +539,16 @@
   A   c2;
   int c3;
   B   c4;
-} C;
+} C, *pC;
 
 void t39() {
 // CHECK-LABEL: define void @t39
   __asm mov eax, [eax].A.b
 // CHECK: mov eax, [eax].4
   __asm mov eax, [eax] A.b
 // CHECK: mov eax, [eax] .4
+  __asm mov eax, [eax] pA.b
+// CHECK: mov eax, [eax] .4
   __asm mov eax, fs:[0] A.b
 // CHECK: mov eax, fs:[$$0] .4
   __asm mov eax, [eax].B.b2.a
@@ -557,6 +559,8 @@
 // CHECK: mov eax, fs:[$$0] .8
   __asm mov eax, [eax]C.c4.b2.b
 // CHECK: mov eax, [eax].24
+  __asm mov eax, [eax]pC.c4.b2.b
+// CHECK: mov eax, [eax].24
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
Index: test/CodeGen/ms-inline-asm.cpp
===
--- test/CodeGen/ms-inline-asm.cpp
+++ test/CodeGen/ms-inline-asm.cpp
@@ -180,3 +180,19 @@
   A::g();
 }
 
+void t9() {
+  // CHECK-LABEL: define void @_Z2t9v()
+  struct A {
+int a;
+int b;
+void g() {
+  __asm mov eax, dword ptr [eax]this.b
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, dword ptr [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+}
+  };
+  A AA;
+  AA.g();
+}
+
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[PATCH] D36450: [X86][Ms-InlineAsm] Extend MS Dot operator to accept "this" + struct/class pointers aliases

2017-08-09 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: lib/Sema/SemaStmtAsm.cpp:702-705
+  // MS InlineAsm often uses struct pointer aliases as a base
+  const QualType QT = TD->getUnderlyingType();
+  RT = isa(QT) ? QT->getPointeeType()->getAs() :
+  QT->getAs();

rnk wrote:
> This would probably be simpler as:
>   QualType Ty = TD->getUnderlyingType();
>   if (const auto *PT = Ty->getAs())
> Ty = PT->getPointeeType();
>   RT = Ty->getAsRecordType();
> ... to avoid repeating getAs().
Indeed. thx for pointing it out!


Repository:
  rL LLVM

https://reviews.llvm.org/D36450



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[PATCH] D36450: [X86][Ms-InlineAsm] Extend MS Dot operator to accept "this" + struct/class pointers aliases

2017-08-09 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL310472: [X86][Ms-InlineAsm] Extend MS Dot operator to accept 
"this" + struct/class… (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D36450?vs=110145&id=110377#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36450

Files:
  cfe/trunk/lib/Sema/SemaStmtAsm.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm.c
  cfe/trunk/test/CodeGen/ms-inline-asm.cpp

Index: cfe/trunk/test/CodeGen/ms-inline-asm.cpp
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.cpp
+++ cfe/trunk/test/CodeGen/ms-inline-asm.cpp
@@ -180,3 +180,19 @@
   A::g();
 }
 
+void t9() {
+  // CHECK-LABEL: define void @_Z2t9v()
+  struct A {
+int a;
+int b;
+void g() {
+  __asm mov eax, dword ptr [eax]this.b
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, dword ptr [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+}
+  };
+  A AA;
+  AA.g();
+}
+
Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -527,7 +527,7 @@
 typedef struct {
   int a;
   int b;
-} A;
+} A, *pA;
 
 typedef struct {
   int b1;
@@ -539,14 +539,16 @@
   A   c2;
   int c3;
   B   c4;
-} C;
+} C, *pC;
 
 void t39() {
 // CHECK-LABEL: define void @t39
   __asm mov eax, [eax].A.b
 // CHECK: mov eax, [eax].4
   __asm mov eax, [eax] A.b
 // CHECK: mov eax, [eax] .4
+  __asm mov eax, [eax] pA.b
+// CHECK: mov eax, [eax] .4
   __asm mov eax, fs:[0] A.b
 // CHECK: mov eax, fs:[$$0] .4
   __asm mov eax, [eax].B.b2.a
@@ -557,6 +559,8 @@
 // CHECK: mov eax, fs:[$$0] .8
   __asm mov eax, [eax]C.c4.b2.b
 // CHECK: mov eax, [eax].24
+  __asm mov eax, [eax]pC.c4.b2.b
+// CHECK: mov eax, [eax].24
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
Index: cfe/trunk/lib/Sema/SemaStmtAsm.cpp
===
--- cfe/trunk/lib/Sema/SemaStmtAsm.cpp
+++ cfe/trunk/lib/Sema/SemaStmtAsm.cpp
@@ -677,22 +677,33 @@
   SmallVector Members;
   Member.split(Members, ".");
 
-  LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
-  LookupOrdinaryName);
+  NamedDecl *FoundDecl = nullptr;
 
-  if (!LookupName(BaseResult, getCurScope()))
-return true;
-  
-  if(!BaseResult.isSingleResult())
+  // MS InlineAsm uses 'this' as a base
+  if (getLangOpts().CPlusPlus && Base.equals("this")) {
+if (const Type *PT = getCurrentThisType().getTypePtrOrNull())
+  FoundDecl = PT->getPointeeType()->getAsTagDecl();
+  } else {
+LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
+LookupOrdinaryName);
+if (LookupName(BaseResult, getCurScope()) && BaseResult.isSingleResult())
+  FoundDecl = BaseResult.getFoundDecl();
+  }
+
+  if (!FoundDecl)
 return true;
-  NamedDecl *FoundDecl = BaseResult.getFoundDecl();
+
   for (StringRef NextMember : Members) {
 const RecordType *RT = nullptr;
 if (VarDecl *VD = dyn_cast(FoundDecl))
   RT = VD->getType()->getAs();
 else if (TypedefNameDecl *TD = dyn_cast(FoundDecl)) {
   MarkAnyDeclReferenced(TD->getLocation(), TD, /*OdrUse=*/false);
-  RT = TD->getUnderlyingType()->getAs();
+  // MS InlineAsm often uses struct pointer aliases as a base
+  QualType QT = TD->getUnderlyingType();
+  if (const auto *PT = QT->getAs())
+QT = PT->getPointeeType();
+  RT = QT->getAs();
 } else if (TypeDecl *TD = dyn_cast(FoundDecl))
   RT = TD->getTypeForDecl()->getAs();
 else if (FieldDecl *TD = dyn_cast(FoundDecl))
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[PATCH] D36230: [X86][Asm] Allow negative immediate to appear before bracketed expression

2017-08-09 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL310529: [X86][Asm] Allow negative immediate to appear before 
bracketed expression (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D36230?vs=109374&id=110485#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36230

Files:
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -484,13 +484,13 @@
   __asm mov eax, (4 + 4) * 16
 // CHECK: mov eax, $$128
   __asm mov eax, 4 + 8 * -16
-// CHECK: mov eax, $$4294967172
+// CHECK: mov eax, $$-124
   __asm mov eax, 4 + 16 / -8
 // CHECK: mov eax, $$2
   __asm mov eax, (16 + 16) / -8
-// CHECK: mov eax, $$4294967292
+// CHECK: mov eax, $$-4
   __asm mov eax, ~15
-// CHECK: mov eax, $$4294967280
+// CHECK: mov eax, $$-16
   __asm mov eax, 6 ^ 3
 // CHECK: mov eax, $$5
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -655,6 +655,12 @@
   // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t46() {
+  // CHECK-LABEL: define void @t46
+  __asm add eax, -128[eax]
+  // CHECK: call void asm sideeffect inteldialect "add eax, $$-128[eax]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -484,13 +484,13 @@
   __asm mov eax, (4 + 4) * 16
 // CHECK: mov eax, $$128
   __asm mov eax, 4 + 8 * -16
-// CHECK: mov eax, $$4294967172
+// CHECK: mov eax, $$-124
   __asm mov eax, 4 + 16 / -8
 // CHECK: mov eax, $$2
   __asm mov eax, (16 + 16) / -8
-// CHECK: mov eax, $$4294967292
+// CHECK: mov eax, $$-4
   __asm mov eax, ~15
-// CHECK: mov eax, $$4294967280
+// CHECK: mov eax, $$-16
   __asm mov eax, 6 ^ 3
 // CHECK: mov eax, $$5
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -655,6 +655,12 @@
   // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", "~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t46() {
+  // CHECK-LABEL: define void @t46
+  __asm add eax, -128[eax]
+  // CHECK: call void asm sideeffect inteldialect "add eax, $$-128[eax]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
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[PATCH] D35205: [Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

2017-08-10 Thread coby via Phabricator via cfe-commits

coby abandoned this revision.
coby added a comment.

superseded by https://reviews.llvm.org/D36371


Repository:
  rL LLVM

https://reviews.llvm.org/D35205



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[PATCH] D36794: Fixups to FE tests affected by D36793

2017-08-16 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Repository:
  rL LLVM

https://reviews.llvm.org/D36794

Files:
  test/CodeGen/mozilla-ms-inline-asm.c
  test/CodeGen/ms-inline-asm-64.c
  test/CodeGen/ms-inline-asm.c
  test/CodeGen/ms-inline-asm.cpp
  test/CodeGenCXX/ms-inline-asm-return.cpp
  test/Sema/ms-inline-asm.c

Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -42,7 +42,7 @@
 void t6(void) {
   __asm int 0x2c
 // CHECK: t6
-// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", "~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t7() {
@@ -61,7 +61,7 @@
 mov eax, ebx
   }
 // CHECK: t7
-// CHECK: call void asm sideeffect inteldialect "int $$0x2cU", "~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", "~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "mov eax, ebx", "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -94,7 +94,7 @@
 // CHECK: t9
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$0x07
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -229,7 +229,7 @@
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
   __asm mov eax, [eax + LENGTH foo * 4]
-// CHECK: mov eax, [eax + $$1 * $$4]
+// CHECK: mov eax, [eax + $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -240,16 +240,16 @@
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
   __asm mov eax, [eax + TYPE foo * 4]
-// CHECK: mov eax, [eax + $$4 * $$4]
+// CHECK: mov eax, [eax + $$16]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
   __asm mov eax, [eax + SIZE _foo * 4]
-// CHECK: mov eax, [eax + $$16 * $$4]
+// CHECK: mov eax, [eax + $$64]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -265,7 +265,7 @@
 // CHECK: t21
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$07H
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -312,13 +312,13 @@
 void t25() {
 // CHECK: t25
   __asm mov eax, 0h
-// CHECK: mov eax, $$0h
+// CHECK: mov eax, $$4294967295
   __asm mov eax, 0fhU
 // CHECK: mov eax, $$15
   __asm mov eax, 0a2h
-// CHECK: mov eax, $$0a2h
+// CHECK: mov eax, $$162
   __asm mov eax, 10100010b
-// CHECK: mov eax, $$10100010b
+// CHECK: mov eax, $$162
   __asm mov eax, 10100010BU
 // CHECK: mov eax, $$162
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -344,7 +344,7 @@
 void t27() {
   __asm mov eax, fs:[0h]
 // CHECK: t27
-// CHECK: call void asm sideeffect inteldialect "mov eax, fs:[$$0h]", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "mov eax, fs:[$$0]", "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t28() {
@@ -426,49 +426,49 @@
 void t34() {
 // CHECK: t34
   __asm prefetchnta 64[eax]
-// CHECK: prefetchnta $$64[eax]
+// CHECK: prefetchnta [eax + $$64]
   __asm mov eax, dword ptr 4[eax]
-// CHECK: mov eax, dword ptr $$4[eax]
+// CHECK: mov eax, dword ptr [eax + $$4]
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t35() {
 // CHECK: t35
   __asm prefetchnta [eax + (200*64)]
-// CHECK: prefetchnta [eax + ($$200*$$64)]
+// CHECK: prefetchnta [eax + $$12800]
   __asm mov eax, dword ptr [eax + (200*64)]
-// CHECK: mov eax, dword ptr [eax + ($$200*$$64)]
+// CHECK: mov eax, dword ptr [eax + $$12800]
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t36() {
 // CHECK: t36
   int arr[4];
   // Work around PR20368: These should be single line blocks
   __asm { mov eax, 4[arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0[$$4]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0[$$8]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 8[arr + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$72$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0[$$72]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 12[4 + arr] }
-// CHECK: call void

[PATCH] D36371: [Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

2017-08-20 Thread coby via Phabricator via cfe-commits

coby updated this revision to Diff 111885.
coby added a comment.
Herald added a subscriber: eraman.

> @rnk: tests?

Add forgotten test.


Repository:
  rL LLVM

https://reviews.llvm.org/D36371

Files:
  lib/Basic/Targets/X86.cpp
  lib/Basic/Targets/X86.h
  lib/CodeGen/TargetInfo.cpp
  test/CodeGen/x86-GCC-inline-asm-Y-constraints.c

Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -870,7 +871,10 @@
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
   StringRef Constraint,
   llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch(Constraint)
+ .Cases("y", "&y", "^Ym", true)
+ .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
 if (cast(Ty)->getBitWidth() != 64) {
   // Invalid MMX constraint
   return nullptr;
Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -1386,7 +1386,9 @@
 switch (*Name) {
 default:
   return false;
+case 'z':
 case '0': // First SSE register.
+case '2':
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1455,33 +1457,39 @@
   case 't':
   case 'u':
 return Size <= 128;
-  case 'v':
-  case 'x':
-if (SSELevel >= AVX512F)
-  // 512-bit zmm registers can be used if target supports AVX512F.
-  return Size <= 512U;
-else if (SSELevel >= AVX)
-  // 256-bit ymm registers can be used if target supports AVX.
-  return Size <= 256U;
-return Size <= 128U;
   case 'Y':
 // 'Y' is the first character for several 2-character constraints.
 switch (Constraint[1]) {
 default:
-  break;
+  return false;
 case 'm':
   // 'Ym' is synonymous with 'y'.
 case 'k':
   return Size <= 64;
+case 'z':
+case '0':
+  // XMM0
+  if (SSELevel >= SSE1)
+return Size <= 128U;
+  return false;
 case 'i':
 case 't':
-  // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
-  if (SSELevel >= AVX512F)
-return Size <= 512U;
-  else if (SSELevel >= AVX)
-return Size <= 256U;
-  return SSELevel >= SSE2 && Size <= 128U;
+case '2':
+  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
+  if (SSELevel < SSE2)
+return false;
+  break;
 }
+  case 'v':
+  case 'x':
+if (SSELevel >= AVX512F)
+  // 512-bit zmm registers can be used if target supports AVX512F.
+  return Size <= 512U;
+else if (SSELevel >= AVX)
+  // 256-bit ymm registers can be used if target supports AVX.
+  return Size <= 256U;
+return Size <= 128U;
+
   }
 
   return true;
@@ -1515,6 +1523,12 @@
   // the return string.
   break;
 case 'k':
+case 'm':
+case 'i':
+case 't':
+case 'z':
+case '0':
+case '2':
   // "^" hints llvm that this is a 2 letter constraint.
   // "Constraint++" is used to promote the string iterator
   // to the next constraint.
Index: lib/Basic/Targets/X86.h
===
--- lib/Basic/Targets/X86.h
+++ lib/Basic/Targets/X86.h
@@ -437,9 +437,12 @@
 // In case the constraint is 'r' we need to return Expression
 case 'r':
   return Expression;
+// Double letters Y constraints
+case 'Y':
+  if ((++I != E) && ((*I == '0') || (*I == 'z')))
+return "xmm0";
 default:
-  // Default value if there is no constraint for the register
-  return "";
+  break;
 }
 return "";
   }
Index: test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
===
--- test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
+++ test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -ffreestanding  -triple=x86_64-apple-darwin -target-cpu skx %s -emit-llvm -o - | FileCheck %s
+#include 
+// This test is complimented by the .ll test under llvm/test/MC/X86/. 
+// At this level we can only check if the constarints are passed correctly
+// from inline asm to llvm IR.
+
+// CHECK-LABEL: @f_Ym
+void f_Ym(__m64 m)
+  {
+  // CHECK: movq  $0, %mm1
+  // CHECK-SAME: "=^Ym,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("movq %0, %%mm1\n\t"
+

[PATCH] D36794: Fixups to FE tests affected by D36793

2017-08-24 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311640: Fixups to FE tests affected by D36793 (authored by 
coby).

Changed prior to commit:
  https://reviews.llvm.org/D36794?vs=111340&id=112518#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36794

Files:
  cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c
  cfe/trunk/test/CodeGen/ms-inline-asm-64.c
  cfe/trunk/test/CodeGen/ms-inline-asm.c
  cfe/trunk/test/CodeGen/ms-inline-asm.cpp
  cfe/trunk/test/CodeGenCXX/ms-inline-asm-return.cpp
  cfe/trunk/test/Sema/ms-inline-asm.c

Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -42,7 +42,7 @@
 void t6(void) {
   __asm int 0x2c
 // CHECK: t6
-// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", "~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t7() {
@@ -61,7 +61,7 @@
 mov eax, ebx
   }
 // CHECK: t7
-// CHECK: call void asm sideeffect inteldialect "int $$0x2cU", "~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", "~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "mov eax, ebx", "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -94,7 +94,7 @@
 // CHECK: t9
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$0x07
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -229,7 +229,7 @@
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
   __asm mov eax, [eax + LENGTH foo * 4]
-// CHECK: mov eax, [eax + $$1 * $$4]
+// CHECK: mov eax, [eax + $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -240,16 +240,16 @@
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
   __asm mov eax, [eax + TYPE foo * 4]
-// CHECK: mov eax, [eax + $$4 * $$4]
+// CHECK: mov eax, [eax + $$16]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
   __asm mov eax, [eax + SIZE _foo * 4]
-// CHECK: mov eax, [eax + $$16 * $$4]
+// CHECK: mov eax, [eax + $$64]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -265,7 +265,7 @@
 // CHECK: t21
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$07H
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -312,13 +312,13 @@
 void t25() {
 // CHECK: t25
   __asm mov eax, 0h
-// CHECK: mov eax, $$0h
+// CHECK: mov eax, $$4294967295
   __asm mov eax, 0fhU
 // CHECK: mov eax, $$15
   __asm mov eax, 0a2h
-// CHECK: mov eax, $$0a2h
+// CHECK: mov eax, $$162
   __asm mov eax, 10100010b
-// CHECK: mov eax, $$10100010b
+// CHECK: mov eax, $$162
   __asm mov eax, 10100010BU
 // CHECK: mov eax, $$162
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -344,7 +344,7 @@
 void t27() {
   __asm mov eax, fs:[0h]
 // CHECK: t27
-// CHECK: call void asm sideeffect inteldialect "mov eax, fs:[$$0h]", "~{eax},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "mov eax, fs:[$$0]", "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t28() {
@@ -426,49 +426,49 @@
 void t34() {
 // CHECK: t34
   __asm prefetchnta 64[eax]
-// CHECK: prefetchnta $$64[eax]
+// CHECK: prefetchnta [eax + $$64]
   __asm mov eax, dword ptr 4[eax]
-// CHECK: mov eax, dword ptr $$4[eax]
+// CHECK: mov eax, dword ptr [eax + $$4]
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t35() {
 // CHECK: t35
   __asm prefetchnta [eax + (200*64)]
-// CHECK: prefetchnta [eax + ($$200*$$64)]
+// CHECK: prefetchnta [eax + $$12800]
   __asm mov eax, dword ptr [eax + (200*64)]
-// CHECK: mov eax, dword ptr [eax + ($$200*$$64)]
+// CHECK: mov eax, dword ptr [eax + $$12800]
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t36() {
 // CHECK: t36
   int arr[4];
   // Work around PR20368: These should be single line blocks
   __asm { mov eax, 4[arr] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0[$$4]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 4[arr + 4] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0[$$8]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 8[arr + 4 + 32*2 - 4] }
-// CHECK: call void asm sideeffect intel

[PATCH] D36371: [Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

2017-08-24 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL311643: [Clang][x86][Inline Asm] support for GCC style 
inline asm - Y constraints (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D36371?vs=111885&id=112521#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36371

Files:
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/lib/Basic/Targets/X86.h
  cfe/trunk/lib/CodeGen/TargetInfo.cpp
  cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c

Index: cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
===
--- cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
+++ cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -ffreestanding  -triple=x86_64-apple-darwin -target-cpu skx %s -emit-llvm -o - | FileCheck %s
+#include 
+// This test is complimented by the .ll test under llvm/test/MC/X86/. 
+// At this level we can only check if the constarints are passed correctly
+// from inline asm to llvm IR.
+
+// CHECK-LABEL: @f_Ym
+void f_Ym(__m64 m)
+  {
+  // CHECK: movq  $0, %mm1
+  // CHECK-SAME: "=^Ym,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("movq %0, %%mm1\n\t"
+  :"=Ym" (m));
+}
+
+// CHECK-LABEL: f_Yi
+void f_Yi(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yi,^Yi,^Yi,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+  :"=Yi" (x)
+  :"Yi" (y),"Yi"(z));
+}
+
+// CHECK-LABEL: f_Yt
+void f_Yt(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yt,^Yt,^Yt,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+  :"=Yt" (x)
+  :"Yt" (y),"Yt"(z));
+}
+
+// CHECK-LABEL: f_Y2
+void f_Y2(__m128 x, __m128 y, __m128 z)
+{
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Y2,^Y2,^Y2,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0, %1, %2\n\t"
+:"=Y2" (x)
+:"Y2" (y),"Y2"(z));
+}
+
+// CHECK-LABEL: f_Yz
+void f_Yz(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: vpaddq
+  // CHECK-SAME: "=^Yi,=^Yz,^Yi,0,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0,%2,%1\n\t"
+   "vpaddq %1,%0,%2\n\t"
+  :"+Yi"(z),"=Yz" (x)
+  :"Yi" (y) );
+}
+
+// CHECK-LABEL: f_Y0
+void f_Y0(__m128 x, __m128 y, __m128 z)
+  {
+  // CHECK: vpaddq
+  // CHECK-SAME: "=^Yi,=^Y0,^Yi,0,~{dirflag},~{fpsr},~{flags}"
+  __asm__ volatile ("vpaddq %0,%2,%1\n\t"
+  "vpaddq %1,%0,%2\n\t"
+  :"+Yi"(z),"=Y0" (x)
+  :"Yi" (y) );
+}
+
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -870,7 +871,10 @@
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
   StringRef Constraint,
   llvm::Type* Ty) {
-  if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) {
+  bool IsMMXCons = llvm::StringSwitch(Constraint)
+ .Cases("y", "&y", "^Ym", true)
+ .Default(false);
+  if (IsMMXCons && Ty->isVectorTy()) {
 if (cast(Ty)->getBitWidth() != 64) {
   // Invalid MMX constraint
   return nullptr;
Index: cfe/trunk/lib/Basic/Targets/X86.h
===
--- cfe/trunk/lib/Basic/Targets/X86.h
+++ cfe/trunk/lib/Basic/Targets/X86.h
@@ -437,9 +437,12 @@
 // In case the constraint is 'r' we need to return Expression
 case 'r':
   return Expression;
+// Double letters Y constraints
+case 'Y':
+  if ((++I != E) && ((*I == '0') || (*I == 'z')))
+return "xmm0";
 default:
-  // Default value if there is no constraint for the register
-  return "";
+  break;
 }
 return "";
   }
Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -1386,7 +1386,9 @@
 switch (*Name) {
 default:
   return false;
+case 'z':
 case '0': // First SSE register.
+case '2':
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1455,33 +1457,39 @@
   case 't':
   case 'u':
 return Size <= 128;
-  case 'v':
-  case 'x':
-if (SSELevel >= AVX512F)
-  // 512-bit zmm registers can be used if

[PATCH] D38445: [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob

2017-11-20 Thread coby via Phabricator via cfe-commits

coby added a comment.

Reid,
can you please have a look?


Repository:
  rL LLVM

https://reviews.llvm.org/D38445



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[PATCH] D38445: [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob

2017-11-21 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL318739: [x86][inline-asm] allow recognition of MPX regs 
inside ms inline-asm blob (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D38445?vs=117278&id=123730#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D38445

Files:
  cfe/trunk/lib/Basic/Targets/X86.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -60,6 +60,7 @@
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 "dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
+"bnd0",  "bnd1",  "bnd2",  "bnd3",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -661,6 +661,17 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47() {
+  // CHECK-LABEL: define void @t47
+  __asm {
+bndmk bnd0, dword ptr [eax]
+bndmk bnd1, dword ptr [ebx]
+bndmk bnd2, dword ptr [ecx]
+bndmk bnd3, dword ptr [edx]
+  }
+  // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr 
[eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr 
[ecx]\0A\09bndmk bnd3, dword ptr [edx]", 
"~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
   // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: cfe/trunk/lib/Basic/Targets/X86.cpp
===
--- cfe/trunk/lib/Basic/Targets/X86.cpp
+++ cfe/trunk/lib/Basic/Targets/X86.cpp
@@ -60,6 +60,7 @@
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 "dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
+"bnd0",  "bnd1",  "bnd2",  "bnd3",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -661,6 +661,17 @@
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", "~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47() {
+  // CHECK-LABEL: define void @t47
+  __asm {
+bndmk bnd0, dword ptr [eax]
+bndmk bnd1, dword ptr [ebx]
+bndmk bnd2, dword ptr [ecx]
+bndmk bnd3, dword ptr [edx]
+  }
+  // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr [eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr [ecx]\0A\09bndmk bnd3, dword ptr [edx]", "~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
   // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
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[PATCH] D31174: [X86][MS-compatability] allow MS TYPE/SIZE/LENGTH operators as a part of a compound expression

2017-03-21 Thread coby via Phabricator via cfe-commits

coby created this revision.

This patch introduces X86AsmParser with the ability to handle the 
aforementioned ops within compound "MS" arithmetical expressions. Currently - 
only supported as a stand alone Operand, e.g.:
"TYPE X"
now allowed :
"4 + TYPE X * 128"

LLVM side: https://reviews.llvm.org/D31173


Repository:
  rL LLVM

https://reviews.llvm.org/D31174

Files:
  test/CodeGen/ms-inline-asm.c


Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -201,6 +201,8 @@
 // CHECK: mov eax, $$4
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
+  __asm mov eax, [eax + LENGTH foo * 4]
+// CHECK: mov eax, [eax + $$1 * $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -210,16 +212,21 @@
 // CHECK: mov eax, $$4
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
+  __asm mov eax, [eax + TYPE foo * 4]
+// CHECK: mov eax, [eax + $$4 * $$4]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
+  __asm mov eax, [eax + SIZE _foo * 4]
+// CHECK: mov eax, [eax + $$16 * $$4]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+
 }
 
 void t21() {


Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -201,6 +201,8 @@
 // CHECK: mov eax, $$4
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
+  __asm mov eax, [eax + LENGTH foo * 4]
+// CHECK: mov eax, [eax + $$1 * $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -210,16 +212,21 @@
 // CHECK: mov eax, $$4
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
+  __asm mov eax, [eax + TYPE foo * 4]
+// CHECK: mov eax, [eax + $$4 * $$4]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
+  __asm mov eax, [eax + SIZE _foo * 4]
+// CHECK: mov eax, [eax + $$16 * $$4]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+
 }
 
 void t21() {
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[PATCH] D31174: [X86][MS-compatability] allow MS TYPE/SIZE/LENGTH operators as a part of a compound expression

2017-03-21 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL298426: [X86][MS-compatability][clang] allow MS 
TYPE/SIZE/LENGTH operators as a part of… (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D31174?vs=92437&id=92529#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D31174

Files:
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -201,6 +201,8 @@
 // CHECK: mov eax, $$4
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
+  __asm mov eax, [eax + LENGTH foo * 4]
+// CHECK: mov eax, [eax + $$1 * $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -210,16 +212,21 @@
 // CHECK: mov eax, $$4
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
+  __asm mov eax, [eax + TYPE foo * 4]
+// CHECK: mov eax, [eax + $$4 * $$4]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
+  __asm mov eax, [eax + SIZE _foo * 4]
+// CHECK: mov eax, [eax + $$16 * $$4]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+
 }
 
 void t21() {


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -201,6 +201,8 @@
 // CHECK: mov eax, $$4
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
+  __asm mov eax, [eax + LENGTH foo * 4]
+// CHECK: mov eax, [eax + $$1 * $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -210,16 +212,21 @@
 // CHECK: mov eax, $$4
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
+  __asm mov eax, [eax + TYPE foo * 4]
+// CHECK: mov eax, [eax + $$4 * $$4]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
   __asm mov eax, SIZE bar
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
+  __asm mov eax, [eax + SIZE _foo * 4]
+// CHECK: mov eax, [eax + $$16 * $$4]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+
 }
 
 void t21() {
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[PATCH] D27418: [X86][inline-asm] Add support for MS 'EVEN' directive

2017-04-04 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL299454: [X86][inline-asm] Add support for MS 'EVEN' 
directive (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D27418?vs=80280&id=94095#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D27418

Files:
  cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
@@ -0,0 +1,15 @@
+// RUN: %clang_cc1 %s -triple i386-unknown-unknown -fasm-blocks -emit-llvm -o 
- | FileCheck %s
+
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK:  .even
+void t1() {
+  __asm {
+.byte 64
+.byte 64
+.byte 64
+EVEN
+mov eax, ebx
+  }
+}


Index: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
@@ -0,0 +1,15 @@
+// RUN: %clang_cc1 %s -triple i386-unknown-unknown -fasm-blocks -emit-llvm -o - | FileCheck %s
+
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK:  .even
+void t1() {
+  __asm {
+.byte 64
+.byte 64
+.byte 64
+EVEN
+mov eax, ebx
+  }
+}
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[PATCH] D28989: [X86][MS]Adjacent comments within multi-line inline assembly statement

2017-01-24 Thread coby via Phabricator via cfe-commits

coby added a comment.

Ping


Repository:
  rL LLVM

https://reviews.llvm.org/D28989



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[PATCH] D28989: [X86][MS]Adjacent comments within multi-line inline assembly statement

2017-02-05 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL294120: [X86][MS]Adjacent comments within multi-line inline 
assembly statement (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D28989?vs=85276&id=87135#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D28989

Files:
  cfe/trunk/lib/Parse/ParseStmtAsm.cpp
  cfe/trunk/test/CodeGen/ms-inline-asm.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -55,9 +55,15 @@
 }
   }
   __asm {}
+  __asm {
+;
+; label
+mov eax, ebx
+  }
 // CHECK: t7
 // CHECK: call void asm sideeffect inteldialect "int $$0x2cU", 
"~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", 
"~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "mov eax, ebx", 
"~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 int t8() {
Index: cfe/trunk/lib/Parse/ParseStmtAsm.cpp
===
--- cfe/trunk/lib/Parse/ParseStmtAsm.cpp
+++ cfe/trunk/lib/Parse/ParseStmtAsm.cpp
@@ -457,6 +457,11 @@
 break;
   LineNo = SrcMgr.getLineNumber(ExpLoc.first, ExpLoc.second);
   SkippedStartOfLine = Tok.isAtStartOfLine();
+} else if (Tok.is(tok::semi)) {
+  // A multi-line asm-statement, where next line is a comment
+  InAsmComment = true;
+  FID = ExpLoc.first;
+  LineNo = SrcMgr.getLineNumber(FID, ExpLoc.second);
 }
   } else if (!InAsmComment && Tok.is(tok::r_brace)) {
 // In MSVC mode, braces only participate in brace matching and


Index: cfe/trunk/test/CodeGen/ms-inline-asm.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c
@@ -55,9 +55,15 @@
 }
   }
   __asm {}
+  __asm {
+;
+; label
+mov eax, ebx
+  }
 // CHECK: t7
 // CHECK: call void asm sideeffect inteldialect "int $$0x2cU", "~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "mov eax, ebx", "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 int t8() {
Index: cfe/trunk/lib/Parse/ParseStmtAsm.cpp
===
--- cfe/trunk/lib/Parse/ParseStmtAsm.cpp
+++ cfe/trunk/lib/Parse/ParseStmtAsm.cpp
@@ -457,6 +457,11 @@
 break;
   LineNo = SrcMgr.getLineNumber(ExpLoc.first, ExpLoc.second);
   SkippedStartOfLine = Tok.isAtStartOfLine();
+} else if (Tok.is(tok::semi)) {
+  // A multi-line asm-statement, where next line is a comment
+  InAsmComment = true;
+  FID = ExpLoc.first;
+  LineNo = SrcMgr.getLineNumber(FID, ExpLoc.second);
 }
   } else if (!InAsmComment && Tok.is(tok::r_brace)) {
 // In MSVC mode, braces only participate in brace matching and
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[PATCH] D33278: [LLVM][x86][Inline Asm] - Enum support for MS syntax

2017-06-27 Thread coby via Phabricator via cfe-commits

coby added inline comments.



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1310
 }
-
-bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) 
{
+bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End,
+bool &ReplaceEnumIdentifier) {

blank line omitted



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1378
+// Check if the parsed identifier was a constant Integer. Here we
+// assume Val is of type MCConstantExpr only when it is safe to replace
+// the identifier with its constant value.

assumption ~~> assertion



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1380
+// the identifier with its constant value.
+if (const MCConstantExpr *CE =
+dyn_cast_or_null(Val)) {

I think this whole section better suites within its own function. something 
like 'ParseInlineAsmEnumValue'



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1383
+  StringRef ErrMsg;
+  // SM should treat the value as it would an explicit integer in the 
+  // expression.

rephrase



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1385
+  // expression.
+  if(SM.onInteger(CE->getValue(), ErrMsg)) 
+return Error(IdentLoc, ErrMsg);

clang format



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1388
+  // In case we are called on a bracketed expression,
+  if (isParsingInlineAsm() && SM.getAddImmPrefix()) {
+// A single rewrite of the integer value is preformed for each enum

'isParsingInlineAsm()' is unnecessary here (you can only reach this piece of 
code when parsing inline asm)



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1826
   }
-
-  // Rewrite the type operator and the C or C++ type or variable in terms of an
-  // immediate.  E.g. TYPE foo -> $$4
-  unsigned Len = End.getPointer() - TypeLoc.getPointer();
-  InstInfo->AsmRewrites->emplace_back(AOK_Imm, TypeLoc, Len, CVal);
-
+  // Only when in bracketed mode, preform explicit rewrite
+  if (AddImmPrefix) {

Not keen to the use of SM.getAddImmPrefix() as a mean of distinguish whether we 
are parsing a bracketed expression. I know it is currently turned on when 
parsing it, but it isn't asserted/guaranteed.
Regardless - I'm pretty sure we can manage without this rewrite, or at the very 
least - should, now that TYPE/LENGTH/SIZE are part of the State Machine.



Comment at: lib/Target/X86/AsmParser/X86AsmParser.cpp:1907
 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
-if (StartTok.getString().size() == Len)
-  // Just add a prefix if this wasn't a complex immediate expression.
-  InstInfo->AsmRewrites->emplace_back(AOK_ImmPrefix, Start);
-else
-  // Otherwise, rewrite the complex expression as a single immediate.
+if (StartTok.getString().size() != Len || ReplaceEnumIdentifier)
+  // Rewrite the complex expression as a single immediate.

you may just perform an AOK_Imm rewrite regardless the complexity of the 
immediate expression, and neglect 'ReplaceEnumIdentifier'


Repository:
  rL LLVM

https://reviews.llvm.org/D33278



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[PATCH] D34740: [X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the two collides

2017-06-27 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

On MS-style, the following snippet:

int eax;
__asm mov eax, ebx

should yield loading of ebx, into the location pointed by the variable eax

This patch sees to it.

Currently, a reg-to-reg move would have been invoked.

llvm: https://reviews.llvm.org/D34739


Repository:
  rL LLVM

https://reviews.llvm.org/D34740

Files:
  test/CodeGen/ms-inline-asm-var-name.c


Index: test/CodeGen/ms-inline-asm-var-name.c
===
--- test/CodeGen/ms-inline-asm-var-name.c
+++ test/CodeGen/ms-inline-asm-var-name.c
@@ -0,0 +1,12 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - 
| FileCheck %s
+
+void t() {
+  int eax;
+  int Ecx;
+  __asm mov eax, ebx
+  // CHECK: mov $0, ebx
+  __asm add ecx, Ecx
+  // CHECK: add ecx, $1
+}
+


Index: test/CodeGen/ms-inline-asm-var-name.c
===
--- test/CodeGen/ms-inline-asm-var-name.c
+++ test/CodeGen/ms-inline-asm-var-name.c
@@ -0,0 +1,12 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s
+
+void t() {
+  int eax;
+  int Ecx;
+  __asm mov eax, ebx
+  // CHECK: mov $0, ebx
+  __asm add ecx, Ecx
+  // CHECK: add ecx, $1
+}
+
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[PATCH] D35775: [x86][inline-asm]Extend support for memory reference expression

2017-07-23 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Extend support for expressions which represent a variable access in ms-style 
inline-asm, to allow the incorporation of both registers and variables.
Currently, expression such as '//__asm mov eax, [var + eax]//' would have been 
reduced to the (equivalent of) '//__asm mov eax, [eax]//'
This patch amends it
llvm counterpart: https://reviews.llvm.org/D35774


Repository:
  rL LLVM

https://reviews.llvm.org/D35775

Files:
  lib/Sema/SemaStmtAsm.cpp
  test/CodeGen/ms-inline-asm-indirect-memory-ref.c
  test/CodeGen/ms-inline-asm.c
  test/Sema/ms-inline-asm.c


Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -665,8 +665,12 @@
   fillInlineAsmTypeInfo(Context, T, Info);
 
   // We can work with the expression as long as it's not an r-value.
-  if (!Result.get()->isRValue())
+  if (!Result.get()->isRValue()) {
 Info.IsVarDecl = true;
+Expr::EvalResult Eval;
+if (Result.get()->EvaluateAsLValue(Eval, Context))
+  Info.IsGlobalLV = Eval.isGlobalLValue();
+  }
 
   return Result;
 }
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -515,7 +515,7 @@
   __asm { mov eax, 4*(4-2)[64 + arr - 2*32] }
 // CHECK: call void asm sideeffect inteldialect "mov eax, $$8$0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
   __asm { mov eax, 32*(4-2)[arr - 2*32] }
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$0$0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"([4 x i32]* %{{.*}})
 }
 
 void cpuid() {
Index: test/CodeGen/ms-inline-asm-indirect-memory-ref.c
===
--- test/CodeGen/ms-inline-asm-indirect-memory-ref.c
+++ test/CodeGen/ms-inline-asm-indirect-memory-ref.c
@@ -0,0 +1,36 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -fasm-blocks -triple x86_64-unknown-linux-gnu -emit-llvm 
-o - | FileCheck %s
+
+int gVar;
+
+void t1() {
+  // CHECK: add eax, dword ptr gVar[eax]
+  __asm add eax, dword ptr gVar[eax]
+  // CHECK: add dword ptr gVar[eax], eax
+  __asm add dword ptr [eax+gVar], eax
+  // CHECK: add ebx, dword ptr gVar[ebx + $$270]
+  __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
+  // CHECK: add dword ptr gVar[ebx + $$828], ebx
+  __asm add dword ptr [ebx + gVar + 828], ebx
+  // CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
+  __asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
+  // CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
+  __asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
+  // CHECK: add gVar[ecx + ebx + $$7], eax
+  __asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
+}
+
+void t2() {
+  int lVar;
+  // CHECK: mov eax, dword ptr ${{[0-9]}}[eax]
+  __asm mov eax, dword ptr lVar[eax]
+  // CHECK: mov dword ptr ${{[0-9]}}[eax], eax
+  __asm mov dword ptr [eax+lVar], eax
+  // CHECK: mov ebx, dword ptr ${{[0-9]}}[ebx + $$270]
+  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
+  // CHECK: mov dword ptr ${{[0-9]}}[ebx + $$828], ebx
+  __asm mov dword ptr [ebx + lVar + 828], ebx
+  // CHECK: mov ${{[0-9]}}[ebx + $$47], eax
+  __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
+}
+
Index: test/Sema/ms-inline-asm.c
===
--- test/Sema/ms-inline-asm.c
+++ test/Sema/ms-inline-asm.c
@@ -59,10 +59,8 @@
 mov eax, arr[1 + (2 * 5) - 3 + 1<<1];
   }
 
-  // expected-error@+1 {{cannot use base register with variable reference}}
-  __asm { mov eax, arr[ebp + 1 + (2 * 5) - 3 + 1<<1] }
-  // expected-error@+1 {{cannot use index register with variable reference}}
-  __asm { mov eax, arr[esi * 4] }
+  // expected-error@+1 {{Can't use a local variable with both base and index 
registers}}
+  __asm { mov eax, [i + eax + ebx] }
   // expected-error@+1 {{cannot use more than one symbol in memory operand}}
   __asm { mov eax, arr[i] }
   // expected-error@+1 {{cannot use more than one symbol in memory operand}}


Index: lib/Sema/SemaStmtAsm.cpp
===
--- lib/Sema/SemaStmtAsm.cpp
+++ lib/Sema/SemaStmtAsm.cpp
@@ -665,8 +665,12 @@
   fillInlineAsmTypeInfo(Context, T, Info);
 
   // We can work with the expression as long as it's not an r-value.
-  if (!Result.get()->isRValue())
+  if (!Result.get()->isRValue()) {
 Info.IsVarDecl = true;
+Expr::EvalResult Eval;
+if (Result.get()->EvaluateAsLValue(Eval, Context))
+  Info.IsGlobalLV = Eval.isGlobalLValue();
+  }
 
   return Result;
 }
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inli

[PATCH] D26587: [AVX512][inline-asm] Fix AVX512 inline assembly instruction resolution when the size qualifier of a memory operand is not specified explicitly.

2017-07-23 Thread coby via Phabricator via cfe-commits

coby abandoned this revision.
coby added a comment.

superseded by https://reviews.llvm.org/rL302179


Repository:
  rL LLVM

https://reviews.llvm.org/D26587



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[PATCH] D34740: [X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the two collides

2017-07-24 Thread coby via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rL308867: [X86][InlineAsm][Ms Compatibility]Prefer variable 
name over a register when the… (authored by coby).

Changed prior to commit:
  https://reviews.llvm.org/D34740?vs=104352&id=107851#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D34740

Files:
  cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c


Index: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
@@ -0,0 +1,12 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - 
| FileCheck %s
+
+void t() {
+  int eax;
+  int Ecx;
+  __asm mov eax, ebx
+  // CHECK: mov $0, ebx
+  __asm add ecx, Ecx
+  // CHECK: add ecx, $1
+}
+


Index: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
===
--- cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
+++ cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
@@ -0,0 +1,12 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s
+
+void t() {
+  int eax;
+  int Ecx;
+  __asm mov eax, ebx
+  // CHECK: mov $0, ebx
+  __asm add ecx, Ecx
+  // CHECK: add ecx, $1
+}
+
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[PATCH] D35903: [x86][inline-asm]Allow a pack of Control Regs to be properly picked

2017-07-26 Thread coby via Phabricator via cfe-commits

coby created this revision.
Herald added a subscriber: eraman.

Allows the incorporation of legit (x86) Control Regs within inline asm 
stataements


Repository:
  rL LLVM

https://reviews.llvm.org/D35903

Files:
  lib/Basic/Targets/X86.cpp
  test/CodeGen/ms-inline-asm.c


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -58,6 +58,7 @@
 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
+"cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -627,6 +627,17 @@
 // CHECK: call void asm sideeffect inteldialect "mov eax, $0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
+void t44() {
+  // CHECK-LABEL: define void @t44
+  __asm {
+mov cr0, eax
+mov cr2, ebx
+mov cr3, ecx
+mov cr4, edx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


Index: lib/Basic/Targets/X86.cpp
===
--- lib/Basic/Targets/X86.cpp
+++ lib/Basic/Targets/X86.cpp
@@ -58,6 +58,7 @@
 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
+"cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {
Index: test/CodeGen/ms-inline-asm.c
===
--- test/CodeGen/ms-inline-asm.c
+++ test/CodeGen/ms-inline-asm.c
@@ -627,6 +627,17 @@
 // CHECK: call void asm sideeffect inteldialect "mov eax, $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
+void t44() {
+  // CHECK-LABEL: define void @t44
+  __asm {
+mov cr0, eax
+mov cr2, ebx
+mov cr3, ecx
+mov cr4, edx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", "~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
 	__asm { mov eax, 3[ebx]A.b}
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[PATCH] D25717: [x86][inline-asm][clang][fixup] accept 'v' constraint

2016-11-27 Thread coby via Phabricator via cfe-commits

coby abandoned this revision.
coby added a comment.

deprecated


Repository:
  rL LLVM

https://reviews.llvm.org/D25717



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[PATCH] D32638: [x86][inline-asm][clang]Amend size directive deduction mechanism of unsized memory operands

2017-04-28 Thread coby via Phabricator via cfe-commits

coby created this revision.

This is an extension of the work being carried by the following change:
https://reviews.llvm.org/D26586
This commit handles cases where the size qualifier of an indirect memory 
reference operand in Intel syntax is missing (e.g. "vaddps xmm1, xmm2, [a]").
GCC will deduce the size qualifier based on the possible matches:
"vaddps xmm1, xmm2, [a]" matches only “XMMWORD PTR” qualifier.
"vaddps xmm1, xmm2, [a]{1to4}" matches only “DWORD PTR” qualifier.
"mov rax, [a]" matches only "QWORD PTR"

Currently, size directive will be deduced based on the size of the memory 
operand (apart from those cases which were handled by 
https://reviews.llvm.org/D26586).
For example:
"vaddps xmm1, xmm2, [a]"
"char a;" will imply "BYTE PTR" qualifier
"short a;" will imply "WORD PTR" qualifier.

This commit aligns LLVM to GCC’s behavior.

This is the Clang part of the review.
The LLVM part can be found here:
https://reviews.llvm.org/D32636


Repository:
  rL LLVM

https://reviews.llvm.org/D32638

Files:
  test/CodeGen/ms-inline-asm-memory-adjustments.c


Index: test/CodeGen/ms-inline-asm-memory-adjustments.c
===
--- test/CodeGen/ms-inline-asm-memory-adjustments.c
+++ test/CodeGen/ms-inline-asm-memory-adjustments.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu 
skylake-avx512 -fasm-blocks -o - | FileCheck %s
+
+void t() {
+  char c;
+  // CHECK: vaddps xmm1, xmm2, dword ptr $1{1to4}
+  __asm vaddps xmm1, xmm2, [c]{1to4}
+  // CHECK: vaddps xmm1, xmm2, xmmword ptr $2
+  __asm vaddps xmm1, xmm2, [c]
+  // CHECK: mov eax, dword ptr $3
+  __asm mov eax, [c]
+  // CHECK: mov qword ptr $0, rax
+  __asm mov [c], rax
+}
+


Index: test/CodeGen/ms-inline-asm-memory-adjustments.c
===
--- test/CodeGen/ms-inline-asm-memory-adjustments.c
+++ test/CodeGen/ms-inline-asm-memory-adjustments.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu skylake-avx512 -fasm-blocks -o - | FileCheck %s
+
+void t() {
+  char c;
+  // CHECK: vaddps xmm1, xmm2, dword ptr $1{1to4}
+  __asm vaddps xmm1, xmm2, [c]{1to4}
+  // CHECK: vaddps xmm1, xmm2, xmmword ptr $2
+  __asm vaddps xmm1, xmm2, [c]
+  // CHECK: mov eax, dword ptr $3
+  __asm mov eax, [c]
+  // CHECK: mov qword ptr $0, rax
+  __asm mov [c], rax
+}
+
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