[clang] [llvm] [RISCV] Add processor definition for Spacemit-K1 (PR #94564)

2024-06-05 Thread Zhijin Zeng via cfe-commits 

zengdage wrote:

> Spacemit K1 is the name of the product/SoC or whatever you call it. The 
> processor definitions in the RISCV backend are focusing on the CPU core. For 
> Spacemit K1, the name of its core should be `X60`? I don't know……

@sunshaoce Hi, the `Spacemit-K1` is the SoC name and the cpu core name is 
`spacemit-x60`, so I suggest to use `spacemit-x60`.

https://github.com/llvm/llvm-project/pull/94564
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[clang] [CodeGen] Apply 'readonly' to 'this' pointer argument. (PR #106499)

2024-08-29 Thread Zhijin Zeng via cfe-commits 

zengdage wrote:

Sorry, I misunderstand the 'readonly' meaning. So this pr is wrong.

https://github.com/llvm/llvm-project/pull/106499
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[clang] [CodeGen] Apply 'readonly' to 'this' pointer argument. (PR #106499)

2024-08-29 Thread Zhijin Zeng via cfe-commits 

https://github.com/zengdage closed 
https://github.com/llvm/llvm-project/pull/106499
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[clang] [CodeGen] Apply 'readonly' to 'this' pointer argument. (PR #106499)

2024-08-29 Thread Zhijin Zeng via cfe-commits 

zengdage wrote:

@nikic @ChuanqiXu9 I am sorry to bother you again. Do you think the attribute 
'nofree' should be added to 'this' pointer argument  in c++ instance method ?  
I think the 'this' pointer pointed to current object and it's life time is 
guaranteed to be longer than the instance method's lifetime.  If can, we can 
add `hasNoFreeAttr` check for 'Argument' case in `Value::canBeFreed`.

https://github.com/llvm/llvm-project/pull/106499
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[clang] [CodeGen] Apply 'readonly' to 'this' pointer argument. (PR #106499)

2024-08-29 Thread Zhijin Zeng via cfe-commits 

https://github.com/zengdage reopened 
https://github.com/llvm/llvm-project/pull/106499
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[clang] [CodeGen] Apply 'nofree' to 'this' pointer argument. (PR #106499)

2024-08-29 Thread Zhijin Zeng via cfe-commits 

https://github.com/zengdage edited 
https://github.com/llvm/llvm-project/pull/106499
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[clang] [llvm] [TargetLibraryInfo] Add libmvec support for risc-v (PR #119844)

2024-12-13 Thread Zhijin Zeng via cfe-commits 

https://github.com/zengdage created 
https://github.com/llvm/llvm-project/pull/119844

1. Rename LIBMVEC_X86 into LIBMVEC to support libmvec (glibc vector match 
library) in risc-v.
2. Add RVVM1/2/4/8 in VFISAKind to distingusih the LMUL value, so we can take 
full advantage of  risc-v vector extension.
3. Declare some RVV vector math functions in VecFuncs.def.

In VecFuncs.def, I add the LI_DEFINE_VECFUNC of LIBMVEC_RVV as follow:

```
TLI_DEFINE_VECFUNC("sin", "_ZGV1Nxv_sin", SCALABLE(1), "_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("sin", "_ZGV2Nxv_sin", SCALABLE(2), "_ZGVr2Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV1Nxv_expf", SCALABLE(2), 
"_ZGVr1Nxv")
TLI_DEFINE_VECFUNC("llvm.exp.f32", "_ZGV2Nxv_expf", SCALABLE(4), 
"_ZGVr2Nxv")
```

The `VEC` of TLI_DEFINE_VECFUNC (e.g., `_ZGV2Nxv_sin`), its name mangling rules 
defined in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/455 . Now 
it's  still under review.

The` VF` (e.g., ` SCALABLE(2)`) should be `vscale x (LMUL * 64 / sizeof(Type)`. 
For example, the type of the parameter of sin is double, so for `_ZGV2Nxv_sin`, 
its VF is `vscale x 2`.

In the `VABI_PREFIX`  (e.g., `_ZGVr1Nxv`), `r` means RISC-V vector extension, 
`1` is LMUL value.
```
_ZGVr1Nxv  --> RISC-V Vector Extension with LMUL=1
_ZGVr2Nxv  --> RISC-V Vector Extension with LMUL=2
_ZGVr4Nxv  --> RISC-V Vector Extension with LMUL=4
_ZGVr8Nxv  --> RISC-V Vector Extension with LMUL=8

```


>From 101d7cb3749f0e3d892a7bf0bf797e40a334882f Mon Sep 17 00:00:00 2001
From: Zhijin Zeng 
Date: Thu, 12 Dec 2024 11:42:32 +0800
Subject: [PATCH 1/2] [NFC] Add vector call tests if use vector-library in
 risc-v

---
 .../LoopVectorize/RISCV/libm-vector-calls.ll  | 415 ++
 1 file changed, 415 insertions(+)
 create mode 100644 
llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll

diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll 
b/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll
new file mode 100644
index 00..75fdd00e25f988
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll
@@ -0,0 +1,415 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 5
+; RUN: opt -mtriple=riscv64 -mattr=+v -vector-library=LIBMVEC-X86 
-passes=inject-tli-mappings,loop-vectorize -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux-gnu"
+
+define void @sin_f64(ptr nocapture %varray) {
+; CHECK-LABEL: define void @sin_f64(
+; CHECK-SAME: ptr nocapture [[VARRAY:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:   [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK:   [[VECTOR_BODY]]:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:[[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:[[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT:[[TMP11:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = sitofp <4 x i32> [[VEC_IND]] to <4 x double>
+; CHECK-NEXT:[[TMP2:%.*]] = sitofp <4 x i32> [[STEP_ADD]] to <4 x double>
+; CHECK-NEXT:[[TMP3:%.*]] = call <4 x double> @_ZGVdN4v_sin(<4 x double> 
[[TMP1]])
+; CHECK-NEXT:[[TMP4:%.*]] = call <4 x double> @_ZGVdN4v_sin(<4 x double> 
[[TMP2]])
+; CHECK-NEXT:[[TMP14:%.*]] = getelementptr inbounds double, ptr 
[[VARRAY]], i64 [[TMP11]]
+; CHECK-NEXT:[[TMP15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], 
i32 0
+; CHECK-NEXT:[[TMP7:%.*]] = getelementptr inbounds double, ptr [[TMP14]], 
i32 4
+; CHECK-NEXT:store <4 x double> [[TMP3]], ptr [[TMP15]], align 4
+; CHECK-NEXT:store <4 x double> [[TMP4]], ptr [[TMP7]], align 4
+; CHECK-NEXT:[[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-NEXT:[[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)
+; CHECK-NEXT:[[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
+; CHECK-NEXT:br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label 
%[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:   [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:br i1 true, label %[[FOR_END:.*]], label %[[SCALAR_PH]]
+; CHECK:   [[SCALAR_PH]]:
+; CHECK-NEXT:[[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, %[[MIDDLE_BLOCK]] ], 
[ 0, %[[ENTRY]] ]
+; CHECK-NEXT:br label %[[FOR_BODY:.*]]
+; CHECK:   [[FOR_BODY]]:
+; CHECK-NEXT:[[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ 
[[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT:[[TMP:%.*]] = trunc i64 [[IV]] to i32
+; CHECK-NEXT:[[CONV:%.*]] = sitofp i32 [[TMP]] to double
+; CHECK-NEXT:[[CALL:%.*]] = tail call double @sin(double [[CONV]]) 
#[[ATTR3:[0-9]+]]
+; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds dou

[clang] [llvm] [TargetLibraryInfo] Add libmvec support for risc-v (PR #119844)

2024-12-13 Thread Zhijin Zeng via cfe-commits 

https://github.com/zengdage updated 
https://github.com/llvm/llvm-project/pull/119844

>From 101d7cb3749f0e3d892a7bf0bf797e40a334882f Mon Sep 17 00:00:00 2001
From: Zhijin Zeng 
Date: Thu, 12 Dec 2024 11:42:32 +0800
Subject: [PATCH 1/2] [NFC] Add vector call tests if use vector-library in
 risc-v

---
 .../LoopVectorize/RISCV/libm-vector-calls.ll  | 415 ++
 1 file changed, 415 insertions(+)
 create mode 100644 
llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll

diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll 
b/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll
new file mode 100644
index 00..75fdd00e25f988
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/libm-vector-calls.ll
@@ -0,0 +1,415 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 
UTC_ARGS: --version 5
+; RUN: opt -mtriple=riscv64 -mattr=+v -vector-library=LIBMVEC-X86 
-passes=inject-tli-mappings,loop-vectorize -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
+target triple = "riscv64-unknown-linux-gnu"
+
+define void @sin_f64(ptr nocapture %varray) {
+; CHECK-LABEL: define void @sin_f64(
+; CHECK-SAME: ptr nocapture [[VARRAY:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:   [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK:   [[VECTOR_BODY]]:
+; CHECK-NEXT:[[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ 
[[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:[[VEC_IND:%.*]] = phi <4 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:[[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT:[[TMP11:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:[[TMP1:%.*]] = sitofp <4 x i32> [[VEC_IND]] to <4 x double>
+; CHECK-NEXT:[[TMP2:%.*]] = sitofp <4 x i32> [[STEP_ADD]] to <4 x double>
+; CHECK-NEXT:[[TMP3:%.*]] = call <4 x double> @_ZGVdN4v_sin(<4 x double> 
[[TMP1]])
+; CHECK-NEXT:[[TMP4:%.*]] = call <4 x double> @_ZGVdN4v_sin(<4 x double> 
[[TMP2]])
+; CHECK-NEXT:[[TMP14:%.*]] = getelementptr inbounds double, ptr 
[[VARRAY]], i64 [[TMP11]]
+; CHECK-NEXT:[[TMP15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], 
i32 0
+; CHECK-NEXT:[[TMP7:%.*]] = getelementptr inbounds double, ptr [[TMP14]], 
i32 4
+; CHECK-NEXT:store <4 x double> [[TMP3]], ptr [[TMP15]], align 4
+; CHECK-NEXT:store <4 x double> [[TMP4]], ptr [[TMP7]], align 4
+; CHECK-NEXT:[[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
+; CHECK-NEXT:[[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4)
+; CHECK-NEXT:[[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000
+; CHECK-NEXT:br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label 
%[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:   [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:br i1 true, label %[[FOR_END:.*]], label %[[SCALAR_PH]]
+; CHECK:   [[SCALAR_PH]]:
+; CHECK-NEXT:[[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, %[[MIDDLE_BLOCK]] ], 
[ 0, %[[ENTRY]] ]
+; CHECK-NEXT:br label %[[FOR_BODY:.*]]
+; CHECK:   [[FOR_BODY]]:
+; CHECK-NEXT:[[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ 
[[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT:[[TMP:%.*]] = trunc i64 [[IV]] to i32
+; CHECK-NEXT:[[CONV:%.*]] = sitofp i32 [[TMP]] to double
+; CHECK-NEXT:[[CALL:%.*]] = tail call double @sin(double [[CONV]]) 
#[[ATTR3:[0-9]+]]
+; CHECK-NEXT:[[ARRAYIDX:%.*]] = getelementptr inbounds double, ptr 
[[VARRAY]], i64 [[IV]]
+; CHECK-NEXT:store double [[CALL]], ptr [[ARRAYIDX]], align 4
+; CHECK-NEXT:[[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT:[[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
+; CHECK-NEXT:br i1 [[EXITCOND]], label %[[FOR_END]], label %[[FOR_BODY]], 
!llvm.loop [[LOOP3:![0-9]+]]
+; CHECK:   [[FOR_END]]:
+; CHECK-NEXT:ret void
+;
+entry:
+  br label %for.body
+
+for.body:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+  %tmp = trunc i64 %iv to i32
+  %conv = sitofp i32 %tmp to double
+  %call = tail call double @sin(double %conv)
+  %arrayidx = getelementptr inbounds double, ptr %varray, i64 %iv
+  store double %call, ptr %arrayidx, align 4
+  %iv.next = add nuw nsw i64 %iv, 1
+  %exitcond = icmp eq i64 %iv.next, 1000
+  br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !1
+
+for.end:
+  ret void
+}
+
+!1 = distinct !{!1, !2}
+!2 = !{!"llvm.loop.vectorize.enable", i1 true}
+
+
+define void @sin_f64_intrinsic(ptr nocapture %varray) {
+; CHECK-LABEL: define void @sin_f64_intrinsic(
+; CHECK-SAME: ptr nocapture [[VARRAY:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:   [[VECTOR_PH]]:
+; CHECK-NEXT:br label %[[VECTOR_BODY:.*]]
+; CHECK:   [[VECTOR_BODY]]:
+; CHECK-NEXT:

[clang] [llvm] [TargetLibraryInfo] Add libmvec support for risc-v (PR #119844)

2024-12-13 Thread Zhijin Zeng via cfe-commits 

zengdage wrote:

@mga-sc Hi, can you help to review the pr? I add RVVM1/2/4/8 in VFISAKind to 
support multiple LMUL value, maybe it can take full advantage of rvv register 
group. Your pr (https://github.com/llvm/llvm-project/pull/114014) looks like 
just support LMUL=2.

https://github.com/llvm/llvm-project/pull/119844
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