[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
poemonsense wrote: > LGTM in general, except one question: will zicbom and zicboz be in the final > RTL? Yes, it's in the final RTL. https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
poemonsense wrote: > @dtcxzyw Could you please confirm the status of this core - is it > commercially available, an academic test chip, something else? It's maintained by Beijing Institute of Open Source Chip (BOSC), a non-profit organziation founded by companies and researech institutions. It is provided as an open-source CPU Core IP to the third party. It's not an academic testchip. It's not commercially available now, but there have already been a couple of companies using it as the CPU Core IP. I cannot disclose the progress of commercial chips now but hopefully we will see it soon. There are also some companies using it on FPGAs now. https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add processor definition for XiangShan-NanHu (PR #70294)
poemonsense wrote: > Please update the official document then. :-) I'll do it. We did not list it previously because it is not the usual thing for user programs, as we were initially implementing it for internal usage. Sorry for causing the confusion. https://github.com/llvm/llvm-project/pull/70294 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
