[clang] [llvm] [RISCV] Add support for getHostCPUFeatures using hwprobe (PR #94352)

[Yangyu Chen via cfe-commits]

@@ -2002,6 +2003,76 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
 
   return true;
 }
+#elif defined(__linux__) && defined(__riscv)
+// struct riscv_hwprobe
+struct RISCVHwProbe {
+  int64_t Key;
+  uint64_t Value;
+};
+bool sys::getHostCPUFeatures(StringMap &Features) {
+  RISCVHwProbe Query[]{{/*RISCV_HWPROBE_KEY_BASE_BEHAVIOR=*/3, 0},
+   {/*RISCV_HWPROBE_KEY_IMA_EXT_0=*/4, 0}};
+  int Ret = syscall(/*__NR_riscv_hwprobe=*/258, /*pairs=*/Query,
+/*pair_count=*/std::size(Query), /*cpu_count=*/0,
+/*cpus=*/0, /*flags=*/0);
+  if (Ret != 0)
+return false;
+
+  uint64_t BaseMask = Query[0].Value;
+  // Check whether RISCV_HWPROBE_BASE_BEHAVIOR_IMA is set.
+  if (BaseMask & 1) {
+Features["i"] = true;
+Features["m"] = true;
+Features["a"] = true;
+  }
+
+  uint64_t ExtMask = Query[1].Value;

cyyself wrote:

I think this is not safe. The minimal ISA for RISC-V Linux is IMA. If someone 
modified the kernel to run on some CPUs without M or A extension(theoretically 
A can be replaced with Zalrsc), the base behavior probe will be zero but it 
doesn’t mean we have IMA.

https://github.com/llvm/llvm-project/pull/94352
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for SpacemiT-X60 (PR #94564)

[Yangyu Chen via cfe-commits]

cyyself wrote:

I have a question: SpacemiT-X60 does not support Zicclsm on Vector, which is 
the same as K230, as discussed in #88029 . Is the Zicclsm safe here?

https://github.com/llvm/llvm-project/pull/94564
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Support `norelax` attribute for RISCV (PR #115981)

[Yangyu Chen via cfe-commits]

cyyself wrote:

> I disagree that this is a thing which should exist. It's solving the problem 
> in the wrong place.

Since a clean solution needs GLIBC update, I think this can be a workaround now 
for some generated IFUNC resolvers, such as target_clones or target_versions.

https://github.com/llvm/llvm-project/pull/115981
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Support `norelax` attribute for RISCV (PR #115981)

[Yangyu Chen via cfe-commits]

cyyself wrote:

> Two comments:
> 
> * I don't think the c-api-doc change is going to be accepted at this rate

I agree. I also changed my mind now through the discussion from the c-api-doc 
PR.


https://github.com/llvm/llvm-project/pull/115981
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add processor definition for XiangShan-KunMingHu-V2R2 (PR #123193)

[Yangyu Chen via cfe-commits]

cyyself wrote:

I think some feature is missing here, such as "Zvbb".

https://github.com/llvm/llvm-project/pull/123193
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits