[PATCH] D140527: [LoongArch] Add intrinsics for CACOP instruction

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
XiaodongLoong requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

The CACOP instruction is mainly used for cache initialization
and cache-consistency maintenance.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140527

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/Driver/loongarch-default-features.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
@@ -42,6 +43,15 @@
   ret i32 %res
 }
 
+define void @cacop_d(i64 %a) nounwind {
+; CHECK-LABEL: cacop_d:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4)
+  ret void
+}
+
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
@@ -46,3 +48,37 @@
   %0 = call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 -1)
   ret i64 %0
 }
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK: llvm.loongarch.cacop.w requires target: loongarch32
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
+
+define void @cacop_arg0_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 32, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg0_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 -1, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg2_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4096)
+  ret void
+}
+
+define void @cacop_arg2_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 -4096)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK-LABEL: cacop_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,5 +1,6 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
 decla

[PATCH] D139686: [lsan] Add lsan support for loongarch64

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong added a comment.

Please rebase code for test errors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139686/new/

https://reviews.llvm.org/D139686

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D140685: [LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
XiaodongLoong requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Instruction formats:
`movgr2fcsr fcsr, rj`
`movfcsr2gr rd, fcsr`
MOVGR2FCSR modifies the value of the software writable field
corresponding to the FCSR (floating-point control and status
register) `fcsr` according to the value of the lower 32 bits of
the GR (general purpose register) `rj`.
MOVFCSR2GR sign extends the 32-bit value of the FCSR `fcsr`
and writes it into the GR `rd`.

Add "i32 @llvm.loongarch.movfcsr2gr(i32)" intrinsic for MOVFCSR2GR
instruction. The argument is FCSR register number. The return value
is the value in the FCSR.
Add "void @llvm.loongarch.movgr2fcsr(i32, i32)" intrinsic for MOVGR2FCSR
instruction. The first argument is the FCSR number, the second argument
is the value in GR.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140685

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
@@ -47,6 +49,26 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK-LABEL: movgr2fcsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movgr2fcsr $fcsr1, $a0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK-LABEL: movfcsr2gr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movfcsr2gr $a0, $fcsr1
+; CHECK-NEXT:ret
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
 define void @syscall() nounwind {
 ; CHECK-LABEL: syscall:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -4,6 +4,8 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_not_constant(i32 %x) nounwind {
@@ -27,6 +29,20 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 %a, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 %a)
+  ret i32 %res
+}
+
 define void @syscall(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -5,105 +5,151 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loonga

[PATCH] D140685: [LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong updated this revision to Diff 485593.
XiaodongLoong marked an inline comment as done.
XiaodongLoong added a comment.

rebase code and change code for @xen0n's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140685/new/

https://reviews.llvm.org/D140685

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
@@ -47,6 +49,26 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK-LABEL: movgr2fcsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movgr2fcsr $fcsr1, $a0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK-LABEL: movfcsr2gr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movfcsr2gr $a0, $fcsr1
+; CHECK-NEXT:ret
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
 define void @syscall() nounwind {
 ; CHECK-LABEL: syscall:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -4,6 +4,8 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_not_constant(i32 %x) nounwind {
@@ -27,6 +29,20 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 %a, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 %a)
+  ret i32 %res
+}
+
 define void @syscall(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -5,105 +5,151 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
-define void @dbar_imm_out_of_hi_range() nounwind {
+define void @dbar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
-define void @dbar_imm_out_of_lo_range() nounwind {
+define void @dbar_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 -1)
   ret void
 }
 
-define void @ibar_imm_out_of_hi_range() nounwind {
+define void @ibar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.ibar' out of range
 entry:
 

[PATCH] D140685: [LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong added a comment.

@xen0n Thanks for your suggestion.




Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td:53
+SDTCisVT<1, GRLenVT>]>;
+def SDT_LoongArchFCSR2GR : SDTypeProfile<1, 1, [SDTCisVT<0, GRLenVT>,
+SDTCisVT<1, i32>]>;

xen0n wrote:
> Be consistent with the surrounding code and spell out the instruction 
> mnemonic fully? Like `SDT_LoongArchMovfcsr2gr`?
Thanks, I changed that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140685/new/

https://reviews.llvm.org/D140685

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D140527: [LoongArch] Add intrinsics for CACOP instruction

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong added a comment.

ping.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140527/new/

https://reviews.llvm.org/D140527

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D140685: [LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong updated this revision to Diff 485921.
XiaodongLoong added a comment.

rebase code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140685/new/

https://reviews.llvm.org/D140685

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
@@ -47,6 +49,26 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK-LABEL: movgr2fcsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movgr2fcsr $fcsr1, $a0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK-LABEL: movfcsr2gr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movfcsr2gr $a0, $fcsr1
+; CHECK-NEXT:ret
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
 define void @syscall() nounwind {
 ; CHECK-LABEL: syscall:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -4,6 +4,8 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_not_constant(i32 %x) nounwind {
@@ -27,6 +29,20 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 %a, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 %a)
+  ret i32 %res
+}
+
 define void @syscall(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -5,105 +5,151 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
-define void @dbar_imm_out_of_hi_range() nounwind {
+define void @dbar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
-define void @dbar_imm_out_of_lo_range() nounwind {
+define void @dbar_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 -1)
   ret void
 }
 
-define void @ibar_imm_out_of_hi_range() nounwind {
+define void @ibar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.ibar' out of range
 entry:
   call void @llvm.loongarch.ibar(i32 32769)
   ret void
 }
 
-define void @ibar_imm_ou

[PATCH] D140685: [LoongArch] Add intrinsics for MOVFCSR2GR and MOVGR2FCSR instructions

[Xiaodong Liu via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG63d46869ea57: [LoongArch] Add intrinsics for MOVFCSR2GR and 
MOVGR2FCSR instructions (authored by XiaodongLoong).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140685/new/

https://reviews.llvm.org/D140685

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -1,10 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+f < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+f < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
@@ -47,6 +49,26 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK-LABEL: movgr2fcsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movgr2fcsr $fcsr1, $a0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr() nounwind {
+; CHECK-LABEL: movfcsr2gr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:movfcsr2gr $a0, $fcsr1
+; CHECK-NEXT:ret
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
+  ret i32 %res
+}
+
 define void @syscall() nounwind {
 ; CHECK-LABEL: syscall:
 ; CHECK:   # %bb.0: # %entry
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -4,6 +4,8 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_not_constant(i32 %x) nounwind {
@@ -27,6 +29,20 @@
   ret void
 }
 
+define void @movgr2fcsr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.movgr2fcsr(i32 %a, i32 %a)
+  ret void
+}
+
+define i32 @movfcsr2gr(i32 %a) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  %res = call i32 @llvm.loongarch.movfcsr2gr(i32 %a)
+  ret i32 %res
+}
+
 define void @syscall(i32 %x) nounwind {
 ; CHECK: immarg operand has non-immediate parameter
 entry:
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -5,105 +5,151 @@
 declare void @llvm.loongarch.dbar(i32)
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.movgr2fcsr(i32, i32)
+declare i32 @llvm.loongarch.movfcsr2gr(i32)
 declare void @llvm.loongarch.syscall(i32)
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
-define void @dbar_imm_out_of_hi_range() nounwind {
+define void @dbar_imm_out_of_hi_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
-define void @dbar_imm_out_of_lo_range() nounwind {
+define void @dbar_imm_out_of_lo_range() #0 {
 ; CHECK: argument to 'llvm.loongarch.dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 -1)
   ret void
 }
 
-define void @ibar_imm_out_of_hi_range() nounwind {
+define void @ibar_imm_out_of_hi_

[PATCH] D140527: [LoongArch] Add intrinsics for CACOP instruction

[Xiaodong Liu via Phabricator via cfe-commits]

XiaodongLoong updated this revision to Diff 486725.
XiaodongLoong added a comment.

rebase code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140527/new/

https://reviews.llvm.org/D140527

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/Driver/loongarch-default-features.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
@@ -46,6 +47,15 @@
   ret i32 %res
 }
 
+define void @cacop_d(i64 %a) nounwind {
+; CHECK-LABEL: cacop_d:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4)
+  ret void
+}
+
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
@@ -46,3 +48,37 @@
   %0 = call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 -1)
   ret i64 %0
 }
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK: llvm.loongarch.cacop.w requires target: loongarch32
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
+
+define void @cacop_arg0_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 32, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg0_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 -1, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg2_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4096)
+  ret void
+}
+
+define void @cacop_arg2_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 -4096)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK-LABEL: cacop_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,5 +1,6 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
@@ -18,6 +19,34 @@
 declare i64 @ll

[PATCH] D140527: [LoongArch] Add intrinsics for CACOP instruction

[Xiaodong Liu via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9e06d18c80e7: [LoongArch] Add intrinsics for CACOP 
instruction (authored by XiaodongLoong).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140527/new/

https://reviews.llvm.org/D140527

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/Driver/loongarch-default-features.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
@@ -46,6 +47,15 @@
   ret i32 %res
 }
 
+define void @cacop_d(i64 %a) nounwind {
+; CHECK-LABEL: cacop_d:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4)
+  ret void
+}
+
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
 ; CHECK:   # %bb.0:
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+declare void @llvm.loongarch.cacop.d(i64, i64, i64)
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
@@ -46,3 +48,37 @@
   %0 = call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 -1)
   ret i64 %0
 }
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK: llvm.loongarch.cacop.w requires target: loongarch32
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
+
+define void @cacop_arg0_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 32, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg0_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 -1, i64 %a, i64 1024)
+  ret void
+}
+
+define void @cacop_arg2_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4096)
+  ret void
+}
+
+define void @cacop_arg2_out_of_lo_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+entry:
+  call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 -4096)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
+
+define void @cacop_w(i32 %a) nounwind {
+; CHECK-LABEL: cacop_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:cacop 1, $a0, 4
+; CHECK-NEXT:ret
+  call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,5 +1,6 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.cacop.w(i32, i32, i32)
 declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.h.w(i32, i