[clang] 4954449 - [Driver][X86] Support branch align options with LTO
Author: Shengchen Kan
Date: 2020-05-28T13:17:14+08:00
New Revision: 49544499954912c5a0f02014de53e0bc0234c7af
URL:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af
DIFF:
https://github.com/llvm/llvm-project/commit/49544499954912c5a0f02014de53e0bc0234c7af.diff
LOG: [Driver][X86] Support branch align options with LTO
Summary: Before this patch, we use two different ways to pass options to align
branch
depending on whether LTO is enabled. For example,
`-mbranches-within-32B-boundaries`
w/o LTO and `-Wl,-plugin-opt=-x86-branches-within-32B-boundaries` w/ LTO. It's
inconvenient, so this patch unifies the way: we only need to pass options like
`-mbranches-within-32B-boundaries` to align branches, no matter LTO is enabled
or not.
Differential Revision: https://reviews.llvm.org/D80289
Added:
Modified:
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/CommonArgs.cpp
clang/lib/Driver/ToolChains/CommonArgs.h
clang/test/Driver/x86-malign-branch.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index f33983db3e1e..dd83cafb2748 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2045,57 +2045,10 @@ void Clang::AddSystemZTargetArgs(const ArgList &Args,
}
}
-static void addX86AlignBranchArgs(const Driver &D, const ArgList &Args,
- ArgStringList &CmdArgs) {
- if (Args.hasArg(options::OPT_mbranches_within_32B_boundaries)) {
-CmdArgs.push_back("-mllvm");
-CmdArgs.push_back("-x86-branches-within-32B-boundaries");
- }
- if (const Arg *A = Args.getLastArg(options::OPT_malign_branch_boundary_EQ)) {
-StringRef Value = A->getValue();
-unsigned Boundary;
-if (Value.getAsInteger(10, Boundary) || Boundary < 16 ||
-!llvm::isPowerOf2_64(Boundary)) {
- D.Diag(diag::err_drv_invalid_argument_to_option)
- << Value << A->getOption().getName();
-} else {
- CmdArgs.push_back("-mllvm");
- CmdArgs.push_back(
- Args.MakeArgString("-x86-align-branch-boundary=" + Twine(Boundary)));
-}
- }
- if (const Arg *A = Args.getLastArg(options::OPT_malign_branch_EQ)) {
-std::string AlignBranch;
-for (StringRef T : A->getValues()) {
- if (T != "fused" && T != "jcc" && T != "jmp" && T != "call" &&
- T != "ret" && T != "indirect")
-D.Diag(diag::err_drv_invalid_malign_branch_EQ)
-<< T << "fused, jcc, jmp, call, ret, indirect";
- if (!AlignBranch.empty())
-AlignBranch += '+';
- AlignBranch += T;
-}
-CmdArgs.push_back("-mllvm");
-CmdArgs.push_back(Args.MakeArgString("-x86-align-branch=" + AlignBranch));
- }
- if (const Arg *A = Args.getLastArg(options::OPT_mpad_max_prefix_size_EQ)) {
-StringRef Value = A->getValue();
-unsigned PrefixSize;
-if (Value.getAsInteger(10, PrefixSize)) {
- D.Diag(diag::err_drv_invalid_argument_to_option)
- << Value << A->getOption().getName();
-} else {
- CmdArgs.push_back("-mllvm");
- CmdArgs.push_back(
- Args.MakeArgString("-x86-pad-max-prefix-size=" + Twine(PrefixSize)));
-}
- }
-}
-
void Clang::AddX86TargetArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
const Driver &D = getToolChain().getDriver();
- addX86AlignBranchArgs(D, Args, CmdArgs);
+ addX86AlignBranchArgs(D, Args, CmdArgs, /*IsLTO=*/false);
if (!Args.hasFlag(options::OPT_mred_zone, options::OPT_mno_red_zone, true) ||
Args.hasArg(options::OPT_mkernel) ||
@@ -6745,7 +6698,8 @@ void ClangAs::AddMIPSTargetArgs(const ArgList &Args,
void ClangAs::AddX86TargetArgs(const ArgList &Args,
ArgStringList &CmdArgs) const {
- addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs);
+ addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
+/*IsLTO=*/false);
if (Arg *A = Args.getLastArg(options::OPT_masm_EQ)) {
StringRef Value = A->getValue();
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index 85a1a4e1ac07..33c43222b5f9 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -358,6 +358,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const
ArgList &Args,
ArgStringList &CmdArgs, const InputInfo &Output,
const InputInfo &Input, bool IsThinLTO) {
const char *Linker = Args.MakeArgString(ToolChain.GetLinkerPath());
+ const Driver &D = ToolChain.getDriver();
if (llvm::sys::path::filename(Linker) != "ld.lld" &&
llvm::sys::path::stem(Linker) != "ld.lld") {
// Tell the linker to load the plugin. This has to come before
@@ -374,10 +375,9 @@ void tools::ad
[clang] ac47588 - [Driver] Add negative option for -fkeep-static-consts
Author: Shengchen Kan
Date: 2020-06-03T14:59:14+08:00
New Revision: ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
URL:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c
DIFF:
https://github.com/llvm/llvm-project/commit/ac47588bc4ff5927a01ed6fcd269ce86aba52a7c.diff
LOG: [Driver] Add negative option for -fkeep-static-consts
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Clang.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index b807febe1d44..05a9121592ef 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -988,8 +988,7 @@ def fsignaling_math : Flag<["-"], "fsignaling-math">,
Group;
def fno_signaling_math : Flag<["-"], "fno-signaling-math">, Group;
defm jump_tables : OptOutFFlag<"jump-tables", "Use", "Do not use", " jump
tables for lowering switches">;
defm force_enable_int128 : OptInFFlag<"force-enable-int128", "Enable",
"Disable", " support for int128_t type">;
-def fkeep_static_consts : Flag<["-"], "fkeep-static-consts">, Group,
Flags<[CC1Option]>,
- HelpText<"Keep static const variables even if unused">;
+defm keep_static_consts : OptInFFlag<"keep-static-consts", "Keep", "Don't
keep", " static const variables if unused", [DriverOption]>;
def ffixed_point : Flag<["-"], "ffixed-point">, Group,
Flags<[CC1Option]>, HelpText<"Enable fixed point types">;
def fno_fixed_point : Flag<["-"], "fno-fixed-point">, Group,
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index d86fe499d69e..b20048768e44 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -5175,7 +5175,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
Args.AddLastArg(CmdArgs, options::OPT_fno_operator_names);
Args.AddLastArg(CmdArgs, options::OPT_femulated_tls,
options::OPT_fno_emulated_tls);
- Args.AddLastArg(CmdArgs, options::OPT_fkeep_static_consts);
// AltiVec-like language extensions aren't relevant for assembling.
if (!isa(JA) || Output.getType() != types::TY_PP_Asm)
@@ -6118,6 +6117,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
CmdArgs.push_back("-fforce-enable-int128");
}
+ if (Args.hasFlag(options::OPT_fkeep_static_consts,
+ options::OPT_fno_keep_static_consts, false))
+CmdArgs.push_back("-fkeep-static-consts");
+
if (Args.hasFlag(options::OPT_fcomplete_member_pointers,
options::OPT_fno_complete_member_pointers, false))
CmdArgs.push_back("-fcomplete-member-pointers");
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[clang] 792b109 - [Driver][X86] Add -mpad-max-prefix-size
Author: Shengchen Kan
Date: 2020-04-09T19:34:12+08:00
New Revision: 792b10978dfdd424721fbf0ffd99c35d628f2321
URL:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321
DIFF:
https://github.com/llvm/llvm-project/commit/792b10978dfdd424721fbf0ffd99c35d628f2321.diff
LOG: [Driver][X86] Add -mpad-max-prefix-size
Summary:
The option `-mpad-max-prefix-size` performs some checking and delegate to MC
option `-x86-pad-max-prefix-size`. This option is designed for eliminate NOPs
when we need to align something by adding redundant prefixes to instructions,
e.g. it can be used along with `-malign-branch`, `-malign-branch-boundary` to
prefix padding branch.
It has similar (but slightly different) effect as GAS's option
`-malign-branch-prefix-size`, e.g. `-mpad-max-prefix-size` can also elminate
NOPs emitted by align directive, so we use a different name here. I remove the
option `-malign-branch-prefix-size` since is unimplemented and not needed. If
we need to be compatible with GAS, we can make `-malign-branch-prefix-size` an
alias for this option later.
Reviewers: jyknight, reames, MaskRay, craig.topper, LuoYuanke
Reviewed By: MaskRay, LuoYuanke
Subscribers: annita.zhang, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77628
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/Driver/x86-malign-branch.c
clang/test/Driver/x86-malign-branch.s
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 430e7292757e..a395b680eb88 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2187,7 +2187,8 @@ def malign_branch_EQ : CommaJoined<["-"],
"malign-branch=">, Group, Fla
HelpText<"Specify types of branches to align">;
def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">,
Group, Flags<[DriverOption]>,
HelpText<"Specify the boundary's size to align branches">;
-def malign_branch_prefix_size_EQ : Joined<["-"],
"malign-branch-prefix-size=">, Group;
+def mpad_max_prefix_size_EQ : Joined<["-"], "mpad-max-prefix-size=">,
Group, Flags<[DriverOption]>,
+ HelpText<"Specify maximum number of prefixes to use for padding">;
def mbranches_within_32B_boundaries : Flag<["-"],
"mbranches-within-32B-boundaries">, Flags<[DriverOption]>, Group,
HelpText<"Align selected branches (fused, jcc, jmp) within 32-byte
boundary">;
def mfancy_math_387 : Flag<["-"], "mfancy-math-387">,
Group;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 2b368131f5cc..5f9b6d813416 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2078,17 +2078,16 @@ static void addX86AlignBranchArgs(const Driver &D,
const ArgList &Args,
CmdArgs.push_back("-mllvm");
CmdArgs.push_back(Args.MakeArgString("-x86-align-branch=" + AlignBranch));
}
- if (const Arg *A =
- Args.getLastArg(options::OPT_malign_branch_prefix_size_EQ)) {
+ if (const Arg *A = Args.getLastArg(options::OPT_mpad_max_prefix_size_EQ)) {
StringRef Value = A->getValue();
unsigned PrefixSize;
-if (Value.getAsInteger(10, PrefixSize) || PrefixSize > 5) {
+if (Value.getAsInteger(10, PrefixSize)) {
D.Diag(diag::err_drv_invalid_argument_to_option)
<< Value << A->getOption().getName();
} else {
CmdArgs.push_back("-mllvm");
- CmdArgs.push_back(Args.MakeArgString("-x86-align-branch-prefix-size=" +
- Twine(PrefixSize)));
+ CmdArgs.push_back(
+ Args.MakeArgString("-x86-pad-max-prefix-size=" + Twine(PrefixSize)));
}
}
}
diff --git a/clang/test/Driver/x86-malign-branch.c
b/clang/test/Driver/x86-malign-branch.c
index 6098caf0b5d4..5180eb0a1619 100644
--- a/clang/test/Driver/x86-malign-branch.c
+++ b/clang/test/Driver/x86-malign-branch.c
@@ -18,14 +18,11 @@
// TYPE-ERR: invalid argument 'foo' to -malign-branch=; each element must be
one of: fused, jcc, jmp, call, ret, indirect
// TYPE-ERR: invalid argument 'bar' to -malign-branch=; each element must be
one of: fused, jcc, jmp, call, ret, indirect
-/// Test -malign-branch-prefix-size=
-// RUN: %clang -target x86_64 -malign-branch-prefix-size=0 %s -c -### 2>&1 |
FileCheck %s --check-prefix=PREFIX-0
-// PREFIX-0: "-mllvm" "-x86-align-branch-prefix-size=0"
-// RUN: %clang -target x86_64 -malign-branch-prefix-size=5 %s -c -### 2>&1 |
FileCheck %s --check-prefix=PREFIX-5
-// PREFIX-5: "-mllvm" "-x86-align-branch-prefix-size=5"
-
-// RUN: %clang -target x86_64 -malign-branch-prefix-size=6 %s -c -### 2>&1 |
FileCheck %s --check-prefix=PREFIX-6
-// PREFIX-6: invalid argument
+/// Test -mpad-max-prefix-size=
+// RUN: %clang -target x86_64 -mpad-max-prefix-size=0 %s -c -### 2>&
[clang] 2c63ea6 - [TEST] TreeTest.cpp - Add a comma to avoid build error with -werror
Author: Shengchen Kan
Date: 2020-06-08T23:14:16+08:00
New Revision: 2c63ea6eded3eed4018306363c28b7f63d7b5898
URL:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898
DIFF:
https://github.com/llvm/llvm-project/commit/2c63ea6eded3eed4018306363c28b7f63d7b5898.diff
LOG: [TEST] TreeTest.cpp - Add a comma to avoid build error with -werror
Summary:
The macro `INSTANTIATE_TEST_CASE_P` is defined as
```
\# define INSTANTIATE_TEST_CASE_P(prefix, test_case_name, generator, ...) \
...
```
If we build the test case with -werror, we will get an error like
```
error: ISO C++11 requires at least one argument for the "..." in a
variadic macro
testing::ValuesIn(TestClangConfig::allConfigs()));
^
```
This patch fixes that.
Reviewers: gribozavr, hlopko, eduucaldas, gribozavr2
Reviewed By: gribozavr2
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81388
Added:
Modified:
clang/unittests/Tooling/Syntax/TreeTest.cpp
Removed:
diff --git a/clang/unittests/Tooling/Syntax/TreeTest.cpp
b/clang/unittests/Tooling/Syntax/TreeTest.cpp
index 49fdcb7a9c54..64acfe30a05b 100644
--- a/clang/unittests/Tooling/Syntax/TreeTest.cpp
+++ b/clang/unittests/Tooling/Syntax/TreeTest.cpp
@@ -2995,6 +2995,6 @@ TEST_P(SyntaxTreeTest, SynthesizedNodes) {
}
INSTANTIATE_TEST_CASE_P(SyntaxTreeTests, SyntaxTreeTest,
-testing::ValuesIn(TestClangConfig::allConfigs()));
+testing::ValuesIn(TestClangConfig::allConfigs()), );
} // namespace
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[clang] ad60ff7 - [NFC] Code cleanup in TargetInfo.cpp
Author: Shengchen Kan
Date: 2020-05-13T14:48:46+08:00
New Revision: ad60ff70eb56a7d198e613152f9974d5d4baabd4
URL:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4
DIFF:
https://github.com/llvm/llvm-project/commit/ad60ff70eb56a7d198e613152f9974d5d4baabd4.diff
LOG: [NFC] Code cleanup in TargetInfo.cpp
Fix the signed/unsigned mismatch issue
Added:
Modified:
clang/lib/CodeGen/TargetInfo.cpp
Removed:
diff --git a/clang/lib/CodeGen/TargetInfo.cpp
b/clang/lib/CodeGen/TargetInfo.cpp
index bc5c1682853b..44608ea461ec 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -6675,9 +6675,9 @@ bool NVPTXABIInfo::isUnsupportedType(QualType T) const {
return true;
if (const auto *EIT = T->getAs())
return EIT->getNumBits() >
- (Context.getTargetInfo().hasInt128Type() ? 128 : 64);
+ (Context.getTargetInfo().hasInt128Type() ? 128U : 64U);
if (!Context.getTargetInfo().hasInt128Type() && T->isIntegerType() &&
- Context.getTypeSize(T) > 64)
+ Context.getTypeSize(T) > 64U)
return true;
if (const auto *AT = T->getAsArrayTypeUnsafe())
return isUnsupportedType(AT->getElementType());
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -119,9 +119,13 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabled(Features, F, true); std::vector UpdatedFeaturesVec; - bool HasEVEX512 = true; + std::vector UpdatedAVX10FeaturesVec; + int HasEVEX512 = -1; KanRobert wrote: Use std::optional ? https://github.com/llvm/llvm-project/pull/71318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -15,8 +15,12 @@
#define __AVX2INTRIN_H
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__,
__target__("avx2"), __min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__,
__target__("avx2"), __min_vector_width__(128)))
+#define __DEFAULT_FN_ATTRS256
\
+ __attribute__((__always_inline__, __nodebug__,
\
+ __target__("avx2,no-evex512"), __min_vector_width__(256)))
KanRobert wrote:
Why does the function targeted at avx2 need `no-evex512`?
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -50,11 +50,11 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS
\
- __attribute__((__always_inline__, __nodebug__, __target__("sse2"),
\
- __min_vector_width__(128)))
+ __attribute__((__always_inline__, __nodebug__,
\
+ __target__("sse2,no-evex512"), __min_vector_width__(128)))
#define __DEFAULT_FN_ATTRS_MMX
\
- __attribute__((__always_inline__, __nodebug__, __target__("mmx,sse2"),
\
- __min_vector_width__(64)))
+ __attribute__((__always_inline__, __nodebug__,
\
KanRobert wrote:
Why does the function targeted at sse2 need no-evex512?
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+ if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+ HasAVX10_512 = true;
+LastAVX10 = Feature;
+ } else if (HasAVX10 && Feature == "-avx10.1-256") {
+HasAVX10 = false;
+HasAVX10_512 = false;
+ } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
+HasAVX10_512 = false;
}
+ // Postpone AVX10 features handling after AVX512 settled.
+ UpdatedAVX10FeaturesVec.push_back(Feature);
+ continue;
} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
HasAVX512F = true;
+ LastAVX512 = Feature;
} else if (HasAVX512F && Feature == "-avx512f") {
HasAVX512F = false;
-} else if (HasAVX10 && Feature == "-avx10.1-256") {
- HasAVX10 = false;
- HasAVX512F = false;
-} else if (!HasEVEX512 && Feature == "+evex512") {
+} else if (HasEVEX512 != true && Feature == "+evex512") {
KanRobert wrote:
Comparing a int value with `true` and `false` may be confusing. I suggest
"std::optional"
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+ if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+ HasAVX10_512 = true;
+LastAVX10 = Feature;
+ } else if (HasAVX10 && Feature == "-avx10.1-256") {
+HasAVX10 = false;
+HasAVX10_512 = false;
+ } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
+HasAVX10_512 = false;
}
+ // Postpone AVX10 features handling after AVX512 settled.
+ UpdatedAVX10FeaturesVec.push_back(Feature);
+ continue;
} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
HasAVX512F = true;
+ LastAVX512 = Feature;
} else if (HasAVX512F && Feature == "-avx512f") {
HasAVX512F = false;
-} else if (HasAVX10 && Feature == "-avx10.1-256") {
- HasAVX10 = false;
- HasAVX512F = false;
-} else if (!HasEVEX512 && Feature == "+evex512") {
+} else if (HasEVEX512 != true && Feature == "+evex512") {
HasEVEX512 = true;
-} else if (HasEVEX512 && Feature == "-avx10.1-512") {
- HasEVEX512 = false;
-} else if (HasEVEX512 && Feature == "-evex512") {
+ continue;
+} else if (HasEVEX512 != false && Feature == "-evex512") {
HasEVEX512 = false;
+ continue;
}
UpdatedFeaturesVec.push_back(Feature);
}
- if (HasAVX512F && HasEVEX512)
-UpdatedFeaturesVec.push_back("+evex512");
- else if (HasAVX10)
-UpdatedFeaturesVec.push_back("-evex512");
+ llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec);
KanRobert wrote:
Does it mean the flags for AVX10 Features will be in the vector
`UpdatedFeaturesVec` 2 times?
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+ if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+ HasAVX10_512 = true;
+LastAVX10 = Feature;
+ } else if (HasAVX10 && Feature == "-avx10.1-256") {
+HasAVX10 = false;
+HasAVX10_512 = false;
+ } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
+HasAVX10_512 = false;
}
+ // Postpone AVX10 features handling after AVX512 settled.
+ UpdatedAVX10FeaturesVec.push_back(Feature);
+ continue;
} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
HasAVX512F = true;
+ LastAVX512 = Feature;
} else if (HasAVX512F && Feature == "-avx512f") {
HasAVX512F = false;
-} else if (HasAVX10 && Feature == "-avx10.1-256") {
- HasAVX10 = false;
- HasAVX512F = false;
-} else if (!HasEVEX512 && Feature == "+evex512") {
+} else if (HasEVEX512 != true && Feature == "+evex512") {
HasEVEX512 = true;
-} else if (HasEVEX512 && Feature == "-avx10.1-512") {
- HasEVEX512 = false;
-} else if (HasEVEX512 && Feature == "-evex512") {
+ continue;
+} else if (HasEVEX512 != false && Feature == "-evex512") {
HasEVEX512 = false;
+ continue;
}
UpdatedFeaturesVec.push_back(Feature);
}
- if (HasAVX512F && HasEVEX512)
-UpdatedFeaturesVec.push_back("+evex512");
- else if (HasAVX10)
-UpdatedFeaturesVec.push_back("-evex512");
+ llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec);
KanRobert wrote:
I see.
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
@@ -131,35 +135,50 @@ bool X86TargetInfo::initFeatureMap(
continue;
}
-if (Feature.substr(0, 7) == "+avx10.") {
- HasAVX10 = true;
- HasAVX512F = true;
- if (Feature.substr(Feature.size() - 3, 3) == "512") {
-HasEVEX512 = true;
- } else if (Feature.substr(7, 2) == "1-") {
-HasEVEX512 = false;
+if (Feature.substr(1, 6) == "avx10.") {
+ if (Feature[0] == '+') {
+HasAVX10 = true;
+if (Feature.substr(Feature.size() - 3, 3) == "512")
+ HasAVX10_512 = true;
+LastAVX10 = Feature;
+ } else if (HasAVX10 && Feature == "-avx10.1-256") {
+HasAVX10 = false;
+HasAVX10_512 = false;
+ } else if (HasAVX10_512 && Feature == "-avx10.1-512") {
+HasAVX10_512 = false;
}
+ // Postpone AVX10 features handling after AVX512 settled.
+ UpdatedAVX10FeaturesVec.push_back(Feature);
+ continue;
} else if (!HasAVX512F && Feature.substr(0, 7) == "+avx512") {
HasAVX512F = true;
+ LastAVX512 = Feature;
} else if (HasAVX512F && Feature == "-avx512f") {
HasAVX512F = false;
-} else if (HasAVX10 && Feature == "-avx10.1-256") {
- HasAVX10 = false;
- HasAVX512F = false;
-} else if (!HasEVEX512 && Feature == "+evex512") {
+} else if (HasEVEX512 != true && Feature == "+evex512") {
KanRobert wrote:
You can check `has_value` for uninitialized value. But enum looks good to me,
too.
https://github.com/llvm/llvm-project/pull/71318
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[clang] [X86][AVX10] Permit AVX512 options/features used together with AVX10 (PR #71318)
https://github.com/KanRobert approved this pull request. LGTM. Maybe we can add some explanations about why we add attribute `no-evex512` for intrinsics in the description of the PR. It's a little tricky. https://github.com/llvm/llvm-project/pull/71318 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][AVX10] Fix a bug when using -march with no-evex512 attribute (PR #72126)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/72126 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] ms inline asm: Fix {call,jmp} fptr (PR #73207)
KanRobert wrote: Investigating, I almost forgot the mechanism of MS inline asm support... https://github.com/llvm/llvm-project/pull/73207 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add a EVEX256 macro to match with GCC and MSVC (PR #71317)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/71317 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86][AVX10] Allow 64-bit mask register used without EVEX512 (PR #75571)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/75571 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Emit Warnings for frontend options to enable knl/knm. (PR #75580)
KanRobert wrote: One more justification... https://www.felixcloutier.com/x86/vscatterpf0dps:vscatterpf0qps:vscatterpf0dpd:vscatterpf0qpd The assembler support for some KNL instructions is buggy https://github.com/llvm/llvm-project/blob/31429e7a89590f88034920edd3e997aeabff8124/llvm/test/MC/X86/apx/evex-format-intel.s#L46 If we deprecate KNL, the bug can go away. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 KanRobert wrote: space between ; and RUN. https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64 KanRobert wrote: Could we use the default check prefix? `X64` is kind of misleading. https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+;RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
--check-prefixes=X64
+
+define i64 @sub8(i64 noundef %res, ptr %byte) {
+; X64-LABEL: sub8:
+; X64: # %bb.0: # %entry
+; X64-NEXT:movq %rdi, %rax
+; X64-NEXT:movb (%rsi), %al
+; X64-NEXT:retq
+entry:
+ %and = and i64 %res, -256
+ %d = load i8, ptr %byte, align 1
+ %conv2 = zext i8 %d to i64
+ %or = or i64 %and, %conv2
+ ret i64 %or
+}
+
+define i64 @sub16(i64 noundef %res, ptr %byte) {
+; X64-LABEL: sub16:
+; X64: # %bb.0: # %entry
+; X64-NEXT:movq %rdi, %rax
+; X64-NEXT:movw (%rsi), %ax
+; X64-NEXT:retq
+entry:
+ %and = and i64 %res, -65536
+ %d = load i16, ptr %byte, align 1
+ %conv2 = zext i16 %d to i64
+ %or = or i64 %and, %conv2
+ ret i64 %or
+}
+
+
+
+
KanRobert wrote:
drop trailing new lines
https://github.com/llvm/llvm-project/pull/75978
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[llvm] [clang] [clang-tools-extra] [ISel] Add pattern matching for depositing subreg value (PR #75978)
@@ -1515,6 +1515,15 @@ def : Pat<(X86add_flag_nocf GR32:$src1, 128), def : Pat<(X86add_flag_nocf GR64:$src1, 128), (SUB64ri32 GR64:$src1, -128)>; +// Depositing value to 8/16 bit subreg: +def : Pat<(or (and GR64:$dst, -256), + (i64 (zextloadi8 addr:$src))), + (INSERT_SUBREG (i64 (COPY $dst)), (MOV8rm i8mem:$src), sub_8bit)>; KanRobert wrote: align with `(or` https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang-tools-extra] [clang] [ISel] Add pattern matching for depositing subreg value (PR #75978)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/75978 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] ms inline asm: Fix {call,jmp} fptr (PR #73207)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/73207 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AArch64] Warn when calling a NEON builtin in a streaming function (PR #73672)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/73672
>From 96464a9c37a532216e4df6c003aa1a8fcb448637 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Tue, 28 Nov 2023 16:22:32 +
Subject: [PATCH 1/2] [AArch64] Warn when calling a NEON builtin in a streaming
function
This patch introduces a warning that is emitted when a Neon builtin is called
from a streaming function, as that situation is not supported.
---
.../clang/Basic/DiagnosticSemaKinds.td| 3 +
clang/lib/Sema/SemaChecking.cpp | 81 +++
.../Sema/aarch64-incompat-sm-builtin-calls.c | 24 ++
3 files changed, 108 insertions(+)
create mode 100644 clang/test/Sema/aarch64-incompat-sm-builtin-calls.c
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 9a7dafa4a2982734..e2b7a695322c14b0 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -3148,6 +3148,9 @@ def err_attribute_bad_sve_vector_size : Error<
def err_attribute_arm_feature_sve_bits_unsupported : Error<
"%0 is only supported when '-msve-vector-bits=' is specified with a "
"value of 128, 256, 512, 1024 or 2048.">;
+def warn_attribute_arm_sm_incompat_builtin : Warning<
+ "builtin call has undefined behaviour when called from a %0 function">,
+ InGroup>;
def err_sve_vector_in_non_sve_target : Error<
"SVE vector type %0 cannot be used in a target without sve">;
def err_attribute_riscv_rvv_bits_unsupported : Error<
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index ae588db02bbe7226..07937047a2843b01 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2993,6 +2993,62 @@ static QualType getNeonEltType(NeonTypeFlags Flags,
ASTContext &Context,
llvm_unreachable("Invalid NeonTypeFlag!");
}
+enum ArmStreamingType {
+ ArmNonStreaming,
+ ArmStreaming,
+ ArmStreamingCompatible,
+ ArmLocallyStreaming,
+ ArmStreamingOrSVE2p1
+};
+
+static ArmStreamingType getArmStreamingFnType(const FunctionDecl *FD) {
+ if (FD->hasAttr())
+return ArmLocallyStreaming;
+ if (const auto *T = FD->getType()->getAs()) {
+if (T->getAArch64SMEAttributes() & FunctionType::SME_PStateSMEnabledMask)
+ return ArmStreaming;
+if (T->getAArch64SMEAttributes() &
FunctionType::SME_PStateSMCompatibleMask)
+ return ArmStreamingCompatible;
+ }
+ return ArmNonStreaming;
+}
+
+static void checkArmStreamingBuiltin(Sema &S, CallExpr *TheCall,
+ const FunctionDecl *FD,
+ ArmStreamingType BuiltinType) {
+ assert(BuiltinType != ArmLocallyStreaming &&
+ "Unexpected locally_streaming attribute for builtin!");
+
+ ArmStreamingType FnType = getArmStreamingFnType(FD);
+ if (BuiltinType == ArmStreamingOrSVE2p1) {
+// Check intrinsics that are available in [sve2p1 or sme/sme2].
+llvm::StringMap CallerFeatureMap;
+S.Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+if (Builtin::evaluateRequiredTargetFeatures("sve2p1", CallerFeatureMap))
+ BuiltinType = ArmStreamingCompatible;
+else
+ BuiltinType = ArmStreaming;
+ }
+
+ if ((FnType == ArmStreaming || FnType == ArmLocallyStreaming) &&
+ BuiltinType == ArmNonStreaming) {
+S.Diag(TheCall->getBeginLoc(),
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "streaming or locally streaming";
+ }
+
+ if ((FnType == ArmStreamingCompatible) &&
+ BuiltinType != ArmStreamingCompatible) {
+S.Diag(TheCall->getBeginLoc(),
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "streaming compatible";
+return;
+ }
+
+ if (FnType == ArmNonStreaming && BuiltinType == ArmStreaming) {
+S.Diag(TheCall->getBeginLoc(),
diag::warn_attribute_arm_sm_incompat_builtin)
+<< TheCall->getSourceRange() << "non-streaming";
+ }
+}
+
bool Sema::CheckSVEBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
// Range check SVE intrinsics that take immediate values.
SmallVector, 3> ImmChecks;
@@ -3136,6 +3192,31 @@ bool Sema::CheckSVEBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
bool Sema::CheckNeonBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID, CallExpr *TheCall)
{
+ if (const FunctionDecl *FD = getCurFunctionDecl()) {
+std::optional BuiltinType;
+
+bool IsNeon = false;
+switch (BuiltinID) {
+default:
+ break;
+#define GET_NEON_BUILTINS
+#define TARGET_BUILTIN(id, x, y, z)
\
+ case NEON::BI##id:
\
+IsNeon = true;
\
+break;
+#define BUILTIN(id, x, y) TARGET_BUILTIN(id, x, y, "");
+#include "clang/Basic/arm_neon.in
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert created
https://github.com/llvm/llvm-project/pull/74199
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Bui
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/2] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/3] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">, Group, HelpText<"Disable generation of gather instructions in auto-vectorization(x86 only)">; def mno_scatter : Flag<["-"], "mno-scatter">, Group, HelpText<"Disable generation of scatter instructions in auto-vectorization(x86 only)">; +def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, +HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; +def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, +HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; +def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; +def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; KanRobert wrote: Explained in the description. https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/4] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
KanRobert wrote:
Yes, done.
https://github.com/llvm/llvm-project/pull/74199
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/5] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/6] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
@@ -422,3 +422,28 @@ // RUN: touch %t.o // RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu -mharden-sls=all %t.o -o /dev/null 2>&1 | count 0 +// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=APXF %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-APXF %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apxf -mapxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=APXF %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf -mno-apxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-APXF %s +// +// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" +// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" + +// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr -mapx-features=ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr -mno-apx-features=ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-EGPR-NO-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr -mapx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mno-apx-features=egpr,ndd -mapx-features=egpr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR-NO-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr,ndd -mno-apx-features=egpr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-EGPR-NDD %s +// RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr -mno-apx-features=egpr,ndd %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-EGPR-NO-NDD %s +// +// EGPR-NDD: "-target-feature" "+egpr" "-target-feature" "+ndd" +// EGPR-NO-NDD: "-target-feature" "-ndd" "-target-feature" "+egpr" +// NO-EGPR-NDD: "-target-feature" "+ndd" "-target-feature" "-egpr" +// NO-EGPR-NO-NDD: "-target-feature" "-egpr" "-target-feature" "-ndd" + KanRobert wrote: Done https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/7] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[clang] [llvm] [X86] Support CFE flags for APX features (PR #74199)
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">, Group, HelpText<"Disable generation of gather instructions in auto-vectorization(x86 only)">; def mno_scatter : Flag<["-"], "mno-scatter">, Group, HelpText<"Disable generation of scatter instructions in auto-vectorization(x86 only)">; +def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, +HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; +def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, +HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; +def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; +def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; KanRobert wrote: Sure. Done https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert updated
https://github.com/llvm/llvm-project/pull/74199
>From 246d6e2bc3f6fb60623b5d4c3f07b53c628ed88a Mon Sep 17 00:00:00 2001
From: Shengchen Kan
Date: Sat, 2 Dec 2023 23:52:53 +0800
Subject: [PATCH 1/8] [X86] Support CFE flags for APX features
Positive options: -mapx-features=
Negative options: -mno-apx-features=
-m[no-]apx-features is designed to be able to control separate APX
features.
Besides, we also support the flag -m[no-]apxf, which can be used like an
alias of -m[no-]apx-features=< all APX features covered by CPUID APX_F>
Behaviour when positive and negative options are used together:
For boolean flags, the last one wins
-mapxf -mno-apxf -> -mno-apxf
-mno-apxf -mapxf -> -mapxf
For flags that take a set as arguments, it sets the mask by order of the
flags
-mapx-features=egpr,ndd -mno-apx-features=egpr -> -egpr,+ndd
-mapx-features=egpr -mno-apx-features=egpr,ndd -> -egpr,-ndd
-mno-apx-features=egpr -mapx-features=egpr,ndd -> +egpr,+ndd
-mno-apx-features=egpr,ndd -mapx-features=egpr -> -ndd,+egpr
The design is aligned with gcc
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628905.html
---
clang/include/clang/Driver/Options.td | 6
clang/lib/Basic/Targets/X86.cpp | 34 +++
clang/lib/Basic/Targets/X86.h | 6
clang/lib/Driver/ToolChains/Arch/X86.cpp | 15
clang/test/Driver/apxf-target-features.c | 25 ++
.../llvm/TargetParser/X86TargetParser.def | 6
llvm/lib/Target/X86/X86.td| 6
llvm/lib/TargetParser/X86TargetParser.cpp | 8 +
8 files changed, 106 insertions(+)
create mode 100644 clang/test/Driver/apxf-target-features.c
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 19d04e82aed4d..631c5ad1c015d 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5999,6 +5999,12 @@ def mno_gather : Flag<["-"], "mno-gather">,
Group,
HelpText<"Disable generation of gather instructions in
auto-vectorization(x86 only)">;
def mno_scatter : Flag<["-"], "mno-scatter">, Group,
HelpText<"Disable generation of scatter instructions in
auto-vectorization(x86 only)">;
+def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">,
Group,
+HelpText<"Enable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">,
Group,
+HelpText<"Disable features of APX">,
Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">;
+def mapxf : Flag<["-"], "mapxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
+def mno_apxf : Flag<["-"], "mno-apxf">, Alias,
AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","cf"]>;
} // let Flags = [TargetSpecific]
// VE feature flags
diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp
index 85d0697ad63ca..9392211aa6fdf 100644
--- a/clang/lib/Basic/Targets/X86.cpp
+++ b/clang/lib/Basic/Targets/X86.cpp
@@ -428,6 +428,18 @@ bool
X86TargetInfo::handleTargetFeatures(std::vector &Features,
HasX87 = true;
} else if (Feature == "+fullbf16") {
HasFullBFloat16 = true;
+} else if (Feature == "+egpr") {
+ HasEGPR = true;
+} else if (Feature == "+push2pop2") {
+ HasPush2Pop2 = true;
+} else if (Feature == "+ppx") {
+ HasPPX = true;
+} else if (Feature == "+ndd") {
+ HasNDD = true;
+} else if (Feature == "+ccmp") {
+ HasCCMP = true;
+} else if (Feature == "+cf") {
+ HasCF = true;
}
X86SSEEnum Level = llvm::StringSwitch(Feature)
@@ -927,6 +939,16 @@ void X86TargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("__USERMSR__");
if (HasCRC32)
Builder.defineMacro("__CRC32__");
+ if (HasEGPR)
+Builder.defineMacro("__EGPR__");
+ if (HasPush2Pop2)
+Builder.defineMacro("__PUSH2POP2__");
+ if (HasNDD)
+Builder.defineMacro("__NDD__");
+ if (HasCCMP)
+Builder.defineMacro("__CCMP__");
+ if (HasCF)
+Builder.defineMacro("__CF__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@@ -1122,6 +1144,12 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name)
const {
.Case("xsavec", true)
.Case("xsaves", true)
.Case("xsaveopt", true)
+ .Case("egpr", true)
+ .Case("push2pop2", true)
+ .Case("ppx", true)
+ .Case("ndd", true)
+ .Case("ccmp", true)
+ .Case("cf", true)
.Default(false);
}
@@ -1238,6 +1266,12 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("xsaves", HasXSAVES)
.Case("xsaveopt", HasXSAVEOPT)
.Case("fullbf16", HasFullBFloat16)
+ .Case("egpr", HasEGPR)
+ .Case("push2pop2", HasPush2Pop2)
+ .Case("ppx", HasPPX)
+ .Case("ndd", HasNDD)
+ .Case("ccmp", HasCCMP)
+ .Case("cf", Ha
[clang] [llvm] [X86] Support CFE flags for APX features (PR #74199)
@@ -422,3 +422,28 @@ // RUN: touch %t.o // RUN: %clang -fdriver-only -Werror --target=x86_64-pc-linux-gnu -mharden-sls=all %t.o -o /dev/null 2>&1 | count 0 +// RUN: %clang -target x86_64-unknown-linux-gnu -mapxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=APXF %s KanRobert wrote: Done https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
KanRobert wrote: @phoebewang Thanks for the review! https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Support CFE flags for APX features (PR #74199)
https://github.com/KanRobert closed https://github.com/llvm/llvm-project/pull/74199 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Correct operand order of UWRMSR. (PR #76389)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76389 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Remove RAO-INT from Grandridge (PR #76420)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76420 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] New calling convention preserve_none (PR #76868)
@@ -1056,6 +1056,22 @@ def CC_Intel_OCL_BI : CallingConv<[ CCDelegateTo ]>; +def CC_X86_64_Preserve_None : CallingConv<[ + // We don't preserve general registers, so all of them can be used to pass + // arguments except + // - RBP frame pointer KanRobert wrote: It does not mention R16-R31 https://github.com/llvm/llvm-project/pull/76868 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang] [llvm] [X86] Emit Warnings for frontend options to enable knl/knm specific ISAs. (PR #75580)
https://github.com/KanRobert approved this pull request. https://github.com/llvm/llvm-project/pull/75580 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][X86] Reformat ia32intrin.h doc to match the other headers (PR #77525)
KanRobert wrote: cc @FreddyLeaf https://github.com/llvm/llvm-project/pull/77525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][X86] Reformat ia32intrin.h doc to match the other headers (PR #77525)
https://github.com/KanRobert approved this pull request. https://github.com/llvm/llvm-project/pull/77525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] New calling convention preserve_none (PR #76868)
@@ -1056,6 +1056,23 @@ def CC_Intel_OCL_BI : CallingConv<[ CCDelegateTo ]>; +def CC_X86_64_Preserve_None : CallingConv<[ + // We don't preserve general registers, so all of them can be used to pass + // arguments except + // - RBPframe pointer + // - R10'nest' parameter + // - RBXbase pointer + // - R16 - R31 these are not available everywhere KanRobert wrote: I won't expect this from the name `preserve_none`. R16-R31 should be used to pas arguments when they're available. https://github.com/llvm/llvm-project/pull/76868 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add missing MACROs in cpuid.h (PR #80815)
https://github.com/KanRobert commented: Past the link of GCC files in description? https://github.com/llvm/llvm-project/pull/80815 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
KanRobert wrote:
My understanding is "apxf" here is used by front-end for FMV, right?
What would happen if there is "apxf" in the IR after this patch?
https://github.com/llvm/llvm-project/pull/80636
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[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["apxf"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
KanRobert wrote:
> if llc read "apxf" in attribute, I think a warning will be given like:
>
> ```
> '+apxf' is not a recognized feature for this target (ignoring feature)
> ```
Did you check the behavior w/ this patch?
https://github.com/llvm/llvm-project/pull/80636
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[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
@@ -462,12 +462,12 @@ TARGET_BUILTIN(__builtin_ia32_blendvps256, "V8fV8fV8fV8f", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufpd256, "V4dV4dV4dIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_shufps256, "V8fV8fV8fIi", "ncV:256:", "avx") TARGET_BUILTIN(__builtin_ia32_dpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmppd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") TARGET_BUILTIN(__builtin_ia32_cmppd256, "V4dV4dV4dIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpps, "V4fV4fV4fIc", "ncV:128:", "avx|sse") TARGET_BUILTIN(__builtin_ia32_cmpps256, "V8fV8fV8fIc", "ncV:256:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx") -TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx") +TARGET_BUILTIN(__builtin_ia32_cmpsd, "V2dV2dV2dIc", "ncV:128:", "avx|sse2") +TARGET_BUILTIN(__builtin_ia32_cmpss, "V4fV4fV4fIc", "ncV:128:", "avx|sse") KanRobert wrote: Why do we need "avx|"? Move this to line 346? https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
KanRobert wrote: My understanding is that you change the required feature of __builtin_ia32_cmp[p|s][s|d] from avx to sse for some condition codes. The title is not accurate. https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Change target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2 (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
KanRobert wrote:
Why? Any background. Please add it to the description.
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
KanRobert wrote:
This is the behavior. But why?
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
@@ -2613,6 +2614,24 @@ void CGBuilderInserter::InsertHelper(
// called function.
void CodeGenFunction::checkTargetFeatures(const CallExpr *E,
const FunctionDecl *TargetDecl) {
+ // SemaCheking cannot handle below x86 builtins because they have different
+ // parameter ranges with different TargetAttribute of caller.
KanRobert wrote:
I see. They corresponds to different instructions.
https://github.com/llvm/llvm-project/pull/84136
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[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
KanRobert wrote: Still not understand. Shouldn't the target feature of the caller be passed to the intrinsic when checking the argument of the intrinsic? https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finely handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
KanRobert wrote: > > Still not understand. Shouldn't the target feature of the caller be passed > > to the intrinsic when checking the argument of the intrinsic? > > The target features passing from option can be passed to Semachecking. It's > special for attribute_target, which is handled in `handleTargetAttr`, which > is after Sema::CheckBuiltinFunctionCall. Then why not move the call `handleTargetAttr` before `Sema::CheckBuiltinFunctionCall`? https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Finally handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avx (PR #84136)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84136 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [clang-tools-extra] [llvm] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -217,10 +217,11 @@ enum ProcessorFeatures {
FEATURE_SM3,
FEATURE_SHA512,
FEATURE_SM4,
- // FEATURE_APX_F,
- FEATURE_USERMSR = 112,
- // FEATURE_AVX10_1_256,
- // FEATURE_AVX10_1_512,
+ //FIXME: gcc used string "apxf" instead of "egpr"
KanRobert wrote:
GCC is using "apxf ". I believe we need to discuss with GCC team about this.
https://github.com/llvm/llvm-project/pull/79086
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[compiler-rt] [llvm] [clang] [clang-tools-extra] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -173,85 +173,86 @@ X86_FEATURE_COMPAT(AVX512VNNI, "avx512vnni", 34) X86_FEATURE_COMPAT(AVX512BITALG,"avx512bitalg", 35) X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16",36) X86_FEATURE_COMPAT(AVX512VP2INTERSECT, "avx512vp2intersect", 37) -// Features below here are not in libgcc/compiler-rt. -X86_FEATURE (3DNOW, "3dnow") +// Below Features has some missings comparing to gcc, it's because gcc has some +// not one-to-one mapped in llvm. +X86_FEATURE_COMPAT(3DNOW, "3dnow", 0) X86_FEATURE (3DNOWA, "3dnowa") +X86_FEATURE_COMPAT(ADX, "adx",0) X86_FEATURE (64BIT, "64bit") -X86_FEATURE (ADX, "adx") -X86_FEATURE (AMX_BF16,"amx-bf16") -X86_FEATURE (AMX_COMPLEX, "amx-complex") -X86_FEATURE (AMX_INT8,"amx-int8") -X86_FEATURE (AMX_TILE,"amx-tile") -X86_FEATURE (CLDEMOTE,"cldemote") -X86_FEATURE (CLFLUSHOPT, "clflushopt") -X86_FEATURE (CLWB,"clwb") -X86_FEATURE_COMPAT(F16C,"f16c", 38) -X86_FEATURE (CLZERO, "clzero") -X86_FEATURE (CMPXCHG16B, "cx16") +X86_FEATURE_COMPAT(CLDEMOTE,"cldemote", 0) +X86_FEATURE_COMPAT(CLFLUSHOPT, "clflushopt", 0) +X86_FEATURE_COMPAT(CLWB,"clwb", 0) +X86_FEATURE_COMPAT(CLZERO, "clzero", 0) +X86_FEATURE_COMPAT(CMPXCHG16B, "cx16", 0) X86_FEATURE (CMPXCHG8B, "cx8") +X86_FEATURE_COMPAT(ENQCMD, "enqcmd", 0) +X86_FEATURE_COMPAT(F16C,"f16c", 0) +X86_FEATURE_COMPAT(FSGSBASE,"fsgsbase", 0) X86_FEATURE (CRC32, "crc32") -X86_FEATURE (ENQCMD, "enqcmd") -X86_FEATURE (FSGSBASE,"fsgsbase") -X86_FEATURE (FXSR,"fxsr") X86_FEATURE (INVPCID, "invpcid") -X86_FEATURE (KL, "kl") -X86_FEATURE (WIDEKL, "widekl") -X86_FEATURE (LWP, "lwp") -X86_FEATURE (LZCNT, "lzcnt") -X86_FEATURE (MOVBE, "movbe") -X86_FEATURE (MOVDIR64B, "movdir64b") -X86_FEATURE (MOVDIRI, "movdiri") -X86_FEATURE (MWAITX, "mwaitx") -X86_FEATURE (PCONFIG, "pconfig") -X86_FEATURE (PKU, "pku") -X86_FEATURE (PREFETCHI, "prefetchi") -X86_FEATURE (PREFETCHWT1, "prefetchwt1") -X86_FEATURE (PRFCHW, "prfchw") -X86_FEATURE (PTWRITE, "ptwrite") -X86_FEATURE (RDPID, "rdpid") X86_FEATURE (RDPRU, "rdpru") -X86_FEATURE (RDRND, "rdrnd") -X86_FEATURE (RDSEED, "rdseed") -X86_FEATURE (RTM, "rtm") X86_FEATURE (SAHF,"sahf") -X86_FEATURE (SERIALIZE, "serialize") -X86_FEATURE (SGX, "sgx") -X86_FEATURE (SHA, "sha") -X86_FEATURE (SHSTK, "shstk") -X86_FEATURE (TBM, "tbm") -X86_FEATURE (TSXLDTRK,"tsxldtrk") -X86_FEATURE (UINTR, "uintr") -X86_FEATURE (VAES,"vaes") X86_FEATURE (VZEROUPPER, "vzeroupper") -X86_FEATURE (WAITPKG, "waitpkg") -X86_FEATURE (WBNOINVD,"wbnoinvd") +X86_FEATURE_COMPAT(LWP, "lwp",0) +X86_FEATURE_COMPAT(LZCNT, "lzcnt", 0) +X86_FEATURE_COMPAT(MOVBE, "movbe", 0) +X86_FEATURE_COMPAT(MOVDIR64B, "movdir64b", 0) +X86_FEATURE_COMPAT(MOVDIRI, "movdiri",0) +X86_FEATURE_COMPAT(MWAITX, "mwaitx", 0) X86_FEATURE (X87, "x87") -X86_FEATURE (XSAVE, "xsave") -X86_FEATURE (XSAVEC, "xsavec") -X86_FEATURE (XSAVEOPT,"xsaveopt") -X86_FEATURE (XSAVES, "xsaves") -X86_FEATURE_COMPAT(AVX512FP16, "avx512fp16",39) -X86_FEATURE (HRESET, "hreset") -X86_FEATURE (RAOINT, "raoint") -X86_FEATURE (AMX_FP16,"amx-fp16") -X86_FEATURE (CMPCCXADD, "cmpccxadd") -X86_FEATURE (AVXNECONVERT,"avxneconvert") -X86_FEATURE (AVXVNNI, "avxvnni") -X86_FEATURE (AVXIFMA, "avxifma") -X86_FEATURE (AVXVNNIINT8, "avxvnniint8") -X86_FEATURE (SHA512, "sha512") -X86_FEATURE (SM3, "sm3") -X86_FEATURE (SM4, "sm4") -X86_FEATURE (AVXVNNIINT16,"avxvnniint16") -X86_FEATURE (EVEX512, "evex512") -X86_FEATURE (AVX10_1, "avx10.1-256") -X86_FEATURE (AVX10_1_512, "avx10.1-512") -X86_FEATURE (U
[compiler-rt] [llvm] [clang] [clang-tools-extra] [X86] Support more ISAs to enable __builtin_cpu_supports (PR #79086)
@@ -1845,6 +1845,7 @@ bool sys::getHostCPUFeatures(StringMap &Features) {
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
Features["avx10.1-256"] = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
+ Features["egpr"] = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
KanRobert wrote:
Same here. Should discuss with GCC team and create a separate PR.
https://github.com/llvm/llvm-project/pull/79086
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[llvm] [clang] [compiler-rt] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -248,10 +248,11 @@ X86_FEATURE_COMPAT(AVXVNNIINT16,"avxvnniint16", 0) X86_FEATURE_COMPAT(SM3, "sm3",0) X86_FEATURE_COMPAT(SHA512, "sha512", 0) X86_FEATURE_COMPAT(SM4, "sm4",0) -X86_FEATURE (EGPR,"egpr") +X86_FEATURE_COMPAT(APXF,"apxf", 0) X86_FEATURE_COMPAT(USERMSR, "usermsr",0) X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256",0) X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512",0) +X86_FEATURE (EGPR,"egpr") KanRobert wrote: I think only the position of X86_FEATURE_COMPAT matters while X86_FEATURE does not? https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [AVX10][Doc] Add documentation about AVX10 options and their attentions (PR #77925)
KanRobert wrote: Thanks for this! https://github.com/llvm/llvm-project/pull/77925 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)
KanRobert wrote: Why not return `i32` for 64-bit mask in 32-bit mode? https://github.com/llvm/llvm-project/pull/77733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)
KanRobert wrote: > > Why not return `i32` for 64-bit mask in 32-bit mode? > > You mean in two `i32` registers? The problem is the inline asm constraint has > 1:1 map with physical register except corner cases. And represent a `k` > constraint into two GPR registers is inefficient. Is it represented by i64 x 1 in 32-bit mode after this patch? https://github.com/llvm/llvm-project/pull/77733 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
// in the normal allocation?
case 'k':
if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1 || VT == MVT::i1)
return std::make_pair(0U, &X86::VK1RegClass);
-if (VT == MVT::i8)
+if (VT == MVT::v8i1 || VT == MVT::i8)
return std::make_pair(0U, &X86::VK8RegClass);
-if (VT == MVT::i16)
+if (VT == MVT::v16i1 || VT == MVT::i16)
return std::make_pair(0U, &X86::VK16RegClass);
}
if (Subtarget.hasBWI()) {
-if (VT == MVT::i32)
+if (VT == MVT::v32i1 || VT == MVT::i32)
return std::make_pair(0U, &X86::VK32RegClass);
-if (VT == MVT::i64)
+if (VT == MVT::v64i1 || VT == MVT::i64)
return std::make_pair(0U, &X86::VK64RegClass);
KanRobert wrote:
i1, i8, i16 is kept for what? backward compatibility of IR?
https://github.com/llvm/llvm-project/pull/77733
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[clang] [llvm] [X86] Use vXi1 for `k` constraint in inline asm (PR #77733)
@@ -57046,17 +57046,17 @@ X86TargetLowering::getRegForInlineAsmConstraint(const
TargetRegisterInfo *TRI,
// in the normal allocation?
case 'k':
if (Subtarget.hasAVX512()) {
-if (VT == MVT::i1)
+if (VT == MVT::v1i1 || VT == MVT::i1)
return std::make_pair(0U, &X86::VK1RegClass);
-if (VT == MVT::i8)
+if (VT == MVT::v8i1 || VT == MVT::i8)
return std::make_pair(0U, &X86::VK8RegClass);
-if (VT == MVT::i16)
+if (VT == MVT::v16i1 || VT == MVT::i16)
return std::make_pair(0U, &X86::VK16RegClass);
}
if (Subtarget.hasBWI()) {
-if (VT == MVT::i32)
+if (VT == MVT::v32i1 || VT == MVT::i32)
return std::make_pair(0U, &X86::VK32RegClass);
-if (VT == MVT::i64)
+if (VT == MVT::v64i1 || VT == MVT::i64)
return std::make_pair(0U, &X86::VK64RegClass);
KanRobert wrote:
Never mind. I see your comment.
https://github.com/llvm/llvm-project/pull/77733
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[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
https://github.com/KanRobert created https://github.com/llvm/llvm-project/pull/78901 None >From 6e490075f52d8b8cefcdde59fe24914b80a64039 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Sun, 21 Jan 2024 22:02:21 +0800 Subject: [PATCH] [X86][Driver] Enable feature ndd for -mapxf --- clang/include/clang/Driver/Options.td | 6 +++--- clang/test/Driver/x86-target-features.c | 4 ++-- clang/test/Preprocessor/x86_target_features.c | 8 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index f1687d823f6e0a..199537404d0c63 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6053,11 +6053,11 @@ def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,cf">; -// Features egpr, push2pop2 and ppx are validated with llvm-test-suite && cpu2017 on Intel SDE. +// Features egpr, push2pop2, ppx and ndd are validated with llvm-test-suite && cpu2017 on Intel SDE. // For stability, we turn on these features only for -mapxf. After a feature pass the validation, // we will add it to -mapxf. -def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; -def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx"]>; +def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx", "ndd"]>; +def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx","ndd"]>; } // let Flags = [TargetSpecific] // VE feature flags diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c index 6fb9df96e2b333..998d5f37da69b4 100644 --- a/clang/test/Driver/x86-target-features.c +++ b/clang/test/Driver/x86-target-features.c @@ -428,8 +428,8 @@ // RUN: %clang -target x86_64-unknown-linux-gnu -mno-apxf -mapxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=APXF %s // RUN: %clang -target x86_64-unknown-linux-gnu -mapxf -mno-apxf %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-APXF %s // -// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" -// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" +// APXF: "-target-feature" "+egpr" "-target-feature" "+push2pop2" "-target-feature" "+ppx" "-target-feature" "+ndd" +// NO-APXF: "-target-feature" "-egpr" "-target-feature" "-push2pop2" "-target-feature" "-ppx" "-target-feature" "-ndd" // RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=egpr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=EGPR %s // RUN: %clang -target x86_64-unknown-linux-gnu -mapx-features=push2pop2 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=PUSH2POP2 %s diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c index 888eecd08d84a2..a1882043910f76 100644 --- a/clang/test/Preprocessor/x86_target_features.c +++ b/clang/test/Preprocessor/x86_target_features.c @@ -803,10 +803,10 @@ // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd -x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-prefix=CCMP %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=cf -x c -E -dM -o - %s | FileCheck --check-prefix=CF %s -// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX %s +// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD %s +// CCMP: #define __CCMP__ 1 +// CF: #define __CF__ 1 // EGPR: #define __EGPR__ 1 +// NDD: #define __NDD__ 1 // PPX: #define __PPX__ 1 // PUSH2POP2: #define __PUSH2POP2__ 1 -// NDD: #define __NDD__ 1 -// CCMP: #define __CCMP__ 1 -// CF: #define __CF__ 1 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
@@ -803,10 +803,10 @@ // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd -x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-prefix=CCMP %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=cf -x c -E -dM -o - %s | FileCheck --check-prefix=CF %s -// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX %s +// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD %s +// CCMP: #define __CCMP__ 1 +// CF: #define __CF__ 1 // EGPR: #define __EGPR__ 1 +// NDD: #define __NDD__ 1 // PPX: #define __PPX__ 1 // PUSH2POP2: #define __PUSH2POP2__ 1 KanRobert wrote: I reorder the check b/c the macro is sorted by alphabetical order. https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
@@ -803,10 +803,10 @@ // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd -x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-prefix=CCMP %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=cf -x c -E -dM -o - %s | FileCheck --check-prefix=CF %s -// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX %s +// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD %s +// CCMP: #define __CCMP__ 1 +// CF: #define __CF__ 1 // EGPR: #define __EGPR__ 1 +// NDD: #define __NDD__ 1 // PPX: #define __PPX__ 1 // PUSH2POP2: #define __PUSH2POP2__ 1 KanRobert wrote: B/c we only checked EGPR, PPX, PUSH2POP2 for `-mapxf`. These three `#define` in this file was already in alphabetical order. https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
@@ -803,10 +803,10 @@ // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ndd -x c -E -dM -o - %s | FileCheck --check-prefix=NDD %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=ccmp -x c -E -dM -o - %s | FileCheck --check-prefix=CCMP %s // RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapx-features=cf -x c -E -dM -o - %s | FileCheck --check-prefix=CF %s -// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX %s +// RUN: %clang -target x86_64-unknown-unknown -march=x86-64 -mapxf -x c -E -dM -o - %s | FileCheck --check-prefixes=EGPR,PUSH2POP2,PPX,NDD %s +// CCMP: #define __CCMP__ 1 +// CF: #define __CF__ 1 // EGPR: #define __EGPR__ 1 +// NDD: #define __NDD__ 1 // PPX: #define __PPX__ 1 // PUSH2POP2: #define __PUSH2POP2__ 1 KanRobert wrote: Line 803 checks for NDD, but it doesn't matter b/c it does not check other macros. The order for the macros matters only when we need to check several macros in one RUN line. https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
KanRobert wrote: Thanks! @phoebewang https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86][Driver] Enable feature ndd for -mapxf (PR #78901)
https://github.com/KanRobert closed https://github.com/llvm/llvm-project/pull/78901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] be08e45 - [X86][MS-InlineAsm] Add constraint *m for memory access w/ global var
Author: Shengchen Kan
Date: 2021-11-05T09:11:41+08:00
New Revision: be08e452f36602cd73f816787bf16d1a0405ff09
URL:
https://github.com/llvm/llvm-project/commit/be08e452f36602cd73f816787bf16d1a0405ff09
DIFF:
https://github.com/llvm/llvm-project/commit/be08e452f36602cd73f816787bf16d1a0405ff09.diff
LOG: [X86][MS-InlineAsm] Add constraint *m for memory access w/ global var
Constraint `*m` should be used when the address of a variable is passed
as a value. And the constraint is missing for MS inline assembly when sth
is written to the address of the variable.
The missing would cause FE delete the definition of the static varible,
and then result in "undefined reference to xxx" issue.
Reviewed By: xiangzhangllvm
Differential Revision: https://reviews.llvm.org/D113096
Added:
clang/test/CodeGen/ms-inline-asm-static-variable.c
llvm/test/CodeGen/X86/ms-inline-asm-array.ll
Modified:
clang/test/CodeGen/X86/ms_fmul.c
clang/test/CodeGen/ms-inline-asm-variables.c
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
Removed:
diff --git a/clang/test/CodeGen/X86/ms_fmul.c
b/clang/test/CodeGen/X86/ms_fmul.c
index a0a1be9e217c5..d1cfcef814625 100644
--- a/clang/test/CodeGen/X86/ms_fmul.c
+++ b/clang/test/CodeGen/X86/ms_fmul.c
@@ -18,4 +18,4 @@ void __attribute__ ((naked)) foo(void)
}}
// CHECK-LABEL: foo
-// CHECK: call void asm sideeffect inteldialect "fmul qword ptr
static_const_table[edx + $$240]\0A\09ret"
+// CHECK: call void asm sideeffect inteldialect "fmul qword ptr $0[edx +
$$240]\0A\09ret"
diff --git a/clang/test/CodeGen/ms-inline-asm-static-variable.c
b/clang/test/CodeGen/ms-inline-asm-static-variable.c
new file mode 100644
index 0..fb80bf7b2f74f
--- /dev/null
+++ b/clang/test/CodeGen/ms-inline-asm-static-variable.c
@@ -0,0 +1,10 @@
+// REQUIRES: x86-registered-target
+// Check the constraint "*m" of operand arr and the definition of arr is not
removed by FE
+// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o -
| FileCheck %s
+
+static int arr[10];
+void t1() {
+ // CHECK: @arr = internal global [10 x i32]
+ // CHECK: call void asm sideeffect inteldialect "mov dword ptr $0[edx *
$$4],edx", "=*m,{{.*}}([10 x i32]* @arr)
+ __asm mov dword ptr arr[edx*4],edx
+}
diff --git a/clang/test/CodeGen/ms-inline-asm-variables.c
b/clang/test/CodeGen/ms-inline-asm-variables.c
index f8fd227610b64..7d0cb3fbcc8f8 100644
--- a/clang/test/CodeGen/ms-inline-asm-variables.c
+++ b/clang/test/CodeGen/ms-inline-asm-variables.c
@@ -3,19 +3,19 @@
int gVar;
void t1() {
- // CHECK: add eax, dword ptr gVar[eax]
+ // CHECK: add eax, dword ptr ${{[0-9]}}[eax]
__asm add eax, dword ptr gVar[eax]
- // CHECK: add dword ptr gVar[eax], eax
+ // CHECK: add dword ptr ${{[0-9]}}[eax], eax
__asm add dword ptr [eax+gVar], eax
- // CHECK: add ebx, dword ptr gVar[ebx + $$270]
+ // CHECK: add ebx, dword ptr ${{[0-9]}}[ebx + $$270]
__asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
- // CHECK: add dword ptr gVar[ebx + $$828], ebx
+ // CHECK: add dword ptr ${{[0-9]}}[ebx + $$828], ebx
__asm add dword ptr [ebx + gVar + 828], ebx
- // CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
+ // CHECK: add ecx, dword ptr ${{[0-9]}}[ecx + ecx * $$4 + $$4590]
__asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
- // CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
+ // CHECK: add dword ptr ${{[0-9]}}[ecx + ecx * $$8 + $$73], ecx
__asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
- // CHECK: add gVar[ecx + ebx + $$7], eax
+ // CHECK: add ${{[0-9]}}[ecx + ebx + $$7], eax
__asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
}
@@ -32,4 +32,3 @@ void t2() {
// CHECK: mov ${{[0-9]}}[ebx + $$47], eax
__asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
}
-
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 511d263abbaab..88b993fb827c8 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1758,8 +1758,8 @@ bool X86AsmParser::CreateMemForMSInlineAsm(
// It is widely common for MS InlineAsm to use a global variable and one/two
// registers in a mmory expression, and though unaccessible via rip/eip.
if (IsGlobalLV && (BaseReg || IndexReg)) {
-Operands.push_back(
-X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size));
+Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
+ End, Size, Identifier, Decl));
return false;
}
// Otherwise, we set the base register to a non-zero value
@@ -2551,6 +2551,8 @@ bool X86AsmParser::ParseIntelOperand(OperandVector
&Operands) {
StringRef ErrMsg;
unsigned BaseReg = SM.getBaseReg();
unsigned IndexReg = SM.getIndexReg();
+ if (IndexReg && BaseReg == X86::RIP)
+BaseReg = 0
[clang] [X86] Align 128/256 variants to use void * as 512 variants. (PR #66310)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/66310 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Add USER_MSR instructions. (PR #68944)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68944 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [X86] Align 128/256 variants to use void * as 512 variants. (PR #66310)
@@ -1223,6 +1223,12 @@ __m256i test_mm256_stream_load_si256(__m256i const *a) {
return _mm256_stream_load_si256(a);
}
+__m256i test_mm256_stream_load_si256_const(void const *a) {
KanRobert wrote:
+1
https://github.com/llvm/llvm-project/pull/66310
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[clang] 6a3506a - [Driver][X86] Add helptext for malign-branch*, mbranches-within-32B-boundaries
Author: Shengchen Kan Date: 2020-02-24T13:45:27+08:00 New Revision: 6a3506a208b90e65c719b0942376f46902a08945 URL: https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945 DIFF: https://github.com/llvm/llvm-project/commit/6a3506a208b90e65c719b0942376f46902a08945.diff LOG: [Driver][X86] Add helptext for malign-branch*, mbranches-within-32B-boundaries Differential Revision: https://reviews.llvm.org/D75017 Added: Modified: clang/include/clang/Driver/Options.td Removed: diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 358540b03d80..f1801e3e89e7 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2166,10 +2166,13 @@ def mno_iamcu : Flag<["-"], "mno-iamcu">, Group, Flags<[DriverOption, C def malign_functions_EQ : Joined<["-"], "malign-functions=">, Group; def malign_loops_EQ : Joined<["-"], "malign-loops=">, Group; def malign_jumps_EQ : Joined<["-"], "malign-jumps=">, Group; -def malign_branch_EQ : CommaJoined<["-"], "malign-branch=">, Group; -def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group; +def malign_branch_EQ : CommaJoined<["-"], "malign-branch=">, Group, Flags<[DriverOption]>, + HelpText<"Specify types of branches to align">; +def malign_branch_boundary_EQ : Joined<["-"], "malign-branch-boundary=">, Group, Flags<[DriverOption]>, + HelpText<"Specify the boundary's size to align branches">; def malign_branch_prefix_size_EQ : Joined<["-"], "malign-branch-prefix-size=">, Group; -def mbranches_within_32B_boundaries : Flag<["-"], "mbranches-within-32B-boundaries">, Flags<[DriverOption]>, Group; +def mbranches_within_32B_boundaries : Flag<["-"], "mbranches-within-32B-boundaries">, Flags<[DriverOption]>, Group, + HelpText<"Align selected branches (fused, jcc, jmp) within 32-byte boundary">; def mfancy_math_387 : Flag<["-"], "mfancy-math-387">, Group; def mlong_calls : Flag<["-"], "mlong-calls">, Group, HelpText<"Generate branches with extended addressability, usually via indirect jumps.">; ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 560aa53 - [X86] Support intrinsics _bextr2*
Author: Shengchen Kan
Date: 2020-03-12T09:26:51+08:00
New Revision: 560aa53f8fe58abcbc4bb441b631e8a401ee78fe
URL:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe
DIFF:
https://github.com/llvm/llvm-project/commit/560aa53f8fe58abcbc4bb441b631e8a401ee78fe.diff
LOG: [X86] Support intrinsics _bextr2*
Reviewers: LuoYuanke, craig.topper, RKSimon, pengfei
Reviewed By: craig.topper
Subscribers: cfe-commits, llvm-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75894
Added:
Modified:
clang/lib/Headers/bmiintrin.h
clang/test/CodeGen/bmi-builtins.c
Removed:
diff --git a/clang/lib/Headers/bmiintrin.h b/clang/lib/Headers/bmiintrin.h
index 841bd84070e8..937f1683b544 100644
--- a/clang/lib/Headers/bmiintrin.h
+++ b/clang/lib/Headers/bmiintrin.h
@@ -192,6 +192,28 @@ _bextr_u32(unsigned int __X, unsigned int __Y, unsigned
int __Z)
return __builtin_ia32_bextr_u32 (__X, ((__Y & 0xff) | ((__Z & 0xff) << 8)));
}
+/* Intel-specified, single-leading-underscore version of BEXTR2 */
+/// Extracts the specified bits from the first operand and returns them
+///in the least significant bits of the result.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the BEXTR instruction.
+///
+/// \param __X
+///An unsigned integer whose bits are to be extracted.
+/// \param __Y
+///An unsigned integer used to specify which bits are extracted. Bits [7:0]
+///specify the index of the least significant bit. Bits [15:8] specify the
+///number of bits to be extracted.
+/// \returns An unsigned integer whose least significant bits contain the
+///extracted bits.
+/// \see __bextr_u32
+static __inline__ unsigned int __DEFAULT_FN_ATTRS
+_bextr2_u32(unsigned int __X, unsigned int __Y) {
+ return __builtin_ia32_bextr_u32(__X, __Y);
+}
+
/// Clears all bits in the source except for the least significant bit
///containing a value of 1 and returns the result.
///
@@ -321,6 +343,28 @@ _bextr_u64(unsigned long long __X, unsigned int __Y,
unsigned int __Z)
return __builtin_ia32_bextr_u64 (__X, ((__Y & 0xff) | ((__Z & 0xff) << 8)));
}
+/* Intel-specified, single-leading-underscore version of BEXTR2 */
+/// Extracts the specified bits from the first operand and returns them
+///in the least significant bits of the result.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the BEXTR instruction.
+///
+/// \param __X
+///An unsigned 64-bit integer whose bits are to be extracted.
+/// \param __Y
+///An unsigned 64-bit integer used to specify which bits are extracted.
Bits
+///[7:0] specify the index of the least significant bit. Bits [15:8]
specify
+///the number of bits to be extracted.
+/// \returns An unsigned 64-bit integer whose least significant bits contain
the
+///extracted bits.
+/// \see __bextr_u64
+static __inline__ unsigned long long __DEFAULT_FN_ATTRS
+_bextr2_u64(unsigned long long __X, unsigned long long __Y) {
+ return __builtin_ia32_bextr_u64(__X, __Y);
+}
+
/// Clears all bits in the source except for the least significant bit
///containing a value of 1 and returns the result.
///
diff --git a/clang/test/CodeGen/bmi-builtins.c
b/clang/test/CodeGen/bmi-builtins.c
index 9f2d776299f8..409dd40c4a33 100644
--- a/clang/test/CodeGen/bmi-builtins.c
+++ b/clang/test/CodeGen/bmi-builtins.c
@@ -155,6 +155,12 @@ unsigned int test_bextr_u32(unsigned int __X, unsigned int
__Y,
return _bextr_u32(__X, __Y, __Z);
}
+unsigned int test_bextr2_u32(unsigned int __X, unsigned int __Y) {
+ // CHECK-LABEL: test_bextr2_u32
+ // CHECK: i32 @llvm.x86.bmi.bextr.32(i32 %{{.*}}, i32 %{{.*}})
+ return _bextr2_u32(__X, __Y);
+}
+
unsigned int test_blsi_u32(unsigned int __X) {
// CHECK-LABEL: test_blsi_u32
// CHECK: sub i32 0, %{{.*}}
@@ -196,6 +202,13 @@ unsigned long long test_bextr_u64(unsigned long __X,
unsigned int __Y,
return _bextr_u64(__X, __Y, __Z);
}
+unsigned long long test_bextr2_u64(unsigned long long __X,
+ unsigned long long __Y) {
+ // CHECK-LABEL: test_bextr2_u64
+ // CHECK: i64 @llvm.x86.bmi.bextr.64(i64 %{{.*}}, i64 %{{.*}})
+ return _bextr2_u64(__X, __Y);
+}
+
unsigned long long test_blsi_u64(unsigned long long __X) {
// CHECK-LABEL: test_blsi_u64
// CHECK: sub i64 0, %{{.*}}
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[clang] ab69cd0 - [X86] Support intrinsic _mm_cldemote
Author: Shengchen Kan
Date: 2020-03-12T10:03:41+08:00
New Revision: ab69cd0779c529519eb7d26e0fa1b8dfb505f838
URL:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838
DIFF:
https://github.com/llvm/llvm-project/commit/ab69cd0779c529519eb7d26e0fa1b8dfb505f838.diff
LOG: [X86] Support intrinsic _mm_cldemote
Reviewers: LuoYuanke, craig.topper, RKSimon, pengfei
Reviewed By: craig.topper
Subscribers: cfe-commits, llvm-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75896
Added:
Modified:
clang/lib/Headers/cldemoteintrin.h
clang/test/CodeGen/cldemote.c
Removed:
diff --git a/clang/lib/Headers/cldemoteintrin.h
b/clang/lib/Headers/cldemoteintrin.h
index 2413e7dea7a1..cfb951c1b4a9 100644
--- a/clang/lib/Headers/cldemoteintrin.h
+++ b/clang/lib/Headers/cldemoteintrin.h
@@ -18,11 +18,19 @@
#define __DEFAULT_FN_ATTRS \
__attribute__((__always_inline__, __nodebug__, __target__("cldemote")))
+/// Hint to hardware that the cache line that contains \p __P should be demoted
+/// from the cache closest to the processor core to a level more distant from
+/// the processor core.
+///
+/// \headerfile
+///
+/// This intrinsic corresponds to the CLDEMOTE instruction.
static __inline__ void __DEFAULT_FN_ATTRS
_cldemote(const void * __P) {
__builtin_ia32_cldemote(__P);
}
+#define _mm_cldemote(p) _cldemote(p)
#undef __DEFAULT_FN_ATTRS
#endif
diff --git a/clang/test/CodeGen/cldemote.c b/clang/test/CodeGen/cldemote.c
index 8c7bdf539333..f5f7ad9f27ea 100644
--- a/clang/test/CodeGen/cldemote.c
+++ b/clang/test/CodeGen/cldemote.c
@@ -7,4 +7,6 @@ void test_cldemote(const void *p) {
//CHECK-LABEL: @test_cldemote
//CHECK: call void @llvm.x86.cldemote(i8* %{{.*}})
_cldemote(p);
+ //CHECK: call void @llvm.x86.cldemote(i8* %{{.*}})
+ _mm_cldemote(p);
}
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[clang] 214d24e - [X86] Support intrinsic _mm_broadcastsi128_si256
Author: Shengchen Kan
Date: 2020-03-12T10:56:39+08:00
New Revision: 214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
URL:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd
DIFF:
https://github.com/llvm/llvm-project/commit/214d24e1f8e0737a5aa2e2c52a1ae095fb1c1abd.diff
LOG: [X86] Support intrinsic _mm_broadcastsi128_si256
Reviewers: LuoYuanke, craig.topper, RKSimon, pengfei
Reviewed By: craig.topper
Subscribers: cfe-commits, llvm-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75897
Added:
Modified:
clang/lib/Headers/avx2intrin.h
clang/test/CodeGen/avx2-builtins.c
Removed:
diff --git a/clang/lib/Headers/avx2intrin.h b/clang/lib/Headers/avx2intrin.h
index 162e83ea2fbc..cc16720949ea 100644
--- a/clang/lib/Headers/avx2intrin.h
+++ b/clang/lib/Headers/avx2intrin.h
@@ -740,6 +740,8 @@ _mm256_broadcastsi128_si256(__m128i __X)
return (__m256i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 1, 0,
1);
}
+#define _mm_broadcastsi128_si256(X) _mm256_broadcastsi128_si256(X)
+
#define _mm_blend_epi32(V1, V2, M) \
(__m128i)__builtin_ia32_pblendd128((__v4si)(__m128i)(V1), \
(__v4si)(__m128i)(V2), (int)(M))
diff --git a/clang/test/CodeGen/avx2-builtins.c
b/clang/test/CodeGen/avx2-builtins.c
index f4c1c3cf4f35..95659895eeaf 100644
--- a/clang/test/CodeGen/avx2-builtins.c
+++ b/clang/test/CodeGen/avx2-builtins.c
@@ -208,6 +208,12 @@ __m256i test_mm256_broadcastsi128_si256(__m128i a) {
return _mm256_broadcastsi128_si256(a);
}
+__m256i test_mm_broadcastsi128_si256(__m128i a) {
+ // CHECK-LABEL: test_mm_broadcastsi128_si256
+ // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <4 x i32>
+ return _mm_broadcastsi128_si256(a);
+}
+
__m128 test_mm_broadcastss_ps(__m128 a) {
// CHECK-LABEL: test_mm_broadcastss_ps
// CHECK-NOT: @llvm.x86.avx2.vbroadcast.ss.ps
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[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -983,6 +983,8 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, setFeature(FEATURE_USERMSR); if (HasLeaf7Subleaf1 && ((EDX >> 19) & 1)) setFeature(FEATURE_AVX10_1_256); + if (HasLeaf7Subleaf1 && ((EDX >> 21) & 1)) KanRobert wrote: Add SPEC sentence in your description. https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64", 95) X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96) X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97) X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98) +X86_MICROARCH_LEVEL(APXF, "apxf",111) KanRobert wrote: Where is 111 from? https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -219,6 +219,7 @@ #define bit_PREFETCHI 0x4000 #define bit_USERMSR 0x8000 #define bit_AVX10 0x0008 +#define bit_APXF 0x0020 KanRobert wrote: Where is the number from? Add the link in your description of the PR. https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
@@ -265,6 +265,7 @@ X86_MICROARCH_LEVEL(X86_64_BASELINE,"x86-64", 95) X86_MICROARCH_LEVEL(X86_64_V2, "x86-64-v2",96) X86_MICROARCH_LEVEL(X86_64_V3, "x86-64-v3",97) X86_MICROARCH_LEVEL(X86_64_V4, "x86-64-v4",98) +X86_MICROARCH_LEVEL(APXF, "apxf",111) KanRobert wrote: Add the link in the description? https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [compiler-rt] [llvm] [X86] Support APXF to enable __builtin_cpu_supports. (PR #80636)
https://github.com/KanRobert approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/80636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver][X86] Add flang visibility for -mapx-features= (PR #97525)
https://github.com/KanRobert created https://github.com/llvm/llvm-project/pull/97525 None >From 1aab0a95629371c61273c80f6335a6723c7d27c4 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Wed, 3 Jul 2024 11:30:47 +0800 Subject: [PATCH] [Driver][X86] Add flang visibility for -mapx-features= --- clang/include/clang/Driver/Options.td | 2 +- flang/test/Driver/target-cpu-features.f90 | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1c2b8cfeef6ce..e1e6a6e3a0fcd 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6319,7 +6319,7 @@ def mno_gather : Flag<["-"], "mno-gather">, Group, def mno_scatter : Flag<["-"], "mno-scatter">, Group, HelpText<"Disable generation of scatter instructions in auto-vectorization(x86 only)">; def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, -HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">; +HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption, CLOption, FlangOption]>; def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">; // For stability, we only add a feature to -mapxf after it passes the validation of llvm-test-suite && cpu2017 on Intel SDE. diff --git a/flang/test/Driver/target-cpu-features.f90 b/flang/test/Driver/target-cpu-features.f90 index e78c3516db45a..2728fb90afa41 100644 --- a/flang/test/Driver/target-cpu-features.f90 +++ b/flang/test/Driver/target-cpu-features.f90 @@ -17,6 +17,9 @@ ! RUN: %flang --target=x86_64-linux-gnu -march=skylake -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-SKYLAKE +! RUN: %flang --target=x86_64-linux-gnu -mapx-features=egpr -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-APX + ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H @@ -51,6 +54,9 @@ ! CHECK-SKYLAKE: "-fc1" "-triple" "x86_64-unknown-linux-gnu" ! CHECK-SKYLAKE-SAME: "-target-cpu" "skylake" +! CHECK-APX: "-fc1" "-triple" "x86_64-unknown-linux-gnu" +! CHECK-APX-SAME: "-target-feature" "+egpr" + ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu" ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase" ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver][X86] Add flang visibility for -mapx-features= (PR #97525)
https://github.com/KanRobert edited https://github.com/llvm/llvm-project/pull/97525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver][X86] Add flang visibility for -mapx-features= (PR #97525)
KanRobert wrote: Also, AArch64 also exposes the tuning flag `msve-vector-bits=` to flang. https://github.com/llvm/llvm-project/pull/97525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang] [Driver][X86] Add flang visibility for -mapx-features= (PR #97525)
https://github.com/KanRobert updated https://github.com/llvm/llvm-project/pull/97525 >From 1aab0a95629371c61273c80f6335a6723c7d27c4 Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Wed, 3 Jul 2024 11:30:47 +0800 Subject: [PATCH 1/2] [Driver][X86] Add flang visibility for -mapx-features= --- clang/include/clang/Driver/Options.td | 2 +- flang/test/Driver/target-cpu-features.f90 | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 1c2b8cfeef6ce..e1e6a6e3a0fcd 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6319,7 +6319,7 @@ def mno_gather : Flag<["-"], "mno-gather">, Group, def mno_scatter : Flag<["-"], "mno-scatter">, Group, HelpText<"Disable generation of scatter instructions in auto-vectorization(x86 only)">; def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, -HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">; +HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption, CLOption, FlangOption]>; def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">; // For stability, we only add a feature to -mapxf after it passes the validation of llvm-test-suite && cpu2017 on Intel SDE. diff --git a/flang/test/Driver/target-cpu-features.f90 b/flang/test/Driver/target-cpu-features.f90 index e78c3516db45a..2728fb90afa41 100644 --- a/flang/test/Driver/target-cpu-features.f90 +++ b/flang/test/Driver/target-cpu-features.f90 @@ -17,6 +17,9 @@ ! RUN: %flang --target=x86_64-linux-gnu -march=skylake -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-SKYLAKE +! RUN: %flang --target=x86_64-linux-gnu -mapx-features=egpr -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-APX + ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H @@ -51,6 +54,9 @@ ! CHECK-SKYLAKE: "-fc1" "-triple" "x86_64-unknown-linux-gnu" ! CHECK-SKYLAKE-SAME: "-target-cpu" "skylake" +! CHECK-APX: "-fc1" "-triple" "x86_64-unknown-linux-gnu" +! CHECK-APX-SAME: "-target-feature" "+egpr" + ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu" ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase" >From ba538ee16385bdedfae770b712646546dfc6b54c Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Wed, 3 Jul 2024 15:32:04 +0800 Subject: [PATCH 2/2] minor improve --- clang/include/clang/Driver/Options.td | 2 +- flang/test/Driver/target-cpu-features.f90 | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index e1e6a6e3a0fcd..1ede75d3782cd 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6321,7 +6321,7 @@ def mno_scatter : Flag<["-"], "mno-scatter">, Group, def mapx_features_EQ : CommaJoined<["-"], "mapx-features=">, Group, HelpText<"Enable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption, CLOption, FlangOption]>; def mno_apx_features_EQ : CommaJoined<["-"], "mno-apx-features=">, Group, -HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">; +HelpText<"Disable features of APX">, Values<"egpr,push2pop2,ppx,ndd,ccmp,nf,cf,zu">, Visibility<[ClangOption, CLOption, FlangOption]>; // For stability, we only add a feature to -mapxf after it passes the validation of llvm-test-suite && cpu2017 on Intel SDE. def mapxf : Flag<["-"], "mapxf">, Alias, AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","nf","cf"]>; def mno_apxf : Flag<["-"], "mno-apxf">, Alias, AliasArgs<["egpr","push2pop2","ppx","ndd","ccmp","nf","cf"]>; diff --git a/flang/test/Driver/target-cpu-features.f90 b/flang/test/Driver/target-cpu-features.f90 index 2728fb90afa41..0f19e4ebff2a0 100644 --- a/flang/test/Driver/target-cpu-features.f90 +++ b/flang/test/Driver/target-cpu-features.f90 @@ -20,6 +20,9 @@ ! RUN: %flang --target=x86_64-linux-gnu -mapx-features=egpr -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-APX +! RUN: %flang --target=x86_64-linux-gnu -mno-apx-features=ccmp -c %s -### 2>&1 \ +! RUN: | FileCheck %s -check-prefix=CHECK-NO-APX + ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H @@ -57,6 +60,9 @@ ! CHECK-APX: "-fc1" "-triple" "x86_64-unknown-linux-gnu" ! CHECK-APX-SAME: "-target-feature" "+egpr" +! CHECK-NO-APX: "-fc1" "-triple" "x86_64-unknown-linux-gnu" +! CHECK-NO-APX-SAME: "-target-feature" "-ccmp" + ! CHECK-X86_64H: "-fc1" "-triple
[clang] [flang] [Driver][X86] Add flang visibility for -mapx-features= (PR #97525)
https://github.com/KanRobert closed https://github.com/llvm/llvm-project/pull/97525 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support branch hint (PR #97721)
@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true", "Use Goldmont specific floating point div/sqrt costs">; +// Starting with Redwood Cove architecture, the branch has branch taken hint +// (i.e., instruction prefix 3EH). +def TuningBranchHint: SubtargetFeature<"branch-hint", "HasBranchHint", "true", KanRobert wrote: We can always add `0x3e` to JCC in 64-bit mode. So it does work on all applicable CPUs. https://github.com/llvm/llvm-project/pull/97721 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support branch hint (PR #97721)
@@ -749,6 +749,11 @@ def TuningUseGLMDivSqrtCosts : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true", "Use Goldmont specific floating point div/sqrt costs">; +// Starting with Redwood Cove architecture, the branch has branch taken hint +// (i.e., instruction prefix 3EH). +def TuningBranchHint: SubtargetFeature<"branch-hint", "HasBranchHint", "true", KanRobert wrote: See Intel SDM ``` — Branch hints1: • 2EH—Branch not taken (used only with Jcc instructions). • 3EH—Branch taken (used only with Jcc instructions). 1. Some earlier microarchitectures used these as branch hints, but recent generations have not and they are reserved for future hint usage. ``` https://github.com/llvm/llvm-project/pull/97721 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support branch hint (PR #97721)
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -branch-hint
-branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s
+
+; Design: Insert "ds # encoding: [0x3e]" for condition branches who has high
probability to take.
+; Source code:
+; int XX = 0;
+; int bar(int x);
+; void foo(int a, int b, char* c) {
+; if (a == 0) {
+; XX += 1;
+; } else {
+; if (c == 0)
+; XX += 2;
+; }
+; for(int i=0; ihttps://github.com/llvm/llvm-project/pull/97721
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[clang] [llvm] [X86] Support branch hint (PR #97721)
@@ -0,0 +1,95 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-linux -branch-hint -branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s + +; Design: Insert "ds # encoding: [0x3e]" for condition branches who has high probability to take. KanRobert wrote: Maybe `branches who has` -> `branch which has`? https://github.com/llvm/llvm-project/pull/97721 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [X86] Support branch hint (PR #97721)
@@ -0,0 +1,95 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-linux -branch-hint -branch-hint-probability-threshold=60 -show-mc-encoding | FileCheck %s + +; Design: Insert "ds # encoding: [0x3e]" for condition branches who has high probability to take. KanRobert wrote: `Insert "ds # encoding: [0x3e]"` -> `Add DS segment override prefix` ? https://github.com/llvm/llvm-project/pull/97721 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
