[PATCH] D61774: [LibTooling] Add RangeSelector library for defining source ranges based on bound AST nodes.

2019-05-22 Thread Petr Penzin via Phabricator via cfe-commits 
penzn added inline comments.



Comment at: cfe/trunk/lib/Tooling/Refactoring/RangeSelector.cpp:229
+RangeSelector tooling::statements(StringRef ID) {
+  return RelativeSelector(ID);
+}

Sorry for posting here, haven't gotten my bugzilla access yet (requested 
though).

This breaks with Visual Studio 2017 (15.7.6):

RangeSelector.cpp(229): error C2971: '`anonymous-namespace'::RelativeSelector': 
template parameter 'Func': 'getStatementsRange': a variable with non-static 
storage duration cannot be used as a non-type argument


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[PATCH] D61774: [LibTooling] Add RangeSelector library for defining source ranges based on bound AST nodes.

2019-05-23 Thread Petr Penzin via Phabricator via cfe-commits 
penzn marked an inline comment as done.
penzn added inline comments.



Comment at: cfe/trunk/lib/Tooling/Refactoring/RangeSelector.cpp:229
+RangeSelector tooling::statements(StringRef ID) {
+  return RelativeSelector(ID);
+}

penzn wrote:
> Sorry for posting here, haven't gotten my bugzilla access yet (requested 
> though).
> 
> This breaks with Visual Studio 2017 (15.7.6):
> 
> RangeSelector.cpp(229): error C2971: 
> '`anonymous-namespace'::RelativeSelector': template parameter 'Func': 
> 'getStatementsRange': a variable with non-static storage duration cannot be 
> used as a non-type argument
Fixed in https://reviews.llvm.org/D62202


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[PATCH] D140773: [WebAssembly] Use `shufflevector` for shuffle

2022-12-29 Thread Petr Penzin via Phabricator via cfe-commits 
penzn created this revision.
penzn added a reviewer: tlively.
Herald added subscribers: pmatos, asb, ecnelises, sunfish, hiraditya, 
jgravelle-google, sbc100, dschuff.
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penzn requested review of this revision.
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Herald added projects: clang, LLVM.

Back out D66983 , "[WebAssembly] Add 
wasm-specific vector shuffle builtin and
intrinsic".

  

Fix shuffle intrinsic tests. Since they are compiled with -O2 masks need to be
updated as well, otherwise optimizer would replace second operand with
`poison`.

  

Fix shuffle codegen tests. They require some mask updates to avoid invalid
`shufflevector` use and to make sure both operands get picked up.

  

This reverts commit 8e3e56f2a36701480eeb65e426701d5a9025cc59 
.


Repository:
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https://reviews.llvm.org/D140773

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/wasm_simd128.h
  clang/test/CodeGen/builtins-wasm.c
  clang/test/Headers/wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -154,15 +154,10 @@
 ; NO-CHECK-NOT: i8x16
 ; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
+; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.shuffle(
-  <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
-  i32, i32, i32, i32, i32)
 define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
-  i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
-  i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35)
+  %res = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> 
   ret <16 x i8> %res
 }
 
@@ -170,13 +165,13 @@
 ; NO-CHECK-NOT: i8x16
 ; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
+; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
+  %res = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <
   i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
   i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
-  i32 undef, i32 undef, i32 undef, i32 2)
+  i32 undef, i32 undef, i32 undef, i32 25>
   ret <16 x i8> %res
 }
 
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1806,24 +1806,6 @@
 SDValue Node = DAG.getTargetExternalSymbol(SymName, PtrVT);
 return DAG.getNode(WebAssemblyISD::Wrapper, DL, PtrVT, Node);
   }
-
-  case Intrinsic::wasm_shuffle: {
-// Drop in-chain and replace undefs, but otherwise pass through unchanged
-SDValue Ops[18];
-size_t OpIdx = 0;
-Ops[OpIdx++] = Op.getOperand(1);
-Ops[OpIdx++] = Op.getOperand(2);
-while (OpIdx < 18) {
-  const SDValue &MaskIdx = Op.getOperand(OpIdx + 1);
-  if (MaskIdx.isUndef() ||
-  cast(MaskIdx.getNode())->getZExtValue() >= 32) {
-Ops[OpIdx++] = DAG.getConstant(0, DL, MVT::i32);
-  } else {
-Ops[OpIdx++] = MaskIdx;
-  }
-}
-return DAG.getNode(WebAssemblyISD::SHUFFLE, DL, Op.getValueType(), Ops);
-  }
   }
 }
 
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -168,14 +168,6 @@
   DefaultAttrsIntrinsic<[llvm_v16i8_ty],
 [llvm_v16i8_ty, llvm_v16i8_ty],
 [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_shuffle :
-  DefaultAttrsIntrinsic<[llvm_v16i8_ty],
-[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty,
- llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
- llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
- llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm

[PATCH] D140773: [WebAssembly] Use `shufflevector` for shuffle

2022-12-29 Thread Petr Penzin via Phabricator via cfe-commits 
penzn added a comment.

I still need to run a few external tests, like the ones mentioned in

https://github.com/emscripten-core/emscripten/issues/9340
https://github.com/WebAssembly/simd/issues/196


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[PATCH] D140773: [WebAssembly] Use `shufflevector` for shuffle

2023-01-05 Thread Petr Penzin via Phabricator via cfe-commits 
penzn updated this revision to Diff 486636.
penzn edited the summary of this revision.

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Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/wasm_simd128.h
  clang/test/CodeGen/builtins-wasm.c
  clang/test/Headers/wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/CodeGen/WebAssembly/simd-shuffle.ll

Index: llvm/test/CodeGen/WebAssembly/simd-shuffle.ll
===
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/simd-shuffle.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s
+
+; Test SIMD128 shuffle lowering.
+
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: shuffle_v16i8:
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %res = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> 
+  ret <16 x i8> %res
+}
+
+; CHECK-LABEL: shuffle_undef_v16i8:
+; NO-CHECK-NOT: i8x16
+; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
+  %res = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <
+  i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
+  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
+  i32 undef, i32 undef, i32 undef, i32 25>
+  ret <16 x i8> %res
+}
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -150,36 +150,6 @@
   ret <16 x i8> %a
 }
 
-; CHECK-LABEL: shuffle_v16i8:
-; NO-CHECK-NOT: i8x16
-; CHECK-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; CHECK-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.shuffle(
-  <16 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32,
-  i32, i32, i32, i32, i32)
-define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
-  i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
-  i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 35)
-  ret <16 x i8> %res
-}
-
-; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-CHECK-NOT: i8x16
-; CHECK-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
-; CHECK-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %res = call <16 x i8> @llvm.wasm.shuffle(<16 x i8> %x, <16 x i8> %y,
-  i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
-  i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef,
-  i32 undef, i32 undef, i32 undef, i32 2)
-  ret <16 x i8> %res
-}
-
 ; CHECK-LABEL: laneselect_v16i8:
 ; CHECK-NEXT: .functype laneselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.relaxed_laneselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
===
--- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -1806,24 +1806,6 @@
 SDValue Node = DAG.getTargetExternalSymbol(SymName, PtrVT);
 return DAG.getNode(WebAssemblyISD::Wrapper, DL, PtrVT, Node);
   }
-
-  case Intrinsic::wasm_shuffle: {
-// Drop in-chain and replace undefs, but otherwise pass through unchanged
-SDValue Ops[18];
-size_t OpIdx = 0;
-Ops[OpIdx++] = Op.getOperand(1);
-Ops[OpIdx++] = Op.getOperand(2);
-while (OpIdx < 18) {
-  const SDValue &MaskIdx = Op.getOperand(OpIdx + 1);
-  if (MaskIdx.isUndef() ||
-  cast(MaskIdx.getNode())->getZExtValue() >= 32) {
-Ops[OpIdx++] = DAG.getCo

[PATCH] D140773: [WebAssembly] Use `shufflevector` for shuffle

2023-01-05 Thread Petr Penzin via Phabricator via cfe-commits 
penzn marked an inline comment as done.
penzn added a comment.

Moved the test out.




Comment at: llvm/test/CodeGen/WebAssembly/simd-shuffle.ll:1-2
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs 
-disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals 
-wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs 
-disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals 
-wasm-keep-registers -mattr=+simd128,+relaxed-simd -fast-isel | FileCheck %s
+

Do we need both isel options? I felt bad about removing a test, but we don't 
check anything specific to the first run line.


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[PATCH] D101112: [WebAssembly] Finalize wasm_simd128.h intrinsics

2021-04-22 Thread Petr Penzin via Phabricator via cfe-commits 
penzn accepted this revision.
penzn added a comment.
This revision is now accepted and ready to land.

Looks good to me.


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[PATCH] D101684: [WebAssembly] Add end-to-end codegen tests for wasm_simd128.h

2021-05-04 Thread Petr Penzin via Phabricator via cfe-commits 
penzn added a comment.

I think there is another dimension to this aside from project composition - 
intrinsics have a tendency to "interact" with their surroundings, and it better 
to capture the IR rather than the end result. Even if we can verify that simple 
calls produce instructions we expect, this might not hold true is the arguments 
change, or the call is in a different context. IR definitely gives more 
opportunities to test things through.


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