[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 220675.
mbrkusanin added a comment.
Herald added subscribers: lldb-commits, cfe-commits, seiya, lenary, rupprecht, 
jrtc27, hiraditya.
Herald added projects: clang, LLDB.

- MCTargetOptions is now always passed to MCAsmInfo (or rather 
createMCAsmInfo). In places where we it wasn't available before we simply pass 
empty MCTargetOptions.
- Patch is now for monorepo. Besides LLVM there are now changes to Clang and 
LLDB. I needed to use monorepo to test if everything builds correctly. If this 
is accepted I will split it into separate patches if needed.
- Also it might be best to split this into two changes. First one that adds 
MCTargetOptions to MCAsmInfo and second one that fixes prefix for Mips which is 
what I set out to solve.




Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D66795/new/

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Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MC

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

In D66795#1650305 , @atanasyan wrote:

> But take a look at `LLVMCreateDisasmCPUFeatures` function from 
> `Disassembler.cpp`. If we cannot retrieve `MCTargetOptions` right in this 
> function, we will have to change "LLVM-C" interface 
> `LLVMCreateDisasmCPUFeatures` function.


As far as I can tell there is currently no way to specify ABI from C interface. 
So I just made empty `MCTargetOptions`. Same with other cases where it was 
needed. Some places like `llvm-mca.cpp` had required options available so there 
we could initialize `MCTargetOptions`.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

Any comment on whether we should split this into two patches? One that adds 
`MCTargetOptions` to `MCAsmInfo` and another one that just fixes prefixes for 
Mips.


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[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 220830.
mbrkusanin added a comment.

- `MipsMCAsmInfo()` now always reads ABI from `MipsABIInfo` instead of `Triple`.


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Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
@@ -37,7 +38,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(Triple));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple, MCOptions));
 Ctx = std::make_unique(MAI.get(), MRI.get(), nullptr);
   }
 
Index: llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
===

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 221931.
mbrkusanin added reviewers: echristo, craig.topper, uweigand, tstellar, 
dylanmckay, petecoup.
mbrkusanin added a comment.

- rebase


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Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
@@ -37,7 +38,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(Triple));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple, MCOptions));
 Ctx = std::make_unique(MAI.get(), MRI.get(), nullptr);
   }
 
Index: llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

@echristo @craig.topper @uweigand @tstellar @dylanmckay @petecoup
Do you have any comments on the current patch?


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[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 222832.
mbrkusanin added a comment.

- rebase


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Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
@@ -37,7 +38,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(Triple));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple, MCOptions));
 Ctx = std::make_unique(MAI.get(), MRI.get(), nullptr);
   }
 
Index: llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
===
--- llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cp

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 224603.
mbrkusanin added a comment.

- Rebase
- Ping

@echristo @craig.topper @tstellar @dylanmckay @petecoup
If there are no objections then I'll split this into llvm, clang and lldb 
patches and commit them next week.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66795/new/

https://reviews.llvm.org/D66795

Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
@@ -37,7 +38,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(Triple));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple, MCOptions));
 Ctx = std::make_unique(MAI.get(), MRI.get(), nullptr);
   }
 
Index: llvm/unittests/Exe

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Mirko Brkusanin via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG4b63ca1379a8: [Mips] Use appropriate private label prefix 
based on Mips ABI (authored by mbrkusanin).

Changed prior to commit:
  https://reviews.llvm.org/D66795?vs=224603&id=226112#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D66795

Files:
  clang/lib/Parse/ParseStmtAsm.cpp
  clang/tools/driver/cc1as_main.cpp
  lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp
  lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
  lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
  llvm/include/llvm/Support/TargetRegistry.h
  llvm/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/lib/MC/MCDisassembler/Disassembler.cpp
  llvm/lib/Object/ModuleSymbolTable.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h
  llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
  llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h
  llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.cpp
  llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
  llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
  llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
  llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
  llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h
  llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp
  llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp
  llvm/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll
  llvm/test/MC/Mips/macro-li.d.s
  llvm/test/MC/Mips/macro-li.s.s
  llvm/test/MC/Mips/private-prefix.s
  llvm/tools/dsymutil/DwarfStreamer.cpp
  llvm/tools/llvm-cfi-verify/lib/FileAnalysis.cpp
  llvm/tools/llvm-dwp/llvm-dwp.cpp
  llvm/tools/llvm-exegesis/lib/Analysis.cpp
  llvm/tools/llvm-jitlink/llvm-jitlink.cpp
  llvm/tools/llvm-mc-assemble-fuzzer/llvm-mc-assemble-fuzzer.cpp
  llvm/tools/llvm-mc/Disassembler.cpp
  llvm/tools/llvm-mc/Disassembler.h
  llvm/tools/llvm-mc/llvm-mc.cpp
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/tools/llvm-objdump/MachODump.cpp
  llvm/tools/llvm-objdump/llvm-objdump.cpp
  llvm/tools/llvm-rtdyld/llvm-rtdyld.cpp
  llvm/tools/sancov/sancov.cpp
  llvm/unittests/DebugInfo/DWARF/DwarfGenerator.cpp
  llvm/unittests/ExecutionEngine/JITLink/JITLinkTestCommon.cpp
  llvm/unittests/MC/DwarfLineTables.cpp
  llvm/unittests/MC/MCInstPrinter.cpp

Index: llvm/unittests/MC/MCInstPrinter.cpp
===
--- llvm/unittests/MC/MCInstPrinter.cpp
+++ llvm/unittests/MC/MCInstPrinter.cpp
@@ -9,6 +9,7 @@
 #include "llvm/MC/MCInstPrinter.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
@@ -40,7 +41,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(TripleName));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
 MII.reset(TheTarget->createMCInstrInfo());
 Printer.reset(TheTarget->createMCInstPrinter(
 Triple(TripleName), MAI->getAssemblerDialect(), *MAI, *MII, *MRI));
Index: llvm/unittests/MC/DwarfLineTables.cpp
===
--- llvm/unittests/MC/DwarfLineTables.cpp
+++ llvm/unittests/MC/DwarfLineTables.cpp
@@ -12,6 +12,7 @@
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDwarf.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCTargetOptions.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "gtest/gtest.h"
@@ -37,7 +38,8 @@
   return;
 
 MRI.reset(TheTarget->createMCRegInfo(Triple));
-MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple));
+MCTargetOptions MCOptions;
+MAI.reset(TheTarget->createMCAsmInfo(*MRI, Triple, MCOptions));
 Ctx = std::make_unique(MAI.get

[PATCH] D152206: [Basic] Support 64-bit x86 target for UEFI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added inline comments.



Comment at: llvm/unittests/IR/DataLayoutTest.cpp:109
+TEST(DataLayoutTest, UEFI) {
+  Triple TT = Triple("x86_64-unknown-uefi");
+

This is giving me a linker error:

$ ninja unittests/IR/IRTests
 
/usr/bin/ld: unittests/IR/CMakeFiles/IRTests.dir/DataLayoutTest.cpp.o: 
undefined reference to symbol '_ZN4llvm6TripleC1ERKNS_5TwineE'
/usr/bin/ld: ../build/lib/libLLVMTargetParser.so.18git: error adding 
symbols: DSO missing from command line

Adding TargetParser to link componenets in llvm/unittests/IR/CMakeLists.txt 
seems to fix it for me, but can you check please?


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[PATCH] D152206: [Basic] Support 64-bit x86 target for UEFI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added inline comments.



Comment at: llvm/unittests/IR/DataLayoutTest.cpp:109
+TEST(DataLayoutTest, UEFI) {
+  Triple TT = Triple("x86_64-unknown-uefi");
+

Prabhuk wrote:
> mbrkusanin wrote:
> > This is giving me a linker error:
> > 
> > $ ninja unittests/IR/IRTests
> >  
> > /usr/bin/ld: unittests/IR/CMakeFiles/IRTests.dir/DataLayoutTest.cpp.o: 
> > undefined reference to symbol '_ZN4llvm6TripleC1ERKNS_5TwineE'
> > /usr/bin/ld: ../build/lib/libLLVMTargetParser.so.18git: error adding 
> > symbols: DSO missing from command line
> > 
> > Adding TargetParser to link componenets in llvm/unittests/IR/CMakeLists.txt 
> > seems to fix it for me, but can you check please?
> Thanks for bringing this to my attention. I am able to build and run the IR 
> tests from top of the tree without any failures. Let me take a closer look on 
> how to reproduce this. 
It seems only few buildbots fail with this same error: 
https://lab.llvm.org/buildbot/#/builders/57/builds/30211
Not sure what is common between me and these buildbots.

But I get the same error with lld as well:

ld.lld: error: undefined symbol: llvm::Triple::Triple(llvm::Twine const&)
/>>> referenced by DataLayoutTest.cpp
/>>>   
unittests/IR/CMakeFiles/IRTests.dir/DataLayoutTest.cpp.o:((anonymous 
namespace)::DataLayoutTest_UEFI_Test::TestBody())






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[PATCH] D152206: [Basic] Support 64-bit x86 target for UEFI

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

If there are others experiencing the same error then I can push my fix: 
https://github.com/llvm/llvm-project/pull/67696 if there are no other 
suggestions.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 243153.

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D73644

Files:
  clang/include/clang/Basic/BuiltinsMips.def
  clang/lib/Headers/msa.h
  clang/lib/Sema/SemaChecking.cpp
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.h
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  llvm/test/CodeGen/Mips/msa/ldr_str.ll

Index: llvm/test/CodeGen/Mips/msa/ldr_str.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
+; RUN: llc -march=mips64   -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+
+; Test intrinsics for 4-byte and 8-byte MSA load and stores.
+
+define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 23($5)
+; MIPS32R5-EB-NEXT:lwl $1, 20($5)
+; MIPS32R5-EB-NEXT:# implicit-def: $v0
+; MIPS32R5-EB-NEXT:lwr $2, 19($5)
+; MIPS32R5-EB-NEXT:lwl $2, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:# implicit-def: $v0
+; MIPS32R5-EL-NEXT:lwr $2, 20($5)
+; MIPS32R5-EL-NEXT:lwl $2, 23($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 20($5)
+; MIPS32R6-EB-NEXT:lw $2, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:lw $2, 20($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EL-NEXT:jrc $ra
+;
+; MIPS64R6-LABEL: llvm_mips_ldr_d_test:
+; MIPS64R6:   # %bb.0: # %entry
+; MIPS64R6-NEXT:ld $1, 16($5)
+; MIPS64R6-NEXT:fill.d $w0, $1
+; MIPS64R6-NEXT:st.d $w0, 0($4)
+; MIPS64R6-NEXT:jrc $ra
+entry:
+  %0 = tail call <2 x i64> @llvm.mips.ldr.d(i8* %ptr, i32 16)
+  store <2 x i64> %0, <2 x i64>* %val
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.ldr.d(i8*, i32) nounwind
+
+define void @llvm_mips_ldrq_w_test(<4 x i32>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 19($5)
+; MIPS32R5-EB-NEXT:lwl $1, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:st.w $w0, 0($4)
+; MIPS32R6-EL-NEXT:jrc $ra
+;
+; MIPS64R6-LABEL: llvm_mips_ldrq_w_test:
+; MIPS64R6:   # %bb.0: # %entry
+; MIPS64R6-NEXT:lw $1

[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

Rebase.

Not yet, a proposal was made to both GCC and LLVM and as far as I can tell no 
work was done on that yet. If we accept these names I'll let them know so we 
end up with matching names.

As for 4/8 byte loads, in case of having them implemented as **ld** plus some 
extra instructions, I don't really see the point about making sure those other 
vector elements have same value as first. So if we ignore those we remain with 
only **ld**. In that case we can just not implement these loads and just have 
the user use `__builtin_msa_ld_w` and `__builtin_msa_ld_d` instead. But if we 
do decide to implement them it would make more sense to have them only read 4/8 
bytes instead of all 16. That way you can use both since **ld** is already 
available.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

Not yet, a proposal was made to both GCC and LLVM and as far as I can tell no 
work was done on GCC yet. If we accept these names I'll let them know so we end 
up with matching names.

As for 4/8 byte loads, in case of having them implemented as **ld** plus some 
extra instructions, I don't really see the point about making sure those other 
vector elements have same value as first. So if we ignore those we remain with 
only **ld**. In that case we can just not implement these loads and just have 
the user use `__builtin_msa_ld_w` and `__builtin_msa_ld_d` instead. But if we 
do decide to implement them it would make more sense to have them only read 4/8 
bytes instead of all 16. That way you can use both since **ld** is already 
available.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin updated this revision to Diff 243775.
mbrkusanin edited the summary of this revision.
mbrkusanin added a comment.

- Rebase
- Rename **ldrq_w** to **ldr_w**; Rename **strq_w** to **str_w**.




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Files:
  clang/include/clang/Basic/BuiltinsMips.def
  clang/lib/Headers/msa.h
  clang/lib/Sema/SemaChecking.cpp
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.h
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  llvm/test/CodeGen/Mips/msa/ldr_str.ll

Index: llvm/test/CodeGen/Mips/msa/ldr_str.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
+; RUN: llc -march=mips64   -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+
+; Test intrinsics for 4-byte and 8-byte MSA load and stores.
+
+define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 23($5)
+; MIPS32R5-EB-NEXT:lwl $1, 20($5)
+; MIPS32R5-EB-NEXT:# implicit-def: $v0
+; MIPS32R5-EB-NEXT:lwr $2, 19($5)
+; MIPS32R5-EB-NEXT:lwl $2, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:# implicit-def: $v0
+; MIPS32R5-EL-NEXT:lwr $2, 20($5)
+; MIPS32R5-EL-NEXT:lwl $2, 23($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 20($5)
+; MIPS32R6-EB-NEXT:lw $2, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:lw $2, 20($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EL-NEXT:jrc $ra
+;
+; MIPS64R6-LABEL: llvm_mips_ldr_d_test:
+; MIPS64R6:   # %bb.0: # %entry
+; MIPS64R6-NEXT:ld $1, 16($5)
+; MIPS64R6-NEXT:fill.d $w0, $1
+; MIPS64R6-NEXT:st.d $w0, 0($4)
+; MIPS64R6-NEXT:jrc $ra
+entry:
+  %0 = tail call <2 x i64> @llvm.mips.ldr.d(i8* %ptr, i32 16)
+  store <2 x i64> %0, <2 x i64>* %val
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.ldr.d(i8*, i32) nounwind
+
+define void @llvm_mips_ldr_w_test(<4 x i32>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 19($5)
+; MIPS32R5-EB-NEXT:lwl $1, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:st.w $

[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG5ba931a84a34: [Mips] Add intrinsics for 4-byte and 8-byte 
MSA loads/stores. (authored by mbrkusanin).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/BuiltinsMips.def
  clang/lib/Headers/msa.h
  clang/lib/Sema/SemaChecking.cpp
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.h
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  llvm/test/CodeGen/Mips/msa/ldr_str.ll

Index: llvm/test/CodeGen/Mips/msa/ldr_str.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
+; RUN: llc -march=mips64   -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+
+; Test intrinsics for 4-byte and 8-byte MSA load and stores.
+
+define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 23($5)
+; MIPS32R5-EB-NEXT:lwl $1, 20($5)
+; MIPS32R5-EB-NEXT:# implicit-def: $v0
+; MIPS32R5-EB-NEXT:lwr $2, 19($5)
+; MIPS32R5-EB-NEXT:lwl $2, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:# implicit-def: $v0
+; MIPS32R5-EL-NEXT:lwr $2, 20($5)
+; MIPS32R5-EL-NEXT:lwl $2, 23($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 20($5)
+; MIPS32R6-EB-NEXT:lw $2, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:lw $2, 20($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EL-NEXT:jrc $ra
+;
+; MIPS64R6-LABEL: llvm_mips_ldr_d_test:
+; MIPS64R6:   # %bb.0: # %entry
+; MIPS64R6-NEXT:ld $1, 16($5)
+; MIPS64R6-NEXT:fill.d $w0, $1
+; MIPS64R6-NEXT:st.d $w0, 0($4)
+; MIPS64R6-NEXT:jrc $ra
+entry:
+  %0 = tail call <2 x i64> @llvm.mips.ldr.d(i8* %ptr, i32 16)
+  store <2 x i64> %0, <2 x i64>* %val
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.ldr.d(i8*, i32) nounwind
+
+define void @llvm_mips_ldr_w_test(<4 x i32>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 19($5)
+; MIPS32R5-EB-NEXT:lwl $1, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_w_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1

[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin created this revision.
mbrkusanin added reviewers: atanasyan, petarj, sdardis, mstojanovic.
mbrkusanin added projects: LLVM, clang.
Herald added subscribers: cfe-commits, jrtc27, hiraditya, arichardson.

New intrinisics are implemented for when we need to port SIMD code from other 
arhitectures and only load or store portions of MSA registers.

Following intriniscs are added which only load/store element 0 of a vector:
v4i32 __builtin_msa_ldrq_w (const void *, imm_n2048_2044);
v2i64 __builtin_msa_ldr_d (const void *, imm_n4096_4088);
void __builtin_msa_strq_w (v4i32, void *, imm_n2048_2044);
void __builtin_msa_str_d (v2i64, void *, imm_n4096_4088);


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73644

Files:
  clang/include/clang/Basic/BuiltinsMips.def
  clang/lib/Headers/msa.h
  clang/lib/Sema/SemaChecking.cpp
  llvm/include/llvm/IR/IntrinsicsMips.td
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.h
  llvm/lib/Target/Mips/MipsMSAInstrInfo.td
  llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  llvm/test/CodeGen/Mips/msa/ldr_str.ll

Index: llvm/test/CodeGen/Mips/msa/ldr_str.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/msa/ldr_str.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mips -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r5 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R5-EL
+; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EB
+; RUN: llc -march=mipsel   -mcpu=mips32r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS32R6-EL
+; RUN: llc -march=mips64   -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=+msa,+fp64 -O0 < %s | FileCheck %s --check-prefix=MIPS64R6
+
+; Test intrinsics for 4-byte and 8-byte MSA load and stores.
+
+define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 23($5)
+; MIPS32R5-EB-NEXT:lwl $1, 20($5)
+; MIPS32R5-EB-NEXT:# implicit-def: $v0
+; MIPS32R5-EB-NEXT:lwr $2, 19($5)
+; MIPS32R5-EB-NEXT:lwl $2, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:# implicit-def: $v0
+; MIPS32R5-EL-NEXT:lwr $2, 20($5)
+; MIPS32R5-EL-NEXT:lwl $2, 23($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R5-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NEXT:nop
+;
+; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EB:   # %bb.0: # %entry
+; MIPS32R6-EB-NEXT:lw $1, 20($5)
+; MIPS32R6-EB-NEXT:lw $2, 16($5)
+; MIPS32R6-EB-NEXT:fill.w $w0, $1
+; MIPS32R6-EB-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EB-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EB-NEXT:jrc $ra
+;
+; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test:
+; MIPS32R6-EL:   # %bb.0: # %entry
+; MIPS32R6-EL-NEXT:lw $1, 16($5)
+; MIPS32R6-EL-NEXT:lw $2, 20($5)
+; MIPS32R6-EL-NEXT:fill.w $w0, $1
+; MIPS32R6-EL-NEXT:insert.w $w0[1], $2
+; MIPS32R6-EL-NEXT:st.d $w0, 0($4)
+; MIPS32R6-EL-NEXT:jrc $ra
+;
+; MIPS64R6-LABEL: llvm_mips_ldr_d_test:
+; MIPS64R6:   # %bb.0: # %entry
+; MIPS64R6-NEXT:ld $1, 16($5)
+; MIPS64R6-NEXT:fill.d $w0, $1
+; MIPS64R6-NEXT:st.d $w0, 0($4)
+; MIPS64R6-NEXT:jrc $ra
+entry:
+  %0 = tail call <2 x i64> @llvm.mips.ldr.d(i8* %ptr, i32 16)
+  store <2 x i64> %0, <2 x i64>* %val
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.ldr.d(i8*, i32) nounwind
+
+define void @llvm_mips_ldrq_w_test(<4 x i32>* %val, i8* %ptr) nounwind {
+; MIPS32R5-EB-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R5-EB:   # %bb.0: # %entry
+; MIPS32R5-EB-NEXT:# implicit-def: $at
+; MIPS32R5-EB-NEXT:lwr $1, 19($5)
+; MIPS32R5-EB-NEXT:lwl $1, 16($5)
+; MIPS32R5-EB-NEXT:fill.w $w0, $1
+; MIPS32R5-EB-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EB-NEXT:jr $ra
+; MIPS32R5-EB-NEXT:nop
+;
+; MIPS32R5-EL-LABEL: llvm_mips_ldrq_w_test:
+; MIPS32R5-EL:   # %bb.0: # %entry
+; MIPS32R5-EL-NEXT:# implicit-def: $at
+; MIPS32R5-EL-NEXT:lwr $1, 16($5)
+; MIPS32R5-EL-NEXT:lwl $1, 19($5)
+; MIPS32R5-EL-NEXT:fill.w $w0, $1
+; MIPS32R5-EL-NEXT:st.w $w0, 0($4)
+; MIPS32R5-EL-NEXT:jr $ra
+; MIPS32R5-EL-NE

[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

A few notes/questions:

1. Generated code was tested with Qemu:
  - For mips32r5 Qemu provides p5600
  - For mips64r6 Qemu provides i6400
  - For mips64r5 there is no cpu on Qemu with MSA and it appears that there 
won't be any hardware with Mips64r5 and MSA.
  - For mips32r6 Qemu only provides a cpu called mips32r6-generic which does 
not support MSA. I tested the code for this on mips64r6.

2. Names of the new intrinsics can be explained in the following way:

`__builtin_msa_ldr_d` (load right half)
`__builtin_msa_ldrq_w` (load right quarter)
`__builtin_msa_str_d` (store right half)
`__builtin_msa_strq_w` (store quarter)
Other proposed names are: ld1_d/ld1_w/st1_d/st1_w and ldc1/lwc1/sdc1/swc1. I 
have no strong preference and would not mind changing then if someone thinks 
they would fit better.

3. I did not make any tests for Clang (c/c++ test) since there are no tests for 
other intrinsics. Also should these new intrinsics be documented somewhere? 
Most other are corresponding to some instruction that already exists but these 
are actually pseudos.

4. emitLDRQ_W() and emitLDR_D() could be combined into one function but it 
decreases readability. Same with emitting stores: emitSTRQ_W() and emitSTR_D(). 
I already tried this and have the code ready if this would be more preferable.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Mirko Brkusanin via Phabricator via cfe-commits]

mbrkusanin added a comment.

We could do that for loads. For example on Mips32r5 (where we need most 
instructions) for intrinsic **ldr_d** instead of:

lwr $1, 16($5)
lwl $1, 19($5)
lwr $2, 20($5)
lwl $2, 23($5)
fill.w  $w0, $1
insert.w$w0[1], $2

We could use already available **ld.d** and then fix up **$w0[2]** and 
**$w0[3]** manually (when working with **MSA128WRegClass** / **v4i32**). 
**ld.d** has no alignment restrictions.

ld.d$w0, 16($5)
copy_s.w$1, $w0[0]
insert.w$w0[2], $1
insert.w$w0[3], $1

Optionally if we don't care what values are loaded in elements other then first 
we could just use **ld.d** and **ld.w** for **ldr_d** and **ldrq_w** 
respectively.

For stores however we cannot use **st.d** or **st.w** because we would write to 
memory we are not supposed to (we write to void* not necessarily v2i64 or 
v4i32).


Repository:
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  https://reviews.llvm.org/D73644/new/

https://reviews.llvm.org/D73644



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