r290642 - Update test that relies on the optimizer to match new output.
Author: mkuper
Date: Tue Dec 27 18:30:43 2016
New Revision: 290642
URL: http://llvm.org/viewvc/llvm-project?rev=290642&view=rev
Log:
Update test that relies on the optimizer to match new output.
Modified:
cfe/trunk/test/CodeGen/avx-shuffle-builtins.c
Modified: cfe/trunk/test/CodeGen/avx-shuffle-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx-shuffle-builtins.c?rev=290642&r1=290641&r2=290642&view=diff
==
--- cfe/trunk/test/CodeGen/avx-shuffle-builtins.c (original)
+++ cfe/trunk/test/CodeGen/avx-shuffle-builtins.c Tue Dec 27 18:30:43 2016
@@ -67,9 +67,7 @@ __m128
test_mm_broadcast_ss(float const *__a) {
// CHECK-LABEL: @test_mm_broadcast_ss
// CHECK: insertelement <4 x float> {{.*}}, i32 0
- // CHECK: insertelement <4 x float> {{.*}}, i32 1
- // CHECK: insertelement <4 x float> {{.*}}, i32 2
- // CHECK: insertelement <4 x float> {{.*}}, i32 3
+ // CHECK: shufflevector <4 x float> {{.*}}, <4 x float> undef, <4 x i32>
zeroinitializer
return _mm_broadcast_ss(__a);
}
@@ -77,9 +75,7 @@ __m256d
test_mm256_broadcast_sd(double const *__a) {
// CHECK-LABEL: @test_mm256_broadcast_sd
// CHECK: insertelement <4 x double> {{.*}}, i32 0
- // CHECK: insertelement <4 x double> {{.*}}, i32 1
- // CHECK: insertelement <4 x double> {{.*}}, i32 2
- // CHECK: insertelement <4 x double> {{.*}}, i32 3
+ // CHECK: shufflevector <4 x double> {{.*}}, <4 x double> undef, <4 x i32>
zeroinitializer
return _mm256_broadcast_sd(__a);
}
@@ -87,13 +83,7 @@ __m256
test_mm256_broadcast_ss(float const *__a) {
// CHECK-LABEL: @test_mm256_broadcast_ss
// CHECK: insertelement <8 x float> {{.*}}, i32 0
- // CHECK: insertelement <8 x float> {{.*}}, i32 1
- // CHECK: insertelement <8 x float> {{.*}}, i32 2
- // CHECK: insertelement <8 x float> {{.*}}, i32 3
- // CHECK: insertelement <8 x float> {{.*}}, i32 4
- // CHECK: insertelement <8 x float> {{.*}}, i32 5
- // CHECK: insertelement <8 x float> {{.*}}, i32 6
- // CHECK: insertelement <8 x float> {{.*}}, i32 7
+ // CHECK: shufflevector <8 x float> {{.*}}, <8 x float> undef, <8 x i32>
zeroinitializer
return _mm256_broadcast_ss(__a);
}
___
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cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r289455 - Bring back note about not supporting global register variables.
Author: mkuper Date: Mon Dec 12 13:11:39 2016 New Revision: 289455 URL: http://llvm.org/viewvc/llvm-project?rev=289455&view=rev Log: Bring back note about not supporting global register variables. This was accidentally removed in r260506, even though we only support non-allocatable global register variables. The general (allocatable) case is explicitly not supported. Differential Revision: https://reviews.llvm.org/D27473 Modified: cfe/trunk/docs/UsersManual.rst Modified: cfe/trunk/docs/UsersManual.rst URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/docs/UsersManual.rst?rev=289455&r1=289454&r2=289455&view=diff == --- cfe/trunk/docs/UsersManual.rst (original) +++ cfe/trunk/docs/UsersManual.rst Mon Dec 12 13:11:39 2016 @@ -1830,6 +1830,10 @@ extensions are not implemented yet: ... local_function(1); +- clang only supports global register variables when the register specified + is non-allocatable (e.g. the stack pointer). Support for general global + register variables is unlikely to be implemented soon because it requires + additional LLVM backend support. - clang does not support static initialization of flexible array members. This appears to be a rarely used extension, but could be implemented pending user demand. ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D13009: [X86] Fix some non-reserved parameter names in intrinsic headers
mkuper created this revision.
mkuper added a reviewer: AsafBadouh.
mkuper added a subscriber: cfe-commits.
http://reviews.llvm.org/D13009
Files:
lib/Headers/avx512fintrin.h
lib/Headers/emmintrin.h
Index: lib/Headers/avx512fintrin.h
===
--- lib/Headers/avx512fintrin.h
+++ lib/Headers/avx512fintrin.h
@@ -872,18 +872,18 @@
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
-_mm512_sqrt_pd(__m512d a)
+_mm512_sqrt_pd(__m512d __a)
{
- return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)a,
+ return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)__a,
(__v8df) _mm512_setzero_pd (),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
-_mm512_sqrt_ps(__m512 a)
+_mm512_sqrt_ps(__m512 __a)
{
- return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)a,
+ return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)__a,
(__v16sf) _mm512_setzero_ps (),
(__mmask16) -1,
_MM_FROUND_CUR_DIRECTION);
@@ -2477,18 +2477,18 @@
}
static __inline __m512i __DEFAULT_FN_ATTRS
-_mm512_cvttps_epi32(__m512 a)
+_mm512_cvttps_epi32(__m512 __a)
{
return (__m512i)
-__builtin_ia32_cvttps2dq512_mask((__v16sf) a,
+__builtin_ia32_cvttps2dq512_mask((__v16sf) __a,
(__v16si) _mm512_setzero_si512 (),
(__mmask16) -1, _MM_FROUND_CUR_DIRECTION);
}
static __inline __m256i __DEFAULT_FN_ATTRS
-_mm512_cvttpd_epi32(__m512d a)
+_mm512_cvttpd_epi32(__m512d __a)
{
- return (__m256i)__builtin_ia32_cvttpd2dq512_mask((__v8df) a,
+ return (__m256i)__builtin_ia32_cvttpd2dq512_mask((__v8df) __a,
(__v8si)_mm256_setzero_si256(),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
Index: lib/Headers/emmintrin.h
===
--- lib/Headers/emmintrin.h
+++ lib/Headers/emmintrin.h
@@ -1128,33 +1128,33 @@
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64x(long long q1, long long q0)
+_mm_set_epi64x(long long __q1, long long __q0)
{
- return (__m128i){ q0, q1 };
+ return (__m128i){ __q0, __q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64(__m64 q1, __m64 q0)
+_mm_set_epi64(__m64 __q1, __m64 __q0)
{
- return (__m128i){ (long long)q0, (long long)q1 };
+ return (__m128i){ (long long)__q0, (long long)__q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi32(int i3, int i2, int i1, int i0)
+_mm_set_epi32(int __i3, int __i2, int __i1, int __i0)
{
- return (__m128i)(__v4si){ i0, i1, i2, i3};
+ return (__m128i)(__v4si){ __i0, __i1, __i2, __i3};
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi16(short w7, short w6, short w5, short w4, short w3, short w2, short w1, short w0)
+_mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, short __w2, short __w1, short __w0)
{
- return (__m128i)(__v8hi){ w0, w1, w2, w3, w4, w5, w6, w7 };
+ return (__m128i)(__v8hi){ __w0, __w1, __w2, __w3, __w4, __w5, __w6, __w7 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi8(char b15, char b14, char b13, char b12, char b11, char b10, char b9, char b8, char b7, char b6, char b5, char b4, char b3, char b2, char b1, char b0)
+_mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, char __b10, char __b9, char __b8, char __b7, char __b6, char __b5, char __b4, char __b3, char __b2, char __b1, char __b0)
{
- return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 };
+ return (__m128i)(__v16qi){ __b0, __b1, __b2, __b3, __b4, __b5, __b6, __b7, __b8, __b9, __b10, __b11, __b12, __b13, __b14, __b15 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
@@ -1188,27 +1188,27 @@
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi64(__m64 q0, __m64 q1)
+_mm_setr_epi64(__m64 __q0, __m64 __q1)
{
- return (__m128i){ (long long)q0, (long long)q1 };
+ return (__m128i){ (long long)__q0, (long long)__q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi32(int i0, int i1, int i2, int i3)
+_mm_setr_epi32(int __i0, int __i1, int __i2, int __i3)
{
- return (__m128i)(__v4si){ i0, i1, i2, i3};
+ return (__m128i)(__v4si){ __i0, __i1, __i2, __i3};
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi16(short w0, short w1, short w2, short w3, short w4, short w5, short w6, short w7)
+_mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, short __w5, short __w6, short __w7)
{
- return (__m128i)(__v8hi){ w0, w1
r248150 - [X86] Fix some non-reserved parameter names in intrinsic headers
Author: mkuper
Date: Mon Sep 21 06:45:27 2015
New Revision: 248150
URL: http://llvm.org/viewvc/llvm-project?rev=248150&view=rev
Log:
[X86] Fix some non-reserved parameter names in intrinsic headers
Differential Revision: http://reviews.llvm.org/D13009
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/lib/Headers/emmintrin.h
Modified: cfe/trunk/lib/Headers/avx512fintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=248150&r1=248149&r2=248150&view=diff
==
--- cfe/trunk/lib/Headers/avx512fintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512fintrin.h Mon Sep 21 06:45:27 2015
@@ -872,18 +872,18 @@ _mm512_mask_mullo_epi32 (__m512i __W, __
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
-_mm512_sqrt_pd(__m512d a)
+_mm512_sqrt_pd(__m512d __a)
{
- return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)a,
+ return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)__a,
(__v8df) _mm512_setzero_pd (),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
-_mm512_sqrt_ps(__m512 a)
+_mm512_sqrt_ps(__m512 __a)
{
- return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)a,
+ return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)__a,
(__v16sf) _mm512_setzero_ps (),
(__mmask16) -1,
_MM_FROUND_CUR_DIRECTION);
@@ -2477,18 +2477,18 @@ _mm512_cvtph_ps(__m256i __A)
}
static __inline __m512i __DEFAULT_FN_ATTRS
-_mm512_cvttps_epi32(__m512 a)
+_mm512_cvttps_epi32(__m512 __a)
{
return (__m512i)
-__builtin_ia32_cvttps2dq512_mask((__v16sf) a,
+__builtin_ia32_cvttps2dq512_mask((__v16sf) __a,
(__v16si) _mm512_setzero_si512 (),
(__mmask16) -1, _MM_FROUND_CUR_DIRECTION);
}
static __inline __m256i __DEFAULT_FN_ATTRS
-_mm512_cvttpd_epi32(__m512d a)
+_mm512_cvttpd_epi32(__m512d __a)
{
- return (__m256i)__builtin_ia32_cvttpd2dq512_mask((__v8df) a,
+ return (__m256i)__builtin_ia32_cvttpd2dq512_mask((__v8df) __a,
(__v8si)_mm256_setzero_si256(),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
Modified: cfe/trunk/lib/Headers/emmintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/emmintrin.h?rev=248150&r1=248149&r2=248150&view=diff
==
--- cfe/trunk/lib/Headers/emmintrin.h (original)
+++ cfe/trunk/lib/Headers/emmintrin.h Mon Sep 21 06:45:27 2015
@@ -1128,33 +1128,33 @@ _mm_undefined_si128()
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64x(long long q1, long long q0)
+_mm_set_epi64x(long long __q1, long long __q0)
{
- return (__m128i){ q0, q1 };
+ return (__m128i){ __q0, __q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64(__m64 q1, __m64 q0)
+_mm_set_epi64(__m64 __q1, __m64 __q0)
{
- return (__m128i){ (long long)q0, (long long)q1 };
+ return (__m128i){ (long long)__q0, (long long)__q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi32(int i3, int i2, int i1, int i0)
+_mm_set_epi32(int __i3, int __i2, int __i1, int __i0)
{
- return (__m128i)(__v4si){ i0, i1, i2, i3};
+ return (__m128i)(__v4si){ __i0, __i1, __i2, __i3};
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi16(short w7, short w6, short w5, short w4, short w3, short w2,
short w1, short w0)
+_mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3,
short __w2, short __w1, short __w0)
{
- return (__m128i)(__v8hi){ w0, w1, w2, w3, w4, w5, w6, w7 };
+ return (__m128i)(__v8hi){ __w0, __w1, __w2, __w3, __w4, __w5, __w6, __w7 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi8(char b15, char b14, char b13, char b12, char b11, char b10, char
b9, char b8, char b7, char b6, char b5, char b4, char b3, char b2, char b1,
char b0)
+_mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, char
__b10, char __b9, char __b8, char __b7, char __b6, char __b5, char __b4, char
__b3, char __b2, char __b1, char __b0)
{
- return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11,
b12, b13, b14, b15 };
+ return (__m128i)(__v16qi){ __b0, __b1, __b2, __b3, __b4, __b5, __b6, __b7,
__b8, __b9, __b10, __b11, __b12, __b13, __b14, __b15 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
@@ -1188,27 +1188,27 @@ _mm_set1_epi8(char __b)
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi64(__m64 q0, __m64 q1)
+_mm_setr_epi64(__m64 __q0, __m64 __q1)
{
Re: [PATCH] D13009: [X86] Fix some non-reserved parameter names in intrinsic headers
This revision was automatically updated to reflect the committed changes.
Closed by commit rL248150: [X86] Fix some non-reserved parameter names in
intrinsic headers (authored by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D13009?vs=35225&id=35230#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13009
Files:
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/lib/Headers/emmintrin.h
Index: cfe/trunk/lib/Headers/emmintrin.h
===
--- cfe/trunk/lib/Headers/emmintrin.h
+++ cfe/trunk/lib/Headers/emmintrin.h
@@ -1128,33 +1128,33 @@
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64x(long long q1, long long q0)
+_mm_set_epi64x(long long __q1, long long __q0)
{
- return (__m128i){ q0, q1 };
+ return (__m128i){ __q0, __q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi64(__m64 q1, __m64 q0)
+_mm_set_epi64(__m64 __q1, __m64 __q0)
{
- return (__m128i){ (long long)q0, (long long)q1 };
+ return (__m128i){ (long long)__q0, (long long)__q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi32(int i3, int i2, int i1, int i0)
+_mm_set_epi32(int __i3, int __i2, int __i1, int __i0)
{
- return (__m128i)(__v4si){ i0, i1, i2, i3};
+ return (__m128i)(__v4si){ __i0, __i1, __i2, __i3};
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi16(short w7, short w6, short w5, short w4, short w3, short w2, short w1, short w0)
+_mm_set_epi16(short __w7, short __w6, short __w5, short __w4, short __w3, short __w2, short __w1, short __w0)
{
- return (__m128i)(__v8hi){ w0, w1, w2, w3, w4, w5, w6, w7 };
+ return (__m128i)(__v8hi){ __w0, __w1, __w2, __w3, __w4, __w5, __w6, __w7 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_set_epi8(char b15, char b14, char b13, char b12, char b11, char b10, char b9, char b8, char b7, char b6, char b5, char b4, char b3, char b2, char b1, char b0)
+_mm_set_epi8(char __b15, char __b14, char __b13, char __b12, char __b11, char __b10, char __b9, char __b8, char __b7, char __b6, char __b5, char __b4, char __b3, char __b2, char __b1, char __b0)
{
- return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 };
+ return (__m128i)(__v16qi){ __b0, __b1, __b2, __b3, __b4, __b5, __b6, __b7, __b8, __b9, __b10, __b11, __b12, __b13, __b14, __b15 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
@@ -1188,27 +1188,27 @@
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi64(__m64 q0, __m64 q1)
+_mm_setr_epi64(__m64 __q0, __m64 __q1)
{
- return (__m128i){ (long long)q0, (long long)q1 };
+ return (__m128i){ (long long)__q0, (long long)__q1 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi32(int i0, int i1, int i2, int i3)
+_mm_setr_epi32(int __i0, int __i1, int __i2, int __i3)
{
- return (__m128i)(__v4si){ i0, i1, i2, i3};
+ return (__m128i)(__v4si){ __i0, __i1, __i2, __i3};
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi16(short w0, short w1, short w2, short w3, short w4, short w5, short w6, short w7)
+_mm_setr_epi16(short __w0, short __w1, short __w2, short __w3, short __w4, short __w5, short __w6, short __w7)
{
- return (__m128i)(__v8hi){ w0, w1, w2, w3, w4, w5, w6, w7 };
+ return (__m128i)(__v8hi){ __w0, __w1, __w2, __w3, __w4, __w5, __w6, __w7 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
-_mm_setr_epi8(char b0, char b1, char b2, char b3, char b4, char b5, char b6, char b7, char b8, char b9, char b10, char b11, char b12, char b13, char b14, char b15)
+_mm_setr_epi8(char __b0, char __b1, char __b2, char __b3, char __b4, char __b5, char __b6, char __b7, char __b8, char __b9, char __b10, char __b11, char __b12, char __b13, char __b14, char __b15)
{
- return (__m128i)(__v16qi){ b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, b10, b11, b12, b13, b14, b15 };
+ return (__m128i)(__v16qi){ __b0, __b1, __b2, __b3, __b4, __b5, __b6, __b7, __b8, __b9, __b10, __b11, __b12, __b13, __b14, __b15 };
}
static __inline__ __m128i __DEFAULT_FN_ATTRS
Index: cfe/trunk/lib/Headers/avx512fintrin.h
===
--- cfe/trunk/lib/Headers/avx512fintrin.h
+++ cfe/trunk/lib/Headers/avx512fintrin.h
@@ -872,18 +872,18 @@
}
static __inline__ __m512d __DEFAULT_FN_ATTRS
-_mm512_sqrt_pd(__m512d a)
+_mm512_sqrt_pd(__m512d __a)
{
- return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)a,
+ return (__m512d)__builtin_ia32_sqrtpd512_mask((__v8df)__a,
(__v8df) _mm512_setzero_pd (),
(__mmask8) -1,
_MM_FROUND_CUR_DIRECTION);
}
static __inline__ __m512 __DEFAULT_FN_ATTRS
-_mm512_sqrt_ps(__m512 a)
+_mm512_sqrt_ps(__m512 __a)
{
- return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)a,
+ return (__m512)__builtin_ia32_sqrtps512_mask((__v16sf)__a,
[PATCH] D13015: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs
mkuper created this revision.
mkuper added a reviewer: AsafBadouh.
mkuper added a subscriber: cfe-commits.
http://reviews.llvm.org/D13015
Files:
lib/Headers/emmintrin.h
lib/Headers/f16cintrin.h
Index: lib/Headers/emmintrin.h
===
--- lib/Headers/emmintrin.h
+++ lib/Headers/emmintrin.h
@@ -35,6 +35,8 @@
typedef short __v8hi __attribute__((__vector_size__(16)));
typedef char __v16qi __attribute__((__vector_size__(16)));
+#include
+
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__,
__target__("sse2")))
Index: lib/Headers/f16cintrin.h
===
--- lib/Headers/f16cintrin.h
+++ lib/Headers/f16cintrin.h
@@ -21,8 +21,8 @@
*===---===
*/
-#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
-#error "Never use directly; include instead."
+#if !defined __X86INTRIN_H && !defined __EMMINTRIN_H && !defined __IMMINTRIN_H
+#error "Never use directly; include instead."
#endif
#ifndef __F16CINTRIN_H
Index: lib/Headers/emmintrin.h
===
--- lib/Headers/emmintrin.h
+++ lib/Headers/emmintrin.h
@@ -35,6 +35,8 @@
typedef short __v8hi __attribute__((__vector_size__(16)));
typedef char __v16qi __attribute__((__vector_size__(16)));
+#include
+
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("sse2")))
Index: lib/Headers/f16cintrin.h
===
--- lib/Headers/f16cintrin.h
+++ lib/Headers/f16cintrin.h
@@ -21,8 +21,8 @@
*===---===
*/
-#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
-#error "Never use directly; include instead."
+#if !defined __X86INTRIN_H && !defined __EMMINTRIN_H && !defined __IMMINTRIN_H
+#error "Never use directly; include instead."
#endif
#ifndef __F16CINTRIN_H
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Re: [PATCH] D13015: [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs
This revision was automatically updated to reflect the committed changes.
Closed by commit rL248156: [X86] Make f16c intrinsics accessible through
emmintrin.h, per Intel docs (authored by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D13015?vs=35237&id=35250#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13015
Files:
cfe/trunk/lib/Headers/emmintrin.h
cfe/trunk/lib/Headers/f16cintrin.h
Index: cfe/trunk/lib/Headers/f16cintrin.h
===
--- cfe/trunk/lib/Headers/f16cintrin.h
+++ cfe/trunk/lib/Headers/f16cintrin.h
@@ -21,8 +21,8 @@
*===---===
*/
-#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
-#error "Never use directly; include instead."
+#if !defined __X86INTRIN_H && !defined __EMMINTRIN_H && !defined __IMMINTRIN_H
+#error "Never use directly; include instead."
#endif
#ifndef __F16CINTRIN_H
Index: cfe/trunk/lib/Headers/emmintrin.h
===
--- cfe/trunk/lib/Headers/emmintrin.h
+++ cfe/trunk/lib/Headers/emmintrin.h
@@ -35,6 +35,8 @@
typedef short __v8hi __attribute__((__vector_size__(16)));
typedef char __v16qi __attribute__((__vector_size__(16)));
+#include
+
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__,
__target__("sse2")))
Index: cfe/trunk/lib/Headers/f16cintrin.h
===
--- cfe/trunk/lib/Headers/f16cintrin.h
+++ cfe/trunk/lib/Headers/f16cintrin.h
@@ -21,8 +21,8 @@
*===---===
*/
-#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
-#error "Never use directly; include instead."
+#if !defined __X86INTRIN_H && !defined __EMMINTRIN_H && !defined __IMMINTRIN_H
+#error "Never use directly; include instead."
#endif
#ifndef __F16CINTRIN_H
Index: cfe/trunk/lib/Headers/emmintrin.h
===
--- cfe/trunk/lib/Headers/emmintrin.h
+++ cfe/trunk/lib/Headers/emmintrin.h
@@ -35,6 +35,8 @@
typedef short __v8hi __attribute__((__vector_size__(16)));
typedef char __v16qi __attribute__((__vector_size__(16)));
+#include
+
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("sse2")))
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r248156 - [X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs
Author: mkuper
Date: Mon Sep 21 08:34:47 2015
New Revision: 248156
URL: http://llvm.org/viewvc/llvm-project?rev=248156&view=rev
Log:
[X86] Make f16c intrinsics accessible through emmintrin.h, per Intel docs
Differential Revision: http://reviews.llvm.org/D13015
Modified:
cfe/trunk/lib/Headers/emmintrin.h
cfe/trunk/lib/Headers/f16cintrin.h
Modified: cfe/trunk/lib/Headers/emmintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/emmintrin.h?rev=248156&r1=248155&r2=248156&view=diff
==
--- cfe/trunk/lib/Headers/emmintrin.h (original)
+++ cfe/trunk/lib/Headers/emmintrin.h Mon Sep 21 08:34:47 2015
@@ -35,6 +35,8 @@ typedef long long __v2di __attribute__ (
typedef short __v8hi __attribute__((__vector_size__(16)));
typedef char __v16qi __attribute__((__vector_size__(16)));
+#include
+
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__,
__target__("sse2")))
Modified: cfe/trunk/lib/Headers/f16cintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/f16cintrin.h?rev=248156&r1=248155&r2=248156&view=diff
==
--- cfe/trunk/lib/Headers/f16cintrin.h (original)
+++ cfe/trunk/lib/Headers/f16cintrin.h Mon Sep 21 08:34:47 2015
@@ -21,8 +21,8 @@
*===---===
*/
-#if !defined __X86INTRIN_H && !defined __IMMINTRIN_H
-#error "Never use directly; include instead."
+#if !defined __X86INTRIN_H && !defined __EMMINTRIN_H && !defined __IMMINTRIN_H
+#error "Never use directly; include instead."
#endif
#ifndef __F16CINTRIN_H
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Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics
mkuper added a comment. Thanks, Simon! I've wanted to add the _undefined intrinsics for a while now, but never got to it. Anyway, this sort of implementation somewhat worries me. Yes, I know that the gcc intrinsics do something very similar. And I also know that in practice we'll get an undef value, nothing worse (assuming reading an uninitialized automatic variable is undefined behavior to begin with - which really depends on the spec interpretation :-) ). And I know this isn't likely to change anytime soon. Still, relying on what may be undefined behavior in the header files worries me, and I'd rather not have it implemented like that. I was thinking about adding a __builtin_undef which explicitly resolves to an undef value. Does that make sense to you? Comment at: test/CodeGen/sse-undefined.c:1 @@ +1,2 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o - | not grep "xmm" +// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -o - | not grep "ymm" Perhaps a more explicit test? Repository: rL LLVM http://reviews.llvm.org/D12052 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics
mkuper added a comment. I think this is slightly less elegant than having a generic builtin, but I'm just fine with it, especially if David/Eric prefer it to the generic version. Repository: rL LLVM http://reviews.llvm.org/D12052 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D12052: [X86][SSE] Add _mm_undefined_* intrinsics
mkuper added a comment. Actually, thinking about it a bit more, a generic builtin most probably won't be more elegant. LGTM. Repository: rL LLVM http://reviews.llvm.org/D12052 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D12271: [X86] Expose the various _rot intrinsics on non-MS platforms
mkuper created this revision.
mkuper added reviewers: majnemer, rnk.
mkuper added a subscriber: cfe-commits.
_rotl, _rotwl and _lrotl (and their right-shift counterparts) are official x86
intrinsics, and should be supported regardless of environment.
This is in contrast to _rotl8, _rotl16, and _rotl64 which are MS-specific.
Note that the MS documentation for _lrotl is different from the Intel
documentation. Intel explicitly documents it as a 64-bit rotate, while for MS,
since sizeof(unsigned long) for MSVC is 4, a 32-bit rotate is clearly implied.
Compare:
https://msdn.microsoft.com/en-us/library/a0w705h5.aspx
vs.
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=rot&techs=Other&expand=3193
Note that this doesn't change the implementations of these intrinsics, which
are currently pretty awful.
We only manage to match the 32-bit versions to a rotate, and even then, still
have the "and" and the control flow in place. That should be dealt with
separately.
http://reviews.llvm.org/D12271
Files:
lib/Headers/Intrin.h
lib/Headers/immintrin.h
test/CodeGen/x86-rot-intrinsics.c
test\CodeGen\x86-rot-intrinsics.c
Index: lib/Headers/immintrin.h
===
--- lib/Headers/immintrin.h
+++ lib/Headers/immintrin.h
@@ -148,4 +148,58 @@
* whereas others are also available at all times. */
#include
+static __inline__ unsigned short __attribute__((__always_inline__, __nodebug__))
+_rotwl(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value << _Shift) | (_Value >> (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned short __attribute__((__always_inline__, __nodebug__))
+_rotwr(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotl(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotr(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+
+/*
+ * MS defines _lrotl/_lrotr in a slightly incompatible way, since
+ * unsigned long is always 32-bit in MSVC.
+ */
+#ifdef _MSC_VER
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+#else
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (64 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (64 - _Shift)) : _Value;
+}
+#endif
+
#endif /* __IMMINTRIN_H */
Index: lib/Headers/Intrin.h
===
--- lib/Headers/Intrin.h
+++ lib/Headers/Intrin.h
@@ -463,26 +463,6 @@
_Shift &= 0xf;
return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
}
-static __inline__ unsigned int __DEFAULT_FN_ATTRS
-_rotl(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned int __DEFAULT_FN_ATTRS
-_rotr(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned long __DEFAULT_FN_ATTRS
-_lrotl(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned long __DEFAULT_FN_ATTRS
-_lrotr(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
static
__inline__ unsigned __int64 __DEFAULT_FN_ATTRS
_rotl64(unsigned __int64 _Value, int _Shift) {
Index: test/CodeGen/x86-rot-intrinsics.c
===
--- test/CodeGen/x86-rot-intrinsics.c
+++ test/CodeGen/x86-rot-intrinsics.c
@@ -0,0 +1,88 @@
+// RUN: %clang_cc1 %s -triple=i686-pc-linux -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN:-triple i686--windows -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-pref
[PATCH] D12278: [X86] Add MSVC-compatible intrinsics for clac, stac, lgdt and sgdt
mkuper created this revision.
mkuper added reviewers: rnk, majnemer.
mkuper added a subscriber: cfe-commits.
LLVM part was posted as D12277
http://reviews.llvm.org/D12278
Files:
include/clang/Basic/BuiltinsX86.def
lib/Headers/Intrin.h
test/CodeGen/builtins-x86.c
Index: lib/Headers/Intrin.h
===
--- lib/Headers/Intrin.h
+++ lib/Headers/Intrin.h
@@ -59,6 +59,7 @@
void __addfsbyte(unsigned long, unsigned char);
void __addfsdword(unsigned long, unsigned long);
void __addfsword(unsigned long, unsigned short);
+static __inline__ void _clac(void);
void __code_seg(const char *);
static __inline__
void __cpuid(int[4], int);
@@ -82,6 +83,7 @@
void __invlpg(void *);
unsigned short __inword(unsigned short);
void __inwordstring(unsigned short, unsigned short *, unsigned long);
+static __inline__ void _lgdt(void *);
void __lidt(void *);
unsigned __int64 __ll_lshift(unsigned __int64, int);
__int64 __ll_rshift(__int64, int);
@@ -130,9 +132,11 @@
unsigned __int64 __readmsr(unsigned long);
unsigned __int64 __readpmc(unsigned long);
unsigned long __segmentlimit(unsigned long);
+static __inline__ void _sgdt(void *);
void __sidt(void *);
void *__slwpcb(void);
static __inline__
+static __inline__ void _stac(void);
void __stosb(unsigned char *, unsigned char, size_t);
static __inline__
void __stosd(unsigned long *, unsigned long, size_t);
@@ -944,6 +948,24 @@
__writecr3(unsigned int __cr3_val) {
__asm__ ("mov %0, %%cr3" : : "q"(__cr3_val) : "memory");
}
+
+static __inline__ void __DEFAULT_FN_ATTRS _clac(void) {
+ __builtin_ia32_clac();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _stac(void) {
+ __builtin_ia32_stac();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _lgdt(void *__ptr) {
+ __builtin_ia32_lgdt(__ptr);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _sgdt(void *__ptr) {
+ __builtin_ia32_sgdt(__ptr);
+}
+
+
#endif
#ifdef __cplusplus
Index: include/clang/Basic/BuiltinsX86.def
===
--- include/clang/Basic/BuiltinsX86.def
+++ include/clang/Basic/BuiltinsX86.def
@@ -671,6 +671,14 @@
BUILTIN(__builtin_ia32_fxsave, "vv*", "")
BUILTIN(__builtin_ia32_fxsave64, "vv*", "")
+// SMAP
+BUILTIN(__builtin_ia32_clac, "v", "")
+BUILTIN(__builtin_ia32_stac, "v", "")
+
+// LGDT, SGDT
+BUILTIN(__builtin_ia32_sgdt, "vv*", "")
+BUILTIN(__builtin_ia32_lgdt, "vv*", "")
+
// ADX
TARGET_BUILTIN(__builtin_ia32_addcarryx_u32, "UcUcUiUiUi*", "", "adx")
TARGET_BUILTIN(__builtin_ia32_addcarryx_u64, "UcUcULLiULLiULLi*", "", "adx")
Index: test/CodeGen/builtins-x86.c
===
--- test/CodeGen/builtins-x86.c
+++ test/CodeGen/builtins-x86.c
@@ -264,6 +264,10 @@
(void)__builtin_ia32_fxsave64(tmp_vp);
(void)__builtin_ia32_fxrstor(tmp_vp);
(void)__builtin_ia32_fxrstor64(tmp_vp);
+ (void)__builtin_ia32_clac();
+ (void)__builtin_ia32_stac();
+ (void)__builtin_ia32_sgdt(tmp_vp);
+ (void)__builtin_ia32_lgdt(tmp_vp);
tmp_V4f = __builtin_ia32_cvtpi2ps(tmp_V4f, tmp_V2i);
tmp_V2i = __builtin_ia32_cvtps2pi(tmp_V4f);
tmp_i = __builtin_ia32_cvtss2si(tmp_V4f);
Index: lib/Headers/Intrin.h
===
--- lib/Headers/Intrin.h
+++ lib/Headers/Intrin.h
@@ -59,6 +59,7 @@
void __addfsbyte(unsigned long, unsigned char);
void __addfsdword(unsigned long, unsigned long);
void __addfsword(unsigned long, unsigned short);
+static __inline__ void _clac(void);
void __code_seg(const char *);
static __inline__
void __cpuid(int[4], int);
@@ -82,6 +83,7 @@
void __invlpg(void *);
unsigned short __inword(unsigned short);
void __inwordstring(unsigned short, unsigned short *, unsigned long);
+static __inline__ void _lgdt(void *);
void __lidt(void *);
unsigned __int64 __ll_lshift(unsigned __int64, int);
__int64 __ll_rshift(__int64, int);
@@ -130,9 +132,11 @@
unsigned __int64 __readmsr(unsigned long);
unsigned __int64 __readpmc(unsigned long);
unsigned long __segmentlimit(unsigned long);
+static __inline__ void _sgdt(void *);
void __sidt(void *);
void *__slwpcb(void);
static __inline__
+static __inline__ void _stac(void);
void __stosb(unsigned char *, unsigned char, size_t);
static __inline__
void __stosd(unsigned long *, unsigned long, size_t);
@@ -944,6 +948,24 @@
__writecr3(unsigned int __cr3_val) {
__asm__ ("mov %0, %%cr3" : : "q"(__cr3_val) : "memory");
}
+
+static __inline__ void __DEFAULT_FN_ATTRS _clac(void) {
+ __builtin_ia32_clac();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _stac(void) {
+ __builtin_ia32_stac();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _lgdt(void *__ptr) {
+ __builtin_ia32_lgdt(__ptr);
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS _sgdt(void *__ptr) {
+ __builtin_ia32_sgdt(__ptr);
+}
+
+
#endif
#ifdef __cplusplus
Index: include/clang/Basic/BuiltinsX86.def
=
Re: [PATCH] D12278: [X86] Add MSVC-compatible intrinsics for clac, stac, lgdt and sgdt
mkuper added inline comments.
Comment at: lib/Headers/Intrin.h:961
@@ +960,3 @@
+static __inline__ void __DEFAULT_FN_ATTRS _lgdt(void *__ptr) {
+ __builtin_ia32_lgdt(__ptr);
+}
compnerd wrote:
> Why does this need a builtin? Is an inline assembly block using lgdt
> insufficient for some reason?
I think using a builtin is, generally, cleaner.
I'm ok with using inline asm (and abandoning the LLVM part of the patch), if
that's the more popular option.
http://reviews.llvm.org/D12278
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r245923 - [X86] Expose the various _rot intrinsics on non-MS platforms
Author: mkuper
Date: Tue Aug 25 02:21:33 2015
New Revision: 245923
URL: http://llvm.org/viewvc/llvm-project?rev=245923&view=rev
Log:
[X86] Expose the various _rot intrinsics on non-MS platforms
_rotl, _rotwl and _lrotl (and their right-shift counterparts) are official x86
intrinsics, and should be supported regardless of environment. This is in
contrast
to _rotl8, _rotl16, and _rotl64 which are MS-specific.
Note that the MS documentation for _lrotl is different from the Intel
documentation. Intel explicitly documents it as a 64-bit rotate, while for MS,
since sizeof(unsigned long) for MSVC is always 4, a 32-bit rotate is implied.
Differential Revision: http://reviews.llvm.org/D12271
Added:
cfe/trunk/test/CodeGen/x86-rot-intrinsics.c (with props)
Modified:
cfe/trunk/lib/Headers/Intrin.h
cfe/trunk/lib/Headers/immintrin.h
Modified: cfe/trunk/lib/Headers/Intrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/Intrin.h?rev=245923&r1=245922&r2=245923&view=diff
==
--- cfe/trunk/lib/Headers/Intrin.h (original)
+++ cfe/trunk/lib/Headers/Intrin.h Tue Aug 25 02:21:33 2015
@@ -463,26 +463,6 @@ _rotr16(unsigned short _Value, unsigned
_Shift &= 0xf;
return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
}
-static __inline__ unsigned int __DEFAULT_FN_ATTRS
-_rotl(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned int __DEFAULT_FN_ATTRS
-_rotr(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned long __DEFAULT_FN_ATTRS
-_lrotl(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-static __inline__ unsigned long __DEFAULT_FN_ATTRS
-_lrotr(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
static
__inline__ unsigned __int64 __DEFAULT_FN_ATTRS
_rotl64(unsigned __int64 _Value, int _Shift) {
Modified: cfe/trunk/lib/Headers/immintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/immintrin.h?rev=245923&r1=245922&r2=245923&view=diff
==
--- cfe/trunk/lib/Headers/immintrin.h (original)
+++ cfe/trunk/lib/Headers/immintrin.h Tue Aug 25 02:21:33 2015
@@ -148,4 +148,58 @@ _writegsbase_u64(unsigned long long __V)
* whereas others are also available at all times. */
#include
+static __inline__ unsigned short __attribute__((__always_inline__,
__nodebug__))
+_rotwl(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value << _Shift) | (_Value >> (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned short __attribute__((__always_inline__,
__nodebug__))
+_rotwr(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotl(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotr(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+
+/*
+ * MS defines _lrotl/_lrotr in a slightly incompatible way, since
+ * unsigned long is always 32-bit in MSVC.
+ */
+#ifdef _MSC_VER
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+#else
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (64 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (64 - _Shift)) : _Value;
+}
+#endif
+
#endif /* __IMMINTRIN_H */
Added: cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/x86-rot-intrinsics.c?rev=245923&view=auto
==
--- cfe/trunk/test/CodeGen/x86-rot-intrinsics.c (added)
+++ cfe/trunk/test
Re: [PATCH] D12271: [X86] Expose the various _rot intrinsics on non-MS platforms
This revision was automatically updated to reflect the committed changes.
Closed by commit rL245923: [X86] Expose the various _rot intrinsics on non-MS
platforms (authored by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D12271?vs=32925&id=33050#toc
Repository:
rL LLVM
http://reviews.llvm.org/D12271
Files:
cfe/trunk/lib/Headers/Intrin.h
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
Index: cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
===
--- cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
+++ cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
@@ -0,0 +1,89 @@
+// RUN: %clang_cc1 %s -triple=i686-pc-linux -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN:-triple i686--windows -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix CHECK -check-prefix MSC
+
+// Don't include mm_malloc.h, it's system specific.
+#define __MM_MALLOC_H
+
+#ifdef _MSC_VER
+#include
+#else
+#include
+#endif
+
+#ifdef _MSC_VER
+unsigned char test_rotl8(unsigned char v, unsigned char s) {
+ //MSC-LABEL: test_rotl8
+ //MSC-NOT: call
+ return _rotl8(v, s);
+}
+
+unsigned char test_rotr8(unsigned char v, unsigned char s) {
+ //MSC-LABEL: test_rotr8
+ //MSC-NOT: call
+ return _rotr8(v, s);
+}
+
+unsigned short test_rotl16(unsigned short v, unsigned char s) {
+ //MSC-LABEL: test_rotl16
+ //MSC-NOT: call
+ return _rotl16(v, s);
+}
+
+unsigned short test_rotr16(unsigned short v, unsigned char s) {
+ //MSC-LABEL: test_rotr16
+ //MSC-NOT: call
+ return _rotr16(v, s);
+}
+
+unsigned __int64 test_rotl64(unsigned __int64 v, int s) {
+ //MSC-LABEL: test_rotl64
+ //MSC-NOT: call
+ return _rotl64(v, s);
+}
+
+unsigned __int64 test_rotr64(unsigned __int64 v, int s) {
+ //MSC-LABEL: test_rotr64
+ //MSC-NOT: call
+ return _rotr64(v, s);
+}
+#endif
+
+unsigned short test_rotwl(unsigned short v, unsigned short s) {
+ //CHECK-LABEL: test_rotwl
+ //CHECK-NOT: call
+ return _rotwl(v, s);
+}
+
+unsigned short test_rotwr(unsigned short v, unsigned short s) {
+ //CHECK-LABEL: test_rotwr
+ //CHECK-NOT: call
+ return _rotwr(v, s);
+}
+
+unsigned int test_rotl(unsigned int v, int s) {
+ //CHECK-LABEL: test_rotl
+ //CHECK-NOT: call
+ return _rotl(v, s);
+}
+
+unsigned int test_rotr(unsigned int v, int s) {
+ //CHECK-LABEL: test_rotr
+ //CHECK-NOT: call
+ return _rotr(v, s);
+}
+
+unsigned long test_lrotl(unsigned long v, int s) {
+ //CHECK-LABEL: test_lrotl
+ //CHECK-NOT: call
+ return _lrotl(v, s);
+}
+
+unsigned long test_lrotr(unsigned long v, int s) {
+ //CHECK-LABEL: test_lrotr
+ //CHECK-NOT: call
+ return _lrotr(v, s);
+}
+
+//CHECK-LABEL: attributes
Index: cfe/trunk/lib/Headers/immintrin.h
===
--- cfe/trunk/lib/Headers/immintrin.h
+++ cfe/trunk/lib/Headers/immintrin.h
@@ -148,4 +148,58 @@
* whereas others are also available at all times. */
#include
+static __inline__ unsigned short __attribute__((__always_inline__, __nodebug__))
+_rotwl(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value << _Shift) | (_Value >> (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned short __attribute__((__always_inline__, __nodebug__))
+_rotwr(unsigned short _Value, int _Shift) {
+ _Shift &= 0xf;
+ return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotl(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
+_rotr(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+
+/*
+ * MS defines _lrotl/_lrotr in a slightly incompatible way, since
+ * unsigned long is always 32-bit in MSVC.
+ */
+#ifdef _MSC_VER
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+#else
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (64 - _Shift)) : _Value;
+}
+
+static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x3f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (64 -
r245929 - Revert r245923 since it breaks mingw.
Author: mkuper
Date: Tue Aug 25 06:42:31 2015
New Revision: 245929
URL: http://llvm.org/viewvc/llvm-project?rev=245929&view=rev
Log:
Revert r245923 since it breaks mingw.
Removed:
cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
Modified:
cfe/trunk/lib/Headers/Intrin.h
cfe/trunk/lib/Headers/immintrin.h
Modified: cfe/trunk/lib/Headers/Intrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/Intrin.h?rev=245929&r1=245928&r2=245929&view=diff
==
--- cfe/trunk/lib/Headers/Intrin.h (original)
+++ cfe/trunk/lib/Headers/Intrin.h Tue Aug 25 06:42:31 2015
@@ -463,6 +463,26 @@ _rotr16(unsigned short _Value, unsigned
_Shift &= 0xf;
return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
}
+static __inline__ unsigned int __DEFAULT_FN_ATTRS
+_rotl(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+static __inline__ unsigned int __DEFAULT_FN_ATTRS
+_rotr(unsigned int _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
+static __inline__ unsigned long __DEFAULT_FN_ATTRS
+_lrotl(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
+}
+static __inline__ unsigned long __DEFAULT_FN_ATTRS
+_lrotr(unsigned long _Value, int _Shift) {
+ _Shift &= 0x1f;
+ return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
+}
static
__inline__ unsigned __int64 __DEFAULT_FN_ATTRS
_rotl64(unsigned __int64 _Value, int _Shift) {
Modified: cfe/trunk/lib/Headers/immintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/immintrin.h?rev=245929&r1=245928&r2=245929&view=diff
==
--- cfe/trunk/lib/Headers/immintrin.h (original)
+++ cfe/trunk/lib/Headers/immintrin.h Tue Aug 25 06:42:31 2015
@@ -148,58 +148,4 @@ _writegsbase_u64(unsigned long long __V)
* whereas others are also available at all times. */
#include
-static __inline__ unsigned short __attribute__((__always_inline__,
__nodebug__))
-_rotwl(unsigned short _Value, int _Shift) {
- _Shift &= 0xf;
- return _Shift ? (_Value << _Shift) | (_Value >> (16 - _Shift)) : _Value;
-}
-
-static __inline__ unsigned short __attribute__((__always_inline__,
__nodebug__))
-_rotwr(unsigned short _Value, int _Shift) {
- _Shift &= 0xf;
- return _Shift ? (_Value >> _Shift) | (_Value << (16 - _Shift)) : _Value;
-}
-
-static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
-_rotl(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-
-static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
-_rotr(unsigned int _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
-
-/*
- * MS defines _lrotl/_lrotr in a slightly incompatible way, since
- * unsigned long is always 32-bit in MSVC.
- */
-#ifdef _MSC_VER
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
-_lrotl(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value << _Shift) | (_Value >> (32 - _Shift)) : _Value;
-}
-
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
-_lrotr(unsigned long _Value, int _Shift) {
- _Shift &= 0x1f;
- return _Shift ? (_Value >> _Shift) | (_Value << (32 - _Shift)) : _Value;
-}
-#else
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
-_lrotl(unsigned long _Value, int _Shift) {
- _Shift &= 0x3f;
- return _Shift ? (_Value << _Shift) | (_Value >> (64 - _Shift)) : _Value;
-}
-
-static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
-_lrotr(unsigned long _Value, int _Shift) {
- _Shift &= 0x3f;
- return _Shift ? (_Value >> _Shift) | (_Value << (64 - _Shift)) : _Value;
-}
-#endif
-
#endif /* __IMMINTRIN_H */
Removed: cfe/trunk/test/CodeGen/x86-rot-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/x86-rot-intrinsics.c?rev=245928&view=auto
==
--- cfe/trunk/test/CodeGen/x86-rot-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/x86-rot-intrinsics.c (removed)
@@ -1,89 +0,0 @@
-// RUN: %clang_cc1 %s -triple=i686-pc-linux -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility
-fms-compatibility-version=17.00 \
-// RUN:-triple i686--windows -emit-llvm %s -o - \
-// RUN: | FileCheck %s -check-prefix CHECK -check-prefix MSC
-
-// Don't include mm_malloc.h, it's system specific.
-#define __MM_MALLOC_H
-
-#ifdef _MSC_VER
-#include
-#else
-#include
-#endif
-
-#ifdef _MSC_VER
-unsigned ch
[PATCH] D13554: [X86] Enable soft float ABI for x86
mkuper created this revision.
mkuper added reviewers: rafael, rnk.
mkuper added a subscriber: cfe-commits.
The Intel MCU psABI is a new soft-float ABI, based on the IA32 psABI.
The document describing the ABI can be found here:
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Perhaps the biggest difference between the IA32 and MCU ABIs is that the MCU
ABI is soft-float.
This patch makes the x86-32 ABI code respect "-mfloat-abi soft" and generate
float inreg arguments.
This is the first patch in a series - there will be separate patches to add the
"-miamcu" driver option, as well as more ABI adjustments to actually make it
work.
(I'll clean up the one-letter variable names in a separate commit.)
http://reviews.llvm.org/D13554
Files:
lib/CodeGen/TargetInfo.cpp
test/CodeGen/x86-soft-float.c
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -798,6 +798,7 @@
bool IsDarwinVectorABI;
bool IsSmallStructInRegABI;
bool IsWin32StructABI;
+ bool IsSoftFloatABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -846,16 +847,17 @@
QualType Ty) const override;
X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
-unsigned r)
+unsigned r, bool s)
: ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
- IsWin32StructABI(w), DefaultNumRegisterParameters(r) {}
+ IsWin32StructABI(w), DefaultNumRegisterParameters(r),
+ IsSoftFloatABI(s) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
- bool d, bool p, bool w, unsigned r)
-:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
+ bool d, bool p, bool w, unsigned r, bool s)
+:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r, s)) {}
static bool isStructReturnInRegABI(
const llvm::Triple &Triple, const CodeGenOptions &Opts);
@@ -1206,10 +1208,12 @@
bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
bool &NeedsPadding) const {
NeedsPadding = false;
- Class C = classify(Ty);
- if (C == Float)
-return false;
-
+ if (!IsSoftFloatABI) {
+Class C = classify(Ty);
+if (C == Float)
+ return false;
+ }
+
unsigned Size = getContext().getTypeSize(Ty);
unsigned SizeInRegs = (Size + 31) / 32;
@@ -1877,7 +1881,7 @@
public:
WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
bool d, bool p, bool w, unsigned RegParms)
-: X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms) {}
+: X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms, false) {}
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
CodeGen::CodeGenModule &CGM) const override;
@@ -7389,7 +7393,8 @@
} else {
return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
Types, IsDarwinVectorABI, IsSmallStructInRegABI,
- IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
+ IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
+ CodeGenOpts.FloatABI == "soft"));
}
}
Index: test/CodeGen/x86-soft-float.c
===
--- test/CodeGen/x86-soft-float.c
+++ test/CodeGen/x86-soft-float.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o -
| FileCheck %s -check-prefix=HARD
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft
-emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT
+
+// HARD: define void @f1(float %a)
+// SOFT: define void @f1(float inreg %a)
+void f1(float a) {}
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -798,6 +798,7 @@
bool IsDarwinVectorABI;
bool IsSmallStructInRegABI;
bool IsWin32StructABI;
+ bool IsSoftFloatABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -846,16 +847,17 @@
QualType Ty) const override;
X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
-unsigned r)
+unsigned r, bool s)
: ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
- IsWin32StructABI(w), DefaultNumRegisterParameters(r) {}
+ IsWin32StructABI(w), DefaultNumRegisterParameters(r),
+ IsSoftFloatABI(s) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
- bool d, bool p, bool w, unsigned r)
-:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
+ bool d, bool p, bool w, unsigned r, bool s)
+
Re: [PATCH] D13554: [X86] Enable soft float ABI for x86
mkuper added a comment. It's ok, thanks a lot for taking the time to review it! http://reviews.llvm.org/D13554 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r250687 - Use saner variable names. NFC.
Author: mkuper
Date: Mon Oct 19 02:52:25 2015
New Revision: 250687
URL: http://llvm.org/viewvc/llvm-project?rev=250687&view=rev
Log:
Use saner variable names. NFC.
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=250687&r1=250686&r2=250687&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Oct 19 02:52:25 2015
@@ -796,7 +796,7 @@ class X86_32ABIInfo : public ABIInfo {
static const unsigned MinABIStackAlignInBytes = 4;
bool IsDarwinVectorABI;
- bool IsSmallStructInRegABI;
+ bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
unsigned DefaultNumRegisterParameters;
@@ -845,17 +845,23 @@ public:
Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
QualType Ty) const override;
- X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool d, bool p, bool w,
-unsigned r)
-: ABIInfo(CGT), IsDarwinVectorABI(d), IsSmallStructInRegABI(p),
- IsWin32StructABI(w), DefaultNumRegisterParameters(r) {}
+ X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
+bool RetSmallStructInRegABI, bool Win32StructABI,
+unsigned NumRegisterParameters)
+: ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
+ IsRetSmallStructInRegABI(RetSmallStructInRegABI),
+ IsWin32StructABI(Win32StructABI),
+ DefaultNumRegisterParameters(NumRegisterParameters) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
- X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
- bool d, bool p, bool w, unsigned r)
-:TargetCodeGenInfo(new X86_32ABIInfo(CGT, d, p, w, r)) {}
+ X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
+ bool RetSmallStructInRegABI, bool Win32StructABI,
+ unsigned NumRegisterParameters)
+ : TargetCodeGenInfo(
+new X86_32ABIInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
+ Win32StructABI, NumRegisterParameters)) {}
static bool isStructReturnInRegABI(
const llvm::Triple &Triple, const CodeGenOptions &Opts);
@@ -978,7 +984,7 @@ void X86_32TargetCodeGenInfo::addReturnR
}
/// shouldReturnTypeInRegister - Determine if the given type should be
-/// passed in a register (for the Darwin ABI).
+/// returned in a register (for the Darwin ABI).
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
@@ -1083,7 +1089,7 @@ ABIArgInfo X86_32ABIInfo::classifyReturn
}
// If specified, structs and unions are always indirect.
-if (!IsSmallStructInRegABI && !RetTy->isAnyComplexType())
+if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
return getIndirectReturnResult(RetTy, State);
// Small structures which are register sized are generally returned
@@ -1876,8 +1882,10 @@ static std::string qualifyWindowsLibrary
class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo {
public:
WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT,
-bool d, bool p, bool w, unsigned RegParms)
-: X86_32TargetCodeGenInfo(CGT, d, p, w, RegParms) {}
+bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
+unsigned NumRegisterParameters)
+: X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
+Win32StructABI, NumRegisterParameters) {}
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
CodeGen::CodeGenModule &CGM) const override;
@@ -7378,17 +7386,17 @@ const TargetCodeGenInfo &CodeGenModule::
case llvm::Triple::x86: {
bool IsDarwinVectorABI = Triple.isOSDarwin();
-bool IsSmallStructInRegABI =
+bool RetSmallStructInRegABI =
X86_32TargetCodeGenInfo::isStructReturnInRegABI(Triple, CodeGenOpts);
bool IsWin32FloatStructABI = Triple.isOSWindows() && !Triple.isOSCygMing();
if (Triple.getOS() == llvm::Triple::Win32) {
return *(TheTargetCodeGenInfo = new WinX86_32TargetCodeGenInfo(
- Types, IsDarwinVectorABI, IsSmallStructInRegABI,
+ Types, IsDarwinVectorABI, RetSmallStructInRegABI,
IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
} else {
return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
- Types, IsDarwinVectorABI, IsSmallStructInRegABI,
+ Types, IsDarwinVectorABI, RetSmallStructInRegABI,
IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
}
}
___
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r250689 - [X86] Enable soft float ABI for x86
Author: mkuper
Date: Mon Oct 19 03:09:43 2015
New Revision: 250689
URL: http://llvm.org/viewvc/llvm-project?rev=250689&view=rev
Log:
[X86] Enable soft float ABI for x86
The Intel MCU psABI requires floating-point values to be passed in-reg.
This makes the x86-32 ABI code respect "-mfloat-abi soft" and generate float
inreg arguments.
Differential Revision: http://reviews.llvm.org/D13554
Added:
cfe/trunk/test/CodeGen/x86-soft-float.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=250689&r1=250688&r2=250689&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Oct 19 03:09:43 2015
@@ -798,6 +798,7 @@ class X86_32ABIInfo : public ABIInfo {
bool IsDarwinVectorABI;
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
+ bool IsSoftFloatABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -847,21 +848,22 @@ public:
X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
-unsigned NumRegisterParameters)
+unsigned NumRegisterParameters, bool SoftFloatABI)
: ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
- DefaultNumRegisterParameters(NumRegisterParameters) {}
+ DefaultNumRegisterParameters(NumRegisterParameters),
+ IsSoftFloatABI(SoftFloatABI) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
- unsigned NumRegisterParameters)
- : TargetCodeGenInfo(
-new X86_32ABIInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
- Win32StructABI, NumRegisterParameters)) {}
+ unsigned NumRegisterParameters, bool SoftFloatABI)
+ : TargetCodeGenInfo(new X86_32ABIInfo(
+CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
+NumRegisterParameters, SoftFloatABI)) {}
static bool isStructReturnInRegABI(
const llvm::Triple &Triple, const CodeGenOptions &Opts);
@@ -1212,9 +1214,11 @@ X86_32ABIInfo::Class X86_32ABIInfo::clas
bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
bool &NeedsPadding) const {
NeedsPadding = false;
- Class C = classify(Ty);
- if (C == Float)
-return false;
+ if (!IsSoftFloatABI) {
+Class C = classify(Ty);
+if (C == Float)
+ return false;
+ }
unsigned Size = getContext().getTypeSize(Ty);
unsigned SizeInRegs = (Size + 31) / 32;
@@ -1885,7 +1889,7 @@ public:
bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
unsigned NumRegisterParameters)
: X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
-Win32StructABI, NumRegisterParameters) {}
+Win32StructABI, NumRegisterParameters, false) {}
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
CodeGen::CodeGenModule &CGM) const override;
@@ -7397,7 +7401,8 @@ const TargetCodeGenInfo &CodeGenModule::
} else {
return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
Types, IsDarwinVectorABI, RetSmallStructInRegABI,
- IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
+ IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
+ CodeGenOpts.FloatABI == "soft"));
}
}
Added: cfe/trunk/test/CodeGen/x86-soft-float.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/x86-soft-float.c?rev=250689&view=auto
==
--- cfe/trunk/test/CodeGen/x86-soft-float.c (added)
+++ cfe/trunk/test/CodeGen/x86-soft-float.c Mon Oct 19 03:09:43 2015
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o -
| FileCheck %s -check-prefix=HARD
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft
-emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT
+
+// HARD: define void @f1(float %a)
+// SOFT: define void @f1(float inreg %a)
+void f1(float a) {}
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Re: [PATCH] D13554: [X86] Enable soft float ABI for x86
This revision was automatically updated to reflect the committed changes.
Closed by commit rL250689: [X86] Enable soft float ABI for x86 (authored by
mkuper).
Changed prior to commit:
http://reviews.llvm.org/D13554?vs=36853&id=37723#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13554
Files:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/x86-soft-float.c
Index: cfe/trunk/test/CodeGen/x86-soft-float.c
===
--- cfe/trunk/test/CodeGen/x86-soft-float.c
+++ cfe/trunk/test/CodeGen/x86-soft-float.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o -
| FileCheck %s -check-prefix=HARD
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft
-emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT
+
+// HARD: define void @f1(float %a)
+// SOFT: define void @f1(float inreg %a)
+void f1(float a) {}
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -798,6 +798,7 @@
bool IsDarwinVectorABI;
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
+ bool IsSoftFloatABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -847,21 +848,22 @@
X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
-unsigned NumRegisterParameters)
+unsigned NumRegisterParameters, bool SoftFloatABI)
: ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
- DefaultNumRegisterParameters(NumRegisterParameters) {}
+ DefaultNumRegisterParameters(NumRegisterParameters),
+ IsSoftFloatABI(SoftFloatABI) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
- unsigned NumRegisterParameters)
- : TargetCodeGenInfo(
-new X86_32ABIInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
- Win32StructABI, NumRegisterParameters)) {}
+ unsigned NumRegisterParameters, bool SoftFloatABI)
+ : TargetCodeGenInfo(new X86_32ABIInfo(
+CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
+NumRegisterParameters, SoftFloatABI)) {}
static bool isStructReturnInRegABI(
const llvm::Triple &Triple, const CodeGenOptions &Opts);
@@ -1212,9 +1214,11 @@
bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
bool &NeedsPadding) const {
NeedsPadding = false;
- Class C = classify(Ty);
- if (C == Float)
-return false;
+ if (!IsSoftFloatABI) {
+Class C = classify(Ty);
+if (C == Float)
+ return false;
+ }
unsigned Size = getContext().getTypeSize(Ty);
unsigned SizeInRegs = (Size + 31) / 32;
@@ -1885,7 +1889,7 @@
bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
unsigned NumRegisterParameters)
: X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
-Win32StructABI, NumRegisterParameters) {}
+Win32StructABI, NumRegisterParameters, false) {}
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
CodeGen::CodeGenModule &CGM) const override;
@@ -7397,7 +7401,8 @@
} else {
return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
Types, IsDarwinVectorABI, RetSmallStructInRegABI,
- IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters));
+ IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
+ CodeGenOpts.FloatABI == "soft"));
}
}
Index: cfe/trunk/test/CodeGen/x86-soft-float.c
===
--- cfe/trunk/test/CodeGen/x86-soft-float.c
+++ cfe/trunk/test/CodeGen/x86-soft-float.c
@@ -0,0 +1,6 @@
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o - | FileCheck %s -check-prefix=HARD
+// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft -emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT
+
+// HARD: define void @f1(float %a)
+// SOFT: define void @f1(float inreg %a)
+void f1(float a) {}
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -798,6 +798,7 @@
bool IsDarwinVectorABI;
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
+ bool IsSoftFloatABI;
unsigned
[PATCH] D13978: [X86] Support MCU psABI when marking inregs
mkuper created this revision.
mkuper added reviewers: rnk, rafael.
mkuper added a subscriber: cfe-commits.
mkuper added a dependency: D13977: [X86] Add elfiamcu triple support, and a
workaround for PR3997.
Herald added a subscriber: aemerson.
The MCU psABI has a calling convention that is somewhat, but not quite, like
-mregparm 3.
This adds support for this calling convention.
It depends on D13977 which introduces MCU triple support.
http://reviews.llvm.org/D13978
Files:
lib/CodeGen/TargetInfo.cpp
test/CodeGen/x86_32-arguments-iamcu.c
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -799,6 +799,7 @@
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
bool IsSoftFloatABI;
+ bool IsMCUABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -848,22 +849,24 @@
X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
-unsigned NumRegisterParameters, bool SoftFloatABI)
+unsigned NumRegisterParameters, bool SoftFloatABI,
+bool MCUABI)
: ABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI),
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
- IsSoftFloatABI(SoftFloatABI),
+ IsSoftFloatABI(SoftFloatABI), IsMCUABI(MCUABI),
DefaultNumRegisterParameters(NumRegisterParameters) {}
};
class X86_32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI,
bool RetSmallStructInRegABI, bool Win32StructABI,
- unsigned NumRegisterParameters, bool SoftFloatABI)
+ unsigned NumRegisterParameters, bool SoftFloatABI,
+ bool MCUABI)
: TargetCodeGenInfo(new X86_32ABIInfo(
CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI,
-NumRegisterParameters, SoftFloatABI)) {}
+NumRegisterParameters, SoftFloatABI, MCUABI)) {}
static bool isStructReturnInRegABI(
const llvm::Triple &Triple, const CodeGenOptions &Opts);
@@ -986,7 +989,7 @@
}
/// shouldReturnTypeInRegister - Determine if the given type should be
-/// returned in a register (for the Darwin ABI).
+/// returned in a register (for the Darwin and MCU ABI).
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
@@ -1226,9 +1229,18 @@
if (SizeInRegs == 0)
return false;
- if (SizeInRegs > State.FreeRegs) {
-State.FreeRegs = 0;
-return false;
+ if (!IsMCUABI) {
+if (SizeInRegs > State.FreeRegs) {
+ State.FreeRegs = 0;
+ return false;
+}
+ } else {
+// The MCU psABI allows passing parameters in-reg even if there are
+// earlier, parameters that are passed on the stack. Also,
+// it does not allow passing >8-byte structs in-register,
+// even if there are 3 free registers available.
+if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
+ return false;
}
State.FreeRegs -= SizeInRegs;
@@ -1372,6 +1384,8 @@
State.FreeSSERegs = 6;
} else if (FI.getHasRegParm())
State.FreeRegs = FI.getRegParm();
+ else if (IsMCUABI)
+State.FreeRegs = 3;
else
State.FreeRegs = DefaultNumRegisterParameters;
@@ -1520,7 +1534,7 @@
return true;
}
- if (Triple.isOSDarwin())
+ if (Triple.isOSDarwin() || Triple.isEnvironmentIAMCU())
return true;
switch (Triple.getOS()) {
@@ -1889,7 +1903,7 @@
bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI,
unsigned NumRegisterParameters)
: X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI,
-Win32StructABI, NumRegisterParameters, false) {}
+Win32StructABI, NumRegisterParameters, false, false) {}
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
CodeGen::CodeGenModule &CGM) const override;
@@ -7402,7 +7416,7 @@
return *(TheTargetCodeGenInfo = new X86_32TargetCodeGenInfo(
Types, IsDarwinVectorABI, RetSmallStructInRegABI,
IsWin32FloatStructABI, CodeGenOpts.NumRegisterParameters,
- CodeGenOpts.FloatABI == "soft"));
+ CodeGenOpts.FloatABI == "soft", Triple.isEnvironmentIAMCU()));
}
}
Index: test/CodeGen/x86_32-arguments-iamcu.c
===
--- test/CodeGen/x86_32-arguments-iamcu.c
+++ test/CodeGen/x86_32-arguments-iamcu.c
@@ -0,0 +1,52 @@
+// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: define void
Re: [PATCH] D13978: [X86] Support MCU psABI when marking inregs
mkuper added inline comments.
Comment at: lib/CodeGen/TargetInfo.cpp:857
@@ -854,3 +856,3 @@
IsWin32StructABI(Win32StructABI),
- IsSoftFloatABI(SoftFloatABI),
+ IsSoftFloatABI(SoftFloatABI), IsMCUABI(MCUABI),
DefaultNumRegisterParameters(NumRegisterParameters) {}
rnk wrote:
> Rather than taking this as a parameter, how about initializing IsMCUABI with
> `getTarget().getTriple().isEnvironmentIAMCU()`? Then you can drop a level of
> parameters.
Sure, will do.
Comment at: test/CodeGen/x86_32-arguments-iamcu.c:1
@@ +1,2 @@
+// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o
- %s | FileCheck %s
+
DavidKreitzer wrote:
> Good test!
>
> I think it would be a good idea to add a varargs function & verify that the
> args do not get marked inreg.
They do get marked inreg, actually.
The varargs handling for -mregparm - and that means for IAMCU as well - happens
on the CG level.
```
def CC_X86_32_C : CallingConv<[
...
// The first 3 integer arguments, if marked 'inreg' and if the call is not
// a vararg call, are passed in integer registers.
**CCIfNotVarArg**>>>,
...
]>;
```
(Yes, this is incredibly ugly. We should probably fix that in a separate patch.)
http://reviews.llvm.org/D13978
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Re: [PATCH] D13978: [X86] Support MCU psABI when marking inregs
This revision was automatically updated to reflect the committed changes.
Closed by commit rL251224: [X86] Mark inregs correctly for MCU psABI (authored
by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D13978?vs=38107&id=38341#toc
Repository:
rL LLVM
http://reviews.llvm.org/D13978
Files:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
Index: cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
===
--- cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
+++ cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
@@ -0,0 +1,58 @@
+// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s
+
+// CHECK-LABEL: define void @ints(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 %d)
+void ints(int a, int b, int c, int d) {}
+
+// CHECK-LABEL: define void @floats(float inreg %a, float inreg %b, float inreg %c, float %d)
+void floats(float a, float b, float c, float d) {}
+
+// CHECK-LABEL: define void @mixed(i32 inreg %a, float inreg %b, i32 inreg %c, float %d)
+void mixed(int a, float b, int c, float d) {}
+
+// CHECK-LABEL: define void @doubles(double inreg %d1, double %d2)
+void doubles(double d1, double d2) {}
+
+// CHECK-LABEL: define void @mixedDoubles(i32 inreg %a, double inreg %d1)
+void mixedDoubles(int a, double d1) {}
+
+typedef struct st4_t {
+ int a;
+} st4_t;
+
+typedef struct st5_t {
+ int a;
+ char b;
+} st5_t;
+
+typedef struct st12_t {
+ int a;
+ int b;
+ int c;
+} st12_t;
+
+// CHECK-LABEL: define void @smallStructs(i32 inreg %st1.coerce, i32 inreg %st2.coerce, i32 inreg %st3.coerce)
+void smallStructs(st4_t st1, st4_t st2, st4_t st3) {}
+
+// CHECK-LABEL: define void @paddedStruct(i32 inreg %i1, i32 inreg %st.coerce0, i32 inreg %st.coerce1, i32 %st4.0)
+void paddedStruct(int i1, st5_t st, st4_t st4) {}
+
+// CHECK-LABEL: define void @largeStruct(i32 %st.0, i32 %st.1, i32 %st.2)
+void largeStruct(st12_t st) {}
+
+// CHECK-LABEL: define void @largeStructMiddle(i32 inreg %i1, i32 %st.0, i32 %st.1, i32 %st.2, i32 inreg %i2, i32 inreg %i3)
+void largeStructMiddle(int i1, st12_t st, int i2, int i3) {}
+
+// CHECK-LABEL: define i32 @retSmallStruct(i32 inreg %r.coerce)
+st4_t retSmallStruct(st4_t r) { return r; }
+
+// CHECK-LABEL: define i64 @retPaddedStruct(i32 inreg %r.coerce0, i32 inreg %r.coerce1)
+st5_t retPaddedStruct(st5_t r) { return r; }
+
+// CHECK-LABEL: define void @retLargeStruct(%struct.st12_t* inreg noalias sret %agg.result, i32 inreg %i1, i32 %r.0, i32 %r.1, i32 %r.2)
+st12_t retLargeStruct(int i1, st12_t r) { return r; }
+
+// FIXME: We really shouldn't be marking this inreg. Right now the
+// inreg gets ignored by the CG for varargs functions, but that's
+// insane.
+// CHECK-LABEL: define i32 @varArgs(i32 inreg %i1, ...)
+int varArgs(int i1, ...) { return i1; }
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -799,6 +799,7 @@
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
bool IsSoftFloatABI;
+ bool IsMCUABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -853,6 +854,7 @@
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
IsSoftFloatABI(SoftFloatABI),
+ IsMCUABI(CGT.getTarget().getTriple().isEnvironmentIAMCU()),
DefaultNumRegisterParameters(NumRegisterParameters) {}
};
@@ -986,7 +988,7 @@
}
/// shouldReturnTypeInRegister - Determine if the given type should be
-/// returned in a register (for the Darwin ABI).
+/// returned in a register (for the Darwin and MCU ABI).
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
@@ -1226,9 +1228,18 @@
if (SizeInRegs == 0)
return false;
- if (SizeInRegs > State.FreeRegs) {
-State.FreeRegs = 0;
-return false;
+ if (!IsMCUABI) {
+if (SizeInRegs > State.FreeRegs) {
+ State.FreeRegs = 0;
+ return false;
+}
+ } else {
+// The MCU psABI allows passing parameters in-reg even if there are
+// earlier parameters that are passed on the stack. Also,
+// it does not allow passing >8-byte structs in-register,
+// even if there are 3 free registers available.
+if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
+ return false;
}
State.FreeRegs -= SizeInRegs;
@@ -1372,6 +1383,8 @@
State.FreeSSERegs = 6;
} else if (FI.getHasRegParm())
State.FreeRegs = FI.getRegParm();
+ else if (IsMCUABI)
+State.FreeRegs = 3;
else
State.FreeRegs = DefaultNumRegisterParameters;
@@ -1520,7 +1533,7 @@
return true;
}
- if (Triple.isOSDarwin())
+ if (Triple.isOSDarwin() || Triple.isEnvironmentIAMCU())
return tru
r251224 - [X86] Mark inregs correctly for MCU psABI
Author: mkuper
Date: Sun Oct 25 03:18:20 2015
New Revision: 251224
URL: http://llvm.org/viewvc/llvm-project?rev=251224&view=rev
Log:
[X86] Mark inregs correctly for MCU psABI
The MCU psABI calling convention is somewhat, but not quite, like -mregparm 3.
In particular, the rules involving structs are different.
Differential Revision: http://reviews.llvm.org/D13978
Added:
cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=251224&r1=251223&r2=251224&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Sun Oct 25 03:18:20 2015
@@ -799,6 +799,7 @@ class X86_32ABIInfo : public ABIInfo {
bool IsRetSmallStructInRegABI;
bool IsWin32StructABI;
bool IsSoftFloatABI;
+ bool IsMCUABI;
unsigned DefaultNumRegisterParameters;
static bool isRegisterSize(unsigned Size) {
@@ -853,6 +854,7 @@ public:
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
IsSoftFloatABI(SoftFloatABI),
+ IsMCUABI(CGT.getTarget().getTriple().isEnvironmentIAMCU()),
DefaultNumRegisterParameters(NumRegisterParameters) {}
};
@@ -986,7 +988,7 @@ void X86_32TargetCodeGenInfo::addReturnR
}
/// shouldReturnTypeInRegister - Determine if the given type should be
-/// returned in a register (for the Darwin ABI).
+/// returned in a register (for the Darwin and MCU ABI).
bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty,
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
@@ -1226,9 +1228,18 @@ bool X86_32ABIInfo::shouldUseInReg(QualT
if (SizeInRegs == 0)
return false;
- if (SizeInRegs > State.FreeRegs) {
-State.FreeRegs = 0;
-return false;
+ if (!IsMCUABI) {
+if (SizeInRegs > State.FreeRegs) {
+ State.FreeRegs = 0;
+ return false;
+}
+ } else {
+// The MCU psABI allows passing parameters in-reg even if there are
+// earlier parameters that are passed on the stack. Also,
+// it does not allow passing >8-byte structs in-register,
+// even if there are 3 free registers available.
+if (SizeInRegs > State.FreeRegs || SizeInRegs > 2)
+ return false;
}
State.FreeRegs -= SizeInRegs;
@@ -1372,6 +1383,8 @@ void X86_32ABIInfo::computeInfo(CGFuncti
State.FreeSSERegs = 6;
} else if (FI.getHasRegParm())
State.FreeRegs = FI.getRegParm();
+ else if (IsMCUABI)
+State.FreeRegs = 3;
else
State.FreeRegs = DefaultNumRegisterParameters;
@@ -1520,7 +1533,7 @@ bool X86_32TargetCodeGenInfo::isStructRe
return true;
}
- if (Triple.isOSDarwin())
+ if (Triple.isOSDarwin() || Triple.isEnvironmentIAMCU())
return true;
switch (Triple.getOS()) {
Added: cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c?rev=251224&view=auto
==
--- cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c (added)
+++ cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c Sun Oct 25 03:18:20 2015
@@ -0,0 +1,58 @@
+// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o
- %s | FileCheck %s
+
+// CHECK-LABEL: define void @ints(i32 inreg %a, i32 inreg %b, i32 inreg %c,
i32 %d)
+void ints(int a, int b, int c, int d) {}
+
+// CHECK-LABEL: define void @floats(float inreg %a, float inreg %b, float
inreg %c, float %d)
+void floats(float a, float b, float c, float d) {}
+
+// CHECK-LABEL: define void @mixed(i32 inreg %a, float inreg %b, i32 inreg %c,
float %d)
+void mixed(int a, float b, int c, float d) {}
+
+// CHECK-LABEL: define void @doubles(double inreg %d1, double %d2)
+void doubles(double d1, double d2) {}
+
+// CHECK-LABEL: define void @mixedDoubles(i32 inreg %a, double inreg %d1)
+void mixedDoubles(int a, double d1) {}
+
+typedef struct st4_t {
+ int a;
+} st4_t;
+
+typedef struct st5_t {
+ int a;
+ char b;
+} st5_t;
+
+typedef struct st12_t {
+ int a;
+ int b;
+ int c;
+} st12_t;
+
+// CHECK-LABEL: define void @smallStructs(i32 inreg %st1.coerce, i32 inreg
%st2.coerce, i32 inreg %st3.coerce)
+void smallStructs(st4_t st1, st4_t st2, st4_t st3) {}
+
+// CHECK-LABEL: define void @paddedStruct(i32 inreg %i1, i32 inreg
%st.coerce0, i32 inreg %st.coerce1, i32 %st4.0)
+void paddedStruct(int i1, st5_t st, st4_t st4) {}
+
+// CHECK-LABEL: define void @largeStruct(i32 %st.0, i32 %st.1, i32 %st.2)
+void largeStruct(st12_t st) {}
+
+// CHECK-LABEL: define void @largeStructMiddle(i32 inreg %i1, i32 %st.0, i32
%st.1, i32 %st.2, i32 inreg %i2, i32 inreg %i3)
+void largeStructMiddle(int i1, st12_t st, int i2, int i3) {}
+
+// CHECK-LABEL: define i32 @r
r251396 - Access the right triple field for IAMCU.
Author: mkuper
Date: Tue Oct 27 02:46:22 2015
New Revision: 251396
URL: http://llvm.org/viewvc/llvm-project?rev=251396&view=rev
Log:
Access the right triple field for IAMCU.
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=251396&r1=251395&r2=251396&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Tue Oct 27 02:46:22 2015
@@ -854,7 +854,7 @@ public:
IsRetSmallStructInRegABI(RetSmallStructInRegABI),
IsWin32StructABI(Win32StructABI),
IsSoftFloatABI(SoftFloatABI),
- IsMCUABI(CGT.getTarget().getTriple().isEnvironmentIAMCU()),
+ IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()),
DefaultNumRegisterParameters(NumRegisterParameters) {}
};
@@ -1533,7 +1533,7 @@ bool X86_32TargetCodeGenInfo::isStructRe
return true;
}
- if (Triple.isOSDarwin() || Triple.isEnvironmentIAMCU())
+ if (Triple.isOSDarwin() || Triple.isOSIAMCU())
return true;
switch (Triple.getOS()) {
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Re: [PATCH] D14205: [x86] Front-end part of MCU psABI support
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM Comment at: lib/Basic/Targets.cpp:2327 @@ -2325,3 +2326,3 @@ // X87 evaluates with 80 bits "long double" precision. return SSELevel == NoSSE ? 2 : 0; } Do you know if we should also change this to be 0? http://reviews.llvm.org/D14205 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D11753: [X86] Add support for _MM_ALIGN16
This revision was automatically updated to reflect the committed changes.
Closed by commit rL244201: [X86] Add support for _MM_ALIGN16 (authored by
mkuper).
Changed prior to commit:
http://reviews.llvm.org/D11753?vs=31317&id=31430#toc
Repository:
rL LLVM
http://reviews.llvm.org/D11753
Files:
cfe/trunk/lib/Headers/xmmintrin.h
cfe/trunk/test/CodeGen/ms-mm-align.c
Index: cfe/trunk/test/CodeGen/ms-mm-align.c
===
--- cfe/trunk/test/CodeGen/ms-mm-align.c
+++ cfe/trunk/test/CodeGen/ms-mm-align.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility
-fms-compatibility-version=17.00 \
+// RUN: -triple i686--windows -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix CHECK
+
+// Intrin.h needs size_t, but -ffreestanding prevents us from getting it from
+// stddef.h. Work around it with this typedef.
+typedef __SIZE_TYPE__ size_t;
+#include
+
+void capture_ptr(int* i);
+void test_mm_align16(int p) {
+ _MM_ALIGN16 int i;
+ capture_ptr(&i);
+}
+
+// CHECK: alloca i32, align 16
Index: cfe/trunk/lib/Headers/xmmintrin.h
===
--- cfe/trunk/lib/Headers/xmmintrin.h
+++ cfe/trunk/lib/Headers/xmmintrin.h
@@ -924,6 +924,11 @@
return __builtin_ia32_movmskps(__a);
}
+
+#ifdef _MSC_VER
+#define _MM_ALIGN16 __declspec(align(16))
+#endif
+
#define _MM_SHUFFLE(z, y, x, w) (((z) << 6) | ((y) << 4) | ((x) << 2) | (w))
#define _MM_EXCEPT_INVALID(0x0001)
Index: cfe/trunk/test/CodeGen/ms-mm-align.c
===
--- cfe/trunk/test/CodeGen/ms-mm-align.c
+++ cfe/trunk/test/CodeGen/ms-mm-align.c
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility -fms-compatibility-version=17.00 \
+// RUN: -triple i686--windows -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix CHECK
+
+// Intrin.h needs size_t, but -ffreestanding prevents us from getting it from
+// stddef.h. Work around it with this typedef.
+typedef __SIZE_TYPE__ size_t;
+#include
+
+void capture_ptr(int* i);
+void test_mm_align16(int p) {
+ _MM_ALIGN16 int i;
+ capture_ptr(&i);
+}
+
+// CHECK: alloca i32, align 16
Index: cfe/trunk/lib/Headers/xmmintrin.h
===
--- cfe/trunk/lib/Headers/xmmintrin.h
+++ cfe/trunk/lib/Headers/xmmintrin.h
@@ -924,6 +924,11 @@
return __builtin_ia32_movmskps(__a);
}
+
+#ifdef _MSC_VER
+#define _MM_ALIGN16 __declspec(align(16))
+#endif
+
#define _MM_SHUFFLE(z, y, x, w) (((z) << 6) | ((y) << 4) | ((x) << 2) | (w))
#define _MM_EXCEPT_INVALID(0x0001)
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r244201 - [X86] Add support for _MM_ALIGN16
Author: mkuper
Date: Thu Aug 6 03:24:38 2015
New Revision: 244201
URL: http://llvm.org/viewvc/llvm-project?rev=244201&view=rev
Log:
[X86] Add support for _MM_ALIGN16
Differential Revision: http://reviews.llvm.org/D11753
Added:
cfe/trunk/test/CodeGen/ms-mm-align.c
Modified:
cfe/trunk/lib/Headers/xmmintrin.h
Modified: cfe/trunk/lib/Headers/xmmintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/xmmintrin.h?rev=244201&r1=244200&r2=244201&view=diff
==
--- cfe/trunk/lib/Headers/xmmintrin.h (original)
+++ cfe/trunk/lib/Headers/xmmintrin.h Thu Aug 6 03:24:38 2015
@@ -924,6 +924,11 @@ _mm_movemask_ps(__m128 __a)
return __builtin_ia32_movmskps(__a);
}
+
+#ifdef _MSC_VER
+#define _MM_ALIGN16 __declspec(align(16))
+#endif
+
#define _MM_SHUFFLE(z, y, x, w) (((z) << 6) | ((y) << 4) | ((x) << 2) | (w))
#define _MM_EXCEPT_INVALID(0x0001)
Added: cfe/trunk/test/CodeGen/ms-mm-align.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-mm-align.c?rev=244201&view=auto
==
--- cfe/trunk/test/CodeGen/ms-mm-align.c (added)
+++ cfe/trunk/test/CodeGen/ms-mm-align.c Thu Aug 6 03:24:38 2015
@@ -0,0 +1,16 @@
+// RUN: %clang_cc1 -ffreestanding -fms-extensions -fms-compatibility
-fms-compatibility-version=17.00 \
+// RUN: -triple i686--windows -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix CHECK
+
+// Intrin.h needs size_t, but -ffreestanding prevents us from getting it from
+// stddef.h. Work around it with this typedef.
+typedef __SIZE_TYPE__ size_t;
+#include
+
+void capture_ptr(int* i);
+void test_mm_align16(int p) {
+ _MM_ALIGN16 int i;
+ capture_ptr(&i);
+}
+
+// CHECK: alloca i32, align 16
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Re: [PATCH] D11476: Marked call instruction in thunk function with tail attribute when applicable
This revision was automatically updated to reflect the committed changes.
Closed by commit rL244207: Mark calls in thunk functions as tail-call
optimization candidates (authored by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D11476?vs=31341&id=31440#toc
Repository:
rL LLVM
http://reviews.llvm.org/D11476
Files:
cfe/trunk/lib/CodeGen/CGVTables.cpp
cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
Index: cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
===
--- cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
+++ cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
@@ -176,7 +176,7 @@
// Do an adjustment from B* to C*.
// DTORS2: getelementptr i8, i8* %{{.*}}, i32 -4
// DTORS2: bitcast i8* %{{.*}} to %"struct.dtor_in_second_nvbase::C"*
-// DTORS2: %[[CALL:.*]] = call x86_thiscallcc i8*
@"\01??_GC@dtor_in_second_nvbase@@UAEPAXI@Z"
+// DTORS2: %[[CALL:.*]] = tail call x86_thiscallcc i8*
@"\01??_GC@dtor_in_second_nvbase@@UAEPAXI@Z"
// DTORS2: ret i8* %[[CALL]]
}
Index: cfe/trunk/lib/CodeGen/CGVTables.cpp
===
--- cfe/trunk/lib/CodeGen/CGVTables.cpp
+++ cfe/trunk/lib/CodeGen/CGVTables.cpp
@@ -312,6 +312,8 @@
// Consider return adjustment if we have ThunkInfo.
if (Thunk && !Thunk->Return.isEmpty())
RV = PerformReturnAdjustment(*this, ResultType, RV, *Thunk);
+ else if (llvm::CallInst* Call = dyn_cast(CallOrInvoke))
+Call->setTailCallKind(llvm::CallInst::TCK_Tail);
// Emit return.
if (!ResultType->isVoidType() && Slot.isNull())
Index: cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
===
--- cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
+++ cfe/trunk/test/CodeGenCXX/microsoft-abi-structors.cpp
@@ -176,7 +176,7 @@
// Do an adjustment from B* to C*.
// DTORS2: getelementptr i8, i8* %{{.*}}, i32 -4
// DTORS2: bitcast i8* %{{.*}} to %"struct.dtor_in_second_nvbase::C"*
-// DTORS2: %[[CALL:.*]] = call x86_thiscallcc i8* @"\01??_GC@dtor_in_second_nvbase@@UAEPAXI@Z"
+// DTORS2: %[[CALL:.*]] = tail call x86_thiscallcc i8* @"\01??_GC@dtor_in_second_nvbase@@UAEPAXI@Z"
// DTORS2: ret i8* %[[CALL]]
}
Index: cfe/trunk/lib/CodeGen/CGVTables.cpp
===
--- cfe/trunk/lib/CodeGen/CGVTables.cpp
+++ cfe/trunk/lib/CodeGen/CGVTables.cpp
@@ -312,6 +312,8 @@
// Consider return adjustment if we have ThunkInfo.
if (Thunk && !Thunk->Return.isEmpty())
RV = PerformReturnAdjustment(*this, ResultType, RV, *Thunk);
+ else if (llvm::CallInst* Call = dyn_cast(CallOrInvoke))
+Call->setTailCallKind(llvm::CallInst::TCK_Tail);
// Emit return.
if (!ResultType->isVoidType() && Slot.isNull())
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Re: [PATCH] D22900: Revert r244207 - Mark calls in thunk functions as tail-call optimization
mkuper resigned from this revision. mkuper removed a reviewer: mkuper. mkuper added a comment. I really don't understand anything about this. :-) https://reviews.llvm.org/D22900 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D22900: Revert r244207 - Mark calls in thunk functions as tail-call optimization
I care highly about my commits. It's just that it's not actually my commit, I committed it on Amjad's behalf before he had commit permissions. :-) I think Eli missed the "Patch by" line when he originally added me to the thread. On Fri, Jul 29, 2016 at 11:16 AM, Gerolf Hoflehner wrote: > Sounds like you care highly about your commit :-) > > > > On Jul 29, 2016, at 10:10 AM, Michael Kuperstein > wrote: > > > > mkuper resigned from this revision. > > mkuper removed a reviewer: mkuper. > > mkuper added a comment. > > > > I really don't understand anything about this. :-) > > > > > > https://reviews.llvm.org/D22900 > > > > > > > > ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D17092: [X86] Add -mseparate-stack-seg
mkuper resigned from this revision. mkuper removed a reviewer: mkuper. mkuper added a comment. I really don't know enough about this part of clang either. http://reviews.llvm.org/D17092 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
mkuper added a comment. Could you point me to where in the documentation it says they must be zero-extended? The Intel intrinsics guide actually has them with shorter return types: __int8 _mm256_extract_epi8 (__m256i a, const int index) __int16 _mm256_extract_epi16 (__m256i a, const int index) Repository: rL LLVM http://reviews.llvm.org/D20468 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
mkuper added a comment. You're right, the underlying instructions zext, and it seems like it's the right thing to do. I'm just wondering if this is something user code is supposed to rely on, given the way the intrinsics guide documents them right now. H.J, could you please take a look? Repository: rL LLVM http://reviews.llvm.org/D20468 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20468: [X86][AVX] Ensure zero-extension of _mm256_extract_epi8 and _mm256_extract_epi16
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. Thanks, Dave! In that case, LGTM. Repository: rL LLVM http://reviews.llvm.org/D20468 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D19458: Add address space 258 to Clang documentation
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM with a small nit - can you change the heading from "Memory references off the GS segment" to something more general? http://reviews.llvm.org/D19458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D19458: Add address space 258 to Clang documentation
mkuper added a comment. LGTM http://reviews.llvm.org/D19458 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
mkuper added a comment. Thanks, Simon! This looks right, but we may lose some end-to-end tests, since right now we have a clang-level test that checks the builtin is lowered to the intrinsic, and (hopefully) a CG-level test that the intrinsic is lowered to the correct instruction. Do you know if there are already CG tests that check we correctly lower these IR patterns to CVTPS2PD, etc? If not, could you add them? Comment at: lib/Headers/emmintrin.h:390 @@ -390,1 +389,3 @@ + return (__m128d) __builtin_convertvector( + __builtin_shufflevector((__v4sf __a, (__v4sf)__a, 0, 1), __v2df); } It looks like there's a missing paren after the first __v4sf. How does the test compile? Or am I misreading? Repository: rL LLVM http://reviews.llvm.org/D20528 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
mkuper added a comment. In http://reviews.llvm.org/D20528#437090, @RKSimon wrote: > In http://reviews.llvm.org/D20528#436893, @mkuper wrote: > > > This looks right, but we may lose some end-to-end tests, since right now we > > have a clang-level test that checks the builtin is lowered to the > > intrinsic, and (hopefully) a CG-level test that the intrinsic is lowered to > > the correct instruction. > > Do you know if there are already CG tests that check we correctly lower > > these IR patterns to CVTPS2PD, etc? If not, could you add them? > > > I do have the relevant changes for > llvm\test\CodeGen\X86\sse2-intrinsics-fast-isel.ll and > llvm\test\CodeGen\X86\avx-intrinsics-fast-isel.ll (I spent most of last week > adding them all.). Do you want me to setup a separate llvm patch for > review? I'm not ready to do the rest of the llvm work (removal of the llvm > intrinsics / auto-upgrade etc.). but the fast-isel changes are very simple. Sorry, I didn't intend to imply the rest of the llvm work is necessary for this to go in. Just that I'd be happier with this patch knowing that we have a regression test for doing the (shuffle + fpext, say) lowering correctly. I didn't even mean fast-isel, only the DAG. Repository: rL LLVM http://reviews.llvm.org/D20528 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
mkuper added a comment. Presumably, the fast-isel lowering of the IR pattern is already correct, and in any case, it isn't affected by this patch. I just want to make sure we don't regress the optimized DAG codegen - that is, it still produces the instruction we'd expect from the intrinsic (or something at least as good). Repository: rL LLVM http://reviews.llvm.org/D20528 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20528: [X86][SSE] Replace lossless i32/f32 to f64 conversion intrinsics with generic IR
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. > The existing llvm\test\CodeGen\X86\vec_fpext.ll and > llvm\test\CodeGen\X86\vec_int_to_fp.ll already demonstrate the correct > optimized DAG codegen using the same IR as output in the > clang\test\CodeGen\*-builtins.c here. That's what I meant by "Do you know if there are already CG tests that check we correctly lower these IR patterns", sorry I wasn't more clear. This LGTM. Repository: rL LLVM http://reviews.llvm.org/D20528 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21173: [X86] _MM_ALIGN16 attribute support for non-windows targets
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM Repository: rL LLVM http://reviews.llvm.org/D21173 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r274805 - [CUDA] Pass correct option in test.
Author: mkuper Date: Thu Jul 7 18:22:39 2016 New Revision: 274805 URL: http://llvm.org/viewvc/llvm-project?rev=274805&view=rev Log: [CUDA] Pass correct option in test. Modified: cfe/trunk/test/Driver/cuda-version-check.cu Modified: cfe/trunk/test/Driver/cuda-version-check.cu URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/cuda-version-check.cu?rev=274805&r1=274804&r2=274805&view=diff == --- cfe/trunk/test/Driver/cuda-version-check.cu (original) +++ cfe/trunk/test/Driver/cuda-version-check.cu Thu Jul 7 18:22:39 2016 @@ -36,7 +36,7 @@ // -nocuda-version-check should suppress all of these errors. // RUN: %clang -v -### --cuda-gpu-arch=sm_60 --sysroot=%S/Inputs/CUDA 2>&1 \ -// RUN:-nocuda-version-check %s | \ +// RUN:--no-cuda-version-check %s | \ // RUN:FileCheck %s --check-prefix=OK // OK-NOT: error: GPU arch ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r256495 - [X86] Better support for the MCU psABI (clang part)
Author: mkuper
Date: Mon Dec 28 08:39:54 2015
New Revision: 256495
URL: http://llvm.org/viewvc/llvm-project?rev=256495&view=rev
Log:
[X86] Better support for the MCU psABI (clang part)
This adds support for the MCU psABI in a way different from r251223 and r251224,
basically reverting most of these two patches. The problem with the approach
taken in r251223/4 is that it only handled libcalls that originated from the
backend.
However, the mid-end also inserts quite a few libcalls and assumes these use the
platform's default calling convention.
The previous patch tried to insert inregs when necessary both in the FE and,
somewhat hackily, in the CG. Instead, we now define a new default calling
convention
for the MCU, which doesn't use inreg marking at all, similarly to what x86-64
does.
Differential Revision: http://reviews.llvm.org/D15055
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=256495&r1=256494&r2=256495&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Dec 28 08:39:54 2015
@@ -841,7 +841,13 @@ class X86_32ABIInfo : public ABIInfo {
Class classify(QualType Ty) const;
ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
- bool shouldUseInReg(QualType Ty, CCState &State, bool &NeedsPadding) const;
+ /// \brief Updates the number of available free registers, returns
+ /// true if any registers were allocated.
+ bool updateFreeRegs(QualType Ty, CCState &State) const;
+
+ bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
+bool &NeedsPadding) const;
+ bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
/// \brief Rewrite the function info so that all memory arguments use
/// inalloca.
@@ -1003,9 +1009,10 @@ bool X86_32ABIInfo::shouldReturnTypeInRe
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
- // Type must be register sized.
- if (!isRegisterSize(Size))
-return false;
+ // For i386, type must be register sized.
+ // For the MCU ABI, it only needs to be <= 8-byte
+ if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
+ return false;
if (Ty->isVectorType()) {
// 64- and 128- bit vectors inside structures are not returned in
@@ -1052,7 +1059,8 @@ ABIArgInfo X86_32ABIInfo::getIndirectRet
// integer register.
if (State.FreeRegs) {
--State.FreeRegs;
-return getNaturalAlignIndirectInReg(RetTy);
+if (!IsMCUABI)
+ return getNaturalAlignIndirectInReg(RetTy);
}
return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
}
@@ -1192,7 +1200,8 @@ ABIArgInfo X86_32ABIInfo::getIndirectRes
if (!ByVal) {
if (State.FreeRegs) {
--State.FreeRegs; // Non-byval indirects just use one pointer.
- return getNaturalAlignIndirectInReg(Ty);
+ if (!IsMCUABI)
+return getNaturalAlignIndirectInReg(Ty);
}
return getNaturalAlignIndirect(Ty, false);
}
@@ -1223,9 +1232,7 @@ X86_32ABIInfo::Class X86_32ABIInfo::clas
return Integer;
}
-bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
- bool &NeedsPadding) const {
- NeedsPadding = false;
+bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
if (!IsSoftFloatABI) {
Class C = classify(Ty);
if (C == Float)
@@ -1253,25 +1260,46 @@ bool X86_32ABIInfo::shouldUseInReg(QualT
}
State.FreeRegs -= SizeInRegs;
+ return true;
+}
+
+bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
+ bool &InReg,
+ bool &NeedsPadding) const {
+ NeedsPadding = false;
+ InReg = !IsMCUABI;
+
+ if (!updateFreeRegs(Ty, State))
+return false;
+
+ if (IsMCUABI)
+return true;
if (State.CC == llvm::CallingConv::X86_FastCall ||
State.CC == llvm::CallingConv::X86_VectorCall) {
-if (Size > 32)
- return false;
-
-if (Ty->isIntegralOrEnumerationType())
- return true;
+if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
+ NeedsPadding = true;
-if (Ty->isPointerType())
- return true;
+return false;
+ }
-if (Ty->isReferenceType())
- return true;
+ return true;
+}
-if (State.FreeRegs)
- NeedsPadding = true;
+bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const
{
+ if (!updateFreeRegs(Ty, State))
+return false;
+ if (IsMCUABI)
return false;
+
+ if (State.CC == llvm::CallingConv::X86_FastCall ||
+ State.CC == llvm::Call
Re: [PATCH] D15055: [X86] Better support for the MCU psABI
This revision was automatically updated to reflect the committed changes.
Closed by commit rL256495: [X86] Better support for the MCU psABI (clang part)
(authored by mkuper).
Changed prior to commit:
http://reviews.llvm.org/D15055?vs=41348&id=43685#toc
Repository:
rL LLVM
http://reviews.llvm.org/D15055
Files:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
Index: cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
===
--- cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
+++ cfe/trunk/test/CodeGen/x86_32-arguments-iamcu.c
@@ -1,20 +1,24 @@
// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s
-// CHECK-LABEL: define void @ints(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 %d)
+// CHECK-LABEL: define void @ints(i32 %a, i32 %b, i32 %c, i32 %d)
void ints(int a, int b, int c, int d) {}
-// CHECK-LABEL: define void @floats(float inreg %a, float inreg %b, float inreg %c, float %d)
+// CHECK-LABEL: define void @floats(float %a, float %b, float %c, float %d)
void floats(float a, float b, float c, float d) {}
-// CHECK-LABEL: define void @mixed(i32 inreg %a, float inreg %b, i32 inreg %c, float %d)
+// CHECK-LABEL: define void @mixed(i32 %a, float %b, i32 %c, float %d)
void mixed(int a, float b, int c, float d) {}
-// CHECK-LABEL: define void @doubles(double inreg %d1, double %d2)
+// CHECK-LABEL: define void @doubles(double %d1, double %d2)
void doubles(double d1, double d2) {}
-// CHECK-LABEL: define void @mixedDoubles(i32 inreg %a, double inreg %d1)
+// CHECK-LABEL: define void @mixedDoubles(i32 %a, double %d1)
void mixedDoubles(int a, double d1) {}
+typedef struct st3_t {
+ char a[3];
+} st3_t;
+
typedef struct st4_t {
int a;
} st4_t;
@@ -30,33 +34,36 @@
int c;
} st12_t;
-// CHECK-LABEL: define void @smallStructs(i32 inreg %st1.coerce, i32 inreg %st2.coerce, i32 inreg %st3.coerce)
+// CHECK-LABEL: define void @smallStructs(i32 %st1.coerce, i32 %st2.coerce, i32 %st3.coerce)
void smallStructs(st4_t st1, st4_t st2, st4_t st3) {}
-// CHECK-LABEL: define void @paddedStruct(i32 inreg %i1, i32 inreg %st.coerce0, i32 inreg %st.coerce1, i32 %st4.0)
+// CHECK-LABEL: define void @paddedStruct(i32 %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0)
void paddedStruct(int i1, st5_t st, st4_t st4) {}
-// CHECK-LABEL: define void @largeStruct(i32 %st.0, i32 %st.1, i32 %st.2)
-void largeStruct(st12_t st) {}
+// CHECK-LABEL: define void @largeStructBegin(%struct.st12_t* byval align 4 %st)
+void largeStructBegin(st12_t st) {}
-// CHECK-LABEL: define void @largeStructMiddle(i32 inreg %i1, i32 %st.0, i32 %st.1, i32 %st.2, i32 inreg %i2, i32 inreg %i3)
+// CHECK-LABEL: define void @largeStructMiddle(i32 %i1, %struct.st12_t* byval align 4 %st, i32 %i2, i32 %i3)
void largeStructMiddle(int i1, st12_t st, int i2, int i3) {}
-// CHECK-LABEL: define i32 @retSmallStruct(i32 inreg %r.coerce)
+// CHECK-LABEL: define void @largeStructEnd(i32 %i1, i32 %i2, i32 %i3, i32 %st.0, i32 %st.1, i32 %st.2)
+void largeStructEnd(int i1, int i2, int i3, st12_t st) {}
+
+// CHECK-LABEL: define i24 @retNonPow2Struct(i32 %r.coerce)
+st3_t retNonPow2Struct(st3_t r) { return r; }
+
+// CHECK-LABEL: define i32 @retSmallStruct(i32 %r.coerce)
st4_t retSmallStruct(st4_t r) { return r; }
-// CHECK-LABEL: define i64 @retPaddedStruct(i32 inreg %r.coerce0, i32 inreg %r.coerce1)
+// CHECK-LABEL: define i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1)
st5_t retPaddedStruct(st5_t r) { return r; }
-// CHECK-LABEL: define void @retLargeStruct(%struct.st12_t* inreg noalias sret %agg.result, i32 inreg %i1, i32 %r.0, i32 %r.1, i32 %r.2)
+// CHECK-LABEL: define void @retLargeStruct(%struct.st12_t* noalias sret %agg.result, i32 %i1, %struct.st12_t* byval align 4 %r)
st12_t retLargeStruct(int i1, st12_t r) { return r; }
-// FIXME: We really shouldn't be marking this inreg. Right now the
-// inreg gets ignored by the CG for varargs functions, but that's
-// insane.
-// CHECK-LABEL: define i32 @varArgs(i32 inreg %i1, ...)
+// CHECK-LABEL: define i32 @varArgs(i32 %i1, ...)
int varArgs(int i1, ...) { return i1; }
-// CHECK-LABEL: define double @longDoubleArg(double inreg %ld1)
+// CHECK-LABEL: define double @longDoubleArg(double %ld1)
long double longDoubleArg(long double ld1) { return ld1; }
Index: cfe/trunk/lib/CodeGen/TargetInfo.cpp
===
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp
@@ -841,7 +841,13 @@
Class classify(QualType Ty) const;
ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
- bool shouldUseInReg(QualType Ty, CCState &State, bool &NeedsPadding) const;
+ /// \brief Updates the number of available free registers, returns
+ /// true if any registers were allocated.
Re: [PATCH] D14954: [x86] Exclusion of incorrect include headers paths for MCU target
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. LGTM http://reviews.llvm.org/D14954 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D15055: [X86] Better support for the MCU psABI
mkuper created this revision.
mkuper added reviewers: rnk, rafael, DavidKreitzer.
mkuper added a subscriber: cfe-commits.
This adds support for the MCU psABI in a way different from r251223 and
r251224, basically reverting most of these two patches.
The problem with the approach taken in r251223 is that it only handled libcalls
that originated from the backend. However, the midend also inserts quite a few
libcalls and - with good reason - assumes these use the platform's default
calling convention.
The previous patch tried to insert inregs when necessary both in the FE and,
somewhat hackily, in the CG. This patch (and its clang companion patch) goes in
a different direction. It defines a new default calling convention for the MCU,
which doesn't use inreg marking at all, similarly to what, say, x86-64 does.
The LLVM part of this patch is D15054.
http://reviews.llvm.org/D15055
Files:
lib/CodeGen/TargetInfo.cpp
test/CodeGen/x86_32-arguments-iamcu.c
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -831,7 +831,12 @@
Class classify(QualType Ty) const;
ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const;
ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const;
- bool shouldUseInReg(QualType Ty, CCState &State, bool &NeedsPadding) const;
+ /// \brief Updates the number of available free registers, returns
+ /// true if any registers were allocated.
+ bool updateFreeRegs(QualType Ty, CCState &State) const;
+ bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg,
+bool &NeedsPadding) const;
+ bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const;
/// \brief Rewrite the function info so that all memory arguments use
/// inalloca.
@@ -993,9 +998,10 @@
ASTContext &Context) const {
uint64_t Size = Context.getTypeSize(Ty);
- // Type must be register sized.
- if (!isRegisterSize(Size))
-return false;
+ // For i386, type must be register sized.
+ // For the MCU ABI, it only needs to be <= 8-byte
+ if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size)))
+ return false;
if (Ty->isVectorType()) {
// 64- and 128- bit vectors inside structures are not returned in
@@ -1042,7 +1048,8 @@
// integer register.
if (State.FreeRegs) {
--State.FreeRegs;
-return getNaturalAlignIndirectInReg(RetTy);
+if (!IsMCUABI)
+ return getNaturalAlignIndirectInReg(RetTy);
}
return getNaturalAlignIndirect(RetTy, /*ByVal=*/false);
}
@@ -1182,7 +1189,8 @@
if (!ByVal) {
if (State.FreeRegs) {
--State.FreeRegs; // Non-byval indirects just use one pointer.
- return getNaturalAlignIndirectInReg(Ty);
+ if (!IsMCUABI)
+return getNaturalAlignIndirectInReg(Ty);
}
return getNaturalAlignIndirect(Ty, false);
}
@@ -1213,9 +1221,7 @@
return Integer;
}
-bool X86_32ABIInfo::shouldUseInReg(QualType Ty, CCState &State,
- bool &NeedsPadding) const {
- NeedsPadding = false;
+bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const {
if (!IsSoftFloatABI) {
Class C = classify(Ty);
if (C == Float)
@@ -1243,25 +1249,45 @@
}
State.FreeRegs -= SizeInRegs;
+ return true;
+}
+
+bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State,
+ bool &InReg, bool &NeedsPadding) const {
+ NeedsPadding = false;
+ InReg = !IsMCUABI;
+
+ if (!updateFreeRegs(Ty, State))
+return false;
+
+ if (IsMCUABI)
+return true;
if (State.CC == llvm::CallingConv::X86_FastCall ||
State.CC == llvm::CallingConv::X86_VectorCall) {
-if (Size > 32)
- return false;
-
-if (Ty->isIntegralOrEnumerationType())
- return true;
+if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs)
+ NeedsPadding = true;
-if (Ty->isPointerType())
- return true;
+return false;
+ }
-if (Ty->isReferenceType())
- return true;
+ return true;
+}
-if (State.FreeRegs)
- NeedsPadding = true;
+bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const {
+ if (!updateFreeRegs(Ty, State))
+return false;
+ if (IsMCUABI)
return false;
+
+ if (State.CC == llvm::CallingConv::X86_FastCall ||
+ State.CC == llvm::CallingConv::X86_VectorCall) {
+if (getContext().getTypeSize(Ty) > 32)
+ return false;
+
+return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
+Ty->isReferenceType());
}
return true;
@@ -1317,21 +1343,27 @@
llvm::LLVMContext &LLVMContext = getVMContext();
llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext);
-bool NeedsPadding;
-if (shouldUseInReg(Ty, State, NeedsPadding)) {
+bool NeedsPadding, InReg;
+if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) {
Re: [PATCH] D15127: Move _mm256_cvtps_ph and _mm256_cvtph_ps to immintrin.h.
mkuper accepted this revision. mkuper added a comment. This revision is now accepted and ready to land. Thanks Paul, LGTM. http://reviews.llvm.org/D15127 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r256121 - [X86] Add signed aliases for popcnt intrinsics
Author: mkuper
Date: Sun Dec 20 06:35:35 2015
New Revision: 256121
URL: http://llvm.org/viewvc/llvm-project?rev=256121&view=rev
Log:
[X86] Add signed aliases for popcnt intrinsics
The Intel manual documents both an unsigned form (_mm_popcnt_u32)
and a signed form (_popcnt32) of the intrinsic. Add the missing signed form.
Differential Revision: http://reviews.llvm.org/D15568
Modified:
cfe/trunk/lib/Headers/popcntintrin.h
cfe/trunk/test/CodeGen/popcnt-builtins.c
Modified: cfe/trunk/lib/Headers/popcntintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/popcntintrin.h?rev=256121&r1=256120&r2=256121&view=diff
==
--- cfe/trunk/lib/Headers/popcntintrin.h (original)
+++ cfe/trunk/lib/Headers/popcntintrin.h Sun Dec 20 06:35:35 2015
@@ -33,12 +33,24 @@ _mm_popcnt_u32(unsigned int __A)
return __builtin_popcount(__A);
}
+static __inline__ int __DEFAULT_FN_ATTRS
+_popcnt32(int __A)
+{
+ return __builtin_popcount(__A);
+}
+
#ifdef __x86_64__
static __inline__ long long __DEFAULT_FN_ATTRS
_mm_popcnt_u64(unsigned long long __A)
{
return __builtin_popcountll(__A);
}
+
+static __inline__ long long __DEFAULT_FN_ATTRS
+_popcnt64(long long __A)
+{
+ return __builtin_popcountll(__A);
+}
#endif /* __x86_64__ */
#undef __DEFAULT_FN_ATTRS
Modified: cfe/trunk/test/CodeGen/popcnt-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/popcnt-builtins.c?rev=256121&r1=256120&r2=256121&view=diff
==
--- cfe/trunk/test/CodeGen/popcnt-builtins.c (original)
+++ cfe/trunk/test/CodeGen/popcnt-builtins.c Sun Dec 20 06:35:35 2015
@@ -6,11 +6,21 @@
#include
unsigned int test_mm_popcnt_u32(unsigned int __X) {
- // CHECK: @llvm.ctpop.i32
+ //CHECK: call i32 @llvm.ctpop.i32
return _mm_popcnt_u32(__X);
}
+unsigned int test_popcnt_32(int __X) {
+ //CHECK: call i32 @llvm.ctpop.i32
+ return _popcnt32(__X);
+}
+
unsigned long long test_mm_popcnt_u64(unsigned long long __X) {
- // CHECK: @llvm.ctpop.i64
+ //CHECK: call i64 @llvm.ctpop.i64
return _mm_popcnt_u64(__X);
}
+
+unsigned long long test_popcnt_64(long long __X) {
+ //CHECK: call i64 @llvm.ctpop.i64
+ return _popcnt64(__X);
+}
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r256122 - [X86] Add missing m64/int64 conversions
Author: mkuper
Date: Sun Dec 20 06:37:18 2015
New Revision: 256122
URL: http://llvm.org/viewvc/llvm-project?rev=256122&view=rev
Log:
[X86] Add missing m64/int64 conversions
Define the 64-bit equivalents of _m_to_int and _m_from_int.
Differential Revision: http://reviews.llvm.org/D15572
Modified:
cfe/trunk/lib/Headers/mmintrin.h
cfe/trunk/test/CodeGen/mmx-builtins.c
Modified: cfe/trunk/lib/Headers/mmintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/mmintrin.h?rev=256122&r1=256121&r2=256122&view=diff
==
--- cfe/trunk/lib/Headers/mmintrin.h (original)
+++ cfe/trunk/lib/Headers/mmintrin.h Sun Dec 20 06:37:18 2015
@@ -443,7 +443,9 @@ _mm_setr_pi8(char __b0, char __b1, char
/* Aliases for compatibility. */
#define _m_empty _mm_empty
#define _m_from_int _mm_cvtsi32_si64
+#define _m_from_int64 _mm_cvtsi64_m64
#define _m_to_int _mm_cvtsi64_si32
+#define _m_to_int64 _mm_cvtm64_si64
#define _m_packsswb _mm_packs_pi16
#define _m_packssdw _mm_packs_pi32
#define _m_packuswb _mm_packs_pu16
Modified: cfe/trunk/test/CodeGen/mmx-builtins.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mmx-builtins.c?rev=256122&r1=256121&r2=256122&view=diff
==
--- cfe/trunk/test/CodeGen/mmx-builtins.c (original)
+++ cfe/trunk/test/CodeGen/mmx-builtins.c Sun Dec 20 06:37:18 2015
@@ -223,6 +223,12 @@ __m64 test_m_from_int(int a) {
return _m_from_int(a);
}
+__m64 test_m_from_int64(long long a) {
+ // CHECK-LABEL: test_m_from_int64
+ // CHECK: bitcast
+ return _m_from_int64(a);
+}
+
__m64 test_mm_hadd_pi16(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_hadd_pi16
// CHECK: call x86_mmx @llvm.x86.ssse3.phadd.w
@@ -553,6 +559,12 @@ int test_m_to_int(__m64 a) {
return _m_to_int(a);
}
+long long test_m_to_int64(__m64 a) {
+ // CHECK-LABEL: test_m_to_int64
+ // CHECK: bitcast
+ return _m_to_int64(a);
+}
+
__m64 test_mm_unpackhi_pi8(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_unpackhi_pi8
// CHECK: call x86_mmx @llvm.x86.mmx.punpckhbw
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