[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added a comment.

ping


https://reviews.llvm.org/D49793



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[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL340018: [AArch64] - Generate pointer authentication 
instructions (authored by LukeCheeseman, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D49793?vs=158491&id=161220#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D49793

Files:
  llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/trunk/test/CodeGen/AArch64/sign-return-address.ll

Index: llvm/trunk/test/CodeGen/AArch64/sign-return-address.ll
===
--- llvm/trunk/test/CodeGen/AArch64/sign-return-address.ll
+++ llvm/trunk/test/CodeGen/AArch64/sign-return-address.ll
@@ -0,0 +1,86 @@
+; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck %s
+
+; CHECK-LABEL: @leaf
+; CHECK-NOT: paci{{[a,b]}}sp
+; CHECK-NOT: auti{{[a,b]}}sp
+define i32 @leaf(i32 %x) {
+  ret i32 %x
+}
+
+; CHECK-LABEL: @leaf_sign_none
+; CHECK-NOT: paci{{[a,b]}}sp
+; CHECK-NOT: auti{{[a,b]}}sp
+define i32 @leaf_sign_none(i32 %x) "sign-return-address"="none"  {
+  ret i32 %x
+}
+
+; CHECK-LABEL: @leaf_sign_non_leaf
+; CHECK-NOT: paci{{[a,b]}}sp
+; CHECK-NOT: auti{{[a,b]}}sp
+define i32 @leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
+  ret i32 %x
+}
+
+; CHECK-LABEL: @leaf_sign_all
+; CHECK: paciasp
+; CHECK: autiasp
+; CHECK-NEXT: ret
+define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
+  ret i32 %x
+}
+
+; CHECK: @leaf_clobbers_lr
+; CHECK: paciasp
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK: ldr  x30, [sp], #16
+; CHECK-NEXT: autiasp
+; CHECK-NEXT: ret
+define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf"  {
+  call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
+  ret i64 %x
+}
+
+declare i32 @foo(i32)
+
+; CHECK: @non_leaf_sign_all
+; CHECK: paciasp
+; CHECK: autiasp
+; CHECK-NEXT: ret
+define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
+  %call = call i32 @foo(i32 %x)
+  ret i32 %call
+}
+
+; CHECK: @non_leaf_sign_non_leaf
+; CHECK: paciasp
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK: ldr  x30, [sp], #16
+; CHECK-NEXT: autiasp
+; CHECK-NEXT: ret
+define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf"  {
+  %call = call i32 @foo(i32 %x)
+  ret i32 %call
+}
+
+; CHECK-LABEL: @leaf_sign_all_v83
+; CHECK: paciasp
+; CHECK-NOT: ret
+; CHECK-NEXT: retaa
+; CHECK-NOT: ret
+define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" {
+  ret i32 %x
+}
+
+declare fastcc i64 @bar(i64)
+
+; CHECK-LABEL: @spill_lr_and_tail_call
+; CHECK: paciasp
+; CHECK-NEXT: str x30, [sp, #-16]!
+; CHECK: ldr  x30, [sp], #16
+; CHECK-NEXT: autiasp
+; CHECK-NEXT: b  bar
+define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
+  call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
+  tail call fastcc i64 @bar(i64 %x)
+  ret void
+}
Index: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
===
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -98,6 +98,7 @@
 #include "AArch64Subtarget.h"
 #include "AArch64TargetMachine.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
+#include "llvm/ADT/ScopeExit.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
@@ -279,6 +280,31 @@
   return MBB.erase(I);
 }
 
+static bool ShouldSignReturnAddress(MachineFunction &MF) {
+  // The function should be signed in the following situations:
+  // - sign-return-address=all
+  // - sign-return-address=non-leaf and the functions spills the LR
+
+  const Function &F = MF.getFunction();
+  if (!F.hasFnAttribute("sign-return-address"))
+return false;
+
+  StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
+  if (Scope.equals("none"))
+return false;
+
+  if (Scope.equals("all"))
+return true;
+
+  assert(Scope.equals("non-leaf") && "Expected all, none or non-leaf");
+
+  for (const auto &Info : MF.getFrameInfo().getCalleeSavedInfo())
+if (Info.getReg() == AArch64::LR)
+  return true;
+
+  return false;
+}
+
 void AArch64FrameLowering::emitCalleeSavedFrameMoves(
 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
   MachineFunction &MF = *MBB.getParent();
@@ -568,6 +594,11 @@
   // to determine the end of the prologue.
   DebugLoc DL;
 
+  if (ShouldSignReturnAddress(MF)) {
+BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
+.setMIFlag(MachineInstr::FrameSetup);
+  }
+
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
@@ -832,6 +863,32 @@
   }
 }
 
+static void InsertReturnAddressAuth(MachineFunction &MF,
+MachineBasicBlock &MBB) {
+  if

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman created this revision.
LukeCheeseman added reviewers: kcc, pcc, eugenis, vlad.tsyrklevich.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, kristof.beyls.

- Add command line options for selecting the B key when enabling return address 
signing (also tidy up the msign_return_address tablegen definiton by suffixing 
the option with EQ)
- This expands the -msign-return-address= to now be 
-msign-return-address=[+] where  is one of a_key or b_key
- Generate the "sign-return-address-key" function attribute with the relevant 
key


Repository:
  rC Clang

https://reviews.llvm.org/D51429

Files:
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c

Index: test/CodeGen/aarch64-sign-return-address.c
===
--- test/CodeGen/aarch64-sign-return-address.c
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -1,6 +1,8 @@
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+a_key %s | FileCheck %s --check-prefix=CHECK-A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+b_key %s | FileCheck %s --check-prefix=CHECK-B-KEY
 
 // CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
 // CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
@@ -11,4 +13,10 @@
 // CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
 // CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
 
+// CHECK-A-KEY: @foo() #[[ATTR:[0-9]*]]
+// CHECK-A-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+
+// CHECK-B-KEY: @foo() #[[ATTR:[0-9]*]]
+// CHECK-B-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="b_key" {{.*}} }
+
 void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1131,8 +1131,11 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
-  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
-StringRef SignScope = A->getValue();
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+const auto SignScopeKey = StringRef(A->getValue()).split('+');
+StringRef SignScope = SignScopeKey.first;
+StringRef SignKey = SignScopeKey.second;
+
 if (SignScope.equals_lower("none"))
   Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::None);
 else if (SignScope.equals_lower("all"))
@@ -1142,7 +1145,17 @@
   CodeGenOptions::SignReturnAddressScope::NonLeaf);
 else
   Diags.Report(diag::err_drv_invalid_value)
-  << A->getAsString(Args) << A->getValue();
+  << A->getAsString(Args) << SignScope;
+
+if (!SignScope.empty() && !SignKey.empty()) {
+  if (SignKey.equals_lower("a_key"))
+Opts.setSignReturnAddressKey(CodeGenOptions::SignReturnAddressKeyValue::AKey);
+  else if (SignKey.equals_lower("b_key"))
+Opts.setSignReturnAddressKey(CodeGenOptions::SignReturnAddressKeyValue::BKey);
+  else
+Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args)
+  << SignKey;
+}
   }
 
   Opts.KeepStaticConsts = Args.hasArg(OPT_fkeep_static_consts);
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -1456,7 +1456,7 @@
   CmdArgs.push_back("-aarch64-enable-global-merge=true");
   }
 
-  if (Arg *A = Args.getLastArg(options::OPT_msign_return_address)) {
+  if (Arg *A = Args.getLastArg(options::OPT_msign_return_address_EQ)) {
 CmdArgs.push_back(
 Args.MakeArgString(Twine("-msign-return-address=") + A->getValue()));
   }
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4985,6 +4985,12 @@
   Kind == CodeGenOptions::SignReturnAddressScope::All
   ? "all"
   : "non-leaf");
+
+auto Key = CGM.getCodeGenOpts().getSignReturnAddressKey();
+Fn->addFnAttr("sign-return-address-key",
+  Key == CodeGenOptions::Si

[PATCH] D51432: [AArch64] Unwinding support for return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman created this revision.
LukeCheeseman added reviewers: pcc, kcc, eugenis, vlad.tsyrklevich.
Herald added a reviewer: javed.absar.
Herald added subscribers: cfe-commits, chrib, JDevlieghere, kristof.beyls.

- When return address signing is enabled, the LR may be signed on function entry
- When an exception is thrown the return address is inspected used to unwind 
the call stack
- Before this happens, the return address must be correctly authenticated to 
avoid causing an abort by dereferencing the signed pointer


Repository:
  rUNW libunwind

https://reviews.llvm.org/D51432

Files:
  include/libunwind.h
  src/DwarfInstructions.hpp
  src/DwarfParser.hpp
  src/Registers.hpp
  src/dwarf2.h

Index: src/dwarf2.h
===
--- src/dwarf2.h
+++ src/dwarf2.h
@@ -49,7 +49,10 @@
   // GNU extensions
   DW_CFA_GNU_window_save  = 0x2D,
   DW_CFA_GNU_args_size= 0x2E,
-  DW_CFA_GNU_negative_offset_extended = 0x2F
+  DW_CFA_GNU_negative_offset_extended = 0x2F,
+
+  // AARCH64 extensions
+  DW_CFA_AARCH64_negate_ra_state  = 0x2D
 };
 
 
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -1819,6 +1819,8 @@
 return false;
   if (regNum > 95)
 return false;
+  if (regNum == UNW_ARM64_RA_SIGN_STATE)
+return true;
   if ((regNum > 31) && (regNum < 64))
 return false;
   return true;
@@ -1829,17 +1831,18 @@
 return _registers.__pc;
   if (regNum == UNW_REG_SP)
 return _registers.__sp;
-  if ((regNum >= 0) && (regNum < 32))
+  if (((regNum >= 0) && (regNum < 32)) || regNum == UNW_ARM64_RA_SIGN_STATE)
 return _registers.__x[regNum];
+
   _LIBUNWIND_ABORT("unsupported arm64 register");
 }
 
 inline void Registers_arm64::setRegister(int regNum, uint64_t value) {
   if (regNum == UNW_REG_IP)
 _registers.__pc = value;
   else if (regNum == UNW_REG_SP)
 _registers.__sp = value;
-  else if ((regNum >= 0) && (regNum < 32))
+  else if ((regNum >= 0) && (regNum < 32) || regNum == UNW_ARM64_RA_SIGN_STATE)
 _registers.__x[regNum] = value;
   else
 _LIBUNWIND_ABORT("unsupported arm64 register");
Index: src/DwarfParser.hpp
===
--- src/DwarfParser.hpp
+++ src/DwarfParser.hpp
@@ -666,6 +666,14 @@
   _LIBUNWIND_TRACE_DWARF(
   "DW_CFA_GNU_negative_offset_extended(%" PRId64 ")\n", offset);
   break;
+
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+case DW_CFA_AARCH64_negate_ra_state:
+  results->savedRegisters[UNW_ARM64_RA_SIGN_STATE].value ^= 0x1;
+  _LIBUNWIND_TRACE_DWARF("DW_CFA_AARCH64_negate_ra_state\n");
+  break;
+#endif
+
 default:
   operand = opcode & 0x3F;
   switch (opcode & 0xC0) {
Index: src/DwarfInstructions.hpp
===
--- src/DwarfInstructions.hpp
+++ src/DwarfInstructions.hpp
@@ -198,6 +198,20 @@
   // restoring SP means setting it to CFA.
   newRegisters.setSP(cfa);
 
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+  // If the target is aarch64 then the return address may have been signed
+  // using the v8.3 pointer authentication extensions. The original
+  // return address needs to be authenticated before the return address is
+  // restored. autia1716 is used instead of autia as autia1716 assembles
+  // to a NOP on pre-v8.3a architectures.
+  if (prolog.savedRegisters[UNW_ARM64_RA_SIGN_STATE].value) {
+register unsigned long long x17 __asm("x17") = returnAddress;
+register unsigned long long x16 __asm("x16") = cfa;
+asm("autia1716": "+r"(x17): "r"(x16));
+returnAddress = x17;
+  }
+#endif
+
   // Return address is address after call site instruction, so setting IP to
   // that does simualates a return.
   newRegisters.setIP(returnAddress);
Index: include/libunwind.h
===
--- include/libunwind.h
+++ include/libunwind.h
@@ -547,6 +547,8 @@
   UNW_ARM64_X31 = 31,
   UNW_ARM64_SP  = 31,
   // reserved block
+  UNW_ARM64_RA_SIGN_STATE = 34,
+  // reserved block
   UNW_ARM64_D0  = 64,
   UNW_ARM64_D1  = 65,
   UNW_ARM64_D2  = 66,
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[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 165467.
LukeCheeseman added a comment.

- updated tests to check the default a_key attribute is included in functions 
that have the return address signing scope attribute
- setting the return-address-sign-key attribute of global static constructors


https://reviews.llvm.org/D51429

Files:
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c
  test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp

Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -4,6 +4,10 @@
 // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | \
 // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+a_key %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+b_key %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-B-KEY
 
 struct Foo {
   Foo() {}
@@ -17,5 +21,7 @@
 // CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
 
 // CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
-// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" {{.*}}}
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+// CHECK-A-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+// CHECK-B-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="b_key" {{.*}} }
Index: test/CodeGen/aarch64-sign-return-address.c
===
--- test/CodeGen/aarch64-sign-return-address.c
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -1,14 +1,22 @@
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+a_key %s | FileCheck %s --check-prefix=CHECK-A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all+b_key %s | FileCheck %s --check-prefix=CHECK-B-KEY
 
 // CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
 // CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
 
 // CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" {{.*}}}
 
 // CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
-// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+
+// CHECK-A-KEY: @foo() #[[ATTR:[0-9]*]]
+// CHECK-A-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+
+// CHECK-B-KEY: @foo() #[[ATTR:[0-9]*]]
+// CHECK-B-KEY: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="b_key" {{.*}} }
 
 void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1129,8 +1129,11 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
-  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
-StringRef SignScope = A->getValue();
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+const auto SignScopeKey = StringRef(A->getValue()).split('+');
+StringRef SignScope = SignScopeKey.first;
+StringRef SignKey = SignScopeKey.second;
+
 if (SignScope.equals_lower("none"))
   Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressSc

[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 157266.
LukeCheeseman edited the summary of this revision.

https://reviews.llvm.org/D49793

Files:
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c

Index: test/CodeGen/aarch64-sign-return-address.c
===
--- /dev/null
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -0,0 +1,14 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+
+// CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} "sign-return-address-key"={{.*}}}
+
+// CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="partial" "sign-return-address-key"="a_key" {{.*}}}
+
+// CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" "sign-return-address-key"="a_key" {{.*}} }
+
+void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1125,6 +1125,19 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
+StringRef SignScope = A->getValue();
+if (SignScope.equals_lower("none"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::None);
+else if (SignScope.equals_lower("all"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::All);
+else if (SignScope.equals_lower("non-leaf"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::Partial);
+else
+  Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args)
+<< A->getValue();
+  }
+
   return Success;
 }
 
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4073,6 +4073,11 @@
 options::OPT_mno_stack_arg_probe, true))
 CmdArgs.push_back(Args.MakeArgString("-mno-stack-arg-probe"));
 
+  if (Arg *A = Args.getLastArg(options::OPT_msign_return_address)) {
+CmdArgs.push_back(
+Args.MakeArgString(Twine("-msign-return-address=") + A->getValue()));
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {
 if (A->getOption().matches(options::OPT_mrestrict_it)) {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4969,6 +4969,23 @@
   }
 
   bool doesReturnSlotInterfereWithArgs() const override { return false; }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD)
+  return;
+llvm::Function *Fn = cast(GV);
+
+auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
+if (Kind == CodeGenOptions::SignReturnAddressScope::None)
+  return;
+
+Fn->addFnAttr("sign-return-address",
+  Kind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "partial");
+  }
 };
 
 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
Index: include/clang/Frontend/CodeGenOptions.h
===
--- include/clang/Frontend/CodeGenOptions.h
+++ include/clang/Frontend/CodeGenOptions.h
@@ -108,6 +108,12 @@
 Embed_Marker// Embed a marker as a placeholder for bitcode.
   };
 
+  enum SignReturnAddressScope {
+None,   // No signing for any function
+Partial,// Sign the return address of functions that spill LR
+All // Sign the return address of all functions
+  };
+
   /// The code model to use (-mcmodel).
   std::string CodeModel;
 
Index: include/clang/Frontend/CodeGenOptions.def
===
--- include/clang/Frontend/CodeGenOptions.def
+++ include/clang/Frontend/CodeGenOptions.def
@@ -339,6 +339,7 @@
 /// Whether to emit an address-significance table into the object file.
 CODEGE

[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 157444.
LukeCheeseman added a comment.

Change codegen option partial to non-leaf to match msign-return-address scope 
values


https://reviews.llvm.org/D49793

Files:
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c

Index: test/CodeGen/aarch64-sign-return-address.c
===
--- /dev/null
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -0,0 +1,14 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+
+// CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
+
+// CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+
+// CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+
+void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1125,6 +1125,19 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
+StringRef SignScope = A->getValue();
+if (SignScope.equals_lower("none"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::None);
+else if (SignScope.equals_lower("all"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::All);
+else if (SignScope.equals_lower("non-leaf"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::NonLeaf);
+else
+  Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args)
+<< A->getValue();
+  }
+
   return Success;
 }
 
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -4073,6 +4073,11 @@
 options::OPT_mno_stack_arg_probe, true))
 CmdArgs.push_back(Args.MakeArgString("-mno-stack-arg-probe"));
 
+  if (Arg *A = Args.getLastArg(options::OPT_msign_return_address)) {
+CmdArgs.push_back(
+Args.MakeArgString(Twine("-msign-return-address=") + A->getValue()));
+  }
+
   if (Arg *A = Args.getLastArg(options::OPT_mrestrict_it,
options::OPT_mno_restrict_it)) {
 if (A->getOption().matches(options::OPT_mrestrict_it)) {
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4969,6 +4969,23 @@
   }
 
   bool doesReturnSlotInterfereWithArgs() const override { return false; }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD)
+  return;
+llvm::Function *Fn = cast(GV);
+
+auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
+if (Kind == CodeGenOptions::SignReturnAddressScope::None)
+  return;
+
+Fn->addFnAttr("sign-return-address",
+  Kind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "non-leaf");
+  }
 };
 
 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
Index: include/clang/Frontend/CodeGenOptions.h
===
--- include/clang/Frontend/CodeGenOptions.h
+++ include/clang/Frontend/CodeGenOptions.h
@@ -108,6 +108,12 @@
 Embed_Marker// Embed a marker as a placeholder for bitcode.
   };
 
+  enum SignReturnAddressScope {
+None,   // No signing for any function
+NonLeaf,// Sign the return address of functions that spill LR
+All // Sign the return address of all functions
+  };
+
   /// The code model to use (-mcmodel).
   std::string CodeModel;
 
Index: include/clang/Frontend/CodeGenOptions.def
===
--- include/clang/Frontend/CodeGenOptions.def
+++ include/clang/Frontend/CodeGenOptions.def
@@ -339,6 +339,7 @@
 /// Whether to emit an address-significance table into the object file.
 CODEGENOPT(Addrsig, 1, 0)
 
+ENUM_C

[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added inline comments.



Comment at: include/clang/Frontend/CodeGenOptions.h:114
+Partial,// Sign the return address of functions that spill LR
+All // Sign the return address of all functions
+  };

kcc wrote:
> what's the purpose of signing LR if it is not spilled? 
Assuming you are in a context where you have managed to gain control of the 
flow of execution. If you don't sign functions that spill LR then those 
functions become good candidates for finding gadgets as now execution can start 
from any point in that function.


https://reviews.llvm.org/D49793



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[PATCH] D49793: [AArch64] - return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 158491.
LukeCheeseman added a comment.

Move -msign-return-address argument handling into AArch64TargetArgs


https://reviews.llvm.org/D49793

Files:
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c

Index: test/CodeGen/aarch64-sign-return-address.c
===
--- /dev/null
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -0,0 +1,14 @@
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+
+// CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
+// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
+
+// CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+
+// CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
+// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+
+void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1125,6 +1125,20 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
+StringRef SignScope = A->getValue();
+if (SignScope.equals_lower("none"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::None);
+else if (SignScope.equals_lower("all"))
+  Opts.setSignReturnAddress(CodeGenOptions::SignReturnAddressScope::All);
+else if (SignScope.equals_lower("non-leaf"))
+  Opts.setSignReturnAddress(
+  CodeGenOptions::SignReturnAddressScope::NonLeaf);
+else
+  Diags.Report(diag::err_drv_invalid_value)
+  << A->getAsString(Args) << A->getValue();
+  }
+
   return Success;
 }
 
Index: lib/Driver/ToolChains/Clang.cpp
===
--- lib/Driver/ToolChains/Clang.cpp
+++ lib/Driver/ToolChains/Clang.cpp
@@ -1455,6 +1455,11 @@
 else
   CmdArgs.push_back("-aarch64-enable-global-merge=true");
   }
+
+  if (Arg *A = Args.getLastArg(options::OPT_msign_return_address)) {
+CmdArgs.push_back(
+Args.MakeArgString(Twine("-msign-return-address=") + A->getValue()));
+  }
 }
 
 void Clang::AddMIPSTargetArgs(const ArgList &Args,
Index: lib/CodeGen/TargetInfo.cpp
===
--- lib/CodeGen/TargetInfo.cpp
+++ lib/CodeGen/TargetInfo.cpp
@@ -4969,6 +4969,23 @@
   }
 
   bool doesReturnSlotInterfereWithArgs() const override { return false; }
+
+  void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
+   CodeGen::CodeGenModule &CGM) const override {
+const FunctionDecl *FD = dyn_cast_or_null(D);
+if (!FD)
+  return;
+llvm::Function *Fn = cast(GV);
+
+auto Kind = CGM.getCodeGenOpts().getSignReturnAddress();
+if (Kind == CodeGenOptions::SignReturnAddressScope::None)
+  return;
+
+Fn->addFnAttr("sign-return-address",
+  Kind == CodeGenOptions::SignReturnAddressScope::All
+  ? "all"
+  : "non-leaf");
+  }
 };
 
 class WindowsAArch64TargetCodeGenInfo : public AArch64TargetCodeGenInfo {
Index: include/clang/Frontend/CodeGenOptions.h
===
--- include/clang/Frontend/CodeGenOptions.h
+++ include/clang/Frontend/CodeGenOptions.h
@@ -108,6 +108,12 @@
 Embed_Marker// Embed a marker as a placeholder for bitcode.
   };
 
+  enum SignReturnAddressScope {
+None,// No signing for any function
+NonLeaf, // Sign the return address of functions that spill LR
+All  // Sign the return address of all functions
+  };
+
   /// The code model to use (-mcmodel).
   std::string CodeModel;
 
Index: include/clang/Frontend/CodeGenOptions.def
===
--- include/clang/Frontend/CodeGenOptions.def
+++ include/clang/Frontend/CodeGenOptions.def
@@ -339,6 +339,7 @@
 /// Whether to emit an address-significance table into the object file.
 CODEGENOPT(Addrsig, 1, 0)
 
+ENUM_CODEGENOPT(SignReturnAddress, SignReturnAddressScope, 2, None)
 
 #undef CODEGENOPT
 #undef ENUM_CODEGENOPT
Index: include/clang/Driver/Options.td
===
--- include/clang/Driver/Options.t

[PATCH] D44555: clang-interpreter example cmake fix

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman created this revision.
LukeCheeseman added a reviewer: marsupial.
Herald added subscribers: cfe-commits, mgorny.

Add in a space when appending the export to the linker options. Without
the space the export is appeneded onto whatever the last link option
was, which might be a file.


Repository:
  rC Clang

https://reviews.llvm.org/D44555

Files:
  examples/clang-interpreter/CMakeLists.txt


Index: examples/clang-interpreter/CMakeLists.txt
===
--- examples/clang-interpreter/CMakeLists.txt
+++ examples/clang-interpreter/CMakeLists.txt
@@ -34,7 +34,7 @@
   # Is this a CMake bug that even with export_executable_symbols, Windows
   # needs to explictly export the type_info vtable
   set_property(TARGET clang-interpreter
-   APPEND_STRING PROPERTY LINK_FLAGS /EXPORT:??_7type_info@@6B@)
+   APPEND_STRING PROPERTY LINK_FLAGS " /EXPORT:??_7type_info@@6B@")
 endif()
 
 function(clang_enable_exceptions TARGET)


Index: examples/clang-interpreter/CMakeLists.txt
===
--- examples/clang-interpreter/CMakeLists.txt
+++ examples/clang-interpreter/CMakeLists.txt
@@ -34,7 +34,7 @@
   # Is this a CMake bug that even with export_executable_symbols, Windows
   # needs to explictly export the type_info vtable
   set_property(TARGET clang-interpreter
-   APPEND_STRING PROPERTY LINK_FLAGS /EXPORT:??_7type_info@@6B@)
+   APPEND_STRING PROPERTY LINK_FLAGS " /EXPORT:??_7type_info@@6B@")
 endif()
 
 function(clang_enable_exceptions TARGET)
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[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 169430.
LukeCheeseman added a comment.

- Stop parsing msign-return-address as a scope and key pair
- pass bti value through to the CC1 driver and handle it, this adds the 
branch-target-enforce attribute to functions


https://reviews.llvm.org/D51429

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Driver/CC1Options.td
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c
  test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp

Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -1,9 +1,9 @@
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | \
 // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL  --check-prefix=CHECK-A-KEY
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL  --check-prefix=CHECK-A-KEY
 
 struct Foo {
   Foo() {}
@@ -16,6 +16,7 @@
 
 // CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
 
-// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
-// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+// CHECK-NONE-NOT: "sign-return-address"={{.*}}
+// CHECK-PARTIAL: "sign-return-address"="non-leaf"
+// CHECK-ALL: "sign-return-address"="all"
+// CHECK-A-KEY: "sign-return-address-key"="a_key"
Index: test/CodeGen/aarch64-sign-return-address.c
===
--- test/CodeGen/aarch64-sign-return-address.c
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -1,14 +1,27 @@
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK --check-prefix=NONE
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.2-a -S -emit-llvm -o - -msign-return-address=all  %s | FileCheck %s --check-prefix=CHECK --check-prefix=ALL --check-prefix=A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -msign-return-address=all %s   | FileCheck %s --check-prefix=CHECK --check-prefix=ALL --check-prefix=A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK --check-prefix=PARTIAL --check-prefix=A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK --check-prefix=ALL --check-prefix=A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.4-a -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK --check-prefix=ALL --check-prefix=A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -mbranch-protection=pac-ret+b-key %s   | FileCheck %s --check-prefix=CHECK --check-prefix=PARTIAL --check-prefix=B-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -mbranch-protection=pac-ret+b-key+leaf %s   | FileCheck %s --check-prefix=CHECK --check-prefix=ALL --check-prefix=B-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.3-a -S -emit-llvm -o - -mbranch-protection=bti %s | FileCheck %s --check-prefix=CHECK --check-prefix=BTE
 
-// CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
-// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
+// REQUIRES: aarch64-registered-target
 
-// CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+// CHECK: @foo() #[[ATTR:[0-9]*]]
+//
+// NONE-NOT: "sign-return-address"={{.*}}
 
-// CHE

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 170869.

https://reviews.llvm.org/D51429

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Driver/CC1Options.td
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c
  test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
  test/Driver/aarch64-security-options.c

Index: test/Driver/aarch64-security-options.c
===
--- /dev/null
+++ test/Driver/aarch64-security-options.c
@@ -0,0 +1,54 @@
+// Check the -msign-return-address= option, which has a required argument to
+// select scope.
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-OFF  --check-prefix=KEY-A --check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=non-leaf 2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-A --check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=all  2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-ALL  --check-prefix=KEY-A --check-prefix=BTE-OFF
+
+// Check that the -msign-return-address= option can also accept the signing key
+// to use.
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=non-leaf   2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-B --check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=all2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-ALL  --check-prefix=KEY-B --check-prefix=BTE-OFF
+
+// -mbranch-protection with standard
+// RUN: %clang -target aarch64--none-eabi -c %s -### -mbranch-protection=standard2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-A --check-prefix=BTE-ON
+
+// If the -msign-return-address and -mbranch-protection are both used, the
+// right-most one controls return address signing.
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=non-leaf -mbranch-protection=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CONFLICT
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -mbranch-protection=pac-ret -msign-return-address=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CONFLICT
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=foo 2>&1 | \
+// RUN: FileCheck %s --check-prefix=BAD-RA-PROTECTION
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -mbranch-protection=bar 2>&1 | \
+// RUN: FileCheck %s --check-prefix=BAD-BP-PROTECTION
+
+// RA-OFF: "-msign-return-address=none"
+// RA-NON-LEAF: "-msign-return-address=non-leaf"
+// RA-ALL: "-msign-return-address=all"
+
+// KEY-A: "-msign-return-address-key=a_key"
+
+// BTE-OFF-NOT: "-mbranch-target-enforce"
+// BTE-ON: "-mbranch-target-enforce"
+
+// CONFLICT: "-msign-return-address=none"
+
+// BAD-RA-PROTECTION: invalid branch protection option 'foo' in '-msign-return-address={{.*}}'
+// BAD-BP-PROTECTION: invalid branch protection option 'bar' in '-mbranch-protection={{.*}}'
+
+// BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}'
+// BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}'
Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -1,9 +1,26 @@
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | \
 // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL  --check-prefix=CHECK-A-KEY
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL  --check-prefix=CHECK-A-KEY
+
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -mbranch-protection=none %s | \
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -mbranch-protection=standard %s | \
+// RUN: FileChec

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman closed this revision.
LukeCheeseman added a comment.

This was committed under 345273. (Forgot to mention the revision in the commit 
message)


https://reviews.llvm.org/D51429



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[PATCH] D57765: [ARM] Add Cortex-M35P Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 188364.
LukeCheeseman added a comment.

- Test cpus Cortex-M33 and Cortex-M35P seperately


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57765/new/

https://reviews.llvm.org/D57765

Files:
  test/Driver/arm-cortex-cpus.c


Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -822,8 +822,10 @@
 // RUN: %clang -target arm -mcpu=cortex-m23 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MBASE %s
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
-// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
-// CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
+// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M33 %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M35P %s
+// CHECK-CORTEX-M33:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} 
"-target-cpu" "cortex-m33"
+// CHECK-CORTEX-M35P:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} 
"-target-cpu" "cortex-m35p"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s


Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -822,8 +822,10 @@
 // RUN: %clang -target arm -mcpu=cortex-m23 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MBASE %s
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
-// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MMAIN %s
-// CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
+// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M33 %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M35P %s
+// CHECK-CORTEX-M33:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m33"
+// CHECK-CORTEX-M35P:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m35p"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
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[PATCH] D57765: [ARM] Add Cortex-M35P Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added a comment.

ping


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[PATCH] D57765: [ARM] Add Cortex-M35P Support

[Luke Cheeseman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL356742: [ARM] Add Cortex-M35P Support (authored by 
LukeCheeseman, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D57765?vs=188364&id=191852#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57765/new/

https://reviews.llvm.org/D57765

Files:
  cfe/trunk/test/Driver/arm-cortex-cpus.c


Index: cfe/trunk/test/Driver/arm-cortex-cpus.c
===
--- cfe/trunk/test/Driver/arm-cortex-cpus.c
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c
@@ -822,8 +822,10 @@
 // RUN: %clang -target arm -mcpu=cortex-m23 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MBASE %s
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
-// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
-// CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
+// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M33 %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CORTEX-M35P %s
+// CHECK-CORTEX-M33:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} 
"-target-cpu" "cortex-m33"
+// CHECK-CORTEX-M35P:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} 
"-target-cpu" "cortex-m35p"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s


Index: cfe/trunk/test/Driver/arm-cortex-cpus.c
===
--- cfe/trunk/test/Driver/arm-cortex-cpus.c
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c
@@ -822,8 +822,10 @@
 // RUN: %clang -target arm -mcpu=cortex-m23 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MBASE %s
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
-// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MMAIN %s
-// CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
+// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M33 %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M35P %s
+// CHECK-CORTEX-M33:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m33"
+// CHECK-CORTEX-M35P:  "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m35p"
 
 // == Check whether -mcpu accepts mixed-case values.
 // RUN: %clang -target arm-linux-gnueabi -mcpu=Cortex-a5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CASE-INSENSITIVE-CPUV7A %s
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[PATCH] D51432: [AArch64] Unwinding support for return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added inline comments.



Comment at: src/Registers.hpp:1835
+  if (((regNum >= 0) && (regNum < 32)) || regNum == UNW_ARM64_RA_SIGN_STATE)
 return _registers.__x[regNum];
+

olista01 wrote:
> When regNum == UNW_ARM64_RA_SIGN_STATE, the index into __x is out of range. 
> We'll need to add new storage to hold this value, I'd suggest replacing the 
> current padding value in the GPRs struct, as that will avoid changing the 
> layout expected by the context save/restore functions.
Good catch. Thanks, I didn't check the struct definition.


Repository:
  rUNW libunwind

https://reviews.llvm.org/D51432



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[PATCH] D51432: [AArch64] Unwinding support for return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 165775.
LukeCheeseman added a comment.

return an error code when trying to sign return addresses and cross unwinding


https://reviews.llvm.org/D51432

Files:
  include/libunwind.h
  src/DwarfInstructions.hpp
  src/DwarfParser.hpp
  src/Registers.hpp
  src/dwarf2.h

Index: src/dwarf2.h
===
--- src/dwarf2.h
+++ src/dwarf2.h
@@ -49,7 +49,10 @@
   // GNU extensions
   DW_CFA_GNU_window_save  = 0x2D,
   DW_CFA_GNU_args_size= 0x2E,
-  DW_CFA_GNU_negative_offset_extended = 0x2F
+  DW_CFA_GNU_negative_offset_extended = 0x2F,
+
+  // AARCH64 extensions
+  DW_CFA_AARCH64_negate_ra_state  = 0x2D
 };
 
 
Index: src/Registers.hpp
===
--- src/Registers.hpp
+++ src/Registers.hpp
@@ -1783,7 +1783,7 @@
 uint64_t __lr;// Link register x30
 uint64_t __sp;// Stack pointer x31
 uint64_t __pc;// Program counter
-uint64_t padding; // 16-byte align
+uint64_t __ra_sign_state; // RA sign state register
   };
 
   GPRs_registers;
@@ -1819,6 +1819,8 @@
 return false;
   if (regNum > 95)
 return false;
+  if (regNum == UNW_ARM64_RA_SIGN_STATE)
+return true;
   if ((regNum > 31) && (regNum < 64))
 return false;
   return true;
@@ -1829,16 +1831,21 @@
 return _registers.__pc;
   if (regNum == UNW_REG_SP)
 return _registers.__sp;
+  if (regNum == UNW_ARM64_RA_SIGN_STATE)
+return _registers.__ra_sign_state;
   if ((regNum >= 0) && (regNum < 32))
 return _registers.__x[regNum];
+
   _LIBUNWIND_ABORT("unsupported arm64 register");
 }
 
 inline void Registers_arm64::setRegister(int regNum, uint64_t value) {
   if (regNum == UNW_REG_IP)
 _registers.__pc = value;
   else if (regNum == UNW_REG_SP)
 _registers.__sp = value;
+  else if (regNum == UNW_ARM64_RA_SIGN_STATE)
+_registers.__ra_sign_state = value;
   else if ((regNum >= 0) && (regNum < 32))
 _registers.__x[regNum] = value;
   else
Index: src/DwarfParser.hpp
===
--- src/DwarfParser.hpp
+++ src/DwarfParser.hpp
@@ -666,6 +666,14 @@
   _LIBUNWIND_TRACE_DWARF(
   "DW_CFA_GNU_negative_offset_extended(%" PRId64 ")\n", offset);
   break;
+
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+case DW_CFA_AARCH64_negate_ra_state:
+  results->savedRegisters[UNW_ARM64_RA_SIGN_STATE].value ^= 0x1;
+  _LIBUNWIND_TRACE_DWARF("DW_CFA_AARCH64_negate_ra_state\n");
+  break;
+#endif
+
 default:
   operand = opcode & 0x3F;
   switch (opcode & 0xC0) {
Index: src/DwarfInstructions.hpp
===
--- src/DwarfInstructions.hpp
+++ src/DwarfInstructions.hpp
@@ -198,6 +198,24 @@
   // restoring SP means setting it to CFA.
   newRegisters.setSP(cfa);
 
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+  // If the target is aarch64 then the return address may have been signed
+  // using the v8.3 pointer authentication extensions. The original
+  // return address needs to be authenticated before the return address is
+  // restored. autia1716 is used instead of autia as autia1716 assembles
+  // to a NOP on pre-v8.3a architectures.
+  if (prolog.savedRegisters[UNW_ARM64_RA_SIGN_STATE].value) {
+#if !defined(_LIBUNWIND_IS_NATIVE_ONLY)
+return UNW_ECROSSRASIGNING;
+#else
+register unsigned long long x17 __asm("x17") = returnAddress;
+register unsigned long long x16 __asm("x16") = cfa;
+asm("autia1716": "+r"(x17): "r"(x16));
+returnAddress = x17;
+#endif
+  }
+#endif
+
   // Return address is address after call site instruction, so setting IP to
   // that does simualates a return.
   newRegisters.setIP(returnAddress);
Index: include/libunwind.h
===
--- include/libunwind.h
+++ include/libunwind.h
@@ -57,6 +57,9 @@
   UNW_EINVAL= -6547, /* unsupported operation or bad value */
   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
   UNW_ENOINFO   = -6549  /* no unwind info found */
+#if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
+  , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
+#endif
 };
 
 struct unw_context_t {
@@ -547,6 +550,8 @@
   UNW_ARM64_X31 = 31,
   UNW_ARM64_SP  = 31,
   // reserved block
+  UNW_ARM64_RA_SIGN_STATE = 34,
+  // reserved block
   UNW_ARM64_D0  = 64,
   UNW_ARM64_D1  = 65,
   UNW_ARM64_D2  = 66,
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[PATCH] D51432: [AArch64] Unwinding support for return address signing

[Luke Cheeseman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL342895: [AArch64] Unwinding support for return address 
signing (authored by LukeCheeseman, committed by ).
Herald added subscribers: llvm-commits, christof.

Changed prior to commit:
  https://reviews.llvm.org/D51432?vs=165775&id=166700#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51432

Files:
  libunwind/trunk/include/libunwind.h
  libunwind/trunk/src/DwarfInstructions.hpp
  libunwind/trunk/src/DwarfParser.hpp
  libunwind/trunk/src/Registers.hpp
  libunwind/trunk/src/dwarf2.h

Index: libunwind/trunk/src/DwarfInstructions.hpp
===
--- libunwind/trunk/src/DwarfInstructions.hpp
+++ libunwind/trunk/src/DwarfInstructions.hpp
@@ -198,6 +198,24 @@
   // restoring SP means setting it to CFA.
   newRegisters.setSP(cfa);
 
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+  // If the target is aarch64 then the return address may have been signed
+  // using the v8.3 pointer authentication extensions. The original
+  // return address needs to be authenticated before the return address is
+  // restored. autia1716 is used instead of autia as autia1716 assembles
+  // to a NOP on pre-v8.3a architectures.
+  if (prolog.savedRegisters[UNW_ARM64_RA_SIGN_STATE].value) {
+#if !defined(_LIBUNWIND_IS_NATIVE_ONLY)
+return UNW_ECROSSRASIGNING;
+#else
+register unsigned long long x17 __asm("x17") = returnAddress;
+register unsigned long long x16 __asm("x16") = cfa;
+asm("autia1716": "+r"(x17): "r"(x16));
+returnAddress = x17;
+#endif
+  }
+#endif
+
   // Return address is address after call site instruction, so setting IP to
   // that does simualates a return.
   newRegisters.setIP(returnAddress);
Index: libunwind/trunk/src/dwarf2.h
===
--- libunwind/trunk/src/dwarf2.h
+++ libunwind/trunk/src/dwarf2.h
@@ -49,7 +49,10 @@
   // GNU extensions
   DW_CFA_GNU_window_save  = 0x2D,
   DW_CFA_GNU_args_size= 0x2E,
-  DW_CFA_GNU_negative_offset_extended = 0x2F
+  DW_CFA_GNU_negative_offset_extended = 0x2F,
+
+  // AARCH64 extensions
+  DW_CFA_AARCH64_negate_ra_state  = 0x2D
 };
 
 
Index: libunwind/trunk/src/DwarfParser.hpp
===
--- libunwind/trunk/src/DwarfParser.hpp
+++ libunwind/trunk/src/DwarfParser.hpp
@@ -666,6 +666,14 @@
   _LIBUNWIND_TRACE_DWARF(
   "DW_CFA_GNU_negative_offset_extended(%" PRId64 ")\n", offset);
   break;
+
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+case DW_CFA_AARCH64_negate_ra_state:
+  results->savedRegisters[UNW_ARM64_RA_SIGN_STATE].value ^= 0x1;
+  _LIBUNWIND_TRACE_DWARF("DW_CFA_AARCH64_negate_ra_state\n");
+  break;
+#endif
+
 default:
   operand = opcode & 0x3F;
   switch (opcode & 0xC0) {
Index: libunwind/trunk/src/Registers.hpp
===
--- libunwind/trunk/src/Registers.hpp
+++ libunwind/trunk/src/Registers.hpp
@@ -1786,7 +1786,7 @@
 uint64_t __lr;// Link register x30
 uint64_t __sp;// Stack pointer x31
 uint64_t __pc;// Program counter
-uint64_t padding; // 16-byte align
+uint64_t __ra_sign_state; // RA sign state register
   };
 
   GPRs_registers;
@@ -1822,6 +1822,8 @@
 return false;
   if (regNum > 95)
 return false;
+  if (regNum == UNW_ARM64_RA_SIGN_STATE)
+return true;
   if ((regNum > 31) && (regNum < 64))
 return false;
   return true;
@@ -1832,16 +1834,21 @@
 return _registers.__pc;
   if (regNum == UNW_REG_SP)
 return _registers.__sp;
+  if (regNum == UNW_ARM64_RA_SIGN_STATE)
+return _registers.__ra_sign_state;
   if ((regNum >= 0) && (regNum < 32))
 return _registers.__x[regNum];
+
   _LIBUNWIND_ABORT("unsupported arm64 register");
 }
 
 inline void Registers_arm64::setRegister(int regNum, uint64_t value) {
   if (regNum == UNW_REG_IP)
 _registers.__pc = value;
   else if (regNum == UNW_REG_SP)
 _registers.__sp = value;
+  else if (regNum == UNW_ARM64_RA_SIGN_STATE)
+_registers.__ra_sign_state = value;
   else if ((regNum >= 0) && (regNum < 32))
 _registers.__x[regNum] = value;
   else
Index: libunwind/trunk/include/libunwind.h
===
--- libunwind/trunk/include/libunwind.h
+++ libunwind/trunk/include/libunwind.h
@@ -57,6 +57,9 @@
   UNW_EINVAL= -6547, /* unsupported operation or bad value */
   UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
   UNW_ENOINFO   = -6549  /* no unwind info found */
+#if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
+  , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
+#endif
 };
 
 struct unw_context_t {
@@ -547,6 +550,8 @@
   UNW_ARM64_

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 167723.
LukeCheeseman added a comment.

- Introduce the -mbranch-protection option. This is to be used for both pointer 
authentication and branch protection security features.
  - The branch protection compiler support will follow later
- The options available are -mbranch-protection=(+)* where  
::= [bti,pac-ret[+leaf,b-key]*]
- This should be the primary way of using branch protection features and the 
-msign-return-address option should be deprecated
- Remove the b-key selection from the earlier patch for -msign-return-address


https://reviews.llvm.org/D51429

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  include/clang/Driver/CC1Options.td
  include/clang/Driver/Options.td
  include/clang/Frontend/CodeGenOptions.def
  include/clang/Frontend/CodeGenOptions.h
  lib/CodeGen/CGDeclCXX.cpp
  lib/CodeGen/TargetInfo.cpp
  lib/Driver/ToolChains/Clang.cpp
  lib/Frontend/CompilerInvocation.cpp
  test/CodeGen/aarch64-sign-return-address.c
  test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp

Index: test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
===
--- test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
+++ test/CodeGenCXX/aarch64-sign-return-address-static-ctor.cpp
@@ -1,9 +1,9 @@
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | \
 // RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL  --check-prefix=CHECK-A-KEY
 // RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | \
-// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL
+// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ALL  --check-prefix=CHECK-A-KEY
 
 struct Foo {
   Foo() {}
@@ -16,6 +16,7 @@
 
 // CHECK: @[[CTOR_FN]]() #[[ATTR:[0-9]*]]
 
-// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
-// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+// CHECK-NONE-NOT: "sign-return-address"={{.*}}
+// CHECK-PARTIAL: "sign-return-address"="non-leaf"
+// CHECK-ALL: "sign-return-address"="all"
+// CHECK-A-KEY: "sign-return-address-key"="a_key"
Index: test/CodeGen/aarch64-sign-return-address.c
===
--- test/CodeGen/aarch64-sign-return-address.c
+++ test/CodeGen/aarch64-sign-return-address.c
@@ -1,14 +1,15 @@
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK-NONE
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK-PARTIAL
-// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s --check-prefix=CHECK-ALL
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=none  %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NONE
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=non-leaf %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-PARTIAL -check-prefix=CHECK-A-KEY
+// RUN: %clang -target aarch64-arm-none-eabi -S -emit-llvm -o - -msign-return-address=all %s | FileCheck %s  --check-prefix=CHECK --check-prefix=CHECK-ALL -check-prefix=CHECK-A-KEY
 
-// CHECK-NONE: @foo() #[[ATTR:[0-9]*]]
-// CHECK-NONE-NOT: attributes #[[ATTR]] = { {{.*}} "sign-return-address"={{.*}} }}
+// CHECK: @foo() #[[ATTR:[0-9]*]]
+//
+// CHECK-NONE-NOT: "sign-return-address"={{.*}}
 
-// CHECK-PARTIAL: @foo() #[[ATTR:[0-9]*]]
-// CHECK-PARTIAL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="non-leaf" {{.*}}}
+// CHECK-PARTIAL: "sign-return-address"="non-leaf"
 
-// CHECK-ALL: @foo() #[[ATTR:[0-9]*]]
-// CHECK-ALL: attributes #[[ATTR]] = { {{.*}} "sign-return-address"="all" {{.*}} }
+// CHECK-ALL: "sign-return-address"="all"
+
+// CHECK-A-KEY: "sign-return-address-key"="a_key"
 
 void foo() {}
Index: lib/Frontend/CompilerInvocation.cpp
===
--- lib/Frontend/CompilerInvocation.cpp
+++ lib/Frontend/CompilerInvocation.cpp
@@ -1129,8 +1129,11 @@
 
   Opts.Addrsig = Args.hasArg(OPT_faddrsig);
 
-  if (Arg *A = Args.getLastArg(OPT_msign_return_address)) {
-StringRef SignScope = A->getValue();
+  if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
+const auto SignScopeKey = StringRef(A->getValue()).split('+');
+StringRef SignScope = SignScopeKey.first;
+StringRef SignKey = SignScopeKey.seco

[PATCH] D51429: [AArch64] Return Address Signing B Key Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added inline comments.



Comment at: include/clang/Frontend/CodeGenOptions.h:117
 
+  enum SignReturnAddressKeyValue { AKey, BKey };
+

javed.absar wrote:
> Perhaps a line of comment on each enum-value would be useful (much like the 
> code around).
I'm not sure what value there would be in adding extra comments here, I think 
the values are fairly self explanatory.


https://reviews.llvm.org/D51429



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[PATCH] D57764: [AArch64] Add Cortex-A76 and Cortex-A76AE Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman created this revision.
LukeCheeseman added a reviewer: olista01.
Herald added subscribers: cfe-commits, kristof.beyls, javed.absar.
Herald added a project: clang.

- Add clang frontend testing for cortex-a76 and cortex-a76ae


Repository:
  rC Clang

https://reviews.llvm.org/D57764

Files:
  test/Driver/aarch64-cpus.c
  test/Driver/aarch64-dotprod.c
  test/Driver/arm-cortex-cpus.c
  test/Driver/arm-dotprod.c

Index: test/Driver/arm-dotprod.c
===
--- test/Driver/arm-dotprod.c
+++ test/Driver/arm-dotprod.c
@@ -7,6 +7,8 @@
 // RUN: %clang -### -target arm-linux-eabi -march=armv8.2a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -march=armv8.3a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a76 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a76ae %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
 // CHECK: "+dotprod"
 
@@ -17,6 +19,10 @@
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // RUN: %clang -### -target arm -mcpu=cortex-a75 %s 2>&1 \
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
+// RUN: %clang -### -target arm -mcpu=cortex-a76 %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
+// RUN: %clang -### -target arm -mcpu=cortex-a76ae %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // RUN: %clang -### -target arm -mcpu=cortex-a55 %s 2>&1 \
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // We rely on the backend disabling dotprod as it depends on neon, so check that
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -667,8 +667,12 @@
 
 // RUN: %clang -target arm -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
 // RUN: %clang -target arm -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76ae -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
 // RUN: %clang -target arm -mcpu=cortex-a55 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
 // RUN: %clang -target arm -mcpu=cortex-a75 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76ae -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
 //
 // RUN: %clang -target arm -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
 // RUN: %clang -target arm -mcpu=exynos-m4 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A %s
@@ -697,8 +701,12 @@
 
 // RUN: %clang -target armeb -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
 // RUN: %clang -target armeb -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target armeb -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target armeb -mcpu=cortex-a76ae -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
 // RUN: %clang -target arm -mcpu=cortex-a55 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
 // RUN: %clang -target arm -mcpu=cortex-a75 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
+// RUN: %clang -target arm -mcpu=cortex-a76ae -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
 //
 // RUN: %clang -target armeb -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
 // RUN: %clang -target arm -mcpu=exynos-m4 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV82A %s
@@ -730,8 +738,12 @@
 
 // RUN: %clang -target arm -mcpu=cortex-a55 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a75 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A-THUMB %s
+// RUN: %clang -target arm -mcpu=cortex-a76 -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A-THUMB %s
+// RUN: %clang -target arm -mcpu=cortex-a76ae -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a55 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV82A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a75 -mlittle-endian -mthumb -### -c %s 2>&1 | FileCheck -che

[PATCH] D57765: [ARM] Add Cortex-M35P Support

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman created this revision.
LukeCheeseman added a reviewer: olista01.
Herald added subscribers: cfe-commits, kristof.beyls, javed.absar.
Herald added a project: clang.

- Add clang frontend testing for Cortex-M35P


Repository:
  rC Clang

https://reviews.llvm.org/D57765

Files:
  test/Driver/arm-cortex-cpus.c


Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -823,6 +823,7 @@
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
 // RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8MMAIN %s
 // CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
 
 // == Check whether -mcpu accepts mixed-case values.


Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -823,6 +823,7 @@
 // CHECK-CPUV8MBASE:  "-cc1"{{.*}} "-triple" "thumbv8m.base-
 
 // RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MMAIN %s
+// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8MMAIN %s
 // CHECK-CPUV8MMAIN:  "-cc1"{{.*}} "-triple" "thumbv8m.main-
 
 // == Check whether -mcpu accepts mixed-case values.
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[PATCH] D57764: [AArch64] Add Cortex-A76 and Cortex-A76AE Support

[Luke Cheeseman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL354789: [AArch64] Add support for Cortex-A76 and 
Cortex-A76AE (authored by LukeCheeseman, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D57764?vs=185332&id=188167#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57764/new/

https://reviews.llvm.org/D57764

Files:
  cfe/trunk/test/Driver/aarch64-cpus.c
  cfe/trunk/test/Driver/aarch64-dotprod.c
  cfe/trunk/test/Driver/arm-cortex-cpus.c
  cfe/trunk/test/Driver/arm-dotprod.c

Index: cfe/trunk/test/Driver/aarch64-dotprod.c
===
--- cfe/trunk/test/Driver/aarch64-dotprod.c
+++ cfe/trunk/test/Driver/aarch64-dotprod.c
@@ -7,5 +7,6 @@
 // RUN: %clang -### -target aarch64 -march=armv8.2a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64 -march=armv8.3a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64 -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target aarch64 -mcpu=cortex-a76 %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target aarch64 -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
 // CHECK: "+dotprod"
Index: cfe/trunk/test/Driver/arm-dotprod.c
===
--- cfe/trunk/test/Driver/arm-dotprod.c
+++ cfe/trunk/test/Driver/arm-dotprod.c
@@ -7,6 +7,8 @@
 // RUN: %clang -### -target arm-linux-eabi -march=armv8.2a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -march=armv8.3a+dotprod %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a76 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a76ae %s 2>&1 | FileCheck %s
 // RUN: %clang -### -target arm-linux-eabi -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
 // CHECK: "+dotprod"
 
@@ -17,6 +19,10 @@
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // RUN: %clang -### -target arm -mcpu=cortex-a75 %s 2>&1 \
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
+// RUN: %clang -### -target arm -mcpu=cortex-a76 %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
+// RUN: %clang -### -target arm -mcpu=cortex-a76ae %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // RUN: %clang -### -target arm -mcpu=cortex-a55 %s 2>&1 \
 // RUN: | FileCheck %s --check-prefix=CHECK-NO-DOTPROD
 // We rely on the backend disabling dotprod as it depends on neon, so check that
Index: cfe/trunk/test/Driver/aarch64-cpus.c
===
--- cfe/trunk/test/Driver/aarch64-cpus.c
+++ cfe/trunk/test/Driver/aarch64-cpus.c
@@ -136,6 +136,22 @@
 // ARM64-CORTEX-A75: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a75"
 // ARM64-CORTEX-A75-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target aarch64 -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76 %s
+// RUN: %clang -target aarch64 -mtune=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76-TUNE %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76-TUNE %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A76-TUNE %s
+// CORTEX-A76: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "cortex-a76"
+// CORTEX-A76-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{(--)?}}"{{.*}} "-target-cpu" "generic"
+
+// RUN: %clang -target arm64 -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CORTEX-A76 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CORTEX-A76 %s
+// RUN: %clang -target arm64 -mtune=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CORTEX-A76-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=cortex-a76 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-CORTEX-A76-TUNE %s
+// ARM64-CORTEX-A76: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a76"
+// ARM64-CORTEX-A76-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
+
 // RUN: %clang -target aarch64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
 // RUN: %clang -target aarch64_be -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=M1 %s
Index: cfe/trunk/test/Driver/arm-cortex-cpus.c
=

[PATCH] D64210: [ARM] Fix vector vsqadd intrinsics operands

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added a comment.

Are there some changes/addition to tests attached to this?


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  rC Clang

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[PATCH] D64211: [ARM] Fix vector vuqadd intrinsics operands

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman added a comment.

Are there some changes/addition to tests attached to this?


Repository:
  rC Clang

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[PATCH] D67542: Fix depfile name construction

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman updated this revision to Diff 220067.
LukeCheeseman added a comment.

- Add a requires shell


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67542/new/

https://reviews.llvm.org/D67542

Files:
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/metadata-with-dots.c


Index: clang/test/Driver/metadata-with-dots.c
===
--- /dev/null
+++ clang/test/Driver/metadata-with-dots.c
@@ -0,0 +1,11 @@
+// REQUIRES: shell
+// RUN: mkdir -p out.dir
+// RUN: cat %s > out.dir/test.c
+// RUN: %clang -E -MMD %s -o out.dir/test
+// RUN: test ! -f %out.d
+// RUN: test -f out.dir/test.d
+// RUN: rm -rf out.dir/test.d out.dir/ out.d
+int main (void)
+{
+return 0;
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -6332,15 +6332,14 @@
 const char *Clang::getDependencyFileName(const ArgList &Args,
  const InputInfoList &Inputs) {
   // FIXME: Think about this more.
-  std::string Res;
 
   if (Arg *OutputOpt = Args.getLastArg(options::OPT_o)) {
-std::string Str(OutputOpt->getValue());
-Res = Str.substr(0, Str.rfind('.'));
-  } else {
-Res = getBaseInputStem(Args, Inputs);
+SmallString<128> OutputFilename(OutputOpt->getValue());
+llvm::sys::path::replace_extension(OutputFilename, llvm::Twine('d'));
+return Args.MakeArgString(OutputFilename);
   }
-  return Args.MakeArgString(Res + ".d");
+
+  return Args.MakeArgString(std::string(getBaseInputStem(Args, Inputs)) + 
".d");
 }
 
 // Begin ClangAs


Index: clang/test/Driver/metadata-with-dots.c
===
--- /dev/null
+++ clang/test/Driver/metadata-with-dots.c
@@ -0,0 +1,11 @@
+// REQUIRES: shell
+// RUN: mkdir -p out.dir
+// RUN: cat %s > out.dir/test.c
+// RUN: %clang -E -MMD %s -o out.dir/test
+// RUN: test ! -f %out.d
+// RUN: test -f out.dir/test.d
+// RUN: rm -rf out.dir/test.d out.dir/ out.d
+int main (void)
+{
+return 0;
+}
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -6332,15 +6332,14 @@
 const char *Clang::getDependencyFileName(const ArgList &Args,
  const InputInfoList &Inputs) {
   // FIXME: Think about this more.
-  std::string Res;
 
   if (Arg *OutputOpt = Args.getLastArg(options::OPT_o)) {
-std::string Str(OutputOpt->getValue());
-Res = Str.substr(0, Str.rfind('.'));
-  } else {
-Res = getBaseInputStem(Args, Inputs);
+SmallString<128> OutputFilename(OutputOpt->getValue());
+llvm::sys::path::replace_extension(OutputFilename, llvm::Twine('d'));
+return Args.MakeArgString(OutputFilename);
   }
-  return Args.MakeArgString(Res + ".d");
+
+  return Args.MakeArgString(std::string(getBaseInputStem(Args, Inputs)) + ".d");
 }
 
 // Begin ClangAs
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[PATCH] D67542: Fix depfile name construction

[Luke Cheeseman via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL371853: Fix depfile name construction (authored by 
LukeCheeseman, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D67542?vs=220067&id=220083#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67542/new/

https://reviews.llvm.org/D67542

Files:
  cfe/trunk/lib/Driver/ToolChains/Clang.cpp
  cfe/trunk/test/Driver/metadata-with-dots.c


Index: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp
@@ -6066,15 +6066,14 @@
 const char *Clang::getDependencyFileName(const ArgList &Args,
  const InputInfoList &Inputs) {
   // FIXME: Think about this more.
-  std::string Res;
 
   if (Arg *OutputOpt = Args.getLastArg(options::OPT_o)) {
-std::string Str(OutputOpt->getValue());
-Res = Str.substr(0, Str.rfind('.'));
-  } else {
-Res = getBaseInputStem(Args, Inputs);
+SmallString<128> OutputFilename(OutputOpt->getValue());
+llvm::sys::path::replace_extension(OutputFilename, llvm::Twine('d'));
+return Args.MakeArgString(OutputFilename);
   }
-  return Args.MakeArgString(Res + ".d");
+
+  return Args.MakeArgString(std::string(getBaseInputStem(Args, Inputs)) + 
".d");
 }
 
 // Begin ClangAs
Index: cfe/trunk/test/Driver/metadata-with-dots.c
===
--- cfe/trunk/test/Driver/metadata-with-dots.c
+++ cfe/trunk/test/Driver/metadata-with-dots.c
@@ -0,0 +1,11 @@
+// REQUIRES: shell
+// RUN: mkdir -p out.dir
+// RUN: cat %s > out.dir/test.c
+// RUN: %clang -E -MMD %s -o out.dir/test
+// RUN: test ! -f %out.d
+// RUN: test -f out.dir/test.d
+// RUN: rm -rf out.dir/test.d out.dir/ out.d
+int main (void)
+{
+return 0;
+}


Index: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp
@@ -6066,15 +6066,14 @@
 const char *Clang::getDependencyFileName(const ArgList &Args,
  const InputInfoList &Inputs) {
   // FIXME: Think about this more.
-  std::string Res;
 
   if (Arg *OutputOpt = Args.getLastArg(options::OPT_o)) {
-std::string Str(OutputOpt->getValue());
-Res = Str.substr(0, Str.rfind('.'));
-  } else {
-Res = getBaseInputStem(Args, Inputs);
+SmallString<128> OutputFilename(OutputOpt->getValue());
+llvm::sys::path::replace_extension(OutputFilename, llvm::Twine('d'));
+return Args.MakeArgString(OutputFilename);
   }
-  return Args.MakeArgString(Res + ".d");
+
+  return Args.MakeArgString(std::string(getBaseInputStem(Args, Inputs)) + ".d");
 }
 
 // Begin ClangAs
Index: cfe/trunk/test/Driver/metadata-with-dots.c
===
--- cfe/trunk/test/Driver/metadata-with-dots.c
+++ cfe/trunk/test/Driver/metadata-with-dots.c
@@ -0,0 +1,11 @@
+// REQUIRES: shell
+// RUN: mkdir -p out.dir
+// RUN: cat %s > out.dir/test.c
+// RUN: %clang -E -MMD %s -o out.dir/test
+// RUN: test ! -f %out.d
+// RUN: test -f out.dir/test.d
+// RUN: rm -rf out.dir/test.d out.dir/ out.d
+int main (void)
+{
+return 0;
+}
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[PATCH] D44555: clang-interpreter example cmake fix

[Luke Cheeseman via Phabricator via cfe-commits]

LukeCheeseman closed this revision.
LukeCheeseman added a comment.

closed by https://reviews.llvm.org/rC328092


Repository:
  rC Clang

https://reviews.llvm.org/D44555



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