[clang] 98cad55 - [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
Author: Lucas Prates
Date: 2020-05-26T10:09:35+01:00
New Revision: 98cad555e29187a03e2bc3db5780762981913902
URL:
https://github.com/llvm/llvm-project/commit/98cad555e29187a03e2bc3db5780762981913902
DIFF:
https://github.com/llvm/llvm-project/commit/98cad555e29187a03e2bc3db5780762981913902.diff
LOG: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1
intrinsicts
Summary:
During CodeGen for AArch64 Neon intrinsics, Clang was incorrectly
assuming all the pointers from which loads were being generated for vld1
intrinsics were aligned according to the intrinsics result type, causing
alignment faults on the code generated by the backend.
This patch updates vld1 intrinsics' CodeGen to properly capture the
correct load alignment based on the type of the pointer provided as
input for the intrinsic.
Reviewers: t.p.northover, ostannard, pcc
Reviewed By: ostannard
Subscribers: kristof.beyls, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79721
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-neon-intrinsics.c
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1adae1a7ea42..ddd9a68a8edb 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -10327,9 +10327,9 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
}
case NEON::BI__builtin_neon_vld1_v:
case NEON::BI__builtin_neon_vld1q_v: {
+auto Alignment = CGM.getNaturalPointeeTypeAlignment(
+E->getArg(0)->IgnoreParenCasts()->getType());
Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_v ? 8 : 16);
return Builder.CreateAlignedLoad(VTy, Ops[0], Alignment);
}
case NEON::BI__builtin_neon_vst1_v:
@@ -10342,8 +10342,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
Ty = llvm::PointerType::getUnqual(VTy->getElementType());
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_lane_v ? 8 : 16);
+auto Alignment = CGM.getNaturalPointeeTypeAlignment(
+E->getArg(0)->IgnoreParenCasts()->getType());
Ops[0] =
Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0], Alignment);
return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vld1_lane");
@@ -10353,8 +10353,8 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
Value *V = UndefValue::get(Ty);
Ty = llvm::PointerType::getUnqual(VTy->getElementType());
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_dup_v ? 8 : 16);
+auto Alignment = CGM.getNaturalPointeeTypeAlignment(
+E->getArg(0)->IgnoreParenCasts()->getType());
Ops[0] =
Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0], Alignment);
llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c
b/clang/test/CodeGen/aarch64-neon-intrinsics.c
index 7744b4f4a159..1fb245f3d342 100644
--- a/clang/test/CodeGen/aarch64-neon-intrinsics.c
+++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c
@@ -8956,7 +8956,7 @@ float64_t test_vrsqrted_f64(float64_t a) {
// CHECK-LABEL: @test_vld1q_u8(
// CHECK: [[TMP0:%.*]] = bitcast i8* %a to <16 x i8>*
-// CHECK: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]]
+// CHECK: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* [[TMP0]], align 1
// CHECK: ret <16 x i8> [[TMP1]]
uint8x16_t test_vld1q_u8(uint8_t const *a) {
return vld1q_u8(a);
@@ -8965,7 +8965,7 @@ uint8x16_t test_vld1q_u8(uint8_t const *a) {
// CHECK-LABEL: @test_vld1q_u16(
// CHECK: [[TMP0:%.*]] = bitcast i16* %a to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <8 x i16>*
-// CHECK: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]]
+// CHECK: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
// CHECK: ret <8 x i16> [[TMP2]]
uint16x8_t test_vld1q_u16(uint16_t const *a) {
return vld1q_u16(a);
@@ -8974,7 +8974,7 @@ uint16x8_t test_vld1q_u16(uint16_t const *a) {
// CHECK-LABEL: @test_vld1q_u32(
// CHECK: [[TMP0:%.*]] = bitcast i32* %a to i8*
// CHECK: [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i32>*
-// CHECK: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]]
+// CHECK: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
// CHECK: ret <4 x i32> [[TMP2]]
uint32x4_t test_vld1q_u32(uint32_t const *a) {
return vld1q_u32(a);
@@ -8983,7 +8983,7 @@ uint32x4_t test_vld1q_u32(uint32_t const *a) {
// CHECK-LABEL: @test_vld1q_u64(
// CHECK: [[TMP0:%.*]] = bitcast i64* %a to i8*
/
[clang] 8beaba1 - [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
Author: Lucas Prates
Date: 2020-06-03T11:39:27+01:00
New Revision: 8beaba13b8a61697008854b82ed3b45377af9d9d
URL:
https://github.com/llvm/llvm-project/commit/8beaba13b8a61697008854b82ed3b45377af9d9d
DIFF:
https://github.com/llvm/llvm-project/commit/8beaba13b8a61697008854b82ed3b45377af9d9d.diff
LOG: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1
intrinsicts
Summary:
During CodeGen for AArch64 Neon intrinsics, Clang was incorrectly
assuming all the pointers from which loads were being generated for vld1
intrinsics were aligned according to the intrinsics result type, causing
alignment faults on the code generated by the backend.
This patch updates vld1 intrinsics' CodeGen to properly capture the
correct load alignment based on the type of the pointer provided as
input for the intrinsic.
Reviewers: t.p.northover, ostannard, pcc, efriedma
Reviewed By: ostannard, efriedma
Subscribers: echristo, plotfi, nickdesaulniers, efriedma, kristof.beyls,
danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79721
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-neon-intrinsics.c
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index cf8c8a1669d7..13c24a5d2686 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -8636,7 +8636,27 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
assert(Error == ASTContext::GE_None && "Should not codegen an error");
llvm::SmallVector Ops;
+ Address PtrOp0 = Address::invalid();
for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++) {
+if (i == 0) {
+ switch (BuiltinID) {
+ case NEON::BI__builtin_neon_vld1_v:
+ case NEON::BI__builtin_neon_vld1q_v:
+ case NEON::BI__builtin_neon_vld1_dup_v:
+ case NEON::BI__builtin_neon_vld1q_dup_v:
+ case NEON::BI__builtin_neon_vld1_lane_v:
+ case NEON::BI__builtin_neon_vld1q_lane_v:
+ case NEON::BI__builtin_neon_vst1_v:
+ case NEON::BI__builtin_neon_vst1q_v:
+ case NEON::BI__builtin_neon_vst1_lane_v:
+ case NEON::BI__builtin_neon_vst1q_lane_v:
+// Get the alignment for the argument in addition to the value;
+// we'll use it later.
+PtrOp0 = EmitPointerWithAlignment(E->getArg(0));
+Ops.push_back(PtrOp0.getPointer());
+continue;
+ }
+}
if ((ICEArguments & (1 << i)) == 0) {
Ops.push_back(EmitScalarExpr(E->getArg(i)));
} else {
@@ -10337,24 +10357,20 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
case NEON::BI__builtin_neon_vld1_v:
case NEON::BI__builtin_neon_vld1q_v: {
Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_v ? 8 : 16);
-return Builder.CreateAlignedLoad(VTy, Ops[0], Alignment);
+return Builder.CreateAlignedLoad(VTy, Ops[0], PtrOp0.getAlignment());
}
case NEON::BI__builtin_neon_vst1_v:
case NEON::BI__builtin_neon_vst1q_v:
Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(VTy));
Ops[1] = Builder.CreateBitCast(Ops[1], VTy);
-return Builder.CreateDefaultAlignedStore(Ops[1], Ops[0]);
+return Builder.CreateAlignedStore(Ops[1], Ops[0], PtrOp0.getAlignment());
case NEON::BI__builtin_neon_vld1_lane_v:
case NEON::BI__builtin_neon_vld1q_lane_v: {
Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
Ty = llvm::PointerType::getUnqual(VTy->getElementType());
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_lane_v ? 8 : 16);
-Ops[0] =
-Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0], Alignment);
+Ops[0] = Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0],
+ PtrOp0.getAlignment());
return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vld1_lane");
}
case NEON::BI__builtin_neon_vld1_dup_v:
@@ -10362,10 +10378,8 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
Value *V = UndefValue::get(Ty);
Ty = llvm::PointerType::getUnqual(VTy->getElementType());
Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
-auto Alignment = CharUnits::fromQuantity(
-BuiltinID == NEON::BI__builtin_neon_vld1_dup_v ? 8 : 16);
-Ops[0] =
-Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0], Alignment);
+Ops[0] = Builder.CreateAlignedLoad(VTy->getElementType(), Ops[0],
+ PtrOp0.getAlignment());
llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
Ops[0] = Builder.CreateInsertElement(V, Ops[0], CI);
return EmitNeonSplat(Ops[0], CI);
@@ -10375,8 +10389,8 @@ Value *CodeGenFunc
[clang] ada4c9d - [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen
Author: Lucas Prates
Date: 2020-06-18T13:17:07+01:00
New Revision: ada4c9dc4a63160b6b3cfd5965884c6cce2a405c
URL:
https://github.com/llvm/llvm-project/commit/ada4c9dc4a63160b6b3cfd5965884c6cce2a405c
DIFF:
https://github.com/llvm/llvm-project/commit/ada4c9dc4a63160b6b3cfd5965884c6cce2a405c.diff
LOG: [ARM][Clang] Removing lowering of half-precision FP arguments and returns
from Clang's CodeGen
Summary:
On the process of moving the argument lowering handling for
half-precision floating point arguments and returns to the backend, this
patch removes the code that was responsible for handling the coercion of
those arguments in Clang's Codegen.
Reviewers: rjmccall, chill, ostannard, dnsampaio
Reviewed By: ostannard
Subscribers: stuij, kristof.beyls, dmgreen, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D81451
Added:
Modified:
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/arm-fp16-arguments.c
clang/test/CodeGen/arm-mve-intrinsics/compare.c
clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
clang/test/CodeGen/arm-mve-intrinsics/dup.c
clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c
clang/test/CodeGen/arm-mve-intrinsics/ternary.c
clang/test/CodeGen/arm-mve-intrinsics/vaddq.c
clang/test/CodeGen/arm-mve-intrinsics/vminvq.c
clang/test/CodeGen/arm-mve-intrinsics/vmulq.c
clang/test/CodeGen/arm-mve-intrinsics/vsubq.c
Removed:
clang/test/CodeGen/cmse-clear-fp16.c
diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp
index 78a0ecef4f3f..87242442a57f 100644
--- a/clang/lib/CodeGen/CGCall.cpp
+++ b/clang/lib/CodeGen/CGCall.cpp
@@ -3124,20 +3124,6 @@ llvm::Value
*CodeGenFunction::EmitCMSEClearRecord(llvm::Value *Src,
return R;
}
-// Emit code to clear the padding bits when returning or passing as an argument
-// a 16-bit floating-point value.
-llvm::Value *CodeGenFunction::EmitCMSEClearFP16(llvm::Value *Src) {
- llvm::Type *RetTy = Src->getType();
- assert(RetTy->isFloatTy() ||
- (RetTy->isIntegerTy() && RetTy->getIntegerBitWidth() == 32));
- if (RetTy->isFloatTy()) {
-llvm::Value *T0 = Builder.CreateBitCast(Src, Builder.getIntNTy(32));
-llvm::Value *T1 = Builder.CreateAnd(T0, 0x, "cmse.clear");
-return Builder.CreateBitCast(T1, RetTy);
- }
- return Builder.CreateAnd(Src, 0x, "cmse.clear");
-}
-
void CodeGenFunction::EmitFunctionEpilog(const CGFunctionInfo &FI,
bool EmitRetDbgLoc,
SourceLocation EndLoc) {
@@ -3307,17 +3293,10 @@ void CodeGenFunction::EmitFunctionEpilog(const
CGFunctionInfo &FI,
if (CurFuncDecl && CurFuncDecl->hasAttr()) {
// For certain return types, clear padding bits, as they may reveal
// sensitive information.
- const Type *RTy = RetTy.getCanonicalType().getTypePtr();
- if (RTy->isFloat16Type() || RTy->isHalfType()) {
-// 16-bit floating-point types are passed in a 32-bit integer or float,
-// with unspecified upper bits.
-RV = EmitCMSEClearFP16(RV);
- } else {
-// Small struct/union types are passed as integers.
-auto *ITy = dyn_cast(RV->getType());
-if (ITy != nullptr && isa(RetTy.getCanonicalType()))
- RV = EmitCMSEClearRecord(RV, ITy, RetTy);
- }
+ // Small struct/union types are passed as integers.
+ auto *ITy = dyn_cast(RV->getType());
+ if (ITy != nullptr && isa(RetTy.getCanonicalType()))
+RV = EmitCMSEClearRecord(RV, ITy, RetTy);
}
EmitReturnValueCheck(RV);
Ret = Builder.CreateRet(RV);
@@ -4620,17 +4599,10 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo
&CallInfo,
if (CallInfo.isCmseNSCall()) {
// For certain parameter types, clear padding bits, as they may
reveal
// sensitive information.
- const Type *PTy = I->Ty.getCanonicalType().getTypePtr();
- // 16-bit floating-point types are passed in a 32-bit integer or
- // float, with unspecified upper bits.
- if (PTy->isFloat16Type() || PTy->isHalfType()) {
-Load = EmitCMSEClearFP16(Load);
- } else {
-// Small struct/union types are passed as integer arrays.
-auto *ATy = dyn_cast(Load->getType());
-if (ATy != nullptr && isa(I->Ty.getCanonicalType()))
- Load = EmitCMSEClearRecord(Load, ATy, I->Ty);
- }
+ // Small struct/union types are passed as integer arrays.
+ auto *ATy = dyn_cast(Load->getType());
+ if (ATy != nullptr && isa(I->Ty.getCanonicalType()))
+Load = EmitCMSEClearRecord(Load, ATy, I->Ty);
}
IRCallArgs[FirstIRArg] = Load;
}
diff --git a/clang/lib/CodeGen/CodeGenFunction.h
b/c
[clang] 0dac639 - [Clang][Sema] Capturing section type conflicts on #pragma clang section
Author: Lucas Prates
Date: 2020-05-07T11:53:30+01:00
New Revision: 0dac639f285a53dffe3239ec5561fa0fc2da0daf
URL:
https://github.com/llvm/llvm-project/commit/0dac639f285a53dffe3239ec5561fa0fc2da0daf
DIFF:
https://github.com/llvm/llvm-project/commit/0dac639f285a53dffe3239ec5561fa0fc2da0daf.diff
LOG: [Clang][Sema] Capturing section type conflicts on #pragma clang section
Summary:
Section names used in clang section pragmas were not validated against
previously defined sections, causing section type conflicts to be
ignored by Sema.
This patch enables Clang to capture these section type conflicts by
using the existing Sema's UnifySection method to validate section names
from clang section pragmas.
Reviewers: hans, rnk, javed.absar
Reviewed By: rnk
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78572
Added:
Modified:
clang/include/clang/AST/ASTContext.h
clang/lib/Parse/ParsePragma.cpp
clang/lib/Sema/SemaAttr.cpp
clang/test/Sema/pragma-clang-section.c
Removed:
diff --git a/clang/include/clang/AST/ASTContext.h
b/clang/include/clang/AST/ASTContext.h
index cd7021a5884b..5f8e7fceabc0 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -2978,6 +2978,7 @@ OPT_LIST(V)
PSF_Write = 0x2,
PSF_Execute = 0x4,
PSF_Implicit = 0x8,
+PSF_ZeroInit = 0x10,
PSF_Invalid = 0x8000U,
};
diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp
index 828d429e6969..816aaf9f0956 100644
--- a/clang/lib/Parse/ParsePragma.cpp
+++ b/clang/lib/Parse/ParsePragma.cpp
@@ -1873,6 +1873,7 @@ void PragmaClangSectionHandler::HandlePragma(Preprocessor
&PP,
return;
}
+SourceLocation PragmaLocation = Tok.getLocation();
PP.Lex(Tok); // eat ['bss'|'data'|'rodata'|'text']
if (Tok.isNot(tok::equal)) {
PP.Diag(Tok.getLocation(),
diag::err_pragma_clang_section_expected_equal) << SecKind;
@@ -1883,10 +1884,11 @@ void
PragmaClangSectionHandler::HandlePragma(Preprocessor &PP,
if (!PP.LexStringLiteral(Tok, SecName, "pragma clang section", false))
return;
-Actions.ActOnPragmaClangSection(Tok.getLocation(),
- (SecName.size()? Sema::PragmaClangSectionAction::PCSA_Set :
- Sema::PragmaClangSectionAction::PCSA_Clear),
- SecKind, SecName);
+Actions.ActOnPragmaClangSection(
+PragmaLocation,
+(SecName.size() ? Sema::PragmaClangSectionAction::PCSA_Set
+: Sema::PragmaClangSectionAction::PCSA_Clear),
+SecKind, SecName);
}
}
diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp
index 50089dea7759..b5cb96dff44b 100644
--- a/clang/lib/Sema/SemaAttr.cpp
+++ b/clang/lib/Sema/SemaAttr.cpp
@@ -256,12 +256,15 @@ void Sema::ActOnPragmaOptionsAlign(PragmaOptionsAlignKind
Kind,
void Sema::ActOnPragmaClangSection(SourceLocation PragmaLoc,
PragmaClangSectionAction Action,
PragmaClangSectionKind SecKind, StringRef
SecName) {
PragmaClangSection *CSec;
+ int SectionFlags = ASTContext::PSF_Read;
switch (SecKind) {
case PragmaClangSectionKind::PCSK_BSS:
CSec = &PragmaClangBSSSection;
+ SectionFlags |= ASTContext::PSF_Write | ASTContext::PSF_ZeroInit;
break;
case PragmaClangSectionKind::PCSK_Data:
CSec = &PragmaClangDataSection;
+ SectionFlags |= ASTContext::PSF_Write;
break;
case PragmaClangSectionKind::PCSK_Rodata:
CSec = &PragmaClangRodataSection;
@@ -271,6 +274,7 @@ void Sema::ActOnPragmaClangSection(SourceLocation
PragmaLoc, PragmaClangSectionA
break;
case PragmaClangSectionKind::PCSK_Text:
CSec = &PragmaClangTextSection;
+ SectionFlags |= ASTContext::PSF_Execute;
break;
default:
llvm_unreachable("invalid clang section kind");
@@ -281,6 +285,9 @@ void Sema::ActOnPragmaClangSection(SourceLocation
PragmaLoc, PragmaClangSectionA
return;
}
+ if (UnifySection(SecName, SectionFlags, PragmaLoc))
+return;
+
CSec->Valid = true;
CSec->SectionName = std::string(SecName);
CSec->PragmaLocation = PragmaLoc;
diff --git a/clang/test/Sema/pragma-clang-section.c
b/clang/test/Sema/pragma-clang-section.c
index 38a3bc92744f..97d10f5f11c3 100644
--- a/clang/test/Sema/pragma-clang-section.c
+++ b/clang/test/Sema/pragma-clang-section.c
@@ -1,5 +1,5 @@
// RUN: %clang_cc1 -fsyntax-only -verify %s -triple arm-none-eabi
-#pragma clang section bss="mybss.1" data="mydata.1" rodata="myrodata.1"
text="mytext.1"
+#pragma clang section bss = "mybss.1" data = "mydata.1" rodata = "myrodata.1"
text = "mytext.1" // expected-note 2 {{#pragma entered here}}
#pragma clang section bss="" data="" rodata="" text=""
#pragma clang section
@@ -16,4 +16,10 @@
#pragma clang section text "text.2" // expected-error {{expected '
[clang] 9d39df0 - [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes
Author: Lucas Prates
Date: 2020-05-07T11:54:46+01:00
New Revision: 9d39df03a984ff4bed7d441a110d44976a8ab21b
URL:
https://github.com/llvm/llvm-project/commit/9d39df03a984ff4bed7d441a110d44976a8ab21b
DIFF:
https://github.com/llvm/llvm-project/commit/9d39df03a984ff4bed7d441a110d44976a8ab21b.diff
LOG: [Clang][Sema] Capturing section type conflicts between #pragma clang
section and section attributes
Summary:
Conflicting types for the same section name defined in clang section
pragmas and GNU-style section attributes were not properly captured by
Clang's Sema. The lack of diagnostics was caused by the fact the section
specification coming from attributes was handled by Sema as implicit,
even though explicitly defined by the user.
This patch enables the diagnostics for section type conflicts between
those specifications by making sure sections defined in section
attributes are correctly handled as explicit.
Reviewers: hans, rnk, javed.absar
Reviewed By: rnk
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78573
Added:
Modified:
clang/include/clang/AST/ASTContext.h
clang/lib/AST/ASTContext.cpp
clang/lib/Sema/SemaAttr.cpp
clang/lib/Sema/SemaDecl.cpp
clang/test/Sema/pragma-clang-section.c
Removed:
diff --git a/clang/include/clang/AST/ASTContext.h
b/clang/include/clang/AST/ASTContext.h
index 5f8e7fceabc0..8eb5aa0230d9 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -3006,6 +3006,10 @@ OPT_LIST(V)
SmallVector, 4> OMPTraitInfoVector;
};
+/// Insertion operator for diagnostics.
+const DiagnosticBuilder &operator<<(const DiagnosticBuilder &DB,
+const ASTContext::SectionInfo &Section);
+
/// Utility function for constructing a nullary selector.
inline Selector GetNullarySelector(StringRef name, ASTContext &Ctx) {
IdentifierInfo* II = &Ctx.Idents.get(name);
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 612f6eec2d0f..4ed0073eba08 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -11011,3 +11011,11 @@ OMPTraitInfo &ASTContext::getNewOMPTraitInfo() {
OMPTraitInfoVector.emplace_back(new OMPTraitInfo());
return *OMPTraitInfoVector.back();
}
+
+const DiagnosticBuilder &
+clang::operator<<(const DiagnosticBuilder &DB,
+ const ASTContext::SectionInfo &Section) {
+ if (Section.Decl)
+return DB << Section.Decl;
+ return DB << "a prior #pragma section";
+}
diff --git a/clang/lib/Sema/SemaAttr.cpp b/clang/lib/Sema/SemaAttr.cpp
index b5cb96dff44b..01f30a985935 100644
--- a/clang/lib/Sema/SemaAttr.cpp
+++ b/clang/lib/Sema/SemaAttr.cpp
@@ -530,42 +530,49 @@ void Sema::PragmaStack::Act(SourceLocation
PragmaLocation,
bool Sema::UnifySection(StringRef SectionName,
int SectionFlags,
DeclaratorDecl *Decl) {
- auto Section = Context.SectionInfos.find(SectionName);
- if (Section == Context.SectionInfos.end()) {
+ SourceLocation PragmaLocation;
+ if (auto A = Decl->getAttr())
+if (A->isImplicit())
+ PragmaLocation = A->getLocation();
+ auto SectionIt = Context.SectionInfos.find(SectionName);
+ if (SectionIt == Context.SectionInfos.end()) {
Context.SectionInfos[SectionName] =
-ASTContext::SectionInfo(Decl, SourceLocation(), SectionFlags);
+ASTContext::SectionInfo(Decl, PragmaLocation, SectionFlags);
return false;
}
// A pre-declared section takes precedence w/o diagnostic.
- if (Section->second.SectionFlags == SectionFlags ||
- !(Section->second.SectionFlags & ASTContext::PSF_Implicit))
+ const auto &Section = SectionIt->second;
+ if (Section.SectionFlags == SectionFlags ||
+ ((SectionFlags & ASTContext::PSF_Implicit) &&
+ !(Section.SectionFlags & ASTContext::PSF_Implicit)))
return false;
- auto OtherDecl = Section->second.Decl;
- Diag(Decl->getLocation(), diag::err_section_conflict)
- << Decl << OtherDecl;
- Diag(OtherDecl->getLocation(), diag::note_declared_at)
- << OtherDecl->getName();
- if (auto A = Decl->getAttr())
-if (A->isImplicit())
- Diag(A->getLocation(), diag::note_pragma_entered_here);
- if (auto A = OtherDecl->getAttr())
-if (A->isImplicit())
- Diag(A->getLocation(), diag::note_pragma_entered_here);
+ Diag(Decl->getLocation(), diag::err_section_conflict) << Decl << Section;
+ if (Section.Decl)
+Diag(Section.Decl->getLocation(), diag::note_declared_at)
+<< Section.Decl->getName();
+ if (PragmaLocation.isValid())
+Diag(PragmaLocation, diag::note_pragma_entered_here);
+ if (Section.PragmaSectionLocation.isValid())
+Diag(Section.PragmaSectionLocation, diag::note_pragma_entered_here);
return true;
}
bool Sema::UnifySection(StringRef SectionName,
int SectionFlags,
[clang] d43fc5a - Reland: [AArch64] Assembly support for the Checked Pointer Arithmetic Extension (#73777)
Author: Lucas Duarte Prates
Date: 2023-12-20T15:43:17Z
New Revision: d43fc5a6ad2f6092ac82b76590951235ec46f6e2
URL:
https://github.com/llvm/llvm-project/commit/d43fc5a6ad2f6092ac82b76590951235ec46f6e2
DIFF:
https://github.com/llvm/llvm-project/commit/d43fc5a6ad2f6092ac82b76590951235ec46f6e2.diff
LOG: Reland: [AArch64] Assembly support for the Checked Pointer Arithmetic
Extension (#73777)
This introduces assembly support for the Checked Pointer Arithmetic
Extension (FEAT_CPA), annouced as part of the Armv9.5-A architecture
version.
The changes include:
* New subtarget feature for FEAT_CPA
* New scalar instruction for pointer arithmetic
* ADDPT, SUBPT, MADDPT, and MSUBPT
* New SVE instructions for pointer arithmetic
* ADDPT (vectors, predicated), ADDPT (vectors, unpredicated)
* SUBPT (vectors, predicated), SUBPT (vectors, unpredicated)
* MADPT and MLAPT
* New ID_AA64ISAR3_EL1 system register
Mode details about the extension can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/
Co-authored-by: Rodolfo Wottrich
Added:
llvm/test/MC/AArch64/SVE/armv9.5a-cpa.s
llvm/test/MC/AArch64/armv9.5a-cpa.s
llvm/test/MC/Disassembler/AArch64/armv9.5a-cpa.txt
Modified:
clang/test/Driver/aarch64-v95a.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AArch64SchedA64FX.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/MC/AArch64/basic-a64-diagnostics.s
llvm/test/MC/AArch64/basic-a64-instructions.s
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-v95a.c
b/clang/test/Driver/aarch64-v95a.c
index 6044a4f155db02..366cade86a9fb7 100644
--- a/clang/test/Driver/aarch64-v95a.c
+++ b/clang/test/Driver/aarch64-v95a.c
@@ -13,3 +13,8 @@
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s
2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu"
"generic" "-target-feature" "+neon" "-target-feature" "+v9.5a"
+// = Features supported on aarch64 =
+
+// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck
-check-prefix=V95A-CPA %s
+// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 |
FileCheck -check-prefix=V95A-CPA %s
+// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
"-target-feature" "+neon" "-target-feature" "+v9.5a" "-target-feature" "+cpa"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 56c32fae712cef..f0b35790133fbe 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -173,6 +173,7 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_CPA = 72, // FEAT_CPA
AEK_NUM_EXTENSIONS
};
using ExtensionBitset = Bitset;
@@ -295,6 +296,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32",
FEAT_INIT, "+sme2,+fp8", 0},
{"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT,
"", 0},
+{"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0},
// Special cases
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "",
ExtensionInfo::MaxFMVPriority},
};
@@ -378,7 +380,8 @@ inline constexpr ArchInfo ARMV9_3A = { VersionTuple{9, 3},
AProfile, "armv9.3-a
AArch64::ExtensionBitset({AArch64::AEK_MOPS, AArch64::AEK_HBC}))};
inline constexpr ArchInfo ARMV9_4A = { VersionTuple{9, 4}, AProfile,
"armv9.4-a", "+v9.4a", (ARMV9_3A.DefaultExts |
AArch64::ExtensionBitset({AArch64::AEK_SPECRES2, AArch64::AEK_CSSC,
AArch64::AEK_RASv2}))};
-inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile,
"armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts)};
+inline constexpr ArchInfo ARMV9_5A = { VersionTuple{9, 5}, AProfile,
"armv9.5-a", "+v9.5a", (ARMV9_4A.DefaultExts |
+
[clang] 70a5c52 - [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Author: Lucas Prates
Date: 2022-06-27T14:08:48+01:00
New Revision: 70a5c525349be3ce9ad2bfdf9c995355ba07c864
URL:
https://github.com/llvm/llvm-project/commit/70a5c525349be3ce9ad2bfdf9c995355ba07c864
DIFF:
https://github.com/llvm/llvm-project/commit/70a5c525349be3ce9ad2bfdf9c995355ba07c864.diff
LOG: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Currently the a AAPCS compliant frame record is not always created for
functions when it should. Although a consistent frame record might not
be required in some cases, there are still scenarios where applications
may want to make use of the call hierarchy made available trough it.
In order to enable the use of AAPCS compliant frame records whilst keep
backwards compatibility, this patch introduces a new command-line option
(`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends.
The option allows users to explicitly select when to use it, and is also
useful to ensure the extra overhead introduced by the frame records is
only introduced when necessary, in particular for Thumb targets.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D125094
Added:
llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
llvm/test/CodeGen/ARM/frame-chain.ll
llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
llvm/test/CodeGen/Thumb/frame-chain.ll
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallingConv.td
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMFrameLowering.h
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/test/CodeGen/Thumb/frame-access.ll
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 06c7e415384cd..3682f7cab4824 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3493,7 +3493,9 @@ defm aapcs_bitfield_width : BoolOption<"f",
"aapcs-bitfield-width",
BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement
stating that"
" volatile bit-field width is dictated by the field container
type. (ARM only).">>,
Group;
-
+def mframe_chain : Joined<["-"], "mframe-chain=">,
+ Group, Values<"none,aapcs,aapcs+leaf">,
+ HelpText<"Select the frame chain model used to emit frame records (Arm
only).">;
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64/x86 only)">;
def mfix_cmse_cve_2021_35465 : Flag<["-"], "mfix-cmse-cve-2021-35465">,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index dc6b35e39cfdd..b79d1f00ea48b 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -718,6 +718,15 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
}
+ // Propagate frame-chain model selection
+ if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) {
+StringRef FrameChainOption = A->getValue();
+if (FrameChainOption.startswith("aapcs"))
+ Features.push_back("+aapcs-frame-chain");
+if (FrameChainOption == "aapcs+leaf")
+ Features.push_back("+aapcs-frame-chain-leaf");
+ }
+
// CMSE: Check for target 8M (for -mcmse to be applicable) is performed
later.
if (Args.getLastArg(options::OPT_mcmse))
Features.push_back("+8msecext");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index e8970b916a5f0..48559a89a30a0 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -546,6 +546,16 @@ def FeatureFixCortexA57AES1742098 :
SubtargetFeature<"fix-cortex-a57-aes-1742098
"FixCortexA57AES1742098", "true",
"Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
+def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
+ "CreateAAPCSFrameChain", "true",
+ "Create an AAPCS compliant frame
chain">;
+
+def FeatureAAPCSFrameChainLeaf : SubtargetFeature<"aapcs-frame-chain-leaf",
+ "CreateAAPCSFrameChainLeaf",
"true",
+ "Create an AAPCS compliant
frame chain "
+ "for leaf functions",
+ [FeatureAAPCSFrameChain]>;
+
//===--===//
// ARM architecture class
//
diff --git a/llvm/lib/Targe
[clang] c4d851b - [ARM][AAarch64] Initial command-line support for v8.7-A
Author: Lucas Prates
Date: 2020-12-17T13:47:28Z
New Revision: c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa
URL:
https://github.com/llvm/llvm-project/commit/c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa
DIFF:
https://github.com/llvm/llvm-project/commit/c4d851b079037e9b7dd3f8613dd1c8a4f3db99fa.diff
LOG: [ARM][AAarch64] Initial command-line support for v8.7-A
This introduces command-line support for the 'armv8.7-a' architecture name
(and an alias without the '-', as usual), and for the 'ls64' extension name.
Based on patches written by Simon Tatham.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D91776
Added:
clang/test/Driver/aarch64-ls64.c
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
clang/test/Driver/aarch64-cpus.c
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/AArch64TargetParser.h
llvm/lib/Support/AArch64TargetParser.cpp
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index c8162dd55220..c1abe8e9f75b 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -196,6 +196,12 @@ void AArch64TargetInfo::getTargetDefinesARMV86A(const
LangOptions &Opts,
getTargetDefinesARMV85A(Opts, Builder);
}
+void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
+MacroBuilder &Builder) const {
+ // Also include the Armv8.6 defines
+ getTargetDefinesARMV86A(Opts, Builder);
+}
+
void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const {
// Target identification.
@@ -371,6 +377,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
case llvm::AArch64::ArchKind::ARMV8_6A:
getTargetDefinesARMV86A(Opts, Builder);
break;
+ case llvm::AArch64::ArchKind::ARMV8_7A:
+getTargetDefinesARMV87A(Opts, Builder);
+break;
}
// All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
@@ -411,6 +420,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFP16FML = false;
HasMTE = false;
HasTME = false;
+ HasLS64 = false;
HasMatMul = false;
HasBFloat16 = false;
HasSVE2 = false;
@@ -486,6 +496,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
if (Feature == "+v8.6a")
ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
+if (Feature == "+v8.7a")
+ ArchKind = llvm::AArch64::ArchKind::ARMV8_7A;
if (Feature == "+v8r")
ArchKind = llvm::AArch64::ArchKind::ARMV8R;
if (Feature == "+fullfp16")
@@ -504,6 +516,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasBFloat16 = true;
if (Feature == "+lse")
HasLSE = true;
+if (Feature == "+ls64")
+ HasLS64 = true;
}
setDataLayout();
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index a70abb7bfd90..bd576680077e 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -36,6 +36,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasFP16FML;
bool HasMTE;
bool HasTME;
+ bool HasLS64;
bool HasMatMul;
bool HasSVE2;
bool HasSVE2AES;
@@ -81,6 +82,8 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
MacroBuilder &Builder) const;
void getTargetDefinesARMV86A(const LangOptions &Opts,
MacroBuilder &Builder) const;
+ void getTargetDefinesARMV87A(const LangOptions &Opts,
+ MacroBuilder &Builder) const;
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 13e4cac292d0..a5e632fd8cdb 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -79,9 +79,10 @@ static bool DecodeAArch64Features(const Driver &D, StringRef
text,
else
return false;
-// +sve implies +f32mm if the base architecture is v8.6A
+// +sve implies +f32mm if the base architecture is v8.6A or v8.7A
// it isn't the case in general that sve implies both f64mm and f32mm
-if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A) && Feature == "sve")
+if ((ArchKind == llvm::AArch64::ArchKind::ARMV8_6A ||
+ ArchKind == llvm::AArch64::ArchKind::ARMV8_7A) && Feature ==
[clang] c5046eb - [ARM] Adding v8.7-A command-line support for the ARM target
Author: Lucas Prates
Date: 2020-12-17T13:48:54Z
New Revision: c5046ebdf6e4be9300677c538ecaa61648c31248
URL:
https://github.com/llvm/llvm-project/commit/c5046ebdf6e4be9300677c538ecaa61648c31248
DIFF:
https://github.com/llvm/llvm-project/commit/c5046ebdf6e4be9300677c538ecaa61648c31248.diff
LOG: [ARM] Adding v8.7-A command-line support for the ARM target
This extends the command-line support for the 'armv8.7-a' architecture
name to the ARM target.
Based on a patch written by Momchil Velikov.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D93231
Added:
Modified:
clang/lib/Basic/Targets/ARM.cpp
clang/test/Driver/arm-cortex-cpus.c
clang/test/Preprocessor/arm-target-features.c
llvm/include/llvm/ADT/Triple.h
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Support/Triple.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 21cfe0107bbb..a2c96ad12a76 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -208,6 +208,8 @@ StringRef ARMTargetInfo::getCPUAttr() const {
return "8_5A";
case llvm::ARM::ArchKind::ARMV8_6A:
return "8_6A";
+ case llvm::ARM::ArchKind::ARMV8_7A:
+return "8_7A";
case llvm::ARM::ArchKind::ARMV8MBaseline:
return "8M_BASE";
case llvm::ARM::ArchKind::ARMV8MMainline:
diff --git a/clang/test/Driver/arm-cortex-cpus.c
b/clang/test/Driver/arm-cortex-cpus.c
index a312ccfda5a1..f1ca801c4ddb 100644
--- a/clang/test/Driver/arm-cortex-cpus.c
+++ b/clang/test/Driver/arm-cortex-cpus.c
@@ -352,6 +352,23 @@
// RUN: %clang -target arm -march=armebv8.6-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V86A %s
// CHECK-BE-V86A: "-cc1"{{.*}} "-triple" "armebv8.6{{.*}}" "-target-cpu"
"generic"
+// RUN: %clang -target armv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7-a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V87A %s
+// RUN: %clang -target armv8.7a -mlittle-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -march=armv8.7a -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V87A %s
+// RUN: %clang -target arm -mlittle-endian -march=armv8.7-a -mlittle-endian
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-V87A %s
+// CHECK-V87A: "-cc1"{{.*}} "-triple" "armv8.7{{.*}}" "-target-cpu" "generic"
+
+// RUN: %clang -target armebv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armv8.7a -mbig-endian -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armeb -march=armebv8.7a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target armeb -march=armebv8.7-a -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target arm -march=armebv8.7a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V87A %s
+// RUN: %clang -target arm -march=armebv8.7-a -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-V87A %s
+// CHECK-BE-V87A: "-cc1"{{.*}} "-triple" "armebv8.7{{.*}}" "-target-cpu"
"generic"
+
// Once we have CPUs with optional v8.2-A FP16, we will need a way to turn it
// on and off. Cortex-A53 is a placeholder for now.
// RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1
| FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
diff --git a/clang/test/Preprocessor/arm-target-features.c
b/clang/test/Preprocessor/arm-target-features.c
index 5eaffa1c372c..9f375162e6ab 100644
--- a/clang/test/Preprocessor/arm-target-features.c
+++ b/clang/test/Preprocessor/arm-target-features.c
@@ -849,6 +849,11 @@
// CHECK-V86A: #define __ARM_ARCH_8_6A__ 1
// CHECK-V86A: #define __ARM_ARCH_PROFILE 'A'
+// RUN: %clang -target armv8.7a-none-none-eabi -x c -E -dM %s -o - | FileCheck
-match-full-lines --check-prefix=CHECK-V87A %s
+// CHECK-V87A: #define __ARM_ARCH 8
+// CHECK-V87A: #define __ARM_ARCH_8_7A__ 1
+// CHECK-V87A: #define __ARM_ARCH_PROFILE 'A'
+
// RUN: %clang -target arm-none-none-eabi -march=armv7-m -mfpu=softvfp -x c -E
-dM %s -o - | FileCheck --check-prefix=CHECK-SOFTVFP %s
// CHECK-SOFTVFP-NOT: #define __ARM_FP 0x
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index 13a35857512a..6e2957f3c32b 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -104,6 +104,7 @@ class Triple {
enum SubArchType {
NoSubArch,
+
[clang] c2c2cc1 - [ARM][AArch64] Adding Neoverse V1 CPU support
Author: Lucas Prates
Date: 2020-11-09T13:15:40Z
New Revision: c2c2cc13601374f987cb03dfc8ef841c64b14024
URL:
https://github.com/llvm/llvm-project/commit/c2c2cc13601374f987cb03dfc8ef841c64b14024
DIFF:
https://github.com/llvm/llvm-project/commit/c2c2cc13601374f987cb03dfc8ef841c64b14024.diff
LOG: [ARM][AArch64] Adding Neoverse V1 CPU support
Add support for the Neoverse V1 CPU to the ARM and AArch64 backends.
This is based on patches from Mark Murray and Victor Campos.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D90765
Added:
Modified:
clang/test/Driver/aarch64-cpus.c
clang/test/Driver/arm-cortex-cpus.c
llvm/include/llvm/MC/SubtargetFeature.h
llvm/include/llvm/Support/AArch64TargetParser.def
llvm/include/llvm/Support/ARMTargetParser.def
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMSubtarget.cpp
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/test/CodeGen/AArch64/cpus.ll
llvm/unittests/Support/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-cpus.c
b/clang/test/Driver/aarch64-cpus.c
index 9cdf346148c3..139746823660 100644
--- a/clang/test/Driver/aarch64-cpus.c
+++ b/clang/test/Driver/aarch64-cpus.c
@@ -177,6 +177,8 @@
// CORTEXX1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x1"
// RUN: %clang -target aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXA78 %s
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
+// RUN: %clang -target aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck
-check-prefix=NEOVERSE-V1 %s
+// NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu"
"neoverse-v1"
// RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck
-check-prefix=CORTEXR82 %s
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
diff --git a/clang/test/Driver/arm-cortex-cpus.c
b/clang/test/Driver/arm-cortex-cpus.c
index 4481ba58fa64..5df872358a7a 100644
--- a/clang/test/Driver/arm-cortex-cpus.c
+++ b/clang/test/Driver/arm-cortex-cpus.c
@@ -840,6 +840,22 @@
// CHECK-CORTEX-A76AE-SOFT: "-target-feature" "+soft-float"
// CHECK-CORTEX-A76AE-SOFT: "-target-feature" "+soft-float-abi"
+// RUN: %clang -target arm -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CPUV84A %s
+// RUN: %clang -target arm -mcpu=neoverse-v1 -mlittle-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV84A %s
+// CHECK-CPUV84A: "-cc1"{{.*}} "-triple" "armv8.4a-{{.*}}
+
+// RUN: %clang -target armeb -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-BE-CPUV84A %s
+// RUN: %clang -target arm -mcpu=neoverse-v1 -mbig-endian -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-CPUV84A %s
+// CHECK-BE-CPUV84A: "-cc1"{{.*}} "-triple" "armebv8.4a-{{.*}}
+
+// RUN: %clang -target arm -mcpu=neoverse-v1 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CPUV84A-THUMB %s
+// RUN: %clang -target arm -mcpu=neoverse-v1 -mlittle-endian -mthumb -### -c
%s 2>&1 | FileCheck -check-prefix=CHECK-CPUV84A-THUMB %s
+// CHECK-CPUV84A-THUMB: "-cc1"{{.*}} "-triple" "thumbv8.4a-{{.*}}
+
+// RUN: %clang -target armeb -mcpu=neoverse-v1 -mthumb -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-BE-CPUV84A-THUMB %s
+// RUN: %clang -target arm -mcpu=neoverse-v1 -mbig-endian -mthumb -### -c %s
2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV84A-THUMB %s
+// CHECK-BE-CPUV84A-THUMB: "-cc1"{{.*}} "-triple" "thumbebv8.4a-{{.*}}
+
// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-x1 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-CORTEX-X1 %s
// RUN: %clang -target armv8a-arm-none-eabi -mcpu=cortex-x1
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck
-check-prefix=CHECK-CORTEX-X1-MFPU %s
// CHECK-CORTEX-X1: "-cc1"{{.*}} "-triple" "armv8.2a-{{.*}} "-target-cpu"
"cortex-x1"
diff --git a/llvm/include/llvm/MC/SubtargetFeature.h
b/llvm/include/llvm/MC/SubtargetFeature.h
index 01ea794a4bc3..cc36b25a4965 100644
--- a/llvm/include/llvm/MC/SubtargetFeature.h
+++ b/llvm/include/llvm/MC/SubtargetFeature.h
@@ -30,7 +30,7 @@ namespace llvm {
class raw_ostream;
class Triple;
-const unsigned MAX_SUBTARGET_WORDS = 3;
+const unsigned MAX_SUBTARGET_WORDS = 4;
const unsigned MAX_SUBTARGET_FEATURES = MAX_SUBTARGET_WORDS * 64;
/// Container class for subtarget features.
diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def
b/llvm/include/llvm/Support/AArch64TargetParser.def
index e6bc1a2c5ff8..cbf0d5d079dd 100644
--- a/llvm/include/llvm/Support/AArch64TargetParser.def
+++ b/llvm/include/llvm/Support/AArch64TargetParser.def
@@ -150,6 +150,10 @@ AARCH64_CPU_NAME("neoverse-n1", ARMV8_2A,
FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_DOTPROD | AArch64:
[clang] 9ea00fc - [NFC][AArch64] Use optional returns in target parser instead of 'invalid' objects
Author: Lucas Prates
Date: 2023-01-27T12:35:58Z
New Revision: 9ea00fc74c3c0032ff2d9a6774e13449a30e4549
URL:
https://github.com/llvm/llvm-project/commit/9ea00fc74c3c0032ff2d9a6774e13449a30e4549
DIFF:
https://github.com/llvm/llvm-project/commit/9ea00fc74c3c0032ff2d9a6774e13449a30e4549.diff
LOG: [NFC][AArch64] Use optional returns in target parser instead of 'invalid'
objects
This updates the parsing methods in AArch64's Target Parser to make use
of optional returns instead of "invalid" enum values, making the API's
behaviour clearer.
Reviewed By: lenary, tmatheson
Differential Revision: https://reviews.llvm.org/D142539
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/TargetParser/AArch64TargetParser.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index dfed95f0513f0..5971489ce8004 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/AArch64TargetParser.h"
#include "llvm/Support/ARMTargetParserCommon.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
#include
using namespace clang;
@@ -223,8 +224,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef
Spec, StringRef,
}
bool AArch64TargetInfo::isValidCPUName(StringRef Name) const {
- return Name == "generic" ||
- llvm::AArch64::parseCpu(Name).Arch != llvm::AArch64::INVALID;
+ return Name == "generic" || llvm::AArch64::parseCpu(Name);
}
bool AArch64TargetInfo::setCPU(const std::string &Name) {
@@ -681,19 +681,19 @@ void
AArch64TargetInfo::setFeatureEnabled(llvm::StringMap &Features,
Features[Name] = Enabled;
// If the feature is an architecture feature (like v8.2a), add all previous
// architecture versions and any dependant target features.
- const llvm::AArch64::ArchInfo &ArchInfo =
+ const std::optional ArchInfo =
llvm::AArch64::ArchInfo::findBySubArch(Name);
- if (ArchInfo == llvm::AArch64::INVALID)
+ if (!ArchInfo)
return; // Not an architecure, nothing more to do.
for (const auto *OtherArch : llvm::AArch64::ArchInfos)
-if (ArchInfo.implies(*OtherArch))
+if (ArchInfo->implies(*OtherArch))
Features[OtherArch->getSubArch()] = Enabled;
// Set any features implied by the architecture
uint64_t Extensions =
- llvm::AArch64::getDefaultExtensions("generic", ArchInfo);
+ llvm::AArch64::getDefaultExtensions("generic", *ArchInfo);
std::vector CPUFeats;
if (llvm::AArch64::getExtensionFeatures(Extensions, CPUFeats)) {
for (auto F : CPUFeats) {
@@ -949,9 +949,9 @@ bool AArch64TargetInfo::initFeatureMap(
const std::vector &FeaturesVec) const {
std::vector UpdatedFeaturesVec;
// Parse the CPU and add any implied features.
- const llvm::AArch64::ArchInfo &Arch = llvm::AArch64::parseCpu(CPU).Arch;
- if (Arch != llvm::AArch64::INVALID) {
-uint64_t Exts = llvm::AArch64::getDefaultExtensions(CPU, Arch);
+ std::optional CpuInfo = llvm::AArch64::parseCpu(CPU);
+ if (CpuInfo) {
+uint64_t Exts = llvm::AArch64::getDefaultExtensions(CPU, CpuInfo->Arch);
std::vector CPUFeats;
llvm::AArch64::getExtensionFeatures(Exts, CPUFeats);
for (auto F : CPUFeats) {
@@ -1033,13 +1033,14 @@ ParsedTargetAttr
AArch64TargetInfo::parseTargetAttr(StringRef Features) const {
FoundArch = true;
std::pair Split =
Feature.split("=").second.trim().split("+");
- const llvm::AArch64::ArchInfo &AI =
llvm::AArch64::parseArch(Split.first);
+ const std::optional AI =
+ llvm::AArch64::parseArch(Split.first);
// Parse the architecture version, adding the required features to
// Ret.Features.
- if (AI == llvm::AArch64::INVALID)
+ if (!AI)
continue;
- Ret.Features.push_back(AI.ArchFeature.str());
+ Ret.Features.push_back(AI->ArchFeature.str());
// Add any extra features, after the +
SplitAndAddFeatures(Split.second, Ret.Features);
} else if (Feature.startswith("cpu=")) {
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 2c559cc8b3b90..81b0245d57a6c 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -123,8 +123,8 @@ static bool DecodeAArch64Features(const Driver &D,
StringRef text,
static bool DecodeAArch64Mcpu(const Driver &D, StringRef Mcpu, StringRef &CPU,
std::vector &Features) {
std::pair Split = Mcpu.split("+");
+ CPU = Split.first;
const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch
[clang] 0753cf2 - [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo objects
Author: Lucas Prates
Date: 2023-01-27T12:37:18Z
New Revision: 0753cf2caca707e3957a70c9756b7f1d42fab2af
URL:
https://github.com/llvm/llvm-project/commit/0753cf2caca707e3957a70c9756b7f1d42fab2af
DIFF:
https://github.com/llvm/llvm-project/commit/0753cf2caca707e3957a70c9756b7f1d42fab2af.diff
LOG: [NFC][AArch64] Get default features directly from ArchInfo and CpuInfo
objects
This updates the AArch64's Target Parser and its uses to capture
information about default features directly from ArchInfo and CpuInfo
objects, instead of relying on an API function to access them
indirectly.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D142540
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Driver/ToolChains/Arch/AArch64.cpp
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/lib/TargetParser/AArch64TargetParser.cpp
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 5971489ce8004..fc171357bb605 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -692,10 +692,8 @@ void
AArch64TargetInfo::setFeatureEnabled(llvm::StringMap &Features,
Features[OtherArch->getSubArch()] = Enabled;
// Set any features implied by the architecture
- uint64_t Extensions =
- llvm::AArch64::getDefaultExtensions("generic", *ArchInfo);
std::vector CPUFeats;
- if (llvm::AArch64::getExtensionFeatures(Extensions, CPUFeats)) {
+ if (llvm::AArch64::getExtensionFeatures(ArchInfo->DefaultExts, CPUFeats)) {
for (auto F : CPUFeats) {
assert(F[0] == '+' && "Expected + in target feature!");
Features[F.drop_front(1)] = true;
@@ -951,7 +949,7 @@ bool AArch64TargetInfo::initFeatureMap(
// Parse the CPU and add any implied features.
std::optional CpuInfo = llvm::AArch64::parseCpu(CPU);
if (CpuInfo) {
-uint64_t Exts = llvm::AArch64::getDefaultExtensions(CPU, CpuInfo->Arch);
+uint64_t Exts = CpuInfo->getImpliedExtensions();
std::vector CPUFeats;
llvm::AArch64::getExtensionFeatures(Exts, CPUFeats);
for (auto F : CPUFeats) {
diff --git a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
index 81b0245d57a6c..4476b9f37bd9d 100644
--- a/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/AArch64.cpp
@@ -140,7 +140,7 @@ static bool DecodeAArch64Mcpu(const Driver &D, StringRef
Mcpu, StringRef &CPU,
Features.push_back(ArchInfo->ArchFeature);
-uint64_t Extension = llvm::AArch64::getDefaultExtensions(CPU, *ArchInfo);
+uint64_t Extension = CpuInfo->getImpliedExtensions();
if (!llvm::AArch64::getExtensionFeatures(Extension, Features))
return false;
}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index ea06d7da29691..b7ecd444c7eef 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -334,6 +334,10 @@ struct CpuInfo {
const ArchInfo &Arch;
uint64_t DefaultExtensions; // Default extensions for this CPU. These will be
// ORd with the architecture defaults.
+
+ uint64_t getImpliedExtensions() const {
+return DefaultExtensions | Arch.DefaultExts;
+ }
};
inline constexpr CpuInfo CpuInfos[] = {
@@ -509,7 +513,6 @@ StringRef getArchExtFeature(StringRef ArchExt);
StringRef resolveCPUAlias(StringRef CPU);
// Information by Name
-uint64_t getDefaultExtensions(StringRef CPU, const ArchInfo &AI);
void getFeatureOption(StringRef Name, std::string &Feature);
std::optional getArchForCpu(StringRef CPU);
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 840f792325cd2..f42ddf7e53eaa 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -6891,8 +6891,7 @@ bool AArch64AsmParser::parseDirectiveArch(SMLoc L) {
// Get the architecture and extension features.
std::vector AArch64Features;
AArch64Features.push_back(ArchInfo->ArchFeature);
- AArch64::getExtensionFeatures(
- AArch64::getDefaultExtensions("generic", *ArchInfo), AArch64Features);
+ AArch64::getExtensionFeatures(ArchInfo->DefaultExts, AArch64Features);
MCSubtargetInfo &STI = copySTI();
std::vector ArchFeatures(AArch64Features.begin(),
AArch64Features.end());
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp
b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 7dd0c45939b63..e2519e8212d81 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cp
[clang] 852bb68 - [NFC][AArch64] Get extension strings directly from ArchInfo in target parser
Author: Lucas Prates
Date: 2023-01-27T15:17:21Z
New Revision: 852bb68ddb2bf9c91421a6ce59a07a6f44d20641
URL:
https://github.com/llvm/llvm-project/commit/852bb68ddb2bf9c91421a6ce59a07a6f44d20641
DIFF:
https://github.com/llvm/llvm-project/commit/852bb68ddb2bf9c91421a6ce59a07a6f44d20641.diff
LOG: [NFC][AArch64] Get extension strings directly from ArchInfo in target
parser
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D142541
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/lib/TargetParser/AArch64TargetParser.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index fc171357bb60..33f9d67ef0e9 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -973,12 +973,16 @@ bool AArch64TargetInfo::initFeatureMap(
}
}
for (const auto &Feature : FeaturesVec)
-if (Feature[0] == '+') {
- std::string F;
- llvm::AArch64::getFeatureOption(Feature, F);
- UpdatedFeaturesVec.push_back(F);
-} else if (Feature[0] != '?')
- UpdatedFeaturesVec.push_back(Feature);
+if (Feature[0] != '?') {
+ std::string UpdatedFeature = Feature;
+ if (Feature[0] == '+') {
+std::optional Extension =
+ llvm::AArch64::parseArchExtension(Feature.substr(1));
+if (Extension)
+ UpdatedFeature = Extension->Feature.str();
+ }
+ UpdatedFeaturesVec.push_back(UpdatedFeature);
+}
return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec);
}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index b7ecd444c7ee..385e7d6dce05 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -513,7 +513,6 @@ StringRef getArchExtFeature(StringRef ArchExt);
StringRef resolveCPUAlias(StringRef CPU);
// Information by Name
-void getFeatureOption(StringRef Name, std::string &Feature);
std::optional getArchForCpu(StringRef CPU);
// Parser
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp
b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index e2519e8212d8..0fea5f77b868 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -25,16 +25,6 @@ static unsigned checkArchVersion(llvm::StringRef Arch) {
return 0;
}
-void AArch64::getFeatureOption(StringRef Name, std::string &Feature) {
- for (const auto &E : llvm::AArch64::Extensions) {
-if (Name == E.Name) {
- Feature = E.Feature;
- return;
-}
- }
- Feature = Name.str();
-}
-
std::optional AArch64::getArchForCpu(StringRef CPU) {
if (CPU == "generic")
return ARMV8A;
___
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[clang] 8246ace - [AArch64] Add command line support for v9.4-A's Instrumentation Extension
Author: Lucas Prates
Date: 2023-01-23T16:39:53Z
New Revision: 8246aceb90c28d27e644fe74e4ad5e2c9e9d85e1
URL:
https://github.com/llvm/llvm-project/commit/8246aceb90c28d27e644fe74e4ad5e2c9e9d85e1
DIFF:
https://github.com/llvm/llvm-project/commit/8246aceb90c28d27e644fe74e4ad5e2c9e9d85e1.diff
LOG: [AArch64] Add command line support for v9.4-A's Instrumentation Extension
This introduces command line support (`+ite`) for the v9.4-A's
Instrumentation Extension (FEAT_ITE).
Patch by Son Tuan Vu.
Reviewed By: lenary, tmatheson
Differential Revision: https://reviews.llvm.org/D141403
Added:
clang/test/Driver/aarch64-ite.c
Modified:
llvm/include/llvm/TargetParser/AArch64TargetParser.h
llvm/unittests/TargetParser/TargetParserTest.cpp
Removed:
diff --git a/clang/test/Driver/aarch64-ite.c b/clang/test/Driver/aarch64-ite.c
new file mode 100644
index 0..d77196e372930
--- /dev/null
+++ b/clang/test/Driver/aarch64-ite.c
@@ -0,0 +1,17 @@
+// Test that target feature ite is implemented and available correctly
+
+// FEAT_ITE is optional (off by default) for v8.9a/9.4a and older, and can be
enabled using +ite
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+ite %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+noite %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a %s
2>&1 | FileCheck %s --check-prefix=NOT_ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+ite %s
2>&1 | FileCheck %s --check-prefix=ENABLED
+// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+noite %s
2>&1 | FileCheck %s --check-prefix=DISABLED
+
+// FEAT_ITE is invalid before v8
+// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+ite %s 2>&1
| FileCheck %s --check-prefix=INVALID
+
+// INVALID: error: unsupported argument 'armv7-a+ite' to option '-march='
+// ENABLED: "-target-feature" "+ite"
+// NOT_ENABLED-NOT: "-target-feature" "+ite"
+// DISABLED: "-target-feature" "-ite"
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index ff6a629c8faa0..71a085f21eb2e 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -147,6 +147,7 @@ enum ArchExtKind : uint64_t {
AEK_LSE128 = 1ULL << 52, // FEAT_LSE128
AEK_SPECRES2 =1ULL << 53, // FEAT_SPECRES2
AEK_RASv2 = 1ULL << 54, // FEAT_RASv2
+ AEK_ITE = 1ULL << 55, // FEAT_ITE
};
// clang-format on
@@ -196,6 +197,7 @@ inline constexpr ExtensionInfo Extensions[] = {
{"frintts", AArch64::AEK_NONE, {}, {}, FEAT_FRINTTS, "+fptoint", 250},
{"hbc", AArch64::AEK_HBC, "+hbc", "-hbc", FEAT_MAX, "", 0},
{"i8mm", AArch64::AEK_I8MM, "+i8mm", "-i8mm", FEAT_I8MM, "+i8mm", 270},
+{"ite", AArch64::AEK_ITE, "+ite", "-ite", FEAT_MAX, "", 0},
{"jscvt", AArch64::AEK_NONE, {}, {}, FEAT_JSCVT,
"+fp-armv8,+neon,+jsconv", 210},
{"ls64_accdata", AArch64::AEK_NONE, {}, {}, FEAT_LS64_ACCDATA, "+ls64",
540},
{"ls64_v", AArch64::AEK_NONE, {}, {}, FEAT_LS64_V, "", 530},
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp
b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 39de9e25c8cca..92756972fcd49 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -1553,6 +1553,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16, AArch64::AEK_CSSC,
AArch64::AEK_RCPC3, AArch64::AEK_THE, AArch64::AEK_D128,
AArch64::AEK_LSE128, AArch64::AEK_SPECRES2, AArch64::AEK_RASv2,
+ AArch64::AEK_ITE,
};
std::vector Features;
@@ -1624,6 +1625,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+d128"));
EXPECT_TRUE(llvm::is_contained(Features, "+lse128"));
EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
+ EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
// Assuming we listed every extension above, this should produce the same
// result. (note that AEK_NONE doesn't have a name so it won't be in the
___
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[clang] 5f6813b - [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver
Author: Lucas Prates
Date: 2023-01-23T16:40:48Z
New Revision: 5f6813beed85a0d9355c117e7638feee26e80b3d
URL:
https://github.com/llvm/llvm-project/commit/5f6813beed85a0d9355c117e7638feee26e80b3d
DIFF:
https://github.com/llvm/llvm-project/commit/5f6813beed85a0d9355c117e7638feee26e80b3d.diff
LOG: [AArch64][Clang] Adjust default features for v8.9-A/v9.4-A in clang driver
Update the clang driver to include the following features as default for
the v8.9-A/v9.4-A architecture versions:
* FEAT_SPECRES2
* FEAT_CSSC
* FEAT_RASv2
Patch by Sam Elliott.
Reviewed By: lenary, tmatheson
Differential Revision: https://reviews.llvm.org/D141404
Added:
Modified:
clang/test/Driver/aarch64-cssc.c
llvm/include/llvm/TargetParser/AArch64TargetParser.h
Removed:
diff --git a/clang/test/Driver/aarch64-cssc.c
b/clang/test/Driver/aarch64-cssc.c
index 0ecda98d6950..8ffe92eac8fd 100644
--- a/clang/test/Driver/aarch64-cssc.c
+++ b/clang/test/Driver/aarch64-cssc.c
@@ -1,15 +1,17 @@
// Test that target feature cssc is implemented and available correctly
-// RUN: %clang -### -target aarch64-none-none-eabi %s
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a%s
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.8-a+cssc %s
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+nocssc %s
2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a%s
2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.3-a+cssc %s
2>&1 | FileCheck %s
-// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+nocssc %s
2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a
onwards.
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
%s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv8.7-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv8.9-a%s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv8.9-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv9.2-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv9.4-a%s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
+// RUN: %clang -S -o - -emit-llvm -target aarch64-none-none-eabi
-march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
-// CHECK: "-target-feature" "+cssc"
-// NO_CSSC: "-target-feature" "-cssc"
-// ABSENT_CSSC-NOT: "-target-feature" "+cssc"
-// ABSENT_CSSC-NOT: "-target-feature" "-cssc"
+// CHECK: "target-features"="{{.*}},+cssc
+// NO_CSSC: "target-features"="{{.*}},-cssc
+// ABSENT_CSSC-NOT: "target-features"="{{.*}},+cssc
+// ABSENT_CSSC-NOT: "target-features"="{{.*}},-cssc
+void test() {}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index 71a085f21eb2..4df96dcf7554 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -315,12 +315,12 @@ constexpr unsigned BaseNoCrypto = ARMV8_5A.DefaultExts ^
AArch64::AEK_CRYPTO; //
inline constexpr ArchInfo ARMV8_6A = { VersionTuple{8, 6}, AProfile,
"armv8.6-a", "+v8.6a", (BaseNoCrypto | AArch64::AEK_SM4 | AArch64::AEK_SHA3 |
AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)};
inline constexpr ArchInfo ARMV8_7A = { VersionTuple{8, 7}, AProfile,
"armv8.7-a", "+v8.7a", (ARMV8_6A.DefaultExts)};
inline constexpr ArchInfo ARMV8_8A = { VersionTuple{8, 8}, AProfile,
"armv8.8-a", "+v8.8a", (ARMV8_7A.DefaultExts | AArch64::AEK_MOPS |
AArch64::AEK_HBC)};
-inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile,
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts)};
+inline constexpr ArchInfo ARMV8_9A = { VersionTuple{8, 9}, AProfile,
"armv8.9-a", "+v8.9a", (ARMV8_8A.DefaultExts | AArch64::AEK_SPECRES2 |
AArch64::AEK_CSSC | AArch64::AEK_RASv2)};
inline constexpr ArchInfo ARMV9A= { Versi
[clang] 6119053 - [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Author: Lucas Prates
Date: 2022-06-13T10:21:06+01:00
New Revision: 6119053dab67129eb1700dbf36db3524dd3e421f
URL:
https://github.com/llvm/llvm-project/commit/6119053dab67129eb1700dbf36db3524dd3e421f
DIFF:
https://github.com/llvm/llvm-project/commit/6119053dab67129eb1700dbf36db3524dd3e421f.diff
LOG: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Currently the a AAPCS compliant frame record is not always created for
functions when it should. Although a consistent frame record might not
be required in some cases, there are still scenarios where applications
may want to make use of the call hierarchy made available trough it.
In order to enable the use of AAPCS compliant frame records whilst keep
backwards compatibility, this patch introduces a new command-line option
(`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends.
The option allows users to explicitly select when to use it, and is also
useful to ensure the extra overhead introduced by the frame records is
only introduced when necessary, in particular for Thumb targets.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D125094
Added:
llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
llvm/test/CodeGen/ARM/frame-chain.ll
llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
llvm/test/CodeGen/Thumb/frame-chain.ll
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallingConv.td
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMFrameLowering.h
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/test/CodeGen/Thumb/frame-access.ll
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 002cd6cc8cb17..a311781181561 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3467,7 +3467,9 @@ defm aapcs_bitfield_width : BoolOption<"f",
"aapcs-bitfield-width",
BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement
stating that"
" volatile bit-field width is dictated by the field container
type. (ARM only).">>,
Group;
-
+def mframe_chain : Joined<["-"], "mframe-chain=">,
+ Group, Values<"none,aapcs,aapcs+leaf">,
+ HelpText<"Select the frame chain model used to emit frame records (Arm
only).">;
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64/x86 only)">;
def mfix_cmse_cve_2021_35465 : Flag<["-"], "mfix-cmse-cve-2021-35465">,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index dc6b35e39cfdd..b79d1f00ea48b 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -718,6 +718,15 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
}
+ // Propagate frame-chain model selection
+ if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) {
+StringRef FrameChainOption = A->getValue();
+if (FrameChainOption.startswith("aapcs"))
+ Features.push_back("+aapcs-frame-chain");
+if (FrameChainOption == "aapcs+leaf")
+ Features.push_back("+aapcs-frame-chain-leaf");
+ }
+
// CMSE: Check for target 8M (for -mcmse to be applicable) is performed
later.
if (Args.getLastArg(options::OPT_mcmse))
Features.push_back("+8msecext");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index e8970b916a5f0..48559a89a30a0 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -546,6 +546,16 @@ def FeatureFixCortexA57AES1742098 :
SubtargetFeature<"fix-cortex-a57-aes-1742098
"FixCortexA57AES1742098", "true",
"Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
+def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
+ "CreateAAPCSFrameChain", "true",
+ "Create an AAPCS compliant frame
chain">;
+
+def FeatureAAPCSFrameChainLeaf : SubtargetFeature<"aapcs-frame-chain-leaf",
+ "CreateAAPCSFrameChainLeaf",
"true",
+ "Create an AAPCS compliant
frame chain "
+ "for leaf functions",
+ [FeatureAAPCSFrameChain]>;
+
//===--===//
// ARM architecture class
//
diff --git a/llvm/lib/Targe
[clang] 33b9ad6 - Revert "[ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records"
Author: Lucas Prates
Date: 2022-06-13T11:00:49+01:00
New Revision: 33b9ad647e9142c8e48f51c3067bf2340b8416c3
URL:
https://github.com/llvm/llvm-project/commit/33b9ad647e9142c8e48f51c3067bf2340b8416c3
DIFF:
https://github.com/llvm/llvm-project/commit/33b9ad647e9142c8e48f51c3067bf2340b8416c3.diff
LOG: Revert "[ARM][Thumb] Command-line option to ensure AAPCS compliant Frame
Records"
Reverting change due to test failure.
This reverts commit 6119053dab67129eb1700dbf36db3524dd3e421f.
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallingConv.td
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMFrameLowering.h
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/test/CodeGen/Thumb/frame-access.ll
Removed:
llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
llvm/test/CodeGen/ARM/frame-chain.ll
llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
llvm/test/CodeGen/Thumb/frame-chain.ll
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index a311781181561..002cd6cc8cb17 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3467,9 +3467,7 @@ defm aapcs_bitfield_width : BoolOption<"f",
"aapcs-bitfield-width",
BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement
stating that"
" volatile bit-field width is dictated by the field container
type. (ARM only).">>,
Group;
-def mframe_chain : Joined<["-"], "mframe-chain=">,
- Group, Values<"none,aapcs,aapcs+leaf">,
- HelpText<"Select the frame chain model used to emit frame records (Arm
only).">;
+
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64/x86 only)">;
def mfix_cmse_cve_2021_35465 : Flag<["-"], "mfix-cmse-cve-2021-35465">,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index b79d1f00ea48b..dc6b35e39cfdd 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -718,15 +718,6 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
}
- // Propagate frame-chain model selection
- if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) {
-StringRef FrameChainOption = A->getValue();
-if (FrameChainOption.startswith("aapcs"))
- Features.push_back("+aapcs-frame-chain");
-if (FrameChainOption == "aapcs+leaf")
- Features.push_back("+aapcs-frame-chain-leaf");
- }
-
// CMSE: Check for target 8M (for -mcmse to be applicable) is performed
later.
if (Args.getLastArg(options::OPT_mcmse))
Features.push_back("+8msecext");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 48559a89a30a0..e8970b916a5f0 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -546,16 +546,6 @@ def FeatureFixCortexA57AES1742098 :
SubtargetFeature<"fix-cortex-a57-aes-1742098
"FixCortexA57AES1742098", "true",
"Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
-def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
- "CreateAAPCSFrameChain", "true",
- "Create an AAPCS compliant frame
chain">;
-
-def FeatureAAPCSFrameChainLeaf : SubtargetFeature<"aapcs-frame-chain-leaf",
- "CreateAAPCSFrameChainLeaf",
"true",
- "Create an AAPCS compliant
frame chain "
- "for leaf functions",
- [FeatureAAPCSFrameChain]>;
-
//===--===//
// ARM architecture class
//
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 1d0e743b94dbf..cae72e465c7bf 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -63,8 +63,12 @@ const MCPhysReg*
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const ARMSubtarget &STI = MF->getSubtarget();
bool UseSplitPush = STI.splitFramePushPop(*MF);
- const Function &F = MF->getFunction();
+ const MCPhysReg *RegList =
+ STI.isTargetDarwin()
+ ? CSR_iOS_SaveList
+ : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
+ const Function &F = MF->getFunctio
[clang] 7625e01 - [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Author: Lucas Prates
Date: 2022-06-14T13:37:51+01:00
New Revision: 7625e01d661644a560884057755d48a0da8b77b4
URL:
https://github.com/llvm/llvm-project/commit/7625e01d661644a560884057755d48a0da8b77b4
DIFF:
https://github.com/llvm/llvm-project/commit/7625e01d661644a560884057755d48a0da8b77b4.diff
LOG: [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Currently the a AAPCS compliant frame record is not always created for
functions when it should. Although a consistent frame record might not
be required in some cases, there are still scenarios where applications
may want to make use of the call hierarchy made available trough it.
In order to enable the use of AAPCS compliant frame records whilst keep
backwards compatibility, this patch introduces a new command-line option
(`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends.
The option allows users to explicitly select when to use it, and is also
useful to ensure the extra overhead introduced by the frame records is
only introduced when necessary, in particular for Thumb targets.
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D125094
Added:
llvm/test/CodeGen/ARM/frame-chain-reserved-fp.ll
llvm/test/CodeGen/ARM/frame-chain.ll
llvm/test/CodeGen/Thumb/frame-chain-reserved-fp.ll
llvm/test/CodeGen/Thumb/frame-chain.ll
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallingConv.td
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMFrameLowering.h
llvm/lib/Target/ARM/ARMMachineFunctionInfo.h
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/test/CodeGen/Thumb/frame-access.ll
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 5fa681f53819..b40cb1167388 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3478,7 +3478,9 @@ defm aapcs_bitfield_width : BoolOption<"f",
"aapcs-bitfield-width",
BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement
stating that"
" volatile bit-field width is dictated by the field container
type. (ARM only).">>,
Group;
-
+def mframe_chain : Joined<["-"], "mframe-chain=">,
+ Group, Values<"none,aapcs,aapcs+leaf">,
+ HelpText<"Select the frame chain model used to emit frame records (Arm
only).">;
def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group,
HelpText<"Generate code which only uses the general purpose registers
(AArch64/x86 only)">;
def mfix_cmse_cve_2021_35465 : Flag<["-"], "mfix-cmse-cve-2021-35465">,
diff --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index dc6b35e39cfd..b79d1f00ea48 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -718,6 +718,15 @@ void arm::getARMTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
}
}
+ // Propagate frame-chain model selection
+ if (Arg *A = Args.getLastArg(options::OPT_mframe_chain)) {
+StringRef FrameChainOption = A->getValue();
+if (FrameChainOption.startswith("aapcs"))
+ Features.push_back("+aapcs-frame-chain");
+if (FrameChainOption == "aapcs+leaf")
+ Features.push_back("+aapcs-frame-chain-leaf");
+ }
+
// CMSE: Check for target 8M (for -mcmse to be applicable) is performed
later.
if (Args.getLastArg(options::OPT_mcmse))
Features.push_back("+8msecext");
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index e8970b916a5f..48559a89a30a 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -546,6 +546,16 @@ def FeatureFixCortexA57AES1742098 :
SubtargetFeature<"fix-cortex-a57-aes-1742098
"FixCortexA57AES1742098", "true",
"Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
+def FeatureAAPCSFrameChain : SubtargetFeature<"aapcs-frame-chain",
+ "CreateAAPCSFrameChain", "true",
+ "Create an AAPCS compliant frame
chain">;
+
+def FeatureAAPCSFrameChainLeaf : SubtargetFeature<"aapcs-frame-chain-leaf",
+ "CreateAAPCSFrameChainLeaf",
"true",
+ "Create an AAPCS compliant
frame chain "
+ "for leaf functions",
+ [FeatureAAPCSFrameChain]>;
+
//===--===//
// ARM architecture class
//
diff --git a/llvm/lib/Target/ARM/
[clang] 2b7ac62 - [AArch64][RCPC3] Add Neon intrinsics for LDAP1 and STL1
Author: Lucas Prates
Date: 2023-07-07T12:31:55+01:00
New Revision: 2b7ac6260627654def127598e0099938869f765a
URL:
https://github.com/llvm/llvm-project/commit/2b7ac6260627654def127598e0099938869f765a
DIFF:
https://github.com/llvm/llvm-project/commit/2b7ac6260627654def127598e0099938869f765a.diff
LOG: [AArch64][RCPC3] Add Neon intrinsics for LDAP1 and STL1
This adds new intrisics to support the LDAP1 and STL1 Advanced SIMD
(Neon) instructions introduced as part of FEAT_LRCPC3.
The new intrinsics `vldap1(q)_lane`/`vstl1(q)_lane` generate IR code
similar to the existing `vld1(q)_lane/st1(q)_lane` ones, but capturing
the difference in the atomic release/acquire memory model.
The LLVM code generation changes to ensure that this instruction pair
is lowered to the correct LDAP1/STL1 instructions will be covered in a
separate commit.
Based on a patch by Sam Elliott.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D153128
Added:
clang/test/CodeGen/aarch64-neon-ldst-one-rcpc3.c
Modified:
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/utils/TableGen/NeonEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 94dfe80acc3587..ba3764d2f778e8 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -2086,3 +2086,9 @@ let ArchGuard = "defined(__aarch64__)", TargetGuard =
"bf16" in {
"csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", "bQb">;
}
}
+
+// v8.9a/v9.4a LRCPC3 intrinsics
+let ArchGuard = "defined(__aarch64__)", TargetGuard = "rcpc3" in {
+ def VLDAP1_LANE : WInst<"vldap1_lane", ".(c*!).I", "QUlQlUlldQdPlQPl">;
+ def VSTL1_LANE : WInst<"vstl1_lane", "v*(.!)I", "QUlQlUlldQdPlQPl">;
+}
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 3d451bd7d140f2..8b503ef6b9c75e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -6790,6 +6790,21 @@ static const std::pair
NEONEquivalentIntrinsicMap[] = {
{ NEON::BI__builtin_neon_vuzpq_f16, NEON::BI__builtin_neon_vuzpq_v, },
{ NEON::BI__builtin_neon_vzip_f16, NEON::BI__builtin_neon_vzip_v, },
{ NEON::BI__builtin_neon_vzipq_f16, NEON::BI__builtin_neon_vzipq_v, },
+ // The mangling rules cause us to have one ID for each type for
vldap1(q)_lane
+ // and vstl1(q)_lane, but codegen is equivalent for all of them. Choose an
+ // arbitrary one to be handled as tha canonical variation.
+ { NEON::BI__builtin_neon_vldap1_lane_u64,
NEON::BI__builtin_neon_vldap1_lane_s64 },
+ { NEON::BI__builtin_neon_vldap1_lane_f64,
NEON::BI__builtin_neon_vldap1_lane_s64 },
+ { NEON::BI__builtin_neon_vldap1_lane_p64,
NEON::BI__builtin_neon_vldap1_lane_s64 },
+ { NEON::BI__builtin_neon_vldap1q_lane_u64,
NEON::BI__builtin_neon_vldap1q_lane_s64 },
+ { NEON::BI__builtin_neon_vldap1q_lane_f64,
NEON::BI__builtin_neon_vldap1q_lane_s64 },
+ { NEON::BI__builtin_neon_vldap1q_lane_p64,
NEON::BI__builtin_neon_vldap1q_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1_lane_u64,
NEON::BI__builtin_neon_vstl1_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1_lane_f64,
NEON::BI__builtin_neon_vstl1_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1_lane_p64,
NEON::BI__builtin_neon_vstl1_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1q_lane_u64,
NEON::BI__builtin_neon_vstl1q_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1q_lane_f64,
NEON::BI__builtin_neon_vstl1q_lane_s64 },
+ { NEON::BI__builtin_neon_vstl1q_lane_p64,
NEON::BI__builtin_neon_vstl1q_lane_s64 },
};
#undef NEONMAP0
@@ -10596,6 +10611,10 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
case NEON::BI__builtin_neon_vst1q_v:
case NEON::BI__builtin_neon_vst1_lane_v:
case NEON::BI__builtin_neon_vst1q_lane_v:
+ case NEON::BI__builtin_neon_vldap1_lane_s64:
+ case NEON::BI__builtin_neon_vldap1q_lane_s64:
+ case NEON::BI__builtin_neon_vstl1_lane_s64:
+ case NEON::BI__builtin_neon_vstl1q_lane_s64:
// Get the alignment for the argument in addition to the value;
// we'll use it later.
PtrOp0 = EmitPointerWithAlignment(E->getArg(0));
@@ -12194,6 +12213,17 @@ Value
*CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
PtrOp0.getAlignment());
return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vld1_lane");
}
+ case NEON::BI__builtin_neon_vldap1_lane_s64:
+ case NEON::BI__builtin_neon_vldap1q_lane_s64: {
+Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
+Ty = llvm::PointerType::getUnqual(VTy->getElementType());
+Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
+llvm::LoadInst *LI = Builder.CreateAlignedLoad(
+VTy->getElementType(), Ops[0], PtrOp0.getAlignment());
+LI->setAtomic(llvm::AtomicOrdering::Acquire);
+Ops[0] = LI;
[clang] f1d7a55 - [Clang][AArch64] Implement ACLE feature macro for FEAT_LRCPC3
Author: Lucas Prates
Date: 2023-07-07T12:33:34+01:00
New Revision: f1d7a55a4e0627302881957d225342d5b1531675
URL:
https://github.com/llvm/llvm-project/commit/f1d7a55a4e0627302881957d225342d5b1531675
DIFF:
https://github.com/llvm/llvm-project/commit/f1d7a55a4e0627302881957d225342d5b1531675.diff
LOG: [Clang][AArch64] Implement ACLE feature macro for FEAT_LRCPC3
This implements the new value for the `__ARM_FEATURE_RCPC` feature
macro, which was introduced to the ACLE to indicate the availability of
FEAT_LRCPC3.
More details can be found on:
https://github.com/ARM-software/acle/blob/main/main/acle.md#rcpc
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D153130
Added:
Modified:
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/Basic/Targets/AArch64.h
clang/test/Preprocessor/aarch64-target-features.c
Removed:
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 6de1728b1e50cc..ed0246d6faee16 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -415,7 +415,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (HasCRC)
Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
- if (HasRCPC)
+ if (HasRCPC3)
+Builder.defineMacro("__ARM_FEATURE_RCPC", "3");
+ else if (HasRCPC)
Builder.defineMacro("__ARM_FEATURE_RCPC", "1");
if (HasFMV)
@@ -671,6 +673,7 @@ bool AArch64TargetInfo::hasFeature(StringRef Feature) const
{
.Case("bti", HasBTI)
.Cases("ls64", "ls64_v", "ls64_accdata", HasLS64)
.Case("wfxt", HasWFxT)
+ .Case("rcpc3", HasRCPC3)
.Default(false);
}
@@ -928,6 +931,8 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasD128 = true;
if (Feature == "+gcs")
HasGCS = true;
+if (Feature == "+rcpc3")
+ HasRCPC3 = true;
}
// Check features that are manually disabled by command line options.
diff --git a/clang/lib/Basic/Targets/AArch64.h
b/clang/lib/Basic/Targets/AArch64.h
index cce80e10f2bb1e..4304693e473dee 100644
--- a/clang/lib/Basic/Targets/AArch64.h
+++ b/clang/lib/Basic/Targets/AArch64.h
@@ -82,6 +82,7 @@ class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public
TargetInfo {
bool HasNoSVE = false;
bool HasFMV = true;
bool HasGCS = false;
+ bool HasRCPC3 = false;
const llvm::AArch64::ArchInfo *ArchInfo = &llvm::AArch64::ARMV8A;
diff --git a/clang/test/Preprocessor/aarch64-target-features.c
b/clang/test/Preprocessor/aarch64-target-features.c
index baf3fda73d591e..7f2b353ab18c0d 100644
--- a/clang/test/Preprocessor/aarch64-target-features.c
+++ b/clang/test/Preprocessor/aarch64-target-features.c
@@ -27,6 +27,7 @@
// CHECK: __ARM_FEATURE_LDREX 0xF
// CHECK: __ARM_FEATURE_NUMERIC_MAXMIN 1
// CHECK-NOT: __ARM_FEATURE_RCPC 1
+// CHECK-NOT: __ARM_FEATURE_RCPC 3
// CHECK-NOT: __ARM_FEATURE_SHA2 1
// CHECK-NOT: __ARM_FEATURE_SHA3 1
// CHECK-NOT: __ARM_FEATURE_SHA512 1
@@ -612,3 +613,6 @@
// RUN: %clang --target=aarch64 -march=armv8.2-a+rcpc -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-RCPC %s
// CHECK-RCPC: __ARM_FEATURE_RCPC 1
+
+// RUN: %clang --target=aarch64 -march=armv8.2-a+rcpc3 -x c -E -dM %s -o - |
FileCheck --check-prefix=CHECK-RCPC3 %s
+// CHECK-RCPC3: __ARM_FEATURE_RCPC 3
___
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[clang] e6cb4b6 - [Clang][CodeGen] Fixing mismatch between memory layout and const expressions for oversized bitfields
Author: Lucas Prates
Date: 2020-04-02T11:55:20+01:00
New Revision: e6cb4b659af9f9c1a4c179093b187e7ad7cc5770
URL:
https://github.com/llvm/llvm-project/commit/e6cb4b659af9f9c1a4c179093b187e7ad7cc5770
DIFF:
https://github.com/llvm/llvm-project/commit/e6cb4b659af9f9c1a4c179093b187e7ad7cc5770.diff
LOG: [Clang][CodeGen] Fixing mismatch between memory layout and const
expressions for oversized bitfields
Summary:
The construction of constants for structs/unions was conflicting the
expected memory layout for over-sized bit-fields. When building the
necessary bits for those fields, clang was ignoring the size information
computed for the struct/union memory layout and using the original data
from the AST's FieldDecl information. This caused an issue in big-endian
targets, where the field's contant was incorrectly misplaced due to
endian calculations.
This patch aims to separate the constant value from the necessary
padding bits, using the proper size information for each one of them.
With this, the layout of constants for over-sized bit-fields matches the
ABI requirements.
Reviewers: rsmith, eli.friedman, efriedma
Reviewed By: efriedma
Subscribers: efriedma, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77048
Added:
Modified:
clang/lib/CodeGen/CGExprConstant.cpp
clang/test/CodeGenCXX/bitfield-layout.cpp
Removed:
diff --git a/clang/lib/CodeGen/CGExprConstant.cpp
b/clang/lib/CodeGen/CGExprConstant.cpp
index e17c1c5f7ac4..da5d778a4922 100644
--- a/clang/lib/CodeGen/CGExprConstant.cpp
+++ b/clang/lib/CodeGen/CGExprConstant.cpp
@@ -589,19 +589,21 @@ bool ConstStructBuilder::AppendBytes(CharUnits
FieldOffsetInChars,
bool ConstStructBuilder::AppendBitField(
const FieldDecl *Field, uint64_t FieldOffset, llvm::ConstantInt *CI,
bool AllowOverwrite) {
- uint64_t FieldSize = Field->getBitWidthValue(CGM.getContext());
+ const CGRecordLayout &RL =
+ CGM.getTypes().getCGRecordLayout(Field->getParent());
+ const CGBitFieldInfo &Info = RL.getBitFieldInfo(Field);
llvm::APInt FieldValue = CI->getValue();
// Promote the size of FieldValue if necessary
// FIXME: This should never occur, but currently it can because initializer
// constants are cast to bool, and because clang is not enforcing bitfield
// width limits.
- if (FieldSize > FieldValue.getBitWidth())
-FieldValue = FieldValue.zext(FieldSize);
+ if (Info.Size > FieldValue.getBitWidth())
+FieldValue = FieldValue.zext(Info.Size);
// Truncate the size of FieldValue to the bit field size.
- if (FieldSize < FieldValue.getBitWidth())
-FieldValue = FieldValue.trunc(FieldSize);
+ if (Info.Size < FieldValue.getBitWidth())
+FieldValue = FieldValue.trunc(Info.Size);
return Builder.addBits(FieldValue,
CGM.getContext().toBits(StartOffset) + FieldOffset,
diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp
b/clang/test/CodeGenCXX/bitfield-layout.cpp
index 46f4a1de..d8f8c87eb28b 100644
--- a/clang/test/CodeGenCXX/bitfield-layout.cpp
+++ b/clang/test/CodeGenCXX/bitfield-layout.cpp
@@ -1,11 +1,14 @@
-// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck -check-prefix CHECK-LP64 %s
-// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck -check-prefix CHECK-LP32 %s
+// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck -check-prefix=CHECK-LP64 -check-prefix=CHECK %s
+// RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 |
FileCheck -check-prefix CHECK-LP32 -check-prefix=CHECK %s
+// RUN: %clang_cc1 %s -triple=aarch64_be-none-eabi -emit-llvm -o - -O3 |
FileCheck -check-prefix CHECK-A64BE -check-prefix=CHECK %s
+// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 |
FileCheck -check-prefix CHECK-A32BE -check-prefix=CHECK %s
// CHECK-LP64: %union.Test1 = type { i32, [4 x i8] }
union Test1 {
int a;
int b: 39;
-} t1;
+};
+Test1 t1;
// CHECK-LP64: %union.Test2 = type { i8 }
union Test2 {
@@ -17,10 +20,16 @@ union Test3 {
int : 9;
} t3;
+// CHECK: %union.Test4 = type { i8, i8 }
+union Test4 {
+ char val : 16;
+};
+Test4 t4;
#define CHECK(x) if (!(x)) return __LINE__
-int f() {
+// CHECK: define i32 @_Z11test_assignv()
+int test_assign() {
struct {
int a;
@@ -37,7 +46,41 @@ int f() {
CHECK(c.b == (unsigned long long)-1);
CHECK(c.c == 0);
-// CHECK-LP64: ret i32 0
-// CHECK-LP32: ret i32 0
+ Test1 u1;
+ Test4 u2;
+
+ u1.b = 1;
+ u2.val = 42;
+
+ CHECK(u1.b == 1);
+ CHECK(u2.val == 42);
+
+ // CHECK: ret i32 0
+ return 0;
+}
+
+// CHECK: define i32 @_Z9test_initv()
+int test_init() {
+ struct S {
+int a;
+
+unsigned long long b : 65;
+
+int c;
+ };
+ S s1 = {1, 42, 0};
+
+ CHECK(s1.a == 1);
+ CHECK(s1.b == (unsigned long long)42);
+ CHECK(s1.c == 0);
+
+ Test1 u1 =
[clang] dade859 - [ARM] Setting missing isLaneQ attribute on Neon Intrisics definitions
Author: Lucas Prates
Date: 2020-03-19T12:04:14Z
New Revision: dade859b58827eaddc88f820c5dd5a28cf3532f3
URL:
https://github.com/llvm/llvm-project/commit/dade859b58827eaddc88f820c5dd5a28cf3532f3
DIFF:
https://github.com/llvm/llvm-project/commit/dade859b58827eaddc88f820c5dd5a28cf3532f3.diff
LOG: [ARM] Setting missing isLaneQ attribute on Neon Intrisics definitions
Summary:
Some of the `*_laneq` intrinsics defined in arm_neon.td were missing the
setting of the `isLaneQ` attribute. This patch sets the attribute on the
related definitions, as they will be required to properly perform range
checks on their lane arguments.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, dnsampaio
Reviewed By: dnsampaio
Subscribers: dnsampaio, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74616
Added:
Modified:
clang/include/clang/Basic/arm_neon.td
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 380a2a0a5fa6..5ae25b311bb2 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -881,16 +881,22 @@ def COPY_LANE : IOpInst<"vcopy_lane", "..I.I",
def COPYQ_LANE : IOpInst<"vcopy_lane", "..IqI",
"QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
def COPY_LANEQ : IOpInst<"vcopy_laneq", "..IQI",
- "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>;
+ "csilPcPsPlUcUsUiUlfd", OP_COPY_LN> {
+ let isLaneQ = 1;
+}
def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "..I.I",
- "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
+ "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN> {
+ let isLaneQ = 1;
+}
// Set all lanes to same value
def VDUP_LANE1: WOpInst<"vdup_lane", ".qI", "hdQhQdPlQPl", OP_DUP_LN>;
def VDUP_LANE2: WOpInst<"vdup_laneq", ".QI",
"csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
-OP_DUP_LN>;
+OP_DUP_LN> {
+ let isLaneQ = 1;
+}
def DUP_N : WOpInst<"vdup_n", ".1", "dQdPlQPl", OP_DUP>;
def MOV_N : WOpInst<"vmov_n", ".1", "dQdPlQPl", OP_DUP>;
@@ -906,38 +912,60 @@ def CREATE : NoTestOpInst<"vcreate", ".(IU>)", "dPl",
OP_CAST> {
def VMLA_LANEQ : IOpInst<"vmla_laneq", "...QI",
- "siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
+ "siUsUifQsQiQUsQUiQf", OP_MLA_LN> {
+ let isLaneQ = 1;
+}
def VMLS_LANEQ : IOpInst<"vmls_laneq", "...QI",
- "siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
+ "siUsUifQsQiQUsQUiQf", OP_MLS_LN> {
+ let isLaneQ = 1;
+}
def VFMA_LANE: IInst<"vfma_lane", "...qI", "fdQfQd">;
def VFMA_LANEQ : IInst<"vfma_laneq", "...QI", "fdQfQd"> {
let isLaneQ = 1;
}
def VFMS_LANE: IOpInst<"vfms_lane", "...qI", "fdQfQd", OP_FMS_LN>;
-def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ>;
+def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ> {
+ let isLaneQ = 1;
+}
-def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN>;
+def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN>
{
+ let isLaneQ = 1;
+}
def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
OP_MLALHi_LN>;
def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
-OP_MLALHi_LN>;
-def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN>;
+OP_MLALHi_LN> {
+ let isLaneQ = 1;
+}
+def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN>
{
+ let isLaneQ = 1;
+}
def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
OP_MLSLHi_LN>;
def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
-OP_MLSLHi_LN>;
+OP_MLSLHi_LN> {
+ let isLaneQ = 1;
+}
-def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si",
OP_QDMLAL_LN>;
+def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si",
OP_QDMLAL_LN> {
+ let isLaneQ = 1;
+}
def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "(>Q)(>Q)Q.I", "si",
OP_QDMLALHi_LN>;
def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "(>Q)(>Q)QQI", "si",
-OP_QDMLALHi_LN>;
-def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "(>Q)(>Q).QI", "si",
OP_QDMLSL_LN>;
+OP_QDMLALHi_LN> {
+ let isLaneQ = 1;
+}
+def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_la
[clang] d427116 - [ARM] Creating 'call_mangled' for Neon intrinsics definitions
Author: Lucas Prates
Date: 2020-03-19T12:05:55Z
New Revision: d42711625af8188edb15c8ddad8c861fbca89c17
URL:
https://github.com/llvm/llvm-project/commit/d42711625af8188edb15c8ddad8c861fbca89c17
DIFF:
https://github.com/llvm/llvm-project/commit/d42711625af8188edb15c8ddad8c861fbca89c17.diff
LOG: [ARM] Creating 'call_mangled' for Neon intrinsics definitions
Summary:
As multiple versions of the same Neon intrinsic can be created through
the same TableGen definition with the same argument types, the existing
`call` operator is not always able to properly perform overload
resolutions.
As these different intrinsic versions are differentiated later on by the
NeonEmitter through name mangling, this patch introduces a new
`call_mangled` operator to the TableGen definitions, which allows a call
for an otherwise ambiguous intrinsic by matching its mangled name with
the mangled variation of the caller.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, dnsampaio
Reviewed By: dnsampaio
Subscribers: dnsampaio, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74618
Added:
Modified:
clang/include/clang/Basic/arm_neon_incl.td
clang/utils/TableGen/NeonEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/arm_neon_incl.td
b/clang/include/clang/Basic/arm_neon_incl.td
index 28b00d162a00..6313faf0fa30 100644
--- a/clang/include/clang/Basic/arm_neon_incl.td
+++ b/clang/include/clang/Basic/arm_neon_incl.td
@@ -60,6 +60,15 @@ def op;
// example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)"
//(assuming $p0 has type int16x8_t).
def call;
+// call_mangled - Invoke another intrinsic matching the mangled name variation
+//of the caller's base type. If there is no intrinsic defined
+//that has the variation and takes the given types, an error
+//is generated at tblgen time.
+// example: (call_mangled "vfma_lane", $p0, $p1) -> "vfma_lane(__p0, __p1)"
+//(assuming non-LaneQ caller)
+// (call_mangled "vfma_lane", $p0, $p1) -> "vfma_laneq(__p0, __p1)"
+//(assuming LaneQ caller)
+def call_mangled;
// cast - Perform a cast to a
diff erent type. This gets emitted as a static
//C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use
//"bitcast".
diff --git a/clang/utils/TableGen/NeonEmitter.cpp
b/clang/utils/TableGen/NeonEmitter.cpp
index 59ea15493f03..ea4060757a4f 100644
--- a/clang/utils/TableGen/NeonEmitter.cpp
+++ b/clang/utils/TableGen/NeonEmitter.cpp
@@ -27,8 +27,9 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/None.h"
-#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Casting.h"
@@ -518,7 +519,8 @@ class Intrinsic {
std::pair emitDagDupTyped(DagInit *DI);
std::pair emitDagShuffle(DagInit *DI);
std::pair emitDagCast(DagInit *DI, bool IsBitCast);
-std::pair emitDagCall(DagInit *DI);
+std::pair emitDagCall(DagInit *DI,
+ bool MatchMangledName);
std::pair emitDagNameReplace(DagInit *DI);
std::pair emitDagLiteral(DagInit *DI);
std::pair emitDagOp(DagInit *DI);
@@ -546,7 +548,8 @@ class NeonEmitter {
public:
/// Called by Intrinsic - this attempts to get an intrinsic that takes
/// the given types as arguments.
- Intrinsic &getIntrinsic(StringRef Name, ArrayRef Types);
+ Intrinsic &getIntrinsic(StringRef Name, ArrayRef Types,
+ Optional MangledName);
/// Called by Intrinsic - returns a globally-unique number.
unsigned getUniqueNumber() { return UniqueNumber++; }
@@ -1383,8 +1386,8 @@ std::pair
Intrinsic::DagEmitter::emitDag(DagInit *DI) {
return emitDagSaveTemp(DI);
if (Op == "op")
return emitDagOp(DI);
- if (Op == "call")
-return emitDagCall(DI);
+ if (Op == "call" || Op == "call_mangled")
+return emitDagCall(DI, Op == "call_mangled");
if (Op == "name_replace")
return emitDagNameReplace(DI);
if (Op == "literal")
@@ -1411,7 +1414,8 @@ std::pair
Intrinsic::DagEmitter::emitDagOp(DagInit *DI) {
}
}
-std::pair Intrinsic::DagEmitter::emitDagCall(DagInit *DI) {
+std::pair
+Intrinsic::DagEmitter::emitDagCall(DagInit *DI, bool MatchMangledName) {
std::vector Types;
std::vector Values;
for (unsigned I = 0; I < DI->getNumArgs() - 1; ++I) {
@@ -1427,7 +1431,13 @@ std::pair
Intrinsic::DagEmitter::emitDagCall(DagInit *DI) {
N = SI->getAsUnquotedString();
else
N = emitDagArg(DI->getArg(0), "").second;
- Intrinsic &Callee = Intr.Emitter.getIntrinsic(N, Types);
+ Optional MangledName;
+ if (MatchMangledName) {
+if (Intr.getRecord()->getValueAsBit("isLaneQ"))
+
[clang] d4ad386 - [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane intrinsics
Author: Lucas Prates
Date: 2020-03-19T12:08:12Z
New Revision: d4ad386ee1955ceb63fc616b3e30abb553e0685f
URL:
https://github.com/llvm/llvm-project/commit/d4ad386ee1955ceb63fc616b3e30abb553e0685f
DIFF:
https://github.com/llvm/llvm-project/commit/d4ad386ee1955ceb63fc616b3e30abb553e0685f.diff
LOG: [ARM] Fixing range checks for Neon's vqdmulhq_lane and vqrdmulhq_lane
intrinsics
Summary:
The range checks performed for the vqrdmulh_lane and vqrdmulh_lane Neon
intrinsics were incorrectly using their return type as the base type for
the range check performed on their 'lane' argument.
This patch updates those intrisics to use the type of the proper reference
argument to perform the range checks.
Reviewers: jmolloy, t.p.northover, rsmith, olista01, dnsampaio
Reviewed By: dnsampaio
Subscribers: dnsampaio, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74766
Added:
Modified:
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/arm-neon-range-checks.c
Removed:
diff --git a/clang/include/clang/Basic/arm_neon.td
b/clang/include/clang/Basic/arm_neon.td
index 4490aad777dd..f949edc378fc 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -547,8 +547,8 @@ def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI",
"siQsQi", OP_QDMULH_LN>;
def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>;
}
let ArchGuard = "defined(__aarch64__)" in {
-def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..qI", "siQsQi">;
-def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..qI", "siQsQi">;
+def A64_VQDMULH_LANE : SInst<"vqdmulh_lane", "..(!q)I", "siQsQi">;
+def A64_VQRDMULH_LANE : SInst<"vqrdmulh_lane", "..(!q)I", "siQsQi">;
}
let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in {
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index d0ac4dd5b737..e42339dbcfcc 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5824,9 +5824,14 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
case NEON::BI__builtin_neon_vqdmulh_lane_v:
case NEON::BI__builtin_neon_vqrdmulhq_lane_v:
case NEON::BI__builtin_neon_vqrdmulh_lane_v: {
+llvm::Type *RTy = Ty;
+if (BuiltinID == NEON::BI__builtin_neon_vqdmulhq_lane_v ||
+BuiltinID == NEON::BI__builtin_neon_vqrdmulhq_lane_v)
+ RTy = llvm::VectorType::get(Ty->getVectorElementType(),
+ Ty->getVectorNumElements() * 2);
llvm::Type *Tys[2] = {
-Ty, GetNeonType(this, NeonTypeFlags(Type.getEltType(), false,
-/*isQuad*/ false))};
+RTy, GetNeonType(this, NeonTypeFlags(Type.getEltType(), false,
+ /*isQuad*/ false))};
return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, NameHint);
}
case NEON::BI__builtin_neon_vqdmulhq_laneq_v:
diff --git a/clang/test/CodeGen/arm-neon-range-checks.c
b/clang/test/CodeGen/arm-neon-range-checks.c
index 313bd07ff190..488dad6d59ac 100644
--- a/clang/test/CodeGen/arm-neon-range-checks.c
+++ b/clang/test/CodeGen/arm-neon-range-checks.c
@@ -280,6 +280,13 @@ void test_vqdmulh_lane(int32x2_t a, int32x2_t b) {
vqdmulh_lane_s32(a, b, 1);
}
+void test_vqdmulhq_lane(int32x4_t a, int32x2_t b) {
+ vqdmulhq_lane_s32(a, b, -1); // expected-error {{argument value -1 is
outside the valid range [0, 1]}}
+ vqdmulhq_lane_s32(a, b, 2); // expected-error {{argument value 2 is outside
the valid range [0, 1]}}
+ vqdmulhq_lane_s32(a, b, 0);
+ vqdmulhq_lane_s32(a, b, 1);
+}
+
#if defined(__aarch64__)
void test_vqdmulh_laneq(int32x2_t a, int32x4_t b) {
vqdmulh_laneq_s32(a, b, -1); // expected-error {{argument value -1 is
outside the valid range [0, 3]}}
@@ -393,6 +400,13 @@ void test_vqrdmulh_lane(int32x2_t a, int32x2_t v) {
vqrdmulh_lane_s32(a, v, 1);
}
+void test_vqrdmulhq_lane(int32x4_t a, int32x2_t v) {
+ vqrdmulhq_lane_s32(a, v, -1); // expected-error {{argument value -1 is
outside the valid range [0, 1]}}
+ vqrdmulhq_lane_s32(a, v, 2); // expected-error {{argument value 2 is
outside the valid range [0, 1]}}
+ vqrdmulhq_lane_s32(a, v, 0);
+ vqrdmulhq_lane_s32(a, v, 1);
+}
+
#if defined(__aarch64__)
void test_vqrdmulh_laneq(int32x2_t a, int32x4_t v) {
vqrdmulh_laneq_s32(a, v, -1); // expected-error {{argument value -1 is
outside the valid range [0, 3]}}
___
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[clang] 59fce6b - [NFC] make clang/test/CodeGen/arm_neon_intrinsics.c resistent to function attribute id changes
Author: Jeroen Dobbelaere
Date: 2021-01-07T17:08:15Z
New Revision: 59fce6b0661647062918a47bdb1874950d3938d5
URL:
https://github.com/llvm/llvm-project/commit/59fce6b0661647062918a47bdb1874950d3938d5
DIFF:
https://github.com/llvm/llvm-project/commit/59fce6b0661647062918a47bdb1874950d3938d5.diff
LOG: [NFC] make clang/test/CodeGen/arm_neon_intrinsics.c resistent to function
attribute id changes
When introducing support for @llvm.experimental.noalias.scope.decl, this tests
started failing because it checks
(for no good reason) for a function attribute id of '#8' which now becomes '#9'
Reviewed By: pratlucas
Differential Revision: https://reviews.llvm.org/D94233
Added:
Modified:
clang/test/CodeGen/arm_neon_intrinsics.c
Removed:
diff --git a/clang/test/CodeGen/arm_neon_intrinsics.c
b/clang/test/CodeGen/arm_neon_intrinsics.c
index 9d3f35f48bb7..56e105a41962 100644
--- a/clang/test/CodeGen/arm_neon_intrinsics.c
+++ b/clang/test/CodeGen/arm_neon_intrinsics.c
@@ -7114,7 +7114,7 @@ uint64x2_t test_vmlal_u32(uint64x2_t a, uint32x2_t b,
uint32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[ADD]]
int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {
@@ -7127,7 +7127,7 @@ int32x4_t test_vmlal_lane_s16(int32x4_t a, int16x4_t b,
int16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]])
// CHECK: [[ADD:%.*]] = add <2 x i64> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <2 x i64> [[ADD]]
int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b, int32x2_t c) {
@@ -7140,7 +7140,7 @@ int64x2_t test_vmlal_lane_s32(int64x2_t a, int32x2_t b,
int32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[ADD:%.*]] = add <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[ADD]]
uint32x4_t test_vmlal_lane_u16(uint32x4_t a, uint16x4_t b, uint16x4_t c) {
@@ -7153,7 +7153,7 @@ uint32x4_t test_vmlal_lane_u16(uint32x4_t a, uint16x4_t
b, uint16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <2 x i32> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x
i32> [[B]], <2 x i32> [[LANE]])
// CHECK: [[ADD:%.*]] = add <2 x i64> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <2 x i64> [[ADD]]
uint64x2_t test_vmlal_lane_u32(uint64x2_t a, uint32x2_t b, uint32x2_t c) {
@@ -7618,7 +7618,7 @@ uint64x2_t test_vmlsl_u32(uint64x2_t a, uint32x2_t b,
uint32x2_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16>
[[TMP1]], <4 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast <4 x i16> [[LANE]] to <8 x i8>
-// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]]) #8
+// CHECK: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x
i16> [[B]], <4 x i16> [[LANE]])
// CHECK: [[SUB:%.*]] = sub <4 x i32> [[A:%.*]], [[VMULL2_I]]
// CHECK: ret <4 x i32> [[SUB]]
int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b, int16x4_t c) {
@@ -7631,7 +7631,7 @@ int32x4_t test_vmlsl_lane_s16(int32x4_t a, int16x4_t b,
int16x4_t c) {
// CHECK: [[LANE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32>
[[TMP1]], <2 x i32>
// CHECK: [[TMP2:%.*]] = bitcast <2 x i32> [[B:%.*]] to <8 x i8>
// CHECK: [[TMP3:%.*]] = bitcast
[clang] 2b1e25b - [AArch64] Adding ACLE intrinsics for the LS64 extension
Author: Lucas Prates
Date: 2021-01-14T09:43:58Z
New Revision: 2b1e25befefc20f012aa49011f46e11e8530ee21
URL:
https://github.com/llvm/llvm-project/commit/2b1e25befefc20f012aa49011f46e11e8530ee21
DIFF:
https://github.com/llvm/llvm-project/commit/2b1e25befefc20f012aa49011f46e11e8530ee21.diff
LOG: [AArch64] Adding ACLE intrinsics for the LS64 extension
This introduces the ARMv8.7-A LS64 extension's intrinsics for 64 bytes
atomic loads and stores: `__arm_ld64b`, `__arm_st64b`, `__arm_st64bv`,
and `__arm_st64bv0`. These are selected into the LS64 instructions
LD64B, ST64B, ST64BV and ST64BV0, respectively.
Based on patches written by Simon Tatham.
Reviewed By: tmatheson
Differential Revision: https://reviews.llvm.org/D93232
Added:
clang/test/CodeGen/aarch64-ls64.c
llvm/test/CodeGen/AArch64/ls64-intrinsics.ll
Modified:
clang/include/clang/Basic/BuiltinsAArch64.def
clang/lib/Basic/Targets/AArch64.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Headers/arm_acle.h
clang/test/Preprocessor/aarch64-target-features.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def
b/clang/include/clang/Basic/BuiltinsAArch64.def
index c684105908de..b35510f8b691 100644
--- a/clang/include/clang/Basic/BuiltinsAArch64.def
+++ b/clang/include/clang/Basic/BuiltinsAArch64.def
@@ -99,6 +99,12 @@ BUILTIN(__builtin_arm_tcommit, "v", "n")
BUILTIN(__builtin_arm_tcancel, "vWUIi", "n")
BUILTIN(__builtin_arm_ttest, "WUi", "nc")
+// Armv8.7-A load/store 64-byte intrinsics
+BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n")
+BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n")
+BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n")
+BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n")
+
TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanForward64, "UcUNi*ULLi", "nh", "intrin.h",
ALL_MS_LANGUAGES, "")
diff --git a/clang/lib/Basic/Targets/AArch64.cpp
b/clang/lib/Basic/Targets/AArch64.cpp
index 312c822ebb05..f17134623b8b 100644
--- a/clang/lib/Basic/Targets/AArch64.cpp
+++ b/clang/lib/Basic/Targets/AArch64.cpp
@@ -356,6 +356,9 @@ void AArch64TargetInfo::getTargetDefines(const LangOptions
&Opts,
if (Opts.BranchTargetEnforcement)
Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
+ if (HasLS64)
+Builder.defineMacro("__ARM_FEATURE_LS64", "1");
+
switch (ArchKind) {
default:
break;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index cf84ad34e1ec..7fa4e4d270ad 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -8979,6 +8979,46 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::aarch64_fjcvtzs), Arg);
}
+ if (BuiltinID == AArch64::BI__builtin_arm_ld64b ||
+ BuiltinID == AArch64::BI__builtin_arm_st64b ||
+ BuiltinID == AArch64::BI__builtin_arm_st64bv ||
+ BuiltinID == AArch64::BI__builtin_arm_st64bv0) {
+llvm::Value *MemAddr = EmitScalarExpr(E->getArg(0));
+llvm::Value *ValPtr = EmitScalarExpr(E->getArg(1));
+
+if (BuiltinID == AArch64::BI__builtin_arm_ld64b) {
+ // Load from the address via an LLVM intrinsic, receiving a
+ // tuple of 8 i64 words, and store each one to ValPtr.
+ Function *F = CGM.getIntrinsic(Intrinsic::aarch64_ld64b);
+ llvm::Value *Val = Builder.CreateCall(F, MemAddr);
+ llvm::Value *ToRet;
+ for (size_t i = 0; i < 8; i++) {
+llvm::Value *ValOffsetPtr = Builder.CreateGEP(ValPtr,
Builder.getInt32(i));
+Address Addr(ValOffsetPtr, CharUnits::fromQuantity(8));
+ToRet = Builder.CreateStore(Builder.CreateExtractValue(Val, i), Addr);
+ }
+ return ToRet;
+} else {
+ // Load 8 i64 words from ValPtr, and store them to the address
+ // via an LLVM intrinsic.
+ SmallVector Args;
+ Args.push_back(MemAddr);
+ for (size_t i = 0; i < 8; i++) {
+llvm::Value *ValOffsetPtr = Builder.CreateGEP(ValPtr,
Builder.getInt32(i));
+Address Addr(ValOffsetPtr, CharUnits::fromQuantity(8));
+Args.push_back(Builder.CreateLoad(Addr));
+ }
+
+ auto Intr = (BuiltinID == AArch64::BI__builtin_arm_st64b
+ ? Intrinsic::aarch64_st64b
+ : BuiltinID == AArch64::BI__builtin_arm_st64bv
+ ? Intrinsic::aarch64_st64bv
+ : Intrinsic::aarch64_st64bv0);
+ Function *F = CGM.getIntrinsic(Intr);
+ return Builder.CreateCall(F, Args);
+}
+ }
+
if (BuiltinID == AArch64::BI__clear_cache) {
assert(E->getNumArgs() == 2 && "__
