r336308 - [Power9] Update fp128 as a valid homogenous aggregate base type
Author: lei
Date: Wed Jul 4 21:32:01 2018
New Revision: 336308
URL: http://llvm.org/viewvc/llvm-project?rev=336308&view=rev
Log:
[Power9] Update fp128 as a valid homogenous aggregate base type
Update clang to treat fp128 as a valid base type for homogeneous aggregate
passing and returning.
Differential Revision: https://reviews.llvm.org/D48044
Added:
cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
Modified:
cfe/trunk/include/clang/AST/Type.h
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/include/clang/AST/Type.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/AST/Type.h?rev=336308&r1=336307&r2=336308&view=diff
==
--- cfe/trunk/include/clang/AST/Type.h (original)
+++ cfe/trunk/include/clang/AST/Type.h Wed Jul 4 21:32:01 2018
@@ -1807,6 +1807,7 @@ public:
bool isFloatingType() const; // C99 6.2.5p11 (real floating + complex)
bool isHalfType() const; // OpenCL 6.1.1.1, NEON (IEEE 754-2008 half)
bool isFloat16Type() const; // C11 extension ISO/IEC TS 18661
+ bool isFloat128Type() const;
bool isRealType() const; // C99 6.2.5p17 (real floating + integer)
bool isArithmeticType() const; // C99 6.2.5p18 (integer + floating)
bool isVoidType() const; // C99 6.2.5p19
@@ -6299,6 +6300,12 @@ inline bool Type::isFloat16Type() const
return false;
}
+inline bool Type::isFloat128Type() const {
+ if (const auto *BT = dyn_cast(CanonicalType))
+return BT->getKind() == BuiltinType::Float128;
+ return false;
+}
+
inline bool Type::isNullPtrType() const {
if (const auto *BT = getAs())
return BT->getKind() == BuiltinType::NullPtr;
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=336308&r1=336307&r2=336308&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Wed Jul 4 21:32:01 2018
@@ -4619,7 +4619,9 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAg
if (const BuiltinType *BT = Ty->getAs()) {
if (BT->getKind() == BuiltinType::Float ||
BT->getKind() == BuiltinType::Double ||
-BT->getKind() == BuiltinType::LongDouble) {
+BT->getKind() == BuiltinType::LongDouble ||
+(getContext().getTargetInfo().hasFloat128Type() &&
+ (BT->getKind() == BuiltinType::Float128))) {
if (IsSoftFloatABI)
return false;
return true;
@@ -4634,10 +4636,13 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAg
bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
const Type *Base, uint64_t Members) const {
- // Vector types require one register, floating point types require one
- // or two registers depending on their size.
+ // Vector and fp128 types require one register, other floating point types
+ // require one or two registers depending on their size.
uint32_t NumRegs =
- Base->isVectorType() ? 1 : (getContext().getTypeSize(Base) + 63) / 64;
+ ((getContext().getTargetInfo().hasFloat128Type() &&
+ Base->isFloat128Type()) ||
+Base->isVectorType()) ? 1
+ : (getContext().getTypeSize(Base) + 63) / 64;
// Homogeneous Aggregates may occupy at most 8 registers.
return Members * NumRegs <= 8;
Added: cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c?rev=336308&view=auto
==
--- cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c (added)
+++ cfe/trunk/test/CodeGen/ppc64le-f128Aggregates.c Wed Jul 4 21:32:01 2018
@@ -0,0 +1,124 @@
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
+// RUN: -target-cpu pwr9 -target-feature +float128 -o - %s | FileCheck %s
+
+// Test homogeneous fp128 aggregate passing and returning.
+
+struct fp1 { __float128 f[1]; };
+struct fp2 { __float128 f[2]; };
+struct fp3 { __float128 f[3]; };
+struct fp4 { __float128 f[4]; };
+struct fp5 { __float128 f[5]; };
+struct fp6 { __float128 f[6]; };
+struct fp7 { __float128 f[7]; };
+struct fp8 { __float128 f[8]; };
+struct fp9 { __float128 f[9]; };
+
+struct fpab { __float128 a; __float128 b; };
+struct fpabc { __float128 a; __float128 b; __float128 c; };
+
+struct fp2a2b { __float128 a[2]; __float128 b[2]; };
+
+// CHECK: define [1 x fp128] @func_f1(fp128 inreg %x.coerce)
+struct fp1 func_f1(struct fp1 x) { return x; }
+
+// CHECK: define [2 x fp128] @func_f2([2 x fp128] %x.coerce)
+struct fp2 func_f2(struct fp2 x) { return x; }
+
+// CHECK: define [3 x fp128] @func_f3([3 x fp128] %x.coerce)
+struct fp3 func_f3(struct fp3 x) { return x; }
+
+// CHECK: define [4 x fp128] @func_f4([4 x fp128] %x.coerce)
+struct fp4 func_f4(struct fp4 x) { return x; }
+
+// CHECK: define [5 x fp128]
[clang] 7eb666b - [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Author: Lei Huang
Date: 2020-05-26T13:48:22-05:00
New Revision: 7eb666b1556b86503f2f386bf921186cdbb2d22a
URL:
https://github.com/llvm/llvm-project/commit/7eb666b1556b86503f2f386bf921186cdbb2d22a
DIFF:
https://github.com/llvm/llvm-project/commit/7eb666b1556b86503f2f386bf921186cdbb2d22a.diff
LOG: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Summary:
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.
Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc
Reviewed By: stefanp, nemanjai, amyk, #powerpc
Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz,
cfe-commits, kbarton, echristo
Tags: #clang, #powerpc, #llvm
Differential Revision: https://reviews.llvm.org/D80020
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 81c13a8104e8..231f94b66f5f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -151,6 +151,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("_ARCH_PWR8");
if (ArchDefs & ArchDefinePwr9)
Builder.defineMacro("_ARCH_PWR9");
+ if (ArchDefs & ArchDefinePwr10)
+Builder.defineMacro("_ARCH_PWR10");
if (ArchDefs & ArchDefineA2)
Builder.defineMacro("_ARCH_A2");
if (ArchDefs & ArchDefineA2q) {
@@ -263,41 +265,51 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr7", true)
.Case("pwr8", true)
.Case("pwr9", true)
+.Case("pwr10", true)
.Case("ppc64", true)
.Case("ppc64le", true)
.Default(false);
Features["qpx"] = (CPU == "a2q");
- Features["power9-vector"] = (CPU == "pwr9");
+ Features["power9-vector"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)
+ .Case("pwr9", true)
+ .Default(false);
Features["crypto"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+ .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["power8-vector"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+ .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["bpermd"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+ .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["extdiv"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+ .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["direct-move"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+.Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["vsx"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
+.Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
@@ -313,10 +325,10 @@ bool PPCTargetInfo::initFeatureMap(
.Case("e500", true)
.Default(false);
- // Future CPU should include all of the features of Power 9 as well as any
+ // Future CPU should include all of the features of Power 10 as well as any
// additional features (yet to be det
[clang] 559845f - Revert "[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm"
Author: Lei Huang
Date: 2020-05-27T09:40:21-05:00
New Revision: 559845f8fe53fabb22f9a392e8d34761df250c72
URL:
https://github.com/llvm/llvm-project/commit/559845f8fe53fabb22f9a392e8d34761df250c72
DIFF:
https://github.com/llvm/llvm-project/commit/559845f8fe53fabb22f9a392e8d34761df250c72.diff
LOG: Revert "[PowerPC] Add support for -mcpu=pwr10 in both clang and llvm"
This reverts commit 7eb666b1556b86503f2f386bf921186cdbb2d22a.
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 231f94b66f5f..81c13a8104e8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -151,8 +151,6 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("_ARCH_PWR8");
if (ArchDefs & ArchDefinePwr9)
Builder.defineMacro("_ARCH_PWR9");
- if (ArchDefs & ArchDefinePwr10)
-Builder.defineMacro("_ARCH_PWR10");
if (ArchDefs & ArchDefineA2)
Builder.defineMacro("_ARCH_A2");
if (ArchDefs & ArchDefineA2q) {
@@ -265,51 +263,41 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr7", true)
.Case("pwr8", true)
.Case("pwr9", true)
-.Case("pwr10", true)
.Case("ppc64", true)
.Case("ppc64le", true)
.Default(false);
Features["qpx"] = (CPU == "a2q");
- Features["power9-vector"] = llvm::StringSwitch(CPU)
- .Case("pwr10", true)
- .Case("pwr9", true)
- .Default(false);
+ Features["power9-vector"] = (CPU == "pwr9");
Features["crypto"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
- .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["power8-vector"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
- .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["bpermd"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
- .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["extdiv"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
- .Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["direct-move"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
-.Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["vsx"] = llvm::StringSwitch(CPU)
.Case("ppc64le", true)
-.Case("pwr10", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
@@ -325,10 +313,10 @@ bool PPCTargetInfo::initFeatureMap(
.Case("e500", true)
.Default(false);
- // Future CPU should include all of the features of Power 10 as well as any
+ // Future CPU should include all of the features of Power 9 as well as any
// additional features (yet to be determined) specific to it.
if (CPU == "future") {
-initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
addFutureSpecificFeatures(Features);
}
@@ -475,17 +463,18 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"}, {"601"}, {"602
[clang] 2368bf5 - [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Author: Lei Huang
Date: 2020-05-27T13:14:25-05:00
New Revision: 2368bf52cd7725a34f09f4b27a9c205cda06f478
URL:
https://github.com/llvm/llvm-project/commit/2368bf52cd7725a34f09f4b27a9c205cda06f478
DIFF:
https://github.com/llvm/llvm-project/commit/2368bf52cd7725a34f09f4b27a9c205cda06f478.diff
LOG: [PowerPC] Add support for -mcpu=pwr10 in both clang and llvm
Summary:
This patch simply adds support for the new CPU in anticipation of
Power10. There isn't really any functionality added so there are no
associated test cases at this time.
Reviewers: stefanp, nemanjai, amyk, hfinkel, power-llvm-team, #powerpc
Reviewed By: stefanp, nemanjai, amyk, #powerpc
Subscribers: NeHuang, steven.zhang, hiraditya, llvm-commits, wuzish, shchenz,
cfe-commits, kbarton, echristo
Tags: #clang, #powerpc, #llvm
Differential Revision: https://reviews.llvm.org/D80020
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init-ppc64.c
llvm/lib/Support/Host.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/test/CodeGen/PowerPC/check-cpu.ll
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 81c13a8104e8..ad34c287b518 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -151,6 +151,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("_ARCH_PWR8");
if (ArchDefs & ArchDefinePwr9)
Builder.defineMacro("_ARCH_PWR9");
+ if (ArchDefs & ArchDefinePwr10)
+Builder.defineMacro("_ARCH_PWR10");
if (ArchDefs & ArchDefineA2)
Builder.defineMacro("_ARCH_A2");
if (ArchDefs & ArchDefineA2q) {
@@ -313,10 +315,17 @@ bool PPCTargetInfo::initFeatureMap(
.Case("e500", true)
.Default(false);
- // Future CPU should include all of the features of Power 9 as well as any
+ // Power10 includes all the same features as Power9 plus any features
specific
+ // to the Power10 core.
+ if (CPU == "pwr10" || CPU == "power10") {
+initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+addP10SpecificFeatures(Features);
+ }
+
+ // Future CPU should include all of the features of Power 10 as well as any
// additional features (yet to be determined) specific to it.
if (CPU == "future") {
-initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
addFutureSpecificFeatures(Features);
}
@@ -333,6 +342,13 @@ bool PPCTargetInfo::initFeatureMap(
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}
+// Add any Power10 specific features.
+void PPCTargetInfo::addP10SpecificFeatures(
+llvm::StringMap &Features) const {
+ Features["htm"] = false; // HTM was removed for P10.
+ return;
+}
+
// Add features specific to the "Future" CPU.
void PPCTargetInfo::addFutureSpecificFeatures(
llvm::StringMap &Features) const {
@@ -463,18 +479,17 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
-{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
-{"620"}, {"630"}, {"g3"}, {"7400"},{"g4"},
-{"7450"}, {"g4+"}, {"750"}, {"8548"},{"970"},
-{"g5"},{"a2"},{"a2q"}, {"e500"},{"e500mc"},
-{"e5500"}, {"power3"},{"pwr3"},{"power4"}, {"pwr4"},
-{"power5"},{"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
-{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
-{"power8"},{"pwr8"}, {"power9"}, {"pwr9"},
{"powerpc"},
-{"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"},
{"ppc64le"},
-{"future"}
-};
+{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
+{"603"}, {"603e"},{"603ev"}, {"604"}, {"604e"},
+{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
+{"7450"},{"g4+"}, {"750"}, {"8548"}, {"970"},
+{"g5"}, {"a2"}, {"a2q"}, {"e500"}, {"e500mc"},
+{"e5500"}, {"power3"}, {"pwr3"},{"power4"},{"pwr4"},
+{"power5"}, {"pwr5"},{"power5x"}, {"pwr5x"}, {"power6"},
+{"pwr6"},{"power6x"}, {"pwr6x"}, {"power7"},{"pwr7"},
+{"power8"}, {"pwr8"},{"power9"}, {"pwr9"}, {"power10"},
+{"pwr10"}, {"powerpc"}
[clang] 7cfded3 - [PowerPC] Add clang option -m[no-]pcrel
Author: Lei Huang
Date: 2020-06-01T15:34:59-05:00
New Revision: 7cfded350a7edc87f4a67f84e4261e44954600d0
URL:
https://github.com/llvm/llvm-project/commit/7cfded350a7edc87f4a67f84e4261e44954600d0
DIFF:
https://github.com/llvm/llvm-project/commit/7cfded350a7edc87f4a67f84e4261e44954600d0.diff
LOG: [PowerPC] Add clang option -m[no-]pcrel
Summary:
Add user-facing front end option to turn off pc-relative memops.
This will be compatible with gcc.
Reviewers: stefanp, nemanjai, hfinkel, power-llvm-team, #powerpc, NeHuang,
saghir
Reviewed By: stefanp, NeHuang, saghir
Subscribers: saghir, wuzish, shchenz, cfe-commits, kbarton, echristo
Tags: #clang, #powerpc
Differential Revision: https://reviews.llvm.org/D80757
Added:
clang/test/Driver/ppc-pcrel.cpp
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 729cbfb6ad4a..0bbeeaf13308 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2470,6 +2470,8 @@ def faltivec : Flag<["-"], "faltivec">, Group,
Flags<[DriverOption]>;
def fno_altivec : Flag<["-"], "fno-altivec">, Group,
Flags<[DriverOption]>;
def maltivec : Flag<["-"], "maltivec">, Group;
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
+def mpcrel: Flag<["-"], "mpcrel">, Group;
+def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
def mspe : Flag<["-"], "mspe">, Group;
def mno_spe : Flag<["-"], "mno-spe">, Group;
def mvsx : Flag<["-"], "mvsx">, Group;
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index ad34c287b518..230548d06caa 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -54,6 +54,8 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+} else if (Feature == "+pcrelative-memops") {
+ HasPCRelativeMemops = true;
} else if (Feature == "+spe") {
HasSPE = true;
LongDoubleWidth = LongDoubleAlign = 64;
@@ -346,6 +348,7 @@ bool PPCTargetInfo::initFeatureMap(
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["pcrelative-memops"] = true;
return;
}
@@ -369,6 +372,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
.Default(false);
}
@@ -389,7 +393,10 @@ void
PPCTargetInfo::setFeatureEnabled(llvm::StringMap &Features,
Features["vsx"] = Features["altivec"] = true;
if (Name == "power9-vector")
Features["power8-vector"] = true;
-Features[Name] = true;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = true;
+else
+ Features[Name] = true;
} else {
// If we're disabling altivec or vsx go ahead and disable all of the vsx
// features.
@@ -398,7 +405,10 @@ void
PPCTargetInfo::setFeatureEnabled(llvm::StringMap &Features,
Features["float128"] = Features["power9-vector"] = false;
if (Name == "power8-vector")
Features["power9-vector"] = false;
-Features[Name] = false;
+if (Name == "pcrel")
+ Features["pcrelative-memops"] = false;
+else
+ Features[Name] = false;
}
}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 691fa5fdcc6d..9c0a7bd755e2 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -69,6 +69,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool HasExtDiv = false;
bool HasP9Vector = false;
bool HasSPE = false;
+ bool HasPCRelativeMemops = false;
protected:
std::string ABI;
diff --git a/clang/test/Driver/ppc-pcrel.cpp b/clang/test/Driver/ppc-pcrel.cpp
new file mode 100644
index ..2b12f0de9280
--- /dev/null
+++ b/clang/test/Driver/ppc-pcrel.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10 -mpcrel
-o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PCREL %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mno-pcrel -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPCREL %s
+// CHECK-NOPCREL: "-target-feature" "-pcrel"
+// CHECK-PCREL: "-target-feature" "+pcrel"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S
%s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mpcrel
-emit-llvm -S %s -o - | grep "attributes.*+pcrelative-memops"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr1
[clang] 7aaa856 - [PowerPC] Add options to control paired vector memops support
Author: Baptiste Saleil
Date: 2020-07-29T14:00:53-05:00
New Revision: 7aaa85627b5937364d4c944d8f6828a6a3759785
URL:
https://github.com/llvm/llvm-project/commit/7aaa85627b5937364d4c944d8f6828a6a3759785
DIFF:
https://github.com/llvm/llvm-project/commit/7aaa85627b5937364d4c944d8f6828a6a3759785.diff
LOG: [PowerPC] Add options to control paired vector memops support
Adds frontend and backend options to enable and disable the
PowerPC paired vector memory operations added in ISA 3.1.
Instructions using these options will be added in subsequent patches.
Differential Revision: https://reviews.llvm.org/D83722
Added:
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-dependent-options.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index b6e31700c0a6..7d91bad1f848 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2453,6 +2453,10 @@ def mdirect_move : Flag<["-"], "mdirect-move">,
Group;
def mnodirect_move : Flag<["-"], "mno-direct-move">,
Group;
+def mpaired_vector_memops: Flag<["-"], "mpaired-vector-memops">,
+Group;
+def mnopaired_vector_memops: Flag<["-"], "mno-paired-vector-memops">,
+Group;
def mhtm : Flag<["-"], "mhtm">, Group;
def mno_htm : Flag<["-"], "mno-htm">, Group;
def mfprnd : Flag<["-"], "mfprnd">, Group;
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 5f716a541ae9..c5ad4a5a2d27 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -62,6 +62,8 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
} else if (Feature == "-hard-float") {
FloatABI = SoftFloat;
+} else if (Feature == "+paired-vector-memops") {
+ PairedVectorMemops = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@@ -218,6 +220,7 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
// - direct-move
// - float128
// - power9-vector
+// - paired-vector-memops
// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
@@ -240,6 +243,7 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
+ Found |= FindVSXSubfeature("+paired-vector-memops",
"-mpaired-vector-memops");
Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
@@ -340,6 +344,7 @@ bool PPCTargetInfo::initFeatureMap(
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap &Features) const {
Features["htm"] = false; // HTM was removed for P10.
+ Features["paired-vector-memops"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
@@ -364,6 +369,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("paired-vector-memops", PairedVectorMemops)
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
@@ -380,6 +386,7 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap
&Features,
.Case("direct-move", true)
.Case("power8-vector", true)
.Case("power9-vector", true)
+ .Case("paired-vector-memops", true)
.Case("power10-vector", true)
.Case("float128", true)
.Default(false);
@@ -399,11 +406,13 @@ void
PPCTargetInfo::setFeatureEnabled(llvm::StringMap &Features,
if ((Name == "altivec") || (Name == "vsx"))
Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
Features["float128"] = Features["power9-vector"] =
- Features["power10-vector"] = false;
+ Features["paired-vector-memops"] = Features["power10-vector"] =
+ false;
if (Name == "power8-vector")
- Features["power9-vector"] = Features["power10-vector"] = false;
+ Features["power9-vector"] = Features["paired-vector-memops"] =
+ Featu
[clang] 88874f0 - [PowerPC]Implement Vector Shift Double Bit Immediate Builtins
Author: Biplob Mishra
Date: 2020-07-01T20:34:53-05:00
New Revision: 88874f07464467f3852dd662d180f7738756649b
URL:
https://github.com/llvm/llvm-project/commit/88874f07464467f3852dd662d180f7738756649b
DIFF:
https://github.com/llvm/llvm-project/commit/88874f07464467f3852dd662d180f7738756649b.diff
LOG: [PowerPC]Implement Vector Shift Double Bit Immediate Builtins
Implement Vector Shift Double Bit Immediate Builtins in LLVM/Clang.
* vec_sldb ();
* vec_srdb ();
Differential Revision: https://reviews.llvm.org/D82440
Added:
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index fa5b0b9d0920..2a5ae08ea7b2 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -316,6 +316,10 @@ BUILTIN(__builtin_altivec_vclrrb, "V16cV16cUi", "")
BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "")
BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
+// P10 Vector Shift built-ins.
+BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
+BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
+
// VSX built-ins.
BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 91279119630d..85f712f18ef3 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16881,6 +16881,14 @@ vec_cnttzm(vector unsigned long long __a, vector
unsigned long long __b) {
return __builtin_altivec_vctzdm(__a, __b);
}
+/* vec_sldbi */
+
+#define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
+
+/* vec_srdbi */
+
+#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
+
#endif /* __POWER10_VECTOR__ */
#undef __ATTRS_o_ai
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index b4554c9fd55a..a8d25bd7e240 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3128,6 +3128,10 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
case PPC::BI__builtin_vsx_xxeval:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 255);
+ case PPC::BI__builtin_altivec_vsldbi:
+ return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
+ case PPC::BI__builtin_altivec_vsrdbi:
+ return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
}
return SemaBuiltinConstantArgRange(TheCall, i, l, u);
}
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index f7930667af79..efb63ce808cb 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -5,10 +5,13 @@
#include
-vector signed char vsca;
+vector signed char vsca, vscb;
vector unsigned char vuca, vucb, vucc;
+vector signed short vssa, vssb;
vector unsigned short vusa, vusb, vusc;
+vector signed int vsia, vsib;
vector unsigned int vuia, vuib, vuic;
+vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
vector unsigned __int128 vui128a, vui128b, vui128c;
unsigned int uia;
@@ -146,3 +149,111 @@ vector unsigned long long test_vctzdm(void) {
// CHECK-NEXT: ret <2 x i64>
return vec_cnttzm(vulla, vullb);
}
+
+vector signed char test_vec_sldb_sc(void) {
+ // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32 0
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_sldb(vsca, vscb, 0);
+ }
+
+vector unsigned char test_vec_sldb_uc(void) {
+ // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
1
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_sldb(vuca, vucb, 1);
+}
+
+vector signed short test_vec_sldb_ss(void) {
+ // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
2
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_sldb(vssa, vssb, 2);
+}
+
+vector unsigned short test_vec_sldb_us(void) {
+ // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
3
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_sldb(vusa, vusb, 3);
+}
+
+vector signed int test_vec_sldb_si(void) {
+ // CHECK: @llvm.ppc.altivec.vsldbi(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, i32
4
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_sldb(vsia, vsib, 4);
+}
+
+vector unsigned int test_vec_sldb_ui(void) {
+ // CHECK: @llvm.ppc
[clang] 2860734 - [PowerPC]Implement Vector Permute Extended Builtin
Author: Biplob Mishra
Date: 2020-07-02T14:53:18-05:00
New Revision: 286073484f7d36c8d0481be2a2f436f973389f54
URL:
https://github.com/llvm/llvm-project/commit/286073484f7d36c8d0481be2a2f436f973389f54
DIFF:
https://github.com/llvm/llvm-project/commit/286073484f7d36c8d0481be2a2f436f973389f54.diff
LOG: [PowerPC]Implement Vector Permute Extended Builtin
Implements vector permute builtin: vec_permx()
Differential Revision: https://reviews.llvm.org/D82869
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 2a5ae08ea7b2..10f2f2cdf0ee 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -451,6 +451,9 @@ BUILTIN(__builtin_vsx_xxsldwi, "v.", "t")
BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
+// P10 Vector Permute Extended built-in.
+BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")
+
// Float 128 built-ins
BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 85f712f18ef3..220f4f88f8e3 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16889,6 +16889,14 @@ vec_cnttzm(vector unsigned long long __a, vector
unsigned long long __b) {
#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
+#ifdef __VSX__
+
+/* vec_permx */
+
+#define vec_permx(__a, __b, __c, __d)
\
+ __builtin_vsx_xxpermx((__a), (__b), (__c), (__d))
+
+#endif /* __VSX__ */
#endif /* __POWER10_VECTOR__ */
#undef __ATTRS_o_ai
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index a8d25bd7e240..672fe77a3359 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3132,6 +3132,8 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
case PPC::BI__builtin_altivec_vsrdbi:
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
+ case PPC::BI__builtin_vsx_xxpermx:
+ return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
}
return SemaBuiltinConstantArgRange(TheCall, i, l, u);
}
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index efb63ce808cb..ecc470a289ce 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -14,6 +14,8 @@ vector unsigned int vuia, vuib, vuic;
vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
vector unsigned __int128 vui128a, vui128b, vui128c;
+vector float vfa, vfb;
+vector double vda, vdb;
unsigned int uia;
vector unsigned long long test_vpdepd(void) {
@@ -257,3 +259,71 @@ vector unsigned long long test_vec_srdb_ull(void) {
// CHECK-NEXT: ret <2 x i64>
return vec_srdb(vulla, vullb, 7);
}
+
+vector signed char test_vec_permx_sc(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_permx(vsca, vscb, vucc, 0);
+}
+
+vector unsigned char test_vec_permx_uc(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_permx(vuca, vucb, vucc, 1);
+}
+
+vector signed short test_vec_permx_ss(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_permx(vssa, vssb, vucc, 2);
+}
+
+vector unsigned short test_vec_permx_us(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <8 x i16>
+ // CHECK-NEXT: ret <8 x i16>
+ return vec_permx(vusa, vusb, vucc, 3);
+}
+
+vector signed int test_vec_permx_si(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_permx(vsia, vsib, vucc, 4);
+}
+
+vector unsigned int test_vec_permx_ui(void) {
+ // CHECK: @llvm.ppc.vsx.xxpermx(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16 x
i8> %{{.+}}, i32
+ // CHECK-NEXT: bitcast <16 x i8> %{{.*}} to <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_permx(v
[clang] ca46463 - [PowerPC] Implement Vector Blend Builtins in LLVM/Clang
Author: Biplob Mishra
Date: 2020-07-02T16:52:52-05:00
New Revision: ca464639a1c9dd3944eb055ffd2796e8c2e7639f
URL:
https://github.com/llvm/llvm-project/commit/ca464639a1c9dd3944eb055ffd2796e8c2e7639f
DIFF:
https://github.com/llvm/llvm-project/commit/ca464639a1c9dd3944eb055ffd2796e8c2e7639f.diff
LOG: [PowerPC] Implement Vector Blend Builtins in LLVM/Clang
Implements vec_blendv()
Differential Revision: https://reviews.llvm.org/D82774
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 10f2f2cdf0ee..856c862fb2a8 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -454,6 +454,12 @@ BUILTIN(__builtin_vsx_xxeval,
"V2ULLiV2ULLiV2ULLiV2ULLiIi", "")
// P10 Vector Permute Extended built-in.
BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "")
+// P10 Vector Blend built-ins.
+BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "")
+BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "")
+BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "")
+BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "")
+
// Float 128 built-ins
BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "")
BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 220f4f88f8e3..39eebb7274c0 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16896,6 +16896,65 @@ vec_cnttzm(vector unsigned long long __a, vector
unsigned long long __b) {
#define vec_permx(__a, __b, __c, __d)
\
__builtin_vsx_xxpermx((__a), (__b), (__c), (__d))
+/* vec_blendv */
+
+static __inline__ vector signed char __ATTRS_o_ai vec_blendv(
+vector signed char __a, vector signed char __b, vector unsigned char __c) {
+ return __builtin_vsx_xxblendvb(__a, __b, __c);
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_blendv(vector unsigned char __a, vector unsigned char __b,
+ vector unsigned char __c) {
+ return __builtin_vsx_xxblendvb(__a, __b, __c);
+}
+
+static __inline__ vector signed short __ATTRS_o_ai
+vec_blendv(vector signed short __a, vector signed short __b,
+ vector unsigned short __c) {
+ return __builtin_vsx_xxblendvh(__a, __b, __c);
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_blendv(vector unsigned short __a, vector unsigned short __b,
+ vector unsigned short __c) {
+ return __builtin_vsx_xxblendvh(__a, __b, __c);
+}
+
+static __inline__ vector signed int __ATTRS_o_ai
+vec_blendv(vector signed int __a, vector signed int __b,
+ vector unsigned int __c) {
+ return __builtin_vsx_xxblendvw(__a, __b, __c);
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_blendv(vector unsigned int __a, vector unsigned int __b,
+ vector unsigned int __c) {
+ return __builtin_vsx_xxblendvw(__a, __b, __c);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_blendv(vector signed long long __a, vector signed long long __b,
+ vector unsigned long long __c) {
+ return __builtin_vsx_xxblendvd(__a, __b, __c);
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_blendv(vector unsigned long long __a, vector unsigned long long __b,
+ vector unsigned long long __c) {
+ return __builtin_vsx_xxblendvd(__a, __b, __c);
+}
+
+static __inline__ vector float __ATTRS_o_ai
+vec_blendv(vector float __a, vector float __b, vector unsigned int __c) {
+ return __builtin_vsx_xxblendvw(__a, __b, __c);
+}
+
+static __inline__ vector double __ATTRS_o_ai
+vec_blendv(vector double __a, vector double __b,
+ vector unsigned long long __c) {
+ return __builtin_vsx_xxblendvd(__a, __b, __c);
+}
#endif /* __VSX__ */
#endif /* __POWER10_VECTOR__ */
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index ecc470a289ce..51f10280bfca 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -327,3 +327,65 @@ vector double test_vec_permx_d(void) {
// CHECK-NEXT: ret <2 x double>
return vec_permx(vda, vdb, vucc, 1);
}
+
+vector signed char test_vec_blend_sc(void) {
+ // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16
x i8>
+ // CHECK-NEXT: ret <16 x i8>
+ return vec_blendv(vsca, vscb, vucc);
+}
+
+vector unsigned char test_vec_blend_uc(void) {
+ // CHECK: @llvm.ppc.vsx.xxblendvb(<16 x i8> %{{.+}}, <16 x i8> %{{.+}}, <16
x i8>
+ // CHECK-
[clang] 0939e04 - [PowerPC] Implement Vector Insert Builtins in LLVM/Clang
Author: Biplob Mishra
Date: 2020-07-03T15:30:41-05:00
New Revision: 0939e04e417634f6d38ec4f06835fb80756afdd3
URL:
https://github.com/llvm/llvm-project/commit/0939e04e417634f6d38ec4f06835fb80756afdd3
DIFF:
https://github.com/llvm/llvm-project/commit/0939e04e417634f6d38ec4f06835fb80756afdd3.diff
LOG: [PowerPC] Implement Vector Insert Builtins in LLVM/Clang
Implements vec_insertl() and vec_inserth().
Differential Revision: https://reviews.llvm.org/D82365
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 856c862fb2a8..d0df5fcd1552 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -320,6 +320,22 @@ BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "")
BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "")
BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "")
+// P10 Vector Insert built-ins.
+BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "")
+BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcULLiV16Uc", "")
+BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsULLiV8Us", "")
+BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiULLiV4Ui", "")
+BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiULLiV4Ui", "")
+
// VSX built-ins.
BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 39eebb7274c0..38d5c00a7981 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16889,6 +16889,136 @@ vec_cnttzm(vector unsigned long long __a, vector
unsigned long long __b) {
#define vec_srdb(__a, __b, __c) __builtin_altivec_vsrdbi(__a, __b, (__c & 0x7))
+/* vec_insertl */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_insertl(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsbrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsblx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_insertl(unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_insertl(unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai vec_insertl(
+unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsdrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsdlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned char __ATTRS_o_ai vec_insertl(
+vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsbvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsbvlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai vec_insertl(
+vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinshvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinshvlx(__b, __c, __a);
+#endif
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_insertl(
+vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinswvrx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinswvlx(__b, __c, __a);
+#endif
+}
+
+/* vec_inserth */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_inserth(unsigned char __a, vector unsigned char __b, unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vinsblx(__b, __c, __a);
+#else
+ return __builtin_altivec_vinsbrx(__b, __c, __a);
+#endif
+}
+
+static __
[clang] e359ab1 - [PowerPC][NFC] Fix indentation
Author: Lei Huang
Date: 2020-07-03T16:47:24-05:00
New Revision: e359ab1eca5727ce4c688bb49323b8a09478d61c
URL:
https://github.com/llvm/llvm-project/commit/e359ab1eca5727ce4c688bb49323b8a09478d61c
DIFF:
https://github.com/llvm/llvm-project/commit/e359ab1eca5727ce4c688bb49323b8a09478d61c.diff
LOG: [PowerPC][NFC] Fix indentation
Added:
Modified:
clang/lib/Headers/altivec.h
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 38d5c00a7981..a63f2ee359fd 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16918,8 +16918,9 @@ vec_insertl(unsigned int __a, vector unsigned int __b,
unsigned int __c) {
#endif
}
-static __inline__ vector unsigned long long __ATTRS_o_ai vec_insertl(
-unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_insertl(unsigned long long __a, vector unsigned long long __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinsdrx(__b, __c, __a);
#else
@@ -16927,8 +16928,9 @@ static __inline__ vector unsigned long long
__ATTRS_o_ai vec_insertl(
#endif
}
-static __inline__ vector unsigned char __ATTRS_o_ai vec_insertl(
-vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_insertl(vector unsigned char __a, vector unsigned char __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinsbvrx(__b, __c, __a);
#else
@@ -16936,8 +16938,9 @@ static __inline__ vector unsigned char __ATTRS_o_ai
vec_insertl(
#endif
}
-static __inline__ vector unsigned short __ATTRS_o_ai vec_insertl(
-vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_insertl(vector unsigned short __a, vector unsigned short __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinshvrx(__b, __c, __a);
#else
@@ -16945,8 +16948,9 @@ static __inline__ vector unsigned short __ATTRS_o_ai
vec_insertl(
#endif
}
-static __inline__ vector unsigned int __ATTRS_o_ai vec_insertl(
-vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_insertl(vector unsigned int __a, vector unsigned int __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinswvrx(__b, __c, __a);
#else
@@ -16983,8 +16987,9 @@ vec_inserth(unsigned int __a, vector unsigned int __b,
unsigned int __c) {
#endif
}
-static __inline__ vector unsigned long long __ATTRS_o_ai vec_inserth(
-unsigned long long __a, vector unsigned long long __b, unsigned int __c) {
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_inserth(unsigned long long __a, vector unsigned long long __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinsdlx(__b, __c, __a);
#else
@@ -16992,8 +16997,9 @@ static __inline__ vector unsigned long long
__ATTRS_o_ai vec_inserth(
#endif
}
-static __inline__ vector unsigned char __ATTRS_o_ai vec_inserth(
-vector unsigned char __a, vector unsigned char __b, unsigned int __c) {
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_inserth(vector unsigned char __a, vector unsigned char __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinsbvlx(__b, __c, __a);
#else
@@ -17001,8 +17007,9 @@ static __inline__ vector unsigned char __ATTRS_o_ai
vec_inserth(
#endif
}
-static __inline__ vector unsigned short __ATTRS_o_ai vec_inserth(
-vector unsigned short __a, vector unsigned short __b, unsigned int __c) {
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_inserth(vector unsigned short __a, vector unsigned short __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinshvlx(__b, __c, __a);
#else
@@ -17010,8 +17017,9 @@ static __inline__ vector unsigned short __ATTRS_o_ai
vec_inserth(
#endif
}
-static __inline__ vector unsigned int __ATTRS_o_ai vec_inserth(
-vector unsigned int __a, vector unsigned int __b, unsigned int __c) {
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_inserth(vector unsigned int __a, vector unsigned int __b,
+unsigned int __c) {
#ifdef __LITTLE_ENDIAN__
return __builtin_altivec_vinswvlx(__b, __c, __a);
#else
@@ -17028,8 +17036,9 @@ static __inline__ vector unsigned int __ATTRS_o_ai
vec_inserth(
/* vec_blendv */
-static __inline__ vector signed char __ATTRS_o_ai vec_blendv(
-vector signed char __a, vector signed char __b, vector unsigned char __c) {
+static __inline__ vector signed char __ATTRS_o_ai
+vec_blendv(vector signed char __a, vector signed ch
[clang] 0c6b6e2 - [PowerPC] Implement Vector Splat Immediate Builtins in Clang
Author: Biplob Mishra
Date: 2020-07-06T20:29:33-05:00
New Revision: 0c6b6e28e70c06a3cb4704d2d8f90829a689e230
URL:
https://github.com/llvm/llvm-project/commit/0c6b6e28e70c06a3cb4704d2d8f90829a689e230
DIFF:
https://github.com/llvm/llvm-project/commit/0c6b6e28e70c06a3cb4704d2d8f90829a689e230.diff
LOG: [PowerPC] Implement Vector Splat Immediate Builtins in Clang
Implements builtins for the following prototypes:
vector signed int vec_splati (const signed int);
vector float vec_splati (const float);
vector double vec_splatid (const float);
vector signed int vec_splati_ins (vector signed int, const unsigned int,
const signed int);
vector unsigned int vec_splati_ins (vector unsigned int, const unsigned int,
const unsigned int);
vector float vec_splati_ins (vector float, const unsigned int, const float);
Differential Revision: https://reviews.llvm.org/D82520
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/test/CodeGen/PowerPC/p10-splatImm.ll
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index a63f2ee359fd..9a4009216930 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17094,6 +17094,58 @@ vec_blendv(vector double __a, vector double __b,
vector unsigned long long __c) {
return __builtin_vsx_xxblendvd(__a, __b, __c);
}
+
+/* vec_splati */
+
+#define vec_splati(__a)
\
+ _Generic((__a), signed int
\
+ : ((vector signed int)__a), unsigned int
\
+ : ((vector unsigned int)__a), float
\
+ : ((vector float)__a))
+
+/* vec_spatid */
+
+static __inline__ vector double __ATTRS_o_ai vec_splatid(const float __a) {
+ return ((vector double)((double)__a));
+}
+
+/* vec_splati_ins */
+
+static __inline__ vector signed int __ATTRS_o_ai vec_splati_ins(
+vector signed int __a, const unsigned int __b, const signed int __c) {
+#ifdef __LITTLE_ENDIAN__
+ __a[1 - __b] = __c;
+ __a[3 - __b] = __c;
+#else
+ __a[__b] = __c;
+ __a[2 + __b] = __c;
+#endif
+ return __a;
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai vec_splati_ins(
+vector unsigned int __a, const unsigned int __b, const unsigned int __c) {
+#ifdef __LITTLE_ENDIAN__
+ __a[1 - __b] = __c;
+ __a[3 - __b] = __c;
+#else
+ __a[__b] = __c;
+ __a[2 + __b] = __c;
+#endif
+ return __a;
+}
+
+static __inline__ vector float __ATTRS_o_ai
+vec_splati_ins(vector float __a, const unsigned int __b, const float __c) {
+#ifdef __LITTLE_ENDIAN__
+ __a[1 - __b] = __c;
+ __a[3 - __b] = __c;
+#else
+ __a[__b] = __c;
+ __a[2 + __b] = __c;
+#endif
+ return __a;
+}
#endif /* __VSX__ */
#endif /* __POWER10_VECTOR__ */
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index b0602dd66f53..22b4e7a6f3ec 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -512,3 +512,72 @@ vector unsigned int test_vec_inserth_uiv(void) {
// CHECK-LE-NEXT: ret <4 x i32>
return vec_inserth(vuia, vuib, uia);
}
+
+vector signed int test_vec_vec_splati_si(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(-17);
+}
+
+vector unsigned int test_vec_vec_splati_ui(void) {
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: ret <4 x i32>
+ return vec_splati(16U);
+}
+
+vector float test_vec_vec_splati_f(void) {
+ // CHECK-BE: ret <4 x float>
+ // CHECK: ret <4 x float>
+ return vec_splati(1.0f);
+}
+
+vector double test_vec_vec_splatid(void) {
+ // CHECK-BE: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-BE-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double
[[T1:%.+]], i32 0
+ // CHECK-BE-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x
double> undef, <2 x i32> zeroinitialize
+ // CHECK-BE-NEXT: ret <2 x double> [[T3:%.+]]
+ // CHECK: [[T1:%.+]] = fpext float %{{.+}} to double
+ // CHECK-NEXT: [[T2:%.+]] = insertelement <2 x double> undef, double
[[T1:%.+]], i32 0
+ // CHECK-NEXT: [[T3:%.+]] = shufflevector <2 x double> [[T2:%.+]], <2 x
double> undef, <2 x i32> zeroinitialize
+ // CHECK-NEXT: ret <2 x double> [[T3:%.+]]
+ return vec_splatid(1.0);
+}
+
+vector signed int test_vec_vec_splati_ins_si(void) {
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 %{{.+}}
+ // CHECK-BE: [[T1:%.+]] = add i32 2, %{{.+}}
+ // CHECK-BE: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK-BE: ret <4 x i32>
+ // CHECK: [[T1:%.+]] = sub i32 1, %{{.+}}
+ // CHECK: insertelement <4 x i32> %{{.+}}, i32 %{{.+}}, i32 [[T1]]
+ // CHECK: [[T2:%.+]] = sub i32 3, %{{.+}}
[clang] 10b60dd - [PowerPC] Refactor ppcUserFeaturesCheck()
Author: Lei Huang
Date: 2020-04-17T15:19:46-05:00
New Revision: 10b60dde767011c250649dc6a305379034c5b5c5
URL:
https://github.com/llvm/llvm-project/commit/10b60dde767011c250649dc6a305379034c5b5c5
DIFF:
https://github.com/llvm/llvm-project/commit/10b60dde767011c250649dc6a305379034c5b5c5.diff
LOG: [PowerPC] Refactor ppcUserFeaturesCheck()
Summary: This function keeps growing, refactor to use lambda.
Reviewers: nemanjai, stefanp
Subscribers: kbarton, shchenz, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D78308
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-dependent-options.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 1877d4a5ef70..81c13a8104e8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -228,33 +228,25 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
const std::vector &FeaturesVec) {
- if (llvm::find(FeaturesVec, "-vsx") != FeaturesVec.end()) {
-if (llvm::find(FeaturesVec, "+power8-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+direct-move") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
- << "-mno-vsx";
- return false;
-}
-
-if (llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128"
- << "-mno-vsx";
- return false;
+ // vsx was not explicitly turned off.
+ if (llvm::find(FeaturesVec, "-vsx") == FeaturesVec.end())
+return true;
+
+ auto FindVSXSubfeature = [&](StringRef Feature, StringRef Option) {
+if (llvm::find(FeaturesVec, Feature) != FeaturesVec.end()) {
+ Diags.Report(diag::err_opt_not_valid_with_opt) << Option << "-mno-vsx";
+ return true;
}
+return false;
+ };
-if (llvm::find(FeaturesVec, "+power9-vector") != FeaturesVec.end()) {
- Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector"
- << "-mno-vsx";
- return false;
-}
- }
+ bool Found = FindVSXSubfeature("+power8-vector", "-mpower8-vector");
+ Found |= FindVSXSubfeature("+direct-move", "-mdirect-move");
+ Found |= FindVSXSubfeature("+float128", "-mfloat128");
+ Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
- return true;
+ // Return false if any vsx subfeatures was found.
+ return !Found;
}
bool PPCTargetInfo::initFeatureMap(
diff --git a/clang/test/Driver/ppc-dependent-options.cpp
b/clang/test/Driver/ppc-dependent-options.cpp
index 9fb812dc218f..c089422c68b9 100644
--- a/clang/test/Driver/ppc-dependent-options.cpp
+++ b/clang/test/Driver/ppc-dependent-options.cpp
@@ -54,6 +54,10 @@
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-FLT128
+// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
+// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
+
#ifdef __VSX__
static_assert(false, "VSX enabled");
#endif
@@ -78,5 +82,7 @@ static_assert(false, "Neither enabled");
// CHECK-NVSX-P9V: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-FLT128: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
// CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with
'-mno-vsx'
+// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with
'-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled
___
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[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/75226
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input of
type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
>From b815b9b0a369f308cf24406fa9606cb6e3b1c7e3 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 16 +++-
.../c.math/constexpr-cxx23-clang.pass.cpp| 6 --
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 83d0a72aac5495..7a700155149e8f 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+&getTarget().getLongDoubleFormat() == &llvm::APFloat::PPCDoubleDouble()
+&& PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3418,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca5..a07260a34516f1 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
___
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[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/75226
>From 2e6a96f141cd103fa40b6926c1d9f0af58c6e72b Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 17 -
.../c.math/constexpr-cxx23-clang.pass.cpp | 6 --
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 83d0a72aac549..b9c752d8d0a22 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+ &getTarget().getLongDoubleFormat() ==
+ &llvm::APFloat::PPCDoubleDouble() &&
+ PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3419,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca..a07260a34516f 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
___
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[libcxx] [clang] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
lei137 wrote: > How hard is it to fix the backend to handle this properly? We should already > have support for other libcalls, I think. I'd like to avoid adding temporary > hacks to clang. @efriedma-quic The original failure is becaues we are producing illegal types after type legalization (i.e. during operation legalization). To fix this in the backend we need to properly handle PPC double-double. I've spoken with the PPC code owner and it was decided that since PPC double-double is a dying type and we are not looking to add more support for it, we would just fix this in the front-end. Work is currently underway to switch to use IEEE Double instead of PPC Double Double by default on PPC. This failure was introduced in https://reviews.llvm.org/D136538 and wasn't caught for PPC since we did not have libc++ builds as part of our bots. That issue have been addressed and our bots now include building of libc++. Hopefully this is something that is acceptable to you. https://github.com/llvm/llvm-project/pull/75226 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const FunctionDecl *FD, &getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() && F128Builtins.contains(BuiltinID)) Name = F128Builtins[BuiltinID]; +else if (getTriple().isPPC() && getTriple().isOSLinux() && + &getTarget().getLongDoubleFormat() == + &llvm::APFloat::PPCDoubleDouble() && + PPCDoubleDoubleBuiltins.contains(BuiltinID)) + Name = PPCDoubleDoubleBuiltins[BuiltinID]; lei137 wrote: I didn't realize that. Thanks for pointing it out. https://github.com/llvm/llvm-project/pull/75226 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libcxx] [clang] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/75226
>From 2e6a96f141cd103fa40b6926c1d9f0af58c6e72b Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH 1/2] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 17 -
.../c.math/constexpr-cxx23-clang.pass.cpp | 6 --
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 83d0a72aac5495..b9c752d8d0a22e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+ &getTarget().getLongDoubleFormat() ==
+ &llvm::APFloat::PPCDoubleDouble() &&
+ PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3419,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca5..a07260a34516f1 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
>From b1d13ea91b289c87c0ec52d2947c811f140e5a85 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Thu, 14 Dec 2023 09:28:50 -0600
Subject: [PATCH 2/2] address Eli's review comments
---
clang/lib/CodeGen/CGBuiltin.cpp | 15 ---
clang/test/CodeGen/math-builtins-long.c | 2 +-
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index b9c752d8d0a22e..f97b6ef680810e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,10 +137,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
- static SmallDenseMap PPCDoubleDoubleBuiltins{
- {Builtin::BI__builtin_frexpl, "frexpl"},
- };
-
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -153,11 +149,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F1
[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/75226
>From 2e6a96f141cd103fa40b6926c1d9f0af58c6e72b Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH 1/3] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 17 -
.../c.math/constexpr-cxx23-clang.pass.cpp | 6 --
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 83d0a72aac5495..b9c752d8d0a22e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+ &getTarget().getLongDoubleFormat() ==
+ &llvm::APFloat::PPCDoubleDouble() &&
+ PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3419,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca5..a07260a34516f1 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
>From b1d13ea91b289c87c0ec52d2947c811f140e5a85 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Thu, 14 Dec 2023 09:28:50 -0600
Subject: [PATCH 2/3] address Eli's review comments
---
clang/lib/CodeGen/CGBuiltin.cpp | 15 ---
clang/test/CodeGen/math-builtins-long.c | 2 +-
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index b9c752d8d0a22e..f97b6ef680810e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,10 +137,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
- static SmallDenseMap PPCDoubleDoubleBuiltins{
- {Builtin::BI__builtin_frexpl, "frexpl"},
- };
-
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -153,11 +149,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F1
[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/75226
>From 6819814317367cf7fc944a5a1ecedd357bc3cd0a Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH 1/3] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 17 -
.../c.math/constexpr-cxx23-clang.pass.cpp | 6 --
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 353b7930b3c1ea..e733bbf8be8b71 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+ &getTarget().getLongDoubleFormat() ==
+ &llvm::APFloat::PPCDoubleDouble() &&
+ PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3419,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca5..a07260a34516f1 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
>From d230bb9f415f9adf4099ef911459b67c692ccd3e Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Thu, 14 Dec 2023 09:28:50 -0600
Subject: [PATCH 2/3] address Eli's review comments
---
clang/lib/CodeGen/CGBuiltin.cpp | 15 ---
clang/test/CodeGen/math-builtins-long.c | 2 +-
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e733bbf8be8b71..73df0ef99f853c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,10 +137,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
- static SmallDenseMap PPCDoubleDoubleBuiltins{
- {Builtin::BI__builtin_frexpl, "frexpl"},
- };
-
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -153,11 +149,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F1
[clang] [libcxx] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/75226
>From f38e709e414d1c9dae4f9d75f1decaf363bf9427 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Tue, 12 Dec 2023 10:58:34 -0600
Subject: [PATCH 1/3] [PowerPC] Emit libcall to frexpl for calls to
frexp(ppcDoublDouble)
On Linux PPC call lib func ``frexpl`` for calls to ``frexp()`` for input
of type PPCDoubleDouble.
Fixes bug: https://github.com/llvm/llvm-project/issues/64426
---
clang/lib/CodeGen/CGBuiltin.cpp | 17 -
.../c.math/constexpr-cxx23-clang.pass.cpp | 6 --
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 353b7930b3c1ea..e733bbf8be8b71 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,6 +137,10 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
+ static SmallDenseMap PPCDoubleDoubleBuiltins{
+ {Builtin::BI__builtin_frexpl, "frexpl"},
+ };
+
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -149,6 +153,11 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F128Builtins[BuiltinID];
+else if (getTriple().isPPC() && getTriple().isOSLinux() &&
+ &getTarget().getLongDoubleFormat() ==
+ &llvm::APFloat::PPCDoubleDouble() &&
+ PPCDoubleDoubleBuiltins.contains(BuiltinID))
+ Name = PPCDoubleDoubleBuiltins[BuiltinID];
else if (getTriple().isOSAIX() &&
&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::IEEEdouble() &&
@@ -3410,9 +3419,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
{ Src0->getType(), Src1->getType() });
return RValue::get(Builder.CreateCall(F, { Src0, Src1 }));
}
+ case Builtin::BI__builtin_frexpl: {
+auto &Triple = getTarget().getTriple();
+if (Triple.isPPC() && Triple.isOSLinux() &&
+&getTarget().getLongDoubleFormat() ==
&llvm::APFloat::PPCDoubleDouble())
+ break;
+LLVM_FALLTHROUGH;
+ }
case Builtin::BI__builtin_frexp:
case Builtin::BI__builtin_frexpf:
- case Builtin::BI__builtin_frexpl:
case Builtin::BI__builtin_frexpf128:
case Builtin::BI__builtin_frexpf16:
return RValue::get(emitFrexpBuiltin(*this, E, Intrinsic::frexp));
diff --git a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
index 31511064ce7ca5..a07260a34516f1 100644
--- a/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
+++ b/libcxx/test/libcxx/numerics/c.math/constexpr-cxx23-clang.pass.cpp
@@ -58,15 +58,9 @@ int main(int, char**) {
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0f, &DummyInt) == 0.0f);
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0, &DummyInt) == 0.0);
-//FIXME: currently linux powerpc does not support this expansion
-// since 0.0L lowers to ppcf128 and special handling is required.
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexp(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpf(0.0f, &DummyInt) == 0.0f);
-#if !defined(__LONG_DOUBLE_IBM128__)
ASSERT_NOT_CONSTEXPR_CXX23(std::frexpl(0.0L, &DummyInt) == 0.0L);
-#endif
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0f) == 0);
ASSERT_NOT_CONSTEXPR_CXX23(std::ilogb(1.0) == 0);
>From 3065e1287b5be023e8e9bf85ff2b76d6c194f58c Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Thu, 14 Dec 2023 09:28:50 -0600
Subject: [PATCH 2/3] address Eli's review comments
---
clang/lib/CodeGen/CGBuiltin.cpp | 15 ---
clang/test/CodeGen/math-builtins-long.c | 2 +-
2 files changed, 5 insertions(+), 12 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index e733bbf8be8b71..73df0ef99f853c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -137,10 +137,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
{Builtin::BI__builtin_modfl, "modf"},
};
- static SmallDenseMap PPCDoubleDoubleBuiltins{
- {Builtin::BI__builtin_frexpl, "frexpl"},
- };
-
// If the builtin has been declared explicitly with an assembler label,
// use the mangled name. This differs from the plain label on platforms
// that prefix labels.
@@ -153,11 +149,6 @@ llvm::Constant *CodeGenModule::getBuiltinLibFunction(const
FunctionDecl *FD,
&getTarget().getLongDoubleFormat() == &llvm::APFloat::IEEEquad() &&
F128Builtins.contains(BuiltinID))
Name = F1
[libcxx] [clang] [PowerPC] Emit libcall to frexpl for calls to frexp(ppcDoublDouble) (PR #75226)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/75226 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] caf7243 - [PowerPC] Fix signatures for vec_replace_unaligned builtin
Author: Lei Huang
Date: 2022-06-29T09:35:52-05:00
New Revision: caf7243a6b53aa16f9fbdfbaa18096defb2eb374
URL:
https://github.com/llvm/llvm-project/commit/caf7243a6b53aa16f9fbdfbaa18096defb2eb374
DIFF:
https://github.com/llvm/llvm-project/commit/caf7243a6b53aa16f9fbdfbaa18096defb2eb374.diff
LOG: [PowerPC] Fix signatures for vec_replace_unaligned builtin
``vec_replace_unaligned`` is meant to return vuc to emphasize that elements
are being inserted on unnatural boundaries.
Reviewed By: amyk, quinnp
Differential Revision: https://reviews.llvm.org/D128288
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
clang/test/CodeGen/PowerPC/builtins-ppc-vec-ins-error.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 4c3ec59d31b34..0b1e76e81cc77 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -18966,23 +18966,23 @@ vec_blendv(vector double __a, vector double __b,
#define vec_replace_unaligned(__a, __b, __c)
\
_Generic((__a), vector signed int
\
- : (vector signed int)__builtin_altivec_vinsw(
\
- (vector unsigned char)__a, (unsigned int)__b, __c),
\
+ : __builtin_altivec_vinsw((vector unsigned char)__a,
\
+ (unsigned int)__b, __c),
\
vector unsigned int
\
- : (vector unsigned int)__builtin_altivec_vinsw(
\
- (vector unsigned char)__a, (unsigned int)__b, __c),
\
+ : __builtin_altivec_vinsw((vector unsigned char)__a,
\
+ (unsigned int)__b, __c),
\
vector unsigned long long
\
- : (vector unsigned long long)__builtin_altivec_vinsd(
\
- (vector unsigned char)__a, (unsigned long long)__b, __c),
\
+ : __builtin_altivec_vinsd((vector unsigned char)__a,
\
+ (unsigned long long)__b, __c),
\
vector signed long long
\
- : (vector signed long long)__builtin_altivec_vinsd(
\
- (vector unsigned char)__a, (unsigned long long)__b, __c),
\
+ : __builtin_altivec_vinsd((vector unsigned char)__a,
\
+ (unsigned long long)__b, __c),
\
vector float
\
- : (vector float)__builtin_altivec_vinsw((vector unsigned char)__a,
\
- (unsigned int)__b, __c),
\
+ : __builtin_altivec_vinsw((vector unsigned char)__a,
\
+ (unsigned int)__b, __c),
\
vector double
\
- : (vector double)__builtin_altivec_vinsd(
\
- (vector unsigned char)__a, (unsigned long long)__b, __c))
+ : __builtin_altivec_vinsd((vector unsigned char)__a,
\
+ (unsigned long long)__b, __c))
#define vec_replace_elt(__a, __b, __c)
\
_Generic((__a), vector signed int
\
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
index c7e9e1a9237f5..c76298a4f0f98 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-p10vector.c
@@ -1183,8 +1183,7 @@ vector double test_vec_replace_elt_d(void) {
// CHECK-BE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-BE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4
x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-BE-NEXT:[[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <16 x i8>
-// CHECK-BE-NEXT:[[TMP6:%.*]] = bitcast <16 x i8> [[TMP5]] to <4 x i32>
-// CHECK-BE-NEXT:ret <4 x i32> [[TMP6]]
+// CHECK-BE-NEXT:ret <16 x i8> [[TMP5]]
//
// CHECK-LE-LABEL: @test_vec_replace_unaligned_si(
// CHECK-LE-NEXT: entry:
@@ -1194,10 +1193,9 @@ vector double test_vec_replace_elt_d(void) {
// CHECK-LE-NEXT:[[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT:[[TMP4:%.*]] = call <4 x i32> @llvm.ppc.altivec.vinsw(<4
x i32> [[TMP3]], i32 [[TMP2]], i32 6)
// CHECK-LE-NEXT:[[TMP5:%.*]] = bitcast <4 x i3
[clang] c8937b6 - [PowerPC] Implement XL compact math builtins
Author: Lei Huang
Date: 2021-07-16T13:21:13-05:00
New Revision: c8937b6cb9751807de1e69f0f0f70a9a58f8f5dc
URL:
https://github.com/llvm/llvm-project/commit/c8937b6cb9751807de1e69f0f0f70a9a58f8f5dc
DIFF:
https://github.com/llvm/llvm-project/commit/c8937b6cb9751807de1e69f0f0f70a9a58f8f5dc.diff
LOG: [PowerPC] Implement XL compact math builtins
Implement a subset of builtins required for compatiblilty with AIX XL compiler.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D105930
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index f7f34122f17db..1c83c59e16233 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -29,7 +29,7 @@
#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) \
CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE)
-// builtins for compatibility with the XL compiler
+// XL Compatibility built-ins
BUILTIN(__builtin_ppc_popcntb, "ULiULi", "")
BUILTIN(__builtin_ppc_poppar4, "iUi", "")
BUILTIN(__builtin_ppc_poppar8, "iULLi", "")
@@ -97,6 +97,21 @@ BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "")
BUILTIN(__builtin_ppc_store2r, "vUiUs*", "")
BUILTIN(__builtin_ppc_store4r, "vUiUi*", "")
BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "")
+BUILTIN(__builtin_ppc_extract_exp, "Uid", "")
+BUILTIN(__builtin_ppc_extract_sig, "ULLid", "")
+BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
+BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
+BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
+BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
+BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "")
+BUILTIN(__builtin_ppc_fmsub, "", "")
+BUILTIN(__builtin_ppc_fmsubs, "", "")
+BUILTIN(__builtin_ppc_fnmadd, "", "")
+BUILTIN(__builtin_ppc_fnmadds, "", "")
+BUILTIN(__builtin_ppc_fnmsub, "", "")
+BUILTIN(__builtin_ppc_fnmsubs, "", "")
+BUILTIN(__builtin_ppc_fre, "dd", "")
+BUILTIN(__builtin_ppc_fres, "ff", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 84cd3d4db0280..10af8494c44ec 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -151,6 +151,21 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__store2r", "__builtin_ppc_store2r");
Builder.defineMacro("__store4r", "__builtin_ppc_store4r");
Builder.defineMacro("__store8r", "__builtin_ppc_store8r");
+ Builder.defineMacro("__extract_exp", "__builtin_ppc_extract_exp");
+ Builder.defineMacro("__extract_sig", "__builtin_ppc_extract_sig");
+ Builder.defineMacro("__mtfsb0", "__builtin_ppc_mtfsb0");
+ Builder.defineMacro("__mtfsb1", "__builtin_ppc_mtfsb1");
+ Builder.defineMacro("__mtfsf", "__builtin_ppc_mtfsf");
+ Builder.defineMacro("__mtfsfi", "__builtin_ppc_mtfsfi");
+ Builder.defineMacro("__insert_exp", "__builtin_ppc_insert_exp");
+ Builder.defineMacro("__fmsub", "__builtin_ppc_fmsub");
+ Builder.defineMacro("__fmsubs", "__builtin_ppc_fmsubs");
+ Builder.defineMacro("__fnmadd", "__builtin_ppc_fnmadd");
+ Builder.defineMacro("__fnmadds", "__builtin_ppc_fnmadds");
+ Builder.defineMacro("__fnmsub", "__builtin_ppc_fnmsub");
+ Builder.defineMacro("__fnmsubs", "__builtin_ppc_fnmsubs");
+ Builder.defineMacro("__fre", "__builtin_ppc_fre");
+ Builder.defineMacro("__fres", "__builtin_ppc_fres");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 849444fc4c25c..cf9a954fd2a23 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3278,6 +3278,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_ppc_maddld:
case PPC::BI__builtin_ppc_load8r:
case PPC::BI__builtin_ppc_store8r:
+ case PPC::BI__builtin_ppc_insert_exp:
+ case PPC::BI__builtin_ppc_extract_sig:
return true;
}
return false;
@@ -3414,6 +3416,19 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
case PPC::BI__builtin_ppc_rldimi:
return SemaBuiltinConstantArg(TheCall, 2, Result) ||
SemaValueIsRunOfOnes(TheCall, 3);
+ ca
[clang] 35a18a9 - [PowerPC] Implement intrinsics for mtfsf[i]
Author: Nemanja Ivanovic
Date: 2021-07-16T16:26:11-05:00
New Revision: 35a18a981f6b0f67899baec46be0086dc1aad757
URL:
https://github.com/llvm/llvm-project/commit/35a18a981f6b0f67899baec46be0086dc1aad757
DIFF:
https://github.com/llvm/llvm-project/commit/35a18a981f6b0f67899baec46be0086dc1aad757.diff
LOG: [PowerPC] Implement intrinsics for mtfsf[i]
This provides intrinsics for emitting instructions that set the FPSCR
(`mtfsf/mtfsfi`).
The patch also conservatively marks the rounding mode as an implicit def for
both since they both may set the rounding mode depending on the operands.
Reviewed By: #powerpc, qiucf
Differential Revision: https://reviews.llvm.org/D105957
Added:
llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-math.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ce238d7ee9374..7896b2a05a09a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15620,6 +15620,13 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Function *F = CGM.getIntrinsic(Intrinsic::ppc_popcntb, {ArgType, ArgType});
return Builder.CreateCall(F, Ops, "popcntb");
}
+ case PPC::BI__builtin_ppc_mtfsf: {
+// The builtin takes a uint32 that needs to be cast to an
+// f64 to be passed to the intrinsic.
+Value *Cast = Builder.CreateUIToFP(Ops[1], DoubleTy);
+llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtfsf);
+return Builder.CreateCall(F, {Ops[0], Cast}, "");
+ }
}
}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-math.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-math.c
index f1bd56b41e909..4895353686afe 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-math.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-math.c
@@ -24,10 +24,8 @@ void mtfsb1 () {
}
// CHECK-LABEL: @mtfsf(
-// CHECK: [[UI_ADDR:%.*]] = alloca i32, align 4
-// CHECK-NEXT:store i32 [[UI:%.*]], i32* [[UI_ADDR]], align 4
-// CHECK-NEXT:[[TMP0:%.*]] = load i32, i32* [[UI_ADDR]], align 4
-// CHECK-NEXT:call void @llvm.ppc.mtfsf(i32 8, i32 [[TMP0]])
+// CHECK: [[TMP0:%.*]] = uitofp i32 %{{.*}} to double
+// CHECK-NEXT:call void @llvm.ppc.mtfsf(i32 8, double [[TMP0]])
// CHECK-NEXT:ret void
//
void mtfsf (unsigned int ui) {
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index cc16f61245e9b..f494da3944344 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1636,9 +1636,8 @@ let TargetPrefix = "ppc" in {
: GCCBuiltin<"__builtin_ppc_mtfsb1">,
Intrinsic <[], [llvm_i32_ty],
[IntrNoMem, IntrHasSideEffects, ImmArg>]>;
- def int_ppc_mtfsf
- : GCCBuiltin<"__builtin_ppc_mtfsf">,
-Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
+ def int_ppc_mtfsf :
+Intrinsic <[], [llvm_i32_ty, llvm_double_ty],
[IntrNoMem, IntrHasSideEffects, ImmArg>]>;
def int_ppc_mtfsfi
: GCCBuiltin<"__builtin_ppc_mtfsfi">,
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td
b/llvm/lib/Target/PowerPC/P9InstrResources.td
index 8ef621c978661..04777bacca455 100644
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -1079,7 +1079,8 @@ def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C,
IP_EXEC_1C,
DISP_3SLOTS_1C, DISP_3SLOTS_1C],
(instrs
(instregex "MTFSF(b|_rec)?$"),
-(instregex "MTFSFI(_rec)?$")
+(instregex "MTFSFI(_rec)?$"),
+MTFSFIb
)>;
// Cracked instruction made of two ALU ops.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index b238520612d55..b9a8d8ffe7bcc 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3103,7 +3103,8 @@ def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
let Defs = [RM] in {
let isCodeGenOnly = 1 in
def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT),
-"mtfsf $FM, $rT", IIC_IntMTFSB0, []>,
+"mtfsf $FM, $rT", IIC_IntMTFSB0,
+[(int_ppc_mtfsf timm:$FM, f64:$rT)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
}
let Uses = [RM] in {
@@ -4483,19 +4484,20 @@ def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins
gprc:$RS, u1imm:$L),
def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
"mcrfs $BF, $BFA", IIC_BrMCR>;
-// If W is 0 and BF is 7, the 60:63 bits will be set, we should set the
-// im
[clang] [clang-format][NFC] Make LangOpts global in namespace Format (PR #81390)
lei137 wrote: @owenca This PR broke the following PowerPC bots: * https://lab.llvm.org/buildbot/#/builders/230 * https://lab.llvm.org/buildbot/#/builders/121 But the rhel both https://lab.llvm.org/buildbot/#/builders/57 is fine. AFAIK the only difference between these bots is that builder 57 is RHEL and 230/121 is Ubuntu. Please let us know if you are able to provide a quick fix. If not, please revert. https://github.com/llvm/llvm-project/pull/81390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
lei137 wrote:
Hi Aokamal,
This maco was not taken into account in the implementation. Can you please open
a bug and assign the issue to nemanjai?
Thank-you for reporting this.
Regards,
Lei
From: Aokamal ***@***.***>
Date: Tuesday, January 30, 2024 at 10:30 AM
To: llvm/llvm-project ***@***.***>
Cc: Lei Huang ***@***.***>, State change ***@***.***>
Subject: [EXTERNAL] Re: [llvm/llvm-project] [PowerPC][X86] Make cpu id builtins
target independent and lower for PPC (PR #68919)
Hi, Sorry I kind of don't know much about the change. We have the following
code snippet #if ABSL_HAVE_BUILTIN(__builtin_cpu_supports) if
(__builtin_cpu_supports("avx2")) { .. . } #endif when run with arm cpu, it
fails with error: builtin is
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Hi,
Sorry I kind of don't know much about the change. We have the following code
snippet
#if ABSL_HAVE_BUILTIN(__builtin_cpu_supports)
if (__builtin_cpu_supports("avx2")) {
...
}
#endif
when run with arm cpu, it fails with error: builtin is not supported on this
target on the second if. Does it mean ABSL_HAVE_BUILTIN is not accurate here ?
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[clang] [Preprocessor] Fix __has_builtin for CPU ID functions (PR #80058)
https://github.com/lei137 approved this pull request. LGTM Thx for the quick fix. https://github.com/llvm/llvm-project/pull/80058 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC][X86] Make cpu id builtins target independent and lower for PPC (PR #68919)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/68919 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 9469ff1 - [PowerPC] Add clang option -m[no-]prefixed
Author: Lei Huang
Date: 2021-05-13T12:02:10-05:00
New Revision: 9469ff15b77905245e26fe7f166fc127d813a0c0
URL:
https://github.com/llvm/llvm-project/commit/9469ff15b77905245e26fe7f166fc127d813a0c0
DIFF:
https://github.com/llvm/llvm-project/commit/9469ff15b77905245e26fe7f166fc127d813a0c0.diff
LOG: [PowerPC] Add clang option -m[no-]prefixed
Add user-facing front end option to turn off power10 prefixed instructions.
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D102191
Added:
clang/test/Driver/ppc-prefixed.cpp
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 78cc0a4e53a5f..1fda2dac0f76f 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3254,6 +3254,8 @@ def maltivec : Flag<["-"], "maltivec">,
Group;
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
def mpcrel: Flag<["-"], "mpcrel">, Group;
def mno_pcrel: Flag<["-"], "mno-pcrel">, Group;
+def mprefixed: Flag<["-"], "mprefixed">, Group;
+def mno_prefixed: Flag<["-"], "mno-prefixed">, Group;
def mspe : Flag<["-"], "mspe">, Group;
def mno_spe : Flag<["-"], "mno-spe">, Group;
def mefpu2 : Flag<["-"], "mefpu2">, Group;
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index cd8cc1aed39ea..cc16934292203 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -56,6 +56,8 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
HasP10Vector = true;
} else if (Feature == "+pcrelative-memops") {
HasPCRelativeMemops = true;
+} else if (Feature == "+prefix-instrs") {
+ HasPrefixInstrs = true;
} else if (Feature == "+spe" || Feature == "+efpu2") {
HasSPE = true;
LongDoubleWidth = LongDoubleAlign = 64;
@@ -394,6 +396,7 @@ void PPCTargetInfo::addP10SpecificFeatures(
Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
+ Features["prefix-instrs"] = true;
return;
}
@@ -419,6 +422,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("paired-vector-memops", PairedVectorMemops)
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
+ .Case("prefix-instrs", HasPrefixInstrs)
.Case("spe", HasSPE)
.Case("mma", HasMMA)
.Case("rop-protect", HasROPProtect)
@@ -451,6 +455,8 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap
&Features,
Features["power8-vector"] = Features["power9-vector"] = true;
if (Name == "pcrel")
Features["pcrelative-memops"] = true;
+else if (Name == "prefixed")
+ Features["prefix-instrs"] = true;
else
Features[Name] = true;
} else {
@@ -471,6 +477,8 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap
&Features,
Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
+else if (Name == "prefixed")
+ Features["prefix-instrs"] = false;
else
Features[Name] = false;
}
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 3feee82d6ccd0..554f2174fee00 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -73,6 +73,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool PairedVectorMemops = false;
bool HasP10Vector = false;
bool HasPCRelativeMemops = false;
+ bool HasPrefixInstrs = false;
protected:
std::string ABI;
diff --git a/clang/test/Driver/ppc-prefixed.cpp
b/clang/test/Driver/ppc-prefixed.cpp
new file mode 100644
index 0..3d6a13f83d0b2
--- /dev/null
+++ b/clang/test/Driver/ppc-prefixed.cpp
@@ -0,0 +1,12 @@
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mprefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-PREFIXED %s
+// RUN: %clang -target powerpc64-unknown-linux-gnu %s -### -mcpu=pwr10
-mno-prefixed -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOPREFIXED %s
+// CHECK-NOPREFIXED: "-target-feature" "-prefixed"
+// CHECK-PREFIXED: "-target-feature" "+prefixed"
+
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -emit-llvm -S
%s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mprefixed
-emit-llvm -S %s -o - | grep "attributes.*+prefix-instrs"
+// RUN: %clang -target powerpc64-unknown-linux-gnu -mcpu=pwr10 -mno-prefixed
-emit-llvm -S %s -o - | grep "attributes.*\-prefix-instrs"
+
+int main(int argc, char *argv[]) {
+ return 0;
+}
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[clang] 8b3d944 - [PowerPC] Disable vector types when not supported by subtarget features
Author: Lei Huang
Date: 2021-10-04T14:16:47-05:00
New Revision: 8b3d944a97cc944a24ed1296c801da5654896092
URL:
https://github.com/llvm/llvm-project/commit/8b3d944a97cc944a24ed1296c801da5654896092
DIFF:
https://github.com/llvm/llvm-project/commit/8b3d944a97cc944a24ed1296c801da5654896092.diff
LOG: [PowerPC] Disable vector types when not supported by subtarget features
Update clang to treat vector unsigned long long and friends as invalid
for AltiVec without VSX.
Reported in: https://bugs.llvm.org/show_bug.cgi?id=47782
Reviewed By: nemanjai, amyk
Differential Revision: https://reviews.llvm.org/D109178
Added:
clang/test/CodeGen/builtins-ppc-int128.c
Modified:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Headers/altivec.h
clang/lib/Sema/DeclSpec.cpp
clang/test/CodeGen/builtins-ppc-vsx.c
clang/test/Parser/altivec-bool-128.c
clang/test/Parser/altivec.c
clang/test/Parser/cxx-altivec-bool-128.cpp
clang/test/Parser/cxx-altivec.cpp
clang/test/Sema/altivec-generic-overload.c
clang/test/Sema/builtins-ppc.c
Removed:
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index c71a00b184328..96cb4a0fcb96f 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -268,10 +268,12 @@ def err_invalid_vector_double_decl_spec : Error <
def err_invalid_vector_bool_int128_decl_spec : Error <
"use of '__int128' with '__vector bool' requires VSX support enabled (on "
"POWER10 or later)">;
+def err_invalid_vector_int128_decl_spec : Error<
+ "use of '__int128' with '__vector' requires extended Altivec support"
+ " (available on POWER8 or later)">;
def err_invalid_vector_long_long_decl_spec : Error <
- "use of 'long long' with '__vector bool' requires VSX support (available on "
- "POWER7 or later) or extended Altivec support (available on POWER8 or later)
"
- "to be enabled">;
+ "use of 'long long' with '__vector' requires VSX support (available on "
+ "POWER7 or later) to be enabled">;
def err_invalid_vector_long_double_decl_spec : Error<
"cannot use 'long double' with '__vector'">;
def warn_vector_long_decl_spec_combination : Warning<
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 5da4fbf72ce97..4e229a4bf510c 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -8842,7 +8842,7 @@ static __inline__ vector long long __ATTRS_o_ai
vec_sl(vector long long __a, vector unsigned long long __b) {
return (vector long long)vec_sl((vector unsigned long long)__a, __b);
}
-#else
+#elif defined(__VSX__)
static __inline__ vector unsigned char __ATTRS_o_ai
vec_vspltb(vector unsigned char __a, unsigned char __b);
static __inline__ vector unsigned long long __ATTRS_o_ai
@@ -,7 +,7 @@ static __inline__ vector long long __ATTRS_o_ai
vec_sl(vector long long __a, vector unsigned long long __b) {
return (vector long long)vec_sl((vector unsigned long long)__a, __b);
}
-#endif
+#endif /* __VSX__ */
/* vec_vslb */
@@ -10353,7 +10353,7 @@ static __inline__ vector long long __ATTRS_o_ai
vec_sr(vector long long __a, vector unsigned long long __b) {
return (vector long long)vec_sr((vector unsigned long long)__a, __b);
}
-#else
+#elif defined(__VSX__)
static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sr(vector unsigned long long __a, vector unsigned long long __b) {
__b %= (vector unsigned long long)(sizeof(unsigned long long) *
__CHAR_BIT__);
@@ -10397,7 +10397,7 @@ static __inline__ vector long long __ATTRS_o_ai
vec_sr(vector long long __a, vector unsigned long long __b) {
return (vector long long)vec_sr((vector unsigned long long)__a, __b);
}
-#endif
+#endif /* __VSX__ */
/* vec_vsrb */
@@ -10483,7 +10483,7 @@ static __inline__ vector unsigned long long __ATTRS_o_ai
vec_sra(vector unsigned long long __a, vector unsigned long long __b) {
return (vector unsigned long long)((vector signed long long)__a >> __b);
}
-#else
+#elif defined(__VSX__)
static __inline__ vector signed long long __ATTRS_o_ai
vec_sra(vector signed long long __a, vector unsigned long long __b) {
__b %= (vector unsigned long long)(sizeof(unsigned long long) *
__CHAR_BIT__);
@@ -10495,7 +10495,7 @@ vec_sra(vector unsigned long long __a, vector unsigned
long long __b) {
__b %= (vector unsigned long long)(sizeof(unsigned long long) *
__CHAR_BIT__);
return (vector unsigned long long)((vector signed long long)__a >> __b);
}
-#endif
+#endif /* __VSX__ */
/* vec_vsrab */
@@ -17227,6 +17227,7 @@ provided.
#define vec_ncipher_be __builtin_altivec_crypto_vncipher
#define vec_ncipherlast_be __builtin_altivec_crypto_vncipherlast
+#ifdef __VSX__
static __inline__ vector unsigned long long __attribute__((__always_inline__))
__builtin_crypto_vsbox(vector unsigned lon
[clang] b259740 - [PowerPC][NFC] Clean up builtin sema checks
Author: Lei Huang
Date: 2021-06-22T16:06:28-05:00
New Revision: b259740801d3515810ecc15bf0c24b0d476a1608
URL:
https://github.com/llvm/llvm-project/commit/b259740801d3515810ecc15bf0c24b0d476a1608
DIFF:
https://github.com/llvm/llvm-project/commit/b259740801d3515810ecc15bf0c24b0d476a1608.diff
LOG: [PowerPC][NFC] Clean up builtin sema checks
Cleanup sema checking for 64bit builtins or builtins that require
specific feature support.
Reviewed By: NeHuang
Differential Revision: https://reviews.llvm.org/D104664
Added:
Modified:
clang/lib/Sema/SemaChecking.cpp
Removed:
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 32b7861f7f003..3b95a1344075a 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3255,34 +3255,33 @@ static QualType DecodePPCMMATypeFromStr(ASTContext
&Context, const char *&Str,
}
}
+static bool isPPC_64Builtin(unsigned BuiltinID) {
+ // These builtins only work on PPC 64bit targets.
+ switch (BuiltinID) {
+ case PPC::BI__builtin_divde:
+ case PPC::BI__builtin_divdeu:
+ case PPC::BI__builtin_bpermd:
+return true;
+ }
+ return false;
+}
+
+static bool SemaFeatureCheck(Sema &S, CallExpr *TheCall,
+ StringRef FeatureToCheck, unsigned DiagID) {
+ if (!S.Context.getTargetInfo().hasFeature(FeatureToCheck))
+return S.Diag(TheCall->getBeginLoc(), DiagID) << TheCall->getSourceRange();
+ return false;
+}
+
bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned
BuiltinID,
CallExpr *TheCall) {
unsigned i = 0, l = 0, u = 0;
- bool Is64BitBltin = BuiltinID == PPC::BI__builtin_divde ||
- BuiltinID == PPC::BI__builtin_divdeu ||
- BuiltinID == PPC::BI__builtin_bpermd;
bool IsTarget64Bit = TI.getTypeWidth(TI.getIntPtrType()) == 64;
- bool IsBltinExtDiv = BuiltinID == PPC::BI__builtin_divwe ||
- BuiltinID == PPC::BI__builtin_divweu ||
- BuiltinID == PPC::BI__builtin_divde ||
- BuiltinID == PPC::BI__builtin_divdeu;
- if (Is64BitBltin && !IsTarget64Bit)
+ if (isPPC_64Builtin(BuiltinID) && !IsTarget64Bit)
return Diag(TheCall->getBeginLoc(), diag::err_64_bit_builtin_32_bit_tgt)
<< TheCall->getSourceRange();
- if ((IsBltinExtDiv && !TI.hasFeature("extdiv")) ||
- (BuiltinID == PPC::BI__builtin_bpermd && !TI.hasFeature("bpermd")))
-return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
- << TheCall->getSourceRange();
-
- auto SemaVSXCheck = [&](CallExpr *TheCall) -> bool {
-if (!TI.hasFeature("vsx"))
- return Diag(TheCall->getBeginLoc(), diag::err_ppc_builtin_only_on_pwr7)
- << TheCall->getSourceRange();
-return false;
- };
-
switch (BuiltinID) {
default: return false;
case PPC::BI__builtin_altivec_crypto_vshasigmaw:
@@ -3308,11 +3307,22 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
case PPC::BI__builtin_vsx_xxpermdi:
case PPC::BI__builtin_vsx_xxsldwi:
return SemaBuiltinVSX(TheCall);
+ case PPC::BI__builtin_divwe:
+ case PPC::BI__builtin_divweu:
+ case PPC::BI__builtin_divde:
+ case PPC::BI__builtin_divdeu:
+return SemaFeatureCheck(*this, TheCall, "extdiv",
+diag::err_ppc_builtin_only_on_pwr7);
+ case PPC::BI__builtin_bpermd:
+return SemaFeatureCheck(*this, TheCall, "bpermd",
+diag::err_ppc_builtin_only_on_pwr7);
case PPC::BI__builtin_unpack_vector_int128:
-return SemaVSXCheck(TheCall) ||
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7) ||
SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
case PPC::BI__builtin_pack_vector_int128:
-return SemaVSXCheck(TheCall);
+return SemaFeatureCheck(*this, TheCall, "vsx",
+diag::err_ppc_builtin_only_on_pwr7);
case PPC::BI__builtin_altivec_vgnb:
return SemaBuiltinConstantArgRange(TheCall, 1, 2, 7);
case PPC::BI__builtin_altivec_vec_replace_elt:
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[clang] 8930af4 - [PowerPC] Implement XL compatibility builtin __addex
Author: Lei Huang
Date: 2021-08-12T16:38:21-05:00
New Revision: 8930af45c35b5224d3b90c8408957f6b7bfa1be0
URL:
https://github.com/llvm/llvm-project/commit/8930af45c35b5224d3b90c8408957f6b7bfa1be0
DIFF:
https://github.com/llvm/llvm-project/commit/8930af45c35b5224d3b90c8408957f6b7bfa1be0.diff
LOG: [PowerPC] Implement XL compatibility builtin __addex
Add builtin and intrinsic for `__addex`.
This patch is part of a series of patches to provide builtins for
compatibility with the XL compiler.
Reviewed By: stefanp, nemanjai, NeHuang
Differential Revision: https://reviews.llvm.org/D107002
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-warning.c
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-error.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/P9InstrResources.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr9-64bit.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index dfe97af300f41..7a1795d9e550d 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -144,6 +144,7 @@ BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
+BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index bf857f58951b3..73217b418e81f 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -9733,6 +9733,9 @@ def err_argument_invalid_range : Error<
def warn_argument_invalid_range : Warning<
"argument value %0 is outside the valid range [%1, %2]">, DefaultError,
InGroup>;
+def warn_argument_undefined_behaviour : Warning<
+ "argument value %0 will result in undefined behaviour">,
+ InGroup>;
def err_argument_not_multiple : Error<
"argument should be a multiple of %0">;
def err_argument_not_power_of_2 : Error<
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 839fb93ff3d0c..c15d2df33f9f7 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -236,6 +236,7 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+ Builder.defineMacro("__addex", "__builtin_ppc_addex");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index d3736311d5662..e5008330a4150 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3294,6 +3294,7 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_ppc_store8r:
case PPC::BI__builtin_ppc_insert_exp:
case PPC::BI__builtin_ppc_extract_sig:
+ case PPC::BI__builtin_ppc_addex:
return true;
}
return false;
@@ -3435,6 +3436,19 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
&TI, unsigned BuiltinID,
case PPC::BI__builtin_ppc_insert_exp:
return SemaFeatureCheck(*this, TheCall, "power9-vector",
diag::err_ppc_builtin_only_on_arch, "9");
+ case PPC::BI__builtin_ppc_addex: {
+if (SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+ diag::err_ppc_builtin_only_on_arch, "9") ||
+SemaBuiltinConstantArgRange(TheCall, 2, 0, 3))
+ return true;
+// Output warning for reserved values 1 to 3.
+int ArgValue =
+TheCall->getArg(2)->getIntegerConstantExpr(Context)->getSExtValue();
+if (ArgValue != 0)
+ Diag(TheCall->getBeginLoc(), diag::warn_argument_undefined_behaviour)
+ << ArgValue;
+return false;
+ }
case PPC::BI__builtin_ppc_mtfsb0:
case PPC::BI__builtin_ppc_mtfsb1:
return SemaBuiltinConstantArgRange(TheCall, 0, 0, 31);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
index 741e87194a7d4..50d5aefdd2941 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-pwr9-64bit.c
@@ -80,3 +80,19 @@ double insert_exp (double d, unsigned long long ull) {
// CHECK-NONPWR9-ERR: error: this builtin is only valid on POWER9 or later
CPUs
return __ins
[clang] 7d8ae9f - [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c
Author: Lei Huang
Date: 2022-08-16T13:56:33-05:00
New Revision: 7d8ae9f755d7ae65ab116220d6d42108ee10f815
URL:
https://github.com/llvm/llvm-project/commit/7d8ae9f755d7ae65ab116220d6d42108ee10f815
DIFF:
https://github.com/llvm/llvm-project/commit/7d8ae9f755d7ae65ab116220d6d42108ee10f815.diff
LOG: [NFC][PowerPC] Add missing NOCOMPAT checks for builtins-ppc-xlcompat.c
Followup patch to address request from https://reviews.llvm.org/D124093
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D131622
Added:
Modified:
clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
Removed:
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
index 1344f551ba9ff..a86d9547558e3 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@ vector unsigned int res_vui;
void test() {
// CHECK-LABEL: @test(
// CHECK-NEXT: entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT: entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT:[[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x
i64> [[TMP0]])
// CHECK-NEXT:fmul <4 x float> [[TMP1]],
+// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]],
res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT:[[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x
i64> [[TMP2]])
// CHECK-NEXT:fmul <4 x float> [[TMP3]],
+// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]],
res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP4]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]],
res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT:fmul <2 x double> [[TMP8]],
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]],
res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm()
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[clang] dba2ff5 - fix x86 sanitizer failure due to use of or
Author: Lei Huang Date: 2022-06-16T17:20:31-05:00 New Revision: dba2ff500d5b29f2d18b93aed5caa5b4ef7c94dd URL: https://github.com/llvm/llvm-project/commit/dba2ff500d5b29f2d18b93aed5caa5b4ef7c94dd DIFF: https://github.com/llvm/llvm-project/commit/dba2ff500d5b29f2d18b93aed5caa5b4ef7c94dd.diff LOG: fix x86 sanitizer failure due to use of or Added: Modified: clang/lib/CodeGen/CGBuiltin.cpp Removed: diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 662a6637bd4a..ce4ecc5c3284 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -15613,7 +15613,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, RangeErrMsg += llvm::to_string(ValidMaxValue) + "]"; // Issue error if third argument is not within the valid range. -if (ConstArg < 0 or ConstArg > ValidMaxValue) +if (ConstArg < 0 || ConstArg > ValidMaxValue) CGM.Error(E->getExprLoc(), RangeErrMsg); // Input to vec_replace_elt is an element index, convert to byte index. ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] febe4f6 - [PowerPC][NFC] Undefine __XL_COMPAT_ALTIVEC__ in builtin lit test
Author: Lei Huang
Date: 2022-06-16T20:16:52-05:00
New Revision: febe4f650b8754188c8cde01701bc16bd4a7a696
URL:
https://github.com/llvm/llvm-project/commit/febe4f650b8754188c8cde01701bc16bd4a7a696
DIFF:
https://github.com/llvm/llvm-project/commit/febe4f650b8754188c8cde01701bc16bd4a7a696.diff
LOG: [PowerPC][NFC] Undefine __XL_COMPAT_ALTIVEC__ in builtin lit test
Add defines and undefines of the __XL_COMPAT_ALTIVEC__ to ensure
consistent results regardless of the default for this macro.
Added:
Modified:
clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
Removed:
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
index c8f32aa0ec261..780131c8a82c7 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-vsx.c
@@ -1,6 +1,10 @@
// REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers
-target-feature +altivec -target-feature +vsx -triple powerpc64-unknown-unknown
-emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers
-target-feature +altivec -target-feature +vsx -triple
powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s
-check-prefix=CHECK-LE
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers
-target-feature \
+// RUN: +altivec -target-feature +vsx -triple powerpc64-unknown-unknown
-emit-llvm \
+// RUN: -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s
+// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers
-target-feature \
+// RUN: +altivec -target-feature +vsx -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm -U__XL_COMPAT_ALTIVEC__ %s -o - | FileCheck %s
-check-prefix=CHECK-LE
#include
vector bool char vbc = { 0, 1, 0, 1, 0, 1, 0, 1,
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[clang] 711a71d - PowerPC] Emit warning for incompatible vector types that are currently diagnosed with -fno-lax-vector-conversions
Author: Maryam Moghadas
Date: 2022-06-16T20:28:34-05:00
New Revision: 711a71d1ab1056b9ae1364eeec5eff2443629bf7
URL:
https://github.com/llvm/llvm-project/commit/711a71d1ab1056b9ae1364eeec5eff2443629bf7
DIFF:
https://github.com/llvm/llvm-project/commit/711a71d1ab1056b9ae1364eeec5eff2443629bf7.diff
LOG: PowerPC] Emit warning for incompatible vector types that are currently
diagnosed with -fno-lax-vector-conversions
This patch is the last prerequisite to switch the default behaviour to
-fno-lax-vector-conversions in the future.
The first path ;D124093; fixed the altivec implicit castings.
Reviewed By: amyk
Differential Revision: https://reviews.llvm.org/D126540
Added:
Modified:
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Sema/Sema.h
clang/lib/Sema/SemaExpr.cpp
clang/lib/Sema/SemaOverload.cpp
clang/test/Parser/cxx-altivec.cpp
Removed:
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index f2190613d740e..3f7b36375eb0a 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -7589,6 +7589,12 @@ def warn_deprecated_altivec_src_compat : Warning<
"'-altivec-compat=xl' option">,
InGroup>;
+def warn_deprecated_lax_vec_conv_all : Warning<
+ "Implicit conversion between vector types ('%0' and '%1') is deprecated. "
+ "In the future, the behavior implied by '-fno-lax-vector-conversions' "
+ "will be the default.">,
+ InGroup>;
+
def err_catch_incomplete_ptr : Error<
"cannot catch pointer to incomplete type %0">;
def err_catch_incomplete_ref : Error<
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 7314a60d3a44f..8d9af0ff12c85 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -12136,6 +12136,8 @@ class Sema final {
bool areVectorTypesSameSize(QualType srcType, QualType destType);
bool areLaxCompatibleVectorTypes(QualType srcType, QualType destType);
bool isLaxVectorConversion(QualType srcType, QualType destType);
+ bool areSameVectorElemTypes(QualType srcType, QualType destType);
+ bool anyAltivecTypes(QualType srcType, QualType destType);
/// type checking declaration initializers (C99 6.7.8)
bool CheckForConstantInitializer(Expr *e, QualType t);
diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp
index 6edf5b355d029..68634c5495cb9 100644
--- a/clang/lib/Sema/SemaExpr.cpp
+++ b/clang/lib/Sema/SemaExpr.cpp
@@ -7733,6 +7733,36 @@ bool Sema::areVectorTypesSameSize(QualType SrcTy,
QualType DestTy) {
return (SrcLen * SrcEltSize == DestLen * DestEltSize);
}
+// This returns true if at least one of the types is an altivec vector.
+bool Sema::anyAltivecTypes(QualType SrcTy, QualType DestTy) {
+ assert((DestTy->isVectorType() || SrcTy->isVectorType()) &&
+ "expected at least one type to be a vector here");
+
+ bool IsSrcTyAltivec =
+ SrcTy->isVectorType() && (SrcTy->castAs()->getVectorKind() ==
+VectorType::AltiVecVector);
+ bool IsDestTyAltivec = DestTy->isVectorType() &&
+ (DestTy->castAs()->getVectorKind() ==
+ VectorType::AltiVecVector);
+
+ return (IsSrcTyAltivec || IsDestTyAltivec);
+}
+
+// This returns true if both vectors have the same element type.
+bool Sema::areSameVectorElemTypes(QualType SrcTy, QualType DestTy) {
+ assert((DestTy->isVectorType() || SrcTy->isVectorType()) &&
+ "expected at least one type to be a vector here");
+
+ uint64_t SrcLen, DestLen;
+ QualType SrcEltTy, DestEltTy;
+ if (!breakDownVectorType(SrcTy, SrcLen, SrcEltTy))
+return false;
+ if (!breakDownVectorType(DestTy, DestLen, DestEltTy))
+return false;
+
+ return (SrcEltTy == DestEltTy);
+}
+
/// Are the two types lax-compatible vector types? That is, given
/// that one of them is a vector, do they have equal storage sizes,
/// where the storage size is the number of elements times the element
@@ -9552,6 +9582,13 @@ Sema::CheckAssignmentConstraints(QualType LHSType,
ExprResult &RHS,
// vectors, the total size only needs to be the same. This is a bitcast;
// no bits are changed but the result type is
diff erent.
if (isLaxVectorConversion(RHSType, LHSType)) {
+// The default for lax vector conversions with Altivec vectors will
+// change, so if we are converting between vector types where
+// at least one is an Altivec vector, emit a warning.
+if (anyAltivecTypes(RHSType, LHSType) &&
+!areSameVectorElemTypes(RHSType, LHSType))
+ Diag(RHS.get()->getExprLoc(), diag::warn_deprecated_lax_vec_conv_all)
+ << RHSType << LHSType;
Kind = CK_BitCast;
return IncompatibleVectors;
}
@@ -9565,6 +9602,9 @@ Sema::Che
[clang-tools-extra] e6f18b7 - [clangd] Remove extra dependancies for clangd
Author: Ahsan Saghir Date: 2023-08-11T08:57:12-05:00 New Revision: e6f18b75d7ffeb6d5a5cb740a61f38f8f122fee1 URL: https://github.com/llvm/llvm-project/commit/e6f18b75d7ffeb6d5a5cb740a61f38f8f122fee1 DIFF: https://github.com/llvm/llvm-project/commit/e6f18b75d7ffeb6d5a5cb740a61f38f8f122fee1.diff LOG: [clangd] Remove extra dependancies for clangd This patch removes dependancies for clangd that were duplicated in 915659bfa1e9fe2e2c748ac84d33881e248f9ad5. The original patch was added to fix build failure with BUILD_SHARED_LIBS=ON. Reviewed By: sammccall Differential Revision: https://reviews.llvm.org/D155540 Added: Modified: clang-tools-extra/clangd/tool/CMakeLists.txt Removed: diff --git a/clang-tools-extra/clangd/tool/CMakeLists.txt b/clang-tools-extra/clangd/tool/CMakeLists.txt index 5c3b566c97364c..6c21175d7687c3 100644 --- a/clang-tools-extra/clangd/tool/CMakeLists.txt +++ b/clang-tools-extra/clangd/tool/CMakeLists.txt @@ -26,11 +26,7 @@ clang_target_link_libraries(clangdMain clangBasic clangFormat clangFrontend - clangLex - clangSema clangTooling - clangToolingCore - clangToolingRefactoring clangToolingSyntax ) @@ -48,11 +44,8 @@ clang_target_link_libraries(clangd PRIVATE clangAST clangBasic - clangFormat - clangFrontend clangLex clangSema - clangTooling clangToolingCore clangToolingRefactoring clangToolingSyntax ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error< def err_builtin_target_unsupported : Error< "builtin is not supported on this target">; +def err_builtin_aix_os_unsupported : Error< + "this builtin is available only on AIX 7.2 and later operating systems">; lei137 wrote: but line 10349 starts with "builtin is ..." better to be consistent no? https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() for aix (PR #80069)
https://github.com/lei137 deleted https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] support builtin_cpu_is() (PR #80069)
https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
@@ -126,4 +126,59 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header
+// file: .
+#ifndef AIX_POWERPC_USE_SYS_CONF
+ #define AIX_POWERPC_USE_SYS_CONF
+ #define AIX_SYSCON_IMPL_IDX 1
+ #define AIX_PPC7_VALUE 0x8000
+ #define AIX_PPC8_VALUE 0x0001
+ #define AIX_PPC9_VALUE 0x0002
+ #define AIX_PPC10_VALUE 0x0004
+
+ #define AIX_BUILTIN_PPC_TRUE 1
lei137 wrote:
```suggestion
// Supported SUPPORT_METHOD values.
#define AIX_BUILTIN_PPC_TRUE 1
```
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
@@ -126,4 +126,59 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header
+// file: .
+#ifndef AIX_POWERPC_USE_SYS_CONF
+ #define AIX_POWERPC_USE_SYS_CONF
+ #define AIX_SYSCON_IMPL_IDX 1
+ #define AIX_PPC7_VALUE 0x8000
+ #define AIX_PPC8_VALUE 0x0001
+ #define AIX_PPC9_VALUE 0x0002
+ #define AIX_PPC10_VALUE 0x0004
+
+ #define AIX_BUILTIN_PPC_TRUE 1
+ #define AIX_BUILTIN_PPC_FALSE 0
+ #define USE_SYS_CONF 2
+
+ #define COMP_EQ 0
lei137 wrote:
```suggestion
// Supported COMPARE_OP values.
#define COMP_EQ 0
```
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
https://github.com/lei137 approved this pull request. https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
https://github.com/lei137 approved this pull request. https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
https://github.com/lei137 dismissed https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX 1
+#define AIX_PPC7_VALUE 0x8000
+#define AIX_PPC8_VALUE 0x0001
+#define AIX_PPC9_VALUE 0x0002
+#define AIX_PPC10_VALUE 0x0004
+
+#define AIX_BUILTIN_PPC_TRUE 1
+#define AIX_BUILTIN_PPC_FALSE 0
+#define COMP_OP 2
+
+#define OP_EQ 0
+
+#endif
+
+//The value of SUPPORT is COMP_OP, it means the feature depend on the
V(INDEX)&MASK OP VALUE
+//If the value of MASK is zero, it means we do not need to do mask, just check
V(INDEX) OP VALUE.
+
lei137 wrote:
agreed
https://github.com/llvm/llvm-project/pull/80069
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[clang] [llvm] [AIX] Lower intrinsic __builtin_cpu_is into AIX platform-specific code. (PR #80069)
https://github.com/lei137 approved this pull request. LGTM Please address remaining nits before commit. https://github.com/llvm/llvm-project/pull/80069 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix codegen for transparent_union function params (PR #104816)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/104816
>From 5ceb717b6f9ce11a12fde4aa9aaa89b4e017ef70 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:24:31 -0400
Subject: [PATCH 1/2] Fix codegen for transparent_union function params
Update codegen for func param with transparent_union attr to be that of
the first union member.
This closes #76773.
---
clang/test/CodeGen/transparent-union-type.c | 81 +
1 file changed, 81 insertions(+)
create mode 100644 clang/test/CodeGen/transparent-union-type.c
diff --git a/clang/test/CodeGen/transparent-union-type.c
b/clang/test/CodeGen/transparent-union-type.c
new file mode 100644
index 00..9972dd2131d1b5
--- /dev/null
+++ b/clang/test/CodeGen/transparent-union-type.c
@@ -0,0 +1,81 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc64-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple powerpc64-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple riscv64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple riscv32-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple i386-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple x86_64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple armv7-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple arm64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple aarch64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+
+typedef union tu_c {
+ signed char a;
+ signed char b;
+} tu_c_t __attribute__((transparent_union));
+
+typedef union tu_s {
+ short a;
+} tu_s_t __attribute__((transparent_union));
+
+typedef union tu_us {
+ unsigned short a;
+} tu_us_t __attribute__((transparent_union));
+
+typedef union tu_l {
+ long a;
+} tu_l_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest0(
+// CHECK-SAME: i8 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest0(tu_c_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest1(
+// CHECK-SAME: i16 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest1(tu_s_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest2(
+// CHECK-SAME: i16 noundef zeroext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest2(tu_us_t uc) { }
+
+// CHECK-64-LABEL: define{{.*}} void @ftest3(
+// CHECK-64-SAME: i64 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-64-NEXT: [[ENTRY:.*:]]
+// CHECK-64-NEXT:ret void
+//
+// CHECK-32-LABEL: define{{.*}} void @ftest3(
+// CHECK-32-SAME: i32 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-32-NEXT: [[ENTRY:.*:]]
+// CHECK-32-NEXT:ret void
+void ftest3(tu_l_t uc) { }
+
+typedef union etest {
+ enum flag {red, yellow, blue} fl;
+ enum weekend {sun, sat} b;
+} etest_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest4(
+// CHECK-SAME: i8 noundef zeroext [[A_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest4(etest_t a) {}
>From bc296d99eaee946d2521f81573fe0ff8b5eca228 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:27:42 -0400
Subject: [PATCH 2/2] update codegen
---
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/lib/CodeGen/Targets/ARM.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 12 ++--
clang/lib/CodeGen/Targets/X86.cpp | 6 +-
.../test/CodeGen/PowerPC/transparent_union.c | 67 ---
5 files changed, 13 insertions(+), 79 deletions(-)
delete mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
diff --git a/
[clang] Fix codegen for transparent_union function params (PR #104816)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/104816
>From 5ceb717b6f9ce11a12fde4aa9aaa89b4e017ef70 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:24:31 -0400
Subject: [PATCH 1/3] Fix codegen for transparent_union function params
Update codegen for func param with transparent_union attr to be that of
the first union member.
This closes #76773.
---
clang/test/CodeGen/transparent-union-type.c | 81 +
1 file changed, 81 insertions(+)
create mode 100644 clang/test/CodeGen/transparent-union-type.c
diff --git a/clang/test/CodeGen/transparent-union-type.c
b/clang/test/CodeGen/transparent-union-type.c
new file mode 100644
index 00..9972dd2131d1b5
--- /dev/null
+++ b/clang/test/CodeGen/transparent-union-type.c
@@ -0,0 +1,81 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc64-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple powerpc64-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple riscv64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple riscv32-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple i386-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple x86_64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple armv7-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple arm64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple aarch64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+
+typedef union tu_c {
+ signed char a;
+ signed char b;
+} tu_c_t __attribute__((transparent_union));
+
+typedef union tu_s {
+ short a;
+} tu_s_t __attribute__((transparent_union));
+
+typedef union tu_us {
+ unsigned short a;
+} tu_us_t __attribute__((transparent_union));
+
+typedef union tu_l {
+ long a;
+} tu_l_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest0(
+// CHECK-SAME: i8 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest0(tu_c_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest1(
+// CHECK-SAME: i16 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest1(tu_s_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest2(
+// CHECK-SAME: i16 noundef zeroext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest2(tu_us_t uc) { }
+
+// CHECK-64-LABEL: define{{.*}} void @ftest3(
+// CHECK-64-SAME: i64 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-64-NEXT: [[ENTRY:.*:]]
+// CHECK-64-NEXT:ret void
+//
+// CHECK-32-LABEL: define{{.*}} void @ftest3(
+// CHECK-32-SAME: i32 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-32-NEXT: [[ENTRY:.*:]]
+// CHECK-32-NEXT:ret void
+void ftest3(tu_l_t uc) { }
+
+typedef union etest {
+ enum flag {red, yellow, blue} fl;
+ enum weekend {sun, sat} b;
+} etest_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest4(
+// CHECK-SAME: i8 noundef zeroext [[A_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest4(etest_t a) {}
>From bc296d99eaee946d2521f81573fe0ff8b5eca228 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:27:42 -0400
Subject: [PATCH 2/3] update codegen
---
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/lib/CodeGen/Targets/ARM.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 12 ++--
clang/lib/CodeGen/Targets/X86.cpp | 6 +-
.../test/CodeGen/PowerPC/transparent_union.c | 67 ---
5 files changed, 13 insertions(+), 79 deletions(-)
delete mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
diff --git a/
[clang] Fix codegen for transparent_union function params (PR #104816)
lei137 wrote: > s-barannikov done. https://github.com/llvm/llvm-project/pull/104816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix codegen for transparent_union function params (PR #104816)
lei137 wrote: > May it make sense to add tests with the argument passed in memory / by > reference? @s-barannikov Done. https://github.com/llvm/llvm-project/pull/104816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix codegen for transparent_union function params (PR #104816)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/104816
>From ea3a071a2255fa103f5097272b2fa896a3d4b979 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:24:31 -0400
Subject: [PATCH 1/3] Fix codegen for transparent_union function params
Update codegen for func param with transparent_union attr to be that of
the first union member.
This closes #76773.
---
clang/test/CodeGen/transparent-union-type.c | 81 +
1 file changed, 81 insertions(+)
create mode 100644 clang/test/CodeGen/transparent-union-type.c
diff --git a/clang/test/CodeGen/transparent-union-type.c
b/clang/test/CodeGen/transparent-union-type.c
new file mode 100644
index 00..9972dd2131d1b5
--- /dev/null
+++ b/clang/test/CodeGen/transparent-union-type.c
@@ -0,0 +1,81 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc64-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple powerpc64-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple riscv64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple riscv32-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple i386-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple x86_64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple armv7-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple arm64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple aarch64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+
+typedef union tu_c {
+ signed char a;
+ signed char b;
+} tu_c_t __attribute__((transparent_union));
+
+typedef union tu_s {
+ short a;
+} tu_s_t __attribute__((transparent_union));
+
+typedef union tu_us {
+ unsigned short a;
+} tu_us_t __attribute__((transparent_union));
+
+typedef union tu_l {
+ long a;
+} tu_l_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest0(
+// CHECK-SAME: i8 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest0(tu_c_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest1(
+// CHECK-SAME: i16 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest1(tu_s_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest2(
+// CHECK-SAME: i16 noundef zeroext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest2(tu_us_t uc) { }
+
+// CHECK-64-LABEL: define{{.*}} void @ftest3(
+// CHECK-64-SAME: i64 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-64-NEXT: [[ENTRY:.*:]]
+// CHECK-64-NEXT:ret void
+//
+// CHECK-32-LABEL: define{{.*}} void @ftest3(
+// CHECK-32-SAME: i32 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-32-NEXT: [[ENTRY:.*:]]
+// CHECK-32-NEXT:ret void
+void ftest3(tu_l_t uc) { }
+
+typedef union etest {
+ enum flag {red, yellow, blue} fl;
+ enum weekend {sun, sat} b;
+} etest_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest4(
+// CHECK-SAME: i8 noundef zeroext [[A_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest4(etest_t a) {}
>From b5511c10638f8ba03818a6e6e017e6e9fd4e9657 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:27:42 -0400
Subject: [PATCH 2/3] update codegen
---
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/lib/CodeGen/Targets/ARM.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 12 ++--
clang/lib/CodeGen/Targets/X86.cpp | 6 +-
.../test/CodeGen/PowerPC/transparent_union.c | 67 ---
5 files changed, 13 insertions(+), 79 deletions(-)
delete mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
diff --git a/
[clang] Fix codegen for transparent_union function params (PR #104816)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/104816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/13] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
lei137 wrote: Seems `CGT.ConvertType(Ty)` does what was needed. I've simplified the patch to use that instead. https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/14] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -141,46 +149,98 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
-
- // Supported COMPARE_OP values.
- #define COMP_EQ 0
-
+ #define SYS_CALL 3
#endif
// The value of SUPPORT_METHOD can be AIX_BUILTIN_PPC_TRUE,
-// AIX_BUILTIN_PPC_FALSE, or USE_SYS_CONF.
-// When the value of SUPPORT_METHOD is USE_SYS_CONF, the return value
-// depends on the result of comparing the data member of
-// _system_configuration specified by INDEX with a certain value.
+// AIX_BUILTIN_PPC_FALSE, USE_SYS_CONF, SYS_CALL.
+// When the value of SUPPORT_METHOD is set to USE_SYS_CONF, the return value
+// depends on comparing VALUE with the specified data member of
+// _system_configuration at INDEX, where the data member is masked by Mask.
+// When the SUPPORT_METHOD value is set to SYS_CALL, the return value depends
+// on comparing a VALUE with the return value of calling `getsystemcfg`
+// with the parameter INDEX, which is then masked by Mask.
+// AIX_BUILTIN_PPC_TRUE and AIX_BUILTIN_PPC_FALSE are for features
+// that are supported or unsupported on all systems respectively.
lei137 wrote:
Maybe this will be more clear:
```suggestion
// The value of SUPPORT_METHOD can be:
//AIX_BUILTIN_PPC_TRUE : feature supported
//AIX_BUILTIN_PPC_FALSE : feature not supported
//USE_SYS_CONF : return value depends on comparing VALUE with the specified
// data member of _system_configuration at INDEX, where the
// data member is masked by Mask.
//SYS_CALL : return value depends on comparing a VALUE with the return value
// of calling `getsystemcfg` with the parameter INDEX, which is
// then masked by Mask.
```
https://github.com/llvm/llvm-project/pull/82809
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[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple powerpc-ibm-aix7.2.0.0 -emit-llvm -o - %s |
FileCheck %s
+
+int main() {
+ int ret = 0;
+ ret += __builtin_cpu_supports("vsx");
+ ret += __builtin_cpu_supports("htm");
+ ret += __builtin_cpu_supports("cellbe");
+ ret += __builtin_cpu_supports("power4");
+ return ret;
lei137 wrote:
would be good to add a call that will directly return true, another call to
syscfg and doc which is which within the src here.
https://github.com/llvm/llvm-project/pull/82809
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[clang] [llvm] Implement a subset of builtin_cpu_supports() features (PR #82809)
https://github.com/lei137 approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/82809 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PPC] Implement BCD assist builtins (PR #101390)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/101390
Implement BCD assist builtins for XL and GCC compatibility.
GCC compat:
```
unsigned int __builtin_cdtbcd (unsigned int);
unsigned int __builtin_cbcdtd (unsigned int);
unsigned int __builtin_addg6s (unsigned int, unsigned int);
```
64BIT XL compat:
```
long long __cdtbcd (long long);
long long __cbcdtd (long long);
long long __addg6s (long long source1, long long source2)
```
>From 6a93c6a2fcfcf8ea49fe59e2e29b6c53a18625a5 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 29 Jul 2024 13:06:51 -0400
Subject: [PATCH 1/5] [PPC] Implement BCD assist builtins
Implement BCD assist builtins for XL and GCC compatibility.
---
clang/include/clang/Basic/BuiltinsPPC.def | 10 ++
clang/lib/Basic/Targets/PPC.cpp | 3 +
.../CodeGen/PowerPC/builtins-bcd-assist.c | 58 +
.../CodeGen/PowerPC/builtins-ppc-bcd-assist.c | 63 ++
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 13 ++
llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 10 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 10 +-
.../CodeGen/PowerPC/builtins-bcd-assist.ll| 111 ++
.../PowerPC/builtins-ppc-bcd-assist.ll| 81 +
9 files changed, 351 insertions(+), 8 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
create mode 100644 clang/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.c
create mode 100644 llvm/test/CodeGen/PowerPC/builtins-bcd-assist.ll
create mode 100644 llvm/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.ll
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 88ae0ce940852..261e91b06b710 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "",
"power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
+// P7 BCD builtins.
+TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions")
+
+// P7 XL Compat BCD builtins.
+TARGET_BUILTIN(__builtin_ppc_cdtbcd, "LLiLLi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_ppc_cbcdtd, "LLiLLi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_ppc_addg6s, "LLiLLiLLi", "", "isa-v206-instructions")
+
// P8 BCD builtins.
TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "",
"isa-v207-instructions")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index d8203f76a5468..b5f9adfdd515b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -105,6 +105,9 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
}
static void defineXLCompatMacros(MacroBuilder &Builder) {
+ Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
+ Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
+ Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
b/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
new file mode 100644
index 0..f346bcf7322c6
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define{{.*}} i64 @cdtbcd_test(i64
+// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32 [[CONV]])
+// CHECK-NEXT:[[CONV1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-NEXT:ret i64 [[CONV1]]
+long long cdtbcd_test(long long ll) {
+return __builtin_cdtbcd (ll);
+}
+
+// CHECK-LABEL: define{{.*}} i32 @cdtbcd_test_ui(i32
+// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32
+// CHECK-NEXT:ret i32 [[TMP0]]
+unsigned int cdtbcd_test_ui(unsigned int ui) {
+return __builtin_cdtbcd (ui);
+}
+
+// CHECK-LABEL: define{{.*}} i64 @cbcdtd_test(i64
+// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.ppc.cbcdtd(i32 [[CONV]])
+// CHECK-NEXT
[clang] [llvm] [PPC] Implement BCD assist builtins (PR #101390)
@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector") TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector") TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector") +// P7 BCD builtins. +TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions") +TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions") +TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions") lei137 wrote: Yes, XL currently have these builtins and `__buitin_ppc_xxx` are implemented to be compat with XL. https://github.com/llvm/llvm-project/pull/101390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/101738
Update codegen for func param with transparent_union attr to be that of the
first union member.
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH] [PowerPC] Fix codegen for transparent_union function params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
ne
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/2] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/3] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/4] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/5] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/6] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 1/7] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGen/
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/10] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGe
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
lei137 wrote:
> Would it do any harm to just unconditionally compute the type and pass it
> into getExtend()?
This seem to cause issues for type `_Bool`, where it changes the function param
from `i1 noundef zeroext %b1` to `i8 noundef zeroext %b1.coerce`.
```
$cat a.c
void fcall(_Bool);
_Bool test_wc_i1(_Bool b1, _Bool b2) {
_Bool o=b1+b2;
fcall(o);
return o;
}
```
IR changes from:
```
target datalayout = "E-m:e-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind
define dso_local zeroext i1 @test_wc_i1(i1 noundef zeroext %b1, i1 noundef
zeroext %b2) local_unnamed_addr #0 {
entry:
%0 = or i1 %b1, %b2
tail call void @fcall(i1 noundef zeroext %0) #3
ret i1 %0
}
declare void @fcall(i1 noundef zeroext) local_unnamed_addr #1
```
to:
```
target datalayout = "E-m:e-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512"
target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind
define dso_local noundef zeroext i1 @test_wc_i1(i8 noundef zeroext %b1.coerce,
i8 noundef zeroext %b2.coerce) local_unnamed_addr #0 {
entry:
%0 = or i8 %b2.coerce, %b1.coerce
%1 = and i8 %0, 1
%tobool = icmp ne i8 %1, 0
tail call void @fcall(i8 noundef zeroext %1) #3
ret i1 %tobool
}
declare void @fcall(i8 noundef zeroext) local_unnamed_addr #1
```
This is probably due to the fact I am getting the coerce type via:
```
llvm::Type *CoerceTy = llvm::IntegerType::get(getVMContext(),
getContext().getTypeSize(Ty));
```
Not sure if there is a more general way to do this?
https://github.com/llvm/llvm-project/pull/101738
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[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
lei137 wrote:
I was thinking it would make the code cleaner if we can do something like this
instead:
```
// For transparent union types, return the type of the first element.
-// Set TU to true if Ty given was a transparent union and to false otherwise.
+// and set CTy the integer type of the first union element. CTy defaults to
nullptr.
-QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty,
+ llvm::Type *CTy) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
- TU = true;
- return UD->field_begin()->getType();
+ QualType UTy = UD->field_begin()->getType();
+ *CTy = llvm::IntegerType::get(getVMContext(),
+getContext().getTypeSize(UTy));
+ return UTy;
}
}
- TU = false;
return Ty;
}
```
Then we can just call `getExtend(Ty, Cty)` by default. But I think I would
need to put this function into `DefaultABIInfo` class to access the
`getVMContext()`? Not sure that's the right thing to do though..
https://github.com/llvm/llvm-project/pull/101738
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[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/11] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac..d73b7e882fe65 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c96..95e48ee49d5a4 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb..d2a3abbe24861 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 0..6c61ce553ba7d
--- /dev/null
+++ b/clang/test/CodeGe
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 converted_to_draft https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PPC] Implement BCD assist builtins (PR #101390)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101390
>From fad942502d77ffe45d23558e9bfa0370b0d06a46 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 29 Jul 2024 13:06:51 -0400
Subject: [PATCH 1/5] [PPC] Implement BCD assist builtins
Implement BCD assist builtins for XL and GCC compatibility.
---
clang/include/clang/Basic/BuiltinsPPC.def | 10 ++
clang/lib/Basic/Targets/PPC.cpp | 3 +
.../CodeGen/PowerPC/builtins-bcd-assist.c | 58 +
.../CodeGen/PowerPC/builtins-ppc-bcd-assist.c | 63 ++
llvm/include/llvm/IR/IntrinsicsPowerPC.td | 13 ++
llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 10 +-
llvm/lib/Target/PowerPC/PPCInstrInfo.td | 10 +-
.../CodeGen/PowerPC/builtins-bcd-assist.ll| 111 ++
.../PowerPC/builtins-ppc-bcd-assist.ll| 81 +
9 files changed, 351 insertions(+), 8 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
create mode 100644 clang/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.c
create mode 100644 llvm/test/CodeGen/PowerPC/builtins-bcd-assist.ll
create mode 100644 llvm/test/CodeGen/PowerPC/builtins-ppc-bcd-assist.ll
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 88ae0ce940852e..261e91b06b7104 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -515,6 +515,16 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "",
"power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector")
TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector")
+// P7 BCD builtins.
+TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_addg6s, "UiUiUi", "", "isa-v206-instructions")
+
+// P7 XL Compat BCD builtins.
+TARGET_BUILTIN(__builtin_ppc_cdtbcd, "LLiLLi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_ppc_cbcdtd, "LLiLLi", "", "isa-v206-instructions")
+TARGET_BUILTIN(__builtin_ppc_addg6s, "LLiLLiLLi", "", "isa-v206-instructions")
+
// P8 BCD builtins.
TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "",
"isa-v207-instructions")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index d8203f76a5468f..b5f9adfdd515b0 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -105,6 +105,9 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
}
static void defineXLCompatMacros(MacroBuilder &Builder) {
+ Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd");
+ Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd");
+ Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s");
Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
Builder.defineMacro("__poppar4", "__builtin_ppc_poppar4");
Builder.defineMacro("__poppar8", "__builtin_ppc_poppar8");
diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
b/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
new file mode 100644
index 00..f346bcf7322c63
--- /dev/null
+++ b/clang/test/CodeGen/PowerPC/builtins-bcd-assist.c
@@ -0,0 +1,58 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 5
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -O2 -target-cpu pwr7 \
+// RUN: -emit-llvm %s -o - | FileCheck %s
+
+// CHECK-LABEL: define{{.*}} i64 @cdtbcd_test(i64
+// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32 [[CONV]])
+// CHECK-NEXT:[[CONV1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-NEXT:ret i64 [[CONV1]]
+long long cdtbcd_test(long long ll) {
+return __builtin_cdtbcd (ll);
+}
+
+// CHECK-LABEL: define{{.*}} i32 @cdtbcd_test_ui(i32
+// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cdtbcd(i32
+// CHECK-NEXT:ret i32 [[TMP0]]
+unsigned int cdtbcd_test_ui(unsigned int ui) {
+return __builtin_cdtbcd (ui);
+}
+
+// CHECK-LABEL: define{{.*}} i64 @cbcdtd_test(i64
+// CHECK: [[CONV:%.*]] = trunc i64 {{.*}} to i32
+// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.ppc.cbcdtd(i32 [[CONV]])
+// CHECK-NEXT:[[CONV1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-NEXT:ret i64 [[CONV1]]
+long long cbcdtd_test(long long ll) {
+return __builtin_cbcdtd (ll);
+}
+
+// CHECK-LABEL: define{{.*}} i32 @cbcdtd_test_ui(i32
+// CHECK: [[TMP0:%.*]] = tail call i32 @llvm.ppc.cbcdtd(i32
+// CHECK-NEXT:ret i32 [[TMP0]]
+unsigned int cbcdtd_test_ui(unsigned int ui) {
+retu
[clang] [llvm] [PPC] Implement BCD assist builtins (PR #101390)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/101390 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 ready_for_review https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/12] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
lei137 wrote: > I'm not an expert here, but I think the change you made makes sense since the > `Ty` is supposed to be the first field. > > Also, might be a dumb question, I saw we have 32-bit Linux run lines, but is > that still worth testing? Thanks for taking a look @amy-kwan. The 32bit linux run line was added in response to review comment from Hubert: https://github.com/llvm/llvm-project/pull/101738#issuecomment-2268003106 https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/15] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
@@ -0,0 +1,123 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux -mcpu=pwr7 \ lei137 wrote: You are right. I verified that this pass even without this update to clang. Will remove this IR test from the PR. https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From f25e4ab65ed16a1e1a3bde91efe24bd0d52e0e74 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/16] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/101738
>From c6a8dee17a0a2eeb3420e04fb445a633dfbee920 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 2 Aug 2024 13:58:37 -0400
Subject: [PATCH 01/16] [PowerPC] Fix codegen for transparent_union function
params
Update codegen for func param with transparent_union attr to be that
of the first union member.
---
clang/lib/CodeGen/ABIInfoImpl.cpp | 7 ++
clang/lib/CodeGen/ABIInfoImpl.h | 4 ++
clang/lib/CodeGen/Targets/PPC.cpp | 26 +--
.../test/CodeGen/PowerPC/transparent_union.c | 54 +++
.../test/CodeGen/PowerPC/transparent_union.ll | 67 +++
5 files changed, 152 insertions(+), 6 deletions(-)
create mode 100644 clang/test/CodeGen/PowerPC/transparent_union.c
create mode 100644 llvm/test/CodeGen/PowerPC/transparent_union.ll
diff --git a/clang/lib/CodeGen/ABIInfoImpl.cpp
b/clang/lib/CodeGen/ABIInfoImpl.cpp
index 35e8f79ba1bac7..d73b7e882fe654 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.cpp
+++ b/clang/lib/CodeGen/ABIInfoImpl.cpp
@@ -143,13 +143,20 @@ bool CodeGen::classifyReturnType(const CGCXXABI &CXXABI,
CGFunctionInfo &FI,
}
QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty) {
+ bool IsTransparentUnion;
+ return useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
+}
+
+QualType CodeGen::useFirstFieldIfTransparentUnion(QualType Ty, bool &TU) {
if (const RecordType *UT = Ty->getAsUnionType()) {
const RecordDecl *UD = UT->getDecl();
if (UD->hasAttr()) {
assert(!UD->field_empty() && "sema created an empty transparent union");
+ TU = true;
return UD->field_begin()->getType();
}
}
+ TU = false;
return Ty;
}
diff --git a/clang/lib/CodeGen/ABIInfoImpl.h b/clang/lib/CodeGen/ABIInfoImpl.h
index 2a3ef6b8a6c961..95e48ee49d5a4e 100644
--- a/clang/lib/CodeGen/ABIInfoImpl.h
+++ b/clang/lib/CodeGen/ABIInfoImpl.h
@@ -65,6 +65,10 @@ CGCXXABI::RecordArgABI getRecordArgABI(QualType T, CGCXXABI
&CXXABI);
bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI,
const ABIInfo &Info);
+// For transparent union types, return the type of the first element.
+// Set reference TU to true if Ty given was a transparent union.
+QualType useFirstFieldIfTransparentUnion(QualType Ty, bool &TU);
+
/// Pass transparent unions as if they were the type of the first element. Sema
/// should ensure that all elements of the union have the same "machine type".
QualType useFirstFieldIfTransparentUnion(QualType Ty);
diff --git a/clang/lib/CodeGen/Targets/PPC.cpp
b/clang/lib/CodeGen/Targets/PPC.cpp
index e4155810963eb8..d2a3abbe248614 100644
--- a/clang/lib/CodeGen/Targets/PPC.cpp
+++ b/clang/lib/CodeGen/Targets/PPC.cpp
@@ -196,7 +196,8 @@ ABIArgInfo AIXABIInfo::classifyReturnType(QualType RetTy)
const {
}
ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -217,8 +218,14 @@ ABIArgInfo AIXABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign*/ TyAlign > CCAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return (ABIArgInfo::getDirect());
}
CharUnits AIXABIInfo::getParamTypeAlignment(QualType Ty) const {
@@ -822,7 +829,8 @@ bool PPC64_SVR4_ABIInfo::isHomogeneousAggregateSmallEnough(
ABIArgInfo
PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty) const {
- Ty = useFirstFieldIfTransparentUnion(Ty);
+ bool IsTransparentUnion;
+ Ty = useFirstFieldIfTransparentUnion(Ty, IsTransparentUnion);
if (Ty->isAnyComplexType())
return ABIArgInfo::getDirect();
@@ -891,8 +899,14 @@ PPC64_SVR4_ABIInfo::classifyArgumentType(QualType Ty)
const {
/*Realign=*/TyAlign > ABIAlign);
}
- return (isPromotableTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
- : ABIArgInfo::getDirect());
+ if (isPromotableTypeForABI(Ty))
+return (IsTransparentUnion ?
+ABIArgInfo::getExtend(Ty,
+llvm::IntegerType::get(getVMContext(),
+ getContext().getTypeSize(Ty)))
+: ABIArgInfo::getExtend(Ty));
+
+ return ABIArgInfo::getDirect();
}
ABIArgInfo
diff --git a/clang/test/CodeGen/PowerPC/transparent_union.c
b/clang/test/CodeGen/PowerPC/transparent_union.c
new file mode 100644
index 00..6c61ce553ba7d7
--- /dev/null
+++ b/clang/tes
[clang] [llvm] [PowerPC] Fix codegen for transparent_union function params (PR #101738)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/101738 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Fix codegen for transparent_union function params (PR #104816)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/104816
Update codegen for func param with transparent_union attr to be that of
the first union member.
This is a followup to #101738 to fix non-ppc codegen and closes #76773.
>From 25f458a6f25ff0fa21d59e30934e314da8abc701 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:24:31 -0400
Subject: [PATCH 1/2] Fix codegen for transparent_union function params
Update codegen for func param with transparent_union attr to be that of
the first union member.
This closes #76773.
---
clang/test/CodeGen/transparent-union-type.c | 81 +
1 file changed, 81 insertions(+)
create mode 100644 clang/test/CodeGen/transparent-union-type.c
diff --git a/clang/test/CodeGen/transparent-union-type.c
b/clang/test/CodeGen/transparent-union-type.c
new file mode 100644
index 00..9972dd2131d1b5
--- /dev/null
+++ b/clang/test/CodeGen/transparent-union-type.c
@@ -0,0 +1,81 @@
+// RUN: %clang_cc1 -triple powerpc64le-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc64-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-linux -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple powerpc64-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple powerpc-aix -O2 -target-cpu pwr7 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple riscv64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple riscv32-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple i386-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple x86_64-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple armv7-linux -O2 -emit-llvm -fshort-enums \
+// RUN: %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-32
+// RUN: %clang_cc1 -triple arm64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+// RUN: %clang_cc1 -triple aarch64 -target-abi darwinpcs -O2 -emit-llvm \
+// RUN: -fshort-enums %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64
+
+typedef union tu_c {
+ signed char a;
+ signed char b;
+} tu_c_t __attribute__((transparent_union));
+
+typedef union tu_s {
+ short a;
+} tu_s_t __attribute__((transparent_union));
+
+typedef union tu_us {
+ unsigned short a;
+} tu_us_t __attribute__((transparent_union));
+
+typedef union tu_l {
+ long a;
+} tu_l_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest0(
+// CHECK-SAME: i8 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest0(tu_c_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest1(
+// CHECK-SAME: i16 noundef signext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest1(tu_s_t uc) { }
+
+// CHECK-LABEL: define{{.*}} void @ftest2(
+// CHECK-SAME: i16 noundef zeroext [[UC_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest2(tu_us_t uc) { }
+
+// CHECK-64-LABEL: define{{.*}} void @ftest3(
+// CHECK-64-SAME: i64 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-64-NEXT: [[ENTRY:.*:]]
+// CHECK-64-NEXT:ret void
+//
+// CHECK-32-LABEL: define{{.*}} void @ftest3(
+// CHECK-32-SAME: i32 [[UC_COERCE:%.*]]) local_unnamed_addr #[[ATTR0]] {
+// CHECK-32-NEXT: [[ENTRY:.*:]]
+// CHECK-32-NEXT:ret void
+void ftest3(tu_l_t uc) { }
+
+typedef union etest {
+ enum flag {red, yellow, blue} fl;
+ enum weekend {sun, sat} b;
+} etest_t __attribute__((transparent_union));
+
+// CHECK-LABEL: define{{.*}} void @ftest4(
+// CHECK-SAME: i8 noundef zeroext [[A_COERCE:%.*]]) local_unnamed_addr
#[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT:ret void
+void ftest4(etest_t a) {}
>From 07207ffe82ba9cb354bd96d1c7637d7b70d827d0 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Mon, 19 Aug 2024 12:27:42 -0400
Subject: [PATCH 2/2] update codegen
---
clang/lib/CodeGen/Targets/AArch64.cpp | 2 +-
clang/lib/CodeGen/Targets/ARM.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 12 ++--
clang/lib/CodeGen/Targets/X86.cpp | 6 +-
.../test/CodeGen/PowerPC/transpare
[clang] Fix codegen for transparent_union function params (PR #104816)
lei137 wrote: > I think the issue could be handled a different (more generic) way, by pulling > `useFirstFieldIfTransparentUnion` to the caller and taking transparent unions > into account when emitting LLVM IR for the formal / actual parameters > somewhere in `CGCall.cpp`, so that ABIInfo implementations don't need to care > about transparent unions at all. I am not familiar with the calling convention and ABI to know if this is how it should be done. It sounds like a reasonable improvement in how we can implement this. However I feel like it is out of scope for what I am trying to do right now. Would this be better as a separate PR to change how this is handled? This PR would fix the current codegen bug that is seen. https://github.com/llvm/llvm-project/pull/104816 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CodeGen] Remove unnecessary ShouldLinkFiles conditional (PR #96951)
lei137 wrote:
I'm getting a build failure with `-Werror` on powerpc from this:
```
~llvm-project/clang/lib/CodeGen/LinkInModulesPass.cpp:24:19: error: field
'ShouldLinkFiles' is uninitialized when used here [-Werror,-Wuninitialized]
407324 | ShouldLinkFiles(ShouldLinkFiles) {}
4074 | ^
```
https://github.com/llvm/llvm-project/pull/96951
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/108584 Checks for clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c seem to have been manually upated to rename temp variables even though it says checks was auto generated. Regenerate via script in prep for changes needed in a followup patch. >From 70077d359e2f98a3c4b24fcf638a51c6a0272473 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 13 Sep 2024 15:00:19 + Subject: [PATCH] [PowerPC][NFC] autogen mma tc checks via llvm/utils/update_cc_test_checks.py Checks for clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c seem to have been manually upated to rename temp variables even though it says checks was auto generated. Regenerate via script in prep for changes needed in a followup patch. --- .../PowerPC/builtins-ppc-pair-mma-types.c | 204 +- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c index a414a2827b2c43..39c040967dc0c3 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c @@ -16,18 +16,18 @@ // CHECK-NEXT:store <16 x i8> [[VC:%.*]], ptr [[VC_ADDR]], align 16 // CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // CHECK-NEXT:store ptr [[TMP0]], ptr [[VQP]], align 8 -// CHECK-NEXT:[[TMP2:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-NEXT:[[TMP3:%.*]] = load <512 x i1>, ptr [[TMP2]], align 64 -// CHECK-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ1]], align 64 -// CHECK-NEXT:[[TMP4:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() -// CHECK-NEXT:store <512 x i1> [[TMP4]], ptr [[VQ2]], align 64 +// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-NEXT:[[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64 +// CHECK-NEXT:store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64 +// CHECK-NEXT:[[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() +// CHECK-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64 +// CHECK-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-NEXT:[[TMP7:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP5]], <16 x i8> [[TMP6]]) -// CHECK-NEXT:store <512 x i1> [[TMP7]], ptr [[VQ3]], align 64 -// CHECK-NEXT:[[TMP8:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 -// CHECK-NEXT:[[TMP9:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-NEXT:store <512 x i1> [[TMP8]], ptr [[TMP9]], align 64 +// CHECK-NEXT:[[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]]) +// CHECK-NEXT:store <512 x i1> [[TMP6]], ptr [[VQ3]], align 64 +// CHECK-NEXT:[[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 +// CHECK-NEXT:[[TMP8:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-NEXT:store <512 x i1> [[TMP7]], ptr [[TMP8]], align 64 // CHECK-NEXT:ret void // // CHECK-BE-LABEL: @testVQLocal( @@ -42,18 +42,18 @@ // CHECK-BE-NEXT:store <16 x i8> [[VC:%.*]], ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // CHECK-BE-NEXT:store ptr [[TMP0]], ptr [[VQP]], align 8 -// CHECK-BE-NEXT:[[TMP2:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-BE-NEXT:[[TMP3:%.*]] = load <512 x i1>, ptr [[TMP2]], align 64 -// CHECK-BE-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ1]], align 64 -// CHECK-BE-NEXT:[[TMP4:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() -// CHECK-BE-NEXT:store <512 x i1> [[TMP4]], ptr [[VQ2]], align 64 +// CHECK-BE-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-BE-NEXT:[[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64 +// CHECK-BE-NEXT:store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64 +// CHECK-BE-NEXT:[[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() +// CHECK-BE-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64 +// CHECK-BE-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-BE-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-BE-NEXT:[[TMP7:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP5]], <16 x i8> [[TMP6]]) -// CHECK-BE-NEXT:store <512 x i1> [[TMP7]], ptr [[VQ3]], align 64 -// CHECK-BE-NEXT:[[TMP8:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 -// CHECK-BE-NEXT:[[TMP9:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-BE-NEXT:store <512 x i1> [[TMP8]], ptr [[TMP9]], align 64 +// CHECK-BE-NEXT:[[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]]) +// CHECK-BE-NEXT:store <512 x i1> [[TMP6]]
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 updated https://github.com/llvm/llvm-project/pull/108584 >From 70077d359e2f98a3c4b24fcf638a51c6a0272473 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 13 Sep 2024 15:00:19 + Subject: [PATCH 1/2] [PowerPC][NFC] autogen mma tc checks via llvm/utils/update_cc_test_checks.py Checks for clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c seem to have been manually upated to rename temp variables even though it says checks was auto generated. Regenerate via script in prep for changes needed in a followup patch. --- .../PowerPC/builtins-ppc-pair-mma-types.c | 204 +- 1 file changed, 102 insertions(+), 102 deletions(-) diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c index a414a2827b2c43..39c040967dc0c3 100644 --- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c @@ -16,18 +16,18 @@ // CHECK-NEXT:store <16 x i8> [[VC:%.*]], ptr [[VC_ADDR]], align 16 // CHECK-NEXT:[[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // CHECK-NEXT:store ptr [[TMP0]], ptr [[VQP]], align 8 -// CHECK-NEXT:[[TMP2:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-NEXT:[[TMP3:%.*]] = load <512 x i1>, ptr [[TMP2]], align 64 -// CHECK-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ1]], align 64 -// CHECK-NEXT:[[TMP4:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() -// CHECK-NEXT:store <512 x i1> [[TMP4]], ptr [[VQ2]], align 64 +// CHECK-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-NEXT:[[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64 +// CHECK-NEXT:store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64 +// CHECK-NEXT:[[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() +// CHECK-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64 +// CHECK-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-NEXT:[[TMP7:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP5]], <16 x i8> [[TMP6]]) -// CHECK-NEXT:store <512 x i1> [[TMP7]], ptr [[VQ3]], align 64 -// CHECK-NEXT:[[TMP8:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 -// CHECK-NEXT:[[TMP9:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-NEXT:store <512 x i1> [[TMP8]], ptr [[TMP9]], align 64 +// CHECK-NEXT:[[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]]) +// CHECK-NEXT:store <512 x i1> [[TMP6]], ptr [[VQ3]], align 64 +// CHECK-NEXT:[[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 +// CHECK-NEXT:[[TMP8:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-NEXT:store <512 x i1> [[TMP7]], ptr [[TMP8]], align 64 // CHECK-NEXT:ret void // // CHECK-BE-LABEL: @testVQLocal( @@ -42,18 +42,18 @@ // CHECK-BE-NEXT:store <16 x i8> [[VC:%.*]], ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT:[[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8 // CHECK-BE-NEXT:store ptr [[TMP0]], ptr [[VQP]], align 8 -// CHECK-BE-NEXT:[[TMP2:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-BE-NEXT:[[TMP3:%.*]] = load <512 x i1>, ptr [[TMP2]], align 64 -// CHECK-BE-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ1]], align 64 -// CHECK-BE-NEXT:[[TMP4:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() -// CHECK-BE-NEXT:store <512 x i1> [[TMP4]], ptr [[VQ2]], align 64 +// CHECK-BE-NEXT:[[TMP1:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-BE-NEXT:[[TMP2:%.*]] = load <512 x i1>, ptr [[TMP1]], align 64 +// CHECK-BE-NEXT:store <512 x i1> [[TMP2]], ptr [[VQ1]], align 64 +// CHECK-BE-NEXT:[[TMP3:%.*]] = call <512 x i1> @llvm.ppc.mma.xxsetaccz() +// CHECK-BE-NEXT:store <512 x i1> [[TMP3]], ptr [[VQ2]], align 64 +// CHECK-BE-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 // CHECK-BE-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-BE-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16 -// CHECK-BE-NEXT:[[TMP7:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP5]], <16 x i8> [[TMP6]]) -// CHECK-BE-NEXT:store <512 x i1> [[TMP7]], ptr [[VQ3]], align 64 -// CHECK-BE-NEXT:[[TMP8:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 -// CHECK-BE-NEXT:[[TMP9:%.*]] = load ptr, ptr [[VQP]], align 8 -// CHECK-BE-NEXT:store <512 x i1> [[TMP8]], ptr [[TMP9]], align 64 +// CHECK-BE-NEXT:[[TMP6:%.*]] = call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> [[TMP4]], <16 x i8> [[TMP5]]) +// CHECK-BE-NEXT:store <512 x i1> [[TMP6]], ptr [[VQ3]], align 64 +// CHECK-BE-NEXT:[[TMP7:%.*]] = load <512 x i1>, ptr [[VQ3]], align 64 +// CHECK-BE-NEXT:[[TMP8:%.*]] = load ptr, ptr [[VQP]], align 8 +// CHECK-BE-NEXT:store <512 x i1> [[TMP7]], ptr [[TMP8]], align 64 // C
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/108584 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/108584 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 edited https://github.com/llvm/llvm-project/pull/108584 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC][NFC] autogen mma tc checks via update_cc_test_checks (PR #108584)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/108584 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (PR #108606)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/108606
Fixes #107229
>From 2c268981bb25cd1a1ed6c121789c5bd763fb1296 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 13 Sep 2024 17:11:09 +
Subject: [PATCH] [PowerPC] Fix incorrect store alignment for
__builtin_vsx_build_pair()
Fixes #107229
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c | 2 +-
clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c | 8
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a52e880a764252..5db5ad5470c366 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18197,7 +18197,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
CallOps.push_back(Ops[i]);
llvm::Function *F = CGM.getIntrinsic(ID);
Value *Call = Builder.CreateCall(F, CallOps);
-return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign(64));
+return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign());
}
case PPC::BI__builtin_ppc_compare_and_swap:
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
index 8a2bc93dd6cd0a..cdbfdd6b7975ad 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
@@ -99,7 +99,7 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector
unsigned char vc1, vec
// CHECK-LE-NOOPT-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC1_ADDR]],
align 16
// CHECK-LE-NOOPT-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC2_ADDR]],
align 16
// CHECK-LE-NOOPT-NEXT:[[TMP6:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP5]], <16 x i8> [[TMP4]])
-// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP6]], ptr [[RES]], align 64
+// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP6]], ptr [[RES]], align 32
// CHECK-LE-NOOPT-NEXT:[[TMP7:%.*]] = load <256 x i1>, ptr [[RES]], align
32
// CHECK-LE-NOOPT-NEXT:[[TMP8:%.*]] = load ptr, ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP7]], ptr [[TMP8]], align 32
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
index 39c040967dc0c3..b18bb3ad050aca 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
@@ -85,11 +85,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
// CHECK-NEXT:[[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP5:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
-// CHECK-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 64
+// CHECK-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 32
// CHECK-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP8:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP7]], <16 x i8> [[TMP6]])
-// CHECK-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
+// CHECK-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 32
// CHECK-NEXT:[[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
// CHECK-NEXT:[[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256
x i1> [[TMP9]], <16 x i8> [[TMP10]])
@@ -118,11 +118,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
// CHECK-BE-NEXT:[[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP5:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
-// CHECK-BE-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 64
+// CHECK-BE-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 32
// CHECK-BE-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP8:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP6]], <16 x i8> [[TMP7]])
-// CHECK-BE-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
+// CHECK-BE-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 32
// CHECK-BE-NEXT:[[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
// CHECK-BE-NEXT:[[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP11:%.*]] = call <512 x i1>
@llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]])
___
cfe
[clang] [PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (PR #108606)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/108606
>From 7d0d50768c75f57663d1c487157c8969e621f128 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Fri, 13 Sep 2024 17:11:09 +
Subject: [PATCH] [PowerPC] Fix incorrect store alignment for
__builtin_vsx_build_pair()
Fixes #107229
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c | 2 +-
clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c | 8
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 659b76dd7994b3..fab055213261ed 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18175,7 +18175,7 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
CallOps.push_back(Ops[i]);
llvm::Function *F = CGM.getIntrinsic(ID);
Value *Call = Builder.CreateCall(F, CallOps);
-return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign(64));
+return Builder.CreateAlignedStore(Call, Ops[0], MaybeAlign());
}
case PPC::BI__builtin_ppc_compare_and_swap:
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
index 8a2bc93dd6cd0a..cdbfdd6b7975ad 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
@@ -99,7 +99,7 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector
unsigned char vc1, vec
// CHECK-LE-NOOPT-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC1_ADDR]],
align 16
// CHECK-LE-NOOPT-NEXT:[[TMP5:%.*]] = load <16 x i8>, ptr [[VC2_ADDR]],
align 16
// CHECK-LE-NOOPT-NEXT:[[TMP6:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP5]], <16 x i8> [[TMP4]])
-// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP6]], ptr [[RES]], align 64
+// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP6]], ptr [[RES]], align 32
// CHECK-LE-NOOPT-NEXT:[[TMP7:%.*]] = load <256 x i1>, ptr [[RES]], align
32
// CHECK-LE-NOOPT-NEXT:[[TMP8:%.*]] = load ptr, ptr [[RESP_ADDR]], align 8
// CHECK-LE-NOOPT-NEXT:store <256 x i1> [[TMP7]], ptr [[TMP8]], align 32
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
index 39c040967dc0c3..b18bb3ad050aca 100644
--- a/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
+++ b/clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
@@ -85,11 +85,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
// CHECK-NEXT:[[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP5:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
-// CHECK-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 64
+// CHECK-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 32
// CHECK-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP8:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP7]], <16 x i8> [[TMP6]])
-// CHECK-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
+// CHECK-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 32
// CHECK-NEXT:[[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
// CHECK-NEXT:[[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-NEXT:[[TMP11:%.*]] = call <512 x i1> @llvm.ppc.mma.xvf64ger(<256
x i1> [[TMP9]], <16 x i8> [[TMP10]])
@@ -118,11 +118,11 @@ void testVQLocal(int *ptr, vector unsigned char vc) {
// CHECK-BE-NEXT:[[TMP3:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP4:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP5:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP3]], <16 x i8> [[TMP4]])
-// CHECK-BE-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 64
+// CHECK-BE-NEXT:store <256 x i1> [[TMP5]], ptr [[VP2]], align 32
// CHECK-BE-NEXT:[[TMP6:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP7:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP8:%.*]] = call <256 x i1>
@llvm.ppc.vsx.assemble.pair(<16 x i8> [[TMP6]], <16 x i8> [[TMP7]])
-// CHECK-BE-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 64
+// CHECK-BE-NEXT:store <256 x i1> [[TMP8]], ptr [[VP2]], align 32
// CHECK-BE-NEXT:[[TMP9:%.*]] = load <256 x i1>, ptr [[VP3]], align 32
// CHECK-BE-NEXT:[[TMP10:%.*]] = load <16 x i8>, ptr [[VC_ADDR]], align 16
// CHECK-BE-NEXT:[[TMP11:%.*]] = call <512 x i1>
@llvm.ppc.mma.xvf64ger(<256 x i1> [[TMP9]], <16 x i8> [[TMP10]])
___
cfe-commits mailin
[clang] [PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (PR #108606)
https://github.com/lei137 closed https://github.com/llvm/llvm-project/pull/108606 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [PowerPC] Fix incorrect store alignment for __builtin_vsx_build_pair() (PR #108606)
lei137 wrote: > Will this affect the code that is generated for ‘__vector_quad’ values? There > is no direct way to load and store those so they will use pair loads and > stores. Not AFAIK. The change will get the alignment from the type given. The LIT test being updated also have `alloca` and `store` of vector quads. The alignment for those instructions stayed 64bit. https://github.com/llvm/llvm-project/pull/108606 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [PowerPC] Update data layout aligment of i128 to 16 (PR #118004)
https://github.com/lei137 created
https://github.com/llvm/llvm-project/pull/118004
Fix 64-bit PowerPC part of https://github.com/llvm/llvm-project/issues/102783.
>From 6abea65c2667ecc0389c95e8a5527c360317524b Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Wed, 27 Nov 2024 18:44:38 +
Subject: [PATCH 1/5] update llc tc affected
---
.../CostModel/PowerPC/load-to-trunc.ll| 4 +-
llvm/test/CodeGen/PowerPC/ctrloop-sh.ll | 58 ++-
llvm/test/CodeGen/PowerPC/pr59074.ll | 29 +-
...lar-shift-by-byte-multiple-legalization.ll | 48 +++
.../PowerPC/wide-scalar-shift-legalization.ll | 33 ++-
.../AtomicExpand/PowerPC/cmpxchg.ll | 6 +-
6 files changed, 92 insertions(+), 86 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
b/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
index 57a6e98cfb4ee6..b78d121ff4f389 100644
--- a/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
+++ b/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
@@ -7,7 +7,7 @@
; Check that cost is 1 for unusual load to register sized load.
define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) {
; CHECK-LABEL: 'loadUnusualIntegerWithTrunc'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out
= load i128, ptr %ptr, align 8
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out
= load i128, ptr %ptr, align 16
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction:
%trunc = trunc i128 %out to i32
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret
i32 %trunc
;
@@ -18,7 +18,7 @@ define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) {
define i128 @loadUnusualInteger(ptr %ptr) {
; CHECK-LABEL: 'loadUnusualInteger'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %out
= load i128, ptr %ptr, align 8
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %out
= load i128, ptr %ptr, align 16
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret
i128 %out
;
%out = load i128, ptr %ptr
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
b/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
index 72de456cba395b..19f86f9d1af6ff 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
@@ -16,39 +16,41 @@ define void @foo1(ptr %a, ptr readonly %b, ptr readonly %c)
#0 {
; CHECK-NEXT:addi 7, 1, 16
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT:#
-; CHECK-NEXT:lwz 8, 0(4)
; CHECK-NEXT:lwz 9, 4(4)
+; CHECK-NEXT:lwz 8, 0(4)
; CHECK-NEXT:lwz 10, 8(4)
; CHECK-NEXT:lwz 11, 12(4)
; CHECK-NEXT:lwz 12, 12(5)
+; CHECK-NEXT:stw 9, 20(1)
+; CHECK-NEXT:mr 9, 7
; CHECK-NEXT:stw 6, 44(1)
+; CHECK-NEXT:rlwimi 9, 12, 29, 28, 29
; CHECK-NEXT:stw 6, 40(1)
; CHECK-NEXT:stw 6, 36(1)
; CHECK-NEXT:stw 6, 32(1)
; CHECK-NEXT:stw 11, 28(1)
; CHECK-NEXT:stw 10, 24(1)
; CHECK-NEXT:clrlwi 10, 12, 27
-; CHECK-NEXT:stw 9, 20(1)
; CHECK-NEXT:stw 8, 16(1)
-; CHECK-NEXT:rlwinm 8, 12, 29, 28, 29
-; CHECK-NEXT:lwzux 9, 8, 7
-; CHECK-NEXT:subfic 12, 10, 32
-; CHECK-NEXT:lwz 11, 8(8)
-; CHECK-NEXT:slw 9, 9, 10
-; CHECK-NEXT:lwz 0, 4(8)
-; CHECK-NEXT:lwz 8, 12(8)
-; CHECK-NEXT:srw 30, 11, 12
-; CHECK-NEXT:slw 29, 0, 10
-; CHECK-NEXT:srw 0, 0, 12
-; CHECK-NEXT:srw 12, 8, 12
-; CHECK-NEXT:slw 11, 11, 10
+; CHECK-NEXT:rlwinm 12, 12, 29, 28, 29
+; CHECK-NEXT:lwz 8, 8(9)
+; CHECK-NEXT:subfic 0, 10, 32
+; CHECK-NEXT:lwz 11, 4(9)
+; CHECK-NEXT:lwz 9, 12(9)
+; CHECK-NEXT:srw 30, 8, 0
+; CHECK-NEXT:lwzx 12, 7, 12
+; CHECK-NEXT:slw 29, 11, 10
+; CHECK-NEXT:srw 11, 11, 0
+; CHECK-NEXT:srw 0, 9, 0
; CHECK-NEXT:slw 8, 8, 10
-; CHECK-NEXT:stw 8, 12(3)
-; CHECK-NEXT:or 8, 11, 12
+; CHECK-NEXT:slw 12, 12, 10
+; CHECK-NEXT:or 8, 8, 0
; CHECK-NEXT:stw 8, 8(3)
-; CHECK-NEXT:or 8, 9, 0
+; CHECK-NEXT:or 8, 12, 11
+; CHECK-NEXT:slw 9, 9, 10
; CHECK-NEXT:stw 8, 0(3)
; CHECK-NEXT:or 8, 29, 30
+; CHECK-NEXT:stw 9, 12(3)
; CHECK-NEXT:stw 8, 4(3)
; CHECK-NEXT:bdnz .LBB0_1
; CHECK-NEXT: # %bb.2: # %for.end
@@ -77,11 +79,11 @@ for.end: ; preds =
%for.body
define void @foo2(ptr %a, ptr readonly %b, ptr readonly %c) #0 {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:stwu 1, -48(1)
-; CHECK-NEXT:stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT:stwu 1, -64(1)
+; CHECK-NEXT:stw 30, 56(1) # 4-byte Folded Spill
; CHECK-NEXT:li 6, 2048
; CHECK-NEXT:mtctr 6
-; CHECK-NEXT:addi 6, 1, 24
+; CHECK-NEXT:addi 6, 1, 32
; CHECK-NEXT: .LBB1_1: # %for.body
; CHECK-NEXT:#
; CHECK-NEXT:lwz 7, 0(4)
@@ -89,18 +91,18 @@ define void @foo2(ptr %a, ptr readonly %b, ptr readonly
[clang] [llvm] [PowerPC] Update data layout aligment of i128 to 16 (PR #118004)
https://github.com/lei137 updated
https://github.com/llvm/llvm-project/pull/118004
>From ae5beae74fcd7717bf40519c80a9d920625bb137 Mon Sep 17 00:00:00 2001
From: Lei Huang
Date: Wed, 27 Nov 2024 18:44:38 +
Subject: [PATCH 1/6] update llc tc affected
---
.../CostModel/PowerPC/load-to-trunc.ll| 4 +-
llvm/test/CodeGen/PowerPC/ctrloop-sh.ll | 58 ++-
llvm/test/CodeGen/PowerPC/pr59074.ll | 29 +-
...lar-shift-by-byte-multiple-legalization.ll | 48 +++
.../PowerPC/wide-scalar-shift-legalization.ll | 33 ++-
.../AtomicExpand/PowerPC/cmpxchg.ll | 6 +-
6 files changed, 92 insertions(+), 86 deletions(-)
diff --git a/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
b/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
index 57a6e98cfb4ee6..b78d121ff4f389 100644
--- a/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
+++ b/llvm/test/Analysis/CostModel/PowerPC/load-to-trunc.ll
@@ -7,7 +7,7 @@
; Check that cost is 1 for unusual load to register sized load.
define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) {
; CHECK-LABEL: 'loadUnusualIntegerWithTrunc'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out
= load i128, ptr %ptr, align 8
+; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %out
= load i128, ptr %ptr, align 16
; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction:
%trunc = trunc i128 %out to i32
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret
i32 %trunc
;
@@ -18,7 +18,7 @@ define i32 @loadUnusualIntegerWithTrunc(ptr %ptr) {
define i128 @loadUnusualInteger(ptr %ptr) {
; CHECK-LABEL: 'loadUnusualInteger'
-; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %out
= load i128, ptr %ptr, align 8
+; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %out
= load i128, ptr %ptr, align 16
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret
i128 %out
;
%out = load i128, ptr %ptr
diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
b/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
index 72de456cba395b..19f86f9d1af6ff 100644
--- a/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
+++ b/llvm/test/CodeGen/PowerPC/ctrloop-sh.ll
@@ -16,39 +16,41 @@ define void @foo1(ptr %a, ptr readonly %b, ptr readonly %c)
#0 {
; CHECK-NEXT:addi 7, 1, 16
; CHECK-NEXT: .LBB0_1: # %for.body
; CHECK-NEXT:#
-; CHECK-NEXT:lwz 8, 0(4)
; CHECK-NEXT:lwz 9, 4(4)
+; CHECK-NEXT:lwz 8, 0(4)
; CHECK-NEXT:lwz 10, 8(4)
; CHECK-NEXT:lwz 11, 12(4)
; CHECK-NEXT:lwz 12, 12(5)
+; CHECK-NEXT:stw 9, 20(1)
+; CHECK-NEXT:mr 9, 7
; CHECK-NEXT:stw 6, 44(1)
+; CHECK-NEXT:rlwimi 9, 12, 29, 28, 29
; CHECK-NEXT:stw 6, 40(1)
; CHECK-NEXT:stw 6, 36(1)
; CHECK-NEXT:stw 6, 32(1)
; CHECK-NEXT:stw 11, 28(1)
; CHECK-NEXT:stw 10, 24(1)
; CHECK-NEXT:clrlwi 10, 12, 27
-; CHECK-NEXT:stw 9, 20(1)
; CHECK-NEXT:stw 8, 16(1)
-; CHECK-NEXT:rlwinm 8, 12, 29, 28, 29
-; CHECK-NEXT:lwzux 9, 8, 7
-; CHECK-NEXT:subfic 12, 10, 32
-; CHECK-NEXT:lwz 11, 8(8)
-; CHECK-NEXT:slw 9, 9, 10
-; CHECK-NEXT:lwz 0, 4(8)
-; CHECK-NEXT:lwz 8, 12(8)
-; CHECK-NEXT:srw 30, 11, 12
-; CHECK-NEXT:slw 29, 0, 10
-; CHECK-NEXT:srw 0, 0, 12
-; CHECK-NEXT:srw 12, 8, 12
-; CHECK-NEXT:slw 11, 11, 10
+; CHECK-NEXT:rlwinm 12, 12, 29, 28, 29
+; CHECK-NEXT:lwz 8, 8(9)
+; CHECK-NEXT:subfic 0, 10, 32
+; CHECK-NEXT:lwz 11, 4(9)
+; CHECK-NEXT:lwz 9, 12(9)
+; CHECK-NEXT:srw 30, 8, 0
+; CHECK-NEXT:lwzx 12, 7, 12
+; CHECK-NEXT:slw 29, 11, 10
+; CHECK-NEXT:srw 11, 11, 0
+; CHECK-NEXT:srw 0, 9, 0
; CHECK-NEXT:slw 8, 8, 10
-; CHECK-NEXT:stw 8, 12(3)
-; CHECK-NEXT:or 8, 11, 12
+; CHECK-NEXT:slw 12, 12, 10
+; CHECK-NEXT:or 8, 8, 0
; CHECK-NEXT:stw 8, 8(3)
-; CHECK-NEXT:or 8, 9, 0
+; CHECK-NEXT:or 8, 12, 11
+; CHECK-NEXT:slw 9, 9, 10
; CHECK-NEXT:stw 8, 0(3)
; CHECK-NEXT:or 8, 29, 30
+; CHECK-NEXT:stw 9, 12(3)
; CHECK-NEXT:stw 8, 4(3)
; CHECK-NEXT:bdnz .LBB0_1
; CHECK-NEXT: # %bb.2: # %for.end
@@ -77,11 +79,11 @@ for.end: ; preds =
%for.body
define void @foo2(ptr %a, ptr readonly %b, ptr readonly %c) #0 {
; CHECK-LABEL: foo2:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:stwu 1, -48(1)
-; CHECK-NEXT:stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT:stwu 1, -64(1)
+; CHECK-NEXT:stw 30, 56(1) # 4-byte Folded Spill
; CHECK-NEXT:li 6, 2048
; CHECK-NEXT:mtctr 6
-; CHECK-NEXT:addi 6, 1, 24
+; CHECK-NEXT:addi 6, 1, 32
; CHECK-NEXT: .LBB1_1: # %for.body
; CHECK-NEXT:#
; CHECK-NEXT:lwz 7, 0(4)
@@ -89,18 +91,18 @@ define void @foo2(ptr %a, ptr readonly %b, ptr readonly %c)
#0 {
; CHECK-NEXT:lwz 11, 12(5)
; CHECK-NEXT:lwz 9, 8(4)
; CHECK
