[clang] [AArch64][SVE] Fold svrev(svrev(v)) to v (PR #116422)

2024-11-15 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto created 
https://github.com/llvm/llvm-project/pull/116422

This PR follows the approach specified in 
https://github.com/llvm/llvm-project/issues/110444#issuecomment-2391540986 by 
making clang emit `llvm.vector.reverse` instead of `llvm.aarch64.sve.rev`, 
meaning instcombine then folds `svrev(svrev(v))` into `v`

>From 61a071a0e5247d6572cb31fcf0fb7b2a78a150c8 Mon Sep 17 00:00:00 2001
From: Jorge Botto 
Date: Fri, 15 Nov 2024 18:56:54 +
Subject: [PATCH] Making Clang emit llvm.vector.reverse instead of
 llvm.aarch64.sve.rev

---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../AArch64/sve-intrinsics/acle_sve_rev.c | 44 +--
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index d492fae4145b92..500f76bc10f2f2 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1058,7 +1058,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
 def SVEXT: SInst<"svext[_{d}]",   "dddi", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2, 
ImmCheckExtract, 1>]>;
 defm SVLASTA : SVEPerm<"svlasta[_{d}]",   "sPd",  "aarch64_sve_lasta">;
 defm SVLASTB : SVEPerm<"svlastb[_{d}]",   "sPd",  "aarch64_sve_lastb">;
-def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_rev", [VerifyRuntimeMode]>;
+def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "vector_reverse", [VerifyRuntimeMode]>;
 def SVSEL: SInst<"svsel[_{d}]",   "dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_sel", [VerifyRuntimeMode]>;
 def SVSPLICE : SInst<"svsplice[_{d}]","dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_splice", [VerifyRuntimeMode]>;
 def SVTBL: SInst<"svtbl[_{d}]",   "ddu",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_tbl", [VerifyRuntimeMode]>;
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c 
b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
index 3c0ae7df79644f..835d1c616aebcb 100644
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
+++ b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
@@ -24,12 +24,12 @@
 
 // CHECK-LABEL: @test_svrev_s8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z13test_svrev_s8u10__SVInt8_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
@@ -39,12 +39,12 @@ svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s16u11__SVInt16_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
@@ -54,12 +54,12 @@ svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s32u11__SVInt32_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
@@ -69,12 +69,12 @@ svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s64u11__SVInt64_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret

[clang] [AArch64][SVE] Fold svrev(svrev(v)) to v (PR #116422)

2025-01-18 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto ready_for_review 
https://github.com/llvm/llvm-project/pull/116422
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[clang] [AArch64][SVE] Fold svrev(svrev(v)) to v (PR #116422)

2025-01-18 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto updated 
https://github.com/llvm/llvm-project/pull/116422

>From fdd0495d57ea7f59ba201b2b570d05d1ed144c99 Mon Sep 17 00:00:00 2001
From: Jorge Botto 
Date: Fri, 15 Nov 2024 18:56:54 +
Subject: [PATCH] Making Clang emit llvm.vector.reverse instead of
 llvm.aarch64.sve.rev

---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../AArch64/sve-intrinsics/acle_sve_rev.c | 44 +--
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index ac1c139b209434..93d5f3265b9b7d 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1060,7 +1060,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
 def SVEXT: SInst<"svext[_{d}]",   "dddi", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2, 
ImmCheckExtract, 1>]>;
 defm SVLASTA : SVEPerm<"svlasta[_{d}]",   "sPd",  "aarch64_sve_lasta">;
 defm SVLASTB : SVEPerm<"svlastb[_{d}]",   "sPd",  "aarch64_sve_lastb">;
-def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_rev", [VerifyRuntimeMode]>;
+def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "vector_reverse", [VerifyRuntimeMode]>;
 def SVSEL: SInst<"svsel[_{d}]",   "dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_sel", [VerifyRuntimeMode]>;
 def SVSPLICE : SInst<"svsplice[_{d}]","dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_splice", [VerifyRuntimeMode]>;
 def SVTBL: SInst<"svtbl[_{d}]",   "ddu",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_tbl", [VerifyRuntimeMode]>;
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c 
b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
index 3c0ae7df79644f..835d1c616aebcb 100644
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
+++ b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
@@ -24,12 +24,12 @@
 
 // CHECK-LABEL: @test_svrev_s8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z13test_svrev_s8u10__SVInt8_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
@@ -39,12 +39,12 @@ svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s16u11__SVInt16_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
@@ -54,12 +54,12 @@ svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s32u11__SVInt32_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
@@ -69,12 +69,12 @@ svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s64u11__SVInt64_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint64_t test_svrev_s64(svint64_t op) MODE_ATTR
@@ -84,12 +84,12 @@ svint64_t test_svrev_s64(svint64_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_u8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.

[clang] [AArch64][SVE] Fold svrev(svrev(v)) to v (PR #116422)

2025-01-18 Thread Jorge Botto via cfe-commits 

jf-botto wrote:

Sorry @MacDue, just wanted to check a few things before removing draft status.

https://github.com/llvm/llvm-project/pull/116422
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[clang] [AArch64][SVE] Fold svrev(svrev(v)) to v (PR #116422)

2025-01-18 Thread Jorge Botto via cfe-commits 

jf-botto wrote:

@sdesmalen-arm fyi

https://github.com/llvm/llvm-project/pull/116422
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[clang] [Arch64][SVE] Lower svrev_* to llvm.vector.reverse (PR #116422)

2025-01-20 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto edited 
https://github.com/llvm/llvm-project/pull/116422
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[clang] [llvm] [Arch64][SVE] Lower svrev_* to llvm.vector.reverse and fold svrev(svrev(x)) -> x (PR #116422)

2025-02-12 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto edited 
https://github.com/llvm/llvm-project/pull/116422
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[clang] [llvm] [Arch64][SVE] Lower svrev_* to llvm.vector.reverse and fold svrev(svrev(x)) -> x (PR #116422)

2025-02-12 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto edited 
https://github.com/llvm/llvm-project/pull/116422
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[clang] [llvm] [Arch64][SVE] Lower svrev_* to llvm.vector.reverse (PR #116422)

2025-02-09 Thread Jorge Botto via cfe-commits 

https://github.com/jf-botto updated 
https://github.com/llvm/llvm-project/pull/116422

>From 75cc7d90fa8a7f0cde0df969577556ac1098256b Mon Sep 17 00:00:00 2001
From: Jorge Botto 
Date: Fri, 15 Nov 2024 18:56:54 +
Subject: [PATCH 1/4] Making Clang emit llvm.vector.reverse instead of
 llvm.aarch64.sve.rev

---
 clang/include/clang/Basic/arm_sve.td  |  2 +-
 .../AArch64/sve-intrinsics/acle_sve_rev.c | 44 +--
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/clang/include/clang/Basic/arm_sve.td 
b/clang/include/clang/Basic/arm_sve.td
index b20383e72e66a37..c954a6582171728 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1060,7 +1060,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
 def SVEXT: SInst<"svext[_{d}]",   "dddi", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2, 
ImmCheckExtract, 1>]>;
 defm SVLASTA : SVEPerm<"svlasta[_{d}]",   "sPd",  "aarch64_sve_lasta">;
 defm SVLASTB : SVEPerm<"svlastb[_{d}]",   "sPd",  "aarch64_sve_lastb">;
-def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_rev", [VerifyRuntimeMode]>;
+def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "vector_reverse", [VerifyRuntimeMode]>;
 def SVSEL: SInst<"svsel[_{d}]",   "dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_sel", [VerifyRuntimeMode]>;
 def SVSPLICE : SInst<"svsplice[_{d}]","dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_splice", [VerifyRuntimeMode]>;
 def SVTBL: SInst<"svtbl[_{d}]",   "ddu",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_tbl", [VerifyRuntimeMode]>;
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c 
b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
index 3c0ae7df79644fa..835d1c616aebcb0 100644
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
+++ b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_rev.c
@@ -24,12 +24,12 @@
 
 // CHECK-LABEL: @test_svrev_s8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z13test_svrev_s8u10__SVInt8_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv16i8( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv16i8( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
@@ -39,12 +39,12 @@ svint8_t test_svrev_s8(svint8_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s16u11__SVInt16_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv8i16( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv8i16( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
@@ -54,12 +54,12 @@ svint16_t test_svrev_s16(svint16_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s32u11__SVInt32_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv4i32( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv4i32( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
@@ -69,12 +69,12 @@ svint32_t test_svrev_s32(svint32_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_s64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CHECK-NEXT:ret  [[TMP0]]
 //
 // CPP-CHECK-LABEL: @_Z14test_svrev_s64u11__SVInt64_t(
 // CPP-CHECK-NEXT:  entry:
-// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarch64.sve.rev.nxv2i64( [[OP:%.*]])
+// CPP-CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.vector.reverse.nxv2i64( [[OP:%.*]])
 // CPP-CHECK-NEXT:ret  [[TMP0]]
 //
 svint64_t test_svrev_s64(svint64_t op) MODE_ATTR
@@ -84,12 +84,12 @@ svint64_t test_svrev_s64(svint64_t op) MODE_ATTR
 
 // CHECK-LABEL: @test_svrev_u8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call  
@llvm.aarc

[clang] [llvm] [Arch64][SVE] Lower svrev_* to llvm.vector.reverse (PR #116422)

2025-02-09 Thread Jorge Botto via cfe-commits 


@@ -1060,7 +1060,7 @@ let SVETargetGuard = "sve,bf16", SMETargetGuard = 
"sme,bf16" in {
 def SVEXT: SInst<"svext[_{d}]",   "dddi", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_ext", [VerifyRuntimeMode], [ImmCheck<2, 
ImmCheckExtract, 1>]>;
 defm SVLASTA : SVEPerm<"svlasta[_{d}]",   "sPd",  "aarch64_sve_lasta">;
 defm SVLASTB : SVEPerm<"svlastb[_{d}]",   "sPd",  "aarch64_sve_lastb">;
-def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_rev", [VerifyRuntimeMode]>;
+def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", 
MergeNone, "vector_reverse", [VerifyRuntimeMode]>;

jf-botto wrote:

Thank you for your comment and the explanation. I've fixed PR accordingly.

https://github.com/llvm/llvm-project/pull/116422
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