[clang] [llvm] [Hexagon] Add Loop Alignment pass. (PR #83379)

2024-02-29 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar approved this pull request.


https://github.com/llvm/llvm-project/pull/83379
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[clang] [hexagon] Add {con, de}structive interference size defn (PR #94877)

2024-06-10 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar approved this pull request.


https://github.com/llvm/llvm-project/pull/94877
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[clang] [Hexagon][Docs] document the change in the default target (PR #125584)

2025-02-03 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar created 
https://github.com/llvm/llvm-project/pull/125584

None

>From 59b76081f1c15c38f2b58ffce062dadce12d5811 Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Mon, 3 Feb 2025 12:47:22 -0800
Subject: [PATCH] [Hexagon][Docs] document the change in the default target

---
 clang/docs/ReleaseNotes.rst | 5 +
 1 file changed, 5 insertions(+)

diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 4266d6c523ab97..33a37bdf3f328a 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -161,6 +161,11 @@ AMDGPU Support
 NVPTX Support
 ^^
 
+Hexagon Support
+^^^
+
+-  The default compilation target has been changed from V60 to V68.
+
 X86 Support
 ^^^
 

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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-02-03 Thread Ikhlas Ajbar via cfe-commits 

iajbar wrote:

I opened a SuperOps ticket SUPEROPS-12973 to update the 21.0 release notes.

https://github.com/llvm/llvm-project/pull/125239
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[clang] [Hexagon][Docs] document the change in the default target (PR #125584)

2025-02-03 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar closed 
https://github.com/llvm/llvm-project/pull/125584
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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-02-03 Thread Ikhlas Ajbar via cfe-commits 

iajbar wrote:

Done. Thanks Brian.

https://github.com/llvm/llvm-project/pull/125239
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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-01-31 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar created 
https://github.com/llvm/llvm-project/pull/125239

Set the default compilation target to V68 if no Hexagon processor is specified 
at the command-line.
Add the elf header changes for v81/v83/v85 architectures.

>From 041813a5de078adaf8d86bbeb2c92f19ce5828eb Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Thu, 30 Jan 2025 15:35:51 -0800
Subject: [PATCH] [Hexagon] Set the default compilation target to V68

Set the default compilation target to V68 if no Hexagon processor is specified
at the command-line.
Add the elf header changes for v81/v83/v85 architectures.
---
 clang/lib/Driver/ToolChains/Hexagon.cpp |  2 +-
 clang/test/Driver/hexagon-cpu-default.c |  4 
 llvm/include/llvm/BinaryFormat/ELF.h| 10 ++
 3 files changed, 15 insertions(+), 1 deletion(-)
 create mode 100644 clang/test/Driver/hexagon-cpu-default.c

diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp 
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 76cedf312d68a1..91dd582eb05a00 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -803,7 +803,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const 
llvm::opt::ArgList &Args) {
 // if no Hexagon processor is selected at the command-line.
 //
 StringRef HexagonToolChain::GetDefaultCPU() {
-  return "hexagonv60";
+  return "hexagonv68";
 }
 
 StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) {
diff --git a/clang/test/Driver/hexagon-cpu-default.c 
b/clang/test/Driver/hexagon-cpu-default.c
new file mode 100644
index 00..31fb839f216569
--- /dev/null
+++ b/clang/test/Driver/hexagon-cpu-default.c
@@ -0,0 +1,4 @@
+// CHECK: "-target-cpu" "hexagonv68"
+
+// RUN: %clang -c %s -### --target=hexagon-unknown-elf \
+// RUN:  2>&1 | FileCheck  %s
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h 
b/llvm/include/llvm/BinaryFormat/ELF.h
index 48ae0db80f43ee..8853c4a88b0b59 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -619,6 +619,7 @@ enum {
   EF_HEXAGON_MACH_V5 = 0x0004,   // Hexagon V5
   EF_HEXAGON_MACH_V55 = 0x0005,  // Hexagon V55
   EF_HEXAGON_MACH_V60 = 0x0060,  // Hexagon V60
+  EF_HEXAGON_MACH_V61 = 0x0061,  // Hexagon V61
   EF_HEXAGON_MACH_V62 = 0x0062,  // Hexagon V62
   EF_HEXAGON_MACH_V65 = 0x0065,  // Hexagon V65
   EF_HEXAGON_MACH_V66 = 0x0066,  // Hexagon V66
@@ -630,7 +631,11 @@ enum {
   EF_HEXAGON_MACH_V71T = 0x8071, // Hexagon V71T
   EF_HEXAGON_MACH_V73 = 0x0073,  // Hexagon V73
   EF_HEXAGON_MACH_V75 = 0x0075,  // Hexagon V75
+  EF_HEXAGON_MACH_V77 = 0x0077,  // Hexagon V77
   EF_HEXAGON_MACH_V79 = 0x0079,  // Hexagon V79
+  EF_HEXAGON_MACH_V81 = 0x0081,  // Hexagon V81
+  EF_HEXAGON_MACH_V83 = 0x0083,  // Hexagon V83
+  EF_HEXAGON_MACH_V85 = 0x0085,  // Hexagon V85
   EF_HEXAGON_MACH = 0x03ff,  // Hexagon V..
 
   // Highest ISA version flags
@@ -642,6 +647,7 @@ enum {
   EF_HEXAGON_ISA_V5 = 0x0040,   // Hexagon V5 ISA
   EF_HEXAGON_ISA_V55 = 0x0050,  // Hexagon V55 ISA
   EF_HEXAGON_ISA_V60 = 0x0060,  // Hexagon V60 ISA
+  EF_HEXAGON_ISA_V61 = 0x0061,  // Hexagon V61 ISA
   EF_HEXAGON_ISA_V62 = 0x0062,  // Hexagon V62 ISA
   EF_HEXAGON_ISA_V65 = 0x0065,  // Hexagon V65 ISA
   EF_HEXAGON_ISA_V66 = 0x0066,  // Hexagon V66 ISA
@@ -651,7 +657,11 @@ enum {
   EF_HEXAGON_ISA_V71 = 0x0071,  // Hexagon V71 ISA
   EF_HEXAGON_ISA_V73 = 0x0073,  // Hexagon V73 ISA
   EF_HEXAGON_ISA_V75 = 0x0075,  // Hexagon V75 ISA
+  EF_HEXAGON_ISA_V77 = 0x0077,  // Hexagon V77 ISA
   EF_HEXAGON_ISA_V79 = 0x0079,  // Hexagon V79 ISA
+  EF_HEXAGON_ISA_V81 = 0x0081,  // Hexagon V81 ISA
+  EF_HEXAGON_ISA_V83 = 0x0083,  // Hexagon V83 ISA
+  EF_HEXAGON_ISA_V85 = 0x0085,  // Hexagon V85 ISA
   EF_HEXAGON_ISA = 0x03ff,  // Hexagon V.. ISA
 };
 

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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-01-31 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar updated 
https://github.com/llvm/llvm-project/pull/125239

>From 31d9cadd9c14e703af6eafa20a5c6e4a69b9c526 Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Thu, 30 Jan 2025 15:35:51 -0800
Subject: [PATCH] [Hexagon] Set the default compilation target to V68

Set the default compilation target to V68 if no Hexagon processor is specified
at the command-line.
Add the elf header changes for v81/v83/v85 architectures.
---
 clang/lib/Driver/ToolChains/Hexagon.cpp |  4 +---
 clang/test/Driver/hexagon-cpu-default.c |  4 
 llvm/include/llvm/BinaryFormat/ELF.h| 10 ++
 3 files changed, 15 insertions(+), 3 deletions(-)
 create mode 100644 clang/test/Driver/hexagon-cpu-default.c

diff --git a/clang/lib/Driver/ToolChains/Hexagon.cpp 
b/clang/lib/Driver/ToolChains/Hexagon.cpp
index 76cedf312d68a1..7ca5ab9af88106 100644
--- a/clang/lib/Driver/ToolChains/Hexagon.cpp
+++ b/clang/lib/Driver/ToolChains/Hexagon.cpp
@@ -802,9 +802,7 @@ bool HexagonToolChain::isAutoHVXEnabled(const 
llvm::opt::ArgList &Args) {
 // Returns the default CPU for Hexagon. This is the default compilation target
 // if no Hexagon processor is selected at the command-line.
 //
-StringRef HexagonToolChain::GetDefaultCPU() {
-  return "hexagonv60";
-}
+StringRef HexagonToolChain::GetDefaultCPU() { return "hexagonv68"; }
 
 StringRef HexagonToolChain::GetTargetCPUVersion(const ArgList &Args) {
   Arg *CpuArg = nullptr;
diff --git a/clang/test/Driver/hexagon-cpu-default.c 
b/clang/test/Driver/hexagon-cpu-default.c
new file mode 100644
index 00..31fb839f216569
--- /dev/null
+++ b/clang/test/Driver/hexagon-cpu-default.c
@@ -0,0 +1,4 @@
+// CHECK: "-target-cpu" "hexagonv68"
+
+// RUN: %clang -c %s -### --target=hexagon-unknown-elf \
+// RUN:  2>&1 | FileCheck  %s
diff --git a/llvm/include/llvm/BinaryFormat/ELF.h 
b/llvm/include/llvm/BinaryFormat/ELF.h
index 48ae0db80f43ee..8853c4a88b0b59 100644
--- a/llvm/include/llvm/BinaryFormat/ELF.h
+++ b/llvm/include/llvm/BinaryFormat/ELF.h
@@ -619,6 +619,7 @@ enum {
   EF_HEXAGON_MACH_V5 = 0x0004,   // Hexagon V5
   EF_HEXAGON_MACH_V55 = 0x0005,  // Hexagon V55
   EF_HEXAGON_MACH_V60 = 0x0060,  // Hexagon V60
+  EF_HEXAGON_MACH_V61 = 0x0061,  // Hexagon V61
   EF_HEXAGON_MACH_V62 = 0x0062,  // Hexagon V62
   EF_HEXAGON_MACH_V65 = 0x0065,  // Hexagon V65
   EF_HEXAGON_MACH_V66 = 0x0066,  // Hexagon V66
@@ -630,7 +631,11 @@ enum {
   EF_HEXAGON_MACH_V71T = 0x8071, // Hexagon V71T
   EF_HEXAGON_MACH_V73 = 0x0073,  // Hexagon V73
   EF_HEXAGON_MACH_V75 = 0x0075,  // Hexagon V75
+  EF_HEXAGON_MACH_V77 = 0x0077,  // Hexagon V77
   EF_HEXAGON_MACH_V79 = 0x0079,  // Hexagon V79
+  EF_HEXAGON_MACH_V81 = 0x0081,  // Hexagon V81
+  EF_HEXAGON_MACH_V83 = 0x0083,  // Hexagon V83
+  EF_HEXAGON_MACH_V85 = 0x0085,  // Hexagon V85
   EF_HEXAGON_MACH = 0x03ff,  // Hexagon V..
 
   // Highest ISA version flags
@@ -642,6 +647,7 @@ enum {
   EF_HEXAGON_ISA_V5 = 0x0040,   // Hexagon V5 ISA
   EF_HEXAGON_ISA_V55 = 0x0050,  // Hexagon V55 ISA
   EF_HEXAGON_ISA_V60 = 0x0060,  // Hexagon V60 ISA
+  EF_HEXAGON_ISA_V61 = 0x0061,  // Hexagon V61 ISA
   EF_HEXAGON_ISA_V62 = 0x0062,  // Hexagon V62 ISA
   EF_HEXAGON_ISA_V65 = 0x0065,  // Hexagon V65 ISA
   EF_HEXAGON_ISA_V66 = 0x0066,  // Hexagon V66 ISA
@@ -651,7 +657,11 @@ enum {
   EF_HEXAGON_ISA_V71 = 0x0071,  // Hexagon V71 ISA
   EF_HEXAGON_ISA_V73 = 0x0073,  // Hexagon V73 ISA
   EF_HEXAGON_ISA_V75 = 0x0075,  // Hexagon V75 ISA
+  EF_HEXAGON_ISA_V77 = 0x0077,  // Hexagon V77 ISA
   EF_HEXAGON_ISA_V79 = 0x0079,  // Hexagon V79 ISA
+  EF_HEXAGON_ISA_V81 = 0x0081,  // Hexagon V81 ISA
+  EF_HEXAGON_ISA_V83 = 0x0083,  // Hexagon V83 ISA
+  EF_HEXAGON_ISA_V85 = 0x0085,  // Hexagon V85 ISA
   EF_HEXAGON_ISA = 0x03ff,  // Hexagon V.. ISA
 };
 

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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-01-31 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar closed 
https://github.com/llvm/llvm-project/pull/125239
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[clang] [llvm] [Hexagon] Add V75 support to compiler and assembler (PR #120773)

2024-12-20 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar created 
https://github.com/llvm/llvm-project/pull/120773

This patch introduces support for the Hexagon V75 architecture. It includes 
instruction formats, definitions, encodings, scheduling classes, and 
builtins/intrinsics.

>From 1d3ac02da5bfb00d86b123334e3a75628e47ef42 Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Fri, 13 Dec 2024 14:54:44 -0800
Subject: [PATCH] Add V75 support to compiler and assembler

This patch introduces support for the Hexagon V75 architecture.
It includes instruction formats, definitions, encodings, scheduling classes,
and builtins/intrinsics.
---
 clang/include/clang/Basic/BuiltinsHexagon.def |  10 +-
 clang/include/clang/Driver/Options.td |   2 +
 clang/lib/Basic/Targets/Hexagon.cpp   |   7 +-
 clang/test/Driver/hexagon-toolchain-elf.c |   7 +
 .../Misc/target-invalid-cpu-note/hexagon.c|   1 +
 clang/test/Preprocessor/hexagon-predefines.c  |  16 +
 llvm/include/llvm/BinaryFormat/ELF.h  |   1 +
 llvm/lib/Object/ELFObjectFile.cpp |   2 +
 llvm/lib/ObjectYAML/ELFYAML.cpp   |   2 +
 llvm/lib/Target/Hexagon/Hexagon.td|  14 +
 llvm/lib/Target/Hexagon/HexagonDepArch.h  |   4 +-
 llvm/lib/Target/Hexagon/HexagonDepArch.td |   2 +
 llvm/lib/Target/Hexagon/HexagonDepIICHVX.td   | 592 
 .../lib/Target/Hexagon/HexagonDepIICScalar.td | 888 ++
 llvm/lib/Target/Hexagon/HexagonSchedule.td|   1 +
 llvm/lib/Target/Hexagon/HexagonScheduleV75.td |  39 +
 llvm/lib/Target/Hexagon/HexagonSubtarget.h|   6 +
 .../MCTargetDesc/HexagonMCELFStreamer.cpp |   3 +
 .../MCTargetDesc/HexagonMCTargetDesc.cpp  |  41 +-
 llvm/test/MC/Hexagon/arch-support.s   |   9 +
 llvm/test/MC/Hexagon/v75_arch.s   |  10 +
 21 files changed, 1638 insertions(+), 19 deletions(-)
 create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV75.td
 create mode 100644 llvm/test/MC/Hexagon/v75_arch.s

diff --git a/clang/include/clang/Basic/BuiltinsHexagon.def 
b/clang/include/clang/Basic/BuiltinsHexagon.def
index 0dc0f4567dd413..ca3f99176110e3 100644
--- a/clang/include/clang/Basic/BuiltinsHexagon.def
+++ b/clang/include/clang/Basic/BuiltinsHexagon.def
@@ -17,8 +17,10 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+#pragma push_macro("V75")
+#define V75 "v75"
 #pragma push_macro("V73")
-#define V73 "v73"
+#define V73 "v73|" V75
 #pragma push_macro("V71")
 #define V71 "v71|" V73
 #pragma push_macro("V69")
@@ -40,8 +42,10 @@
 #pragma push_macro("V5")
 #define V5 "v5|" V55
 
+#pragma push_macro("HVXV75")
+#define HVXV75 "hvxv75"
 #pragma push_macro("HVXV73")
-#define HVXV73 "hvxv73"
+#define HVXV73 "hvxv73|" HVXV75
 #pragma push_macro("HVXV71")
 #define HVXV71 "hvxv71|" HVXV73
 #pragma push_macro("HVXV69")
@@ -143,6 +147,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("HVXV69")
 #pragma pop_macro("HVXV71")
 #pragma pop_macro("HVXV73")
+#pragma pop_macro("HVXV75")
 
 #pragma pop_macro("V5")
 #pragma pop_macro("V55")
@@ -155,6 +160,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("V69")
 #pragma pop_macro("V71")
 #pragma pop_macro("V73")
+#pragma pop_macro("V75")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 638f8c52053ec5..9edf308cc685ea 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6224,6 +6224,8 @@ def mv71t : Flag<["-"], "mv71t">, 
Group,
   Alias, AliasArgs<["hexagonv71t"]>;
 def mv73 : Flag<["-"], "mv73">, Group,
   Alias, AliasArgs<["hexagonv73"]>;
+def mv75 : Flag<["-"], "mv75">, Group,
+  Alias, AliasArgs<["hexagonv75"]>;
 def mhexagon_hvx : Flag<["-"], "mhvx">, Group,
   HelpText<"Enable Hexagon Vector eXtensions">;
 def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp 
b/clang/lib/Basic/Targets/Hexagon.cpp
index 0282ac812c306f..1fce0d0ed006ec 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -78,6 +78,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   } else if (CPU == "hexagonv73") {
 Builder.defineMacro("__HEXAGON_V73__");
 Builder.defineMacro("__HEXAGON_ARCH__", "73");
+  } else if (CPU == "hexagonv75") {
+Builder.defineMacro("__HEXAGON_V75__");
+Builder.defineMacro("__HEXAGON_ARCH__", "75");
   }
 
   if (hasFeature("hvx-length64b")) {
@@ -234,8 +237,8 @@ static constexpr CPUSuffix Suffixes[] = {
 {{"hexagonv65"}, {"65"}}, {{"hexagonv66"},  {"66"}},
 {{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
 {{"hexagonv68"}, {"68"}}, {{"hexagonv69"},  {"69"}},
-{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"},  {"71t"}},
-{{"hexagonv73"}, {"73"}},
+{{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
+{{"hexagonv73

[clang] [llvm] [Hexagon] Add V75 support to compiler and assembler (PR #120773)

2024-12-20 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar updated 
https://github.com/llvm/llvm-project/pull/120773

>From a57f928e545e4bd398fe0ae3fca8702c83a79516 Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Fri, 13 Dec 2024 14:54:44 -0800
Subject: [PATCH] [Hexagon] Add V75 support to compiler and assembler

This patch introduces support for the Hexagon V75 architecture.
It includes instruction formats, definitions, encodings, scheduling classes,
and builtins/intrinsics.
---
 clang/include/clang/Basic/BuiltinsHexagon.def |  10 +-
 clang/include/clang/Driver/Options.td |   2 +
 clang/lib/Basic/Targets/Hexagon.cpp   |  15 +-
 clang/test/Driver/hexagon-toolchain-elf.c |   7 +
 .../Misc/target-invalid-cpu-note/hexagon.c|   1 +
 clang/test/Preprocessor/hexagon-predefines.c  |  16 +
 llvm/include/llvm/BinaryFormat/ELF.h  |   1 +
 llvm/lib/Object/ELFObjectFile.cpp |   2 +
 llvm/lib/ObjectYAML/ELFYAML.cpp   |   2 +
 llvm/lib/Target/Hexagon/Hexagon.td|  14 +
 llvm/lib/Target/Hexagon/HexagonDepArch.h  |   4 +-
 llvm/lib/Target/Hexagon/HexagonDepArch.td |   2 +
 llvm/lib/Target/Hexagon/HexagonDepIICHVX.td   | 592 
 .../lib/Target/Hexagon/HexagonDepIICScalar.td | 888 ++
 llvm/lib/Target/Hexagon/HexagonSchedule.td|   1 +
 llvm/lib/Target/Hexagon/HexagonScheduleV75.td |  39 +
 llvm/lib/Target/Hexagon/HexagonSubtarget.h|   6 +
 .../MCTargetDesc/HexagonMCELFStreamer.cpp |   3 +
 .../MCTargetDesc/HexagonMCTargetDesc.cpp  |  68 +-
 llvm/test/MC/Hexagon/arch-support.s   |   9 +
 llvm/test/MC/Hexagon/v75_arch.s   |  10 +
 21 files changed, 1656 insertions(+), 36 deletions(-)
 create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV75.td
 create mode 100644 llvm/test/MC/Hexagon/v75_arch.s

diff --git a/clang/include/clang/Basic/BuiltinsHexagon.def 
b/clang/include/clang/Basic/BuiltinsHexagon.def
index 0dc0f4567dd413..ca3f99176110e3 100644
--- a/clang/include/clang/Basic/BuiltinsHexagon.def
+++ b/clang/include/clang/Basic/BuiltinsHexagon.def
@@ -17,8 +17,10 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+#pragma push_macro("V75")
+#define V75 "v75"
 #pragma push_macro("V73")
-#define V73 "v73"
+#define V73 "v73|" V75
 #pragma push_macro("V71")
 #define V71 "v71|" V73
 #pragma push_macro("V69")
@@ -40,8 +42,10 @@
 #pragma push_macro("V5")
 #define V5 "v5|" V55
 
+#pragma push_macro("HVXV75")
+#define HVXV75 "hvxv75"
 #pragma push_macro("HVXV73")
-#define HVXV73 "hvxv73"
+#define HVXV73 "hvxv73|" HVXV75
 #pragma push_macro("HVXV71")
 #define HVXV71 "hvxv71|" HVXV73
 #pragma push_macro("HVXV69")
@@ -143,6 +147,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("HVXV69")
 #pragma pop_macro("HVXV71")
 #pragma pop_macro("HVXV73")
+#pragma pop_macro("HVXV75")
 
 #pragma pop_macro("V5")
 #pragma pop_macro("V55")
@@ -155,6 +160,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("V69")
 #pragma pop_macro("V71")
 #pragma pop_macro("V73")
+#pragma pop_macro("V75")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 638f8c52053ec5..9edf308cc685ea 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6224,6 +6224,8 @@ def mv71t : Flag<["-"], "mv71t">, 
Group,
   Alias, AliasArgs<["hexagonv71t"]>;
 def mv73 : Flag<["-"], "mv73">, Group,
   Alias, AliasArgs<["hexagonv73"]>;
+def mv75 : Flag<["-"], "mv75">, Group,
+  Alias, AliasArgs<["hexagonv75"]>;
 def mhexagon_hvx : Flag<["-"], "mhvx">, Group,
   HelpText<"Enable Hexagon Vector eXtensions">;
 def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp 
b/clang/lib/Basic/Targets/Hexagon.cpp
index 0282ac812c306f..931327bd8657b0 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -78,6 +78,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   } else if (CPU == "hexagonv73") {
 Builder.defineMacro("__HEXAGON_V73__");
 Builder.defineMacro("__HEXAGON_ARCH__", "73");
+  } else if (CPU == "hexagonv75") {
+Builder.defineMacro("__HEXAGON_V75__");
+Builder.defineMacro("__HEXAGON_ARCH__", "75");
   }
 
   if (hasFeature("hvx-length64b")) {
@@ -229,13 +232,13 @@ struct CPUSuffix {
 };
 
 static constexpr CPUSuffix Suffixes[] = {
-{{"hexagonv5"},  {"5"}},  {{"hexagonv55"},  {"55"}},
-{{"hexagonv60"}, {"60"}}, {{"hexagonv62"},  {"62"}},
-{{"hexagonv65"}, {"65"}}, {{"hexagonv66"},  {"66"}},
+{{"hexagonv5"}, {"5"}},   {{"hexagonv55"}, {"55"}},
+{{"hexagonv60"}, {"60"}}, {{"hexagonv62"}, {"62"}},
+{{"hexagonv65"}, {"65"}}, {{"hexagonv66"}, {"66"}},
 {{"hexagonv67"}, {"67"}}, {{"hexagonv67t"}, {"67t"}},
-{{"hexagonv68"}, {"68"}}, {{"hexagonv69"},  {"69"}},
-{{"hexa

[clang] [llvm] [Hexagon] Add V75 support to compiler and assembler (PR #120773)

2024-12-20 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar closed 
https://github.com/llvm/llvm-project/pull/120773
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[clang] [StrTable] Mechanically convert Hexagon builtins to use TableGen (PR #123460)

2025-01-23 Thread Ikhlas Ajbar via cfe-commits 

iajbar wrote:

Thanks @chandlerc. I am testing this patch in our downstream repo.

https://github.com/llvm/llvm-project/pull/123460
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[clang] [StrTable] Mechanically convert Hexagon builtins to use TableGen (PR #123460)

2025-01-26 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar approved this pull request.

LGTM, thanks.

https://github.com/llvm/llvm-project/pull/123460
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[clang] [llvm] [Hexagon] Add missing builtins for V79 (PR #122916)

2025-01-14 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar created 
https://github.com/llvm/llvm-project/pull/122916

This patch adds new builtins that were added in V79 architecture.

>From b6e7e3fc8ea46c51f32c3c3bdb78c0c2160942de Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Fri, 10 Jan 2025 11:38:04 -0800
Subject: [PATCH] [Hexagon] Add missing builtins for V79

This patch adds new builtins that were added in V79 architecture.
---
 .../clang/Basic/BuiltinsHexagonDep.def|  45 +++
 .../lib/Target/Hexagon/HexagonDepInstrInfo.td | 277 ++
 .../Target/Hexagon/HexagonDepMapAsm2Intrin.td |  87 ++
 llvm/lib/Target/Hexagon/HexagonSubtarget.h|   3 +
 4 files changed, 412 insertions(+)

diff --git a/clang/include/clang/Basic/BuiltinsHexagonDep.def 
b/clang/include/clang/Basic/BuiltinsHexagonDep.def
index 6f1ae69037e3a3..616ff3ccf5b6b0 100644
--- a/clang/include/clang/Basic/BuiltinsHexagonDep.def
+++ b/clang/include/clang/Basic/BuiltinsHexagonDep.def
@@ -1923,3 +1923,48 @@ TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc, 
"V32iV32iV16iV16i", "", HVXV
 TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_sf_bf_acc_128B, "V64iV64iV32iV32i", 
"", HVXV73)
 TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf, "V32iV16iV16i", "", HVXV73)
 TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_sf_bf_128B, "V64iV32iV32i", "", 
HVXV73)
+
+// V79 HVX Instructions.
+
+TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext, "V16iV16ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_128B, "V32iV32ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_oracc, "V16iV16iV16ii", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_get_qfext_oracc_128B, "V32iV32iV32ii", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_set_qfext, "V16iV16ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_set_qfext_128B, "V32iV32ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_f8, "V16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vabs_f8_128B, "V32iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_f8, "V32iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vadd_hf_f8_128B, "V64iV32iV32i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_b_hf, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_b_hf_128B, "V32iV32iV32i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_b, "V32iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_b_128B, "V64iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_ub, "V32iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_hf_ub_128B, "V64iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_ub_hf, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt2_ub_hf_128B, "V32iV32iV32i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_f8_hf, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_f8_hf_128B, "V32iV32iV32i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_f8, "V32iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vcvt_hf_f8_128B, "V64iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_f8, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmax_f8_128B, "V32iV32iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_f8, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfmin_f8_128B, "V32iV32iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_f8, "V16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vfneg_f8_128B, "V32iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmerge_qf, "V16iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmerge_qf_128B, "V32iV32iV32i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8, "V32iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_128B, "V64iV32iV32i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_acc, "V32iV32iV16iV16i", "", 
HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_hf_f8_acc_128B, "V64iV64iV32iV32i", 
"", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_hf, "V16iV16ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_hf_128B, "V32iV32ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_qf16, "V16iV16ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_qf16_128B, "V32iV32ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_sf, "V16iV16ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vmpy_rt_sf_128B, "V32iV32ii", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_f8, "V32iV16iV16i", "", HVXV79)
+TARGET_BUILTIN(__builtin_HEXAGON_V6_vsub_hf_f8_128B, "V64iV32iV32i", "", 
HVXV79)
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td 
b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 7935c4b86af535..ae96753f40cf2c 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -26853,6 +26853,21 @@ let isPseudo = 1;
 let isCodeGenOnly = 1;
 let DecoderNamespace = "EXT_mmvec";

[clang] [llvm] [Hexagon] Add V79 support to compiler and assembler (PR #120983)

2024-12-23 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar created 
https://github.com/llvm/llvm-project/pull/120983

This patch introduces support for the Hexagon V79 architecture. It includes 
instruction formats, definitions, encodings, scheduling classes, and 
builtins/intrinsics. It also adds missing Hexagon v73 builtins to clang.

>From 847bc3c54f328fe9cbd013fb486eb5e853169d3f Mon Sep 17 00:00:00 2001
From: Ikhlas Ajbar 
Date: Fri, 20 Dec 2024 11:23:25 -0800
Subject: [PATCH] [Hexagon] Add V79 support to compiler and assembler

This patch introduces support for the Hexagon V79 architecture.
It includes instruction formats, definitions, encodings, scheduling classes,
and builtins/intrinsics. It also adds missing Hexagon v73 builtins to clang.
---
 clang/include/clang/Basic/BuiltinsHexagon.def |  10 +-
 clang/include/clang/Driver/Options.td |   2 +
 clang/lib/Basic/Targets/Hexagon.cpp   |   4 +
 clang/lib/Headers/hvx_hexagon_protos.h| 427 +
 clang/test/Driver/hexagon-toolchain-elf.c |   7 +
 .../Misc/target-invalid-cpu-note/hexagon.c|   1 +
 clang/test/Preprocessor/hexagon-predefines.c  |  17 +
 llvm/include/llvm/BinaryFormat/ELF.h  |   2 +
 llvm/include/llvm/IR/IntrinsicsHexagonDep.td  | 127 +++
 llvm/lib/Target/Hexagon/Hexagon.td|  13 +
 llvm/lib/Target/Hexagon/HexagonDepArch.h  |   4 +-
 llvm/lib/Target/Hexagon/HexagonDepArch.td |   2 +
 llvm/lib/Target/Hexagon/HexagonDepIICHVX.td   | 592 
 .../lib/Target/Hexagon/HexagonDepIICScalar.td | 888 ++
 llvm/lib/Target/Hexagon/HexagonSchedule.td|   1 +
 llvm/lib/Target/Hexagon/HexagonScheduleV75.td |   4 -
 llvm/lib/Target/Hexagon/HexagonScheduleV79.td |  31 +
 llvm/lib/Target/Hexagon/HexagonSubtarget.h|   6 +
 .../MCTargetDesc/HexagonMCELFStreamer.cpp |   3 +
 .../MCTargetDesc/HexagonMCTargetDesc.cpp  |  46 +-
 llvm/test/MC/Hexagon/arch-support.s   |   3 +
 llvm/test/MC/Hexagon/v79_arch.s   |  10 +
 22 files changed, 2179 insertions(+), 21 deletions(-)
 create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV79.td
 create mode 100644 llvm/test/MC/Hexagon/v79_arch.s

diff --git a/clang/include/clang/Basic/BuiltinsHexagon.def 
b/clang/include/clang/Basic/BuiltinsHexagon.def
index ca3f99176110e3..adff9f884c0494 100644
--- a/clang/include/clang/Basic/BuiltinsHexagon.def
+++ b/clang/include/clang/Basic/BuiltinsHexagon.def
@@ -17,8 +17,10 @@
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
+#pragma push_macro("V79")
+#define V79 "v79"
 #pragma push_macro("V75")
-#define V75 "v75"
+#define V75 "v75|" V79
 #pragma push_macro("V73")
 #define V73 "v73|" V75
 #pragma push_macro("V71")
@@ -42,8 +44,10 @@
 #pragma push_macro("V5")
 #define V5 "v5|" V55
 
+#pragma push_macro("HVXV79")
+#define HVXV79 "hvxv79"
 #pragma push_macro("HVXV75")
-#define HVXV75 "hvxv75"
+#define HVXV75 "hvxv75|" HVXV79
 #pragma push_macro("HVXV73")
 #define HVXV73 "hvxv73|" HVXV75
 #pragma push_macro("HVXV71")
@@ -148,6 +152,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("HVXV71")
 #pragma pop_macro("HVXV73")
 #pragma pop_macro("HVXV75")
+#pragma pop_macro("HVXV79")
 
 #pragma pop_macro("V5")
 #pragma pop_macro("V55")
@@ -161,6 +166,7 @@ 
TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "
 #pragma pop_macro("V71")
 #pragma pop_macro("V73")
 #pragma pop_macro("V75")
+#pragma pop_macro("V79")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 9e81c39f6869bd..d922709db17786 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -6226,6 +6226,8 @@ def mv73 : Flag<["-"], "mv73">, 
Group,
   Alias, AliasArgs<["hexagonv73"]>;
 def mv75 : Flag<["-"], "mv75">, Group,
   Alias, AliasArgs<["hexagonv75"]>;
+def mv79 : Flag<["-"], "mv79">, Group,
+  Alias, AliasArgs<["hexagonv79"]>;
 def mhexagon_hvx : Flag<["-"], "mhvx">, Group,
   HelpText<"Enable Hexagon Vector eXtensions">;
 def mhexagon_hvx_EQ : Joined<["-"], "mhvx=">,
diff --git a/clang/lib/Basic/Targets/Hexagon.cpp 
b/clang/lib/Basic/Targets/Hexagon.cpp
index 931327bd8657b0..b5e06b679ece72 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -81,6 +81,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions 
&Opts,
   } else if (CPU == "hexagonv75") {
 Builder.defineMacro("__HEXAGON_V75__");
 Builder.defineMacro("__HEXAGON_ARCH__", "75");
+  } else if (CPU == "hexagonv79") {
+Builder.defineMacro("__HEXAGON_V79__");
+Builder.defineMacro("__HEXAGON_ARCH__", "79");
   }
 
   if (hasFeature("hvx-length64b")) {
@@ -239,6 +242,7 @@ static constexpr CPUSuffix Suffixes[] = {
 {{"hexagonv68"}, {"68"}}, {{"hexagonv69"}, {"69"}},
 {{"hexagonv71"}, {"71"}}, {{"hexagonv71t"}, {"71t"}},
 {{"hexagonv73"}, {"73"}}, {{"hexagonv75"}, {"75

[clang] [llvm] [Hexagon] Add V79 support to compiler and assembler (PR #120983)

2024-12-23 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar closed 
https://github.com/llvm/llvm-project/pull/120983
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[clang] [llvm] [Hexagon] Add missing builtins for V79 (PR #122916)

2025-01-14 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar closed 
https://github.com/llvm/llvm-project/pull/122916
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[clang] [llvm] [Hexagon] Set the default compilation target to V68 (PR #125239)

2025-02-24 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar milestoned 
https://github.com/llvm/llvm-project/pull/125239
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[clang] [hexagon] Enable --eh-frame-hdr (PR #130225)

2025-03-11 Thread Ikhlas Ajbar via cfe-commits 

https://github.com/iajbar approved this pull request.


https://github.com/llvm/llvm-project/pull/130225
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