[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
https://github.com/HankChang736 created
https://github.com/llvm/llvm-project/pull/128636
This patch use the hook getClobbers() in RISCV target and mark {vl, type} as
clobber to prevent Post-RA scheduler moving vsetvl across inline assembly.
Fixing [#97794](https://github.com/llvm/llvm-project/pull/97794).
>From d7718e9ed9f03990895f0d89b87808d8c96bb67c Mon Sep 17 00:00:00 2001
From: Hank Chang
Date: Sun, 23 Feb 2025 23:59:23 +0800
Subject: [PATCH] [RISCV] Mark {vl, vtype} as clobber in inline assembly
This patch use the hook getClobbers() in RISCV target and mark {vl, type} as
clobber to prevent
Post-RA scheduler move vsetvl across inline assembly.
---
clang/lib/Basic/Targets/RISCV.h | 2 +-
.../CodeGen/RISCV/riscv-inline-asm-clobber.c | 48 ++-
.../test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 8 ++--
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 42
.../rvv/vsetvl-cross-inline-asm-clobber.ll| 37 ++
.../RISCV/rvv/vsetvl-cross-inline-asm.ll | 37 ++
6 files changed, 136 insertions(+), 38 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm-clobber.ll
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index c26aa19080162..5590aa9d03c75 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -68,7 +68,7 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override { return "~{vl},~{vtype}"; }
StringRef getConstraintRegister(StringRef Constraint,
StringRef Expression) const override {
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
index 8aa80386f205f..65cfc081fe26d 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
@@ -7,38 +7,62 @@
// Test RISC-V specific clobbered registers in inline assembly.
-// CHECK-LABEL: define {{.*}} void @test_fflags
-// CHECK:tail call void asm sideeffect "", "~{fflags}"()
+// CHECK-LABEL: define dso_local void @test_fflags(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{fflags},~{vl},~{vtype}"() #[[ATTR1:[0-9]+]], !srcloc [[META6:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_fflags(void) {
asm volatile ("" :::"fflags");
}
-// CHECK-LABEL: define {{.*}} void @test_frm
-// CHECK:tail call void asm sideeffect "", "~{frm}"()
+// CHECK-LABEL: define dso_local void @test_frm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{frm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META7:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_frm(void) {
asm volatile ("" :::"frm");
}
-// CHECK-LABEL: define {{.*}} void @test_vtype
-// CHECK:tail call void asm sideeffect "", "~{vtype}"()
+// CHECK-LABEL: define dso_local void @test_vtype(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vtype},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META8:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vtype(void) {
asm volatile ("" :::"vtype");
}
-// CHECK-LABEL: define {{.*}} void @test_vl
-// CHECK:tail call void asm sideeffect "", "~{vl}"()
+// CHECK-LABEL: define dso_local void @test_vl(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vl},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META9:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vl(void) {
asm volatile ("" :::"vl");
}
-// CHECK-LABEL: define {{.*}} void @test_vxsat
-// CHECK:tail call void asm sideeffect "", "~{vxsat}"()
+// CHECK-LABEL: define dso_local void @test_vxsat(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vxsat},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META10:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxsat(void) {
asm volatile ("" :::"vxsat");
}
-// CHECK-LABEL: define {{.*}} void @test_vxrm
-// CHECK:tail call void asm sideeffect "", "~{vxrm}"()
+// CHECK-LABEL: define dso_local void @test_vxrm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vxrm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META11:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxrm(void) {
asm volatile ("" :::"vxrm");
}
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
b/clang/test/CodeGen/RISCV/riscv
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
HankChang736 wrote: > I think this may not be the right way. > > 1. We should at least add vl/vtype to clobbered registers when V is > specified. > > 2. The asm may not depend on vl/type, but adding vl/type dependencies > unconditionally stop further scheduling. Yes, you're right. But the purpose we add vl/vtype dependencies is to prevent the Post-RA scheduler moving vsetvl instruction across inline assembly. I'm not sure if there's better approach to solve this problem. https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
https://github.com/HankChang736 updated
https://github.com/llvm/llvm-project/pull/128636
>From d7718e9ed9f03990895f0d89b87808d8c96bb67c Mon Sep 17 00:00:00 2001
From: Hank Chang
Date: Sun, 23 Feb 2025 23:59:23 +0800
Subject: [PATCH 1/2] [RISCV] Mark {vl, vtype} as clobber in inline assembly
This patch use the hook getClobbers() in RISCV target and mark {vl, type} as
clobber to prevent
Post-RA scheduler move vsetvl across inline assembly.
---
clang/lib/Basic/Targets/RISCV.h | 2 +-
.../CodeGen/RISCV/riscv-inline-asm-clobber.c | 48 ++-
.../test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 8 ++--
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 42
.../rvv/vsetvl-cross-inline-asm-clobber.ll| 37 ++
.../RISCV/rvv/vsetvl-cross-inline-asm.ll | 37 ++
6 files changed, 136 insertions(+), 38 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm-clobber.ll
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index c26aa19080162..5590aa9d03c75 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -68,7 +68,7 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override { return "~{vl},~{vtype}"; }
StringRef getConstraintRegister(StringRef Constraint,
StringRef Expression) const override {
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
index 8aa80386f205f..65cfc081fe26d 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
@@ -7,38 +7,62 @@
// Test RISC-V specific clobbered registers in inline assembly.
-// CHECK-LABEL: define {{.*}} void @test_fflags
-// CHECK:tail call void asm sideeffect "", "~{fflags}"()
+// CHECK-LABEL: define dso_local void @test_fflags(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{fflags},~{vl},~{vtype}"() #[[ATTR1:[0-9]+]], !srcloc [[META6:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_fflags(void) {
asm volatile ("" :::"fflags");
}
-// CHECK-LABEL: define {{.*}} void @test_frm
-// CHECK:tail call void asm sideeffect "", "~{frm}"()
+// CHECK-LABEL: define dso_local void @test_frm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{frm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META7:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_frm(void) {
asm volatile ("" :::"frm");
}
-// CHECK-LABEL: define {{.*}} void @test_vtype
-// CHECK:tail call void asm sideeffect "", "~{vtype}"()
+// CHECK-LABEL: define dso_local void @test_vtype(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vtype},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META8:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vtype(void) {
asm volatile ("" :::"vtype");
}
-// CHECK-LABEL: define {{.*}} void @test_vl
-// CHECK:tail call void asm sideeffect "", "~{vl}"()
+// CHECK-LABEL: define dso_local void @test_vl(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vl},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META9:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vl(void) {
asm volatile ("" :::"vl");
}
-// CHECK-LABEL: define {{.*}} void @test_vxsat
-// CHECK:tail call void asm sideeffect "", "~{vxsat}"()
+// CHECK-LABEL: define dso_local void @test_vxsat(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vxsat},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META10:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxsat(void) {
asm volatile ("" :::"vxsat");
}
-// CHECK-LABEL: define {{.*}} void @test_vxrm
-// CHECK:tail call void asm sideeffect "", "~{vxrm}"()
+// CHECK-LABEL: define dso_local void @test_vxrm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vxrm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META11:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxrm(void) {
asm volatile ("" :::"vxrm");
}
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
index 879fb1238d83a..e9444c6a76d87 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
@@ -18,12 +18,12 @@ void test_v_reg() {
:
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
@@ -68,7 +68,7 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override { return "~{vl},~{vtype}"; }
HankChang736 wrote:
I think this implementation is better, just update it with your implementation.
https://github.com/llvm/llvm-project/pull/128636
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[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
@@ -68,7 +68,11 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override {
+if (ISAInfo->hasExtension("zve32x"))
HankChang736 wrote:
I just reverted this implementation.
https://github.com/llvm/llvm-project/pull/128636
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[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
https://github.com/HankChang736 edited https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
HankChang736 wrote:
I tested the following case without passing the 'v' extension in the Clang
command line argument:
```c
__attribute__((target("arch=rv32gcv_zve32x")))
void test_A(int *p) {
asm volatile("" :: "A"(*p));
}
```
The generated LLVM IR result is:
```
; Function Attrs: nounwind
define dso_local void @test_A(ptr noundef %p) local_unnamed_addr #0 {
entry:
tail call void asm sideeffect "", "*A"(ptr elementtype(i32) %p) #1, !srcloc !6
ret void
}
attributes #0 = { nounwind "no-trapping-math"="true"
"stack-protector-buffer-size"="8" "target-cpu"="generic-rv32"
"target-features"="+32bit,+a,+c,+d,+f,+m,+relax,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b
...
```
>From this result, it appears that the target attribute does not have the
>intended effect in this case. Given this, perhaps we should keep the initial
>implementation temporary and try the RISCVInsertVSETVLI approach for future
>improvements.
cc @wangpc-pp @topperc
https://github.com/llvm/llvm-project/pull/128636
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[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
https://github.com/HankChang736 updated
https://github.com/llvm/llvm-project/pull/128636
>From d7718e9ed9f03990895f0d89b87808d8c96bb67c Mon Sep 17 00:00:00 2001
From: Hank Chang
Date: Sun, 23 Feb 2025 23:59:23 +0800
Subject: [PATCH 1/3] [RISCV] Mark {vl, vtype} as clobber in inline assembly
This patch use the hook getClobbers() in RISCV target and mark {vl, type} as
clobber to prevent
Post-RA scheduler move vsetvl across inline assembly.
---
clang/lib/Basic/Targets/RISCV.h | 2 +-
.../CodeGen/RISCV/riscv-inline-asm-clobber.c | 48 ++-
.../test/CodeGen/RISCV/riscv-inline-asm-rvv.c | 8 ++--
clang/test/CodeGen/RISCV/riscv-inline-asm.c | 42
.../rvv/vsetvl-cross-inline-asm-clobber.ll| 37 ++
.../RISCV/rvv/vsetvl-cross-inline-asm.ll | 37 ++
6 files changed, 136 insertions(+), 38 deletions(-)
create mode 100644
llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm-clobber.ll
create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index c26aa19080162..5590aa9d03c75 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -68,7 +68,7 @@ class RISCVTargetInfo : public TargetInfo {
return TargetInfo::VoidPtrBuiltinVaList;
}
- std::string_view getClobbers() const override { return ""; }
+ std::string_view getClobbers() const override { return "~{vl},~{vtype}"; }
StringRef getConstraintRegister(StringRef Constraint,
StringRef Expression) const override {
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
index 8aa80386f205f..65cfc081fe26d 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c
@@ -7,38 +7,62 @@
// Test RISC-V specific clobbered registers in inline assembly.
-// CHECK-LABEL: define {{.*}} void @test_fflags
-// CHECK:tail call void asm sideeffect "", "~{fflags}"()
+// CHECK-LABEL: define dso_local void @test_fflags(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{fflags},~{vl},~{vtype}"() #[[ATTR1:[0-9]+]], !srcloc [[META6:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_fflags(void) {
asm volatile ("" :::"fflags");
}
-// CHECK-LABEL: define {{.*}} void @test_frm
-// CHECK:tail call void asm sideeffect "", "~{frm}"()
+// CHECK-LABEL: define dso_local void @test_frm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{frm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META7:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_frm(void) {
asm volatile ("" :::"frm");
}
-// CHECK-LABEL: define {{.*}} void @test_vtype
-// CHECK:tail call void asm sideeffect "", "~{vtype}"()
+// CHECK-LABEL: define dso_local void @test_vtype(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vtype},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META8:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vtype(void) {
asm volatile ("" :::"vtype");
}
-// CHECK-LABEL: define {{.*}} void @test_vl
-// CHECK:tail call void asm sideeffect "", "~{vl}"()
+// CHECK-LABEL: define dso_local void @test_vl(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vl},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META9:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vl(void) {
asm volatile ("" :::"vl");
}
-// CHECK-LABEL: define {{.*}} void @test_vxsat
-// CHECK:tail call void asm sideeffect "", "~{vxsat}"()
+// CHECK-LABEL: define dso_local void @test_vxsat(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "",
"~{vxsat},~{vl},~{vtype}"() #[[ATTR1]], !srcloc [[META10:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxsat(void) {
asm volatile ("" :::"vxsat");
}
-// CHECK-LABEL: define {{.*}} void @test_vxrm
-// CHECK:tail call void asm sideeffect "", "~{vxrm}"()
+// CHECK-LABEL: define dso_local void @test_vxrm(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:tail call void asm sideeffect "", "~{vxrm},~{vl},~{vtype}"()
#[[ATTR1]], !srcloc [[META11:![0-9]+]]
+// CHECK-NEXT:ret void
+//
void test_vxrm(void) {
asm volatile ("" :::"vxrm");
}
diff --git a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
index 879fb1238d83a..e9444c6a76d87 100644
--- a/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
+++ b/clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
@@ -18,12 +18,12 @@ void test_v_reg() {
:
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
HankChang736 wrote: I create another pull request [#130733](https://github.com/llvm/llvm-project/pull/130733) that is implemented with the RISCVInsertVSETVL approach, since it's a new approach. https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
HankChang736 wrote: [#130733](https://github.com/llvm/llvm-project/pull/130733) is merged. This pr will be marked as closed. https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
HankChang736 wrote:
I tried the test case below without passing 'v' extension in Clang command line
argument.
`__attribute__((target("zve32x")))
void test_A(int *p) {
asm volatile("" :: "A"(*p));
}
`
The generated LLVM IR result is :
`; Function Attrs: nounwind
define dso_local void @test_A(ptr noundef %p) local_unnamed_addr #0 {
entry:
tail call void asm sideeffect "", "*A"(ptr elementtype(i32) %p) #1, !srcloc !6
ret void
}
`
https://github.com/llvm/llvm-project/pull/128636
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[clang] [llvm] [RISCV] Mark {vl, vtype} as clobber in inline assembly (PR #128636)
https://github.com/HankChang736 closed https://github.com/llvm/llvm-project/pull/128636 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
