r332193 - Added atomic_fetch_min, max, umin, umax intrinsics to clang.
Author: delena
Date: Sun May 13 00:45:58 2018
New Revision: 332193
URL: http://llvm.org/viewvc/llvm-project?rev=332193&view=rev
Log:
Added atomic_fetch_min, max, umin, umax intrinsics to clang.
These intrinsics work exactly as all other atomic_fetch_* intrinsics and allow
to create *atomicrmw* with ordering.
Updated the clang-extensions document.
Differential Revision: https://reviews.llvm.org/D46386
Modified:
cfe/trunk/docs/LanguageExtensions.rst
cfe/trunk/include/clang/Basic/Builtins.def
cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
cfe/trunk/lib/AST/Expr.cpp
cfe/trunk/lib/CodeGen/CGAtomic.cpp
cfe/trunk/lib/Sema/SemaChecking.cpp
cfe/trunk/test/CodeGen/Atomics.c
cfe/trunk/test/Sema/atomic-ops.c
Modified: cfe/trunk/docs/LanguageExtensions.rst
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/docs/LanguageExtensions.rst?rev=332193&r1=332192&r2=332193&view=diff
==
--- cfe/trunk/docs/LanguageExtensions.rst (original)
+++ cfe/trunk/docs/LanguageExtensions.rst Sun May 13 00:45:58 2018
@@ -1975,6 +1975,32 @@ is disallowed in general).
Support for constant expression evaluation for the above builtins be detected
with ``__has_feature(cxx_constexpr_string_builtins)``.
+Atomic Min/Max builtins with memory ordering
+
+
+There are two atomic builtins with min/max in-memory comparison and swap.
+The syntax and semantics are similar to GCC-compatible __atomic_* builtins.
+
+* ``__atomic_fetch_min``
+* ``__atomic_fetch_max``
+
+The builtins work with signed and unsigned integers and require to specify
memory ordering.
+The return value is the original value that was stored in memory before
comparison.
+
+Example:
+
+.. code-block:: c
+
+ unsigned int val = __atomic_fetch_min(unsigned int *pi, unsigned int ui,
__ATOMIC_RELAXED);
+
+The third argument is one of the memory ordering specifiers
``__ATOMIC_RELAXED``,
+``__ATOMIC_CONSUME``, ``__ATOMIC_ACQUIRE``, ``__ATOMIC_RELEASE``,
+``__ATOMIC_ACQ_REL``, or ``__ATOMIC_SEQ_CST`` following C++11 memory model
semantics.
+
+In terms or aquire-release ordering barriers these two operations are always
+considered as operations with *load-store* semantics, even when the original
value
+is not actually modified after comparison.
+
.. _langext-__c11_atomic:
__c11_atomic builtins
@@ -2734,4 +2760,3 @@ Specifying Linker Options on ELF Targets
The ``#pragma comment(lib, ...)`` directive is supported on all ELF targets.
The second parameter is the library name (without the traditional Unix prefix
of
``lib``). This allows you to provide an implicit link of dependent libraries.
-
Modified: cfe/trunk/include/clang/Basic/Builtins.def
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/Builtins.def?rev=332193&r1=332192&r2=332193&view=diff
==
--- cfe/trunk/include/clang/Basic/Builtins.def (original)
+++ cfe/trunk/include/clang/Basic/Builtins.def Sun May 13 00:45:58 2018
@@ -721,6 +721,10 @@ ATOMIC_BUILTIN(__opencl_atomic_fetch_xor
ATOMIC_BUILTIN(__opencl_atomic_fetch_min, "v.", "t")
ATOMIC_BUILTIN(__opencl_atomic_fetch_max, "v.", "t")
+// GCC does not support these, they are a Clang extension.
+ATOMIC_BUILTIN(__atomic_fetch_min, "iiD*i.", "t")
+ATOMIC_BUILTIN(__atomic_fetch_max, "v.", "t")
+
#undef ATOMIC_BUILTIN
// Non-overloaded atomic builtins.
Modified: cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td?rev=332193&r1=332192&r2=332193&view=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td Sun May 13 00:45:58
2018
@@ -7127,6 +7127,8 @@ def err_atomic_op_needs_trivial_copy : E
def err_atomic_op_needs_atomic_int_or_ptr : Error<
"address argument to atomic operation must be a pointer to %select{|atomic
}0"
"integer or pointer (%1 invalid)">;
+def err_atomic_op_needs_int32_or_ptr : Error<
+ "address argument to atomic operation must be a pointer to signed or
unsigned 32-bit integer">;
def err_atomic_op_bitwise_needs_atomic_int : Error<
"address argument to bitwise atomic operation must be a pointer to "
"%select{|atomic }0integer (%1 invalid)">;
Modified: cfe/trunk/lib/AST/Expr.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/AST/Expr.cpp?rev=332193&r1=332192&r2=332193&view=diff
==
--- cfe/trunk/lib/AST/Expr.cpp (original)
+++ cfe/trunk/lib/AST/Expr.cpp Sun May 13 00:45:58 2018
@@ -4052,6 +4052,8 @@ unsigned AtomicExpr::getNumSubExprs(Atom
case AO__atomic_or_fetch:
case AO__atomic_xor_fetch:
case AO__atomic_nand_fetch:
+ case AO__atomic_fetc
Re: [PATCH] D25004: [x86][inline-asm][clang] accept 'v' constraint
delena added inline comments. Comment at: test/CodeGen/x86-inline-asm-v-constraint.c:2 @@ +1,3 @@ +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu x86-64 -o - | FileCheck %s --check-prefix SSE +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu skylake -D AVX -o - | FileCheck %s --check-prefixes AVX,SSE +// RUN: %clang_cc1 %s -triple x86_64-unknown-linux-gnu -emit-llvm -target-cpu skylake-avx512 -D AVX512 -D AVX -o - | FileCheck %s --check-prefixes AVX512,AVX,SSE add KNL tests here. Repository: rL LLVM https://reviews.llvm.org/D25004 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21505: [Clang][AVX512][Intrinsics]Adding intrinsics for mov{ss|sd} instruction set
delena added inline comments.
Comment at: lib/Headers/avx512fintrin.h:9337
@@ +9336,3 @@
+{
+ return (__m128) _mm_move_ss( __A, __builtin_ia32_selectps_128 ((__mmask8)
__U,
+ (__v4sf) __B,
selectps should not be used here. It complicates IR.
You can write the following:
res = __A;
res[0] = (__U&1)? __B[0]:__W[0];
Comment at: test/CodeGen/avx512f-builtins.c:393
@@ +392,3 @@
+ // CHECK: select <4 x i1> {{.*}}, <4 x float> {{.*}}, <4 x float> {{.*}}
+ // CHECK: load <4 x float>, <4 x float>* {{.*}}
+ return _mm_mask_load_ss ( __W, __U, __A);
you should not see any "load" here.
https://reviews.llvm.org/D21505
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[PATCH] D25902: [AVX-512] Fix the operand order for all calls to __builtin_ia32_vfmaddss3_mask.
delena added inline comments.
Comment at: lib/Headers/avx512fintrin.h:8394
_MM_FROUND_CUR_DIRECTION);
}
Using vfmaddss3_mask is wrong in this case.
It will propagate -B to lower bits if mask==0.
Comment at: lib/Headers/avx512fintrin.h:8453
{
return (__m128) __builtin_ia32_vfmaddss3_maskz (-(__v4sf) __A,
(__v4sf) __B,
This one is, probably, also wrong, because we should copy the upper bits of __A
as is.
IF k[0]
dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0]
ELSE
dst[31:0] := c[31:0]
FI
dst[127:32] := a[127:32]
dst[MAX:128] := 0
https://reviews.llvm.org/D25902
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[PATCH] D25902: [AVX-512] Fix the operand order for all calls to __builtin_ia32_vfmaddss3_mask.
delena accepted this revision. delena added a comment. This revision is now accepted and ready to land. LGTM. Agree, one-by-one. https://reviews.llvm.org/D25902 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13014: [X86] Add XSAVE intrinsics (Clang part)
delena added a comment. Do you need to add some tests for clang? Repository: rL LLVM http://reviews.llvm.org/D13014 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13014: [X86] Add XSAVE intrinsics (Clang part)
delena added a comment. You should add the "xsave" features to all appropriate CPUs. It can be done in a separate patch. LGTM. Repository: rL LLVM http://reviews.llvm.org/D13014 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D13861: [x86] fix wrong maskload/store intrinsic definitions in avxintrin.h (follow up of D13776).
delena added a comment. LGTM http://reviews.llvm.org/D13861 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21959: [X86] Add xgetbv xsetbv intrinsics
delena added a comment.
#include in the test is not clear for me. Does it mean that you
broke backward compatibility?
Comment at: lib/CodeGen/CGBuiltin.cpp:6779
@@ -6776,1 +6778,3 @@
}
+ case X86::BI__builtin_ia32_xgetbv: {
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_xgetbv), Ops);
remove {}
Comment at: lib/Headers/intrin.h:905
@@ -906,9 +904,3 @@
}
-static __inline__ unsigned __int64 __cdecl __DEFAULT_FN_ATTRS
-_xgetbv(unsigned int __xcr_no) {
- unsigned int __eax, __edx;
- __asm__ ("xgetbv" : "=a" (__eax), "=d" (__edx) : "c" (__xcr_no));
- return ((unsigned __int64)__edx << 32) | __eax;
-}
static __inline__ void __DEFAULT_FN_ATTRS
__halt(void) {
I'm not sure that we can move it from one file to another. And what was wrong
with current implementation.
https://reviews.llvm.org/D21959
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Re: [PATCH] D22212: [X86][AVX512] Constants for integer comparison predicates
delena accepted this revision.
This revision is now accepted and ready to land.
Comment at: ../tunkClang/tools/clang/test/CodeGen/avx512vl-builtins.c:504
@@ -503,3 +503,3 @@
__mmask8 test_mm_cmp_epi32_mask(__m128i __a, __m128i __b) {
// CHECK-LABEL: @test_mm_cmp_epi32_mask
Please change test name for each case.
Repository:
rL LLVM
https://reviews.llvm.org/D22212
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r261467 - Added SKL and CNL processors and features to Clang
Author: delena
Date: Sun Feb 21 01:41:23 2016
New Revision: 261467
URL: http://llvm.org/viewvc/llvm-project?rev=261467&view=rev
Log:
Added SKL and CNL processors and features to Clang
Differential Revision: http://reviews.llvm.org/D16756
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=261467&r1=261466&r2=261467&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Sun Feb 21 01:41:23 2016
@@ -2117,7 +2117,11 @@ class X86TargetInfo : public TargetInfo
bool HasAVX512DQ = false;
bool HasAVX512BW = false;
bool HasAVX512VL = false;
+ bool HasAVX512VBMI = false;
+ bool HasAVX512IFMA = false;
bool HasSHA = false;
+ bool HasMPX = false;
+ bool HasSGX = false;
bool HasCX16 = false;
bool HasFXSR = false;
bool HasXSAVE = false;
@@ -2125,6 +2129,12 @@ class X86TargetInfo : public TargetInfo
bool HasXSAVEC = false;
bool HasXSAVES = false;
bool HasPKU = false;
+ bool HasCLFLUSHOPT = false;
+ bool HasPCOMMIT = false;
+ bool HasCLWB = false;
+ bool HasUMIP = false;
+ bool HasMOVBE = false;
+ bool HasPREFETCHWT1 = false;
/// \brief Enumeration of all of the X86 CPUs supported by Clang.
///
@@ -2225,9 +2235,17 @@ class X86TargetInfo : public TargetInfo
/// Broadwell microarchitecture based processors.
CK_Broadwell,
-/// \name Skylake
-/// Skylake microarchitecture based processors.
-CK_Skylake,
+/// \name Skylake Client
+/// Skylake client microarchitecture based processors.
+CK_SkylakeClient,
+
+/// \name Skylake Server
+/// Skylake server microarchitecture based processors.
+CK_SkylakeServer,
+
+/// \name Cannonlake Client
+/// Cannonlake client microarchitecture based processors.
+CK_Cannonlake,
/// \name Knights Landing
/// Knights Landing processor.
@@ -2332,8 +2350,10 @@ class X86TargetInfo : public TargetInfo
.Case("haswell", CK_Haswell)
.Case("core-avx2", CK_Haswell) // Legacy name.
.Case("broadwell", CK_Broadwell)
-.Case("skylake", CK_Skylake)
-.Case("skx", CK_Skylake) // Legacy name.
+.Case("skylake", CK_SkylakeClient)
+.Case("skylake-avx512", CK_SkylakeServer)
+.Case("skx", CK_SkylakeServer) // Legacy name.
+.Case("cannonlake", CK_Cannonlake)
.Case("knl", CK_KNL)
.Case("k6", CK_K6)
.Case("k6-2", CK_K6_2)
@@ -2508,7 +2528,9 @@ public:
case CK_IvyBridge:
case CK_Haswell:
case CK_Broadwell:
-case CK_Skylake:
+case CK_SkylakeClient:
+case CK_SkylakeServer:
+case CK_Cannonlake:
case CK_KNL:
case CK_Athlon64:
case CK_Athlon64SSE3:
@@ -2618,15 +2640,28 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "fxsr", true);
setFeatureEnabledImpl(Features, "cx16", true);
break;
- case CK_Skylake:
+ case CK_Cannonlake:
+setFeatureEnabledImpl(Features, "avx512ifma", true);
+setFeatureEnabledImpl(Features, "avx512vbmi", true);
+setFeatureEnabledImpl(Features, "sha", true);
+setFeatureEnabledImpl(Features, "umip", true);
+// FALLTHROUGH
+ case CK_SkylakeServer:
setFeatureEnabledImpl(Features, "avx512f", true);
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512dq", true);
setFeatureEnabledImpl(Features, "avx512bw", true);
setFeatureEnabledImpl(Features, "avx512vl", true);
+setFeatureEnabledImpl(Features, "pku", true);
+setFeatureEnabledImpl(Features, "pcommit", true);
+setFeatureEnabledImpl(Features, "clwb", true);
+// FALLTHROUGH
+ case CK_SkylakeClient:
setFeatureEnabledImpl(Features, "xsavec", true);
setFeatureEnabledImpl(Features, "xsaves", true);
-setFeatureEnabledImpl(Features, "pku", true);
+setFeatureEnabledImpl(Features, "mpx", true);
+setFeatureEnabledImpl(Features, "sgx", true);
+setFeatureEnabledImpl(Features, "clflushopt", true);
// FALLTHROUGH
case CK_Broadwell:
setFeatureEnabledImpl(Features, "rdseed", true);
@@ -2639,6 +2674,7 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
setFeatureEnabledImpl(Features, "fma", true);
+setFeatureEnabledImpl(Features, "movbe", true);
// FALLTHROUGH
case CK_IvyBridge:
setFeatureEnabledImpl(Features, "rdrnd", true);
@@ -2665,6 +2701,7 @@ bool X86TargetInfo::initFeatureMap(
setFeatureEnabledImpl(Features, "avx512cd", true);
setFeatureEnabledImpl(Features, "avx512er", true);
setFeatureEnabledImpl(Features, "avx512pf", true);
+setFeatureEnabledImpl(Features, "prefetchwt1", true);
setFeatureEnabledImpl(Features, "fxsr", t
Re: [PATCH] D17092: [X86] Add -mseparate-stack-seg
delena added a subscriber: delena.
Comment at: lib/CodeGen/TargetInfo.cpp:1569
@@ +1568,3 @@
+CGF.getTarget().getTargetOpts().Features;
+ if (std::find(TargetFeatures.begin(), TargetFeatures.end(),
+"+separate-stack-seg") != TargetFeatures.end()) {
Hi,
I'm not clang reviewer at all and you can ignore my comment.
Searching string looks strange for me. I suppose that this string should be
defined in another form. Something like
options::OPT_separate_stack_seg.
Comment at: lib/CodeGen/TargetInfo.cpp:1577
@@ +1576,3 @@
+ CGF.Builder.CreatePtrToInt(Addr.getPointer(), CGF.IntPtrTy);
+llvm::Value *PtrInStackSeg = CGF.Builder.CreateIntToPtr(PtrAsInt,
+
DirectTy->getPointerTo(258));
You should not use 258 as a constant. It should be defined somewhere as address
space enum.
Comment at: lib/CodeGen/TargetInfo.cpp:1578
@@ +1577,3 @@
+llvm::Value *PtrInStackSeg = CGF.Builder.CreateIntToPtr(PtrAsInt,
+
DirectTy->getPointerTo(258));
+return Address(PtrInStackSeg, Addr.getAlignment());
This line alignment does not match LLVM style.
Comment at: lib/CodeGen/TargetInfo.cpp:1580
@@ +1579,3 @@
+return Address(PtrInStackSeg, Addr.getAlignment());
+ }
+
Again, not sure that I'm right. You are trying to create addressspacecast. Is
it the right way to create ptrtoint + inttoptr?
http://reviews.llvm.org/D17092
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Re: [PATCH] D20626: [Clang][AVX512][intrinsics] Adding missing intrinsics div_pd and div_ps
delena added inline comments. Comment at: test/CodeGen/avx512f-builtins.c:1927 @@ +1926,3 @@ + // check-label: @test_mm512_div_pd + // check: @llvm.x86.avx512.mask.div.pd.512 + return _mm512_div_pd(__a,__b); I don't understand how do you receive intrinsic if you issue IR. http://reviews.llvm.org/D20626 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20782: [AVX512] Emit generic masked store intrinsics directly from clang instead of using x86 specific intrinsics.
delena added inline comments.
Comment at: lib/CodeGen/CGBuiltin.cpp:6304
@@ +6303,3 @@
+ Indices[i] = i;
+Ops[2] = CGF.Builder.CreateShuffleVector(Ops[2], Ops[2],
+ makeArrayRef(Indices, NumElts),
What code do you receive at the end? There is no shuffle instruction in the
architecture for mask vector.
Comment at: test/CodeGen/avx512f-builtins.c:123
@@ -122,2 +122,3 @@
// CHECK-LABEL: @test_mm512_storeu_si512
- // CHECK: @llvm.x86.avx512.mask.storeu.d.512
+ // CHECK: store <16 x i32> %5, <16 x i32>* %6, align 1
+ // CHECK-NEXT: ret void
I suggest to remove %5, %6 from the test, you can put something like this:
CHECK: store <16 x i32> {{.*}}, align 1
http://reviews.llvm.org/D20782
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Re: [PATCH] D20782: [AVX512] Emit generic masked store intrinsics directly from clang instead of using x86 specific intrinsics.
delena added inline comments. Comment at: lib/CodeGen/CGBuiltin.cpp:6304 @@ +6303,3 @@ + Indices[i] = i; +Ops[2] = CGF.Builder.CreateShuffleVector(Ops[2], Ops[2], + makeArrayRef(Indices, NumElts), craig.topper wrote: > delena wrote: > > What code do you receive at the end? There is no shuffle instruction in the > > architecture for mask vector. > That's not really a shuffle. It's an extract subvector, but the IR doesn't > have a real instruction for that. > > It's needed so we can go from i8 -> v8i1 -> v2i1/v4i1. I understand. I just wanted to be sure that you receive only one "kmov %edi, %k1" at the end. http://reviews.llvm.org/D20782 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20782: [AVX512] Emit generic masked store intrinsics directly from clang instead of using x86 specific intrinsics.
delena accepted this revision. delena added a comment. This revision is now accepted and ready to land. LGTM, After tests cleanup http://reviews.llvm.org/D20782 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D20871: [Clang][AVX512][Intrinsics] Adding two definitions _mm512_setzero and _mm512_setzero_epi32
delena added a comment. Why do you need them. Is it a part of API? http://reviews.llvm.org/D20871 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: [PATCH] D21021: [Clang][AVX512][BuiltIn]Adding intrinsics move_{sd|ss} to clang
delena added inline comments.
Comment at: lib/Headers/avx512fintrin.h:9124
@@ +9123,3 @@
+{
+ return (__m128) __builtin_ia32_movss_mask ((__v4sf) __A, (__v4sf) __B,
+ (__v4sf) __W,
please try the following:
if (__U)
return __builtin_shuffle(A, B, (0, 5, 6, 7)); // may be you need to swap A
and B
return W;
I know that the immediate code will be less optimal, but we can optimize it
later.
http://reviews.llvm.org/D21021
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Re: [PATCH] D21505: [Clang][AVX512][Intrinsics]Adding intrinsics for mov{ss|sd} instruction set
delena added inline comments.
Comment at: lib/Headers/avx512fintrin.h:4518
@@ -4493,1 +4517,3 @@
+static __inline__ __m128 __DEFAULT_FN_ATTRS
+_mm_mask_store_ss (float * __W, __mmask8 __U, __m128 __A)
this intrinsic should be void.
Comment at: test/CodeGen/avx512f-builtins.c:248
@@ +247,3 @@
+ // CHECK: store float {{.*}}, float* {{.*}}
+ // CHECK: load <4 x float>, <4 x float>* {{.*}}
+ return _mm_mask_store_ss (__W, __U, __A);
Why do you see load here?
http://reviews.llvm.org/D21505
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Re: [PATCH] D21973: [AVX512] add float/double abs intrinsics
delena accepted this revision.
This revision is now accepted and ready to land.
Comment at: ../tunkClang/tools/clang/test/CodeGen/avx512f-builtins.c:1413-1414
@@ -1412,3 +1412,4 @@
// CHECK-LABEL: @test_mm512_mask_and_epi32
- // CHECK: @llvm.x86.avx512.mask.pand.d.512
+ // CHECK: and <16 x i32>
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
return _mm512_mask_and_epi32(__src, __k,__a, __b);
The right thing to do here:
// CHECK: %[[MASK:.*]] = bitcast
// CHECK: %[[AND_RES:.*]] = and <16 x i32>
// CHECK: select <16 x i1> %[[MASK]], <16 x i32>%[[AND_RES]]
Up to you.
Repository:
rL LLVM
http://reviews.llvm.org/D21973
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