r314300 - [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Sep 27 05:36:54 2017
New Revision: 314300

URL: http://llvm.org/viewvc/llvm-project?rev=314300&view=rev
Log:
[X86][MS-InlineAsm] Extended support for variables / identifiers on memory / 
immediate expressions

Allow the proper recognition of Enum values and global variables inside ms 
inline-asm memory / immediate expressions, as they require some additional 
overhead and treated incorrect if doesn't early recognized.
supersedes D33277, D35775
Corrsponds with D37412, D37413

Added:
cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp   (with props)
cfe/trunk/test/CodeGen/ms-inline-asm-variables.c   (with props)

Added: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp?rev=314300&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp (added)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp Wed Sep 27 05:36:54 2017
@@ -0,0 +1,54 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - 
| FileCheck %s
+
+namespace x {
+  enum { A = 12 };
+  struct y_t {
+enum { A = 17 };
+int r;
+  } y;
+}
+
+// CHECK-LABEL: t1
+void t1() {
+  enum { A = 1 };
+  // CHECK: call void asm
+  // CHECK-SAME: mov eax, $$12
+  __asm mov eax, x::A
+  // CHECK-SAME: mov eax, $$17
+  __asm mov eax, x::y_t::A
+  // CHECK-NEXT: call void asm
+  // CHECK-SAME: mov eax, $$1
+  __asm {mov eax, A}
+}
+
+// CHECK-LABEL: t2
+void t2() {
+  enum { A = 1, B };
+  // CHECK: call void asm
+  // CHECK-SAME: mov eax, $$21
+  __asm mov eax, (A + 9) * 2 + A
+  // CHECK-SAME: mov eax, $$4
+  __asm mov eax, A << 2
+  // CHECK-SAME: mov eax, $$2
+  __asm mov eax, B & 3
+  // CHECK-SAME: mov eax, $$5
+  __asm mov eax, 3 + (B & 3)
+  // CHECK-SAME: mov eax, $$8
+  __asm mov eax, 2 << A * B
+}
+
+// CHECK-LABEL: t3
+void t3() {
+  int arr[4];
+  enum { A = 4, B };
+  // CHECK: call void asm
+  // CHECK-SAME: mov eax, [eax + $$47]
+  __asm { mov eax, [(x::A + 9) + A * B + 3 + 3 + eax] }
+  // CHECK-NEXT: call void asm
+  // CHECK-SAME: mov eax, dword ptr $0[$$4]
+  __asm { mov eax, dword ptr [arr + A] }
+  // CHECK-NEXT: call void asm
+  // CHECK-SAME: mov eax, dword ptr $0[$$8]
+  __asm { mov eax, dword ptr A[arr + A] }
+}

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
--
svn:eol-style = native

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
--
svn:keywords = Author Date Id Rev URL

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
--
svn:mime-type = text/plain

Added: cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-variables.c?rev=314300&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-variables.c (added)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-variables.c Wed Sep 27 05:36:54 2017
@@ -0,0 +1,35 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - 
| FileCheck %s
+
+int gVar;
+void t1() {
+  // CHECK: add eax, dword ptr gVar[eax]
+  __asm add eax, dword ptr gVar[eax]
+  // CHECK: add dword ptr gVar[eax], eax
+  __asm add dword ptr [eax+gVar], eax
+  // CHECK: add ebx, dword ptr gVar[ebx + $$270]
+  __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
+  // CHECK: add dword ptr gVar[ebx + $$828], ebx
+  __asm add dword ptr [ebx + gVar + 828], ebx
+  // CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
+  __asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
+  // CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
+  __asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
+  // CHECK: add gVar[ecx + ebx + $$7], eax
+  __asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
+}
+
+void t2() {
+  int lVar;
+  // CHECK: mov eax, dword ptr ${{[0-9]}}[eax]
+  __asm mov eax, dword ptr lVar[eax]
+  // CHECK: mov dword ptr ${{[0-9]}}[eax], eax
+  __asm mov dword ptr [eax+lVar], eax
+  // CHECK: mov ebx, dword ptr ${{[0-9]}}[ebx + $$270]
+  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
+  // CHECK: mov dword ptr ${{[0-9]}}[ebx + $$828], ebx
+  __asm mov dword ptr [ebx + lVar + 828], ebx
+  // CHECK: mov ${{[0-9]}}[ebx + $$47], eax
+  __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
+}
+

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
--
svn:eol-style = native

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
--
svn:keyword

r314302 - revert rL314300

2017-09-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Sep 27 06:02:44 2017
New Revision: 314302

URL: http://llvm.org/viewvc/llvm-project?rev=314302&view=rev
Log:
revert rL314300
accidently added only tests w/o the respective changes..


Removed:
cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
cfe/trunk/test/CodeGen/ms-inline-asm-variables.c

Removed: cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp?rev=314301&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp (removed)
@@ -1,54 +0,0 @@
-// REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - 
| FileCheck %s
-
-namespace x {
-  enum { A = 12 };
-  struct y_t {
-enum { A = 17 };
-int r;
-  } y;
-}
-
-// CHECK-LABEL: t1
-void t1() {
-  enum { A = 1 };
-  // CHECK: call void asm
-  // CHECK-SAME: mov eax, $$12
-  __asm mov eax, x::A
-  // CHECK-SAME: mov eax, $$17
-  __asm mov eax, x::y_t::A
-  // CHECK-NEXT: call void asm
-  // CHECK-SAME: mov eax, $$1
-  __asm {mov eax, A}
-}
-
-// CHECK-LABEL: t2
-void t2() {
-  enum { A = 1, B };
-  // CHECK: call void asm
-  // CHECK-SAME: mov eax, $$21
-  __asm mov eax, (A + 9) * 2 + A
-  // CHECK-SAME: mov eax, $$4
-  __asm mov eax, A << 2
-  // CHECK-SAME: mov eax, $$2
-  __asm mov eax, B & 3
-  // CHECK-SAME: mov eax, $$5
-  __asm mov eax, 3 + (B & 3)
-  // CHECK-SAME: mov eax, $$8
-  __asm mov eax, 2 << A * B
-}
-
-// CHECK-LABEL: t3
-void t3() {
-  int arr[4];
-  enum { A = 4, B };
-  // CHECK: call void asm
-  // CHECK-SAME: mov eax, [eax + $$47]
-  __asm { mov eax, [(x::A + 9) + A * B + 3 + 3 + eax] }
-  // CHECK-NEXT: call void asm
-  // CHECK-SAME: mov eax, dword ptr $0[$$4]
-  __asm { mov eax, dword ptr [arr + A] }
-  // CHECK-NEXT: call void asm
-  // CHECK-SAME: mov eax, dword ptr $0[$$8]
-  __asm { mov eax, dword ptr A[arr + A] }
-}

Removed: cfe/trunk/test/CodeGen/ms-inline-asm-variables.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-variables.c?rev=314301&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-variables.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-variables.c (removed)
@@ -1,35 +0,0 @@
-// REQUIRES: x86-registered-target
-// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - 
| FileCheck %s
-
-int gVar;
-void t1() {
-  // CHECK: add eax, dword ptr gVar[eax]
-  __asm add eax, dword ptr gVar[eax]
-  // CHECK: add dword ptr gVar[eax], eax
-  __asm add dword ptr [eax+gVar], eax
-  // CHECK: add ebx, dword ptr gVar[ebx + $$270]
-  __asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
-  // CHECK: add dword ptr gVar[ebx + $$828], ebx
-  __asm add dword ptr [ebx + gVar + 828], ebx
-  // CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
-  __asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
-  // CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
-  __asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
-  // CHECK: add gVar[ecx + ebx + $$7], eax
-  __asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
-}
-
-void t2() {
-  int lVar;
-  // CHECK: mov eax, dword ptr ${{[0-9]}}[eax]
-  __asm mov eax, dword ptr lVar[eax]
-  // CHECK: mov dword ptr ${{[0-9]}}[eax], eax
-  __asm mov dword ptr [eax+lVar], eax
-  // CHECK: mov ebx, dword ptr ${{[0-9]}}[ebx + $$270]
-  __asm mov ebx, dword ptr lVar[271 - 82 + 81 + ebx]
-  // CHECK: mov dword ptr ${{[0-9]}}[ebx + $$828], ebx
-  __asm mov dword ptr [ebx + lVar + 828], ebx
-  // CHECK: mov ${{[0-9]}}[ebx + $$47], eax
-  __asm mov 5 + 8 + 13 + 21[lVar + ebx], eax
-}
-


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r314494 - [X86][MS-InlineAsm] Extended support for variables / identifiers on memory / immediate expressions

2017-09-29 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Fri Sep 29 00:02:49 2017
New Revision: 314494

URL: http://llvm.org/viewvc/llvm-project?rev=314494&view=rev
Log:
[X86][MS-InlineAsm] Extended support for variables / identifiers on memory / 
immediate expressions

Allow the proper recognition of Enum values and global variables inside ms 
inline-asm memory / immediate expressions, as they require some additional 
overhead and treated incorrect if doesn't early recognized.
supersedes D33278, D35774

Differential Revision: https://reviews.llvm.org/D37413

Added:
cfe/trunk/test/CodeGen/ms-inline-asm-enums.cpp   (with props)
cfe/trunk/test/CodeGen/ms-inline-asm-variables.c   (with props)
Modified:
cfe/trunk/include/clang/Parse/Parser.h
cfe/trunk/include/clang/Sema/Sema.h
cfe/trunk/lib/Parse/ParseStmtAsm.cpp
cfe/trunk/lib/Sema/SemaStmtAsm.cpp

Modified: cfe/trunk/include/clang/Parse/Parser.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Parse/Parser.h?rev=314494&r1=314493&r2=314494&view=diff
==
--- cfe/trunk/include/clang/Parse/Parser.h (original)
+++ cfe/trunk/include/clang/Parse/Parser.h Fri Sep 29 00:02:49 2017
@@ -1474,7 +1474,6 @@ public:
 
   ExprResult ParseMSAsmIdentifier(llvm::SmallVectorImpl &LineToks,
   unsigned &NumLineToksConsumed,
-  void *Info,
   bool IsUnevaluated);
 
 private:

Modified: cfe/trunk/include/clang/Sema/Sema.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Sema/Sema.h?rev=314494&r1=314493&r2=314494&view=diff
==
--- cfe/trunk/include/clang/Sema/Sema.h (original)
+++ cfe/trunk/include/clang/Sema/Sema.h Fri Sep 29 00:02:49 2017
@@ -3788,15 +3788,15 @@ public:
  Expr *AsmString, MultiExprArg Clobbers,
  SourceLocation RParenLoc);
 
+  void FillInlineAsmIdentifierInfo(Expr *Res,
+   llvm::InlineAsmIdentifierInfo &Info);
   ExprResult LookupInlineAsmIdentifier(CXXScopeSpec &SS,
SourceLocation TemplateKWLoc,
UnqualifiedId &Id,
-   llvm::InlineAsmIdentifierInfo &Info,
bool IsUnevaluatedContext);
   bool LookupInlineAsmField(StringRef Base, StringRef Member,
 unsigned &Offset, SourceLocation AsmLoc);
   ExprResult LookupInlineAsmVarDeclField(Expr *RefExpr, StringRef Member,
- llvm::InlineAsmIdentifierInfo &Info,
  SourceLocation AsmLoc);
   StmtResult ActOnMSAsmStmt(SourceLocation AsmLoc, SourceLocation LBraceLoc,
 ArrayRef AsmToks,

Modified: cfe/trunk/lib/Parse/ParseStmtAsm.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Parse/ParseStmtAsm.cpp?rev=314494&r1=314493&r2=314494&view=diff
==
--- cfe/trunk/lib/Parse/ParseStmtAsm.cpp (original)
+++ cfe/trunk/lib/Parse/ParseStmtAsm.cpp Fri Sep 29 00:02:49 2017
@@ -54,9 +54,9 @@ public:
 assert(AsmToks.size() == AsmTokOffsets.size());
   }
 
-  void *LookupInlineAsmIdentifier(StringRef &LineBuf,
-  llvm::InlineAsmIdentifierInfo &Info,
-  bool IsUnevaluatedContext) override {
+  void LookupInlineAsmIdentifier(StringRef &LineBuf,
+ llvm::InlineAsmIdentifierInfo &Info,
+ bool IsUnevaluatedContext) override {
 // Collect the desired tokens.
 SmallVector LineToks;
 const Token *FirstOrigToken = nullptr;
@@ -64,7 +64,7 @@ public:
 
 unsigned NumConsumedToks;
 ExprResult Result = TheParser.ParseMSAsmIdentifier(
-LineToks, NumConsumedToks, &Info, IsUnevaluatedContext);
+LineToks, NumConsumedToks, IsUnevaluatedContext);
 
 // If we consumed the entire line, tell MC that.
 // Also do this if we consumed nothing as a way of reporting failure.
@@ -89,9 +89,10 @@ public:
   LineBuf = LineBuf.substr(0, TotalOffset);
 }
 
-// Initialize the "decl" with the lookup result.
-Info.OpDecl = static_cast(Result.get());
-return Info.OpDecl;
+// Initialize Info with the lookup result.
+if (!Result.isUsable())
+  return;
+TheParser.getActions().FillInlineAsmIdentifierInfo(Result.get(), Info);
   }
 
   StringRef LookupInlineAsmLabel(StringRef Identifier, llvm::SourceMgr &LSM,
@@ -178,16 +179,9 @@ private:
 }
 
 /// Parse an identifier in an MS-style inline assembly block.
-///
-/// \param CastInfo - a void* so that we don't have to teach Parser.h
-///   about the actual type.
 ExprResult Parser::ParseMSAsmIdentifier(llvm::SmallVe

r314529 - fixup, post rL314493

2017-09-29 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Fri Sep 29 09:04:16 2017
New Revision: 314529

URL: http://llvm.org/viewvc/llvm-project?rev=314529&view=rev
Log:
fixup, post rL314493
'InlineAsmIdentifierInfo' is now a struct - notify Sema.h it isn't a class 
anymore

Modified:
cfe/trunk/include/clang/Sema/Sema.h

Modified: cfe/trunk/include/clang/Sema/Sema.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Sema/Sema.h?rev=314529&r1=314528&r2=314529&view=diff
==
--- cfe/trunk/include/clang/Sema/Sema.h (original)
+++ cfe/trunk/include/clang/Sema/Sema.h Fri Sep 29 09:04:16 2017
@@ -64,7 +64,7 @@ namespace llvm {
   template  struct DenseMapInfo;
   template  class DenseSet;
   class SmallBitVector;
-  class InlineAsmIdentifierInfo;
+  struct InlineAsmIdentifierInfo;
 }
 
 namespace clang {


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r321474 - [x86][icelake][vaes]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 00:16:54 2017
New Revision: 321474

URL: http://llvm.org/viewvc/llvm-project?rev=321474&view=rev
Log:
[x86][icelake][vaes]
added vaes feature recognition
added intrinsics support for vaes instructions, matching a similar work on the 
backend (D40078)
  _mm256_aesenc_epi128
  _mm512_aesenc_epi128
  _mm256_aesenclast_epi128
  _mm512_aesenclast_epi128
  _mm256_aesdec_epi128
  _mm512_aesdec_epi128
  _mm256_aesdeclast_epi128
  _mm512_aesdeclast_epi128

Added:
cfe/trunk/lib/Headers/vaesintrin.h   (with props)
cfe/trunk/test/CodeGen/vaes-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
cfe/trunk/test/Preprocessor/x86_target_features.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321474&r1=321473&r2=321474&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 00:16:54 2017
@@ -429,6 +429,16 @@ TARGET_BUILTIN(__builtin_ia32_aesdeclast
 TARGET_BUILTIN(__builtin_ia32_aesimc128, "V2LLiV2LLi", "", "aes")
 TARGET_BUILTIN(__builtin_ia32_aeskeygenassist128, "V2LLiV2LLiIc", "", "aes")
 
+// VAES
+TARGET_BUILTIN(__builtin_ia32_aesenc256, "V4LLiV4LLiV4LLi", "", "vaes")
+TARGET_BUILTIN(__builtin_ia32_aesenc512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
+TARGET_BUILTIN(__builtin_ia32_aesenclast256, "V4LLiV4LLiV4LLi", "", "vaes")
+TARGET_BUILTIN(__builtin_ia32_aesenclast512, "V8LLiV8LLiV8LLi", "", 
"avx512f,vaes")
+TARGET_BUILTIN(__builtin_ia32_aesdec256, "V4LLiV4LLiV4LLi", "", "vaes")
+TARGET_BUILTIN(__builtin_ia32_aesdec512, "V8LLiV8LLiV8LLi", "", "avx512f,vaes")
+TARGET_BUILTIN(__builtin_ia32_aesdeclast256, "V4LLiV4LLiV4LLi", "", "vaes")
+TARGET_BUILTIN(__builtin_ia32_aesdeclast512, "V8LLiV8LLiV8LLi", "", 
"avx512f,vaes")
+
 // CLMUL
 TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
 

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=321474&r1=321473&r2=321474&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Dec 27 00:16:54 2017
@@ -2543,6 +2543,8 @@ def msha : Flag<["-"], "msha">, Group, Group;
 def mtbm : Flag<["-"], "mtbm">, Group;
 def mno_tbm : Flag<["-"], "mno-tbm">, Group;
+def mvaes : Flag<["-"], "mvaes">, Group;
+def mno_vaes : Flag<["-"], "mno-vaes">, Group;
 def mxop : Flag<["-"], "mxop">, Group;
 def mno_xop : Flag<["-"], "mno-xop">, Group;
 def mxsave : Flag<["-"], "mxsave">, Group;

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=321474&r1=321473&r2=321474&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Wed Dec 27 00:16:54 2017
@@ -132,6 +132,7 @@ bool X86TargetInfo::initFeatureMap(
 break;
 
   case CK_Icelake:
+setFeatureEnabledImpl(Features, "vaes", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -460,7 +461,7 @@ void X86TargetInfo::setSSELevel(llvm::St
 LLVM_FALLTHROUGH;
   case AVX:
 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
-Features["xsaveopt"] = false;
+Features["xsaveopt"] = Features["vaes"] = false;
 setXOPLevel(Features, FMA4, false);
 LLVM_FALLTHROUGH;
   case AVX2:
@@ -572,6 +573,13 @@ void X86TargetInfo::setFeatureEnabledImp
   } else if (Name == "aes") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+else
+  Features["vaes"] = false;
+  } else if (Name == "vaes") {
+if (Enabled) {
+  setSSELevel(Features, AVX, Enabled);
+  Features["aes"] = true;
+}
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
@@ -636,6 +644,8 @@ bool X86TargetInfo::handleTargetFeatures
 
 if (Feature == "+aes") {
   HasAES = true;
+} else if (Feature == "+vaes") {
+  HasVAES = true;
 } else if (Feature == "+pclmul") {
   HasPCLMUL = true;
 } else if (Feature == "+lzcnt") {
@@ -934,6 +944,9 @@ void X86TargetInfo::getTargetDefines(con
   if (HasAES)
 Builder.defineMacro("__AES__");
 
+  if (HasVAES)
+Builder.defineMacro("__VAES__");
+

r321477 - [x86][icelake][gfni]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 00:37:47 2017
New Revision: 321477

URL: http://llvm.org/viewvc/llvm-project?rev=321477&view=rev
Log:
[x86][icelake][gfni]
added gfni feature recognition
added intrinsics support for gfni instructions
  _mm_gf2p8affineinv_epi64_epi8
  _mm_mask_gf2p8affineinv_epi64_epi8
  _mm_maskz_gf2p8affineinv_epi64_epi8
  _mm256_gf2p8affineinv_epi64_epi8
  _mm256_mask_gf2p8affineinv_epi64_epi8
  _mm256_maskz_gf2p8affineinv_epi64_epi8
  _mm512_gf2p8affineinv_epi64_epi8
  _mm512_mask_gf2p8affineinv_epi64_epi8
  _mm512_maskz_gf2p8affineinv_epi64_epi8
  _mm_gf2p8affine_epi64_epi8
  _mm_mask_gf2p8affine_epi64_epi8
  _mm_maskz_gf2p8affine_epi64_epi8
  _mm256_gf2p8affine_epi64_epi8
  _mm256_mask_gf2p8affine_epi64_epi8
  _mm256_maskz_gf2p8affine_epi64_epi8
  _mm512_gf2p8affine_epi64_epi8
  _mm512_mask_gf2p8affine_epi64_epi8
  _mm512_maskz_gf2p8affine_epi64_epi8
  _mm_gf2p8mul_epi8
  _mm_mask_gf2p8mul_epi8
  _mm_maskz_gf2p8mul_epi8
  _mm256_gf2p8mul_epi8
  _mm256_mask_gf2p8mul_epi8
  _mm256_maskz_gf2p8mul_epi8
  _mm512_gf2p8mul_epi8
  _mm512_mask_gf2p8mul_epi8
  _mm512_maskz_gf2p8mul_epi8
matching a similar work on the backend (D40373)
Differential Revision: https://reviews.llvm.org/D41582

Added:
cfe/trunk/lib/Headers/gfniintrin.h   (with props)
cfe/trunk/test/CodeGen/gfni-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
cfe/trunk/test/Preprocessor/x86_target_features.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321477&r1=321476&r2=321477&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 00:37:47 2017
@@ -439,6 +439,17 @@ TARGET_BUILTIN(__builtin_ia32_aesdec512,
 TARGET_BUILTIN(__builtin_ia32_aesdeclast256, "V4LLiV4LLiV4LLi", "", "vaes")
 TARGET_BUILTIN(__builtin_ia32_aesdeclast512, "V8LLiV8LLiV8LLi", "", 
"avx512f,vaes")
 
+// GFNI
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v16qi, "V16cV16cV16cIc", "", 
"gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v32qi, "V32cV32cV32cIc", "", 
"avx,gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineinvqb_v64qi, "V64cV64cV64cIc", "", 
"avx512bw,gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v16qi, "V16cV16cV16cIc", "", 
"gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v32qi, "V32cV32cV32cIc", "", 
"avx,gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8affineqb_v64qi, "V64cV64cV64cIc", "", 
"avx512bw,gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v16qi, "V16cV16cV16c", "", "gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v32qi, "V32cV32cV32c", "", "avx,gfni")
+TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb_v64qi, "V64cV64cV64c", "", 
"avx512bw,gfni")
+
 // CLMUL
 TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
 

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=321477&r1=321476&r2=321477&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Dec 27 00:37:47 2017
@@ -2511,6 +2511,8 @@ def mfsgsbase : Flag<["-"], "mfsgsbase">
 def mno_fsgsbase : Flag<["-"], "mno-fsgsbase">, Group;
 def mfxsr : Flag<["-"], "mfxsr">, Group;
 def mno_fxsr : Flag<["-"], "mno-fxsr">, Group;
+def mgfni : Flag<["-"], "mgfni">, Group;
+def mno_gfni : Flag<["-"], "mno-gfni">, Group;
 def mlwp : Flag<["-"], "mlwp">, Group;
 def mno_lwp : Flag<["-"], "mno-lwp">, Group;
 def mlzcnt : Flag<["-"], "mlzcnt">, Group;

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=321477&r1=321476&r2=321477&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Wed Dec 27 00:37:47 2017
@@ -133,6 +133,7 @@ bool X86TargetInfo::initFeatureMap(
 
   case CK_Icelake:
 setFeatureEnabledImpl(Features, "vaes", true);
+setFeatureEnabledImpl(Features, "gfni", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -444,7 +445,7 @@ void X86TargetInfo::setSSELevel(llvm::St
 LLVM_FALLTHROUGH;
   case SSE2:
 Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] =
-false;
+Features["gfni"] = false;
 LL

r321480 - [x86][icelake][vpclmulqdq]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 01:00:31 2017
New Revision: 321480

URL: http://llvm.org/viewvc/llvm-project?rev=321480&view=rev
Log:
[x86][icelake][vpclmulqdq]
added vpclmulqdq feature recognition
added intrinsics support for vpclmulqdq instructions
  _mm256_clmulepi64_epi128
  _mm512_clmulepi64_epi128
matching a similar work on the backend (D40101)
Differential Revision: https://reviews.llvm.org/D41573

Added:
cfe/trunk/lib/Headers/vpclmulqdqintrin.h   (with props)
cfe/trunk/test/CodeGen/vpclmulqdq-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
cfe/trunk/test/Preprocessor/x86_target_features.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321480&r1=321479&r2=321480&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 01:00:31 2017
@@ -453,6 +453,10 @@ TARGET_BUILTIN(__builtin_ia32_vgf2p8mulb
 // CLMUL
 TARGET_BUILTIN(__builtin_ia32_pclmulqdq128, "V2LLiV2LLiV2LLiIc", "", "pclmul")
 
+// VPCLMULQDQ
+TARGET_BUILTIN(__builtin_ia32_pclmulqdq256, "V4LLiV4LLiV4LLiIc", "", 
"vpclmulqdq")
+TARGET_BUILTIN(__builtin_ia32_pclmulqdq512, "V8LLiV8LLiV8LLiIc", "", 
"avx512f,vpclmulqdq")
+
 // AVX
 TARGET_BUILTIN(__builtin_ia32_addsubpd256, "V4dV4dV4d", "", "avx")
 TARGET_BUILTIN(__builtin_ia32_addsubps256, "V8fV8fV8f", "", "avx")

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=321480&r1=321479&r2=321480&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Dec 27 01:00:31 2017
@@ -2547,6 +2547,8 @@ def mtbm : Flag<["-"], "mtbm">, Group, Group;
 def mvaes : Flag<["-"], "mvaes">, Group;
 def mno_vaes : Flag<["-"], "mno-vaes">, Group;
+def mvpclmulqdq : Flag<["-"], "mvpclmulqdq">, Group;
+def mno_vpclmulqdq : Flag<["-"], "mno-vpclmulqdq">, 
Group;
 def mxop : Flag<["-"], "mxop">, Group;
 def mno_xop : Flag<["-"], "mno-xop">, Group;
 def mxsave : Flag<["-"], "mxsave">, Group;

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=321480&r1=321479&r2=321480&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Wed Dec 27 01:00:31 2017
@@ -134,6 +134,7 @@ bool X86TargetInfo::initFeatureMap(
   case CK_Icelake:
 setFeatureEnabledImpl(Features, "vaes", true);
 setFeatureEnabledImpl(Features, "gfni", true);
+setFeatureEnabledImpl(Features, "vpclmulqdq", true);
 // TODO: Add icelake features here.
 LLVM_FALLTHROUGH;
   case CK_Cannonlake:
@@ -462,7 +463,7 @@ void X86TargetInfo::setSSELevel(llvm::St
 LLVM_FALLTHROUGH;
   case AVX:
 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
-Features["xsaveopt"] = Features["vaes"] = false;
+Features["xsaveopt"] = Features["vaes"] = Features["vpclmulqdq"] = 
false;
 setXOPLevel(Features, FMA4, false);
 LLVM_FALLTHROUGH;
   case AVX2:
@@ -584,6 +585,13 @@ void X86TargetInfo::setFeatureEnabledImp
   } else if (Name == "pclmul") {
 if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
+else
+  Features["vpclmulqdq"] = false;
+  } else if (Name == "vpclmulqdq") {
+if (Enabled) {
+  setSSELevel(Features, AVX, Enabled);
+  Features["pclmul"] = true;
+}
   } else if (Name == "gfni") {
  if (Enabled)
   setSSELevel(Features, SSE2, Enabled);
@@ -652,6 +660,8 @@ bool X86TargetInfo::handleTargetFeatures
   HasVAES = true;
 } else if (Feature == "+pclmul") {
   HasPCLMUL = true;
+} else if (Feature == "+vpclmulqdq") {
+  HasVPCLMULQDQ = true;
 } else if (Feature == "+lzcnt") {
   HasLZCNT = true;
 } else if (Feature == "+rdrnd") {
@@ -956,6 +966,9 @@ void X86TargetInfo::getTargetDefines(con
   if (HasPCLMUL)
 Builder.defineMacro("__PCLMUL__");
 
+  if (HasVPCLMULQDQ)
+Builder.defineMacro("__VPCLMULQDQ__");
+
   if (HasLZCNT)
 Builder.defineMacro("__LZCNT__");
 
@@ -1209,6 +1222,7 @@ bool X86TargetInfo::isValidFeatureName(S
   .Case("sse4a", true)
   .Case("tbm", true)
   .Case("vaes", true)
+  .Case("vpclmulqdq", true)
   .Case("x87", true)
   .

r321482 - [hotfix]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 01:22:34 2017
New Revision: 321482

URL: http://llvm.org/viewvc/llvm-project?rev=321482&view=rev
Log:
[hotfix]
fixinig test failures as seen here:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/22791/steps/test/logs/stdio
which resulted by rL321480

Modified:
cfe/trunk/test/Driver/x86-target-features.c

Modified: cfe/trunk/test/Driver/x86-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/x86-target-features.c?rev=321482&r1=321481&r2=321482&view=diff
==
--- cfe/trunk/test/Driver/x86-target-features.c (original)
+++ cfe/trunk/test/Driver/x86-target-features.c Wed Dec 27 01:22:34 2017
@@ -102,17 +102,11 @@
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mgfni %s -### -o 
%t.o 2>&1 | FileCheck -check-prefix=GFNI %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-gfni %s -### -o 
%t.o 2>&1 | FileCheck -check-prefix=NO-GFNI %s
-<<<
 // GFNI: "-target-feature" "+gfni"
 // NO-GFNI: "-target-feature" "-gfni
 
-===
-// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-clzero %s -### 
-o %t.o 2>&1 | FileCheck -check-prefix=NO-CLZERO %s
-// CLZERO: "-target-feature" "+clzero"
-// NO-CLZERO: "-target-feature" "-clzero"
-
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mvpclmulqdq %s -### 
-o %t.o 2>&1 | FileCheck -check-prefix=VPCLMULQDQ %s
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vpclmulqdq %s 
-### -o %t.o 2>&1 | FileCheck -check-prefix=NO-VPCLMULQDQ %s
 // VPCLMULQDQ: "-target-feature" "+vpclmulqdq"
 // NO-VPCLMULQDQ: "-target-feature" "-vpclmulqdq"
->>>
+


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r321483 - [x86][icelake][bitalg]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 02:01:00 2017
New Revision: 321483

URL: http://llvm.org/viewvc/llvm-project?rev=321483&view=rev
Log:
[x86][icelake][bitalg]
added bitalg feature recognition
added intrinsics support for bitalg instructions
_mm512_popcnt_epi16
_mm512_mask_popcnt_epi16
_mm512_maskz_popcnt_epi16
_mm512_popcnt_epi8
_mm512_mask_popcnt_epi8
_mm512_maskz_popcnt_epi8
_mm512_mask_bitshuffle_epi64_mask
_mm512_bitshuffle_epi64_mask
_mm256_popcnt_epi16
_mm256_mask_popcnt_epi16
_mm256_maskz_popcnt_epi16
_mm128_popcnt_epi16
_mm128_mask_popcnt_epi16
_mm128_maskz_popcnt_epi16
_mm256_popcnt_epi8
_mm256_mask_popcnt_epi8
_mm256_maskz_popcnt_epi8
_mm128_popcnt_epi8
_mm128_mask_popcnt_epi8
_mm128_maskz_popcnt_epi8
_mm256_mask_bitshuffle_epi32_mask
_mm256_bitshuffle_epi32_mask
_mm128_mask_bitshuffle_epi16_mask
_mm128_bitshuffle_epi16_mask
matching a similar work on the backend (D40222)
Differential Revision: https://reviews.llvm.org/D41564

Added:
cfe/trunk/lib/Headers/avx512bitalgintrin.h   (with props)
cfe/trunk/lib/Headers/avx512vlbitalgintrin.h   (with props)
cfe/trunk/test/CodeGen/avx512bitalg-builtins.c   (with props)
cfe/trunk/test/CodeGen/avx512vlbitalg-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
cfe/trunk/test/Preprocessor/x86_target_features.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321483&r1=321482&r2=321483&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 02:01:00 2017
@@ -1092,6 +1092,17 @@ TARGET_BUILTIN(__builtin_ia32_vpopcntq_2
 TARGET_BUILTIN(__builtin_ia32_vpopcntd_512, "V16iV16i", "", "avx512vpopcntdq")
 TARGET_BUILTIN(__builtin_ia32_vpopcntq_512, "V8LLiV8LLi", "", 
"avx512vpopcntdq")
 
+TARGET_BUILTIN(__builtin_ia32_vpopcntb_128, "V16cV16c", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpopcntw_128, "V8sV8s", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpopcntb_256, "V32cV32c", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpopcntw_256, "V16sV16s", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpopcntb_512, "V64cV64c", "", "avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpopcntw_512, "V32sV32s", "", "avx512bitalg")
+
+TARGET_BUILTIN(__builtin_ia32_vpshufbitqmb128_mask, "UsV16cV16cUs", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpshufbitqmb256_mask, "UiV32cV32cUi", "", 
"avx512vl,avx512bitalg")
+TARGET_BUILTIN(__builtin_ia32_vpshufbitqmb512_mask, "ULLiV64cV64cULLi", "", 
"avx512bitalg")
+
 TARGET_BUILTIN(__builtin_ia32_vpermi2varhi128_mask, "V8sV8sV8sV8sUc", "", 
"avx512vl,avx512bw")
 TARGET_BUILTIN(__builtin_ia32_vpermi2varhi256_mask, "V16sV16sV16sV16sUs", "", 
"avx512vl,avx512bw")
 TARGET_BUILTIN(__builtin_ia32_vpermt2varhi128_mask, "V8sV8sV8sV8sUc", "", 
"avx512vl,avx512bw")

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=321483&r1=321482&r2=321483&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Dec 27 02:01:00 2017
@@ -2467,6 +2467,8 @@ def mavx2 : Flag<["-"], "mavx2">, Group<
 def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
 def mavx512f : Flag<["-"], "mavx512f">, Group;
 def mno_avx512f : Flag<["-"], "mno-avx512f">, Group;
+def mavx512bitalg : Flag<["-"], "mavx512bitalg">, Group;
+def mno_avx512bitalg : Flag<["-"], "mno-avx512bitalg">, 
Group;
 def mavx512bw : Flag<["-"], "mavx512bw">, Group;
 def mno_avx512bw : Flag<["-"], "mno-avx512bw">, Group;
 def mavx512cd : Flag<["-"], "mavx512cd">, Group;

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=321483&r1=321482&r2=321483&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Wed Dec 27 02:01:00 2017
@@ -135,6 +135,7 @@ bool X86TargetInfo::initFeatureMap(
 setFeatureEnabledImpl(Features, "vaes", true);
 setFeatureEnabledImpl(Features, "gfni", true);
 setFeatureEnabledImpl(Features, "vpclmulqdq", true);
+setFeatureEnabledImpl(Features, "avx512bitalg", true);
 // TODO: Add icelake features here.

r321484 - [x86][icelake][vnni]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 02:37:51 2017
New Revision: 321484

URL: http://llvm.org/viewvc/llvm-project?rev=321484&view=rev
Log:
[x86][icelake][vnni]
added vnni feature recognition
added intrinsics support for VNNI instructions
_mm256_mask_dpbusd_epi32
_mm256_maskz_dpbusd_epi32
_mm256_dpbusd_epi32
_mm256_mask_dpbusds_epi32
_mm256_maskz_dpbusds_epi32
_mm256_dpbusds_epi32
_mm256_mask_dpwssd_epi32
_mm256_maskz_dpwssd_epi32
_mm256_dpwssd_epi32
_mm256_mask_dpwssds_epi32
_mm256_maskz_dpwssds_epi32
_mm256_dpwssds_epi32
_mm128_mask_dpbusd_epi32
_mm128_maskz_dpbusd_epi32
_mm128_dpbusd_epi32
_mm128_mask_dpbusds_epi32
_mm128_maskz_dpbusds_epi32
_mm128_dpbusds_epi32
_mm128_mask_dpwssd_epi32
_mm128_maskz_dpwssd_epi32
_mm128_dpwssd_epi32
_mm128_mask_dpwssds_epi32
_mm128_maskz_dpwssds_epi32
_mm128_dpwssds_epi32
_mm512_mask_dpbusd_epi32
_mm512_maskz_dpbusd_epi32
_mm512_dpbusd_epi32
_mm512_mask_dpbusds_epi32
_mm512_maskz_dpbusds_epi32
_mm512_dpbusds_epi32
_mm512_mask_dpwssd_epi32
_mm512_maskz_dpwssd_epi32
_mm512_dpwssd_epi32
_mm512_mask_dpwssds_epi32
_mm512_maskz_dpwssds_epi32
_mm512_dpwssds_epi32
matching a similar work on the backend (D40208)
Differential Revision: https://reviews.llvm.org/D41558

Added:
cfe/trunk/lib/Headers/avx512vlvnniintrin.h   (with props)
cfe/trunk/lib/Headers/avx512vnniintrin.h   (with props)
cfe/trunk/test/CodeGen/avx512vlvnni-builtins.c   (with props)
cfe/trunk/test/CodeGen/avx512vnni-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321484&r1=321483&r2=321484&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 02:37:51 2017
@@ -979,6 +979,31 @@ TARGET_BUILTIN(__builtin_ia32_vpermt2var
 TARGET_BUILTIN(__builtin_ia32_vpermt2varps512_mask, "V16fV16iV16fV16fUs", "", 
"avx512f")
 TARGET_BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "", 
"avx512f")
 
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd128_mask, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd256_mask, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd512_mask, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds128_mask, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds256_mask, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds512_mask, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd128_mask, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd256_mask, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd512_mask, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds128_mask, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds256_mask, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds512_mask, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd128_maskz, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd256_maskz, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusd512_maskz, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds128_maskz, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds256_maskz, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpbusds512_maskz, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd128_maskz, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd256_maskz, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssd512_maskz, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds128_maskz, "V4iV4iV4iV4iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds256_maskz, "V8iV8iV8iV8iUc", "", 
"avx512vl,avx512vnni")
+TARGET_BUILTIN(__builtin_ia32_vpdpwssds512_maskz, "V16iV16iV16iV16iUs", "", 
"avx512vnni")
+
 TARGET_BUILTIN(__builtin_ia32_gather3div2df, 
"V2dV2ddC*V2LLiUcIi","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_gather3div2di, 
"V2LLiV2LLiLLiC*V2LLiUcIi","","avx512vl")
 TARGET_BUILTIN(__builtin_ia32_gather3d

r321487 - [x86][icelake][vbmi2]

2017-12-27 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Dec 27 03:25:07 2017
New Revision: 321487

URL: http://llvm.org/viewvc/llvm-project?rev=321487&view=rev
Log:
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557

Added:
cfe/trunk/lib/Headers/avx512vbmi2intrin.h   (with props)
cfe/trunk/lib/Headers/avx512vlvbmi2intrin.h   (with props)
cfe/trunk/test/CodeGen/avx512vbmi2-builtins.c   (with props)
cfe/trunk/test/CodeGen/avx512vlvbmi2-builtins.c   (with props)
Modified:
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/predefined-arch-macros.c
cfe/trunk/test/Preprocessor/x86_target_features.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsX86.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsX86.def?rev=321487&r1=321486&r2=321487&view=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def Wed Dec 27 03:25:07 2017
@@ -1168,6 +1168,12 @@ TARGET_BUILTIN(__builtin_ia32_compressdf
 TARGET_BUILTIN(__builtin_ia32_compressdf256_mask, "V4dV4dV4dUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressdi128_mask, "V2LLiV2LLiV2LLiUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressdi256_mask, "V4LLiV4LLiV4LLiUc", "", 
"avx512vl")
+
+TARGET_BUILTIN(__builtin_ia32_compresshi128_mask, 
"V8sV8sV8sUc","","avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compresshi256_mask, 
"V16sV16sV16sUs","","avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compressqi128_mask, 
"V16cV16cV16cUs","","avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compressqi256_mask, 
"V32cV32cV32cUi","","avx512vl,avx512vbmi2")
+
 TARGET_BUILTIN(__builtin_ia32_compresssf128_mask, "V4fV4fV4fUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compresssf256_mask, "V8fV8fV8fUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compresssi128_mask, "V4iV4iV4iUc", "", 
"avx512vl")
@@ -1176,6 +1182,12 @@ TARGET_BUILTIN(__builtin_ia32_compressst
 TARGET_BUILTIN(__builtin_ia32_compressstoredf256_mask, "vV4d*V4dUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressstoredi128_mask, "vV2LLi*V2LLiUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressstoredi256_mask, "vV4LLi*V4LLiUc", "", 
"avx512vl")
+
+TARGET_BUILTIN(__builtin_ia32_compressstorehi128_mask, "vV8s*V8sUc", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compressstorehi256_mask, "vV16s*V16sUs", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compressstoreqi128_mask, "vV16c*V16cUs", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_compressstoreqi256_mask, "vV32c*V32cUi", "", 
"avx512vl,avx512vbmi2")
+
 TARGET_BUILTIN(__builtin_ia32_compressstoresf128_mask, "vV4f*V4fUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressstoresf256_mask, "vV8f*V8fUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_compressstoresi128_mask, "vV4i*V4iUc", "", 
"avx512vl")
@@ -1208,10 +1220,22 @@ TARGET_BUILTIN(__builtin_ia32_expanddf12
 TARGET_BUILTIN(__builtin_ia32_expanddf256_mask, "V4dV4dV4dUc", "", "avx512vl")
 TARGET_BUILTIN(__builtin_ia32_expanddi128_mask, "V2LLiV2LLiV2LLiUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_expanddi256_mask, "V4LLiV4LLiV4LLiUc", "", 
"avx512vl")
+
+TARGET_BUILTIN(__builtin_ia32_expandhi128_mask, "V8sV8sV8sUc", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_expandhi256_mask, "V16sV16sV16sUs", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_expandqi128_mask, "V16cV16cV16cUs", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_expandqi256_mask, "V32cV32cV32cUi", "", 
"avx512vl,avx512vbmi2")
+
 TARGET_BUILTIN(__builtin_ia32_expandloaddf128_mask, "V2dV2d*V2dUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_expandloaddf256_mask, "V4dV4d*V4dUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_expandloaddi128_mask, "V4iV2LLi*V2LLiUc", "", 
"avx512vl")
 TARGET_BUILTIN(__builtin_ia32_expandloaddi256_mask, "V4LLiV4LLi*V4LLiUc", "", 
"avx512vl")
+
+TARGET_BUILTIN(__builtin_ia32_expandloadhi128_mask, "V8sV8sC*V8sUc", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_expandloadhi256_mask, "V16sV16sC*V16sUs", "", 
"avx512vl,avx512vbmi2")
+TARGET_BUILTIN(__builtin_ia32_

r312882 - [clang][SemaStmtAsm] small refactoring, NFC.

2017-09-10 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Sun Sep 10 05:39:21 2017
New Revision: 312882

URL: http://llvm.org/viewvc/llvm-project?rev=312882&view=rev
Log:
[clang][SemaStmtAsm] small refactoring, NFC.


Modified:
cfe/trunk/lib/Sema/SemaStmtAsm.cpp

Modified: cfe/trunk/lib/Sema/SemaStmtAsm.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaStmtAsm.cpp?rev=312882&r1=312881&r2=312882&view=diff
==
--- cfe/trunk/lib/Sema/SemaStmtAsm.cpp (original)
+++ cfe/trunk/lib/Sema/SemaStmtAsm.cpp Sun Sep 10 05:39:21 2017
@@ -62,11 +62,13 @@ static bool CheckAsmLValue(const Expr *E
 
 /// isOperandMentioned - Return true if the specified operand # is mentioned
 /// anywhere in the decomposed asm string.
-static bool isOperandMentioned(unsigned OpNo,
- ArrayRef AsmStrPieces) {
+static bool
+isOperandMentioned(unsigned OpNo,
+   ArrayRef AsmStrPieces) {
   for (unsigned p = 0, e = AsmStrPieces.size(); p != e; ++p) {
 const GCCAsmStmt::AsmStringPiece &Piece = AsmStrPieces[p];
-if (!Piece.isOperand()) continue;
+if (!Piece.isOperand())
+  continue;
 
 // If this is a reference to the input and if the input was the smaller
 // one, then we have to reject this asm.


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r309510 - [x86][inline-asm][ms-compat] legalize the use of "jc/jz short "

2017-07-30 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Sun Jul 30 04:13:46 2017
New Revision: 309510

URL: http://llvm.org/viewvc/llvm-project?rev=309510&view=rev
Log:
[x86][inline-asm][ms-compat] legalize the use of "jc/jz short "

MS ignores the keyword "short" when used after a jc/jz instruction, LLVM ought 
to do the same.
llvm: D35892

Differential Revision: https://reviews.llvm.org/D35893

Modified:
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=309510&r1=309509&r2=309510&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Sun Jul 30 04:13:46 2017
@@ -704,10 +704,12 @@ void label5() {
 void label6(){
   __asm {
   jmp short label
+  jc  short label
+  jz  short label
 label:
   }
   // CHECK-LABEL: define void @label6
-  // CHECK: call void asm sideeffect inteldialect "jmp 
{{.*}}__MSASMLABEL_.${:uid}__label\0A\09{{.*}}__MSASMLABEL_.${:uid}__label:", 
"~{dirflag},~{fpsr},~{flags}"()
+  // CHECK: jmp {{.*}}__MSASMLABEL_.${:uid}__label\0A\09jc 
{{.*}}__MSASMLABEL_.${:uid}__label\0A\09jz 
{{.*}}__MSASMLABEL_.${:uid}__label\0A\09{{.*}}__MSASMLABEL_.${:uid}__label:"
 }
 
 // Don't include mxcsr in the clobber list.


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r309508 - [x86][inline-asm]Allow a pack of Control Regs to be properly picked

2017-07-30 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Sun Jul 30 03:19:10 2017
New Revision: 309508

URL: http://llvm.org/viewvc/llvm-project?rev=309508&view=rev
Log:
[x86][inline-asm]Allow a pack of Control Regs to be properly picked

Allows the incorporation of legit (x86) Control Regs within inline asm 
stataements

Differential Revision: https://reviews.llvm.org/D35903

Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=309508&r1=309507&r2=309508&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Sun Jul 30 03:19:10 2017
@@ -58,6 +58,7 @@ static const char *const GCCRegNames[] =
 "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
+"cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=309508&r1=309507&r2=309508&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Sun Jul 30 03:19:10 2017
@@ -627,6 +627,17 @@ void t43() {
 // CHECK: call void asm sideeffect inteldialect "mov eax, $0", 
"*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
 }
 
+void t44() {
+  // CHECK-LABEL: define void @t44
+  __asm {
+mov cr0, eax
+mov cr2, ebx
+mov cr3, ecx
+mov cr4, edx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


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r309672 - [x86][inline-asm]Allow a pack of Control Debug to be properly picked

2017-08-01 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Tue Aug  1 03:51:09 2017
New Revision: 309672

URL: http://llvm.org/viewvc/llvm-project?rev=309672&view=rev
Log:
[x86][inline-asm]Allow a pack of Control Debug to be properly picked

Allows the incorporation of legit (x86) Debug Regs within inline asm stataements

Differential Revision: https://reviews.llvm.org/D36074

Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=309672&r1=309671&r2=309672&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Tue Aug  1 03:51:09 2017
@@ -59,6 +59,7 @@ static const char *const GCCRegNames[] =
 "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0","k1",
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
+"dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=309672&r1=309671&r2=309672&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Tue Aug  1 03:51:09 2017
@@ -638,6 +638,19 @@ void t44() {
   // CHECK: call void asm sideeffect inteldialect "mov cr0, eax\0A\09mov cr2, 
ebx\0A\09mov cr3, ecx\0A\09mov cr4, edx", 
"~{cr0},~{cr2},~{cr3},~{cr4},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t45() {
+  // CHECK-LABEL: define void @t45
+  __asm {
+mov dr0, eax
+mov dr1, ebx
+mov dr2, ebx
+mov dr3, ecx
+mov dr6, edx
+mov dr7, ecx
+  }
+  // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


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r310472 - [X86][Ms-InlineAsm] Extend MS Dot operator to accept "this" + struct/class pointers aliases

2017-08-09 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Aug  9 06:31:41 2017
New Revision: 310472

URL: http://llvm.org/viewvc/llvm-project?rev=310472&view=rev
Log:
[X86][Ms-InlineAsm] Extend MS Dot operator to accept "this" + struct/class 
pointers aliases

MS InlineAsm Dot operator accepts "Bases" such as "this" (cpp) and class/struct 
pointer typedef.
This patch enhance its implementation with this behavior.

Differential Revision: https://reviews.llvm.org/D36450

Modified:
cfe/trunk/lib/Sema/SemaStmtAsm.cpp
cfe/trunk/test/CodeGen/ms-inline-asm.c
cfe/trunk/test/CodeGen/ms-inline-asm.cpp

Modified: cfe/trunk/lib/Sema/SemaStmtAsm.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaStmtAsm.cpp?rev=310472&r1=310471&r2=310472&view=diff
==
--- cfe/trunk/lib/Sema/SemaStmtAsm.cpp (original)
+++ cfe/trunk/lib/Sema/SemaStmtAsm.cpp Wed Aug  9 06:31:41 2017
@@ -677,22 +677,33 @@ bool Sema::LookupInlineAsmField(StringRe
   SmallVector Members;
   Member.split(Members, ".");
 
-  LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
-  LookupOrdinaryName);
+  NamedDecl *FoundDecl = nullptr;
 
-  if (!LookupName(BaseResult, getCurScope()))
-return true;
-  
-  if(!BaseResult.isSingleResult())
+  // MS InlineAsm uses 'this' as a base
+  if (getLangOpts().CPlusPlus && Base.equals("this")) {
+if (const Type *PT = getCurrentThisType().getTypePtrOrNull())
+  FoundDecl = PT->getPointeeType()->getAsTagDecl();
+  } else {
+LookupResult BaseResult(*this, &Context.Idents.get(Base), SourceLocation(),
+LookupOrdinaryName);
+if (LookupName(BaseResult, getCurScope()) && BaseResult.isSingleResult())
+  FoundDecl = BaseResult.getFoundDecl();
+  }
+
+  if (!FoundDecl)
 return true;
-  NamedDecl *FoundDecl = BaseResult.getFoundDecl();
+
   for (StringRef NextMember : Members) {
 const RecordType *RT = nullptr;
 if (VarDecl *VD = dyn_cast(FoundDecl))
   RT = VD->getType()->getAs();
 else if (TypedefNameDecl *TD = dyn_cast(FoundDecl)) {
   MarkAnyDeclReferenced(TD->getLocation(), TD, /*OdrUse=*/false);
-  RT = TD->getUnderlyingType()->getAs();
+  // MS InlineAsm often uses struct pointer aliases as a base
+  QualType QT = TD->getUnderlyingType();
+  if (const auto *PT = QT->getAs())
+QT = PT->getPointeeType();
+  RT = QT->getAs();
 } else if (TypeDecl *TD = dyn_cast(FoundDecl))
   RT = TD->getTypeForDecl()->getAs();
 else if (FieldDecl *TD = dyn_cast(FoundDecl))

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=310472&r1=310471&r2=310472&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Wed Aug  9 06:31:41 2017
@@ -527,7 +527,7 @@ void cpuid() {
 typedef struct {
   int a;
   int b;
-} A;
+} A, *pA;
 
 typedef struct {
   int b1;
@@ -539,7 +539,7 @@ typedef struct {
   A   c2;
   int c3;
   B   c4;
-} C;
+} C, *pC;
 
 void t39() {
 // CHECK-LABEL: define void @t39
@@ -547,6 +547,8 @@ void t39() {
 // CHECK: mov eax, [eax].4
   __asm mov eax, [eax] A.b
 // CHECK: mov eax, [eax] .4
+  __asm mov eax, [eax] pA.b
+// CHECK: mov eax, [eax] .4
   __asm mov eax, fs:[0] A.b
 // CHECK: mov eax, fs:[$$0] .4
   __asm mov eax, [eax].B.b2.a
@@ -557,6 +559,8 @@ void t39() {
 // CHECK: mov eax, fs:[$$0] .8
   __asm mov eax, [eax]C.c4.b2.b
 // CHECK: mov eax, [eax].24
+  __asm mov eax, [eax]pC.c4.b2.b
+// CHECK: mov eax, [eax].24
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.cpp?rev=310472&r1=310471&r2=310472&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.cpp (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.cpp Wed Aug  9 06:31:41 2017
@@ -180,3 +180,19 @@ void t8() {
   A::g();
 }
 
+void t9() {
+  // CHECK-LABEL: define void @_Z2t9v()
+  struct A {
+int a;
+int b;
+void g() {
+  __asm mov eax, dword ptr [eax]this.b
+  // CHECK: call void asm sideeffect inteldialect
+  // CHECK-SAME: mov eax, dword ptr [eax].4
+  // CHECK-SAME: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+}
+  };
+  A AA;
+  AA.g();
+}
+


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r310529 - [X86][Asm] Allow negative immediate to appear before bracketed expression

2017-08-09 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Wed Aug  9 14:50:22 2017
New Revision: 310529

URL: http://llvm.org/viewvc/llvm-project?rev=310529&view=rev
Log:
[X86][Asm] Allow negative immediate to appear before bracketed expression

Currently, only non-negative immediate is allowed prior to a brac expression 
(memory reference).
MASM / GAS does not have any problem cope with the left side of the real line, 
so we should be able to as well.

llvm: D36229

Differential Revision: https://reviews.llvm.org/D36230

Modified:
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=310529&r1=310528&r2=310529&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Wed Aug  9 14:50:22 2017
@@ -484,13 +484,13 @@ void t37() {
   __asm mov eax, (4 + 4) * 16
 // CHECK: mov eax, $$128
   __asm mov eax, 4 + 8 * -16
-// CHECK: mov eax, $$4294967172
+// CHECK: mov eax, $$-124
   __asm mov eax, 4 + 16 / -8
 // CHECK: mov eax, $$2
   __asm mov eax, (16 + 16) / -8
-// CHECK: mov eax, $$4294967292
+// CHECK: mov eax, $$-4
   __asm mov eax, ~15
-// CHECK: mov eax, $$4294967280
+// CHECK: mov eax, $$-16
   __asm mov eax, 6 ^ 3
 // CHECK: mov eax, $$5
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -655,6 +655,12 @@ void t45() {
   // CHECK: call void asm sideeffect inteldialect "mov dr0, eax\0A\09mov dr1, 
ebx\0A\09mov dr2, ebx\0A\09mov dr3, ecx\0A\09mov dr6, edx\0A\09mov dr7, ecx", 
"~{dr0},~{dr1},~{dr2},~{dr3},~{dr6},~{dr7},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t46() {
+  // CHECK-LABEL: define void @t46
+  __asm add eax, -128[eax]
+  // CHECK: call void asm sideeffect inteldialect "add eax, $$-128[eax]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
 // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


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r311640 - Fixups to FE tests affected by D36793

2017-08-24 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Thu Aug 24 01:47:26 2017
New Revision: 311640

URL: http://llvm.org/viewvc/llvm-project?rev=311640&view=rev
Log:
Fixups to FE tests affected by D36793

Differential Revision: https://reviews.llvm.org/D36794

Modified:
cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c
cfe/trunk/test/CodeGen/ms-inline-asm-64.c
cfe/trunk/test/CodeGen/ms-inline-asm.c
cfe/trunk/test/CodeGen/ms-inline-asm.cpp
cfe/trunk/test/CodeGenCXX/ms-inline-asm-return.cpp
cfe/trunk/test/Sema/ms-inline-asm.c

Modified: cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c?rev=311640&r1=311639&r2=311640&view=diff
==
--- cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/mozilla-ms-inline-asm.c Thu Aug 24 01:47:26 2017
@@ -33,7 +33,7 @@ void invoke(void* that, unsigned methodI
 // CHECK-SAME: push ecx
 // CHECK-SAME: mov edx,[ecx]
 // CHECK-SAME: mov eax,$4
-// CHECK-SAME: call dword ptr[edx+eax*$$4]
+// CHECK-SAME: call dword ptr[edx + eax * $$4]
 // CHECK-SAME: mov esp,ebp
 // CHECK-SAME: pop ebp
 // CHECK-SAME: ret

Modified: cfe/trunk/test/CodeGen/ms-inline-asm-64.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-64.c?rev=311640&r1=311639&r2=311640&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-64.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-64.c Thu Aug 24 01:47:26 2017
@@ -34,8 +34,8 @@ int t3() {
 // CHECK: t3
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: lea ebx, $0
-// CHECK-SAME: mov eax, [ebx].0
-// CHECK-SAME: mov [ebx].4, ecx
+// CHECK-SAME: mov eax, [ebx]
+// CHECK-SAME: mov [ebx + $$4], ecx
 // CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* 
%{{.*}})
 }
 
@@ -54,7 +54,7 @@ int t4() {
 // CHECK: t4
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: lea ebx, $0
-// CHECK-SAME: mov eax, [ebx].0
-// CHECK-SAME: mov [ebx].4, ecx
+// CHECK-SAME: mov eax, [ebx]
+// CHECK-SAME: mov [ebx + $$4], ecx
 // CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* 
%{{.*}})
 }

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=311640&r1=311639&r2=311640&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Thu Aug 24 01:47:26 2017
@@ -42,7 +42,7 @@ void t5(void) {
 void t6(void) {
   __asm int 0x2c
 // CHECK: t6
-// CHECK: call void asm sideeffect inteldialect "int $$0x2c", 
"~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", 
"~{dirflag},~{fpsr},~{flags}"()
 }
 
 void t7() {
@@ -61,7 +61,7 @@ void t7() {
 mov eax, ebx
   }
 // CHECK: t7
-// CHECK: call void asm sideeffect inteldialect "int $$0x2cU", 
"~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "int $$44", 
"~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", 
"~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "mov eax, ebx", 
"~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -94,7 +94,7 @@ void t9() {
 // CHECK: t9
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$0x07
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -229,7 +229,7 @@ void t20() {
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
   __asm mov eax, [eax + LENGTH foo * 4]
-// CHECK: mov eax, [eax + $$1 * $$4]
+// CHECK: mov eax, [eax + $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -240,7 +240,7 @@ void t20() {
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
   __asm mov eax, [eax + TYPE foo * 4]
-// CHECK: mov eax, [eax + $$4 * $$4]
+// CHECK: mov eax, [eax + $$16]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
@@ -249,7 +249,7 @@ void t20() {
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
   __asm mov eax, [eax + SIZE _foo * 4]
-// CHECK: mov eax, [eax + $$16 * $$4]
+// CHECK: mov eax, [eax + $$64]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
@@ -265,7 +265,7 @@ void t21() {
 // CHECK: t21
 // CHECK: call void asm sideeffect inteldialect
 // CHECK-SAME: push ebx
-// CHECK-SAME: mov ebx, $$07H
+// CHECK-SAME: mov ebx, $$7
 // CHECK-SAME: pop ebx
 // CHECK-SAME: "~{ebx},~{esp},~{dirflag},~{fpsr},~{flags}"()
 }
@@ -312,13 +312,13 @@ void t24() {
 void t25() {
 // CHECK: t25
   __asm mov eax, 0h
-// CHECK: mov eax, $$0h
+// CHECK: mov eax, $$4294967295
   __asm mov eax, 0fhU
 // CHECK: mov eax, $$15
   __asm mov eax, 0a2h
-// CHE

r311643 - [Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

2017-08-24 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Thu Aug 24 02:07:34 2017
New Revision: 311643

URL: http://llvm.org/viewvc/llvm-project?rev=311643&view=rev
Log:
[Clang][x86][Inline Asm] support for GCC style inline asm - Y constraints

This patch is intended to enable the use of basic double letter constraints 
used in GCC extended inline asm {Yi Y2 Yz Y0 Ym Yt}.
Supersedes D35205
llvm counterpart: D36369

Differential Revision: https://reviews.llvm.org/D36371

Added:
cfe/trunk/test/CodeGen/x86-GCC-inline-asm-Y-constraints.c   (with props)
Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/CodeGen/TargetInfo.cpp

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=311643&r1=311642&r2=311643&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Thu Aug 24 02:07:34 2017
@@ -1386,7 +1386,9 @@ bool X86TargetInfo::validateAsmConstrain
 switch (*Name) {
 default:
   return false;
+case 'z':
 case '0': // First SSE register.
+case '2':
 case 't': // Any SSE register, when SSE2 is enabled.
 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
 case 'm': // Any MMX register, when inter-unit moves enabled.
@@ -1455,33 +1457,39 @@ bool X86TargetInfo::validateOperandSize(
   case 't':
   case 'u':
 return Size <= 128;
-  case 'v':
-  case 'x':
-if (SSELevel >= AVX512F)
-  // 512-bit zmm registers can be used if target supports AVX512F.
-  return Size <= 512U;
-else if (SSELevel >= AVX)
-  // 256-bit ymm registers can be used if target supports AVX.
-  return Size <= 256U;
-return Size <= 128U;
   case 'Y':
 // 'Y' is the first character for several 2-character constraints.
 switch (Constraint[1]) {
 default:
-  break;
+  return false;
 case 'm':
   // 'Ym' is synonymous with 'y'.
 case 'k':
   return Size <= 64;
+case 'z':
+case '0':
+  // XMM0
+  if (SSELevel >= SSE1)
+return Size <= 128U;
+  return false;
 case 'i':
 case 't':
-  // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
-  if (SSELevel >= AVX512F)
-return Size <= 512U;
-  else if (SSELevel >= AVX)
-return Size <= 256U;
-  return SSELevel >= SSE2 && Size <= 128U;
+case '2':
+  // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
+  if (SSELevel < SSE2)
+return false;
+  break;
 }
+  case 'v':
+  case 'x':
+if (SSELevel >= AVX512F)
+  // 512-bit zmm registers can be used if target supports AVX512F.
+  return Size <= 512U;
+else if (SSELevel >= AVX)
+  // 256-bit ymm registers can be used if target supports AVX.
+  return Size <= 256U;
+return Size <= 128U;
+
   }
 
   return true;
@@ -1515,6 +1523,12 @@ std::string X86TargetInfo::convertConstr
   // the return string.
   break;
 case 'k':
+case 'm':
+case 'i':
+case 't':
+case 'z':
+case '0':
+case '2':
   // "^" hints llvm that this is a 2 letter constraint.
   // "Constraint++" is used to promote the string iterator
   // to the next constraint.

Modified: cfe/trunk/lib/Basic/Targets/X86.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.h?rev=311643&r1=311642&r2=311643&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.h (original)
+++ cfe/trunk/lib/Basic/Targets/X86.h Thu Aug 24 02:07:34 2017
@@ -437,9 +437,12 @@ public:
 // In case the constraint is 'r' we need to return Expression
 case 'r':
   return Expression;
+// Double letters Y constraints
+case 'Y':
+  if ((++I != E) && ((*I == '0') || (*I == 'z')))
+return "xmm0";
 default:
-  // Default value if there is no constraint for the register
-  return "";
+  break;
 }
 return "";
   }

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=311643&r1=311642&r2=311643&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Aug 24 02:07:34 2017
@@ -22,6 +22,7 @@
 #include "clang/CodeGen/SwiftCallingConv.h"
 #include "clang/Frontend/CodeGenOptions.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Type.h"
@@ -870,7 +871,10 @@ bool IsX86_MMXType(llvm::Type *IRType) {
 static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF,
   StringRef Constraint,
   llvm::Type* Ty

r318739 - [x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob

2017-11-21 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Tue Nov 21 00:50:10 2017
New Revision: 318739

URL: http://llvm.org/viewvc/llvm-project?rev=318739&view=rev
Log:
[x86][inline-asm] allow recognition of MPX regs inside ms inline-asm blob
Differential Revision: https://reviews.llvm.org/D38445

Modified:
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/lib/Basic/Targets/X86.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/X86.cpp?rev=318739&r1=318738&r2=318739&view=diff
==
--- cfe/trunk/lib/Basic/Targets/X86.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/X86.cpp Tue Nov 21 00:50:10 2017
@@ -60,6 +60,7 @@ static const char *const GCCRegNames[] =
 "k2","k3","k4","k5","k6",  "k7",
 "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
 "dr0",   "dr1",   "dr2",   "dr3",   "dr6", "dr7",
+"bnd0",  "bnd1",  "bnd2",  "bnd3",
 };
 
 const TargetInfo::AddlRegName AddlRegNames[] = {

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=318739&r1=318738&r2=318739&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Tue Nov 21 00:50:10 2017
@@ -661,6 +661,17 @@ void t46() {
   // CHECK: call void asm sideeffect inteldialect "add eax, [eax + $$-128]", 
"~{eax},~{flags},~{dirflag},~{fpsr},~{flags}"()
 }
 
+void t47() {
+  // CHECK-LABEL: define void @t47
+  __asm {
+bndmk bnd0, dword ptr [eax]
+bndmk bnd1, dword ptr [ebx]
+bndmk bnd2, dword ptr [ecx]
+bndmk bnd3, dword ptr [edx]
+  }
+  // CHECK: call void asm sideeffect inteldialect "bndmk bnd0, dword ptr 
[eax]\0A\09bndmk bnd1, dword ptr [ebx]\0A\09bndmk bnd2, dword ptr 
[ecx]\0A\09bndmk bnd3, dword ptr [edx]", 
"~{bnd0},~{bnd1},~{bnd2},~{bnd3},~{dirflag},~{fpsr},~{flags}"()
+}
+
 void dot_operator(){
   // CHECK-LABEL: define void @dot_operator
__asm { mov eax, 3[ebx]A.b}


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r298426 - [X86][MS-compatability][clang] allow MS TYPE/SIZE/LENGTH operators as a part of a compound expression

2017-03-21 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Tue Mar 21 14:33:32 2017
New Revision: 298426

URL: http://llvm.org/viewvc/llvm-project?rev=298426&view=rev
Log:
[X86][MS-compatability][clang] allow MS TYPE/SIZE/LENGTH operators as a part of 
a compound expression

This patch introduces X86AsmParser with the ability to handle the 
aforementioned ops within compound "MS" arithmetical expressions.
Currently - only supported as a stand alone Operand, e.g.:
"TYPE X"
now allowed :
"4 + TYPE X * 128"

LLVM side: https://reviews.llvm.org/D31173
Differential Revision: https://reviews.llvm.org/D31174

Modified:
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=298426&r1=298425&r2=298426&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Tue Mar 21 14:33:32 2017
@@ -201,6 +201,8 @@ void t20() {
 // CHECK: mov eax, $$4
   __asm mov eax, LENGTH _bar
 // CHECK: mov eax, $$2
+  __asm mov eax, [eax + LENGTH foo * 4]
+// CHECK: mov eax, [eax + $$1 * $$4]
 
   __asm mov eax, TYPE foo
 // CHECK: mov eax, $$4
@@ -210,6 +212,8 @@ void t20() {
 // CHECK: mov eax, $$4
   __asm mov eax, TYPE _bar
 // CHECK: mov eax, $$1
+  __asm mov eax, [eax + TYPE foo * 4]
+// CHECK: mov eax, [eax + $$4 * $$4]
 
   __asm mov eax, SIZE foo
 // CHECK: mov eax, $$4
@@ -217,9 +221,12 @@ void t20() {
 // CHECK: mov eax, $$1
   __asm mov eax, SIZE _foo
 // CHECK: mov eax, $$16
+  __asm mov eax, [eax + SIZE _foo * 4]
+// CHECK: mov eax, [eax + $$16 * $$4]
   __asm mov eax, SIZE _bar
 // CHECK: mov eax, $$2
 // CHECK: "~{eax},~{dirflag},~{fpsr},~{flags}"()
+
 }
 
 void t21() {


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r299454 - [X86][inline-asm] Add support for MS 'EVEN' directive

2017-04-04 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Tue Apr  4 12:58:28 2017
New Revision: 299454

URL: http://llvm.org/viewvc/llvm-project?rev=299454&view=rev
Log:
[X86][inline-asm] Add support for MS 'EVEN' directive

MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t 
'.even'.
This patch include the (small, simple) changes need to allow it.

llvm-side:
https://reviews.llvm.org/D27417

Differential Revision: https://reviews.llvm.org/D27418


Added:
cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c   (with props)

Added: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c?rev=299454&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c (added)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c Tue Apr  4 12:58:28 2017
@@ -0,0 +1,15 @@
+// RUN: %clang_cc1 %s -triple i386-unknown-unknown -fasm-blocks -emit-llvm -o 
- | FileCheck %s
+
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK: .byte 64
+// CHECK:  .even
+void t1() {
+  __asm {
+.byte 64
+.byte 64
+.byte 64
+EVEN
+mov eax, ebx
+  }
+}

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
--
svn:eol-style = native

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
--
svn:keywords = Author Date Id Rev URL

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
--
svn:mime-type = text/plain


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r299459 - [fixup][X86][inline-asm] Add support for MS 'EVEN' directive

2017-04-04 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Tue Apr  4 14:20:21 2017
New Revision: 299459

URL: http://llvm.org/viewvc/llvm-project?rev=299459&view=rev
Log:
[fixup][X86][inline-asm] Add support for MS 'EVEN' directive

refining tested targets resolution, to amend failures caused by rL299454

Modified:
cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c

Modified: cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c?rev=299459&r1=299458&r2=299459&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-EVEN.c Tue Apr  4 14:20:21 2017
@@ -1,4 +1,5 @@
-// RUN: %clang_cc1 %s -triple i386-unknown-unknown -fasm-blocks -emit-llvm -o 
- | FileCheck %s
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - 
| FileCheck %s
 
 // CHECK: .byte 64
 // CHECK: .byte 64


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r294120 - [X86][MS]Adjacent comments within multi-line inline assembly statement

2017-02-05 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Sun Feb  5 04:23:06 2017
New Revision: 294120

URL: http://llvm.org/viewvc/llvm-project?rev=294120&view=rev
Log:
[X86][MS]Adjacent comments within multi-line inline assembly statement

Allowing adjacent comments within MS inline assembly multi-line statement

Differential Revision: https://reviews.llvm.org/D28989


Modified:
cfe/trunk/lib/Parse/ParseStmtAsm.cpp
cfe/trunk/test/CodeGen/ms-inline-asm.c

Modified: cfe/trunk/lib/Parse/ParseStmtAsm.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Parse/ParseStmtAsm.cpp?rev=294120&r1=294119&r2=294120&view=diff
==
--- cfe/trunk/lib/Parse/ParseStmtAsm.cpp (original)
+++ cfe/trunk/lib/Parse/ParseStmtAsm.cpp Sun Feb  5 04:23:06 2017
@@ -457,6 +457,11 @@ StmtResult Parser::ParseMicrosoftAsmStat
 break;
   LineNo = SrcMgr.getLineNumber(ExpLoc.first, ExpLoc.second);
   SkippedStartOfLine = Tok.isAtStartOfLine();
+} else if (Tok.is(tok::semi)) {
+  // A multi-line asm-statement, where next line is a comment
+  InAsmComment = true;
+  FID = ExpLoc.first;
+  LineNo = SrcMgr.getLineNumber(FID, ExpLoc.second);
 }
   } else if (!InAsmComment && Tok.is(tok::r_brace)) {
 // In MSVC mode, braces only participate in brace matching and

Modified: cfe/trunk/test/CodeGen/ms-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm.c?rev=294120&r1=294119&r2=294120&view=diff
==
--- cfe/trunk/test/CodeGen/ms-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/ms-inline-asm.c Sun Feb  5 04:23:06 2017
@@ -55,9 +55,15 @@ void t7() {
 }
   }
   __asm {}
+  __asm {
+;
+; label
+mov eax, ebx
+  }
 // CHECK: t7
 // CHECK: call void asm sideeffect inteldialect "int $$0x2cU", 
"~{dirflag},~{fpsr},~{flags}"()
 // CHECK: call void asm sideeffect inteldialect "", 
"~{dirflag},~{fpsr},~{flags}"()
+// CHECK: call void asm sideeffect inteldialect "mov eax, ebx", 
"~{eax},~{dirflag},~{fpsr},~{flags}"()
 }
 
 int t8() {


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r308867 - [X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the two collides

2017-07-24 Thread Coby Tayree via cfe-commits 
Author: coby
Date: Mon Jul 24 00:06:37 2017
New Revision: 308867

URL: http://llvm.org/viewvc/llvm-project?rev=308867&view=rev
Log:
[X86][InlineAsm][Ms Compatibility]Prefer variable name over a register when the 
two collides

On MS-style, the following snippet:

int eax;
__asm mov eax, ebx

should yield loading of ebx, into the location pointed by the variable eax

This patch sees to it.

Currently, a reg-to-reg move would have been invoked.

llvm: D34739

Differential Revision: https://reviews.llvm.org/D34740

Added:
cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c   (with props)

Added: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c?rev=308867&view=auto
==
--- cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c (added)
+++ cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c Mon Jul 24 00:06:37 2017
@@ -0,0 +1,12 @@
+// REQUIRES: x86-registered-target
+// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - 
| FileCheck %s
+
+void t() {
+  int eax;
+  int Ecx;
+  __asm mov eax, ebx
+  // CHECK: mov $0, ebx
+  __asm add ecx, Ecx
+  // CHECK: add ecx, $1
+}
+

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
--
svn:eol-style = native

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
--
svn:keywords = Author Date Id Rev URL

Propchange: cfe/trunk/test/CodeGen/ms-inline-asm-var-name.c
--
svn:mime-type = text/plain


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