from:"Andrew Jeffery via cfe\-commits"

[PATCH v3] [PPC64]: Add support for Swift calling convention

2017-06-21 Thread Andrew Jeffery via cfe-commits

For the tests I've extracted the int5 and int8 cases to cater for
different alignments for different platform ABIs. For Linux on POWER the
5 and 8 element vectors must be naturally aligned with respect to the
total "soft" vector size, despite being represented as an aggregate.
Specifically, the patch caters for the following differences in
supporting powerpc64le-unknown-linux:

   $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
   --- test/CodeGen/64bit-swiftcall.c   2017-04-20 17:14:59.797963820 +0930
   +++ test/CodeGen/ppc64-swiftcall.c   2017-04-20 17:15:11.621965118 +0930
   @@ -1,7 +1,6 @@
   -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
-emit-llvm -o - %s | FileCheck %s
   -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm 
-o - %s | FileCheck %s
   +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - %s | 
FileCheck %s

   -// REQUIRES: aarch64-registered-target,x86-registered-target
   +// REQUIRES: powerpc-registered-target

#define SWIFTCALL __attribute__((swiftcall))
#define OUT __attribute__((swift_indirect_result))
   @@ -370,8 +369,8 @@

TEST(int8)
// CHECK-LABEL: define {{.*}} @return_int8()
   -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
   +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
// CHECK:   [[VAR:%.*]] = alloca [[REC]], align
// CHECK:   store
// CHECK:   load
// CHECK:   store
   @@ -414,8 +413,8 @@

TEST(int5)
// CHECK-LABEL: define {{.*}} @return_int5()
   -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
   +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
// CHECK:   [[VAR:%.*]] = alloca [[REC]], align
// CHECK:   store
// CHECK:   load
// CHECK:   store

Despite some duplication, the advantage of this approach over using
pattern matching for alignment in 64bit-swiftcall.c is that we ensure
each platform is using the expected alignment but without duplicating
the entirety of 64bit-swiftcall.c.

Signed-off-by: Andrew Jeffery 
---

Hello,

The only change in v3 is rebasing it on top upstream HEAD, fixing a conflict in
one of the lit REQUIRES lines.

Ulrich, Hal, Bill: I've Cc'ed you as you were fingered by the blame output. As
some background I sent the patch several months ago but it hasn't got much
traction aside from a LGTM from Adrian (thanks!). I'm hoping it gets a bit more
attention as without it we get build failures for Swift on POWER, which is
in-turn blocking some CI efforts. 

Cheers,

Andrew

 lib/Basic/Targets.cpp |  11 ++
 lib/CodeGen/TargetInfo.cpp|  14 ++-
 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 ++
 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 +
 test/CodeGen/64bit-swiftcall.c|  93 +
 5 files changed, 258 insertions(+), 93 deletions(-)
 create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
 create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index e23a93e..54b5911 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1753,6 +1753,17 @@ public:
 }
 return false;
   }
+
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
+switch (CC) {
+case CC_C:
+case CC_Swift:
+return CCCR_OK;
+default:
+break;
+}
+return CCCR_Warning;
+  }
 };
 
 class DarwinPPC32TargetInfo : public DarwinTargetInfo {
diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
index 8d00e05..a82cd24 100644
--- a/lib/CodeGen/TargetInfo.cpp
+++ b/lib/CodeGen/TargetInfo.cpp
@@ -4179,7 +4179,7 @@ 
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
 
 namespace {
 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
-class PPC64_SVR4_ABIInfo : public ABIInfo {
+class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
 public:
   enum ABIKind {
 ELFv1 = 0,
@@ -4223,7 +4223,7 @@ private:
 public:
   PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
  bool SoftFloatABI)
-  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
+  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
 IsSoftFloatABI(SoftFloatABI) {}
 
   bool isPromotableTypeForABI(QualType Ty) const;
@@ -4266,6 +4266,16 @@ public:
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
+
+  bool isSwiftErrorInRegister() const override {
+return true;
+  }
 };
 
 class PPC64_SVR4_TargetCodeGenInfo : publ

[PATCH] [PPC64]: Add support for Swift calling convention

2017-03-22 Thread Andrew Jeffery via cfe-commits

Signed-off-by: Andrew Jeffery 
---
 lib/Basic/Targets.cpp  | 11 +++
 lib/CodeGen/TargetInfo.cpp | 14 --
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index fdedd91a3e15..6d7f37f2479a 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1708,6 +1708,17 @@ public:
 }
 return false;
   }
+
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
+switch (CC) {
+case CC_C:
+case CC_Swift:
+return CCCR_OK;
+default:
+break;
+}
+return CCCR_Warning;
+  }
 };
 
 class DarwinPPC32TargetInfo : public DarwinTargetInfo {
diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
index d2fc3888ef29..6193f6c4ac29 100644
--- a/lib/CodeGen/TargetInfo.cpp
+++ b/lib/CodeGen/TargetInfo.cpp
@@ -4175,7 +4175,7 @@ 
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
 
 namespace {
 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
-class PPC64_SVR4_ABIInfo : public ABIInfo {
+class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
 public:
   enum ABIKind {
 ELFv1 = 0,
@@ -4219,7 +4219,7 @@ private:
 public:
   PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
  bool SoftFloatABI)
-  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
+  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
 IsSoftFloatABI(SoftFloatABI) {}
 
   bool isPromotableTypeForABI(QualType Ty) const;
@@ -4262,6 +4262,16 @@ public:
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
+
+  bool isSwiftErrorInRegister() const override {
+return true;
+  }
 };
 
 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
-- 
2.9.3

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Re: [PATCH] [PPC64]: Add support for Swift calling convention

2017-04-05 Thread Andrew Jeffery via cfe-commits

Ping - Is anyone happy to review or apply the patch?

If I've missed some process I should have followed, please let me know!

Andrew

On Wed, 2017-03-22 at 22:30 +1030, Andrew Jeffery wrote:
> Signed-off-by: Andrew Jeffery 
> ---
>  lib/Basic/Targets.cpp  | 11 +++
>  lib/CodeGen/TargetInfo.cpp | 14 --
>  2 files changed, 23 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> index fdedd91a3e15..6d7f37f2479a 100644
> --- a/lib/Basic/Targets.cpp
> +++ b/lib/Basic/Targets.cpp
> @@ -1708,6 +1708,17 @@ public:
>  }
>  return false;
>    }
> +
> +  CallingConvCheckResult checkCallingConvention(CallingConv CC)
> const override {
> +switch (CC) {
> +case CC_C:
> +case CC_Swift:
> +return CCCR_OK;
> +default:
> +break;
> +}
> +return CCCR_Warning;
> +  }
>  };
>  
>  class DarwinPPC32TargetInfo : public
> DarwinTargetInfo {
> diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> index d2fc3888ef29..6193f6c4ac29 100644
> --- a/lib/CodeGen/TargetInfo.cpp
> +++ b/lib/CodeGen/TargetInfo.cpp
> @@ -4175,7 +4175,7 @@
> PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunct
> ion &CGF,
>  
>  namespace {
>  /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI
> information.
> -class PPC64_SVR4_ABIInfo : public ABIInfo {
> +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
>  public:
>    enum ABIKind {
>  ELFv1 = 0,
> @@ -4219,7 +4219,7 @@ private:
>  public:
>    PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool
> HasQPX,
>   bool SoftFloatABI)
> -  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
> +  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
>  IsSoftFloatABI(SoftFloatABI) {}
>  
>    bool isPromotableTypeForABI(QualType Ty) const;
> @@ -4262,6 +4262,16 @@ public:
>  
>    Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
>  QualType Ty) const override;
> +
> +  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
> +ArrayRef scalars,
> +bool asReturnValue) const
> override {
> +return occupiesMoreThan(CGT, scalars, /*total*/ 4);
> +  }
> +
> +  bool isSwiftErrorInRegister() const override {
> +return true;
> +  }
>  };
>  
>  class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {

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Re: [PATCH] [PPC64]: Add support for Swift calling convention

2017-04-12 Thread Andrew Jeffery via cfe-commits

On Wed, 2017-04-12 at 14:01 -0700, Adrian Prantl wrote:
> Is it possible to add a testcase for this?

I will look into it.

Thanks for the review!

Andrew

> 
> -- adrian
> 
> 
> > On Mar 22, 2017, at 5:00 AM, Andrew Jeffery via cfe-commits 
> >  wrote:
> > 
> > > > Signed-off-by: Andrew Jeffery 
> > ---
> > lib/Basic/Targets.cpp  | 11 +++
> > lib/CodeGen/TargetInfo.cpp | 14 --
> > 2 files changed, 23 insertions(+), 2 deletions(-)
> > 
> > diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> > index fdedd91a3e15..6d7f37f2479a 100644
> > --- a/lib/Basic/Targets.cpp
> > +++ b/lib/Basic/Targets.cpp
> > @@ -1708,6 +1708,17 @@ public:
> > }
> > return false;
> >   }
> > +
> > +  CallingConvCheckResult checkCallingConvention(CallingConv CC) const 
> > override {
> > +switch (CC) {
> > +case CC_C:
> > +case CC_Swift:
> > +return CCCR_OK;
> > +default:
> > +break;
> > +}
> > +return CCCR_Warning;
> > +  }
> > };
> > 
> > class DarwinPPC32TargetInfo : public DarwinTargetInfo {
> > diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> > index d2fc3888ef29..6193f6c4ac29 100644
> > --- a/lib/CodeGen/TargetInfo.cpp
> > +++ b/lib/CodeGen/TargetInfo.cpp
> > @@ -4175,7 +4175,7 @@ 
> > PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction 
> > &CGF,
> > 
> > namespace {
> > /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
> > -class PPC64_SVR4_ABIInfo : public ABIInfo {
> > +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
> > public:
> >   enum ABIKind {
> > ELFv1 = 0,
> > @@ -4219,7 +4219,7 @@ private:
> > public:
> >   PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
> >  bool SoftFloatABI)
> > -  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
> > +  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
> > IsSoftFloatABI(SoftFloatABI) {}
> > 
> >   bool isPromotableTypeForABI(QualType Ty) const;
> > @@ -4262,6 +4262,16 @@ public:
> > 
> >   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
> > QualType Ty) const override;
> > +
> > +  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
> > +ArrayRef scalars,
> > +bool asReturnValue) const override {
> > +return occupiesMoreThan(CGT, scalars, /*total*/ 4);
> > +  }
> > +
> > +  bool isSwiftErrorInRegister() const override {
> > +return true;
> > +  }
> > };
> > 
> > class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
> > -- 
> > 2.9.3
> > 
> > ___
> > cfe-commits mailing list
> > cfe-commits@lists.llvm.org
> > http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
> 
> 

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Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

2017-07-05 Thread Andrew Jeffery via cfe-commits

Ping - is anyone able to provide feedback?

Cheers,

Andrew

On Thu, 2017-06-22 at 16:02 +0930, Andrew Jeffery wrote:
> For the tests I've extracted the int5 and int8 cases to cater for
> different alignments for different platform ABIs. For Linux on POWER the
> 5 and 8 element vectors must be naturally aligned with respect to the
> total "soft" vector size, despite being represented as an aggregate.
> Specifically, the patch caters for the following differences in
> supporting powerpc64le-unknown-linux:
> 
>    $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
> >    --- test/CodeGen/64bit-swiftcall.c   2017-04-20 17:14:59.797963820 
> > +0930
> >    +++ test/CodeGen/ppc64-swiftcall.c   2017-04-20 17:15:11.621965118 
> > +0930
>    @@ -1,7 +1,6 @@
>    -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
> -emit-llvm -o - %s | FileCheck %s
>    -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone 
> -emit-llvm -o - %s | FileCheck %s
>    +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - %s | 
> FileCheck %s
> 
>    -// REQUIRES: aarch64-registered-target,x86-registered-target
>    +// REQUIRES: powerpc-registered-target
> 
> #define SWIFTCALL __attribute__((swiftcall))
> #define OUT __attribute__((swift_indirect_result))
>    @@ -370,8 +369,8 @@
> 
> TEST(int8)
> // CHECK-LABEL: define {{.*}} @return_int8()
>    -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
>    +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
> // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> // CHECK:   store
> // CHECK:   load
> // CHECK:   store
>    @@ -414,8 +413,8 @@
> 
> TEST(int5)
> // CHECK-LABEL: define {{.*}} @return_int5()
>    -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
>    +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
> // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> // CHECK:   store
> // CHECK:   load
> // CHECK:   store
> 
> Despite some duplication, the advantage of this approach over using
> pattern matching for alignment in 64bit-swiftcall.c is that we ensure
> each platform is using the expected alignment but without duplicating
> the entirety of 64bit-swiftcall.c.
> 
> > Signed-off-by: Andrew Jeffery 
> ---
> 
> Hello,
> 
> The only change in v3 is rebasing it on top upstream HEAD, fixing a conflict 
> in
> one of the lit REQUIRES lines.
> 
> Ulrich, Hal, Bill: I've Cc'ed you as you were fingered by the blame output. As
> some background I sent the patch several months ago but it hasn't got much
> traction aside from a LGTM from Adrian (thanks!). I'm hoping it gets a bit 
> more
> attention as without it we get build failures for Swift on POWER, which is
> in-turn blocking some CI efforts. 
> 
> Cheers,
> 
> Andrew
> 
>  lib/Basic/Targets.cpp |  11 ++
>  lib/CodeGen/TargetInfo.cpp|  14 ++-
>  test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 
> ++
>  test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 +
>  test/CodeGen/64bit-swiftcall.c|  93 +
>  5 files changed, 258 insertions(+), 93 deletions(-)
>  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
>  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c
> 
> diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> index e23a93e..54b5911 100644
> --- a/lib/Basic/Targets.cpp
> +++ b/lib/Basic/Targets.cpp
> @@ -1753,6 +1753,17 @@ public:
>  }
>  return false;
>    }
> +
> +  CallingConvCheckResult checkCallingConvention(CallingConv CC) const 
> override {
> +switch (CC) {
> +case CC_C:
> +case CC_Swift:
> +return CCCR_OK;
> +default:
> +break;
> +}
> +return CCCR_Warning;
> +  }
>  };
>  
>  class DarwinPPC32TargetInfo : public DarwinTargetInfo {
> diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> index 8d00e05..a82cd24 100644
> --- a/lib/CodeGen/TargetInfo.cpp
> +++ b/lib/CodeGen/TargetInfo.cpp
> @@ -4179,7 +4179,7 @@ 
> PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
>  
>  namespace {
>  /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
> -class PPC64_SVR4_ABIInfo : public ABIInfo {
> +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
>  public:
>    enum ABIKind {
>  ELFv1 = 0,
> @@ -4223,7 +4223,7 @@ private:
>  public:
>    PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
>   bool SoftFloatABI)
> -  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
> +  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
>  IsSoftFloatABI(SoftFloatABI) {}
>  
>    bool isPromotableTypeForABI(QualType Ty) const;
> @@ -4266,6 +4266,16 @@ public:
>  
>    Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
>

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

2017-07-18 Thread Andrew Jeffery via cfe-commits

Another friendly ping :)

Cheers,

Andrew

On Wed, 2017-07-05 at 11:23 +0930, Andrew Jeffery wrote:
> Ping - is anyone able to provide feedback?
> 
> Cheers,
> 
> Andrew
> 
> On Thu, 2017-06-22 at 16:02 +0930, Andrew Jeffery wrote:
> > For the tests I've extracted the int5 and int8 cases to cater for
> > different alignments for different platform ABIs. For Linux on
> > POWER the
> > 5 and 8 element vectors must be naturally aligned with respect to
> > the
> > total "soft" vector size, despite being represented as an
> > aggregate.
> > Specifically, the patch caters for the following differences in
> > supporting powerpc64le-unknown-linux:
> > 
> >    $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-
> > swiftcall.c
> > >    --- test/CodeGen/64bit-swiftcall.c 2017-04-20
> > > 17:14:59.797963820 +0930
> > >    +++ test/CodeGen/ppc64-swiftcall.c 2017-04-20
> > > 17:15:11.621965118 +0930
> > 
> >    @@ -1,7 +1,6 @@
> >    -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu
> > core2 -emit-llvm -o - %s | FileCheck %s
> >    -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone
> > -emit-llvm -o - %s | FileCheck %s
> >    +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm 
> > -o - %s | FileCheck %s
> > 
> >    -// REQUIRES: aarch64-registered-target,x86-registered-target
> >    +// REQUIRES: powerpc-registered-target
> > 
> > #define SWIFTCALL __attribute__((swiftcall))
> > #define OUT __attribute__((swift_indirect_result))
> >    @@ -370,8 +369,8 @@
> > 
> > TEST(int8)
> > // CHECK-LABEL: define {{.*}} @return_int8()
> >    -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
> >    +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
> > // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> > // CHECK:   store
> > // CHECK:   load
> > // CHECK:   store
> >    @@ -414,8 +413,8 @@
> > 
> > TEST(int5)
> > // CHECK-LABEL: define {{.*}} @return_int5()
> >    -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
> >    +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
> > // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> > // CHECK:   store
> > // CHECK:   load
> > // CHECK:   store
> > 
> > Despite some duplication, the advantage of this approach over using
> > pattern matching for alignment in 64bit-swiftcall.c is that we
> > ensure
> > each platform is using the expected alignment but without
> > duplicating
> > the entirety of 64bit-swiftcall.c.
> > 
> > > Signed-off-by: Andrew Jeffery 
> > 
> > ---
> > 
> > Hello,
> > 
> > The only change in v3 is rebasing it on top upstream HEAD, fixing a
> > conflict in
> > one of the lit REQUIRES lines.
> > 
> > Ulrich, Hal, Bill: I've Cc'ed you as you were fingered by the blame
> > output. As
> > some background I sent the patch several months ago but it hasn't
> > got much
> > traction aside from a LGTM from Adrian (thanks!). I'm hoping it
> > gets a bit more
> > attention as without it we get build failures for Swift on POWER,
> > which is
> > in-turn blocking some CI efforts. 
> > 
> > Cheers,
> > 
> > Andrew
> > 
> >  lib/Basic/Targets.cpp |  11 ++
> >  lib/CodeGen/TargetInfo.cpp|  14 ++-
> >  test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117
> > ++
> >  test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116
> > +
> >  test/CodeGen/64bit-swiftcall.c|  93 +-
> > ---
> >  5 files changed, 258 insertions(+), 93 deletions(-)
> >  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-
> > align16.c
> >  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-
> > align32.c
> > 
> > diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> > index e23a93e..54b5911 100644
> > --- a/lib/Basic/Targets.cpp
> > +++ b/lib/Basic/Targets.cpp
> > @@ -1753,6 +1753,17 @@ public:
> >  }
> >  return false;
> >    }
> > +
> > +  CallingConvCheckResult checkCallingConvention(CallingConv CC)
> > const override {
> > +switch (CC) {
> > +case CC_C:
> > +case CC_Swift:
> > +return CCCR_OK;
> > +default:
> > +break;
> > +}
> > +return CCCR_Warning;
> > +  }
> >  };
> >  
> >  class DarwinPPC32TargetInfo : public
> > DarwinTargetInfo {
> > diff --git a/lib/CodeGen/TargetInfo.cpp
> > b/lib/CodeGen/TargetInfo.cpp
> > index 8d00e05..a82cd24 100644
> > --- a/lib/CodeGen/TargetInfo.cpp
> > +++ b/lib/CodeGen/TargetInfo.cpp
> > @@ -4179,7 +4179,7 @@
> > PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFun
> > ction &CGF,
> >  
> >  namespace {
> >  /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI
> > information.
> > -class PPC64_SVR4_ABIInfo : public ABIInfo {
> > +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
> >  public:
> >    enum ABIKind {
> >  ELFv1 = 0,
> > @@ -4223,7 +4223,7 @@ private:
> >  public:
> >    PPC64_SVR4_ABIInfo(CodeGen:

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

2017-07-23 Thread Andrew Jeffery via cfe-commits

On Wed, 2017-07-19 at 08:26 -0700, Adrian Prantl wrote:
> > > > On Jun 21, 2017, at 11:32 PM, Andrew Jeffery  wrote:
> > 
> > For the tests I've extracted the int5 and int8 cases to cater for
> > different alignments for different platform ABIs. For Linux on POWER the
> > 5 and 8 element vectors must be naturally aligned with respect to the
> > total "soft" vector size, despite being represented as an aggregate.
> > Specifically, the patch caters for the following differences in
> > supporting powerpc64le-unknown-linux:
> > 
> >   $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
> > > >   --- test/CodeGen/64bit-swiftcall.c2017-04-20 17:14:59.797963820 
> > > > +0930
> > > >   +++ test/CodeGen/ppc64-swiftcall.c2017-04-20 17:15:11.621965118 
> > > > +0930
> >   @@ -1,7 +1,6 @@
> >   -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
> > -emit-llvm -o - %s | FileCheck %s
> >   -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone 
> > -emit-llvm -o - %s | FileCheck %s
> >   +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - %s 
> > | FileCheck %s
> > 
> >   -// REQUIRES: aarch64-registered-target,x86-registered-target
> >   +// REQUIRES: powerpc-registered-target
> > 
> >    #define SWIFTCALL __attribute__((swiftcall))
> >    #define OUT __attribute__((swift_indirect_result))
> >   @@ -370,8 +369,8 @@
> > 
> >    TEST(int8)
> >    // CHECK-LABEL: define {{.*}} @return_int8()
> >   -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
> >   +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
> >    // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> >    // CHECK:   store
> >    // CHECK:   load
> >    // CHECK:   store
> >   @@ -414,8 +413,8 @@
> > 
> >    TEST(int5)
> >    // CHECK-LABEL: define {{.*}} @return_int5()
> >   -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
> >   +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
> >    // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> >    // CHECK:   store
> >    // CHECK:   load
> >    // CHECK:   store
> > 
> > Despite some duplication, the advantage of this approach over using
> > pattern matching for alignment in 64bit-swiftcall.c is that we ensure
> > each platform is using the expected alignment but without duplicating
> > the entirety of 64bit-swiftcall.c.
> 
> You could also write all in one file and use invoke FileCheck with 
> --check-prefix=CHECK-PPC64 to have a second set of CHECK-lines in the same 
> input file.
> 

Ah, interesting. That's probably worth a respin.

Thanks for the feedback.

Andrew

> -- adrian
> > 
> > > > Signed-off-by: Andrew Jeffery 
> > ---
> > 
> > Hello,
> > 
> > The only change in v3 is rebasing it on top upstream HEAD, fixing a 
> > conflict in
> > one of the lit REQUIRES lines.
> > 
> > Ulrich, Hal, Bill: I've Cc'ed you as you were fingered by the blame output. 
> > As
> > some background I sent the patch several months ago but it hasn't got much
> > traction aside from a LGTM from Adrian (thanks!). I'm hoping it gets a bit 
> > more
> > attention as without it we get build failures for Swift on POWER, which is
> > in-turn blocking some CI efforts. 
> > 
> > Cheers,
> > 
> > Andrew
> > 
> > lib/Basic/Targets.cpp |  11 ++
> > lib/CodeGen/TargetInfo.cpp|  14 ++-
> > test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 
> > ++
> > test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 
> > +
> > test/CodeGen/64bit-swiftcall.c|  93 +
> > 5 files changed, 258 insertions(+), 93 deletions(-)
> > create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
> > create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c
> > 
> > diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> > index e23a93e..54b5911 100644
> > --- a/lib/Basic/Targets.cpp
> > +++ b/lib/Basic/Targets.cpp
> > @@ -1753,6 +1753,17 @@ public:
> > }
> > return false;
> >   }
> > +
> > +  CallingConvCheckResult checkCallingConvention(CallingConv CC) const 
> > override {
> > +switch (CC) {
> > +case CC_C:
> > +case CC_Swift:
> > +return CCCR_OK;
> > +default:
> > +break;
> > +}
> > +return CCCR_Warning;
> > +  }
> > };
> > 
> > class DarwinPPC32TargetInfo : public DarwinTargetInfo {
> > diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> > index 8d00e05..a82cd24 100644
> > --- a/lib/CodeGen/TargetInfo.cpp
> > +++ b/lib/CodeGen/TargetInfo.cpp
> > @@ -4179,7 +4179,7 @@ 
> > PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction 
> > &CGF,
> > 
> > namespace {
> > /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
> > -class PPC64_SVR4_ABIInfo : public ABIInfo {
> > +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
> > public:
> >   enum ABIKind {
> > ELFv1 = 0,
> > @@ -4223,7 +4223,7 @@ p

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

2017-07-23 Thread Andrew Jeffery via cfe-commits

Hi Hal,

On Sat, 2017-07-22 at 23:26 -0500, Hal Finkel wrote:
> On 07/19/2017 10:26 AM, Adrian Prantl wrote:
> > > > > > On Jun 21, 2017, at 11:32 PM, Andrew Jeffery  
> > > > > > wrote:
> > > 
> > > For the tests I've extracted the int5 and int8 cases to cater for
> > > different alignments for different platform ABIs. For Linux on POWER the
> > > 5 and 8 element vectors must be naturally aligned with respect to the
> > > total "soft" vector size, despite being represented as an aggregate.
> > > Specifically, the patch caters for the following differences in
> > > supporting powerpc64le-unknown-linux:
> > > 
> > >    $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
> > > > > >    --- test/CodeGen/64bit-swiftcall.c   2017-04-20 
> > > > > > 17:14:59.797963820 +0930
> > > > > >    +++ test/CodeGen/ppc64-swiftcall.c   2017-04-20 
> > > > > > 17:15:11.621965118 +0930
> > >    @@ -1,7 +1,6 @@
> > >    -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
> > > -emit-llvm -o - %s | FileCheck %s
> > >    -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone 
> > > -emit-llvm -o - %s | FileCheck %s
> > >    +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - 
> > > %s | FileCheck %s
> > > 
> > >    -// REQUIRES: aarch64-registered-target,x86-registered-target
> > >    +// REQUIRES: powerpc-registered-target
> > > 
> > > #define SWIFTCALL __attribute__((swiftcall))
> > > #define OUT __attribute__((swift_indirect_result))
> > >    @@ -370,8 +369,8 @@
> > > 
> > > TEST(int8)
> > > // CHECK-LABEL: define {{.*}} @return_int8()
> > >    -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
> > >    +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
> > > // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> > > // CHECK:   store
> > > // CHECK:   load
> > > // CHECK:   store
> > >    @@ -414,8 +413,8 @@
> > > 
> > > TEST(int5)
> > > // CHECK-LABEL: define {{.*}} @return_int5()
> > >    -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
> > >    +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
> > > // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> > > // CHECK:   store
> > > // CHECK:   load
> > > // CHECK:   store
> > > 
> > > Despite some duplication, the advantage of this approach over using
> > > pattern matching for alignment in 64bit-swiftcall.c is that we ensure
> > > each platform is using the expected alignment but without duplicating
> > > the entirety of 64bit-swiftcall.c.
> > 
> > You could also write all in one file and use invoke FileCheck with 
> > --check-prefix=CHECK-PPC64 to have a second set of CHECK-lines in the same 
> > input file.
> > 
> > -- adrian
> > > > > > Signed-off-by: Andrew Jeffery 
> > > ---
> > > 
> > > Hello,
> > > 
> > > The only change in v3 is rebasing it on top upstream HEAD, fixing a 
> > > conflict in
> > > one of the lit REQUIRES lines.
> > > 
> > > Ulrich, Hal, Bill: I've Cc'ed you as you were fingered by the blame 
> > > output. As
> > > some background I sent the patch several months ago but it hasn't got much
> > > traction aside from a LGTM from Adrian (thanks!). I'm hoping it gets a 
> > > bit more
> > > attention as without it we get build failures for Swift on POWER, which is
> > > in-turn blocking some CI efforts.
> > > 
> > > Cheers,
> > > 
> > > Andrew
> > > 
> > > lib/Basic/Targets.cpp |  11 ++
> > > lib/CodeGen/TargetInfo.cpp|  14 ++-
> > > test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 
> > > ++
> > > test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 
> > > +
> > > test/CodeGen/64bit-swiftcall.c|  93 +
> > > 5 files changed, 258 insertions(+), 93 deletions(-)
> > > create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
> > > create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c
> > > 
> > > diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> > > index e23a93e..54b5911 100644
> > > --- a/lib/Basic/Targets.cpp
> > > +++ b/lib/Basic/Targets.cpp
> > > @@ -1753,6 +1753,17 @@ public:
> > >  }
> > >  return false;
> > >    }
> > > +
> > > +  CallingConvCheckResult checkCallingConvention(CallingConv CC) const 
> > > override {
> > > +switch (CC) {
> > > +case CC_C:
> > > +case CC_Swift:
> > > +return CCCR_OK;
> > > +default:
> > > +break;
> > > +}
> > > +return CCCR_Warning;
> > > +  }
> > > };
> > > 
> > > class DarwinPPC32TargetInfo : public DarwinTargetInfo {
> > > diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> > > index 8d00e05..a82cd24 100644
> > > --- a/lib/CodeGen/TargetInfo.cpp
> > > +++ b/lib/CodeGen/TargetInfo.cpp
> > > @@ -4179,7 +4179,7 @@ 
> > > PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction 
> > > &CGF,
> > > 
> > > n

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

2017-07-24 Thread Andrew Jeffery via cfe-commits

On Mon, 2017-07-24 at 09:32 +0200, Ulrich Weigand wrote:
> > Andrew Jeffery  wrote on 24.07.2017 03:54:05:
> 
> > > > > +  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
> > > > > +ArrayRef scalars,
> > > > > +bool asReturnValue) 
> > > > > constoverride {
> > > > > +return occupiesMoreThan(CGT, scalars, /*total*/ 4);
> > > 
> > > I don't know much about Swift; the code changes seem reasonable. One 
> > > question I have is: from where does this number 4 come? Is there some 
> > > corresponding patch to Swift that this matches?
> > 
> > As far as I'm aware a patch to Swift is not necessary, rather 4 comes
> > from Ulrich's '[PowerPC] Support multiple return values with fast isel'
> > patch[1] which allows up to 4 values to be returned in registers.
> > 
> > To give some confidence, with this patch Swift builds and the tests
> > pass for PPC64 on PPC64. Looking at the other implementations of
> > shouldPassIndirectlyForSwift() none of them seem to have behaviour
> > dependent on asReturnValue, however must say I'm not certain about the
> > false (argument) case. Maybe Ulrich can provide some insight?
> 
> That LLVM back-end patch simply *allows* front-ends to return integers
> in up to 4 registers.  (I did this because Anton Blanchard pointed out
> in PR 26190 that Swift at that time wanted to return three values in
> registers.)  The choice of 4 here is somewhat arbitrary, and the back-
> end could as well be changed to allow using up to 8 registers; in fact,
> this would even be more logical since it would allow using any of the
> argument registers also as return register.
> 
> But this has really nothing to do with how Swift choses to *use* this.
> Which and how many values Swift wants to return in registers is in
> the end a choice to be made by the front-end.  Ideally, there should
> be an ABI document specifying the Swift ABI for each platform.  I
> don't really know what Swift is trying to do here; in particular, I
> do not know whether Swift is attempting to be compatible with some
> other ABI to allow interoperability, or whether this is a completely
> private choice.  So I cannot really say whether 4 is "correct" here.

Thanks the response! I naively approached the patch from a "how to make
it work" perspective rather than a "how *should* it work", and you've
exposed that here. Swift document the ABI commitments[1] and calling
convention[2], which I'd looked over in the early days of developing
the patch but haven't recently revisited them. I need to take a deeper
dive to better understand the aims and how these should be exploited on
Power so I can answer the question.

Cheers,

Andrew

[1] https://github.com/apple/swift/blob/master/docs/ABIStabilityManifesto.md
[2] https://github.com/apple/swift/blob/master/docs/CallingConvention.rst

> 
> Bye,
> Ulrich
> 

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[PATCH v2] [PPC64]: Add support for Swift calling convention

2017-04-26 Thread Andrew Jeffery via cfe-commits

For the tests I've extracted the int5 and int8 cases to cater for
different alignments for different platform ABIs. For Linux on POWER the
5 and 8 element vectors must be naturally aligned with respect to the
total "soft" vector size, despite being represented as an aggregate.
Specifically, the patch caters for the following differences in
supporting powerpc64le-unknown-linux:

   $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
   --- test/CodeGen/64bit-swiftcall.c   2017-04-20 17:14:59.797963820 +0930
   +++ test/CodeGen/ppc64-swiftcall.c   2017-04-20 17:15:11.621965118 +0930
   @@ -1,7 +1,6 @@
   -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
-emit-llvm -o - %s | FileCheck %s
   -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm 
-o - %s | FileCheck %s
   +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - %s | 
FileCheck %s

   -// REQUIRES: aarch64-registered-target,x86-registered-target
   +// REQUIRES: powerpc-registered-target

#define SWIFTCALL __attribute__((swiftcall))
#define OUT __attribute__((swift_indirect_result))
   @@ -370,8 +369,8 @@

TEST(int8)
// CHECK-LABEL: define {{.*}} @return_int8()
   -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
   +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
// CHECK:   [[VAR:%.*]] = alloca [[REC]], align
// CHECK:   store
// CHECK:   load
// CHECK:   store
   @@ -414,8 +413,8 @@

TEST(int5)
// CHECK-LABEL: define {{.*}} @return_int5()
   -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
   +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
// CHECK:   [[VAR:%.*]] = alloca [[REC]], align
// CHECK:   store
// CHECK:   load
// CHECK:   store

Despite some duplication, the advantage of this approach over using
pattern matching for alignment in 64bit-swiftcall.c is that we ensure
each platform is using the expected alignment but without duplicating
the entirety of 64bit-swiftcall.c.

Signed-off-by: Andrew Jeffery 
---
 lib/Basic/Targets.cpp |  11 ++
 lib/CodeGen/TargetInfo.cpp|  14 ++-
 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 ++
 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 +
 test/CodeGen/64bit-swiftcall.c|  93 +
 5 files changed, 258 insertions(+), 93 deletions(-)
 create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
 create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index aab3160af0f9..e32ad0b2dc39 100644
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -1708,6 +1708,17 @@ public:
 }
 return false;
   }
+
+  CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
+switch (CC) {
+case CC_C:
+case CC_Swift:
+return CCCR_OK;
+default:
+break;
+}
+return CCCR_Warning;
+  }
 };
 
 class DarwinPPC32TargetInfo : public DarwinTargetInfo {
diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
index d2fc3888ef29..6193f6c4ac29 100644
--- a/lib/CodeGen/TargetInfo.cpp
+++ b/lib/CodeGen/TargetInfo.cpp
@@ -4175,7 +4175,7 @@ 
PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
 
 namespace {
 /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
-class PPC64_SVR4_ABIInfo : public ABIInfo {
+class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
 public:
   enum ABIKind {
 ELFv1 = 0,
@@ -4219,7 +4219,7 @@ private:
 public:
   PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
  bool SoftFloatABI)
-  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
+  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
 IsSoftFloatABI(SoftFloatABI) {}
 
   bool isPromotableTypeForABI(QualType Ty) const;
@@ -4262,6 +4262,16 @@ public:
 
   Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
 QualType Ty) const override;
+
+  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
+ArrayRef scalars,
+bool asReturnValue) const override {
+return occupiesMoreThan(CGT, scalars, /*total*/ 4);
+  }
+
+  bool isSwiftErrorInRegister() const override {
+return true;
+  }
 };
 
 class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
diff --git a/test/CodeGen/64bit-swiftcall-extvec-agg-align16.c 
b/test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
new file mode 100644
index ..fa00484fc185
--- /dev/null
+++ b/test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
@@ -0,0 +1,117 @@
+// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm 
-o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o

Re: [PATCH v2] [PPC64]: Add support for Swift calling convention

2017-05-11 Thread Andrew Jeffery via cfe-commits

Ping - does anyone have a moment to take a look?

Cheers,

Andrew

On Thu, 2017-04-27 at 13:52 +0930, Andrew Jeffery wrote:
> For the tests I've extracted the int5 and int8 cases to cater for
> different alignments for different platform ABIs. For Linux on POWER the
> 5 and 8 element vectors must be naturally aligned with respect to the
> total "soft" vector size, despite being represented as an aggregate.
> Specifically, the patch caters for the following differences in
> supporting powerpc64le-unknown-linux:
> 
>    $ diff -u test/CodeGen/64bit-swiftcall.c test/CodeGen/ppc64-swiftcall.c
> >    --- test/CodeGen/64bit-swiftcall.c   2017-04-20 17:14:59.797963820 
> > +0930
> >    +++ test/CodeGen/ppc64-swiftcall.c   2017-04-20 17:15:11.621965118 
> > +0930
>    @@ -1,7 +1,6 @@
>    -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 
> -emit-llvm -o - %s | FileCheck %s
>    -// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone 
> -emit-llvm -o - %s | FileCheck %s
>    +// RUN: %clang_cc1 -triple powerpc64le-unknown-linux -emit-llvm -o - %s | 
> FileCheck %s
> 
>    -// REQUIRES: aarch64-registered-target,x86-registered-target
>    +// REQUIRES: powerpc-registered-target
> 
> #define SWIFTCALL __attribute__((swiftcall))
> #define OUT __attribute__((swift_indirect_result))
>    @@ -370,8 +369,8 @@
> 
> TEST(int8)
> // CHECK-LABEL: define {{.*}} @return_int8()
>    -// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 16
>    +// CHECK:   [[RET:%.*]] = alloca [[REC:<8 x i32>]], align 32
> // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> // CHECK:   store
> // CHECK:   load
> // CHECK:   store
>    @@ -414,8 +413,8 @@
> 
> TEST(int5)
> // CHECK-LABEL: define {{.*}} @return_int5()
>    -// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 16
>    +// CHECK:   [[RET:%.*]] = alloca [[REC:<5 x i32>]], align 32
> // CHECK:   [[VAR:%.*]] = alloca [[REC]], align
> // CHECK:   store
> // CHECK:   load
> // CHECK:   store
> 
> Despite some duplication, the advantage of this approach over using
> pattern matching for alignment in 64bit-swiftcall.c is that we ensure
> each platform is using the expected alignment but without duplicating
> the entirety of 64bit-swiftcall.c.
> 
> > Signed-off-by: Andrew Jeffery 
> ---
>  lib/Basic/Targets.cpp |  11 ++
>  lib/CodeGen/TargetInfo.cpp|  14 ++-
>  test/CodeGen/64bit-swiftcall-extvec-agg-align16.c | 117 
> ++
>  test/CodeGen/64bit-swiftcall-extvec-agg-align32.c | 116 +
>  test/CodeGen/64bit-swiftcall.c|  93 +
>  5 files changed, 258 insertions(+), 93 deletions(-)
>  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align16.c
>  create mode 100644 test/CodeGen/64bit-swiftcall-extvec-agg-align32.c
> 
> diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
> index aab3160af0f9..e32ad0b2dc39 100644
> --- a/lib/Basic/Targets.cpp
> +++ b/lib/Basic/Targets.cpp
> @@ -1708,6 +1708,17 @@ public:
>  }
>  return false;
>    }
> +
> +  CallingConvCheckResult checkCallingConvention(CallingConv CC) const 
> override {
> +switch (CC) {
> +case CC_C:
> +case CC_Swift:
> +return CCCR_OK;
> +default:
> +break;
> +}
> +return CCCR_Warning;
> +  }
>  };
>  
>  class DarwinPPC32TargetInfo : public DarwinTargetInfo {
> diff --git a/lib/CodeGen/TargetInfo.cpp b/lib/CodeGen/TargetInfo.cpp
> index d2fc3888ef29..6193f6c4ac29 100644
> --- a/lib/CodeGen/TargetInfo.cpp
> +++ b/lib/CodeGen/TargetInfo.cpp
> @@ -4175,7 +4175,7 @@ 
> PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
>  
>  namespace {
>  /// PPC64_SVR4_ABIInfo - The 64-bit PowerPC ELF (SVR4) ABI information.
> -class PPC64_SVR4_ABIInfo : public ABIInfo {
> +class PPC64_SVR4_ABIInfo : public SwiftABIInfo {
>  public:
>    enum ABIKind {
>  ELFv1 = 0,
> @@ -4219,7 +4219,7 @@ private:
>  public:
>    PPC64_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind, bool HasQPX,
>   bool SoftFloatABI)
> -  : ABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
> +  : SwiftABIInfo(CGT), Kind(Kind), HasQPX(HasQPX),
>  IsSoftFloatABI(SoftFloatABI) {}
>  
>    bool isPromotableTypeForABI(QualType Ty) const;
> @@ -4262,6 +4262,16 @@ public:
>  
>    Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
>  QualType Ty) const override;
> +
> +  bool shouldPassIndirectlyForSwift(CharUnits totalSize,
> +ArrayRef scalars,
> +bool asReturnValue) const override {
> +return occupiesMoreThan(CGT, scalars, /*total*/ 4);
> +  }
> +
> +  bool isSwiftErrorInRegister() const override {
> +return true;
> +  }
>  };
>  
>  class PPC64_SVR4_TargetCodeGenInfo : public TargetCodeGenInfo {
> diff --git a/test/CodeGen/64bit-swiftcall

[PATCH v3] [PPC64]: Add support for Swift calling convention

[PATCH] [PPC64]: Add support for Swift calling convention

Re: [PATCH] [PPC64]: Add support for Swift calling convention

Re: [PATCH] [PPC64]: Add support for Swift calling convention

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

Re: [PATCH v3] [PPC64]: Add support for Swift calling convention

[PATCH v2] [PPC64]: Add support for Swift calling convention

Re: [PATCH v2] [PPC64]: Add support for Swift calling convention

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