[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)
https://github.com/wangpc-pp approved this pull request. https://github.com/llvm/llvm-project/pull/131261 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang-doc] [feat] add --repository-line-prefix argument (PR #131280)
https://github.com/hulxv created
https://github.com/llvm/llvm-project/pull/131280
### Description
This PR adds a new command-line option that allows users to specify the prefix
used for line-based anchors in repository URLs. Different repository interfaces
use different formats for line anchors (GitHub uses "#L123", chromium-project
uses "#123", etc.). This option enables users to customize the line prefix to
match their repository platform without requiring hard-coded values for each
service.
Fix #59814
>From bf9bd4156cb7f652c9cf0477f537e5c58b470448 Mon Sep 17 00:00:00 2001
From: hulxv
Date: Fri, 14 Mar 2025 07:39:15 +0200
Subject: [PATCH 1/2] [clang-doc] [feat] add `--repository-line-prefix`
argument (fix #59814)
---
clang-tools-extra/clang-doc/HTMLGenerator.cpp | 66 ---
clang-tools-extra/clang-doc/MDGenerator.cpp | 7 +-
.../clang-doc/Representation.cpp | 4 ++
clang-tools-extra/clang-doc/Representation.h | 5 +-
.../clang-doc/tool/ClangDocMain.cpp | 13 ++--
5 files changed, 64 insertions(+), 31 deletions(-)
diff --git a/clang-tools-extra/clang-doc/HTMLGenerator.cpp
b/clang-tools-extra/clang-doc/HTMLGenerator.cpp
index 18a0de826630c..967275f93193b 100644
--- a/clang-tools-extra/clang-doc/HTMLGenerator.cpp
+++ b/clang-tools-extra/clang-doc/HTMLGenerator.cpp
@@ -491,9 +491,9 @@ genReferencesBlock(const std::vector &References,
return Out;
}
-static std::unique_ptr
-writeFileDefinition(const Location &L,
-std::optional RepositoryUrl = std::nullopt) {
+static std::unique_ptr writeFileDefinition(
+const Location &L, std::optional RepositoryUrl = std::nullopt,
+std::optional RepositoryLinePrefix = std::nullopt) {
if (!L.IsFileInRootDir && !RepositoryUrl)
return std::make_unique(
HTMLTag::TAG_P, "Defined at line " + std::to_string(L.LineNumber) +
@@ -514,17 +514,21 @@ writeFileDefinition(const Location &L,
Node->Children.emplace_back(std::make_unique("Defined at line "));
auto LocNumberNode =
std::make_unique(HTMLTag::TAG_A, std::to_string(L.LineNumber));
- // The links to a specific line in the source code use the github /
- // googlesource notation so it won't work for all hosting pages.
- // FIXME: we probably should have a configuration setting for line number
- // rendering in the HTML. For example, GitHub uses #L22, while googlesource
- // uses #22 for line numbers.
- LocNumberNode->Attributes.emplace_back(
- "href", (FileURL + "#" + std::to_string(L.LineNumber)).str());
+
+ std::string LineAnchor = "#";
+
+ if (RepositoryLinePrefix)
+LineAnchor += RepositoryLinePrefix.value().str();
+
+ LineAnchor += std::to_string(L.LineNumber);
+
+ LocNumberNode->Attributes.emplace_back("href", (FileURL + LineAnchor).str());
Node->Children.emplace_back(std::move(LocNumberNode));
Node->Children.emplace_back(std::make_unique(" of file "));
+
auto LocFileNode = std::make_unique(
HTMLTag::TAG_A, llvm::sys::path::filename(FileURL));
+
LocFileNode->Attributes.emplace_back("href", std::string(FileURL));
Node->Children.emplace_back(std::move(LocFileNode));
return Node;
@@ -750,11 +754,15 @@ genHTML(const EnumInfo &I, const ClangDocContext &CDCtx) {
Out.emplace_back(std::move(Table));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(
- writeFileDefinition(*I.DefLoc, StringRef{*CDCtx.RepositoryUrl}));
+std::optional RepoUrl;
+std::optional RepoLinePrefix;
+
+if (CDCtx.RepositoryUrl)
+ RepoUrl = StringRef{*CDCtx.RepositoryUrl};
+if (CDCtx.RepositoryLinePrefix)
+ RepoLinePrefix = StringRef{*CDCtx.RepositoryLinePrefix};
+
+Out.emplace_back(writeFileDefinition(*I.DefLoc, RepoUrl, RepoLinePrefix));
}
std::string Description;
@@ -799,11 +807,15 @@ genHTML(const FunctionInfo &I, const ClangDocContext
&CDCtx,
FunctionHeader->Children.emplace_back(std::make_unique(")"));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(writeFileDefinition(
- *I.DefLoc, StringRef{*CDCtx.RepositoryUrl}));
+std::optional RepoUrl;
+std::optional RepoLinePrefix;
+
+if (CDCtx.RepositoryUrl)
+ RepoUrl = StringRef{*CDCtx.RepositoryUrl};
+if (CDCtx.RepositoryLinePrefix)
+ RepoLinePrefix = StringRef{*CDCtx.RepositoryLinePrefix};
+
+Out.emplace_back(writeFileDefinition(*I.DefLoc, RepoUrl, RepoLinePrefix));
}
std::string Description;
@@ -866,11 +878,15 @@ genHTML(const RecordInfo &I, Index &InfoIndex, const
ClangDocContext &CDCtx,
Out.emplace_back(std::make_unique(HTMLTag::TAG_H1, InfoTitle));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(writeFileDefinition(
- *I.DefLoc, StringRef{*CDCtx.RepositoryUrl}))
[clang] Reapply "[Clang] Improve diagnostics for expansion length mismatch" (PR #121044)
https://github.com/zyn0217 updated
https://github.com/llvm/llvm-project/pull/121044
>From 77537d523bc164a86b46e83651500a4b37c0c3bf Mon Sep 17 00:00:00 2001
From: Younan Zhang
Date: Tue, 24 Dec 2024 13:06:44 +0800
Subject: [PATCH 1/3] Reapply "[Clang] Improve diagnostics for expansion length
mismatch"
... and "[Clang] fix missing initialization of original number of expansions"
This reverts commit acecf68c8b7c3c625cfa00f00f8ddc8f15baae44.
Co-authored-by: Matheus Izvekov
---
clang/include/clang/Sema/Sema.h | 8 +-
clang/include/clang/Sema/SemaInternal.h | 2 +-
clang/lib/AST/ExprCXX.cpp | 2 +-
clang/lib/Sema/SemaDeclCXX.cpp| 2 +-
clang/lib/Sema/SemaTemplateDeduction.cpp | 7 +-
clang/lib/Sema/SemaTemplateVariadic.cpp | 340 +-
clang/lib/Sema/TreeTransform.h| 1 +
.../CXX/temp/temp.decls/temp.variadic/p5.cpp | 50 +++
.../SemaTemplate/cxx1z-fold-expressions.cpp | 2 +-
clang/test/SemaTemplate/pack-deduction.cpp| 51 ++-
10 files changed, 285 insertions(+), 180 deletions(-)
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 9ac26d8728446..34f99b8adf467 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -232,9 +232,11 @@ void threadSafetyCleanup(BeforeSet *Cache);
// FIXME: No way to easily map from TemplateTypeParmTypes to
// TemplateTypeParmDecls, so we have this horrible PointerUnion.
-typedef std::pair,
- SourceLocation>
-UnexpandedParameterPack;
+using UnexpandedParameterPack = std::pair<
+llvm::PointerUnion<
+const TemplateTypeParmType *, const SubstTemplateTypeParmPackType *,
+const SubstNonTypeTemplateParmPackExpr *, const NamedDecl *>,
+SourceLocation>;
/// Describes whether we've seen any nullability information for the given
/// file.
diff --git a/clang/include/clang/Sema/SemaInternal.h
b/clang/include/clang/Sema/SemaInternal.h
index 95874077050a9..acf6c8146d70d 100644
--- a/clang/include/clang/Sema/SemaInternal.h
+++ b/clang/include/clang/Sema/SemaInternal.h
@@ -75,7 +75,7 @@ getDepthAndIndex(UnexpandedParameterPack UPP) {
if (const auto *TTP = dyn_cast(UPP.first))
return std::make_pair(TTP->getDepth(), TTP->getIndex());
- return getDepthAndIndex(cast(UPP.first));
+ return getDepthAndIndex(cast(UPP.first));
}
class TypoCorrectionConsumer : public VisibleDeclConsumer {
diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp
index c8d61e2cf3f26..afa3db950284b 100644
--- a/clang/lib/AST/ExprCXX.cpp
+++ b/clang/lib/AST/ExprCXX.cpp
@@ -1734,7 +1734,7 @@ PackIndexingExpr *PackIndexingExpr::Create(
NamedDecl *PackIndexingExpr::getPackDecl() const {
if (auto *D = dyn_cast(getPackIdExpression()); D) {
NamedDecl *ND = dyn_cast(D->getDecl());
-assert(ND && "exected a named decl");
+assert(ND && "expected a named decl");
return ND;
}
assert(false && "invalid declaration kind in pack indexing expression");
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index 96aac7871db1e..756937f44e948 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -17589,7 +17589,7 @@ DeclResult Sema::ActOnTemplatedFriendTag(
unsigned FriendDeclDepth = TempParamLists.front()->getDepth();
for (UnexpandedParameterPack &U : Unexpanded) {
if (getDepthAndIndex(U).first >= FriendDeclDepth) {
- auto *ND = dyn_cast(U.first);
+ auto *ND = dyn_cast(U.first);
if (!ND)
ND = cast(U.first)->getDecl();
Diag(U.second, diag::friend_template_decl_malformed_pack_expansion)
diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp
b/clang/lib/Sema/SemaTemplateDeduction.cpp
index e6ec4a7178e81..6af842121ae79 100644
--- a/clang/lib/Sema/SemaTemplateDeduction.cpp
+++ b/clang/lib/Sema/SemaTemplateDeduction.cpp
@@ -874,8 +874,11 @@ class PackDeductionScope {
SmallVector Unexpanded;
S.collectUnexpandedParameterPacks(Pattern, Unexpanded);
for (unsigned I = 0, N = Unexpanded.size(); I != N; ++I) {
-unsigned Depth, Index;
-std::tie(Depth, Index) = getDepthAndIndex(Unexpanded[I]);
+UnexpandedParameterPack U = Unexpanded[I];
+if (isa(U.first))
+ continue;
+auto [Depth, Index] = getDepthAndIndex(U);
if (Depth == Info.getDeducedDepth())
AddPack(Index);
}
diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp
b/clang/lib/Sema/SemaTemplateVariadic.cpp
index d9256dbd07d7a..d6c71ecec13b6 100644
--- a/clang/lib/Sema/SemaTemplateVariadic.cpp
+++ b/clang/lib/Sema/SemaTemplateVariadic.cpp
@@ -38,7 +38,7 @@ class CollectUnexpandedParameterPacksVisitor
unsigned DepthLimit = (unsigned)-1;
#ifndef NDEBUG
-bool ContainsIntermediatePacks = false;
+ bool ContainsIntermediatePacks = false;
#endif
void addUnexpanded(NamedDecl *ND, SourceLocation Loc = SourceLocation(
[clang] [clang-format] Add support for absl nullability macros (PR #130346)
https://github.com/owenca updated
https://github.com/llvm/llvm-project/pull/130346
>From 10df1857532a6a27b0e5286e10c9f0724d6d7e1d Mon Sep 17 00:00:00 2001
From: Jan Voung
Date: Fri, 7 Mar 2025 21:02:16 +
Subject: [PATCH 1/9] [clang-format] Add support for absl nullability macros
---
clang/lib/Format/Format.cpp| 4
clang/unittests/Format/ConfigParseTest.cpp | 4 +++-
clang/unittests/Format/FormatTest.cpp | 19 +--
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index b5f1241321891..1401b51586d03 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -1508,6 +1508,10 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind
Language) {
LLVMStyle.AlwaysBreakAfterDefinitionReturnType = FormatStyle::DRTBS_None;
LLVMStyle.AlwaysBreakBeforeMultilineStrings = false;
LLVMStyle.AttributeMacros.push_back("__capability");
+ // Abseil aliases to clang's `_Nonnull`, `_Nullable` and `_Null_unspecified`.
+ LLVMStyle.AttributeMacros.push_back("absl_nonnull");
+ LLVMStyle.AttributeMacros.push_back("absl_nullable");
+ LLVMStyle.AttributeMacros.push_back("absl_nullability_unknown");
LLVMStyle.BinPackArguments = true;
LLVMStyle.BinPackLongBracedList = true;
LLVMStyle.BinPackParameters = FormatStyle::BPPS_BinPack;
diff --git a/clang/unittests/Format/ConfigParseTest.cpp
b/clang/unittests/Format/ConfigParseTest.cpp
index 273bab87b1ee1..2cc2a45a7a590 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -908,7 +908,9 @@ TEST(ConfigParseTest, ParsesConfiguration) {
Style.AttributeMacros.clear();
CHECK_PARSE("BasedOnStyle: LLVM", AttributeMacros,
- std::vector{"__capability"});
+ std::vector({"__capability", "absl_nonnull",
"absl_nullable",
+"absl_nullability_unknown"}));
+ Style.AttributeMacros.clear();
CHECK_PARSE("AttributeMacros: [attr1, attr2]", AttributeMacros,
std::vector({"attr1", "attr2"}));
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index bd335f4b6a21b..a17cad0b67b08 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -12375,6 +12375,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
@@ -12518,6 +12521,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyIndependentOfContext("MACRO(A *_Nonnull a);");
verifyIndependentOfContext("MACRO(A *_Nullable a);");
verifyIndependentOfContext("MACRO(A *_Null_unspecified a);");
+ verifyIndependentOfContext("MACRO(A *absl_nonnull a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullable a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullability_unknown a);");
verifyIndependentOfContext("MACRO(A *__attribute__((foo)) a);");
verifyIndependentOfContext("MACRO(A *__attribute((foo)) a);");
verifyIndependentOfContext("MACRO(A *[[clang::attr]] a);");
@@ -12674,6 +12680,12 @@ TEST_F(FormatTest, UnderstandsAttributes) {
verifyFormat("SomeType *__unused s{InitValue};", CustomAttrs);
verifyFormat("SomeType s __unused(InitValue);", CustomAttrs);
verifyFormat("SomeType s __unused{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s(InitValue);",
CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s{InitValue};",
CustomAttrs);
verifyFormat("SomeType *__capability s(InitValue);", CustomAttrs);
verifyFormat("SomeType *__capability s{InitValue};", CustomAttrs);
}
@@ -12687,7 +12699,9 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
verifyFormat("x = (foo *_Nonnull)*v;");
verifyFormat("x = (foo *_Nullable)*v;");
verifyFormat("x = (foo *_Null_unspecified)*v;");
- verifyFormat("x = (foo *_Nonnull)*v;");
+ verifyFormat("x = (foo *absl_nonnull)*v;");
+ verifyFormat("x = (foo *absl_nullable)*v;");
+ verifyFormat("x = (foo *absl_nullability_unknown)*v;");
verifyFormat("x = (foo *[[clang::attr]])*v;");
verifyFormat("x = (foo *[[clang::attr(\"foo\")]])*v;");
verifyFormat("x = (foo *__ptr32)*v;");
@@ -12701,7 +12715,8 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
LongPointerLeft.PointerAlignment = FormatStyle::PAS_Left;
StringRef AllQualifiers =
"const volatile restrict __attribute__((foo)) _Nonnull _Null_unspecified
"
-
[clang] Reapply "[Clang] Improve diagnostics for expansion length mismatch" (PR #121044)
https://github.com/zyn0217 updated
https://github.com/llvm/llvm-project/pull/121044
>From 77537d523bc164a86b46e83651500a4b37c0c3bf Mon Sep 17 00:00:00 2001
From: Younan Zhang
Date: Tue, 24 Dec 2024 13:06:44 +0800
Subject: [PATCH 1/4] Reapply "[Clang] Improve diagnostics for expansion length
mismatch"
... and "[Clang] fix missing initialization of original number of expansions"
This reverts commit acecf68c8b7c3c625cfa00f00f8ddc8f15baae44.
Co-authored-by: Matheus Izvekov
---
clang/include/clang/Sema/Sema.h | 8 +-
clang/include/clang/Sema/SemaInternal.h | 2 +-
clang/lib/AST/ExprCXX.cpp | 2 +-
clang/lib/Sema/SemaDeclCXX.cpp| 2 +-
clang/lib/Sema/SemaTemplateDeduction.cpp | 7 +-
clang/lib/Sema/SemaTemplateVariadic.cpp | 340 +-
clang/lib/Sema/TreeTransform.h| 1 +
.../CXX/temp/temp.decls/temp.variadic/p5.cpp | 50 +++
.../SemaTemplate/cxx1z-fold-expressions.cpp | 2 +-
clang/test/SemaTemplate/pack-deduction.cpp| 51 ++-
10 files changed, 285 insertions(+), 180 deletions(-)
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 9ac26d8728446..34f99b8adf467 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -232,9 +232,11 @@ void threadSafetyCleanup(BeforeSet *Cache);
// FIXME: No way to easily map from TemplateTypeParmTypes to
// TemplateTypeParmDecls, so we have this horrible PointerUnion.
-typedef std::pair,
- SourceLocation>
-UnexpandedParameterPack;
+using UnexpandedParameterPack = std::pair<
+llvm::PointerUnion<
+const TemplateTypeParmType *, const SubstTemplateTypeParmPackType *,
+const SubstNonTypeTemplateParmPackExpr *, const NamedDecl *>,
+SourceLocation>;
/// Describes whether we've seen any nullability information for the given
/// file.
diff --git a/clang/include/clang/Sema/SemaInternal.h
b/clang/include/clang/Sema/SemaInternal.h
index 95874077050a9..acf6c8146d70d 100644
--- a/clang/include/clang/Sema/SemaInternal.h
+++ b/clang/include/clang/Sema/SemaInternal.h
@@ -75,7 +75,7 @@ getDepthAndIndex(UnexpandedParameterPack UPP) {
if (const auto *TTP = dyn_cast(UPP.first))
return std::make_pair(TTP->getDepth(), TTP->getIndex());
- return getDepthAndIndex(cast(UPP.first));
+ return getDepthAndIndex(cast(UPP.first));
}
class TypoCorrectionConsumer : public VisibleDeclConsumer {
diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp
index c8d61e2cf3f26..afa3db950284b 100644
--- a/clang/lib/AST/ExprCXX.cpp
+++ b/clang/lib/AST/ExprCXX.cpp
@@ -1734,7 +1734,7 @@ PackIndexingExpr *PackIndexingExpr::Create(
NamedDecl *PackIndexingExpr::getPackDecl() const {
if (auto *D = dyn_cast(getPackIdExpression()); D) {
NamedDecl *ND = dyn_cast(D->getDecl());
-assert(ND && "exected a named decl");
+assert(ND && "expected a named decl");
return ND;
}
assert(false && "invalid declaration kind in pack indexing expression");
diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp
index 96aac7871db1e..756937f44e948 100644
--- a/clang/lib/Sema/SemaDeclCXX.cpp
+++ b/clang/lib/Sema/SemaDeclCXX.cpp
@@ -17589,7 +17589,7 @@ DeclResult Sema::ActOnTemplatedFriendTag(
unsigned FriendDeclDepth = TempParamLists.front()->getDepth();
for (UnexpandedParameterPack &U : Unexpanded) {
if (getDepthAndIndex(U).first >= FriendDeclDepth) {
- auto *ND = dyn_cast(U.first);
+ auto *ND = dyn_cast(U.first);
if (!ND)
ND = cast(U.first)->getDecl();
Diag(U.second, diag::friend_template_decl_malformed_pack_expansion)
diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp
b/clang/lib/Sema/SemaTemplateDeduction.cpp
index e6ec4a7178e81..6af842121ae79 100644
--- a/clang/lib/Sema/SemaTemplateDeduction.cpp
+++ b/clang/lib/Sema/SemaTemplateDeduction.cpp
@@ -874,8 +874,11 @@ class PackDeductionScope {
SmallVector Unexpanded;
S.collectUnexpandedParameterPacks(Pattern, Unexpanded);
for (unsigned I = 0, N = Unexpanded.size(); I != N; ++I) {
-unsigned Depth, Index;
-std::tie(Depth, Index) = getDepthAndIndex(Unexpanded[I]);
+UnexpandedParameterPack U = Unexpanded[I];
+if (isa(U.first))
+ continue;
+auto [Depth, Index] = getDepthAndIndex(U);
if (Depth == Info.getDeducedDepth())
AddPack(Index);
}
diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp
b/clang/lib/Sema/SemaTemplateVariadic.cpp
index d9256dbd07d7a..d6c71ecec13b6 100644
--- a/clang/lib/Sema/SemaTemplateVariadic.cpp
+++ b/clang/lib/Sema/SemaTemplateVariadic.cpp
@@ -38,7 +38,7 @@ class CollectUnexpandedParameterPacksVisitor
unsigned DepthLimit = (unsigned)-1;
#ifndef NDEBUG
-bool ContainsIntermediatePacks = false;
+ bool ContainsIntermediatePacks = false;
#endif
void addUnexpanded(NamedDecl *ND, SourceLocation Loc = SourceLocation(
[clang] [clang][CodeGen] Do not try to emit definition of variable whose initializer contains errors (PR #131278)
zyn0217 wrote: Note that doing so might also hide those similar bugs where we accidentally make RecoveryExpr into CodeGen. So I don't know if this is on the right track https://github.com/llvm/llvm-project/pull/131278 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)
llvmbot wrote:
@llvm/pr-subscribers-clang
@llvm/pr-subscribers-backend-risc-v
Author: Brandon Wu (4vtomat)
Changes
---
Full diff: https://github.com/llvm/llvm-project/pull/131261.diff
1 Files Affected:
- (modified) clang/lib/Sema/SemaRISCV.cpp (+20-19)
``diff
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 47660319fa3af..85d71b6408930 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -666,22 +666,22 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vaeskf2_vi_tu:
case RISCVVector::BI__builtin_rvv_vaeskf2_vi:
case RISCVVector::BI__builtin_rvv_vsm4k_vi_tu: {
-QualType Op1Type = TheCall->getArg(0)->getType();
-QualType Op2Type = TheCall->getArg(1)->getType();
-return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type, 128) ||
- CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op2Type, 128) ||
+QualType Arg0Type = TheCall->getArg(0)->getType();
+QualType Arg1Type = TheCall->getArg(1)->getType();
+return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg0Type, 128) ||
+ CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg1Type, 128) ||
SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);
}
case RISCVVector::BI__builtin_rvv_vsm3c_vi_tu:
case RISCVVector::BI__builtin_rvv_vsm3c_vi: {
-QualType Op1Type = TheCall->getArg(0)->getType();
-return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type, 256) ||
+QualType Arg0Type = TheCall->getArg(0)->getType();
+return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg0Type, 256) ||
SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 31);
}
case RISCVVector::BI__builtin_rvv_vaeskf1_vi:
case RISCVVector::BI__builtin_rvv_vsm4k_vi: {
-QualType Op1Type = TheCall->getArg(0)->getType();
-return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type, 128) ||
+QualType Arg0Type = TheCall->getArg(0)->getType();
+return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg0Type, 128) ||
SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 31);
}
case RISCVVector::BI__builtin_rvv_vaesdf_vv:
@@ -706,10 +706,10 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vaesz_vs_tu:
case RISCVVector::BI__builtin_rvv_vsm4r_vv_tu:
case RISCVVector::BI__builtin_rvv_vsm4r_vs_tu: {
-QualType Op1Type = TheCall->getArg(0)->getType();
-QualType Op2Type = TheCall->getArg(1)->getType();
-return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type, 128) ||
- CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op2Type, 128);
+QualType Arg0Type = TheCall->getArg(0)->getType();
+QualType Arg1Type = TheCall->getArg(1)->getType();
+return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg0Type, 128) ||
+ CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg1Type, 128);
}
case RISCVVector::BI__builtin_rvv_vsha2ch_vv:
case RISCVVector::BI__builtin_rvv_vsha2cl_vv:
@@ -717,22 +717,23 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vsha2ch_vv_tu:
case RISCVVector::BI__builtin_rvv_vsha2cl_vv_tu:
case RISCVVector::BI__builtin_rvv_vsha2ms_vv_tu: {
-QualType Op1Type = TheCall->getArg(0)->getType();
-QualType Op2Type = TheCall->getArg(1)->getType();
-QualType Op3Type = TheCall->getArg(2)->getType();
+QualType Arg0Type = TheCall->getArg(0)->getType();
+QualType Arg1Type = TheCall->getArg(1)->getType();
+QualType Arg2Type = TheCall->getArg(2)->getType();
ASTContext::BuiltinVectorTypeInfo Info =
-Context.getBuiltinVectorTypeInfo(Op1Type->castAs());
+Context.getBuiltinVectorTypeInfo(Arg0Type->castAs());
uint64_t ElemSize = Context.getTypeSize(Info.ElementType);
if (ElemSize == 64 && !TI.hasFeature("zvknhb"))
return Diag(TheCall->getBeginLoc(),
diag::err_riscv_builtin_requires_extension)
<< /* IsExtension */ true << TheCall->getSourceRange() <<
"zvknhb";
-return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op1Type,
+return CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg0Type,
ElemSize * 4) ||
- CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op2Type,
+ CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg1Type,
ElemSize * 4) ||
- CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Op3Type, ElemSize *
4);
+ CheckInvalidVLENandLMUL(TI, TheCall, SemaRef, Arg2Type,
+ ElemSize * 4);
}
case RISCVVector::BI__builtin_rvv_sf_vc_i_se:
``
https://github.com/llvm/llvm-project/pull/131261
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[clang] [clang][RISCV] Rename variable name in SemaRISCV. NFC (PR #131261)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/131261 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] [Sema] Make -Wreturn-type an error by default (PR #131207)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (Sirraide)
Changes
Yet another attempt at this. Release note, tests etc are still missing since
this is just to see if CI is happy with it this time round (note:
warning-flags.c has proven to be very stubborn and I haven’t been able to fix
that test on its own despite trying several times so it is included here).
---
Full diff: https://github.com/llvm/llvm-project/pull/131207.diff
2 Files Affected:
- (modified) clang/include/clang/Basic/DiagnosticSemaKinds.td (+1-1)
- (modified) clang/test/Index/warning-flags.c (+1-1)
``diff
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 8e6e6e892cdd7..113e684a53c2b 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -722,7 +722,7 @@ def warn_falloff_nonvoid : Warning<
"non-void "
"%enum_select{%Function{function}|%Block{block}|%Lambda{lambda}|%Coroutine{coroutine}}0"
" does not return a value%select{| in all control paths}1">,
- InGroup;
+ InGroup, DefaultError;
def err_falloff_nonvoid : Error<
"non-void %select{function|block|lambda|coroutine}0 "
"does not return a value%select{| in all control paths}1">;
diff --git a/clang/test/Index/warning-flags.c b/clang/test/Index/warning-flags.c
index 1694c6abab562..3229f000c4ae0 100644
--- a/clang/test/Index/warning-flags.c
+++ b/clang/test/Index/warning-flags.c
@@ -9,7 +9,7 @@ int *bar(float *f) { return f; }
// RUN: c-index-test -test-load-source-reparse 5 all -w %s 2>&1 | FileCheck
-check-prefix=NOWARNINGS %s
// RUN: c-index-test -test-load-source all -w -O4 %s 2>&1 | FileCheck
-check-prefix=NOWARNINGS %s
-// CHECK-BOTH-WARNINGS: warning: non-void function does not return a value
+// CHECK-BOTH-WARNINGS: error: non-void function does not return a value
// CHECK-BOTH-WARNINGS: warning: incompatible pointer types returning 'float
*' from a function with result type 'int *'
// CHECK-SECOND-WARNING-NOT:non-void function does not return a value
``
https://github.com/llvm/llvm-project/pull/131207
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 42748a4 - [Clang driver] Diagnose `-maix-shared-lib-tls-model-opt` on wrong targets (#130865)
Author: Hubert Tong
Date: 2025-03-14T00:58:32-04:00
New Revision: 42748a454fc9d9a42504e8290234aaf9407437ce
URL:
https://github.com/llvm/llvm-project/commit/42748a454fc9d9a42504e8290234aaf9407437ce
DIFF:
https://github.com/llvm/llvm-project/commit/42748a454fc9d9a42504e8290234aaf9407437ce.diff
LOG: [Clang driver] Diagnose `-maix-shared-lib-tls-model-opt` on wrong targets
(#130865)
Added:
Modified:
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Driver/aix-shared-lib-tls-model-opt.c
Removed:
diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
index 57baa186a9eb7..f0ced406fca86 100644
--- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -72,6 +72,11 @@ void ppc::getPPCTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
D.Diag(diag::err_drv_argument_only_allowed_with)
<< "-maix-small-local-[exec|dynamic]-tls" << "-fdata-sections";
}
+
+ if (Args.hasArg(options::OPT_maix_shared_lib_tls_model_opt) &&
+ !(Triple.isOSAIX() && Triple.isArch64Bit()))
+D.Diag(diag::err_opt_not_valid_on_target)
+<< "-maix-shared-lib-tls-model-opt";
}
ppc::ReadGOTPtrMode ppc::getPPCReadGOTPtrMode(const Driver &D, const
llvm::Triple &Triple,
diff --git a/clang/test/Driver/aix-shared-lib-tls-model-opt.c
b/clang/test/Driver/aix-shared-lib-tls-model-opt.c
index e610bb6d15d9d..7acf091f0a049 100644
--- a/clang/test/Driver/aix-shared-lib-tls-model-opt.c
+++ b/clang/test/Driver/aix-shared-lib-tls-model-opt.c
@@ -6,12 +6,11 @@
// RUN: %clang -target powerpc64-unknown-aix -maix-shared-lib-tls-model-opt -S
-emit-llvm \
// RUN:%s -o - | FileCheck %s --check-prefixes=CHECK-AIX,CHECK-AIX-ON
-// FIXME: Clang driver diagnostic not implemented.
-// RUN: true || not %clang -target powerpc-unknown-aix
-maix-shared-lib-tls-model-opt \
+// RUN: not %clang -target powerpc-unknown-aix -maix-shared-lib-tls-model-opt \
// RUN:-fsyntax-only %s 2>&1 | FileCheck
--check-prefix=CHECK-UNSUPPORTED-TARGET %s
-// RUN: true || not %clang -target powerpc64le-unknown-linux-gnu
-maix-shared-lib-tls-model-opt \
+// RUN: not %clang -target powerpc64le-unknown-linux-gnu
-maix-shared-lib-tls-model-opt \
// RUN:-fsyntax-only %s 2>&1 | FileCheck
--check-prefix=CHECK-UNSUPPORTED-TARGET %s
-// RUN: true || not %clang -target powerpc64-unknown-linux-gnu
-maix-shared-lib-tls-model-opt \
+// RUN: not %clang -target powerpc64-unknown-linux-gnu
-maix-shared-lib-tls-model-opt \
// RUN:-fsyntax-only %s 2>&1 | FileCheck
--check-prefix=CHECK-UNSUPPORTED-TARGET %s
int test(void) {
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+ let Name = "GPRPairNoX0RV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairNoX0";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+ let Name = "GPRPairCRV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairC";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32,
uimm9_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]
topperc wrote:
Go ahead and add RISCVInstrinInfoZclsd.td after RISCVInstrinInfoZilsd.td. I'll
investigate if we should change the order.
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (PR #130779)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/130779 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CodeGen] Do not try to emit definition of variable whose initializer contains errors (PR #131278)
HighCommander4 wrote: > Note that doing so might also hide those similar bugs where we accidentally > make RecoveryExpr into CodeGen. So I don't know if this is on the right track Agreed. I wrote this patch for illustrative purposes but as I mentioned [here](https://github.com/llvm/llvm-project/issues/50067#issuecomment-2723653347) I'd rather not take it. https://github.com/llvm/llvm-project/pull/131278 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
https://github.com/dong-miao updated https://github.com/llvm/llvm-project/pull/131094 >From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 17:53:58 +0800 Subject: [PATCH 01/21] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 39853cf13a920..41b96e1497e70 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>; def : SysReg<"hvip", 0x645>; def : SysReg<"htinst", 0x64A>; def : SysReg<"hgeip", 0xE12>; +def : SysReg<"hedelegh", 0x612>; //===--===// // Hypervisor Configuration @@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>; def : SysReg<"mip", 0x344>; def : SysReg<"mtinst", 0x34A>; def : SysReg<"mtval2", 0x34B>; +def : SysReg<"medelegh", 0x312>; //===--===// // Machine Configuration >From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 18:02:40 +0800 Subject: [PATCH 02/21] Update rv32-hypervisor-csr-names.s --- llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++ 1 file changed, 18 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s index aadee4fb4f3ad..79d87b3f2471c 100644 --- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s @@ -219,3 +219,21 @@ csrrs t2, 0x214, zero csrrs t1, vsiph, zero # uimm12 csrrs t2, 0x254, zero + +## +# Hypervisor Trap Setup +## + +# hedelegh +# name +# CHECK-INST: csrrs t1, hedelegh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61] +# CHECK-INST-ALIAS: csrr t1, hedelegh +# uimm12 +# CHECK-INST: csrrs t2, hedelegh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61] +# CHECK-INST-ALIAS: csrr t2, hedelegh +# name +csrrs t1, hedelegh, zero +# uimm12 +csrrs t2, 0x612, zero >From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 18:05:04 +0800 Subject: [PATCH 03/21] Update rv32-machine-csr-names.s --- llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++ 1 file changed, 14 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s index 3d527e382376e..9e929b7eddeed 100644 --- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s @@ -22,6 +22,20 @@ csrrs t1, mstatush, zero # uimm12 csrrs t2, 0x310, zero +# medelegh +# name +# CHECK-INST: csrrs t1, medelegh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31] +# CHECK-INST-ALIAS: csrr t1, medelegh +# uimm12 +# CHECK-INST: csrrs t2, medelegh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31] +# CHECK-INST-ALIAS: csrr t2, medelegh +# name +csrrs t1, medelegh, zero +# uimm12 +csrrs t2, 0x312, zero + # # Machine Configuration # >From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sun, 5 Jan 2025 11:12:53 +0800 Subject: [PATCH 04/21] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 41b96e1497e70..21f912bbc84d1 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>; def : SysReg<"hvip", 0x645>; def : SysReg<"htinst", 0x64A>; def : SysReg<"hgeip", 0xE12>; +let isRV32Only = 1 in def : SysReg<"hedelegh", 0x612>; //===--===// @@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>; def : SysReg<"mip", 0x344>; def : SysReg<"mtinst", 0x34A>; def : SysReg<"mtval2", 0x34B>; +let isRV32Only = 1 in def : SysReg<"medelegh", 0x312>; //===--===// >From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sun, 5 Jan 2025 11:30:33 +0800 Subject: [PATCH 05/21] Update rv32-only-csr-names.s --- llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 1 file changed, 4 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s index db88eacf9396b..1604469210193 100644 --- a/llvm/test/MC/RISCV/rv32-only-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s @@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN
[clang] [llvm] [HLSL] Remove old resource annotations (PR #130338)
https://github.com/hekota updated
https://github.com/llvm/llvm-project/pull/130338
>From 99539251dcf58aab9a88973f9162156ae6f1aa77 Mon Sep 17 00:00:00 2001
From: Helena Kotas
Date: Thu, 6 Mar 2025 18:22:07 -0800
Subject: [PATCH 1/4] [HLSL][NFC] Update resource metadata tests to not use
obsolete metadata annotations
---
clang/test/CodeGenHLSL/cbuffer.hlsl | 78 +-
.../DirectX/Metadata/cbuffer_metadata.ll | 80 +++
.../CodeGen/DirectX/Metadata/srv_metadata.ll | 103 +
.../CodeGen/DirectX/Metadata/uav_metadata.ll | 135 ++
llvm/test/CodeGen/DirectX/UAVMetadata.ll | 77 --
llvm/test/CodeGen/DirectX/cbuf.ll | 37 -
.../CodeGen/DirectX/legacy_cb_layout_0.ll | 14 --
.../CodeGen/DirectX/legacy_cb_layout_1.ll | 37 -
.../CodeGen/DirectX/legacy_cb_layout_2.ll | 51 ---
.../CodeGen/DirectX/legacy_cb_layout_3.ll | 81 ---
10 files changed, 394 insertions(+), 299 deletions(-)
create mode 100644 llvm/test/CodeGen/DirectX/Metadata/cbuffer_metadata.ll
create mode 100644 llvm/test/CodeGen/DirectX/Metadata/srv_metadata.ll
create mode 100644 llvm/test/CodeGen/DirectX/Metadata/uav_metadata.ll
delete mode 100644 llvm/test/CodeGen/DirectX/UAVMetadata.ll
delete mode 100644 llvm/test/CodeGen/DirectX/cbuf.ll
delete mode 100644 llvm/test/CodeGen/DirectX/legacy_cb_layout_0.ll
delete mode 100644 llvm/test/CodeGen/DirectX/legacy_cb_layout_1.ll
delete mode 100644 llvm/test/CodeGen/DirectX/legacy_cb_layout_2.ll
delete mode 100644 llvm/test/CodeGen/DirectX/legacy_cb_layout_3.ll
diff --git a/clang/test/CodeGenHLSL/cbuffer.hlsl
b/clang/test/CodeGenHLSL/cbuffer.hlsl
index 38093c6dfacd7..b5e435619438f 100644
--- a/clang/test/CodeGenHLSL/cbuffer.hlsl
+++ b/clang/test/CodeGenHLSL/cbuffer.hlsl
@@ -20,6 +20,14 @@
// CHECK: %anon = type <{ float }>
// CHECK: %anon.0 = type <{ <2 x i32> }>
+// CHECK: %__cblayout_CB_A = type <{ [2 x double], [3 x <3 x float>], float,
[3 x double], half, [1 x <2 x double>], float, [2 x <3 x half>], <3 x half> }>
+// CHECK: %__cblayout_CB_B = type <{ [3 x <3 x double>], <3 x half> }>
+// CHECK: %__cblayout_CB_C = type <{ i32, target("dx.Layout", %F, 96, 0, 16,
28, 32, 56, 64, 80, 84, 90), half, target("dx.Layout", %G, 258, 0, 48, 64,
256), double }>
+
+// CHECK: %F = type <{ double, <3 x float>, float, <3 x double>, half, <2 x
double>, float, <3 x half>, <3 x half> }>
+// CHECK: %G = type <{ target("dx.Layout", %E, 36, 0, 8, 16, 20, 22, 24, 32),
[1 x float], [2 x target("dx.Layout", %F, 96, 0, 16, 28, 32, 56, 64, 80, 84,
90)], half }>
+// CHECK: %E = type <{ float, double, float, half, i16, i64, i32 }>
+
cbuffer CBScalars : register(b1, space5) {
float a1;
double a2;
@@ -155,6 +163,64 @@ cbuffer CBMix {
uint16_t f9;
};
+// CHECK: @CB_A.cb = external constant target("dx.CBuffer",
target("dx.Layout", %__cblayout_CB_A, 188, 0, 32, 76, 80, 120, 128, 144, 160,
182))
+
+cbuffer CB_A {
+ double B0[2];
+ float3 B1[3];
+ float B2;
+ double B3[3];
+ half B4;
+ double2 B5[1];
+ float B6;
+ half3 B7[2];
+ half3 B8;
+}
+
+// CHECK: @CB_B.cb = external constant target("dx.CBuffer",
target("dx.Layout", %__cblayout_CB_B, 94, 0, 88))
+cbuffer CB_B {
+ double3 B9[3];
+ half3 B10;
+}
+
+struct E {
+ float A0;
+ double A1;
+ float A2;
+ half A3;
+ int16_t A4;
+ int64_t A5;
+ int A6;
+};
+
+struct F {
+ double B0;
+ float3 B1;
+ float B2;
+ double3 B3;
+ half B4;
+ double2 B5;
+ float B6;
+ half3 B7;
+ half3 B8;
+};
+
+struct G {
+ E C0;
+ float C1[1];
+ F C2[2];
+ half C3;
+};
+
+// CHECK: @CB_C.cb = external constant target("dx.CBuffer",
target("dx.Layout", %__cblayout_CB_C, 400, 0, 16, 112, 128, 392))
+cbuffer CB_C {
+ int D0;
+ F D1;
+ half D2;
+ G D3;
+ double D4;
+}
+
// CHECK: define internal void @_init_resource_CBScalars.cb()
// CHECK-NEXT: entry:
// CHECK-NEXT: %[[HANDLE1:.*]] = call target("dx.CBuffer", target("dx.Layout",
%__cblayout_CBScalars, 56, 0, 8, 16, 24, 32, 36, 40, 48))
@@ -171,7 +237,7 @@ RWBuffer Buf;
[numthreads(4,1,1)]
void main() {
- Buf[0] = a1 + b1.z + c1[2] + a.f1.y + f1;
+ Buf[0] = a1 + b1.z + c1[2] + a.f1.y + f1 + B1[0].x + B10.z + D1.B2;
}
// CHECK: define internal void @_GLOBAL__sub_I_cbuffer.hlsl()
@@ -179,7 +245,8 @@ void main() {
// CHECK-NEXT: call void @_init_resource_CBScalars.cb()
// CHECK-NEXT: call void @_init_resource_CBArrays.cb()
-// CHECK: !hlsl.cbs = !{![[CBSCALARS:[0-9]+]], ![[CBVECTORS:[0-9]+]],
![[CBARRAYS:[0-9]+]], ![[CBSTRUCTS:[0-9]+]], ![[CBMIX:[0-9]+]]}
+// CHECK: !hlsl.cbs = !{![[CBSCALARS:[0-9]+]], ![[CBVECTORS:[0-9]+]],
![[CBARRAYS:[0-9]+]], ![[CBSTRUCTS:[0-9]+]], ![[CBMIX:[0-9]+]],
+// CHECK-SAME: ![[CB_A:[0-9]+]], ![[CB_B:[0-9]+]], ![[CB_C:[0-9]+]]}
// CHECK: ![[CBSCALARS]] = !{ptr @CBScalars.cb, ptr addrspace(2) @a1, ptr
addrspace(2) @a2, ptr addrspace(2) @a3, ptr addrspace(2) @a4,
// CHECK-SAME: ptr addrspace(2) @a5, ptr addrspace(2) @a6, ptr
[clang] [Clang] Force expressions with UO_Not to not be non-negative (PR #126846)
glandium wrote:
This had the side effect of adding implicit-int-conversion warnings on e.g. the
following code:
```
unsigned char foo(unsigned char x)
{
return ~x;
}
```
This seems correct, but this should probably be highlighted in the release
notes.
Another example is:
```
unsigned int foo(unsigned char x)
{
return ~(1
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+ let Name = "GPRPairNoX0RV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairNoX0";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+ let Name = "GPRPairCRV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairC";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32,
uimm9_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]
dong-miao wrote:
I added it, but due to the file reference order in
llvm/lib/Target/RISCVInstrInfo.td, an error occurred: Variable not defined:
'LD_RV32' `def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1,
uimm9_lsb000:$imm)`.
May I ask what I should do? Do I need to directly add 'RISCVInstrinInfoZclsd.
td' after 'RISCVInstrinInfoZilsd. td'? But this will disrupt the order of file
references in RISCVInstrInfo.td.
https://github.com/llvm/llvm-project/pull/131094
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[clang] [flang-rt] Pass the whole path of libflang_rt.runtime.a to linker on AIX (PR #131041)
@@ -1345,7 +1345,16 @@ void tools::addFortranRuntimeLibs(const ToolChain &TC,
const ArgList &Args,
if (AsNeeded)
addAsNeededOption(TC, Args, CmdArgs, /*as_needed=*/false);
}
-CmdArgs.push_back("-lflang_rt.runtime");
+if (TC.getTriple().isOSAIX()) {
+ // On AIX, pass the whole path of flang_rt.runtime.a to be consistent
+ // with clang.
+ std::string CRTBasename = "libflang_rt.runtime.a";
+ SmallString<128> Path(TC.getCompilerRTPath());
+ llvm::sys::path::append(Path, CRTBasename);
+ if (TC.getVFS().exists(Path))
+CmdArgs.push_back(Args.MakeArgString(std::string(Path)));
Meinersbur wrote:
> There are some similar usages in the Driver code.
And its source of one of my biggest grievences. See #122152
If the file does not exist, I want an error message about the file not
existing. With the runtime not being added, one will get an error about a
symbol not resolved. Someone will have to debug why flang-rt does not define
the symbol only to discover that flang-rt is not added to the linker line. Then
they have to find out why and the only way I can think of is to find this line
in the source that tells them that the flang-rt it not present or in the wrong
path. The result of `getCompilerRTPath()` varies by some parameters, or the
triple is sligthly different (`x86_64-unknown-linux-gnu` vs
`x86_64-linux-gnu`), or ... . I know because I went through this rabbit hole
for #122152. Let's please just not do this.
If the absolute path cannot be resolved, at least add `-lflang_rt.runtime` so
the linker can either resolve the library itself, or display an appropriate
error.
https://github.com/llvm/llvm-project/pull/131041
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[clang] [HLSL] Make sure `isSigned` flag is set on target type for `TypedBuffer` resources with signed int vectors (PR #130223)
@@ -59,8 +59,14 @@ llvm::Type *DirectXTargetCodeGenInfo::getHLSLType(
SmallVector Ints = {/*IsWriteable*/ ResAttrs.ResourceClass ==
llvm::dxil::ResourceClass::UAV,
/*IsROV*/ ResAttrs.IsROV};
-if (!ResAttrs.RawBuffer)
- Ints.push_back(/*IsSigned*/ ContainedTy->isSignedIntegerType());
+if (!ResAttrs.RawBuffer) {
+ const clang::Type *ElemType = ContainedTy->getUnqualifiedDesugaredType();
+ if (ElemType->isVectorType())
bob80905 wrote:
Does it make sense to add a while loop here?
Could it be more than a 2D vector?
https://github.com/llvm/llvm-project/pull/130223
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[clang-tools-extra] [clang-doc] [feat] add --repository-line-prefix argument (PR #131280)
llvmbot wrote:
@llvm/pr-subscribers-clang-tools-extra
Author: Mohamed Emad (hulxv)
Changes
### Description
This PR adds a new command-line option that allows users to specify the prefix
used for line-based anchors in repository URLs. Different repository interfaces
use different formats for line anchors (GitHub uses `#L123`, googlesource uses
`#123`, etc.). This option enables users to customize the line prefix
to match their repository platform without requiring hard-coded values for each
service.
Fix #59814
---
Patch is 26.52 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/131280.diff
6 Files Affected:
- (modified) clang-tools-extra/clang-doc/HTMLGenerator.cpp (+41-25)
- (modified) clang-tools-extra/clang-doc/MDGenerator.cpp (+6-1)
- (modified) clang-tools-extra/clang-doc/Representation.cpp (+4)
- (modified) clang-tools-extra/clang-doc/Representation.h (+4-1)
- (modified) clang-tools-extra/clang-doc/tool/ClangDocMain.cpp (+9-4)
- (added) clang-tools-extra/test/clang-doc/basic-project-with-line-prefix.test
(+342)
``diff
diff --git a/clang-tools-extra/clang-doc/HTMLGenerator.cpp
b/clang-tools-extra/clang-doc/HTMLGenerator.cpp
index 18a0de826630c..967275f93193b 100644
--- a/clang-tools-extra/clang-doc/HTMLGenerator.cpp
+++ b/clang-tools-extra/clang-doc/HTMLGenerator.cpp
@@ -491,9 +491,9 @@ genReferencesBlock(const std::vector &References,
return Out;
}
-static std::unique_ptr
-writeFileDefinition(const Location &L,
-std::optional RepositoryUrl = std::nullopt) {
+static std::unique_ptr writeFileDefinition(
+const Location &L, std::optional RepositoryUrl = std::nullopt,
+std::optional RepositoryLinePrefix = std::nullopt) {
if (!L.IsFileInRootDir && !RepositoryUrl)
return std::make_unique(
HTMLTag::TAG_P, "Defined at line " + std::to_string(L.LineNumber) +
@@ -514,17 +514,21 @@ writeFileDefinition(const Location &L,
Node->Children.emplace_back(std::make_unique("Defined at line "));
auto LocNumberNode =
std::make_unique(HTMLTag::TAG_A, std::to_string(L.LineNumber));
- // The links to a specific line in the source code use the github /
- // googlesource notation so it won't work for all hosting pages.
- // FIXME: we probably should have a configuration setting for line number
- // rendering in the HTML. For example, GitHub uses #L22, while googlesource
- // uses #22 for line numbers.
- LocNumberNode->Attributes.emplace_back(
- "href", (FileURL + "#" + std::to_string(L.LineNumber)).str());
+
+ std::string LineAnchor = "#";
+
+ if (RepositoryLinePrefix)
+LineAnchor += RepositoryLinePrefix.value().str();
+
+ LineAnchor += std::to_string(L.LineNumber);
+
+ LocNumberNode->Attributes.emplace_back("href", (FileURL + LineAnchor).str());
Node->Children.emplace_back(std::move(LocNumberNode));
Node->Children.emplace_back(std::make_unique(" of file "));
+
auto LocFileNode = std::make_unique(
HTMLTag::TAG_A, llvm::sys::path::filename(FileURL));
+
LocFileNode->Attributes.emplace_back("href", std::string(FileURL));
Node->Children.emplace_back(std::move(LocFileNode));
return Node;
@@ -750,11 +754,15 @@ genHTML(const EnumInfo &I, const ClangDocContext &CDCtx) {
Out.emplace_back(std::move(Table));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(
- writeFileDefinition(*I.DefLoc, StringRef{*CDCtx.RepositoryUrl}));
+std::optional RepoUrl;
+std::optional RepoLinePrefix;
+
+if (CDCtx.RepositoryUrl)
+ RepoUrl = StringRef{*CDCtx.RepositoryUrl};
+if (CDCtx.RepositoryLinePrefix)
+ RepoLinePrefix = StringRef{*CDCtx.RepositoryLinePrefix};
+
+Out.emplace_back(writeFileDefinition(*I.DefLoc, RepoUrl, RepoLinePrefix));
}
std::string Description;
@@ -799,11 +807,15 @@ genHTML(const FunctionInfo &I, const ClangDocContext
&CDCtx,
FunctionHeader->Children.emplace_back(std::make_unique(")"));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(writeFileDefinition(
- *I.DefLoc, StringRef{*CDCtx.RepositoryUrl}));
+std::optional RepoUrl;
+std::optional RepoLinePrefix;
+
+if (CDCtx.RepositoryUrl)
+ RepoUrl = StringRef{*CDCtx.RepositoryUrl};
+if (CDCtx.RepositoryLinePrefix)
+ RepoLinePrefix = StringRef{*CDCtx.RepositoryLinePrefix};
+
+Out.emplace_back(writeFileDefinition(*I.DefLoc, RepoUrl, RepoLinePrefix));
}
std::string Description;
@@ -866,11 +878,15 @@ genHTML(const RecordInfo &I, Index &InfoIndex, const
ClangDocContext &CDCtx,
Out.emplace_back(std::make_unique(HTMLTag::TAG_H1, InfoTitle));
if (I.DefLoc) {
-if (!CDCtx.RepositoryUrl)
- Out.emplace_back(writeFileDefinition(*I.DefLoc));
-else
- Out.emplace_back(writeFileDefinition(
- *I.DefLoc, Stri
[clang] [Sema] Avoid repeated hash lookups (NFC) (PR #131263)
https://github.com/cor3ntin approved this pull request. https://github.com/llvm/llvm-project/pull/131263 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang-doc] [feat] add --repository-line-prefix argument (PR #131280)
github-actions[bot] wrote: Thank you for submitting a Pull Request (PR) to the LLVM Project! This PR will be automatically labeled and the relevant teams will be notified. If you wish to, you can add reviewers by using the "Reviewers" section on this page. If this is not working for you, it is probably because you do not have write permissions for the repository. In which case you can instead tag reviewers by name in a comment by using `@` followed by their GitHub username. If you have received no comments on your PR for a week, you can request a review by "ping"ing the PR by adding a comment “Ping”. The common courtesy "ping" rate is once a week. Please remember that you are asking for valuable time from other developers. If you have further questions, they may be answered by the [LLVM GitHub User Guide](https://llvm.org/docs/GitHub.html). You can also ask questions in a comment on this PR, on the [LLVM Discord](https://discord.com/invite/xS7Z362) or on the [forums](https://discourse.llvm.org/). https://github.com/llvm/llvm-project/pull/131280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang-tools-extra] [clang-doc] [feat] add --repository-line-prefix argument (PR #131280)
https://github.com/hulxv edited https://github.com/llvm/llvm-project/pull/131280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
https://github.com/dong-miao updated https://github.com/llvm/llvm-project/pull/131094 >From bcdf9641037507b855a20a8ba5d26b127dd248e8 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 17:53:58 +0800 Subject: [PATCH 01/20] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 39853cf13a920..41b96e1497e70 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>; def : SysReg<"hvip", 0x645>; def : SysReg<"htinst", 0x64A>; def : SysReg<"hgeip", 0xE12>; +def : SysReg<"hedelegh", 0x612>; //===--===// // Hypervisor Configuration @@ -239,6 +240,7 @@ def : SysReg<"mbadaddr", 0x343>; def : SysReg<"mip", 0x344>; def : SysReg<"mtinst", 0x34A>; def : SysReg<"mtval2", 0x34B>; +def : SysReg<"medelegh", 0x312>; //===--===// // Machine Configuration >From 30e3fbe156581efe49a3c6def9dd444dc546f134 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 18:02:40 +0800 Subject: [PATCH 02/20] Update rv32-hypervisor-csr-names.s --- llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s | 18 ++ 1 file changed, 18 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s index aadee4fb4f3ad..79d87b3f2471c 100644 --- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s @@ -219,3 +219,21 @@ csrrs t2, 0x214, zero csrrs t1, vsiph, zero # uimm12 csrrs t2, 0x254, zero + +## +# Hypervisor Trap Setup +## + +# hedelegh +# name +# CHECK-INST: csrrs t1, hedelegh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x61] +# CHECK-INST-ALIAS: csrr t1, hedelegh +# uimm12 +# CHECK-INST: csrrs t2, hedelegh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x61] +# CHECK-INST-ALIAS: csrr t2, hedelegh +# name +csrrs t1, hedelegh, zero +# uimm12 +csrrs t2, 0x612, zero >From e41e745626caf701b2a21eb2577ead05b922f590 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sat, 4 Jan 2025 18:05:04 +0800 Subject: [PATCH 03/20] Update rv32-machine-csr-names.s --- llvm/test/MC/RISCV/rv32-machine-csr-names.s | 14 ++ 1 file changed, 14 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s index 3d527e382376e..9e929b7eddeed 100644 --- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s @@ -22,6 +22,20 @@ csrrs t1, mstatush, zero # uimm12 csrrs t2, 0x310, zero +# medelegh +# name +# CHECK-INST: csrrs t1, medelegh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x31] +# CHECK-INST-ALIAS: csrr t1, medelegh +# uimm12 +# CHECK-INST: csrrs t2, medelegh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x31] +# CHECK-INST-ALIAS: csrr t2, medelegh +# name +csrrs t1, medelegh, zero +# uimm12 +csrrs t2, 0x312, zero + # # Machine Configuration # >From ea2c1afaa0eede9cf9dfbf68d10fada108b0164b Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sun, 5 Jan 2025 11:12:53 +0800 Subject: [PATCH 04/20] Update RISCVSystemOperands.td --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 41b96e1497e70..21f912bbc84d1 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -158,6 +158,7 @@ def : SysReg<"hip", 0x644>; def : SysReg<"hvip", 0x645>; def : SysReg<"htinst", 0x64A>; def : SysReg<"hgeip", 0xE12>; +let isRV32Only = 1 in def : SysReg<"hedelegh", 0x612>; //===--===// @@ -240,6 +241,7 @@ def : SysReg<"mbadaddr", 0x343>; def : SysReg<"mip", 0x344>; def : SysReg<"mtinst", 0x34A>; def : SysReg<"mtval2", 0x34B>; +let isRV32Only = 1 in def : SysReg<"medelegh", 0x312>; //===--===// >From 6b074f3d744bdfaf2f4de9fa49484b25f76df3d4 Mon Sep 17 00:00:00 2001 From: dong-miao Date: Sun, 5 Jan 2025 11:30:33 +0800 Subject: [PATCH 05/20] Update rv32-only-csr-names.s --- llvm/test/MC/RISCV/rv32-only-csr-names.s | 4 1 file changed, 4 insertions(+) diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s index db88eacf9396b..1604469210193 100644 --- a/llvm/test/MC/RISCV/rv32-only-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s @@ -41,12 +41,16 @@ csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LIN
[clang] [clang][DependencyScanning] Track modules that resolve from sysroot. (PR #130634)
https://github.com/cyndyishida updated
https://github.com/llvm/llvm-project/pull/130634
>From aca254a154489fda68292f6d06a866ae7011a7f6 Mon Sep 17 00:00:00 2001
From: Cyndy Ishida
Date: Mon, 10 Mar 2025 09:06:32 -0700
Subject: [PATCH 1/3] [clang][DependencyScanning] Track modules that resolve
from sysroot.
That patch tracks whether all the file & module dependencies of a module
resolve to a sysroot location. This information will later be queried by
build systems for determining where to store the accompanying pcms.
---
.../DependencyScanning/ModuleDepCollector.h | 7 ++
.../DependencyScanning/ModuleDepCollector.cpp | 25 +++-
clang/test/ClangScanDeps/modules-in-sysroot.c | 107 ++
clang/tools/clang-scan-deps/ClangScanDeps.cpp | 2 +
4 files changed, 139 insertions(+), 2 deletions(-)
create mode 100644 clang/test/ClangScanDeps/modules-in-sysroot.c
diff --git
a/clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
b/clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
index 20fb4de6a2a73..6187f0168e6d9 100644
--- a/clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
+++ b/clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
@@ -114,6 +114,10 @@ struct ModuleDeps {
/// Whether this is a "system" module.
bool IsSystem;
+ /// Whether this is a module where it's dependencies resolve within the
+ /// sysroot.
+ bool IsInSysroot;
+
/// The path to the modulemap file which defines this module.
///
/// This can be used to explicitly build this module. This file will
@@ -219,6 +223,9 @@ class ModuleDepCollectorPP final : public PPCallbacks {
llvm::DenseSet &AddedModules);
void addAffectingClangModule(const Module *M, ModuleDeps &MD,
llvm::DenseSet &AddedModules);
+
+ /// Add discovered module dependency for the given module.
+ void addClangModule(const Module *M, const ModuleID ID, ModuleDeps &MD);
};
/// Collects modular and non-modular dependencies of the main file by attaching
diff --git a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
index 36b75c1016cd8..86eda34472cf0 100644
--- a/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
+++ b/clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
@@ -698,6 +698,15 @@ ModuleDepCollectorPP::handleTopLevelModule(const Module
*M) {
MD.ID.ModuleName = M->getFullModuleName();
MD.IsSystem = M->IsSystem;
+
+ // Start off with the assumption that this module is in the sysroot when
there
+ // is a sysroot provided. As more dependencies are discovered, check if those
+ // come from the provided sysroot.
+ const StringRef CurrSysroot = MDC.ScanInstance.getHeaderSearchOpts().Sysroot;
+ MD.IsInSysroot =
+ !CurrSysroot.empty() &&
+ (llvm::sys::path::root_directory(CurrSysroot) != CurrSysroot);
+
// For modules which use export_as link name, the linked product that of the
// corresponding export_as-named module.
if (!M->UseExportAsModuleLinkName)
@@ -739,6 +748,11 @@ ModuleDepCollectorPP::handleTopLevelModule(const Module
*M) {
MDC.ScanInstance.getASTReader()->visitInputFileInfos(
*MF, /*IncludeSystem=*/true,
[&](const serialization::InputFileInfo &IFI, bool IsSystem) {
+auto FullFilePath = ASTReader::ResolveImportedPath(
+PathBuf, IFI.UnresolvedImportedFilename, MF->BaseDirectory);
+if (MD.IsInSysroot)
+ MD.IsInSysroot = FullFilePath->starts_with(CurrSysroot);
+PathBuf.resize_for_overwrite(256);
if (!(IFI.TopLevel && IFI.ModuleMap))
return;
if (IFI.UnresolvedImportedFilenameAsRequested.ends_with(
@@ -835,6 +849,13 @@ void ModuleDepCollectorPP::addAllSubmoduleDeps(
});
}
+void ModuleDepCollectorPP::addClangModule(const Module *M, const ModuleID ID,
+ ModuleDeps &MD) {
+ MD.ClangModuleDeps.push_back(ID);
+ if (MD.IsInSysroot)
+MD.IsInSysroot = MDC.ModularDeps[M]->IsInSysroot;
+}
+
void ModuleDepCollectorPP::addModuleDep(
const Module *M, ModuleDeps &MD,
llvm::DenseSet &AddedModules) {
@@ -843,7 +864,7 @@ void ModuleDepCollectorPP::addModuleDep(
!MDC.isPrebuiltModule(Import)) {
if (auto ImportID = handleTopLevelModule(Import->getTopLevelModule()))
if (AddedModules.insert(Import->getTopLevelModule()).second)
- MD.ClangModuleDeps.push_back(*ImportID);
+ addClangModule(Import->getTopLevelModule(), *ImportID, MD);
}
}
}
@@ -867,7 +888,7 @@ void ModuleDepCollectorPP::addAffectingClangModule(
!MDC.isPrebuiltModule(Affecting)) {
if (auto ImportID = handleTopLevelModule(Affecting))
if (AddedModules.insert(Affecting).second)
- MD.ClangModuleDeps.push_back(*ImportID);
+ addClangModule(Affecting, *ImportID, MD);
}
}
}
diff --git a/clang/test/
[clang] [libc][nfc] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131134
>From 7347ebc6a0aadd1b9676e329bdf7705dbfae7875 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 12:49:42 +
Subject: [PATCH] [libc][nfc] Steps to allow sharing code between gpu intrin.h
headers
---
clang/lib/Headers/amdgpuintrin.h | 22 ++
clang/lib/Headers/gpuintrin.h| 26 +++---
clang/lib/Headers/nvptxintrin.h | 27 ---
3 files changed, 25 insertions(+), 50 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 839a05175cf3e..56748f6c3e818 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -13,11 +13,8 @@
#error "This file is intended for AMDGPU targets or offloading to AMDGPU"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -146,17 +143,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
return __builtin_amdgcn_ds_bpermute(__lane << 2, __x);
}
-// Shuffles the the lanes inside the wavefront according to the given index.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
- uint32_t __width) {
- uint32_t __hi = (uint32_t)(__x >> 32ull);
- uint32_t __lo = (uint32_t)(__x & 0x);
- return ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __hi, __width)
- << 32ull) |
- ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __lo, __width));
-}
-
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
@@ -238,8 +224,4 @@ _DEFAULT_FN_ATTRS static __inline__ void
__gpu_thread_suspend(void) {
_Pragma("omp end declare variant");
_Pragma("omp end declare target");
-#if !defined(__cplusplus)
-_Pragma("pop_macro(\"bool\")");
-#endif
-
#endif // __AMDGPUINTRIN_H
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index 4181628d18048..ac79d685337c5 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -25,6 +25,13 @@
#endif
#endif
+#include
+
+#if !defined(__cplusplus)
+_Pragma("push_macro(\"bool\")");
+#define bool _Bool
+#endif
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -33,13 +40,6 @@
#error "This header is only meant to be used on GPU architectures."
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
-#endif
-
_Pragma("omp begin declare target device_type(nohost)");
_Pragma("omp begin declare variant match(device = {kind(gpu)})");
@@ -141,6 +141,18 @@ __gpu_read_first_lane_f64(uint64_t __lane_mask, double
__x) {
__builtin_bit_cast(uint64_t, __x)));
}
+// Shuffles the the lanes according to the given index.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
+ uint32_t __width) {
+ uint32_t __hi = (uint32_t)(__x >> 32ull);
+ uint32_t __lo = (uint32_t)(__x & 0x);
+ uint32_t __mask = (uint32_t)__lane_mask;
+ return ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __hi, __width)
+ << 32ull) |
+ ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __lo, __width));
+}
+
// Shuffles the the lanes according to the given index.
_DEFAULT_FN_ATTRS static __inline__ float
__gpu_shuffle_idx_f32(uint64_t __lane_mask, uint32_t __idx, float __x,
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index d00a5f6de3950..10ad7a682d4cd 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -13,15 +13,12 @@
#error "This file is intended for NVPTX targets or offloading to NVPTX"
#endif
-#ifndef __CUDA_ARCH__
-#define __CUDA_ARCH__ 0
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __CUDA_ARCH__
+#define __CUDA_ARCH__ 0
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -153,18 +150,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
((__gpu_num_lanes() - __width) << 8u) |
0x1f);
}
-// Shuffles the the lanes inside the warp according to the given index.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
- uint32_t __width) {
- uint32_t __hi = (uint32_t)(__x >> 32ull);
- uint32_t __lo = (uint32_t)(__x & 0x);
- uint32_t __mask =
[clang] [MS][clang] Add support for vector deleting destructors (PR #126240)
AaronBallman wrote: > Yes, I'm prioritizing this today. I had hoped filteredbrk.obj was enough, but > I'm working on uploading full linker repros. > > It turns out another issue (https://crbug.com/402425841) also bisected to > this PR. That one is a run-time problem, so it may be trickier to figure out, > but I will look into it next. Thank you for the help, it's really appreciated! https://github.com/llvm/llvm-project/pull/126240 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [flang-rt] Pass the whole path of libflang_rt.runtime.a to linker on AIX (PR #131041)
https://github.com/Meinersbur edited https://github.com/llvm/llvm-project/pull/131041 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Lex: add support for `i128` and `ui128` suffixes (PR #130993)
@@ -3924,10 +3924,18 @@ ExprResult Sema::ActOnNumericConstant(const Token &Tok,
Scope *UDLScope) {
// to get the integer value from an overly-wide APInt is *extremely*
// expensive, so the naive approach of assuming
// llvm::IntegerType::MAX_INT_BITS is a big performance hit.
-unsigned BitsNeeded =
-Literal.isBitInt ? llvm::APInt::getSufficientBitsNeeded(
- Literal.getLiteralDigits(), Literal.getRadix())
- : Context.getTargetInfo().getIntMaxTWidth();
+unsigned BitsNeeded = Context.getTargetInfo().getIntMaxTWidth();
+if (Literal.isBitInt)
+ BitsNeeded = llvm::APInt::getSufficientBitsNeeded(
+ Literal.getLiteralDigits(), Literal.getRadix());
+if (Literal.MicrosoftInteger) {
+ if (Literal.MicrosoftInteger == 128 &&
Fznamznon wrote:
Do we really have to check `Literal.MicrosoftInteger` two times?
```suggestion
if (Literal.MicrosoftInteger == 128 &&
```
https://github.com/llvm/llvm-project/pull/130993
___
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[clang] [flang] [flang] Add support for -f[no-]verbose-asm (PR #130788)
https://github.com/tarunprabhu approved this pull request. Thanks for all the changes, Tom! LGTM. https://github.com/llvm/llvm-project/pull/130788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131141
>From 28cb801f73e6886eacfd5cdbcd17abb68b6dd947 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_any between targets
---
clang/lib/Headers/amdgpuintrin.h | 34 ++
clang/lib/Headers/gpuintrin.h| 60 +++-
clang/lib/Headers/nvptxintrin.h | 36 +++
3 files changed, 65 insertions(+), 65 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..7176fcc1c353a 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,39 +142,13 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u64(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..30aa32e8363eb 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,26 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Forward declare a few functions for the implementation header.
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x);
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u64(uint64_t __lane_mask, uint64_t __x);
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +135,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
@@ -234,6 +254,44 @@ __DO_LANE_SUM(float, f32);// float
__gpu_lane_sum_f32(m, x)
__DO_LANE_SUM(double, f64); // double __gpu_lane_sum_f64(m, x)
#undef __DO_LANE_SUM
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(
[clang] Reduce memory usage in AST parent map generation by lazily checking if nodes have been seen (PR #129934)
https://github.com/erichkeane approved this pull request. Interesting... this ends up just being a set-vector with a different identity being stored for the set. So this ends up being ~4 ptr-sizes (IIRC you said that DynTypedNode is 3x the size of a pointer) per-record (though the extra 1 is only for those with memoization data). Did you run the space benchmark here from the original bug? I definitely believe that this is an improvement (changes from 6x-ptr/element to < 4x-ptr/element), and perhaps the deduplication makes up for the extra data (since it only has to remove ONE duplicate to make up for 3 elements). AS FAR AS the `SmallVector`/`SmallDenseSet` vs `std::vector`/`std::set`, the decision here is interesting. `SmallVector` has a pretty massive stack size in exchange for saving on an allocation (it isn't SSO-like, it is more, "size-of-vector + N, so that our allocation is on-stack unless size > N). So it kinda depends on whether we think MOST uses of this are going to be '1' element, vs '0' or '1+' (that is, for the small-vector suggested by @cor3ntin of size 1). If it is almost always going to be 1, I agree with him. If it is almost always going to be 0 or more than 1, std::vector is probably correct (as in the 0 case, std::vector is smaller, and in the 1+ case, the allocation is happening anyway, and we just have dead stack space again). https://github.com/llvm/llvm-project/pull/129934 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Qualcomn uC Xqcili (load large immediates) extension (PR #130012)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/130012 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 01aca42 - [flang] Add support for -f[no-]verbose-asm (#130788)
Author: Tom Eccles
Date: 2025-03-13T15:22:13Z
New Revision: 01aca42363ac18f29580d21f6a30af677c2581b9
URL:
https://github.com/llvm/llvm-project/commit/01aca42363ac18f29580d21f6a30af677c2581b9
DIFF:
https://github.com/llvm/llvm-project/commit/01aca42363ac18f29580d21f6a30af677c2581b9.diff
LOG: [flang] Add support for -f[no-]verbose-asm (#130788)
This flag provides extra commentary in the assembly output.
Added:
flang/test/Driver/verbose-asm.f90
Modified:
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/Flang.cpp
flang/include/flang/Frontend/TargetOptions.h
flang/lib/Frontend/CompilerInvocation.cpp
flang/lib/Frontend/FrontendActions.cpp
Removed:
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index e69cd6b833c3a..ac6392f92f311 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -3467,7 +3467,7 @@ defm use_cxa_atexit : BoolFOption<"use-cxa-atexit",
PosFlag>;
def fno_unwind_tables : Flag<["-"], "fno-unwind-tables">, Group;
def fno_verbose_asm : Flag<["-"], "fno-verbose-asm">, Group,
- Visibility<[ClangOption, CC1Option]>,
+ Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>,
MarshallingInfoNegativeFlag>;
def fno_working_directory : Flag<["-"], "fno-working-directory">,
Group;
def fobjc_arc : Flag<["-"], "fobjc-arc">, Group,
@@ -4142,7 +4142,8 @@ defm use_init_array : BoolFOption<"use-init-array",
PosFlag>;
def fno_var_tracking : Flag<["-"], "fno-var-tracking">,
Group;
def fverbose_asm : Flag<["-"], "fverbose-asm">, Group,
- HelpText<"Generate verbose assembly output">;
+ HelpText<"Generate verbose assembly output">,
+ Visibility<[ClangOption, CC1Option, FlangOption, FC1Option]>;
def dA : Flag<["-"], "dA">, Alias;
defm visibility_from_dllstorageclass :
BoolFOption<"visibility-from-dllstorageclass",
LangOpts<"VisibilityFromDLLStorageClass">, DefaultFalse,
diff --git a/clang/lib/Driver/ToolChains/Flang.cpp
b/clang/lib/Driver/ToolChains/Flang.cpp
index 3ee305fc0460d..5dbc5cbe77d0a 100644
--- a/clang/lib/Driver/ToolChains/Flang.cpp
+++ b/clang/lib/Driver/ToolChains/Flang.cpp
@@ -514,6 +514,9 @@ void Flang::addTargetOptions(const ArgList &Args,
else
CmdArgs.push_back(A->getValue());
}
+
+ Args.addAllArgs(CmdArgs,
+ {options::OPT_fverbose_asm, options::OPT_fno_verbose_asm});
}
void Flang::addOffloadOptions(Compilation &C, const InputInfoList &Inputs,
diff --git a/flang/include/flang/Frontend/TargetOptions.h
b/flang/include/flang/Frontend/TargetOptions.h
index 4a854644e7ff6..002d8d158abd4 100644
--- a/flang/include/flang/Frontend/TargetOptions.h
+++ b/flang/include/flang/Frontend/TargetOptions.h
@@ -50,6 +50,9 @@ class TargetOptions {
/// Extended Altivec ABI on AIX
bool EnableAIXExtendedAltivecABI;
+
+ /// Print verbose assembly
+ bool asmVerbose = false;
};
} // end namespace Fortran::frontend
diff --git a/flang/lib/Frontend/CompilerInvocation.cpp
b/flang/lib/Frontend/CompilerInvocation.cpp
index 1537122ddced5..edf738785fb97 100644
--- a/flang/lib/Frontend/CompilerInvocation.cpp
+++ b/flang/lib/Frontend/CompilerInvocation.cpp
@@ -476,6 +476,10 @@ static void parseTargetArgs(TargetOptions &opts,
llvm::opt::ArgList &args) {
opts.EnableAIXExtendedAltivecABI = false;
}
}
+
+ opts.asmVerbose =
+ args.hasFlag(clang::driver::options::OPT_fverbose_asm,
+ clang::driver::options::OPT_fno_verbose_asm, false);
}
// Tweak the frontend configuration based on the frontend action
static void setUpFrontendBasedOnAction(FrontendOptions &opts) {
diff --git a/flang/lib/Frontend/FrontendActions.cpp
b/flang/lib/Frontend/FrontendActions.cpp
index 94de376aaf7d6..46ec7550e4140 100644
--- a/flang/lib/Frontend/FrontendActions.cpp
+++ b/flang/lib/Frontend/FrontendActions.cpp
@@ -1220,6 +1220,7 @@ void CodeGenAction::executeAction() {
clang::DiagnosticsEngine &diags = ci.getDiagnostics();
const CodeGenOptions &codeGenOpts = ci.getInvocation().getCodeGenOpts();
+ const TargetOptions &targetOpts = ci.getInvocation().getTargetOpts();
Fortran::lower::LoweringOptions &loweringOpts =
ci.getInvocation().getLoweringOpts();
mlir::DefaultTimingManager &timingMgr = ci.getTimingManager();
@@ -1284,6 +1285,8 @@ void CodeGenAction::executeAction() {
// given on the command-line).
llvm::TargetMachine &targetMachine = ci.getTargetMachine();
+ targetMachine.Options.MCOptions.AsmVerbose = targetOpts.asmVerbose;
+
const llvm::Triple &theTriple = targetMachine.getTargetTriple();
if (llvmModule->getTargetTriple() != theTriple) {
diff --git a/flang/test/Driver/verbose-asm.f90
b/flang/test/Driver/verbose-asm.f90
new file mode 100644
index 0..7cadf19b32d3c
--- /dev/null
+++ b/flang/test/Driver/verbose-asm.f90
@@ -0,0 +1,16 @@
+! RUN: %flang -### -S
[clang] [flang] [flang] Add support for -f[no-]verbose-asm (PR #130788)
https://github.com/tblah closed https://github.com/llvm/llvm-project/pull/130788 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+ let Name = "GPRPairNoX0RV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairNoX0";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+ let Name = "GPRPairCRV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairC";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32,
uimm9_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ let Inst{4-2} = imm{8-6};
+ }
topperc wrote:
Closing curly brace should be at the start of the line.
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,36 @@ +//===-- RISCVInstrInfoZilsd.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file describes the RISC-V instructions from the standard 'Zilsd', +// Load/Store pair instructions extension. +// +//===--===// +// Instruction Class Templates +//===--===// + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class ld_r topperc wrote: ld_r -> PairLoad_ri? https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -401,6 +408,14 @@ def FeatureStdExtZcf "Compressed Single-Precision Floating-Point Instructions", [FeatureStdExtF, FeatureStdExtZca]>; +def FeatureStdExtZclsd +: RISCVExtension<1, 0, + "Compressed Load/Store pair instructions", + [FeatureStdExtZilsd,FeatureStdExtZca]>; +def HasStdExtZclsd : Predicate<"Subtarget->hasStdExtZclsd() && !Subtarget->hasStdExtZcf()">, topperc wrote: The conflict with Zcf needs to be checked in `RISCVISAInfo::checkDependency` in llvm/lib/TargetParser/RISCVISAInfo.cpp https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,90 @@ +//===-- RISCVInstrInfoZclsd.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// This file describes the RISC-V instructions from the standard 'Zclsd', +// Compressed Load/Store pair instructions extension. +//===--===// +// Instruction Class Templates topperc wrote: Please add a blank line and another horizontal line to separate this from the file header. https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd),
+(ins GPRMem:$rs1, simm12:$imm12),
+ opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r
topperc wrote:
PairStore_rri?
https://github.com/llvm/llvm-project/pull/131094
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[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,36 @@
+//===-- RISCVInstrInfoZilsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the RISC-V instructions from the standard 'Zilsd',
+// Load/Store pair instructions extension.
+//
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class ld_r
+: RVInstI<0b011, OPC_LOAD, (outs RC:$rd),
+(ins GPRMem:$rs1, simm12:$imm12),
+ opcodestr, "${rd}, ${imm12}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class sd_r
+: RVInstS<0b011, OPC_STORE, (outs),
+ (ins RC:$rs2, GPRMem:$rs1, simm12:$imm12),
topperc wrote:
Indent `ins` one more space
https://github.com/llvm/llvm-project/pull/131094
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[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131141 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang-format] Add support for absl nullability macros (PR #130346)
@@ -3185,6 +3185,53 @@ TEST_F(TokenAnnotatorTest, UnderstandsAttributes) {
EXPECT_TOKEN(Tokens[5], tok::r_paren, TT_AttributeRParen);
}
+TEST_F(TokenAnnotatorTest, UnderstandsNullabilityAttributes) {
+ auto Tokens = annotate("x = (foo *_Nullable)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Nullable, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ Tokens = annotate("x = (foo *_Nonnull)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Nonnull, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ Tokens = annotate("x = (foo *_Null_unspecified)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Null_unspecified, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ // Under Google style, also handles the Abseil macro aliases for the
+ // nullability annotations.
+ FormatStyle Style = getGoogleStyle(FormatStyle::LK_Cpp);
+ Tokens = annotate("x = (foo *absl_nullable)*v;", Style);
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::identifier, TT_AttributeMacro);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ Tokens = annotate("x = (foo *absl_nonnull)*v;", Style);
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
jvoung wrote:
Done
https://github.com/llvm/llvm-project/pull/130346
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[clang] [clang-format] Add support for absl nullability macros (PR #130346)
@@ -3185,6 +3185,53 @@ TEST_F(TokenAnnotatorTest, UnderstandsAttributes) {
EXPECT_TOKEN(Tokens[5], tok::r_paren, TT_AttributeRParen);
}
+TEST_F(TokenAnnotatorTest, UnderstandsNullabilityAttributes) {
+ auto Tokens = annotate("x = (foo *_Nullable)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Nullable, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ Tokens = annotate("x = (foo *_Nonnull)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Nonnull, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ Tokens = annotate("x = (foo *_Null_unspecified)*v;");
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
+ EXPECT_TOKEN(Tokens[4], tok::star, TT_PointerOrReference);
+ EXPECT_TOKEN(Tokens[5], tok::kw__Null_unspecified, TT_Unknown);
+ EXPECT_TOKEN(Tokens[7], tok::star, TT_UnaryOperator);
+
+ // Under Google style, also handles the Abseil macro aliases for the
+ // nullability annotations.
+ FormatStyle Style = getGoogleStyle(FormatStyle::LK_Cpp);
+ Tokens = annotate("x = (foo *absl_nullable)*v;", Style);
+ ASSERT_EQ(Tokens.size(), 11u) << Tokens;
+ EXPECT_TOKEN(Tokens[3], tok::identifier, TT_Unknown);
jvoung wrote:
Done
https://github.com/llvm/llvm-project/pull/130346
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[clang] [libc][nfc] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
https://github.com/jhuber6 approved this pull request. LG https://github.com/llvm/llvm-project/pull/131141 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][SYCL] Disable float128 device mode diagnostic (PR #128513)
@@ -4700,7 +4700,8 @@ void Sema::AddModeAttr(Decl *D, const AttributeCommonInfo
&CI,
if (NewElemTy.isNull()) {
// Only emit diagnostic on host for 128-bit mode attribute
-if (!(DestWidth == 128 && getLangOpts().CUDAIsDevice))
+if (!(DestWidth == 128 &&
+ (getLangOpts().CUDAIsDevice || getLangOpts().SYCLIsDevice)))
npmiller wrote:
No I'm not very familiar with this part of the compiler, and even less with
OpenMP.
https://github.com/llvm/llvm-project/pull/128513
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[clang] [clang] Remove usage of llvm-spirv in clang LIT tests (PR #131158)
https://github.com/sarnex edited https://github.com/llvm/llvm-project/pull/131158 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang codegen][PPC] Produce AIX-specific "target features" only for AIX (PR #130864)
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[clang] 2044dd0 - [InstrProf] Remove -forder-file-instrumentation (#130192)
Author: Ellis Hoag
Date: 2025-03-13T08:28:16-07:00
New Revision: 2044dd07da99714bbeb801bafe6dd5179493fd48
URL:
https://github.com/llvm/llvm-project/commit/2044dd07da99714bbeb801bafe6dd5179493fd48
DIFF:
https://github.com/llvm/llvm-project/commit/2044dd07da99714bbeb801bafe6dd5179493fd48.diff
LOG: [InstrProf] Remove -forder-file-instrumentation (#130192)
Added:
Modified:
clang/docs/UsersManual.rst
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChain.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Driver/ToolChains/SYCL.cpp
clang/test/Driver/clang_f_opts.c
compiler-rt/include/profile/InstrProfData.inc
compiler-rt/include/profile/instr_prof_interface.h
compiler-rt/lib/profile/InstrProfiling.h
compiler-rt/lib/profile/InstrProfilingFile.c
compiler-rt/lib/profile/InstrProfilingPlatformAIX.c
compiler-rt/lib/profile/InstrProfilingPlatformDarwin.c
compiler-rt/lib/profile/InstrProfilingPlatformLinux.c
compiler-rt/lib/profile/InstrProfilingPlatformOther.c
compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
lld/test/MachO/start-end.s
llvm/include/llvm/ProfileData/InstrProfData.inc
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Passes/PassBuilderPipelines.cpp
llvm/lib/Passes/PassRegistry.def
llvm/lib/Transforms/Instrumentation/CMakeLists.txt
llvm/utils/gn/secondary/llvm/lib/Transforms/Instrumentation/BUILD.gn
Removed:
compiler-rt/test/profile/Inputs/instrprof-order-file.c
compiler-rt/test/profile/instrprof-order-file.test
llvm/include/llvm/Transforms/Instrumentation/InstrOrderFile.h
llvm/lib/Transforms/Instrumentation/InstrOrderFile.cpp
llvm/test/Instrumentation/InstrOrderFile/basic.ll
diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst
index b4a99d5e8..2ea4b9d90ad34 100644
--- a/clang/docs/UsersManual.rst
+++ b/clang/docs/UsersManual.rst
@@ -3195,7 +3195,6 @@ be collected.
the profile file to ``Name``.
* ``void __llvm_profile_reset_counters(void)``: resets all counters to zero.
* ``int __llvm_profile_dump(void)``: write the profile data to disk.
- * ``int __llvm_orderfile_dump(void)``: write the order file to disk.
For example, the following pattern can be used to skip profiling program
initialization, profile two specific hot regions, and skip profiling program
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index ac6392f92f311..66ae8f1c7f064 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -1811,15 +1811,13 @@ def fprofile_continuous : Flag<["-"],
"fprofile-continuous">,
HelpText<"Enable continuous instrumentation profiling mode">,
MarshallingInfoFlag>;
-defm pseudo_probe_for_profiling : BoolFOption<"pseudo-probe-for-profiling",
- CodeGenOpts<"PseudoProbeForProfiling">, DefaultFalse,
- PosFlag,
- NegFlag,
- BothFlags<[], [ClangOption, CC1Option],
- " pseudo probes for sample profiling">>;
-def forder_file_instrumentation : Flag<["-"], "forder-file-instrumentation">,
-Group, Visibility<[ClangOption, CC1Option, CLOption]>,
-HelpText<"Generate instrumented code to collect order file into
default.profraw file (overridden by '=' form of option or LLVM_PROFILE_FILE env
var). Deprecated, please use -ftemporal-profile">;
+defm pseudo_probe_for_profiling
+: BoolFOption<"pseudo-probe-for-profiling",
+ CodeGenOpts<"PseudoProbeForProfiling">, DefaultFalse,
+ PosFlag,
+ NegFlag,
+ BothFlags<[], [ClangOption, CC1Option],
+" pseudo probes for sample profiling">>;
def fprofile_list_EQ : Joined<["-"], "fprofile-list=">,
Group, Visibility<[ClangOption, CC1Option, CLOption]>,
HelpText<"Filename defining the list of functions/files to instrument. "
diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp
index f3bafbd01c5af..5f75d004eede0 100644
--- a/clang/lib/Driver/ToolChain.cpp
+++ b/clang/lib/Driver/ToolChain.cpp
@@ -955,7 +955,6 @@ bool ToolChain::needsProfileRT(const ArgList &Args) {
Args.hasArg(options::OPT_fprofile_instr_generate) ||
Args.hasArg(options::OPT_fprofile_instr_generate_EQ) ||
Args.hasArg(options::OPT_fcreate_profile) ||
- Args.hasArg(options::OPT_forder_file_instrumentation) ||
Args.hasArg(options::OPT_fprofile_generate_cold_function_coverage) ||
Args.hasArg(options::OPT_fprofile_generate_cold_function_coverage_EQ);
}
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index a6a96286e9857..fe172d923ac07 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -8030,21 +8030,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
}
}
- if (const
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,90 @@
+//===-- RISCVInstrInfoZclsd.td -*- tablegen
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+// This file describes the RISC-V instructions from the standard 'Zclsd',
+// Compressed Load/Store pair instructions extension.
+//===--===//
+// Instruction Class Templates
+//===--===//
+
+def GPRPairNoX0RV32Operand : AsmOperandClass {
+ let Name = "GPRPairNoX0RV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairNoX0";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairNoX0RV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairNoX0RV32Operand;
+}
+
+def GPRPairCRV32Operand : AsmOperandClass {
+ let Name = "GPRPairCRV32";
+ let ParserMethod = "parseGPRPair";
+ let PredicateMethod = "isGPRPairC";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRPairCRV32 : RegisterOperand {
+ let ParserMatchClass = GPRPairCRV32Operand;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCStackLoad funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CI;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStackStore funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CSS;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class PairCLoad_ri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CL;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class PairCStore_rri funct3, string OpcodeStr,
+ DAGOperand RC, DAGOperand opnd>
+: RVInst16CS;
+
+//===--===//
+// Instructions
+//===--===//
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LDSP_RV32 : PairCStackLoad<0b011, "c.ldsp", GPRPairNoX0RV32,
uimm9_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ let Inst{4-2} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SDSP_RV32 : PairCStackStore<0b111, "c.sdsp", GPRPairRV32, uimm9_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ let Inst{9-7} = imm{8-6};
+ }
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_LD_RV32 : PairCLoad_ri<0b011, "c.ld", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteLDD, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}
+
+let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in
+def C_SD_RV32 : PairCStore_rri<0b111, "c.sd", GPRPairCRV32, uimm8_lsb000>,
+ Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
+ bits<8> imm;
+ let Inst{12-10} = imm{5-3};
+ let Inst{6-5} = imm{7-6};
+}// Predicates = [HasStdExtZclsd, IsRV32]
topperc wrote:
Missing CompressPats? They're considered part of the MC layer since they effect
the assembler.
https://github.com/llvm/llvm-project/pull/131094
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[clang] [clang-format] Add support for absl nullability macros (PR #130346)
https://github.com/jvoung updated
https://github.com/llvm/llvm-project/pull/130346
>From 10df1857532a6a27b0e5286e10c9f0724d6d7e1d Mon Sep 17 00:00:00 2001
From: Jan Voung
Date: Fri, 7 Mar 2025 21:02:16 +
Subject: [PATCH 1/8] [clang-format] Add support for absl nullability macros
---
clang/lib/Format/Format.cpp| 4
clang/unittests/Format/ConfigParseTest.cpp | 4 +++-
clang/unittests/Format/FormatTest.cpp | 19 +--
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index b5f1241321891..1401b51586d03 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -1508,6 +1508,10 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind
Language) {
LLVMStyle.AlwaysBreakAfterDefinitionReturnType = FormatStyle::DRTBS_None;
LLVMStyle.AlwaysBreakBeforeMultilineStrings = false;
LLVMStyle.AttributeMacros.push_back("__capability");
+ // Abseil aliases to clang's `_Nonnull`, `_Nullable` and `_Null_unspecified`.
+ LLVMStyle.AttributeMacros.push_back("absl_nonnull");
+ LLVMStyle.AttributeMacros.push_back("absl_nullable");
+ LLVMStyle.AttributeMacros.push_back("absl_nullability_unknown");
LLVMStyle.BinPackArguments = true;
LLVMStyle.BinPackLongBracedList = true;
LLVMStyle.BinPackParameters = FormatStyle::BPPS_BinPack;
diff --git a/clang/unittests/Format/ConfigParseTest.cpp
b/clang/unittests/Format/ConfigParseTest.cpp
index 273bab87b1ee1..2cc2a45a7a590 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -908,7 +908,9 @@ TEST(ConfigParseTest, ParsesConfiguration) {
Style.AttributeMacros.clear();
CHECK_PARSE("BasedOnStyle: LLVM", AttributeMacros,
- std::vector{"__capability"});
+ std::vector({"__capability", "absl_nonnull",
"absl_nullable",
+"absl_nullability_unknown"}));
+ Style.AttributeMacros.clear();
CHECK_PARSE("AttributeMacros: [attr1, attr2]", AttributeMacros,
std::vector({"attr1", "attr2"}));
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index bd335f4b6a21b..a17cad0b67b08 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -12375,6 +12375,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
@@ -12518,6 +12521,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyIndependentOfContext("MACRO(A *_Nonnull a);");
verifyIndependentOfContext("MACRO(A *_Nullable a);");
verifyIndependentOfContext("MACRO(A *_Null_unspecified a);");
+ verifyIndependentOfContext("MACRO(A *absl_nonnull a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullable a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullability_unknown a);");
verifyIndependentOfContext("MACRO(A *__attribute__((foo)) a);");
verifyIndependentOfContext("MACRO(A *__attribute((foo)) a);");
verifyIndependentOfContext("MACRO(A *[[clang::attr]] a);");
@@ -12674,6 +12680,12 @@ TEST_F(FormatTest, UnderstandsAttributes) {
verifyFormat("SomeType *__unused s{InitValue};", CustomAttrs);
verifyFormat("SomeType s __unused(InitValue);", CustomAttrs);
verifyFormat("SomeType s __unused{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s(InitValue);",
CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s{InitValue};",
CustomAttrs);
verifyFormat("SomeType *__capability s(InitValue);", CustomAttrs);
verifyFormat("SomeType *__capability s{InitValue};", CustomAttrs);
}
@@ -12687,7 +12699,9 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
verifyFormat("x = (foo *_Nonnull)*v;");
verifyFormat("x = (foo *_Nullable)*v;");
verifyFormat("x = (foo *_Null_unspecified)*v;");
- verifyFormat("x = (foo *_Nonnull)*v;");
+ verifyFormat("x = (foo *absl_nonnull)*v;");
+ verifyFormat("x = (foo *absl_nullable)*v;");
+ verifyFormat("x = (foo *absl_nullability_unknown)*v;");
verifyFormat("x = (foo *[[clang::attr]])*v;");
verifyFormat("x = (foo *[[clang::attr(\"foo\")]])*v;");
verifyFormat("x = (foo *__ptr32)*v;");
@@ -12701,7 +12715,8 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
LongPointerLeft.PointerAlignment = FormatStyle::PAS_Left;
StringRef AllQualifiers =
"const volatile restrict __attribute__((foo)) _Nonnull _Null_unspecified
"
-
[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
@@ -32,6 +32,31 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Forward declare a few functions for the implementation header.
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x);
JonChesterfield wrote:
Sure, done
https://github.com/llvm/llvm-project/pull/131141
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[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 7e9802f - [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (#131134)
Author: Jon Chesterfield
Date: 2025-03-13T13:17:52Z
New Revision: 7e9802f348e36bf826d9fe83d0d187478e0e9639
URL:
https://github.com/llvm/llvm-project/commit/7e9802f348e36bf826d9fe83d0d187478e0e9639
DIFF:
https://github.com/llvm/llvm-project/commit/7e9802f348e36bf826d9fe83d0d187478e0e9639.diff
LOG: [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers
(#131134)
Adds macro guards to error if the implementation headers are included
directly as part of dropping the need for them to be standalone. Lifts
the bool macro into gpuintrin.h.
Moves shuffle_idx_u64 into gpuintrin in passing, was the same
implementation in each architecture file.
Added:
Modified:
clang/lib/Headers/amdgpuintrin.h
clang/lib/Headers/gpuintrin.h
clang/lib/Headers/nvptxintrin.h
Removed:
diff --git a/clang/lib/Headers/amdgpuintrin.h
b/clang/lib/Headers/amdgpuintrin.h
index 839a05175cf3e..56748f6c3e818 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -13,11 +13,8 @@
#error "This file is intended for AMDGPU targets or offloading to AMDGPU"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -146,17 +143,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
return __builtin_amdgcn_ds_bpermute(__lane << 2, __x);
}
-// Shuffles the the lanes inside the wavefront according to the given index.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
- uint32_t __width) {
- uint32_t __hi = (uint32_t)(__x >> 32ull);
- uint32_t __lo = (uint32_t)(__x & 0x);
- return ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __hi, __width)
- << 32ull) |
- ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __lo, __width));
-}
-
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
@@ -238,8 +224,4 @@ _DEFAULT_FN_ATTRS static __inline__ void
__gpu_thread_suspend(void) {
_Pragma("omp end declare variant");
_Pragma("omp end declare target");
-#if !defined(__cplusplus)
-_Pragma("pop_macro(\"bool\")");
-#endif
-
#endif // __AMDGPUINTRIN_H
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index 4181628d18048..ac79d685337c5 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -25,6 +25,13 @@
#endif
#endif
+#include
+
+#if !defined(__cplusplus)
+_Pragma("push_macro(\"bool\")");
+#define bool _Bool
+#endif
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -33,13 +40,6 @@
#error "This header is only meant to be used on GPU architectures."
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
-#endif
-
_Pragma("omp begin declare target device_type(nohost)");
_Pragma("omp begin declare variant match(device = {kind(gpu)})");
@@ -141,6 +141,18 @@ __gpu_read_first_lane_f64(uint64_t __lane_mask, double
__x) {
__builtin_bit_cast(uint64_t, __x)));
}
+// Shuffles the the lanes according to the given index.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
+ uint32_t __width) {
+ uint32_t __hi = (uint32_t)(__x >> 32ull);
+ uint32_t __lo = (uint32_t)(__x & 0x);
+ uint32_t __mask = (uint32_t)__lane_mask;
+ return ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __hi, __width)
+ << 32ull) |
+ ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __lo, __width));
+}
+
// Shuffles the the lanes according to the given index.
_DEFAULT_FN_ATTRS static __inline__ float
__gpu_shuffle_idx_f32(uint64_t __lane_mask, uint32_t __idx, float __x,
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index d00a5f6de3950..10ad7a682d4cd 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -13,15 +13,12 @@
#error "This file is intended for NVPTX targets or offloading to NVPTX"
#endif
-#ifndef __CUDA_ARCH__
-#define __CUDA_ARCH__ 0
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __CUDA_ARCH__
+#define __CUDA_ARCH__ 0
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -153,18 +150,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
((__gpu_num_lanes() - __width) << 8u) |
0x1f);
}
-// Shuffles the
[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/jhuber6 edited https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/jhuber6 approved this pull request. LG https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield created
https://github.com/llvm/llvm-project/pull/131141
Declare a few functions before including the target specific headers then
define a fallback_match_any, used by amdgpu and by older nvptx.
>From b9fdef141a83969eff8e7ac2dbc8c98163c0fbf5 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_any between targets
---
clang/lib/Headers/amdgpuintrin.h | 19 +
clang/lib/Headers/gpuintrin.h| 48 +++-
clang/lib/Headers/nvptxintrin.h | 19 ++---
3 files changed, 50 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..74054068c9714 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,20 +142,7 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..e4a9a49e10e1f 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,52 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Returns the bit-mask of active threads in the current warp or wavefront.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_lane_mask(void) {
+
+// Returns a bitmask of threads in the current lane for which \p x is true.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_ballot(uint64_t __lane_mask,
+ bool __x);
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint32_t
+__gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x) {
+
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(__lane_mask);
+ return __match_mask;
+}
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +161,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index 10ad7a682d4cd..1da9402040b52 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -34,10 +34,6 @@ _Pragma("omp begin declare variant match(device =
{arch(nvptx64)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((nvptx_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEF
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131141
>From 42253295a3b11b4303e15c3455047e3bfc5d196a Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_any between targets
---
clang/lib/Headers/amdgpuintrin.h | 19 +
clang/lib/Headers/gpuintrin.h| 48 +++-
clang/lib/Headers/nvptxintrin.h | 19 ++---
3 files changed, 50 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..74054068c9714 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,20 +142,7 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..811356b1f1deb 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,52 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Returns the bit-mask of active threads in the current warp or wavefront.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_lane_mask(void) {
+
+// Returns a bitmask of threads in the current lane for which \p x is true.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_ballot(uint64_t __lane_mask,
+ bool __x);
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint32_t
+ __gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x);
+
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(__lane_mask);
+ return __match_mask;
+}
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +161,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index 10ad7a682d4cd..1da9402040b52 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -34,10 +34,6 @@ _Pragma("omp begin declare variant match(device =
{arch(nvptx64)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((nvptx_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of CUDA b
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
llvmbot wrote:
@llvm/pr-subscribers-clang
Author: Jon Chesterfield (JonChesterfield)
Changes
Declare a few functions before including the target specific headers then
define a fallback_match_any, used by amdgpu and by older nvptx.
---
Full diff: https://github.com/llvm/llvm-project/pull/131141.diff
3 Files Affected:
- (modified) clang/lib/Headers/amdgpuintrin.h (+1-18)
- (modified) clang/lib/Headers/gpuintrin.h (+47-1)
- (modified) clang/lib/Headers/nvptxintrin.h (+2-17)
``diff
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..74054068c9714 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,20 +142,7 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..e4a9a49e10e1f 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,52 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Returns the bit-mask of active threads in the current warp or wavefront.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_lane_mask(void) {
+
+// Returns a bitmask of threads in the current lane for which \p x is true.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_ballot(uint64_t __lane_mask,
+ bool __x);
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint32_t
+__gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x) {
+
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(__lane_mask);
+ return __match_mask;
+}
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +161,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index 10ad7a682d4cd..1da9402040b52 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -34,10 +34,6 @@ _Pragma("omp begin declare variant match(device =
{arch(nvptx64)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((nvptx_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of CUDA blocks in the 'x' dimension.
_
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
llvmbot wrote:
@llvm/pr-subscribers-backend-amdgpu
Author: Jon Chesterfield (JonChesterfield)
Changes
Declare a few functions before including the target specific headers then
define a fallback_match_any, used by amdgpu and by older nvptx.
---
Full diff: https://github.com/llvm/llvm-project/pull/131141.diff
3 Files Affected:
- (modified) clang/lib/Headers/amdgpuintrin.h (+1-18)
- (modified) clang/lib/Headers/gpuintrin.h (+47-1)
- (modified) clang/lib/Headers/nvptxintrin.h (+2-17)
``diff
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..74054068c9714 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,20 +142,7 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..e4a9a49e10e1f 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,52 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Returns the bit-mask of active threads in the current warp or wavefront.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_lane_mask(void) {
+
+// Returns a bitmask of threads in the current lane for which \p x is true.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_ballot(uint64_t __lane_mask,
+ bool __x);
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint32_t
+__gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x) {
+
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(__lane_mask);
+ return __match_mask;
+}
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +161,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index 10ad7a682d4cd..1da9402040b52 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -34,10 +34,6 @@ _Pragma("omp begin declare variant match(device =
{arch(nvptx64)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((nvptx_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of CUDA blocks in the 'x' dime
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131141
>From e1456be61130ea0ea006472990c7d294b8a32c03 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_any between targets
---
clang/lib/Headers/amdgpuintrin.h | 19 +
clang/lib/Headers/gpuintrin.h| 48 +++-
clang/lib/Headers/nvptxintrin.h | 19 ++---
3 files changed, 50 insertions(+), 36 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..74054068c9714 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,20 +142,7 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..78d55eafaaf0a 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,52 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Returns the bit-mask of active threads in the current warp or wavefront.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_lane_mask(void);
+
+// Returns a bitmask of threads in the current lane for which \p x is true.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t __gpu_ballot(uint64_t __lane_mask,
+ bool __x);
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint32_t
+ __gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x);
+
+
+// Copies the value from the first active thread to the rest.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
+ uint32_t __match_mask = 0;
+
+ bool __done = 0;
+ while (__gpu_ballot(__lane_mask, !__done)) {
+if (!__done) {
+ uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
+ if (__first == __x) {
+__match_mask = __gpu_lane_mask();
+__done = 1;
+ }
+}
+ }
+ __gpu_sync_lane(__lane_mask);
+ return __match_mask;
+}
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -115,7 +161,7 @@ __gpu_is_first_in_lane(uint64_t __lane_mask) {
return __gpu_lane_id() == __gpu_first_lane_id(__lane_mask);
}
-// Copies the value from the first active thread in the wavefront to the rest.
+// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x) {
uint32_t __hi = (uint32_t)(__x >> 32ull);
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index 10ad7a682d4cd..1da9402040b52 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -34,10 +34,6 @@ _Pragma("omp begin declare variant match(device =
{arch(nvptx64)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((nvptx_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of CUDA bl
[clang] Reapply "[Clang] Improve diagnostics for expansion length mismatch" (PR #121044)
@@ -75,7 +75,7 @@ getDepthAndIndex(UnexpandedParameterPack UPP) {
if (const auto *TTP = dyn_cast(UPP.first))
return std::make_pair(TTP->getDepth(), TTP->getIndex());
cor3ntin wrote:
We should add support for SubstTemplateTypeParmPackType /
SubstNonTypeTemplateParmPackExpr here
https://github.com/llvm/llvm-project/pull/121044
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[clang] [flang-rt] Pass the whole path of libflang_rt.runtime.a to linker on AIX (PR #131041)
Meinersbur wrote: > Right. I tried with `FLANG_RT_ENABLE_SHARED=ON` on AIX. I was able to > dynamically link to the shared `flang-rt` and execute the `a.out` > successfully. With this PR applied? It hardcodes `libflang_rt.runtime.a` on AIX, how can it find the `.so`? > As for buildCompilerRTBasename, it is currently specific to clang_rt with > different Component (e.g. builtins or profile). flang-rt also has components, currently there are `runtime`, `quadmath`, and `cuda_`. > Would you prefer to have a new additional set of functions for flang-rt? I don't find the compiler-rt ones very logical as they have grown over time, especially with the `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR` transition. Flang-RT only does `LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=ON` which could simplify some things, but code-reuse of the compiler-rt functions could be worthwhile as well. I would have to experiment to know what works best. Note that the linker currently resolves `-lflang_rt.runtime` because `ToolChain::LibraryPath` (I think) which contains `ToolChain::getRuntimePath()` is added as `-L` argument to the linker. That might be the way to get the location of `flang_rt.*.a`. It would just be nice to have a function that returns the canonical location of `flang_rt.*.a` because currently its all over the place. Also: [multilib](https://github.com/llvm/llvm-project/issues/127538). https://github.com/llvm/llvm-project/pull/131041 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] Filter out configuration line (PR #131099)
https://github.com/kwk created https://github.com/llvm/llvm-project/pull/131099
The commands to run the compilation when printed with `-###` shows various
irrelevant lines for the perf-training. Most of them are filtered out already
but when configured with
`CLANG_CONFIG_FILE_SYSTEM_DIR` a new line like the following is added and needs
to be filtered out:
`Configuration file: /etc/clang/x86_64-redhat-linux-gnu-clang.cfg`
>From db5d475fd1e24278782536f9ed13b898a2bc450a Mon Sep 17 00:00:00 2001
From: Konrad Kleine
Date: Thu, 13 Mar 2025 09:12:24 +0100
Subject: [PATCH] Filter out configuration line
The commands to run the compilation when printed with `-###` shows
various irrelevant lines for the perf-training. Most of them are
filtered out already but when configured with
`CLANG_CONFIG_FILE_SYSTEM_DIR` a new line like the following is
added and needs to be filtered out:
`Configuration file: /etc/clang/x86_64-redhat-linux-gnu-clang.cfg`
---
clang/utils/perf-training/perf-helper.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/clang/utils/perf-training/perf-helper.py
b/clang/utils/perf-training/perf-helper.py
index 80c6356d0497c..29904aded5ab0 100644
--- a/clang/utils/perf-training/perf-helper.py
+++ b/clang/utils/perf-training/perf-helper.py
@@ -237,6 +237,7 @@ def get_cc1_command_for_args(cmd, env):
or ln.startswith("InstalledDir:")
or ln.startswith("LLVM Profile Note")
or ln.startswith(" (in-process)")
+or ln.startswith("Configuration file:")
or " version " in ln
):
continue
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[clang] [libc][nfc] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
@@ -13,11 +13,8 @@
#error "This file is intended for AMDGPU targets or offloading to AMDGPU"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __GPUINTRIN_H
+#warning "This file is intended as an implementation detail of gpuintrin.h"
JonChesterfield wrote:
yep, done
https://github.com/llvm/llvm-project/pull/131134
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[clang] [libc][nfc] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
@@ -263,8 +256,4 @@ _DEFAULT_FN_ATTRS static __inline__ void
__gpu_thread_suspend(void) {
_Pragma("omp end declare variant");
_Pragma("omp end declare target");
-#if !defined(__cplusplus)
-_Pragma("pop_macro(\"bool\")");
JonChesterfield wrote:
Up into gpuintrin.h
https://github.com/llvm/llvm-project/pull/131134
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[clang] [Clang][Diagnostics] Update select uses in DiagnosticXKinds.td to use enum_select (PR #130868)
@@ -131,17 +131,21 @@ def note_constexpr_past_end : Note<
"dereferenced pointer past the end of %select{|subobject of }0"
"%select{temporary|%2}1 is not a constant expression">;
def note_constexpr_past_end_subobject : Note<
- "cannot %select{access base class of|access derived class of|access field
of|"
- "access array element of|ERROR|"
- "access real component of|access imaginary component of}0 "
- "pointer past the end of object">;
+ "cannot %enum_select{"
+"%BaseClassAccess{access base class of}|%DerivedClassAccess{access derived
class of}|"
+"%FieldAccess{access field of}|%ArrayElementAccess{access array element
of}|"
+"%ErrorAccess{ERROR}|"
+"%RealComponentAccess{access real component
of}|%ImaginaryComponentAccess{access imaginary component of}"
+ "}0 pointer past the end of object">;
def note_non_null_attribute_failed : Note<
"null passed to a callee that requires a non-null argument">;
def note_constexpr_null_subobject : Note<
- "cannot %select{access base class of|access derived class of|access field
of|"
- "access array element of|perform pointer arithmetic on|"
- "access real component of|"
- "access imaginary component of}0 null pointer">;
+ "cannot %enum_select{"
Sirraide wrote:
> additionally
Or actually, maybe *instead* rather than *additionally*? I.e. don’t allow
`%enum_select{...}` for the same `T` multiple times, but instead only allow
referencing an existing `enum_select` by writing e.g. just `%enum_select0`
rather than `%enum_select{...}0`. That would also save us from having to
check whether two definitions of an `enum_select` are actually the same.
https://github.com/llvm/llvm-project/pull/130868
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[clang] [Clang][Diagnostics] Update select uses in DiagnosticXKinds.td to use enum_select (PR #130868)
@@ -131,17 +131,21 @@ def note_constexpr_past_end : Note<
"dereferenced pointer past the end of %select{|subobject of }0"
"%select{temporary|%2}1 is not a constant expression">;
def note_constexpr_past_end_subobject : Note<
- "cannot %select{access base class of|access derived class of|access field
of|"
- "access array element of|ERROR|"
- "access real component of|access imaginary component of}0 "
- "pointer past the end of object">;
+ "cannot %enum_select{"
+"%BaseClassAccess{access base class of}|%DerivedClassAccess{access derived
class of}|"
Sirraide wrote:
I think these can just be e.g. `BaseClass` rather than `BaseClassAccess`,
otherwise we’ll end up with `AccessKind::BaseClassAccess`, which feels a bit
redundant.
https://github.com/llvm/llvm-project/pull/130868
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[clang] [libc][nfc] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff d3255474be3ea24d876eadb6e97a6424c132b23d
f0149fdf6d8fcf60b128bef8aacf299e846cc4a8 --extensions h --
clang/lib/Headers/amdgpuintrin.h clang/lib/Headers/gpuintrin.h
clang/lib/Headers/nvptxintrin.h
``
View the diff from clang-format here.
``diff
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index 8d300b5b9a..515948b357 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -38,7 +38,6 @@ _Pragma("push_macro(\"bool\")");
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -47,7 +46,6 @@ __gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
#error "This header is only meant to be used on GPU architectures."
#endif
-
_Pragma("omp begin declare target device_type(nohost)");
_Pragma("omp begin declare variant match(device = {kind(gpu)})");
``
https://github.com/llvm/llvm-project/pull/131134
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[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 7e9802f348e36bf826d9fe83d0d187478e0e9639
e1456be61130ea0ea006472990c7d294b8a32c03 --extensions h --
clang/lib/Headers/amdgpuintrin.h clang/lib/Headers/gpuintrin.h
clang/lib/Headers/nvptxintrin.h
``
View the diff from clang-format here.
``diff
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index 78d55eafaa..69e545b523 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,7 +32,6 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
-
_Pragma("omp begin declare target device_type(nohost)");
_Pragma("omp begin declare variant match(device = {kind(gpu)})");
@@ -45,15 +44,12 @@ _DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_ballot(uint64_t __lane_mask,
// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint32_t
- __gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x);
-
+__gpu_read_first_lane_u32(uint64_t __lane_mask, uint32_t __x);
// Copies the value from the first active thread to the rest.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
-
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
@@ -73,11 +69,9 @@ __gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t
__x) {
return __match_mask;
}
-
_Pragma("omp end declare variant");
_Pragma("omp end declare target");
-
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
``
https://github.com/llvm/llvm-project/pull/131141
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[clang-tools-extra] [lld] [llvm] tools: Remove untested PluginLoader includes (PR #117644)
arsenm wrote: ping https://github.com/llvm/llvm-project/pull/117644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Add Zilsd and Zclsd Extensions (PR #131094)
@@ -0,0 +1,36 @@ +//===-- RISCVInstrInfoZilsd.td -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===--===// +// +// This file describes the RISC-V instructions from the standard 'Zilsd', +// Load/Store pair instructions extension. +// +//===--===// +// Instruction Class Templates +//===--===// + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class ld_r +: RVInstI<0b011, OPC_LOAD, (outs RC:$rd), +(ins GPRMem:$rs1, simm12:$imm12), topperc wrote: The `ins` need to be indented 2 more spaced to align with `0b011` on the previous line. https://github.com/llvm/llvm-project/pull/131094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang] Remove usage of llvm-spirv in clang LIT tests (PR #131158)
https://github.com/sarnex created
https://github.com/llvm/llvm-project/pull/131158
We use the backend now, so remove the requirement from the only test that
actually executes it and remove the LIT requirement variable.
>From 196e880b258e48c18ec0f6a88a11eb8149d3b16b Mon Sep 17 00:00:00 2001
From: "Sarnie, Nick"
Date: Thu, 13 Mar 2025 08:31:46 -0700
Subject: [PATCH] [clang] Remove usage of llvm-spirv in clang LIT tests
Signed-off-by: Sarnie, Nick
---
clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp | 2 +-
clang/test/Tooling/lit.local.cfg | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
b/clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
index 9b16727d74192..af98904677283 100644
--- a/clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
+++ b/clang/test/Tooling/clang-linker-wrapper-spirv-elf.cpp
@@ -1,7 +1,7 @@
// Verify the ELF packaging of OpenMP SPIR-V device images.
// REQUIRES: system-linux
// REQUIRES: spirv-tools
-// REQUIRES: llvm-spirv
+// REQUIRES: spirv-registered-target
// RUN: mkdir -p %t_tmp
// RUN: cd %t_tmp
// RUN: %clangxx -fopenmp -fopenmp-targets=spirv64-intel -nogpulib -c -o
%t_clang-linker-wrapper-spirv-elf.o %s
diff --git a/clang/test/Tooling/lit.local.cfg b/clang/test/Tooling/lit.local.cfg
index 61f328c91e4d3..46d32e6ebf454 100644
--- a/clang/test/Tooling/lit.local.cfg
+++ b/clang/test/Tooling/lit.local.cfg
@@ -9,6 +9,3 @@ if config.spirv_tools_tests:
config.substitutions.append(("spirv-val",
os.path.join(config.llvm_tools_dir, "spirv-val")))
config.substitutions.append(("spirv-as",
os.path.join(config.llvm_tools_dir, "spirv-as")))
config.substitutions.append(("spirv-link",
os.path.join(config.llvm_tools_dir, "spirv-link")))
-
-if lit.util.which("llvm-spirv"):
-config.available_features.add("llvm-spirv")
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[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
https://github.com/JonChesterfield closed https://github.com/llvm/llvm-project/pull/131141 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] c9d7f70 - [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (#131141)
Author: Jon Chesterfield
Date: 2025-03-13T15:44:24Z
New Revision: c9d7f707c101896294d2f4ccbf26329894295dc9
URL:
https://github.com/llvm/llvm-project/commit/c9d7f707c101896294d2f4ccbf26329894295dc9
DIFF:
https://github.com/llvm/llvm-project/commit/c9d7f707c101896294d2f4ccbf26329894295dc9.diff
LOG: [Headers][NFC] Deduplicate gpu_match_ between targets via inlining
(#131141)
Declare a few functions before including the target specific headers
then define a fallback_match_{any,all} used by amdgpu and by older
nvptx.
Fixes a minor bug on pre-volta where one of the four fallback paths was
missing a sync_lane.
Added:
Modified:
clang/lib/Headers/amdgpuintrin.h
clang/lib/Headers/gpuintrin.h
clang/lib/Headers/nvptxintrin.h
Removed:
diff --git a/clang/lib/Headers/amdgpuintrin.h
b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..f7fb8e2814180 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,57 +142,25 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_match_any_u32_impl(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_match_any_u64_impl(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_match_all_u32_impl(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_match_all_u64_impl(__lane_mask, __x);
}
// Returns true if the flat pointer points to AMDGPU 'shared' memory.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..0fb3916acac61 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,30 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Forward declare a few functions for the implementation header.
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_match_any_u32_impl(uint64_t __lane_mask, uint32_t __x);
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_match_any_u64_impl(uint64_t __lane_mask, uint64_t __x);
+
+// Returns the current lane mask if every lane contains __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_match_all_u32_impl(uint64_t __lane_mask, uint32_t __x);
+
+// Returns the current lane mask if every
[clang] [Clang][WIP] Constant Expressions inside of gcc'asm strings (PR #131003)
@@ -609,9 +632,10 @@ int GCCAsmStmt::getNamedOperand(StringRef SymbolicName)
const {
/// true, otherwise return false.
unsigned GCCAsmStmt::AnalyzeAsmString(SmallVectorImpl&Pieces,
const ASTContext &C, unsigned &DiagOffs) const
{
- StringRef Str = getAsmString()->getString();
- const char *StrStart = Str.begin();
- const char *StrEnd = Str.end();
+
+ std::string Str = getAsmString();
+ const char *StrStart = Str.data();
erichkeane wrote:
Isn't the type of the iterators `const char*`?
https://github.com/llvm/llvm-project/pull/131003
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[clang] [llvm] Reapply "[AArch64][SVE] Improve fixed-length addressing modes. (#130263)" (PR #130625)
https://github.com/rj-jesus updated
https://github.com/llvm/llvm-project/pull/130625
>From 03471cbf9270d1707191057de46dd38409c8a046 Mon Sep 17 00:00:00 2001
From: Ricardo Jesus
Date: Mon, 10 Mar 2025 01:57:20 -0700
Subject: [PATCH 1/4] Reapply "[AArch64][SVE] Improve fixed-length addressing
modes." (#130263)
This reverts commit 21610e3ecc8bc727f99047e544186b35b1291bcd.
---
.../CodeGen/AArch64/sve-vector-bits-codegen.c | 9 +-
.../Target/AArch64/AArch64ISelDAGToDAG.cpp| 15 +-
llvm/lib/Target/AArch64/AArch64Subtarget.h| 12 +-
.../AArch64/sve-fixed-length-offsets.ll | 362 ++
.../AArch64/sve-fixed-length-shuffles.ll | 90 ++---
5 files changed, 434 insertions(+), 54 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
diff --git a/clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
b/clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
index 0ed14b4b3b793..1391a1b09fbd1 100644
--- a/clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
+++ b/clang/test/CodeGen/AArch64/sve-vector-bits-codegen.c
@@ -13,12 +13,9 @@
void func(int *restrict a, int *restrict b) {
// CHECK-LABEL: func
-// CHECK256-COUNT-1: str
-// CHECK256-COUNT-7: st1w
-// CHECK512-COUNT-1: str
-// CHECK512-COUNT-3: st1w
-// CHECK1024-COUNT-1: str
-// CHECK1024-COUNT-1: st1w
+// CHECK256-COUNT-8: str
+// CHECK512-COUNT-4: str
+// CHECK1024-COUNT-2: str
// CHECK2048-COUNT-1: st1w
#pragma clang loop vectorize(enable)
for (int i = 0; i < 64; ++i)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 3ca9107cb2ce5..07bcd802962fa 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -7380,12 +7380,23 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ int64_t MulImm = std::numeric_limits::max();
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm = cast(VScale.getOperand(0))->getSExtValue();
+ } else if (auto C = dyn_cast(VScale)) {
+int64_t ByteOffset = C->getSExtValue();
+const auto KnownVScale =
+Subtarget->getSVEVectorSizeInBits() / AArch64::SVEBitsPerBlock;
+
+if (!KnownVScale || ByteOffset % KnownVScale != 0)
+ return false;
+
+MulImm = ByteOffset / KnownVScale;
+ } else
return false;
TypeSize TS = MemVT.getSizeInBits();
int64_t MemWidthBytes = static_cast(TS.getKnownMinValue()) / 8;
- int64_t MulImm = cast(VScale.getOperand(0))->getSExtValue();
if ((MulImm % MemWidthBytes) != 0)
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h
b/llvm/lib/Target/AArch64/AArch64Subtarget.h
index c6eb77e3bc3ba..f5ffc72cae537 100644
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -391,7 +391,7 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
void mirFileLoaded(MachineFunction &MF) const override;
// Return the known range for the bit length of SVE data registers. A value
- // of 0 means nothing is known about that particular limit beyong what's
+ // of 0 means nothing is known about that particular limit beyond what's
// implied by the architecture.
unsigned getMaxSVEVectorSizeInBits() const {
assert(isSVEorStreamingSVEAvailable() &&
@@ -405,6 +405,16 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ unsigned getSVEVectorSizeInBits() const {
+assert(isSVEorStreamingSVEAvailable() &&
+ "Tried to get SVE vector length without SVE support!");
+if (MinSVEVectorSizeInBits == MaxSVEVectorSizeInBits)
+ return MaxSVEVectorSizeInBits;
+return 0;
+ }
+
bool useSVEForFixedLengthVectors() const {
if (!isSVEorStreamingSVEAvailable())
return false;
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
b/llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
new file mode 100644
index 0..700bbe4f060ca
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-offsets.ll
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s |
FileCheck %s --check-prefix=CHECK-128
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s |
FileCheck %s --check-prefix=CHECK-256
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-m
[clang] [Clang] Fixed UnresolvedLookupExpr propagating into the codegen phase (PR #124609)
@@ -703,6 +703,48 @@ auto f(auto x) { // cxx14-error {{'auto' not allowed in
function prototype}}
return f(1) + 1;
}
+namespace GH122892 {
zyn0217 wrote:
I think the test should live in CodeGen/ rather than SemaCXX/, which mostly
contains '-fsyntax-only' tests, while the issue arises in the codegen stage?
https://github.com/llvm/llvm-project/pull/124609
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[clang] [clang-format] Add support for absl nullability macros (PR #130346)
https://github.com/jvoung updated
https://github.com/llvm/llvm-project/pull/130346
>From 10df1857532a6a27b0e5286e10c9f0724d6d7e1d Mon Sep 17 00:00:00 2001
From: Jan Voung
Date: Fri, 7 Mar 2025 21:02:16 +
Subject: [PATCH 1/7] [clang-format] Add support for absl nullability macros
---
clang/lib/Format/Format.cpp| 4
clang/unittests/Format/ConfigParseTest.cpp | 4 +++-
clang/unittests/Format/FormatTest.cpp | 19 +--
3 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index b5f1241321891..1401b51586d03 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -1508,6 +1508,10 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind
Language) {
LLVMStyle.AlwaysBreakAfterDefinitionReturnType = FormatStyle::DRTBS_None;
LLVMStyle.AlwaysBreakBeforeMultilineStrings = false;
LLVMStyle.AttributeMacros.push_back("__capability");
+ // Abseil aliases to clang's `_Nonnull`, `_Nullable` and `_Null_unspecified`.
+ LLVMStyle.AttributeMacros.push_back("absl_nonnull");
+ LLVMStyle.AttributeMacros.push_back("absl_nullable");
+ LLVMStyle.AttributeMacros.push_back("absl_nullability_unknown");
LLVMStyle.BinPackArguments = true;
LLVMStyle.BinPackLongBracedList = true;
LLVMStyle.BinPackParameters = FormatStyle::BPPS_BinPack;
diff --git a/clang/unittests/Format/ConfigParseTest.cpp
b/clang/unittests/Format/ConfigParseTest.cpp
index 273bab87b1ee1..2cc2a45a7a590 100644
--- a/clang/unittests/Format/ConfigParseTest.cpp
+++ b/clang/unittests/Format/ConfigParseTest.cpp
@@ -908,7 +908,9 @@ TEST(ConfigParseTest, ParsesConfiguration) {
Style.AttributeMacros.clear();
CHECK_PARSE("BasedOnStyle: LLVM", AttributeMacros,
- std::vector{"__capability"});
+ std::vector({"__capability", "absl_nonnull",
"absl_nullable",
+"absl_nullability_unknown"}));
+ Style.AttributeMacros.clear();
CHECK_PARSE("AttributeMacros: [attr1, attr2]", AttributeMacros,
std::vector({"attr1", "attr2"}));
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index bd335f4b6a21b..a17cad0b67b08 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -12375,6 +12375,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
+ verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
verifyFormat("vector v;");
@@ -12518,6 +12521,9 @@ TEST_F(FormatTest, UnderstandsUsesOfStarAndAmp) {
verifyIndependentOfContext("MACRO(A *_Nonnull a);");
verifyIndependentOfContext("MACRO(A *_Nullable a);");
verifyIndependentOfContext("MACRO(A *_Null_unspecified a);");
+ verifyIndependentOfContext("MACRO(A *absl_nonnull a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullable a);");
+ verifyIndependentOfContext("MACRO(A *absl_nullability_unknown a);");
verifyIndependentOfContext("MACRO(A *__attribute__((foo)) a);");
verifyIndependentOfContext("MACRO(A *__attribute((foo)) a);");
verifyIndependentOfContext("MACRO(A *[[clang::attr]] a);");
@@ -12674,6 +12680,12 @@ TEST_F(FormatTest, UnderstandsAttributes) {
verifyFormat("SomeType *__unused s{InitValue};", CustomAttrs);
verifyFormat("SomeType s __unused(InitValue);", CustomAttrs);
verifyFormat("SomeType s __unused{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nonnull s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s(InitValue);", CustomAttrs);
+ verifyFormat("SomeType *absl_nullable s{InitValue};", CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s(InitValue);",
CustomAttrs);
+ verifyFormat("SomeType *absl_nullability_unknown s{InitValue};",
CustomAttrs);
verifyFormat("SomeType *__capability s(InitValue);", CustomAttrs);
verifyFormat("SomeType *__capability s{InitValue};", CustomAttrs);
}
@@ -12687,7 +12699,9 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
verifyFormat("x = (foo *_Nonnull)*v;");
verifyFormat("x = (foo *_Nullable)*v;");
verifyFormat("x = (foo *_Null_unspecified)*v;");
- verifyFormat("x = (foo *_Nonnull)*v;");
+ verifyFormat("x = (foo *absl_nonnull)*v;");
+ verifyFormat("x = (foo *absl_nullable)*v;");
+ verifyFormat("x = (foo *absl_nullability_unknown)*v;");
verifyFormat("x = (foo *[[clang::attr]])*v;");
verifyFormat("x = (foo *[[clang::attr(\"foo\")]])*v;");
verifyFormat("x = (foo *__ptr32)*v;");
@@ -12701,7 +12715,8 @@ TEST_F(FormatTest, UnderstandsPointerQualifiersInCast) {
LongPointerLeft.PointerAlignment = FormatStyle::PAS_Left;
StringRef AllQualifiers =
"const volatile restrict __attribute__((foo)) _Nonnull _Null_unspecified
"
-
[clang] [Clang] Fixed UnresolvedLookupExpr propagating into the codegen phase (PR #124609)
@@ -703,6 +703,48 @@ auto f(auto x) { // cxx14-error {{'auto' not allowed in
function prototype}}
return f(1) + 1;
}
+namespace GH122892 {
erichkeane wrote:
I don't think so? Since this is replacing the condition that previously
crashed in codegen with a sema-error, right?
https://github.com/llvm/llvm-project/pull/124609
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[clang] [compiler-rt] [llvm] llvm-cov: Merge records for template instantiations (PR #121197)
evodius96 wrote: I agree; I apologize for my silence as I have had several distractions. I plan to start looking at more of these next week. https://github.com/llvm/llvm-project/pull/121197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers] Create stub spirv64intrin.h (PR #131164)
https://github.com/jhuber6 commented: Should probably just be called `spirvintrin.h` unless there's something that significantly distinguishes this from the 32-bit counterpart. (Same reason it's `nvptxintrin` and not `nvptx64intrin`. https://github.com/llvm/llvm-project/pull/131164 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_any between targets (PR #131141)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131141
>From cde4232ed28eed2b0c0c1cb11815b5a4317345b6 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_any between targets
---
clang/lib/Headers/amdgpuintrin.h | 44 ++---
clang/lib/Headers/gpuintrin.h| 83 +++-
clang/lib/Headers/nvptxintrin.h | 48 +++---
3 files changed, 94 insertions(+), 81 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..5e7f9b967bd17 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,57 +142,25 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u64(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_fallback_match_all_u32(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_fallback_match_all_u64(__lane_mask, __x);
}
// Returns true if the flat pointer points to AMDGPU 'shared' memory.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..f231f3c519a34 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,31 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Forward declare a few functions for the implementation header.
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x);
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u64(uint64_t __lane_mask, uint64_t __x);
+
+// Returns the current lane mask if every lane contains __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_all_u32(uint64_t __lane_mask, uint32_t __x);
+
+// Returns the current lane mask if every lane contains __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_all_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -1
[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131141 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
https://github.com/JonChesterfield edited https://github.com/llvm/llvm-project/pull/131141 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield closed https://github.com/llvm/llvm-project/pull/131134 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Deduplicate gpu_match_ between targets via inlining (PR #131141)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131141
>From 5e55b829eb3c7f4a4e674333cdde73b5bfe970f8 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 13:23:38 +
Subject: [PATCH] [Headers][NFC] Deduplicate gpu_match_ between targets via
inlining
---
clang/lib/Headers/amdgpuintrin.h | 44 ++---
clang/lib/Headers/gpuintrin.h| 83 +++-
clang/lib/Headers/nvptxintrin.h | 48 +++---
3 files changed, 94 insertions(+), 81 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 56748f6c3e818..5e7f9b967bd17 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -30,10 +30,6 @@ _Pragma("omp begin declare variant match(device =
{arch(amdgcn)})");
// Attribute to declare a function as a kernel.
#define __gpu_kernel __attribute__((amdgpu_kernel, visibility("protected")))
-// Defined in gpuintrin.h, used later in this file.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_read_first_lane_u64(uint64_t __lane_mask, uint64_t __x);
-
// Returns the number of workgroups in the 'x' dimension of the grid.
_DEFAULT_FN_ATTRS static __inline__ uint32_t __gpu_num_blocks_x(void) {
return __builtin_amdgcn_grid_size_x() / __builtin_amdgcn_workgroup_size_x();
@@ -146,57 +142,25 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u32(__lane_mask, __x);
}
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __match_mask = 0;
-
- bool __done = 0;
- while (__gpu_ballot(__lane_mask, !__done)) {
-if (!__done) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- if (__first == __x) {
-__match_mask = __gpu_lane_mask();
-__done = 1;
- }
-}
- }
- __gpu_sync_lane(__lane_mask);
- return __match_mask;
+ return __gpu_fallback_match_any_u64(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u32(uint64_t __lane_mask, uint32_t __x) {
- uint32_t __first = __gpu_read_first_lane_u32(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_fallback_match_all_u32(__lane_mask, __x);
}
// Returns the current lane mask if every lane contains __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_all_u64(uint64_t __lane_mask, uint64_t __x) {
- uint64_t __first = __gpu_read_first_lane_u64(__lane_mask, __x);
- uint64_t __ballot = __gpu_ballot(__lane_mask, __x == __first);
- __gpu_sync_lane(__lane_mask);
- return __ballot == __gpu_lane_mask() ? __gpu_lane_mask() : 0ull;
+ return __gpu_fallback_match_all_u64(__lane_mask, __x);
}
// Returns true if the flat pointer points to AMDGPU 'shared' memory.
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index ac79d685337c5..f231f3c519a34 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -32,6 +32,31 @@ _Pragma("push_macro(\"bool\")");
#define bool _Bool
#endif
+_Pragma("omp begin declare target device_type(nohost)");
+_Pragma("omp begin declare variant match(device = {kind(gpu)})");
+
+// Forward declare a few functions for the implementation header.
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u32(uint64_t __lane_mask, uint32_t __x);
+
+// Returns a bitmask marking all lanes that have the same value of __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_any_u64(uint64_t __lane_mask, uint64_t __x);
+
+// Returns the current lane mask if every lane contains __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_all_u32(uint64_t __lane_mask, uint32_t __x);
+
+// Returns the current lane mask if every lane contains __x.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_fallback_match_all_u64(uint64_t __lane_mask, uint64_t __x);
+
+
+_Pragma("omp end declare variant");
+_Pragma("omp end declare target");
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDG
[clang] [Clang] Fixed UnresolvedLookupExpr propagating into the codegen phase (PR #124609)
@@ -14228,9 +14228,15 @@ ExprResult Sema::BuildOverloadedCallExpr(Scope *S,
Expr *Fn,
const FunctionDecl *FDecl = Best->Function;
if (FDecl && FDecl->isTemplateInstantiation() &&
FDecl->getReturnType()->isUndeducedType()) {
+
+ // As there'll be no attempt to resolve UnresolvedLookupExpr again inside
+ // non-dependent context, skip considering it as type-dependent.
+ const DeclContext *DC = CurContext;
+ const bool Resolvable = DC && DC->isDependentContext();
erichkeane wrote:
`Resolvable` isn't a good name here, it sorta implies the opposite of what we
mean, but not to the point of `NotResolvable` being a good idea. I think just
putting `&& CurContext->isDependentContext()` below is actually more readable.
Also, you don't really have to check the `DeclContext`, having a null one I
think requires that you be outside of a `TranslationUnitDecl`, which isn't
possible.
I see that we are just going through `FinishOverloadedCallExpr` in the event
that we are going to instantiate this again, which I guess makes sense, since
this is creating a call with a `DependentTy`, but this comment doesn't make it
clear what i I think I'd be happy with a better commit message explaining the
whole situation and why this works. I've debugged a while and think I have a
good hold on it though, so just a better description I think would help
https://github.com/llvm/llvm-project/pull/124609
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[clang] [Clang] Fixed UnresolvedLookupExpr propagating into the codegen phase (PR #124609)
https://github.com/erichkeane commented: I have minor suggestions, and am not quite comfortable with this yet, so please improve the commit message and make the change I requested (re `Resolvable`), and I'll revisit this afterwards. https://github.com/llvm/llvm-project/pull/124609 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][NFCI] Fix getGridValues for unsupported targets (PR #131023)
https://github.com/sarnex closed https://github.com/llvm/llvm-project/pull/131023 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Headers][NFC] Steps to allow sharing code between gpu intrin.h headers (PR #131134)
https://github.com/JonChesterfield updated
https://github.com/llvm/llvm-project/pull/131134
>From 7347ebc6a0aadd1b9676e329bdf7705dbfae7875 Mon Sep 17 00:00:00 2001
From: Jon Chesterfield
Date: Thu, 13 Mar 2025 12:49:42 +
Subject: [PATCH] [libc][nfc] Steps to allow sharing code between gpu intrin.h
headers
---
clang/lib/Headers/amdgpuintrin.h | 22 ++
clang/lib/Headers/gpuintrin.h| 26 +++---
clang/lib/Headers/nvptxintrin.h | 27 ---
3 files changed, 25 insertions(+), 50 deletions(-)
diff --git a/clang/lib/Headers/amdgpuintrin.h b/clang/lib/Headers/amdgpuintrin.h
index 839a05175cf3e..56748f6c3e818 100644
--- a/clang/lib/Headers/amdgpuintrin.h
+++ b/clang/lib/Headers/amdgpuintrin.h
@@ -13,11 +13,8 @@
#error "This file is intended for AMDGPU targets or offloading to AMDGPU"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -146,17 +143,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
return __builtin_amdgcn_ds_bpermute(__lane << 2, __x);
}
-// Shuffles the the lanes inside the wavefront according to the given index.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
- uint32_t __width) {
- uint32_t __hi = (uint32_t)(__x >> 32ull);
- uint32_t __lo = (uint32_t)(__x & 0x);
- return ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __hi, __width)
- << 32ull) |
- ((uint64_t)__gpu_shuffle_idx_u32(__lane_mask, __idx, __lo, __width));
-}
-
// Returns a bitmask marking all lanes that have the same value of __x.
_DEFAULT_FN_ATTRS static __inline__ uint64_t
__gpu_match_any_u32(uint64_t __lane_mask, uint32_t __x) {
@@ -238,8 +224,4 @@ _DEFAULT_FN_ATTRS static __inline__ void
__gpu_thread_suspend(void) {
_Pragma("omp end declare variant");
_Pragma("omp end declare target");
-#if !defined(__cplusplus)
-_Pragma("pop_macro(\"bool\")");
-#endif
-
#endif // __AMDGPUINTRIN_H
diff --git a/clang/lib/Headers/gpuintrin.h b/clang/lib/Headers/gpuintrin.h
index 4181628d18048..ac79d685337c5 100644
--- a/clang/lib/Headers/gpuintrin.h
+++ b/clang/lib/Headers/gpuintrin.h
@@ -25,6 +25,13 @@
#endif
#endif
+#include
+
+#if !defined(__cplusplus)
+_Pragma("push_macro(\"bool\")");
+#define bool _Bool
+#endif
+
#if defined(__NVPTX__)
#include
#elif defined(__AMDGPU__)
@@ -33,13 +40,6 @@
#error "This header is only meant to be used on GPU architectures."
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
-#endif
-
_Pragma("omp begin declare target device_type(nohost)");
_Pragma("omp begin declare variant match(device = {kind(gpu)})");
@@ -141,6 +141,18 @@ __gpu_read_first_lane_f64(uint64_t __lane_mask, double
__x) {
__builtin_bit_cast(uint64_t, __x)));
}
+// Shuffles the the lanes according to the given index.
+_DEFAULT_FN_ATTRS static __inline__ uint64_t
+__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
+ uint32_t __width) {
+ uint32_t __hi = (uint32_t)(__x >> 32ull);
+ uint32_t __lo = (uint32_t)(__x & 0x);
+ uint32_t __mask = (uint32_t)__lane_mask;
+ return ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __hi, __width)
+ << 32ull) |
+ ((uint64_t)__gpu_shuffle_idx_u32(__mask, __idx, __lo, __width));
+}
+
// Shuffles the the lanes according to the given index.
_DEFAULT_FN_ATTRS static __inline__ float
__gpu_shuffle_idx_f32(uint64_t __lane_mask, uint32_t __idx, float __x,
diff --git a/clang/lib/Headers/nvptxintrin.h b/clang/lib/Headers/nvptxintrin.h
index d00a5f6de3950..10ad7a682d4cd 100644
--- a/clang/lib/Headers/nvptxintrin.h
+++ b/clang/lib/Headers/nvptxintrin.h
@@ -13,15 +13,12 @@
#error "This file is intended for NVPTX targets or offloading to NVPTX"
#endif
-#ifndef __CUDA_ARCH__
-#define __CUDA_ARCH__ 0
+#ifndef __GPUINTRIN_H
+#error "Never use directly; include instead"
#endif
-#include
-
-#if !defined(__cplusplus)
-_Pragma("push_macro(\"bool\")");
-#define bool _Bool
+#ifndef __CUDA_ARCH__
+#define __CUDA_ARCH__ 0
#endif
_Pragma("omp begin declare target device_type(nohost)");
@@ -153,18 +150,6 @@ __gpu_shuffle_idx_u32(uint64_t __lane_mask, uint32_t
__idx, uint32_t __x,
((__gpu_num_lanes() - __width) << 8u) |
0x1f);
}
-// Shuffles the the lanes inside the warp according to the given index.
-_DEFAULT_FN_ATTRS static __inline__ uint64_t
-__gpu_shuffle_idx_u64(uint64_t __lane_mask, uint32_t __idx, uint64_t __x,
- uint32_t __width) {
- uint32_t __hi = (uint32_t)(__x >> 32ull);
- uint32_t __lo = (uint32_t)(__x & 0x);
- uint32_t __mask =
[clang] [llvm] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and scalable vectors. (PR #130973)
@@ -26,11 +26,15 @@ typedef vbool64_t fixed_bool64_t
__attribute__((riscv_rvv_vector_bits(__riscv_v_
//
// CHECK-128-LABEL: @call_bool32_ff(
// CHECK-128-NEXT: entry:
+// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1
paulwalker-arm wrote:
I don't know, perhaps there is a front end problem for RISCV. When
investigating one of the affected test cases where vscale=2:
```
fixed_bool32_t call_bool32_ff(fixed_bool32_t op1, fixed_bool32_t op2) {
return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 32);
}
```
I see the snippet:
```
%saved-value = alloca <1 x i8>, align 1
store <1 x i8> %0, ptr %saved-value, align 1, !tbaa !6
%1 = load , ptr %saved-value, align 1, !tbaa !6
```
However:
```
DL.getTypeStoreSize(<1 x i8>) => 1
DL.getTypeStoreSize() => vscale x 1
```
This means the store size of `` is 2 bytes, which makes the
load undefined behaviour? Looking at the new output it's just not removing the
undefined accesses.
I'm not familiar with the RVV instructions (does it have sub-byte memory
accesses?) but for SVE the store size for predicates is always a multiple of
bytes and thus we model the storage of fixed length predicates as i8 vectors
and then "cast" them to scalable boolean vectors. We also have a later combine
to reconstitute a real scalable vector predicate load/store when possible.
Even for pure scalable vectors the storage type is always byte sized (i.e.
) with us using reinterpret intrinsics to shrink/expand them.
I know SVE is not perfect here though as trying to alloca/load/store something
smaller will likely lead to isel failures, but that cannot (or at least
shouldn't) happen outside of hand written ll tests.
https://github.com/llvm/llvm-project/pull/130973
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[clang] [llvm] Add support for template as type parameter (PR #127654)
https://github.com/ykhatav ready_for_review https://github.com/llvm/llvm-project/pull/127654 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [CIR] Upstream CastOp and scalar conversions (PR #130690)
@@ -121,29 +375,174 @@ mlir::Value CIRGenFunction::emitScalarExpr(const Expr
*e) {
return ScalarExprEmitter(*this, builder).Visit(const_cast(e));
}
+[[maybe_unused]] static bool MustVisitNullValue(const Expr *e) {
+ // If a null pointer expression's type is the C++0x nullptr_t, then
+ // it's not necessarily a simple constant and it must be evaluated
+ // for its potential side effects.
+ return e->getType()->isNullPtrType();
+}
+
// Emit code for an explicit or implicit cast. Implicit
// casts have to handle a more broad range of conversions than explicit
// casts, as they handle things like function to ptr-to-function decay
// etc.
mlir::Value ScalarExprEmitter::VisitCastExpr(CastExpr *ce) {
- Expr *e = ce->getSubExpr();
+ Expr *subExpr = ce->getSubExpr();
QualType destTy = ce->getType();
CastKind kind = ce->getCastKind();
+ // These cases are generally not written to ignore the result of evaluating
+ // their sub-expressions, so we clear this now.
+ ignoreResultAssign = false;
erichkeane wrote:
You'll have to do a void cast on it then, else this will cause a warning.
https://github.com/llvm/llvm-project/pull/130690
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[clang] 7a5e4f5 - [clang][NFCI] Fix getGridValues for unsupported targets (#131023)
Author: Nick Sarnie
Date: 2025-03-13T14:28:49Z
New Revision: 7a5e4f540580d8f7e292292dc960178d8d8ba1d7
URL:
https://github.com/llvm/llvm-project/commit/7a5e4f540580d8f7e292292dc960178d8d8ba1d7
DIFF:
https://github.com/llvm/llvm-project/commit/7a5e4f540580d8f7e292292dc960178d8d8ba1d7.diff
LOG: [clang][NFCI] Fix getGridValues for unsupported targets (#131023)
I broke this in
https://github.com/llvm/llvm-project/commit/f3cd2238383f695c719e7eab6aebec828781ec91,
I should have added this to the `SPIRV64` subclass, but I accidentally
added it to base `TargetInfo`.
Using an unsupported target should error in the driver way before this
though.
Signed-off-by: Sarnie, Nick
Added:
Modified:
clang/include/clang/Basic/TargetInfo.h
clang/lib/Basic/Targets/SPIR.h
Removed:
diff --git a/clang/include/clang/Basic/TargetInfo.h
b/clang/include/clang/Basic/TargetInfo.h
index d136b459e9cd4..497d68779b92b 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1675,7 +1675,7 @@ class TargetInfo : public TransferrableTargetInfo,
// access target-specific GPU grid values that must be consistent between
// host RTL (plugin), deviceRTL and clang.
virtual const llvm::omp::GV &getGridValue() const {
-return llvm::omp::SPIRVGridValues;
+llvm_unreachable("getGridValue not implemented on this target");
}
/// Retrieve the name of the platform as it is used in the
diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h
index 610efa1fe00d9..78505d66d6f2f 100644
--- a/clang/lib/Basic/Targets/SPIR.h
+++ b/clang/lib/Basic/Targets/SPIR.h
@@ -370,6 +370,10 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64TargetInfo : public
BaseSPIRVTargetInfo {
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override;
+
+ const llvm::omp::GV &getGridValue() const override {
+return llvm::omp::SPIRVGridValues;
+ }
};
class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final
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[clang] [compiler-rt] [llvm] llvm-cov: Merge records for template instantiations (PR #121197)
chapuni wrote: @evodius96 I think you would be the best person to review my remaining requests. https://github.com/llvm/llvm-project/pull/121197 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][CIR] Add missing dependency on MLIR headers (PR #131057)
https://github.com/darkbuck updated https://github.com/llvm/llvm-project/pull/131057 >From 2a86c00614aed22f409c262dcb076f018e1fbbde Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Tue, 4 Mar 2025 12:47:24 -0500 Subject: [PATCH] [clang][CIR] Add missing dependency on MLIR headers --- clang/lib/CIR/FrontendAction/CMakeLists.txt | 3 +++ clang/lib/FrontendTool/CMakeLists.txt | 5 + 2 files changed, 8 insertions(+) diff --git a/clang/lib/CIR/FrontendAction/CMakeLists.txt b/clang/lib/CIR/FrontendAction/CMakeLists.txt index 6d5a8758468f6..df0e075fb7532 100644 --- a/clang/lib/CIR/FrontendAction/CMakeLists.txt +++ b/clang/lib/CIR/FrontendAction/CMakeLists.txt @@ -11,6 +11,9 @@ add_clang_library(clangCIRFrontendAction DEPENDS MLIRCIROpsIncGen MLIRCIROpInterfacesIncGen + # Add mlir-generic-headers dependency as the header CIRGenAction.h needs to + # include BuiltinOps.h + mlir-generic-headers LINK_LIBS clangAST diff --git a/clang/lib/FrontendTool/CMakeLists.txt b/clang/lib/FrontendTool/CMakeLists.txt index d7a3699361f0a..5a828ce239c64 100644 --- a/clang/lib/FrontendTool/CMakeLists.txt +++ b/clang/lib/FrontendTool/CMakeLists.txt @@ -15,6 +15,11 @@ set(link_libs set(deps) if(CLANG_ENABLE_CIR) + # Add mlir-generic-headers dependency as the header CIRGenAction.h needs to + # include BuiltinOps.h + list(APPEND deps +mlir-generic-headers + ) list(APPEND link_libs clangCIRFrontendAction MLIRIR ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
