RE: [PATCH] drm/amdgpu/vcn3: remove unused variable.

[Zhang, Boyuan]

[AMD Official Use Only]

Patch is
Reviewed-by: Boyuan Zhang 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: May 19, 2021 4:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian 

Subject: [PATCH] drm/amdgpu/vcn3: remove unused variable.

Not used so remove it.

Fixes: a8ccb542539ff1 ("drm/amdgpu: stop touching sched.ready in the backend")
Signed-off-by: Alex Deucher 
Cc: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 2d67caba9293..946335d0f19c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -381,7 +381,7 @@ static int vcn_v3_0_hw_fini(void *handle)  {
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_ring *ring;
-   int i, j;
+   int i;

for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
--
2.31.1

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RE: [PATCH] drm/amdgpu/vcn: drop gfxoff control for VCN2+

[Zhang, Boyuan]

[AMD Official Use Only]

Patch is
Reviewed-by: Boyuan Zhang 

Thanks,
Boyuan

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: June 7, 2021 4:29 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/vcn: drop gfxoff control for VCN2+

Drop disabling of gfxoff during VCN use.  This allows gfxoff to kick in and 
potentially save power if the user is not using gfx for color space conversion 
or scaling.

VCN1.0 had a bug which prevented it from working properly with gfxoff, so we 
disabled it while using VCN.  That said, most apps today use gfx for scaling 
and color space conversion rather than overlay planes so it was generally in 
use anyway. This was fixed on VCN2+, but since we mostly use gfx for color 
space conversion and scaling and rapidly powering up/down gfx can negate the 
advantages of gfxoff, we left gfxoff disabled. As more applications use overlay 
planes for color space conversion and scaling, this starts to be a win, so go 
ahead and leave gfxoff enabled.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 1dc11dbd62b7..647d2c31e8bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -393,7 +393,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
}

if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
-   amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO, @@ -413,7 +412,6 @@ void 
amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
atomic_inc(&adev->vcn.total_submission_cnt);

if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
-   amdgpu_gfx_off_ctrl(adev, false);
r = amdgpu_dpm_switch_power_profile(adev, 
PP_SMC_POWER_PROFILE_VIDEO,
true);
if (r)
--
2.31.1

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[PATCH] drm/amdgpu: enable VCN PG and CG for vangogh

[Zhang, Boyuan]

[AMD Official Use Only - Internal Distribution Only]

Enable VCN 3.0 PG and CG for Vangogh by setting up flags.

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 4b1a4acb60d9..ce787489aaeb 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -938,8 +938,13 @@ static int nv_common_early_init(void *handle)
  adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
  AMD_CG_SUPPORT_GFX_CGLS |
  AMD_CG_SUPPORT_GFX_3D_CGCG |
- AMD_CG_SUPPORT_GFX_3D_CGLS;
- adev->pg_flags = AMD_PG_SUPPORT_GFX_PG;
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_VCN_MGCG |
+ AMD_CG_SUPPORT_JPEG_MGCG;
+ adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
+ AMD_PG_SUPPORT_VCN |
+ AMD_PG_SUPPORT_VCN_DPG |
+ AMD_PG_SUPPORT_JPEG;
  adev->external_rev_id = adev->rev_id + 0x01;
  break;
--
2.25.1
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[PATCH] drm/amdgpu: update dec ring test for VCN 3.0

[Zhang, Boyuan]

[AMD Official Use Only - Internal Distribution Only]


To enable SW ring for VCN 3.0



Signed-off-by: Boyuan Zhang mailto:boyuan.zh...@amd.com>>

---

 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-

 1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

index ddc1c43e09a8..8adebb3b2a3f 100644

--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

@@ -1372,7 +1372,7 @@ static const struct amdgpu_ring_funcs 
vcn_v3_0_dec_ring_vm_funcs = {

  .emit_ib = vcn_v2_0_dec_ring_emit_ib,

  .emit_fence = vcn_v2_0_dec_ring_emit_fence,

  .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,

- .test_ring = amdgpu_vcn_dec_ring_test_ring,

+ .test_ring = vcn_v2_0_dec_ring_test_ring,

  .test_ib = amdgpu_vcn_dec_ring_test_ib,

  .insert_nop = vcn_v2_0_dec_ring_insert_nop,

  .insert_start = vcn_v2_0_dec_ring_insert_start,

--

2.17.1

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[PATCH V2] drm/amdgpu/vcn3: send smu interface type

[Zhang, Boyuan]

[AMD Official Use Only]

From: Boyuan Zhang mailto:boyuan.zh...@amd.com>>

For VCN FW to detect ASIC type, in order to use different mailbox registers.

V2: simplify codes and fix format issue.

Signed-off-by: Boyuan Zhang mailto:boyuan.zh...@amd.com>>
Acked-by Huang Rui 
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 7 +++
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 5 +
2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index e2fde88aaf5e..f06fb7f882e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -159,6 +159,7 @@
#define AMDGPU_VCN_MULTI_QUEUE_FLAG   (1 << 8)
#define AMDGPU_VCN_SW_RING_FLAG  (1 << 9)
#define AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
+#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER0x0001
#define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x0001
@@ -279,6 +280,11 @@ struct amdgpu_fw_shared_fw_logging {
   uint32_t size;
};
+struct amdgpu_fw_shared_smu_interface_info {
+ uint8_t smu_interface_type;
+ uint8_t padding[3];
+};
+
struct amdgpu_fw_shared {
   uint32_t present_flag_0;
   uint8_t pad[44];
@@ -287,6 +293,7 @@ struct amdgpu_fw_shared {
   struct amdgpu_fw_shared_multi_queue multi_queue;
   struct amdgpu_fw_shared_sw_ring sw_ring;
   struct amdgpu_fw_shared_fw_logging fw_log;
+ struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
};
 struct amdgpu_vcn_fwlog {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index b16c56aa2d22..9925b2bc63b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -219,6 +219,11 @@ static int vcn_v3_0_sw_init(void *handle)

cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |

cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
   fw_shared->sw_ring.is_enabled = 
cpu_to_le32(DEC_SW_RING_ENABLED);
+ fw_shared->present_flag_0 |= 
AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
+ if (adev->ip_versions[UVD_HWIP][0] == 
IP_VERSION(3, 1, 2))
+ 
fw_shared->smu_interface_info.smu_interface_type = 2;
+ else if (adev->ip_versions[UVD_HWIP][0] == 
IP_VERSION(3, 1, 1))
+ 
fw_shared->smu_interface_info.smu_interface_type = 1;
if (amdgpu_vcnfw_log)
   
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
--
2.25.1

RE: [PATCH] drm/amdgpu/vcn3: send smu interface type

[Zhang, Boyuan]

[AMD Official Use Only]

Hi Paul,

This change is to differentiate device (IP_VERSION(3, 1, 2)) and device 
(IP_VERSION(3, 1, 1)), since they are using different mailbox registers for VCN 
DPM. There is no other impact for VCN.

And thank for pointing out the format issue. I just sent out V2. Please have a 
look.

Regards,
Boyuan

-Original Message-
From: Paul Menzel 
Sent: March 24, 2022 1:56 AM
To: Zhang, Yifan ; Zhang, Boyuan 
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Huang, Ray 
Subject: Re: [PATCH] drm/amdgpu/vcn3: send smu interface type

Dear Yifan, dear Boyuan,


Am 24.03.22 um 03:59 schrieb Yifan Zhang:
> From: Boyuan Zhang 
>
> For VCN FW to detect ASIC type

What affect does this have? How does VCN FW behave different now?

> Signed-off-by: Boyuan Zhang 
> Signed-off-by: Yifan Zhang 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 7 +++
>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 7 +++
>   2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index e2fde88aaf5e..f06fb7f882e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -159,6 +159,7 @@
>   #define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
>   #define AMDGPU_VCN_SW_RING_FLAG (1 << 9)
>   #define AMDGPU_VCN_FW_LOGGING_FLAG  (1 << 10)
> +#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
>
>   #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER0x0001
>   #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER  0x0001
> @@ -279,6 +280,11 @@ struct amdgpu_fw_shared_fw_logging {
>   uint32_t size;
>   };
>
> +struct amdgpu_fw_shared_smu_interface_info {
> + uint8_t smu_interface_type;
> + uint8_t padding[3];
> +};
> +
>   struct amdgpu_fw_shared {
>   uint32_t present_flag_0;
>   uint8_t pad[44];
> @@ -287,6 +293,7 @@ struct amdgpu_fw_shared {
>   struct amdgpu_fw_shared_multi_queue multi_queue;
>   struct amdgpu_fw_shared_sw_ring sw_ring;
>   struct amdgpu_fw_shared_fw_logging fw_log;
> + struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
>   };
>
>   struct amdgpu_vcn_fwlog {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index b16c56aa2d22..c5bf7cbfa82c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -219,6 +219,13 @@ static int vcn_v3_0_sw_init(void *handle)
>
> cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
>
> cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
>   fw_shared->sw_ring.is_enabled = 
> cpu_to_le32(DEC_SW_RING_ENABLED);
> + if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 2)) {
> + fw_shared->present_flag_0 |= 
> AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
> + fw_shared->smu_interface_info.smu_interface_type = 2;
> + } else if(adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 
> 1)) {

Please add a space before the (, which `checkpatch.pl` also would have
found:

 $ scripts/checkpatch.pl
/dev/shm/0001-drm-amdgpu-vcn3-send-smu-interface-type.patch
 ERROR: space required before the open parenthesis '('
 #58: FILE: drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c:225:
+   } else if(adev->ip_versions[UVD_HWIP][0] ==
IP_VERSION(3, 1, 1)) {

Also why not order it smallest version first? Will there ever be other
IP versions for VCN 3.0?

> + fw_shared->present_flag_0 |= 
> AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
> + fw_shared->smu_interface_info.smu_interface_type = 1;
> + }
>
>   if (amdgpu_vcnfw_log)
>   amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);


Kind regards,

Paul

RE: [PATCH V2] drm/amdgpu/vcn3: send smu interface type

[Zhang, Boyuan]

[AMD Official Use Only]

Hi Paul,

I just sent out V3, which re-ordered the if/else condition as you suggested.

By the way, both V2 and V3 can be applied successfully on my local machine. In 
case it still doesn't apply on your side, can I ask which branch are you using?

Thanks,
Boyuan

-Original Message-
From: Paul Menzel 
Sent: March 25, 2022 2:10 AM
To: Zhang, Boyuan 
Cc: Deucher, Alexander ; Zhang, Yifan 
; Huang, Ray ; Liu, Leo 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH V2] drm/amdgpu/vcn3: send smu interface type

Dear Boyuan,


Am 25.03.22 um 06:53 schrieb Paul Menzel:
> Dear Boyuan,
>
>
> Thank for the improved patch.
>
>
> Am 24.03.22 um 18:25 schrieb Zhang, Boyuan:
>> [AMD Official Use Only]
>
> No idea if this would confuse `git am`.
>
>> From: Boyuan Zhang
>> mailto:boyuan.zh...@amd.com>>
>
> Your mailer(?) mangled the patch. Did you edit it in your MUA’s
> compose window?
>
>> For VCN FW to detect ASIC type, in order to use different mailbox
>> registers.
>>
>> V2: simplify codes and fix format issue.
>>
>> Signed-off-by: Boyuan Zhang
>> mailto:boyuan.zh...@amd.com>>
>> Acked-by Huang Rui 
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 7 +++
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 5 +
>> 2 files changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index e2fde88aaf5e..f06fb7f882e2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -159,6 +159,7 @@
>> #define AMDGPU_VCN_MULTI_QUEUE_FLAG   (1 << 8) #define
>> AMDGPU_VCN_SW_RING_FLAG  (1 << 9) #define
>> AMDGPU_VCN_FW_LOGGING_FLAG (1 << 10)
>> +#define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
>>   #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER0x0001 #define
>> AMDGPU_VCN_CMD_FLAG_MSG_BUFFER 0x0001 @@
>> -279,6 +280,11 @@ struct amdgpu_fw_shared_fw_logging {
>> uint32_t size;
>> };
>> +struct amdgpu_fw_shared_smu_interface_info {
>> + uint8_t smu_interface_type;
>> + uint8_t padding[3];
>> +};
>> +
>> struct amdgpu_fw_shared {
>> uint32_t present_flag_0;
>> uint8_t pad[44];
>> @@ -287,6 +293,7 @@ struct amdgpu_fw_shared {
>> struct amdgpu_fw_shared_multi_queue multi_queue;
>> struct amdgpu_fw_shared_sw_ring sw_ring;
>> struct amdgpu_fw_shared_fw_logging fw_log;
>> + struct amdgpu_fw_shared_smu_interface_info
>> smu_interface_info;
>> };
>>   struct amdgpu_vcn_fwlog {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index b16c56aa2d22..9925b2bc63b9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -219,6 +219,11 @@ static int vcn_v3_0_sw_init(void *handle)
>>
>> cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
>>
>> cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
>> fw_shared->sw_ring.is_enabled =
>> cpu_to_le32(DEC_SW_RING_ENABLED);
>> + fw_shared->present_flag_0 |=
>> AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
>> + if (adev->ip_versions[UVD_HWIP][0] ==
>> IP_VERSION(3, 1, 2))
>> +
>> fw_shared->smu_interface_info.smu_interface_type = 2;
>> + else if (adev->ip_versions[UVD_HWIP][0]
>> == IP_VERSION(3, 1, 1))

As commented on patch v1, please also put (3, 1, 1) first.

>> +
>> fw_shared->smu_interface_info.smu_interface_type = 1;
>>  if (amdgpu_vcnfw_log)
>>
>> amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
>> --
>> 2.25.1
>
> The whole patch cannot be applied. Did `scripts/checkpatch.pl` not
> detect this? Please fix and resend.


Kind regards,

Paul

RE: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

[Zhang, Boyuan]

This patch is 
Reviewed-by: Boyuan Zhang 


-Original Message-
From: amd-gfx  On Behalf Of Leo Liu
Sent: December 11, 2019 2:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Leo 
Subject: [PATCH] drm/amdgpu: add JPEG check to VCN idle handler and begin use

Since it's only needed with VCN1.0 when HW has no its own JPEG HW IP block

Signed-off-by: Leo Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 29 +++--  
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
 2 files changed, 20 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 428cfd58b37d..95ac721f2de0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -186,6 +186,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
}
}
 
+   adev->vcn.has_jpeg_block = (amdgpu_device_ip_get_ip_block(adev, 
AMD_IP_BLOCK_TYPE_JPEG)) ?
+   true : false;
+
return 0;
 }
 
@@ -306,15 +309,17 @@ static void amdgpu_vcn_idle_work_handler(struct 
work_struct *work)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
-
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
adev->vcn.pause_dpg_mode(adev, &new_state);
}
 
-   fence[j] += 
amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec);
+   if (!adev->vcn.has_jpeg_block)
+   fence[j] += 
+amdgpu_fence_count_emitted(&adev->jpeg.inst[j].ring_dec);
fence[j] += 
amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
fences += fence[j];
}
@@ -358,14 +363,16 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
else
new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-   if 
(amdgpu_fence_count_emitted(&adev->jpeg.inst[ring->me].ring_dec))
-   new_state.jpeg = VCN_DPG_STATE__PAUSE;
-   else
-   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   if (!adev->vcn.has_jpeg_block) {
+   if 
(amdgpu_fence_count_emitted(&adev->jpeg.inst[ring->me].ring_dec))
+   new_state.jpeg = VCN_DPG_STATE__PAUSE;
+   else
+   new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
+   }
 
if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
new_state.fw_based = VCN_DPG_STATE__PAUSE;
-   else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
+   else if (!adev->vcn.has_jpeg_block && ring->funcs->type == 
+AMDGPU_RING_TYPE_VCN_JPEG)
new_state.jpeg = VCN_DPG_STATE__PAUSE;
 
adev->vcn.pause_dpg_mode(adev, &new_state); diff --git 
a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 402a5046b985..9a2381d006c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -192,6 +192,8 @@ struct amdgpu_vcn {
unsignedharvest_config;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
struct dpg_pause_state *new_state);
+
+   bool has_jpeg_block;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
--
2.17.1

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RE: [PATCH libdrm] tests/amdgpu/vcn: fix the nop command in IBs

[Zhang, Boyuan]

Patch is 
Reviewed-by: Boyuan Zhang 

Regards,
Boyuan

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Liu, 
Leo
Sent: December-11-18 4:04 PM
To: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org
Cc: Liu, Leo
Subject: [PATCH libdrm] tests/amdgpu/vcn: fix the nop command in IBs

Just make them properly i.e. put 0 to the Nop reg

Signed-off-by: Leo Liu 
---
 tests/amdgpu/vcn_tests.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c
index d9f05af8..859ec496 100644
--- a/tests/amdgpu/vcn_tests.c
+++ b/tests/amdgpu/vcn_tests.c
@@ -268,8 +268,10 @@ static void amdgpu_cs_vcn_dec_create(void)
ib_cpu[len++] = msg_buf.addr >> 32;
ib_cpu[len++] = 0x81C3;
ib_cpu[len++] = 0;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x81ff;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }
 
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
@@ -336,8 +338,10 @@ static void amdgpu_cs_vcn_dec_decode(void)
 
ib_cpu[len++] = 0x81C6;
ib_cpu[len++] = 0x1;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x8000;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }
 
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
@@ -373,8 +377,10 @@ static void amdgpu_cs_vcn_dec_destroy(void)
ib_cpu[len++] = msg_buf.addr >> 32;
ib_cpu[len++] = 0x81C3;
ib_cpu[len++] = 0;
-   for (; len % 16; ++len)
-   ib_cpu[len] = 0x8000;
+   for (; len % 16; ) {
+   ib_cpu[len++] = 0x81ff;
+   ib_cpu[len++] = 0;
+   }
 
r = submit(len, AMDGPU_HW_IP_VCN_DEC);
CU_ASSERT_EQUAL(r, 0);
-- 
2.17.1

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Re: [PATCH 3/5] drm/amdgpu: enable system interrupt for jrbc

[Zhang, Boyuan]

Yes, agree! It's better to use that existing function. Will change it 
accordingly.


Thanks,

Boyuan


From: Liu, Leo
Sent: July 19, 2018 2:13:50 PM
To: Zhang, Boyuan; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/amdgpu: enable system interrupt for jrbc



On 07/18/2018 04:39 PM, boyuan.zh...@amd.com wrote:
> From: Boyuan Zhang 
>
> Enable system interrupt for jrbc during engine starting time.
>
> Signed-off-by: Boyuan Zhang 
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 +++-
>   1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 4fccb21..22c1588 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -595,6 +595,7 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
>struct amdgpu_ring *ring = &adev->vcn.ring_dec;
>uint32_t rb_bufsz, tmp;
>uint32_t lmi_swap_cntl;
> + uint32_t reg_temp;
>int i, j, r;
>
>/* disable byte swapping */
> @@ -700,6 +701,11 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
>(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
>~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
>
> + /* enable system interrupt for JRBC*/
> + reg_temp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN));
> + reg_temp |= UVD_SYS_INT_EN__UVD_JRBC_EN_MASK;
> + WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), reg_temp);

Here you could use below instead.
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 
UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);

Ether way, the whole series are
Acked-by: Leo Liu 



> +
>/* clear the bit 4 of VCN_STATUS */
>WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
>~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
> @@ -1754,7 +1760,7 @@ static const struct amdgpu_irq_src_funcs 
> vcn_v1_0_irq_funcs = {
>
>   static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
>   {
> - adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
> + adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
>adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
>   }
>

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drm/amdgpu update uvd 7.0 enc test

[Zhang, Boyuan]

Update UVD 7.0 enc test according to firmware interface changes for session 
info ib.


Please review.


Regards,

Boyuan

From 41a3084055bb070b0541315cef5cfa7356624afa Mon Sep 17 00:00:00 2001
From: Boyuan Zhang 
Date: Tue, 15 Aug 2017 16:29:37 -0400
Subject: [PATCH] drm/amdgpu: update uvd enc test for new fw

session info interface changed due to fw interface changes,
update test ib accordingly.

Signed-off-by: Boyuan Zhang 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 23a8575..466aff9 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -225,8 +225,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
 	ib->length_dw = 0;
 	ib->ptr[ib->length_dw++] = 0x0018;
 	ib->ptr[ib->length_dw++] = 0x0001; /* session info */
-	ib->ptr[ib->length_dw++] = handle;
 	ib->ptr[ib->length_dw++] = 0x;
+	ib->ptr[ib->length_dw++] = 0x0001;
 	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 	ib->ptr[ib->length_dw++] = dummy;
 
@@ -288,8 +288,8 @@ int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 	ib->length_dw = 0;
 	ib->ptr[ib->length_dw++] = 0x0018;
 	ib->ptr[ib->length_dw++] = 0x0001;
-	ib->ptr[ib->length_dw++] = handle;
 	ib->ptr[ib->length_dw++] = 0x;
+	ib->ptr[ib->length_dw++] = 0x0001;
 	ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 	ib->ptr[ib->length_dw++] = dummy;
 
-- 
2.7.4

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Re: [PATCH] drm/amdgpu/vcn: fix idle work handler for VCN 2.5

[Zhang, Boyuan]

[AMD Official Use Only - AMD Internal Distribution Only]


V4 is Reviewed-by: Boyuan Zhang 



From: amd-gfx  on behalf of Alex Deucher 

Sent: March 7, 2025 10:22 AM
To: Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org 
Subject: Re: [PATCH] drm/amdgpu/vcn: fix idle work handler for VCN 2.5

Ping?  This fixes a regression on VCN 2.5.

Thanks,

Alex

On Thu, Mar 6, 2025 at 10:05 AM Alex Deucher  wrote:
>
> Ping?
>
> Thanks,
>
> Alex
>
> On Wed, Mar 5, 2025 at 2:42 PM Alex Deucher  wrote:
> >
> > VCN 2.5 uses the PG callback to enable VCN DPM which is
> > a global state.  As such, we need to make sure all instances
> > are in the same state.
> >
> > v2: switch to a ref count (Lijo)
> > v3: switch to its own idle work handler
> > v4: fix logic in DPG handling
> >
> > Fixes: 4ce4fe27205c ("drm/amdgpu/vcn: use per instance callbacks for idle 
> > work handler")
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 120 +-
> >  1 file changed, 116 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 
> > b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > index dff1a88590363..ff03436698a4f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> > @@ -107,6 +107,115 @@ static int amdgpu_ih_clientid_vcns[] = {
> > SOC15_IH_CLIENTID_VCN1
> >  };
> >
> > +static void vcn_v2_5_idle_work_handler(struct work_struct *work)
> > +{
> > +   struct amdgpu_vcn_inst *vcn_inst =
> > +   container_of(work, struct amdgpu_vcn_inst, idle_work.work);
> > +   struct amdgpu_device *adev = vcn_inst->adev;
> > +   unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
> > +   unsigned int i, j;
> > +   int r = 0;
> > +
> > +   for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> > +   struct amdgpu_vcn_inst *v = &adev->vcn.inst[i];
> > +
> > +   if (adev->vcn.harvest_config & (1 << i))
> > +   continue;
> > +
> > +   for (j = 0; j < v->num_enc_rings; ++j)
> > +   fence[i] += 
> > amdgpu_fence_count_emitted(&v->ring_enc[j]);
> > +
> > +   /* Only set DPG pause for VCN3 or below, VCN4 and above 
> > will be handled by FW */
> > +   if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
> > +   !v->using_unified_queue) {
> > +   struct dpg_pause_state new_state;
> > +
> > +   if (fence[i] ||
> > +   
> > unlikely(atomic_read(&v->dpg_enc_submission_cnt)))
> > +   new_state.fw_based = VCN_DPG_STATE__PAUSE;
> > +   else
> > +   new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
> > +
> > +   v->pause_dpg_mode(v, &new_state);
> > +   }
> > +
> > +   fence[i] += amdgpu_fence_count_emitted(&v->ring_dec);
> > +   fences += fence[i];
> > +
> > +   }
> > +
> > +   if (!fences && 
> > !atomic_read(&adev->vcn.inst[0].total_submission_cnt)) {
> > +   amdgpu_device_ip_set_powergating_state(adev, 
> > AMD_IP_BLOCK_TYPE_VCN,
> > +  AMD_PG_STATE_GATE);
> > +   r = amdgpu_dpm_switch_power_profile(adev, 
> > PP_SMC_POWER_PROFILE_VIDEO,
> > +   false);
> > +   if (r)
> > +   dev_warn(adev->dev, "(%d) failed to disable video 
> > power profile mode\n", r);
> > +   } else {
> > +   schedule_delayed_work(&adev->vcn.inst[0].idle_work, 
> > VCN_IDLE_TIMEOUT);
> > +   }
> > +}
> > +
> > +static void vcn_v2_5_ring_begin_use(struct amdgpu_ring *ring)
> > +{
> > +   struct amdgpu_device *adev = ring->adev;
> > +   struct amdgpu_vcn_inst *v = &adev->vcn.inst[ring->me];
> > +   int r = 0;
> > +
> > +   atomic_inc(&adev->vcn.inst[0].total_submission_cnt);
> > +
> > +   if (!cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work)) {
> > +   r = amdgpu_dpm_switch_power_profile(adev, 
> > PP_SMC_POWER_PROFILE_VIDEO,
> > +   true);
> > +   if (r)
> > +   dev_warn(adev->dev, "(%d) failed to switch to video 
> > power profile mode\n", r);
> > +   }
> > +
> > +   mutex_lock(&adev->vcn.inst[0].vcn_pg_lock);
> > +   amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
> > +  AMD_PG_STATE_UNGATE);
> > +
> > +   /* Only set DPG pause for VCN3 or below, VCN4 and above will be 
> > handled by FW */
> > +   if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
> > +   !v->using_unified_queue) {
> > +   struct dpg_pause_state new_state;
> > +
> > +   if (rin

Re: [PATCH] drm/amdgpu/vcn2.5: fix VCN stop logic

[Zhang, Boyuan]

[AMD Official Use Only - AMD Internal Distribution Only]


Reviewed-by: Boyuan Zhang <mailto:boyuan.zh...@amd.com>


From: Alex Deucher 
Sent: February 25, 2025 10:07 AM
To: Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org ; Zhang, 
Boyuan 
Subject: Re: [PATCH] drm/amdgpu/vcn2.5: fix VCN stop logic

Ping?

On Mon, Feb 24, 2025 at 2:39 PM Alex Deucher  wrote:
>
> Need to make sure we call amdgpu_dpm_enable_vcn()
> in vcn_v2_5_stop() at the end if there are errors
> or DPG is enabled.
>
> Fixes: ebc25499de12 ("drm/amdgpu/vcn2.5: split code along instances")
> Suggested-by: Boyuan Zhang 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 15 +--
>  1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index a6726afcf89cb..e36e2a5676df9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1414,13 +1414,15 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, 
> int i)
>
> if (adev->vcn.harvest_config & (1 << i))
> return 0;
> -   if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> -   return vcn_v2_5_stop_dpg_mode(adev, i);
> +   if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> +   r = vcn_v2_5_stop_dpg_mode(adev, i);
> +   goto done;
> +   }
>
> /* wait for vcn idle */
> r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
> if (r)
> -   return r;
> +   goto done;
>
> tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
> UVD_LMI_STATUS__READ_CLEAN_MASK |
> @@ -1428,7 +1430,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, 
> int i)
> UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
> r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
> if (r)
> -   return r;
> +   goto done;
>
> /* block LMI UMC channel */
> tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
> @@ -1439,7 +1441,7 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, 
> int i)
> UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
> r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
> if (r)
> -   return r;
> +   goto done;
>
> /* block VCPU register access */
> WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
> @@ -1465,10 +1467,11 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev, 
> int i)
>  UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
>  ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
>
> +done:
> if (adev->pm.dpm_enabled)
> amdgpu_dpm_enable_vcn(adev, false, i);
>
> -   return 0;
> +   return r;
>  }
>
>  static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
> --
> 2.48.1
>