[PATCH 08/29] drm/amdgpu: pass ip_block in set_clockgating_state
From: Boyuan Zhang Pass ip_block instead of adev in set_clockgating_state() callback functions. Modify set_clockgating_state()for all correspoding ip blocks. v2: remove all changes for is_idle(), remove type casting Signed-off-by: Boyuan Zhang Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cz_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 13 - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 13 - drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 8 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 7 --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/a
Re: [PATCH 2/2] drm: remove driver date from struct drm_driver and all drivers
Hi Jani,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on next-20241024]
[cannot apply to drm-exynos/exynos-drm-next shawnguo/for-next
drm-xe/drm-xe-next linus/master v6.12-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-remove-driver-date-from-struct-drm_driver-and-all-drivers/20241025-002344
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20241024162240.2398664-2-jani.nikula%40intel.com
patch subject: [PATCH 2/2] drm: remove driver date from struct drm_driver and
all drivers
config: i386-buildonly-randconfig-004-20241025
(https://download.01.org/0day-ci/archive/20241025/202410251351.r16zfufe-...@intel.com/config)
compiler: gcc-12 (Debian 12.2.0-14) 12.2.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20241025/202410251351.r16zfufe-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202410251351.r16zfufe-...@intel.com/
All warnings (new ones prefixed by >>):
drivers/accel/qaic/qaic_drv.c:211:10: error: 'const struct drm_driver' has
no member named 'date'
211 | .date = "20190618",
| ^~~~
>> drivers/accel/qaic/qaic_drv.c:211:35: warning: initialization of 'unsigned
>> int' from 'char *' makes integer from pointer without a cast
>> [-Wint-conversion]
211 | .date = "20190618",
| ^~
drivers/accel/qaic/qaic_drv.c:211:35: note: (near initialization for
'qaic_accel_driver.driver_features')
drivers/accel/qaic/qaic_drv.c:211:35: warning: initialized field overwritten
[-Woverride-init]
drivers/accel/qaic/qaic_drv.c:211:35: note: (near initialization for
'qaic_accel_driver.driver_features')
vim +211 drivers/accel/qaic/qaic_drv.c
c501ca23a6a306 Jeffrey Hugo 2023-03-27 205
c501ca23a6a306 Jeffrey Hugo 2023-03-27 206 static const struct drm_driver
qaic_accel_driver = {
c501ca23a6a306 Jeffrey Hugo 2023-03-27 207 .driver_features=
DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 208
c501ca23a6a306 Jeffrey Hugo 2023-03-27 209 .name =
QAIC_NAME,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 210 .desc =
QAIC_DESC,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 @211 .date =
"20190618",
c501ca23a6a306 Jeffrey Hugo 2023-03-27 212
c501ca23a6a306 Jeffrey Hugo 2023-03-27 213 .fops =
&qaic_accel_fops,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 214 .open =
qaic_open,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 215 .postclose =
qaic_postclose,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 216
c501ca23a6a306 Jeffrey Hugo 2023-03-27 217 .ioctls =
qaic_drm_ioctls,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 218 .num_ioctls =
ARRAY_SIZE(qaic_drm_ioctls),
c501ca23a6a306 Jeffrey Hugo 2023-03-27 219 .gem_prime_import =
qaic_gem_prime_import,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 220 };
c501ca23a6a306 Jeffrey Hugo 2023-03-27 221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Re: [PATCH 2/2] drm: remove driver date from struct drm_driver and all drivers
Hi Jani,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on next-20241024]
[cannot apply to drm-exynos/exynos-drm-next shawnguo/for-next
drm-xe/drm-xe-next linus/master v6.12-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-remove-driver-date-from-struct-drm_driver-and-all-drivers/20241025-002344
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20241024162240.2398664-2-jani.nikula%40intel.com
patch subject: [PATCH 2/2] drm: remove driver date from struct drm_driver and
all drivers
config: loongarch-allmodconfig
(https://download.01.org/0day-ci/archive/20241025/202410251306.cos7w98u-...@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 14.1.0
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20241025/202410251306.cos7w98u-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202410251306.cos7w98u-...@intel.com/
All errors (new ones prefixed by >>):
>> drivers/accel/qaic/qaic_drv.c:211:10: error: 'const struct drm_driver' has
>> no member named 'date'
211 | .date = "20190618",
| ^~~~
>> drivers/accel/qaic/qaic_drv.c:211:35: error: initialization of 'unsigned
>> int' from 'char *' makes integer from pointer without a cast
>> [-Wint-conversion]
211 | .date = "20190618",
| ^~
drivers/accel/qaic/qaic_drv.c:211:35: note: (near initialization for
'qaic_accel_driver.driver_features')
>> drivers/accel/qaic/qaic_drv.c:211:35: error: initializer element is not
>> computable at load time
drivers/accel/qaic/qaic_drv.c:211:35: note: (near initialization for
'qaic_accel_driver.driver_features')
vim +211 drivers/accel/qaic/qaic_drv.c
c501ca23a6a306 Jeffrey Hugo 2023-03-27 205
c501ca23a6a306 Jeffrey Hugo 2023-03-27 206 static const struct drm_driver
qaic_accel_driver = {
c501ca23a6a306 Jeffrey Hugo 2023-03-27 207 .driver_features=
DRIVER_GEM | DRIVER_COMPUTE_ACCEL,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 208
c501ca23a6a306 Jeffrey Hugo 2023-03-27 209 .name =
QAIC_NAME,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 210 .desc =
QAIC_DESC,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 @211 .date =
"20190618",
c501ca23a6a306 Jeffrey Hugo 2023-03-27 212
c501ca23a6a306 Jeffrey Hugo 2023-03-27 213 .fops =
&qaic_accel_fops,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 214 .open =
qaic_open,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 215 .postclose =
qaic_postclose,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 216
c501ca23a6a306 Jeffrey Hugo 2023-03-27 217 .ioctls =
qaic_drm_ioctls,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 218 .num_ioctls =
ARRAY_SIZE(qaic_drm_ioctls),
c501ca23a6a306 Jeffrey Hugo 2023-03-27 219 .gem_prime_import =
qaic_gem_prime_import,
c501ca23a6a306 Jeffrey Hugo 2023-03-27 220 };
c501ca23a6a306 Jeffrey Hugo 2023-03-27 221
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
RE: [PATCH] drm/amdgpu/smu13: fix profile reporting
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Kenneth Feng kenneth.f...@amd.com
-Original Message-
From: amd-gfx On Behalf Of Alex Deucher
Sent: Friday, October 25, 2024 6:10 AM
To: Deucher, Alexander
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/smu13: fix profile reporting
Caution: This message originated from an External Source. Use proper caution
when opening attachments, clicking links, or responding.
Ping?
On Wed, Oct 23, 2024 at 9:23 AM Alex Deucher wrote:
>
> The following 3 commits landed in parallel:
> commit d7d2688bf4ea ("drm/amd/pm: update workload mask after the
> setting") commit 7a1613e47e65 ("drm/amdgpu/smu13: always apply the
> powersave optimization") commit 7c210ca5a2d7 ("drm/amdgpu: handle
> default profile on on devices without fullscreen 3D") While everything
> is set correctly, this caused the profile to be reported incorrectly
> because both the powersave and fullscreen3d bits were set in the mask
> and when the driver prints the profile, it looks for the first bit set.
>
> Fixes: d7d2688bf4ea ("drm/amd/pm: update workload mask after the
> setting")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index cb923e33fd6f..d53e162dcd8d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2485,7 +2485,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> DpmActivityMonitorCoeffInt_t *activity_monitor =
> &(activity_monitor_external.DpmActivityMonitorCoeffInt);
> int workload_type, ret = 0;
> - u32 workload_mask;
> + u32 workload_mask, selected_workload_mask;
>
> smu->power_profile_mode = input[size];
>
> @@ -2552,7 +2552,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> if (workload_type < 0)
> return -EINVAL;
>
> - workload_mask = 1 << workload_type;
> + selected_workload_mask = workload_mask = 1 << workload_type;
>
> /* Add optimizations for SMU13.0.0/10. Reuse the power saving
> profile */
> if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> IP_VERSION(13, 0, 0) && @@ -2572,7 +2572,7 @@ static int
> smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
>workload_mask,
>NULL);
> if (!ret)
> - smu->workload_mask = workload_mask;
> + smu->workload_mask = selected_workload_mask;
>
> return ret;
> }
> --
> 2.46.2
>
Re: [PATCH 2/2] drm: remove driver date from struct drm_driver and all drivers
Hi Jani,
kernel test robot noticed the following build errors:
[auto build test ERROR on drm-misc/drm-misc-next]
[also build test ERROR on next-20241024]
[cannot apply to drm-exynos/exynos-drm-next shawnguo/for-next
drm-xe/drm-xe-next linus/master v6.12-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url:
https://github.com/intel-lab-lkp/linux/commits/Jani-Nikula/drm-remove-driver-date-from-struct-drm_driver-and-all-drivers/20241025-002344
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link:
https://lore.kernel.org/r/20241024162240.2398664-2-jani.nikula%40intel.com
patch subject: [PATCH 2/2] drm: remove driver date from struct drm_driver and
all drivers
config: s390-allmodconfig
(https://download.01.org/0day-ci/archive/20241025/202410251345.na1ihu0x-...@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project
5886454669c3c9026f7f27eab13509dd0241f2d6)
reproduce (this is a W=1 build):
(https://download.01.org/0day-ci/archive/20241025/202410251345.na1ihu0x-...@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot
| Closes:
https://lore.kernel.org/oe-kbuild-all/202410251345.na1ihu0x-...@intel.com/
All errors (new ones prefixed by >>):
In file included from drivers/accel/qaic/qaic_drv.c:7:
In file included from include/linux/dma-mapping.h:8:
In file included from include/linux/device.h:32:
In file included from include/linux/device/driver.h:21:
In file included from include/linux/module.h:19:
In file included from include/linux/elf.h:6:
In file included from arch/s390/include/asm/elf.h:181:
In file included from arch/s390/include/asm/mmu_context.h:11:
In file included from arch/s390/include/asm/pgalloc.h:18:
In file included from include/linux/mm.h:2213:
include/linux/vmstat.h:504:43: warning: arithmetic between different
enumeration types ('enum zone_stat_item' and 'enum numa_stat_item')
[-Wenum-enum-conversion]
504 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
|~ ^
505 |item];
|
include/linux/vmstat.h:511:43: warning: arithmetic between different
enumeration types ('enum zone_stat_item' and 'enum numa_stat_item')
[-Wenum-enum-conversion]
511 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
|~ ^
512 |NR_VM_NUMA_EVENT_ITEMS +
|~~
include/linux/vmstat.h:518:36: warning: arithmetic between different
enumeration types ('enum node_stat_item' and 'enum lru_list')
[-Wenum-enum-conversion]
518 | return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
| ~~~ ^ ~~~
include/linux/vmstat.h:524:43: warning: arithmetic between different
enumeration types ('enum zone_stat_item' and 'enum numa_stat_item')
[-Wenum-enum-conversion]
524 | return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
|~ ^
525 |NR_VM_NUMA_EVENT_ITEMS +
|~~
In file included from drivers/accel/qaic/qaic_drv.c:7:
In file included from include/linux/dma-mapping.h:11:
In file included from include/linux/scatterlist.h:9:
In file included from arch/s390/include/asm/io.h:93:
include/asm-generic/io.h:548:31: warning: performing pointer arithmetic on a
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
548 | val = __raw_readb(PCI_IOBASE + addr);
| ~~ ^
include/asm-generic/io.h:561:61: warning: performing pointer arithmetic on a
null pointer has undefined behavior [-Wnull-pointer-arithmetic]
561 | val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE +
addr));
| ~~ ^
include/uapi/linux/byteorder/big_endian.h:37:59: note: expanded from macro
'__le16_to_cpu'
37 | #define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
| ^
include/uapi/linux/swab.h:102:54: note: expanded from macro '__swab16'
102 | #define __swab16(x) (__u16)__builtin_bswap16((__u16)(x))
| ^
In file included from drivers/accel/qa
[PATCH 14/29] drm/amdgpu: power vcn 4_0 by instance
From: Boyuan Zhang
For vcn 4_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 495 +-
2 files changed, 245 insertions(+), 253 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2a606e8c6930..aaa759765dba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2347,7 +2347,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2):
case IP_VERSION(4, 0, 4):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v4_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 87c8f1c084a5..0cc0eb52b54f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -172,7 +172,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
+
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
uint32_t *ptr;
@@ -186,45 +187,43 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* Init instance 0 sched_score to 1, so it's scheduled after
other instances */
- if (i == 0)
- atomic_set(&adev->vcn.inst[i].sched_score, 1);
- else
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ /* Init instance 0 sched_score to 1, so it's scheduled after other
instances */
+ if (inst == 0)
+ atomic_set(&adev->vcn.inst[inst].sched_score, 1);
+ else
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON,
&adev->vcn.inst[i].ras_poison_irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON,
&adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1)
+ 1;
- else
- ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0,
&adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 <<
1) + inst * (adev->vcn.num_enc_rings + 1) + 1;
+ else
+ ring->doorbell_inde
[PATCH 10/29] drm/amdgpu: move per inst variables to amdgpu_vcn_inst
From: Boyuan Zhang
Move all per instance variables from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.fw[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_config[i] from amdgpu_vcn to amdgpu_vcn_inst.
Move adev->vcn.vcn_codec_disable_mask[i] from amdgpu_vcn to amdgpu_vcn_inst.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 20 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++--
11 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 73f4d56c5de4..cce3f1a6f288 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1340,7 +1340,7 @@ static int amdgpu_discovery_reg_base_init(struct
amdgpu_device *adev)
*/
if (adev->vcn.num_vcn_inst <
AMDGPU_MAX_VCN_INSTANCES) {
-
adev->vcn.vcn_config[adev->vcn.num_vcn_inst] =
+
adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config =
ip->revision & 0xc0;
adev->vcn.num_vcn_inst++;
adev->vcn.inst_mask |=
@@ -1705,7 +1705,7 @@ static int amdgpu_discovery_get_vcn_info(struct
amdgpu_device *adev)
* so this won't overflow.
*/
for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
- adev->vcn.vcn_codec_disable_mask[v] =
+ adev->vcn.inst[v].vcn_codec_disable_mask =
le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
}
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index aecb78e0519f..49802e66a358 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -99,11 +99,11 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev)
amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix,
sizeof(ucode_prefix));
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) ==
IP_VERSION(4, 0, 6))
- r = amdgpu_ucode_request(adev, &adev->vcn.fw[i],
"amdgpu/%s_%d.bin", ucode_prefix, i);
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
"amdgpu/%s_%d.bin", ucode_prefix, i);
else
- r = amdgpu_ucode_request(adev, &adev->vcn.fw[i],
"amdgpu/%s.bin", ucode_prefix);
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
"amdgpu/%s.bin", ucode_prefix);
if (r) {
- amdgpu_ucode_release(&adev->vcn.fw[i]);
+ amdgpu_ucode_release(&adev->vcn.inst[i].fw);
return r;
}
}
@@ -151,7 +151,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
adev->vcn.using_unified_queue =
amdgpu_ip_version(adev, UVD_HWIP, 0) >= IP_VERSION(4, 0, 0);
- hdr = (const struct common_firmware_header *)adev->vcn.fw[0]->data;
+ hdr = (const struct common_firmware_header *)adev->vcn.inst[0].fw->data;
adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
/* Bit 20-23, it is encode major and non-zero for new naming convention.
@@ -270,7 +270,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
- amdgpu_ucode_release(&adev->vcn.fw[j]);
+ amdgpu_ucode_release(&adev->vcn.inst[j].fw);
}
mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
@@ -282,7 +282,7 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type
type, uint32_t vcn_instance)
{
bool ret = false;
- int vcn_config = adev->vcn.vcn_config[vcn_instance];
+ int vcn_config = adev->vcn.inst[vcn_instance].vcn_config;
if ((type == VCN_ENCODE_RING) && (vcn_config &
VCN_BLOCK_ENCODE_DISABLE_MASK))
ret = t
[PATCH v4] drm/amdkfd: Use dynamic allocation for CU occupancy array in 'kfd_get_cu_occupancy()'
The `kfd_get_cu_occupancy` function previously declared a large
`cu_occupancy` array as a local variable, which could lead to stack
overflows due to excessive stack usage. This commit replaces the static
array allocation with dynamic memory allocation using `kcalloc`,
thereby reducing the stack size.
This change avoids the risk of stack overflows in kernel space, in
scenarios where `AMDGPU_MAX_QUEUES` is large. The allocated memory is
freed using `kfree` before the function returns to prevent memory
leaks.
Fixes the below with gcc W=1:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c: In function
‘kfd_get_cu_occupancy’:
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.c:322:1: warning: the frame
size of 1056 bytes is larger than 1024 bytes [-Wframe-larger-than=]
322 | }
| ^
Fixes: 6fc91266b798 ("drm/amdkfd: Update logic for CU occupancy calculations")
Cc: Harish Kasiviswanathan
Cc: Felix Kuehling
Cc: Christian König
Cc: Alex Deucher
Signed-off-by: Srinivasan Shanmugam
Suggested-by: Mukul Joshi
---
v4:
- Allocation is moved just before it's needed (Mukul)
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
index d4aa843aacfd..6bab6fc6a35d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c
@@ -271,11 +271,9 @@ static int kfd_get_cu_occupancy(struct attribute *attr,
char *buffer)
struct kfd_process *proc = NULL;
struct kfd_process_device *pdd = NULL;
int i;
- struct kfd_cu_occupancy cu_occupancy[AMDGPU_MAX_QUEUES];
+ struct kfd_cu_occupancy *cu_occupancy;
u32 queue_format;
- memset(cu_occupancy, 0x0, sizeof(cu_occupancy));
-
pdd = container_of(attr, struct kfd_process_device, attr_cu_occupancy);
dev = pdd->dev;
if (dev->kfd2kgd->get_cu_occupancy == NULL)
@@ -293,6 +291,10 @@ static int kfd_get_cu_occupancy(struct attribute *attr,
char *buffer)
wave_cnt = 0;
max_waves_per_cu = 0;
+ cu_occupancy = kcalloc(AMDGPU_MAX_QUEUES, sizeof(*cu_occupancy),
GFP_KERNEL);
+ if (!cu_occupancy)
+ return -ENOMEM;
+
/*
* For GFX 9.4.3, fetch the CU occupancy from the first XCC in the
partition.
* For AQL queues, because of cooperative dispatch we multiply the wave
count
@@ -318,6 +320,7 @@ static int kfd_get_cu_occupancy(struct attribute *attr,
char *buffer)
/* Translate wave count to number of compute units */
cu_cnt = (wave_cnt + (max_waves_per_cu - 1)) / max_waves_per_cu;
+ kfree(cu_occupancy);
return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt);
}
--
2.34.1
Re: [PATCH 07/32] drm/amdgpu: pass ip_block in set_powergating_state
On 2024-10-22 03:42, Khatri, Sunil wrote: On 10/17/2024 6:50 PM, boyuan.zh...@amd.com wrote: From: Boyuan Zhang Pass ip_block instead of adev in set_powergating_state callback function. Modify set_powergating_state ip functions for all correspoding ip blocks. v2: fix a ip block index error. Signed-off-by: Boyuan Zhang Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 5 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 13 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/veg
[PATCH 01/29] drm/amd/pm: add inst to dpm_set_vcn_enable
From: Boyuan Zhang
Add an instance parameter to the existing function dpm_set_vcn_enable()
for future implementation. Re-write all pptable functions accordingly.
v2: Remove duplicated dpm_set_vcn_enable() functions in v1. Instead,
adding instance parameter to existing functions.
Signed-off-by: Boyuan Zhang
Suggested-by: Christian König
Suggested-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h| 3 ++-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h| 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c| 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 ++-
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c| 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c| 4 +++-
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 3 ++-
13 files changed, 31 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 8d4aee4e2287..fe2a740766a2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -252,7 +252,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (atomic_read(&power_gate->vcn_gated) ^ enable)
return 0;
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff);
if (!ret)
atomic_set(&power_gate->vcn_gated, !enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 8bb32b3f0d9c..4ebcc1e53ea2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -739,7 +739,7 @@ struct pptable_funcs {
* @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
* management.
*/
- int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
+ int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable, int
inst);
/**
* @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 044d6893b43e..ae3563d71fa0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -255,7 +255,8 @@ int smu_v13_0_wait_for_event(struct smu_context *smu, enum
smu_event_type event,
uint64_t event_arg);
int smu_v13_0_set_vcn_enable(struct smu_context *smu,
-bool enable);
+ bool enable,
+ int inst);
int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 07c220102c1d..0546b02e198d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -210,7 +210,8 @@ int smu_v14_0_wait_for_event(struct smu_context *smu, enum
smu_event_type event,
uint64_t event_arg);
int smu_v14_0_set_vcn_enable(struct smu_context *smu,
-bool enable);
+ bool enable,
+ int inst);
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 5ad09323a29d..6c8e80f6b592 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -1571,7 +1571,9 @@ static bool arcturus_is_dpm_running(struct smu_context
*smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int arcturus_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable,
+ int inst)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 9fa305ba6422..faa8e7d9c3c6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1135,7 +1135,9 @@ static int navi10_set_default_dpm_table(struct
smu_context *smu)
[PATCH v2] drm/amdgpu: add new AMDGPU_INFO subquery for fw objects
Currently, the shadow FW space size and alignment information is
protected under a flag (adev->gfx.cp_gfx_shadow) which gets set
only in case of SRIOV setups.
if (amdgpu_sriov_vf(adev))
adev->gfx.cp_gfx_shadow = true;
But we need this information for GFX Userqueues, so that user can
create these objects while creating userqueue. This patch series
creates a method to get this information bypassing the dependency
on this check.
This patch:
- adds a new subquery (AMDGPU_INFO_FW_OBJ_SZ) in
AMDGPU_INFO_IOCTL to get the size and alignment of shadow
and csa objects from the FW setup.
- adds a new input parameter flag to the gfx.funcs->get_gfx_shadow_info
fptr definition, so that it can accommodate the information without the
check (adev->gfx.cp_gfx_shadow) on request.
- updates the existing definition of amdgpu_gfx_get_gfx_shadow_info to
adjust with this new flag.
V2: Added Alex's suggestions and addressed review comments:
- make this query IP specific (GFX/SDMA etc)
- give a better title (AMDGPU_INFO_UQ_METADATA)
- restructured the code as per sample code shared by Alex
Cc: Alex Deucher
Cc: Christian Koenig
Cc: Arvind Yadav
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 30 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 19 +++-
include/uapi/drm/amdgpu_drm.h | 24
4 files changed, 70 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index f710178a21bc..efea172c41b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -302,7 +302,8 @@ struct amdgpu_gfx_funcs {
void (*init_spm_golden)(struct amdgpu_device *adev);
void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
int (*get_gfx_shadow_info)(struct amdgpu_device *adev,
- struct amdgpu_gfx_shadow_info *shadow_info);
+ struct amdgpu_gfx_shadow_info *shadow_info,
+ bool skip_check);
enum amdgpu_gfx_partition
(*query_partition_mode)(struct amdgpu_device *adev);
int (*switch_partition_mode)(struct amdgpu_device *adev,
@@ -491,7 +492,7 @@ struct amdgpu_gfx_ras_mem_id_entry {
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id)
((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id)))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid, xcc_id)
((adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid),
(xcc_id)))
#define amdgpu_gfx_init_spm_golden(adev)
(adev)->gfx.funcs->init_spm_golden((adev))
-#define amdgpu_gfx_get_gfx_shadow_info(adev, si)
((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si)))
+#define amdgpu_gfx_get_gfx_shadow_info(adev, si)
((adev)->gfx.funcs->get_gfx_shadow_info((adev), (si), false))
/**
* amdgpu_gfx_create_bitmask - create a bitmask
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index b53c35992152..285149258882 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -371,6 +371,20 @@ static int amdgpu_firmware_info(struct
drm_amdgpu_info_firmware *fw_info,
return 0;
}
+static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev,
+struct drm_amdgpu_info *info,
+struct drm_amdgpu_info_uq_metadata_gfx *meta)
+{
+ int ret = -EOPNOTSUPP;
+
+ if (adev->gfx.funcs->get_gfx_shadow_info) {
+ adev->gfx.funcs->get_gfx_shadow_info(adev, (struct
amdgpu_gfx_shadow_info *)meta, true);
+ ret = 0;
+ }
+
+ return ret;
+}
+
static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
struct drm_amdgpu_info *info,
struct drm_amdgpu_info_hw_ip *result)
@@ -1282,6 +1296,22 @@ int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file *filp)
return copy_to_user(out, &gpuvm_fault,
min((size_t)size, sizeof(gpuvm_fault))) ?
-EFAULT : 0;
}
+ case AMDGPU_INFO_UQ_METADATA: {
+ struct drm_amdgpu_info_uq_metadata meta_info = {};
+
+ switch (info->query_hw_ip.type) {
+ case AMDGPU_HW_IP_GFX:
+ ret = amdgpu_userq_metadata_info_gfx(adev, info,
&meta_info.gfx);
+ if (ret)
+ return ret;
+
+ ret = copy_to_user(out, &meta_info,
+ min((size_t)size,
sizeof(meta_info))) ? -EFAULT : 0;
+ return 0;
+ default:
+ return -ENOTSUPP;
+
[PATCH] drm/fourcc: add AMD_FMT_MOD_TILE_GFX9_4K_D_X
From: Qiang Yu This is used when radeonsi export small texture's modifier to user with eglExportDMABUFImageQueryMESA(). mesa changes is available here: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658 Signed-off-by: Qiang Yu --- include/uapi/drm/drm_fourcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 78abd819fd62..70f3b00b0681 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -1516,6 +1516,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. */ #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 -- 2.43.0
[PATCH 13/29] drm/amdgpu: power vcn 3_0 by instance
From: Boyuan Zhang
For vcn 3_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 583 +-
2 files changed, 289 insertions(+), 297 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 6bdd4055c192..2a606e8c6930 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2336,7 +2336,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev,
&jpeg_v3_0_ip_block);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 3b38b67f6da2..690224a5e783 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -160,7 +160,7 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block
*ip_block)
static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int inst = ip_block->instance, j, r;
int vcn_doorbell_index = 0;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
uint32_t *ptr;
@@ -189,93 +189,91 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block
*ip_block)
vcn_doorbell_index = vcn_doorbell_index << 1;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low =
mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high =
mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.scratch9 = SOC15_REG_OFFSET(VCN, inst,
mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data0 = SOC15_REG_OFFSET(VCN, inst,
mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data1 = SOC15_REG_OFFSET(VCN, inst,
mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.cmd = SOC15_REG_OFFSET(VCN, inst,
mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.nop = SOC15_REG_OFFSET(VCN, inst,
mmUVD_NO_OP);
+
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
&adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
+
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- adev->vcn.internal.context_id =
mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid =
mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_low =
mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_high =
mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
- adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
- adev->vcn.internal.gp_scratch8 =
mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
-
- adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i,
mmUVD_SCRATCH9);
- adev->vcn.internal.data0 =
mmUVD_GPCOM_V
[PATCH] drm: amdgpu: fix comment about amdgpu.abmlevel defaults
Since 040fdcde288a2830edc31dd507963d6aadf990d2 ("drm/amdgpu: respect the
abmlevel module parameter value if it is set"), the default value for
amdgpu.abmlevel was set to -1, or auto. However, the comment explaining
the default value was not updated to reflect the change (-1, or auto;
not
-1, or disabled).
Clarify that the default value (-1) means auto.
Fixes: 040fdcde288a2830edc31dd507963d6aadf990d2 ("drm/amdgpu: respect
the abmlevel module parameter value if it is set")
Reported-by: Ruikai Liu
Signed-off-by: Mingcong Bai
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 81d9877c8735..b248d7096abc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -892,7 +892,7 @@ module_param_named(visualconfirm,
amdgpu_dc_visual_confirm, uint, 0444);
* the ABM algorithm, with 1 being the least reduction and 4 being the
most
* reduction.
*
- * Defaults to -1, or disabled. Userspace can only override this level
after
+ * Defaults to -1, or auto. Userspace can only override this level
after
* boot if it's set to auto.
*/
int amdgpu_dm_abm_level = -1;
--
2.47.0
[PATCH 3/4] drm/amdgpu: Stop reporting special chip memory pools as CPU memory in fdinfo
From: Tvrtko Ursulin
So far these specialized on chip memory pools were reported as system
memory (aka 'cpu') which is not correct and misleading. Lets remove that
and consider later making them visible as their own thing.
Signed-off-by: Tvrtko Ursulin
Suggested-by: Christian König
Cc: Yunxiang Li
Cc: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0d3fb6b4212e..b5f65ef1efcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1209,17 +1209,6 @@ void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
type = res->mem_type;
}
- /* Squash some into 'cpu' to keep the legacy userspace view. */
- switch (type) {
- case TTM_PL_VRAM:
- case TTM_PL_TT:
- case TTM_PL_SYSTEM:
- break;
- default:
- type = TTM_PL_SYSTEM;
- break;
- }
-
if (drm_WARN_ON_ONCE(&adev->ddev, type >= sz))
return;
--
2.46.0
[PATCH 0/4] fdinfo fixes
From: Tvrtko Ursulin I included two Teddy's patches which have been reviewed and acked and IMO makes sense to pull them in straight away. Then patch three does what Christian suggested - stops reporting GWS, GDS, OA and DOORBELL TTM regions as 'CPU' memory. Last patch is RFC in case there is value to expose the above mentioned as their own memory regions. Looks questionable since I only see all zeros so not much value for a lot of new text to parse? $ cat /proc/1967/fdinfo/4 pos: 0 flags: 0212 mnt_id: 24 ino: 1181 drm-driver: amdgpu drm-client-id: 30 drm-pdev: :04:00.0 pasid: 32785 drm-total-cpu: 0 drm-shared-cpu: 0 drm-active-cpu: 0 drm-resident-cpu: 0 drm-purgeable-cpu: 0 drm-total-gtt: 20 MiB drm-shared-gtt: 0 drm-active-gtt: 0 drm-resident-gtt: 20 MiB drm-purgeable-gtt: 0 drm-total-vram: 155068 KiB drm-shared-vram: 13584 KiB drm-active-vram: 0 drm-resident-vram: 155068 KiB drm-purgeable-vram: 0 drm-total-gds: 0 drm-shared-gds: 0 drm-active-gds: 0 drm-resident-gds: 0 drm-purgeable-gds: 0 drm-total-gws: 0 drm-shared-gws: 0 drm-active-gws: 0 drm-resident-gws: 0 drm-purgeable-gws: 0 drm-total-oa: 0 drm-shared-oa: 0 drm-active-oa: 0 drm-resident-oa: 0 drm-purgeable-oa: 0 drm-total-doorbell: 0 drm-shared-doorbell: 0 drm-active-doorbell: 0 drm-resident-doorbell: 0 drm-purgeable-doorbell: 0 drm-memory-vram: 155068 KiB drm-memory-gtt: 20480 KiB drm-memory-cpu: 0 KiB amd-evicted-vram: 0 KiB amd-requested-vram: 155068 KiB amd-requested-gtt: 20480 KiB drm-engine-gfx: 19291217545 ns Cc: Christian König Cc: Yunxiang Li Cc: Alex Deucher Tvrtko Ursulin (2): drm/amdgpu: Stop reporting special chip memory pools as CPU memory in fdinfo drm/amdgpu: Expose special on chip memory pools in fdinfo Yunxiang Li (2): drm/amdgpu: make drm-memory-* report resident memory drm/amdgpu: stop tracking visible memory stats drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 23 - drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 24 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 11 -- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 11 +- 4 files changed, 25 insertions(+), 44 deletions(-) -- 2.46.0
[PATCH] drm/amdgpu: add get_gfx_shadow_info callback for gfx12
This callback gets the size and alignment requirements
for the gfx shadow buffer for preemption.
Cc: Alex Deucher
Cc: Christian Koenig
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 29 ++
1 file changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 02244bd2c418..0ac0222b178c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -860,6 +860,34 @@ static void gfx_v12_0_select_me_pipe_q(struct
amdgpu_device *adev,
soc24_grbm_select(adev, me, pipe, q, vm);
}
+/* all sizes are in bytes */
+#define MQD_SHADOW_BASE_SIZE 73728
+#define MQD_SHADOW_BASE_ALIGNMENT 256
+#define MQD_FWWORKAREA_SIZE 484
+#define MQD_FWWORKAREA_ALIGNMENT 256
+
+static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev,
+ struct amdgpu_gfx_shadow_info
*shadow_info)
+{
+ shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
+ shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
+ shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
+ shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
+}
+
+static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev,
+struct amdgpu_gfx_shadow_info
*shadow_info,
+bool skip_check)
+{
+ if (adev->gfx.cp_gfx_shadow || skip_check) {
+ gfx_v12_0_get_gfx_shadow_info_nocheck(adev, shadow_info);
+ return 0;
+ }
+
+ memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
+ return -EINVAL;
+}
+
static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v12_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v12_0_select_se_sh,
@@ -868,6 +896,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = {
.read_wave_vgprs = &gfx_v12_0_read_wave_vgprs,
.select_me_pipe_q = &gfx_v12_0_select_me_pipe_q,
.update_perfmon_mgcg = &gfx_v12_0_update_perf_clk,
+ .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info,
};
static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev)
--
2.46.2
Re: [PATCH 2/2] drm: remove driver date from struct drm_driver and all drivers
Jani Nikula writes:
Hello Jani,
> We stopped using the driver initialized date in commit 7fb8af6798e8
> ("drm: deprecate driver date") and (eventually) started returning "0"
> for drm_version ioctl instead.
>
> Finish the job, and remove the unused date member from struct
> drm_driver, its initialization from drivers, along with the common
> DRIVER_DATE macros.
>
> Signed-off-by: Jani Nikula
>
Reviewed-by: Javier Martinez Canillas
--
Best regards,
Javier Martinez Canillas
Core Platforms
Red Hat
RE: [PATCH] drm/amd/amdgpu: limit single process inside MES
[AMD Official Use Only - AMD Internal Distribution Only]
If the old FW doesn't support the isolation feature, it won't check that bit,
the setting there will be ignored , so it won't cause the problem .
Regards
Shaoyun.liu
-Original Message-
From: Alex Deucher
Sent: Thursday, October 24, 2024 9:21 AM
To: Liu, Shaoyun
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/amdgpu: limit single process inside MES
On Wed, Oct 23, 2024 at 8:48 PM Shaoyun Liu wrote:
>
> This is for MES to limit only one process for the user queues
>
> Signed-off-by: Shaoyun Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 24
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 19 +++
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 +++
> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 11 +++
> 5 files changed, 71 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index e96984c53e72..72e38d621a29 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1576,9 +1576,11 @@ static ssize_t amdgpu_gfx_set_enforce_isolation(struct
> device *dev,
> if (adev->enforce_isolation[i] && !partition_values[i]) {
> /* Going from enabled to disabled */
> amdgpu_vmid_free_reserved(adev,
> AMDGPU_GFXHUB(i));
> + amdgpu_mes_set_enforce_isolation(adev, i,
> + false);
> } else if (!adev->enforce_isolation[i] &&
> partition_values[i]) {
> /* Going from disabled to enabled */
> amdgpu_vmid_alloc_reserved(adev,
> AMDGPU_GFXHUB(i));
> + amdgpu_mes_set_enforce_isolation(adev, i,
> + true);
> }
> adev->enforce_isolation[i] = partition_values[i];
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index bf584e9bcce4..dfc7d320fcbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -1674,6 +1674,30 @@ bool amdgpu_mes_suspend_resume_all_supported(struct
> amdgpu_device *adev)
> return is_supported;
> }
>
> +/* Fix me -- node_id is used to identify the correct MES instances in
> +the future */ int amdgpu_mes_set_enforce_isolation(struct
> +amdgpu_device *adev, uint32_t node_id, bool enable) {
> + struct mes_misc_op_input op_input = {0};
> + int r;
> +
> + op_input.op = MES_MISC_OP_CHANGE_CONFIG;
> + op_input.change_config.option.limit_single_process = enable ?
> + 1 : 0;
> +
> + if (!adev->mes.funcs->misc_op) {
> + dev_err(adev->dev,"mes change config is not supported!\n");
> + r = -EINVAL;
> + goto error;
> + }
> +
> + r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> + if (r)
> + dev_err(adev->dev, "failed to change_config.\n");
> +
> +error:
> + return r;
> +
> +}
> +
> #if defined(CONFIG_DEBUG_FS)
>
> static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void
> *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 79f13d7e5e16..91bff6443c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -311,6 +311,7 @@ enum mes_misc_opcode {
> MES_MISC_OP_WRM_REG_WAIT,
> MES_MISC_OP_WRM_REG_WR_WAIT,
> MES_MISC_OP_SET_SHADER_DEBUGGER,
> + MES_MISC_OP_CHANGE_CONFIG,
> };
>
> struct mes_misc_op_input {
> @@ -349,6 +350,21 @@ struct mes_misc_op_input {
> uint32_t tcp_watch_cntl[4];
> uint32_t trap_en;
> } set_shader_debugger;
> +
> + struct {
> + union {
> + struct {
> + uint32_t limit_single_process : 1;
> + uint32_t enable_hws_logging_buffer :
> 1;
> + uint32_t reserved : 30;
> + };
> + uint32_t all;
> + } option;
> + struct {
> + uint32_t tdr_level;
> + uint32_t tdr_delay;
> + } tdr_config;
> + } change_config;
> };
> };
>
> @@ -519,4 +535,7 @@ static inline void amdgpu_mes_unlock(struct
> amdgpu_mes *mes) }
>
> bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device
> *adev);
> +
> +int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev,
> +uint32_t node_id, bool enable);
> +
> #endif /* __AMDGPU_MES_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
[PATCH V3 1/5] drm/amdgpu: Add sysfs interface for gc reset mask
Add two sysfs interfaces for gfx and compute:
gfx_reset_mask
compute_reset_mask
These interfaces are read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.
V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
and print the strings in the order they are applied (Christian)
check amdgpu_gpu_recovery before creating sysfs file itself,
and initialize supported_reset_types in IP version files (Lijo)
Signed-off-by: Jesse Zhang
Suggested-by:Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 8 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 66 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 4 ++
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c| 12
7 files changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 48c9b9b06905..aea1031d7b84 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -300,6 +300,12 @@ extern int amdgpu_wbrf;
#define AMDGPU_RESET_VCE (1 << 13)
#define AMDGPU_RESET_VCE1 (1 << 14)
+/* reset mask */
+#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset,
mode1/mode2/BACO/etc. */
+#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */
+#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
+#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
+
/* max cursor sizes (in pixels) */
#define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128
@@ -1466,6 +1472,8 @@ struct dma_fence *amdgpu_device_get_gang(struct
amdgpu_device *adev);
struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
struct dma_fence *gang);
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
+ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
+ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ef715b2bbcdb..cd1e3f018893 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -6684,3 +6684,40 @@ uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device
*adev,
}
return ret;
}
+
+ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring)
+{
+ ssize_t size = 0;
+
+ if (!ring)
+ return size;
+
+ if (amdgpu_device_should_recover_gpu(ring->adev))
+ size |= AMDGPU_RESET_TYPE_FULL;
+
+ if (unlikely(!ring->adev->debug_disable_soft_recovery) &&
+ !amdgpu_sriov_vf(ring->adev) && ring->funcs->soft_recovery)
+ size |= AMDGPU_RESET_TYPE_SOFT_RESET;
+
+ return size;
+}
+
+ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset)
+{
+ ssize_t size = 0;
+
+ if (supported_reset & AMDGPU_RESET_TYPE_SOFT_RESET)
+ size += sysfs_emit_at(buf, size, "soft ");
+
+ if (supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE)
+ size += sysfs_emit_at(buf, size, "queue ");
+
+ if (supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)
+ size += sysfs_emit_at(buf, size, "pipe ");
+
+ if (supported_reset & AMDGPU_RESET_TYPE_FULL)
+ size += sysfs_emit_at(buf, size, "full ");
+
+ size += sysfs_emit_at(buf, size, "\n");
+ return size;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index e96984c53e72..6de1f3bf6863 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -1588,6 +1588,32 @@ static ssize_t amdgpu_gfx_set_enforce_isolation(struct
device *dev,
return count;
}
+static ssize_t amdgpu_gfx_get_gfx_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->gfx.gfx_supported_reset);
+}
+
+static ssize_t amdgpu_gfx_get_compute_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+
[PATCH 2/2] drm/amdgpu: Add gpu_addr support to seq64 allocation
Add gpu address support to seq64 alloc function.
v1:(Christian)
- Add the user of this new interface change to the same
patch.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c | 10 --
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 8
drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 1 +
4 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
index 12cad4424fc0..2f01a209ec3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c
@@ -166,7 +166,8 @@ void amdgpu_seq64_unmap(struct amdgpu_device *adev, struct
amdgpu_fpriv *fpriv)
* Returns:
* 0 on success or a negative error code on failure
*/
-int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 **cpu_addr)
+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va,
+ u64 *gpu_addr, u64 **cpu_addr)
{
unsigned long bit_pos;
@@ -175,7 +176,12 @@ int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64
*va, u64 **cpu_addr)
return -ENOSPC;
__set_bit(bit_pos, adev->seq64.used);
+
*va = bit_pos * sizeof(u64) + amdgpu_seq64_get_va_base(adev);
+
+ if (gpu_addr)
+ *gpu_addr = bit_pos * sizeof(u64) + adev->seq64.gpu_addr;
+
*cpu_addr = bit_pos + adev->seq64.cpu_base_addr;
return 0;
@@ -236,7 +242,7 @@ int amdgpu_seq64_init(struct amdgpu_device *adev)
*/
r = amdgpu_bo_create_kernel(adev, AMDGPU_VA_RESERVED_SEQ64_SIZE,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
- &adev->seq64.sbo, NULL,
+ &adev->seq64.sbo, &adev->seq64.gpu_addr,
(void **)&adev->seq64.cpu_base_addr);
if (r) {
dev_warn(adev->dev, "(%d) create seq64 failed\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
index 4203b2ab318d..26a249aaaee1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.h
@@ -32,13 +32,14 @@
struct amdgpu_seq64 {
struct amdgpu_bo *sbo;
u32 num_sem;
+ u64 gpu_addr;
u64 *cpu_base_addr;
DECLARE_BITMAP(used, AMDGPU_MAX_SEQ64_SLOTS);
};
void amdgpu_seq64_fini(struct amdgpu_device *adev);
int amdgpu_seq64_init(struct amdgpu_device *adev);
-int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *gpu_addr, u64
**cpu_addr);
+int amdgpu_seq64_alloc(struct amdgpu_device *adev, u64 *va, u64 *gpu_addr, u64
**cpu_addr);
void amdgpu_seq64_free(struct amdgpu_device *adev, u64 gpu_addr);
int amdgpu_seq64_map(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo_va **bo_va);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
index bec53776fe5f..8cf169e7e893 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
@@ -82,7 +82,7 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device
*adev,
}
/* Acquire seq64 memory */
- r = amdgpu_seq64_alloc(adev, &fence_drv->gpu_addr,
+ r = amdgpu_seq64_alloc(adev, &fence_drv->va, &fence_drv->gpu_addr,
&fence_drv->cpu_addr);
if (r) {
kfree(fence_drv);
@@ -113,7 +113,7 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device
*adev,
return 0;
free_seq64:
- amdgpu_seq64_free(adev, fence_drv->gpu_addr);
+ amdgpu_seq64_free(adev, fence_drv->va);
free_fence_drv:
kfree(fence_drv);
@@ -183,7 +183,7 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref)
xa_unlock_irqrestore(xa, flags);
/* Free seq64 memory */
- amdgpu_seq64_free(adev, fence_drv->gpu_addr);
+ amdgpu_seq64_free(adev, fence_drv->va);
kfree(fence_drv);
}
@@ -751,7 +751,7 @@ int amdgpu_userq_wait_ioctl(struct drm_device *dev, void
*data,
}
/* Store drm syncobj's gpu va address and value */
- fence_info[cnt].va = fence_drv->gpu_addr;
+ fence_info[cnt].va = fence_drv->va;
fence_info[cnt].value = fences[i]->seqno;
dma_fence_put(fences[i]);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
index 89c82ba38b50..f1a90840ac1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
@@ -44,6 +44,7 @@ struct amdgpu_userq_fence {
struct amdgpu_userq_fence_driver {
struct kref refcount;
+ u64 va;
u64 gpu_addr;
Re: [PATCH] drm/amd : Update MES API header file for v11 & v12
On Mon, Oct 21, 2024 at 10:11 PM Shaoyun Liu wrote:
>
> New features require the new fields defines
>
> Signed-off-by: Shaoyun Liu
> ---
> drivers/gpu/drm/amd/include/mes_v11_api_def.h | 32 -
> drivers/gpu/drm/amd/include/mes_v12_api_def.h | 34 ++-
> 2 files changed, 64 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> index 21ceafce1f9b..663f368eb4f0 100644
> --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> @@ -230,13 +230,23 @@ union MESAPI_SET_HW_RESOURCES {
> uint32_t disable_add_queue_wptr_mc_addr : 1;
> uint32_t enable_mes_event_int_logging : 1;
> uint32_t enable_reg_active_poll : 1;
> - uint32_t reserved : 21;
> + uint32_t
> use_disable_queue_in_legacy_uq_preemption : 1;
> + uint32_t send_write_data : 1;
> + uint32_t os_tdr_timeout_override : 1;
> + uint32_t use_rs64mem_for_proc_gang_ctx : 1;
> + uint32_t use_add_queue_unmap_flag_addr : 1;
> + uint32_t enable_mes_sch_stb_log : 1;
> + uint32_t limit_single_process : 1;
> + uint32_t is_strix_tmz_wa_enabled :1;
> + uint32_t reserved : 13;
> };
> uint32_tuint32_t_all;
> };
> uint32_toversubscription_timer;
> uint64_tdoorbell_info;
> uint64_tevent_intr_history_gpu_mc_ptr;
> + uint64_ttimestamp;
> + uint32_tos_tdr_timeout_in_sec;
Will this change break backwards compatibility? It changes the size
of the packet.
Alex
> };
>
> uint32_tmax_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
> @@ -563,6 +573,11 @@ enum MESAPI_MISC_OPCODE {
> MESAPI_MISC__READ_REG,
> MESAPI_MISC__WAIT_REG_MEM,
> MESAPI_MISC__SET_SHADER_DEBUGGER,
> + MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
> + MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
> + MESAPI_MISC__CHANGE_CONFIG,
> + MESAPI_MISC__LAUNCH_CLEANER_SHADER,
> +
> MESAPI_MISC__MAX,
> };
>
> @@ -617,6 +632,20 @@ struct SET_SHADER_DEBUGGER {
> uint32_t trap_en;
> };
>
> +struct CHANGE_CONFIG
> +{
> +union
> +{
> +struct
> +{
> +uint32_t limit_single_process : 1;
> +uint32_t reserved : 31;
> +}bits;
> +uint32_t all;
> +}option;
> +};
> +
> +
> union MESAPI__MISC {
> struct {
> union MES_API_HEADERheader;
> @@ -631,6 +660,7 @@ union MESAPI__MISC {
> struct WAIT_REG_MEM wait_reg_mem;
> struct SET_SHADER_DEBUGGER
> set_shader_debugger;
> enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
> + struct CHANGE_CONFIG change_config;
>
> uint32_tdata[MISC_DATA_MAX_SIZE_IN_DWORDS];
> };
> diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> index 101e2fe962c6..62df832810ca 100644
> --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> @@ -643,6 +643,10 @@ enum MESAPI_MISC_OPCODE {
> MESAPI_MISC__SET_SHADER_DEBUGGER,
> MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
> MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
> + MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
> + MESAPI_MISC__CHANGE_CONFIG,
> + MESAPI_MISC__LAUNCH_CLEANER_SHADER,
> + MESAPI_MISC__SETUP_MES_DBGEXT,
>
> MESAPI_MISC__MAX,
> };
> @@ -713,6 +717,34 @@ struct SET_GANG_SUBMIT {
> uint32_t slave_gang_context_array_index;
> };
>
> +enum MESAPI_MISC__CHANGE_CONFIG_OPTION
> +{
> + MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
> + MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
> + MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG= 2,
> +
> + MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
> +};
> +
> +struct CHANGE_CONFIG
> +{
> + enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
> + union {
> + struct {
> + uint32_t limit_single_process : 1;
> + uint32_t enable_hws_logging_buffer : 1;
> + uint32_t reserved : 30;
> + }bits;
> + uint32_t all;
> + } option;
> +
> + struct {
> + uint32_t tdr_level;
> + uint32_t tdr
Re: [PATCH] drm/amd : Update MES API header file for v11 & v12
On Thu, Oct 24, 2024 at 9:31 AM Alex Deucher wrote:
>
> On Mon, Oct 21, 2024 at 10:11 PM Shaoyun Liu wrote:
> >
> > New features require the new fields defines
> >
> > Signed-off-by: Shaoyun Liu
> > ---
> > drivers/gpu/drm/amd/include/mes_v11_api_def.h | 32 -
> > drivers/gpu/drm/amd/include/mes_v12_api_def.h | 34 ++-
> > 2 files changed, 64 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> > b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> > index 21ceafce1f9b..663f368eb4f0 100644
> > --- a/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> > +++ b/drivers/gpu/drm/amd/include/mes_v11_api_def.h
> > @@ -230,13 +230,23 @@ union MESAPI_SET_HW_RESOURCES {
> > uint32_t disable_add_queue_wptr_mc_addr : 1;
> > uint32_t enable_mes_event_int_logging : 1;
> > uint32_t enable_reg_active_poll : 1;
> > - uint32_t reserved : 21;
> > + uint32_t
> > use_disable_queue_in_legacy_uq_preemption : 1;
> > + uint32_t send_write_data : 1;
> > + uint32_t os_tdr_timeout_override : 1;
> > + uint32_t use_rs64mem_for_proc_gang_ctx : 1;
> > + uint32_t use_add_queue_unmap_flag_addr : 1;
> > + uint32_t enable_mes_sch_stb_log : 1;
> > + uint32_t limit_single_process : 1;
> > + uint32_t is_strix_tmz_wa_enabled :1;
> > + uint32_t reserved : 13;
> > };
> > uint32_tuint32_t_all;
> > };
> > uint32_toversubscription_timer;
> > uint64_tdoorbell_info;
> > uint64_tevent_intr_history_gpu_mc_ptr;
> > + uint64_ttimestamp;
> > + uint32_tos_tdr_timeout_in_sec;
>
> Will this change break backwards compatibility? It changes the size
> of the packet.
Nevermind, the packets are always of size API_FRAME_SIZE_IN_DWORDS.
Reviewed-by: Alex Deucher
Alex
>
> Alex
>
> > };
> >
> > uint32_tmax_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
> > @@ -563,6 +573,11 @@ enum MESAPI_MISC_OPCODE {
> > MESAPI_MISC__READ_REG,
> > MESAPI_MISC__WAIT_REG_MEM,
> > MESAPI_MISC__SET_SHADER_DEBUGGER,
> > + MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
> > + MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
> > + MESAPI_MISC__CHANGE_CONFIG,
> > + MESAPI_MISC__LAUNCH_CLEANER_SHADER,
> > +
> > MESAPI_MISC__MAX,
> > };
> >
> > @@ -617,6 +632,20 @@ struct SET_SHADER_DEBUGGER {
> > uint32_t trap_en;
> > };
> >
> > +struct CHANGE_CONFIG
> > +{
> > +union
> > +{
> > +struct
> > +{
> > +uint32_t limit_single_process : 1;
> > +uint32_t reserved : 31;
> > +}bits;
> > +uint32_t all;
> > +}option;
> > +};
> > +
> > +
> > union MESAPI__MISC {
> > struct {
> > union MES_API_HEADERheader;
> > @@ -631,6 +660,7 @@ union MESAPI__MISC {
> > struct WAIT_REG_MEM wait_reg_mem;
> > struct SET_SHADER_DEBUGGER
> > set_shader_debugger;
> > enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
> > + struct CHANGE_CONFIG change_config;
> >
> > uint32_tdata[MISC_DATA_MAX_SIZE_IN_DWORDS];
> > };
> > diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> > b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> > index 101e2fe962c6..62df832810ca 100644
> > --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> > +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> > @@ -643,6 +643,10 @@ enum MESAPI_MISC_OPCODE {
> > MESAPI_MISC__SET_SHADER_DEBUGGER,
> > MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
> > MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
> > + MESAPI_MISC__QUERY_HUNG_ENGINE_ID,
> > + MESAPI_MISC__CHANGE_CONFIG,
> > + MESAPI_MISC__LAUNCH_CLEANER_SHADER,
> > + MESAPI_MISC__SETUP_MES_DBGEXT,
> >
> > MESAPI_MISC__MAX,
> > };
> > @@ -713,6 +717,34 @@ struct SET_GANG_SUBMIT {
> > uint32_t slave_gang_context_array_index;
> > };
> >
> > +enum MESAPI_MISC__CHANGE_CONFIG_OPTION
> > +{
> > + MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
> > + MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
> > + MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG= 2,
> > +
> > + MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
> > +};
> > +
> > +struct CHANGE_CONFIG
> > +{
> > + enum MESAPI_MISC__CHANGE_CONFIG_OPTION o
Re: [PATCH] drm/amd/amdgpu: limit single process inside MES
On Wed, Oct 23, 2024 at 8:48 PM Shaoyun Liu wrote:
>
> This is for MES to limit only one process for the user queues
>
> Signed-off-by: Shaoyun Liu
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 2 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 24
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 19 +++
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 +++
> drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 11 +++
> 5 files changed, 71 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index e96984c53e72..72e38d621a29 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1576,9 +1576,11 @@ static ssize_t amdgpu_gfx_set_enforce_isolation(struct
> device *dev,
> if (adev->enforce_isolation[i] && !partition_values[i]) {
> /* Going from enabled to disabled */
> amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(i));
> + amdgpu_mes_set_enforce_isolation(adev, i, false);
> } else if (!adev->enforce_isolation[i] &&
> partition_values[i]) {
> /* Going from disabled to enabled */
> amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i));
> + amdgpu_mes_set_enforce_isolation(adev, i, true);
> }
> adev->enforce_isolation[i] = partition_values[i];
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index bf584e9bcce4..dfc7d320fcbc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -1674,6 +1674,30 @@ bool amdgpu_mes_suspend_resume_all_supported(struct
> amdgpu_device *adev)
> return is_supported;
> }
>
> +/* Fix me -- node_id is used to identify the correct MES instances in the
> future */
> +int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t
> node_id, bool enable)
> +{
> + struct mes_misc_op_input op_input = {0};
> + int r;
> +
> + op_input.op = MES_MISC_OP_CHANGE_CONFIG;
> + op_input.change_config.option.limit_single_process = enable ? 1 : 0;
> +
> + if (!adev->mes.funcs->misc_op) {
> + dev_err(adev->dev,"mes change config is not supported!\n");
> + r = -EINVAL;
> + goto error;
> + }
> +
> + r = adev->mes.funcs->misc_op(&adev->mes, &op_input);
> + if (r)
> + dev_err(adev->dev, "failed to change_config.\n");
> +
> +error:
> + return r;
> +
> +}
> +
> #if defined(CONFIG_DEBUG_FS)
>
> static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void
> *unused)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 79f13d7e5e16..91bff6443c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -311,6 +311,7 @@ enum mes_misc_opcode {
> MES_MISC_OP_WRM_REG_WAIT,
> MES_MISC_OP_WRM_REG_WR_WAIT,
> MES_MISC_OP_SET_SHADER_DEBUGGER,
> + MES_MISC_OP_CHANGE_CONFIG,
> };
>
> struct mes_misc_op_input {
> @@ -349,6 +350,21 @@ struct mes_misc_op_input {
> uint32_t tcp_watch_cntl[4];
> uint32_t trap_en;
> } set_shader_debugger;
> +
> + struct {
> + union {
> + struct {
> + uint32_t limit_single_process : 1;
> + uint32_t enable_hws_logging_buffer :
> 1;
> + uint32_t reserved : 30;
> + };
> + uint32_t all;
> + } option;
> + struct {
> + uint32_t tdr_level;
> + uint32_t tdr_delay;
> + } tdr_config;
> + } change_config;
> };
> };
>
> @@ -519,4 +535,7 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes
> *mes)
> }
>
> bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
> +
> +int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, uint32_t
> node_id, bool enable);
> +
> #endif /* __AMDGPU_MES_H__ */
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 57db0c006c8f..c621ba805433 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -644,6 +644,18 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
>
> sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl));
> misc_pkt.set_shader_debugger.trap_en =
> input->set_shader_debugger.trap_
Re: [PATCH next] drm/amdgpu: Fix amdgpu_ip_block_hw_fini()
On 10/24/2024 03:17, Dan Carpenter wrote:
This NULL check is reversed so the function doesn't work.
Fixes: dad01f93f432 ("drm/amdgpu: validate hw_fini before function call")
Signed-off-by: Dan Carpenter
Thanks!
Reviewed-by: Mario Limonciello
Also applied to amd-staging-drm-next.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 91c1f2188498..f12fab13386a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3309,7 +3309,7 @@ static void amdgpu_ip_block_hw_fini(struct
amdgpu_ip_block *ip_block)
{
int r;
- if (ip_block->version->funcs->hw_fini) {
+ if (!ip_block->version->funcs->hw_fini) {
DRM_ERROR("hw_fini of IP block <%s> not defined\n",
ip_block->version->funcs->name);
} else {
Re: [PATCH] drm/amdgpu/smu13: fix profile reporting
Ping?
On Wed, Oct 23, 2024 at 9:23 AM Alex Deucher wrote:
>
> The following 3 commits landed in parallel:
> commit d7d2688bf4ea ("drm/amd/pm: update workload mask after the setting")
> commit 7a1613e47e65 ("drm/amdgpu/smu13: always apply the powersave
> optimization")
> commit 7c210ca5a2d7 ("drm/amdgpu: handle default profile on on devices
> without fullscreen 3D")
> While everything is set correctly, this caused the profile to be
> reported incorrectly because both the powersave and fullscreen3d bits
> were set in the mask and when the driver prints the profile, it looks
> for the first bit set.
>
> Fixes: d7d2688bf4ea ("drm/amd/pm: update workload mask after the setting")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index cb923e33fd6f..d53e162dcd8d 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2485,7 +2485,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> DpmActivityMonitorCoeffInt_t *activity_monitor =
> &(activity_monitor_external.DpmActivityMonitorCoeffInt);
> int workload_type, ret = 0;
> - u32 workload_mask;
> + u32 workload_mask, selected_workload_mask;
>
> smu->power_profile_mode = input[size];
>
> @@ -2552,7 +2552,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
> if (workload_type < 0)
> return -EINVAL;
>
> - workload_mask = 1 << workload_type;
> + selected_workload_mask = workload_mask = 1 << workload_type;
>
> /* Add optimizations for SMU13.0.0/10. Reuse the power saving
> profile */
> if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0,
> 0) &&
> @@ -2572,7 +2572,7 @@ static int smu_v13_0_0_set_power_profile_mode(struct
> smu_context *smu,
>workload_mask,
>NULL);
> if (!ret)
> - smu->workload_mask = workload_mask;
> + smu->workload_mask = selected_workload_mask;
>
> return ret;
> }
> --
> 2.46.2
>
RE: [PATCH v3 2/2] drm/amdgpu: clean up the suspend_complete
[AMD Official Use Only - AMD Internal Distribution Only]
> From: Lazar, Lijo
> Sent: Thursday, October 24, 2024 4:40 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH v3 2/2] drm/amdgpu: clean up the suspend_complete
>
>
>
> On 10/24/2024 1:51 PM, Prike Liang wrote:
> > To check the status of S3 suspend completion, use the PM core
> > pm_suspend_global_flags bit(1) to detect S3 abort events. Therefore,
> > clean up the AMDGPU driver's private flag suspend_complete.
> >
> > Signed-off-by: Prike Liang
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
> > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
> > drivers/gpu/drm/amd/amdgpu/soc21.c | 16 ++--
> > 5 files changed, 10 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 48c9b9b06905..9b35763ae0a7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -,8 +,6 @@ struct amdgpu_device {
> > boolin_s3;
> > boolin_s4;
> > boolin_s0ix;
> > - /* indicate amdgpu suspension status */
> > - boolsuspend_complete;
> >
> > enum pp_mp1_state mp1_state;
> > struct amdgpu_doorbell_index doorbell_index; diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index 680e44fdee6e..78972151b970 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -2501,7 +2501,6 @@ static int amdgpu_pmops_suspend(struct device *dev)
> > struct drm_device *drm_dev = dev_get_drvdata(dev);
> > struct amdgpu_device *adev = drm_to_adev(drm_dev);
> >
> > - adev->suspend_complete = false;
> > if (amdgpu_acpi_is_s0ix_active(adev))
> > adev->in_s0ix = true;
> > else if (amdgpu_acpi_is_s3_active(adev)) @@ -2516,7 +2515,6 @@
> > static int amdgpu_pmops_suspend_noirq(struct device *dev)
> > struct drm_device *drm_dev = dev_get_drvdata(dev);
> > struct amdgpu_device *adev = drm_to_adev(drm_dev);
> >
> > - adev->suspend_complete = true;
> > if (amdgpu_acpi_should_gpu_reset(adev))
> > return amdgpu_asic_reset(adev);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index b4c4b9916289..6ffcee3008ba 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -3276,8 +3276,8 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device
> *adev)
> > * confirmed that the APU gfx10/gfx11 needn't such update.
> > */
> > if (adev->flags & AMD_IS_APU &&
> > - adev->in_s3 && !adev->suspend_complete) {
> > - DRM_INFO(" Will skip the CSB packet resubmit\n");
> > + adev->in_s3 && !pm_resume_via_firmware()) {
> > + DRM_INFO("Will skip the CSB packet resubmit\n");
> > return 0;
> > }
> > r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 12ff6cf568dc..d9d11131a744 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -584,13 +584,10 @@ static bool soc15_need_reset_on_resume(struct
> amdgpu_device *adev)
> > *performing pm core test.
> > */
> > if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> > - !pm_resume_via_firmware()) {
> > - adev->suspend_complete = false;
> > + !pm_resume_via_firmware())
> > return true;
> > - } else {
> > - adev->suspend_complete = true;
> > + else
> > return false;
> > - }
> > }
> >
> > static int soc15_asic_reset(struct amdgpu_device *adev) diff --git
> > a/drivers/gpu/drm/amd/amdgpu/soc21.c
> > b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > index c4b950e75133..8d5844d7a10f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> > @@ -897,22 +897,18 @@ static int soc21_common_suspend(struct
> > amdgpu_ip_block *ip_block)
> >
> > static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) {
> > - u32 sol_reg1, sol_reg2;
> > + u32 sol_reg;
> >
> > /* Will reset for the following suspend abort cases.
> > * 1) Only reset dGPU side.
> > * 2) S3 suspend got aborted and TOS is active.
> > */
> > - if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
> > - !adev->suspend_complete) {
> > - sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
> > - msleep(100);
> > - sol_reg2 = RREG32_SOC15(MP
Re: [PATCH v3 2/2] drm/amdgpu: clean up the suspend_complete
On 10/25/2024 8:54 AM, Liang, Prike wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>> From: Lazar, Lijo
>> Sent: Thursday, October 24, 2024 4:40 PM
>> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subject: Re: [PATCH v3 2/2] drm/amdgpu: clean up the suspend_complete
>>
>>
>>
>> On 10/24/2024 1:51 PM, Prike Liang wrote:
>>> To check the status of S3 suspend completion, use the PM core
>>> pm_suspend_global_flags bit(1) to detect S3 abort events. Therefore,
>>> clean up the AMDGPU driver's private flag suspend_complete.
>>>
>>> Signed-off-by: Prike Liang
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
>>> drivers/gpu/drm/amd/amdgpu/soc21.c | 16 ++--
>>> 5 files changed, 10 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 48c9b9b06905..9b35763ae0a7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -,8 +,6 @@ struct amdgpu_device {
>>> boolin_s3;
>>> boolin_s4;
>>> boolin_s0ix;
>>> - /* indicate amdgpu suspension status */
>>> - boolsuspend_complete;
>>>
>>> enum pp_mp1_state mp1_state;
>>> struct amdgpu_doorbell_index doorbell_index; diff --git
>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> index 680e44fdee6e..78972151b970 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>>> @@ -2501,7 +2501,6 @@ static int amdgpu_pmops_suspend(struct device *dev)
>>> struct drm_device *drm_dev = dev_get_drvdata(dev);
>>> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>>>
>>> - adev->suspend_complete = false;
>>> if (amdgpu_acpi_is_s0ix_active(adev))
>>> adev->in_s0ix = true;
>>> else if (amdgpu_acpi_is_s3_active(adev)) @@ -2516,7 +2515,6 @@
>>> static int amdgpu_pmops_suspend_noirq(struct device *dev)
>>> struct drm_device *drm_dev = dev_get_drvdata(dev);
>>> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>>>
>>> - adev->suspend_complete = true;
>>> if (amdgpu_acpi_should_gpu_reset(adev))
>>> return amdgpu_asic_reset(adev);
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index b4c4b9916289..6ffcee3008ba 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -3276,8 +3276,8 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device
>> *adev)
>>> * confirmed that the APU gfx10/gfx11 needn't such update.
>>> */
>>> if (adev->flags & AMD_IS_APU &&
>>> - adev->in_s3 && !adev->suspend_complete) {
>>> - DRM_INFO(" Will skip the CSB packet resubmit\n");
>>> + adev->in_s3 && !pm_resume_via_firmware()) {
>>> + DRM_INFO("Will skip the CSB packet resubmit\n");
>>> return 0;
>>> }
>>> r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> index 12ff6cf568dc..d9d11131a744 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>>> @@ -584,13 +584,10 @@ static bool soc15_need_reset_on_resume(struct
>> amdgpu_device *adev)
>>> *performing pm core test.
>>> */
>>> if (adev->flags & AMD_IS_APU && adev->in_s3 &&
>>> - !pm_resume_via_firmware()) {
>>> - adev->suspend_complete = false;
>>> + !pm_resume_via_firmware())
>>> return true;
>>> - } else {
>>> - adev->suspend_complete = true;
>>> + else
>>> return false;
>>> - }
>>> }
>>>
>>> static int soc15_asic_reset(struct amdgpu_device *adev) diff --git
>>> a/drivers/gpu/drm/amd/amdgpu/soc21.c
>>> b/drivers/gpu/drm/amd/amdgpu/soc21.c
>>> index c4b950e75133..8d5844d7a10f 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
>>> @@ -897,22 +897,18 @@ static int soc21_common_suspend(struct
>>> amdgpu_ip_block *ip_block)
>>>
>>> static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) {
>>> - u32 sol_reg1, sol_reg2;
>>> + u32 sol_reg;
>>>
>>> /* Will reset for the following suspend abort cases.
>>> * 1) Only reset dGPU side.
>>> * 2) S3 suspend got aborted and TOS is active.
>>> */
>>> - if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
>>> - !adev->suspend_complete) {
>>> - sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
>>> -
[PATCH 05/29] drm/amd/pm: add inst to dpm_set_powergating_by_smu
From: Boyuan Zhang
Add an instance parameter to amdgpu_dpm_set_powergating_by_smu() function,
and use the instance to call set_powergating_by_smu().
v2: remove duplicated functions.
remove for-loop in amdgpu_dpm_set_powergating_by_smu(), and temporarily
move it to amdgpu_dpm_enable_vcn(), in order to keep the exact same logic
as before, until further separation in next patch.
Signed-off-by: Boyuan Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c| 14 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c| 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c| 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c| 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c| 4 +-
drivers/gpu/drm/amd/pm/amdgpu_dpm.c| 51 +-
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h| 3 +-
16 files changed, 73 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index ec5e0dcf8613..769200cda626 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -140,7 +140,7 @@ static int acp_poweroff(struct generic_pm_domain *genpd)
* 2. power off the acp tiles
* 3. check and enter ulv state
*/
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true, 0);
return 0;
}
@@ -157,7 +157,7 @@ static int acp_poweron(struct generic_pm_domain *genpd)
* 2. turn on acp clock
* 3. power on acp tiles
*/
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false,
0);
return 0;
}
@@ -236,7 +236,7 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block)
ip_block->version->major, ip_block->version->minor);
/* -ENODEV means board uses AZ rather than ACP */
if (r == -ENODEV) {
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true, 0);
return 0;
} else if (r) {
return r;
@@ -508,7 +508,7 @@ static int acp_hw_fini(struct amdgpu_ip_block *ip_block)
/* return early if no ACP */
if (!adev->acp.acp_genpd) {
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false, 0);
return 0;
}
@@ -565,7 +565,7 @@ static int acp_suspend(struct amdgpu_ip_block *ip_block)
/* power up on suspend */
if (!adev->acp.acp_cell)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
false, 0);
return 0;
}
@@ -575,7 +575,7 @@ static int acp_resume(struct amdgpu_ip_block *ip_block)
/* power down again on resume */
if (!adev->acp.acp_cell)
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP,
true, 0);
return 0;
}
@@ -596,7 +596,7 @@ static int acp_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool enable = (state == AMD_PG_STATE_GATE);
- amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable,
0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6c0ff1c2ae4c..2924fa15b74b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3469,7 +3469,7 @@ static void amdgpu_device_delay_enable_gfx_off(struct
work_struct *work)
WARN_ON_ONCE(adev->gfx.gfx_off_state);
WARN_ON_ONCE(adev->gfx.gfx_off_req_count);
- if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
true))
+ if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
true, 0))
adev->gfx.gfx_off_state = true;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index e96984c53e72..0c3249
[PATCH 06/29] drm/amdgpu: add inst to amdgpu_dpm_enable_vcn
From: Boyuan Zhang
Add an instance parameter to amdgpu_dpm_enable_vcn() function, and change
all calls from vcn ip functions to add instance argument. vcn generations
with only one instance (v1.0, v2.0) always use 0 as instance number. vcn
generations with multiple instances (v2.5, v3.0, v4.0, v4.0.3, v4.0.5,
v5.0.0) use the actual instance number.
v2: remove for-loop in amdgpu_dpm_enable_vcn(), and temporarily move it
to vcn ip with multiple instances, in order to keep the exact same logic
as before, until further separation in next patch.
v3: fix missing prefix
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 12
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 12
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 12
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 12 +---
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 +-
10 files changed, 59 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 511d76e188f2..7ad2ab3affe4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -303,7 +303,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block
*ip_block)
idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
if (idle_work_unexecuted) {
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
}
r = vcn_v1_0_hw_fini(ip_block);
@@ -1856,7 +1856,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct
*work)
if (fences == 0) {
amdgpu_gfx_off_ctrl(adev, true);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
else
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
@@ -1886,7 +1886,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring
*ring, bool set_clocks)
if (set_clocks) {
amdgpu_gfx_off_ctrl(adev, false);
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 0);
else
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 697822abf3fc..f34cab96d0b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -978,7 +978,7 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)
int i, j, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 0);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram);
@@ -1235,7 +1235,7 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
power_off:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 0);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 0afbcf72cd51..beab2c24042d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1012,8 +1012,10 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
uint32_t rb_bufsz, tmp;
int i, j, k, r;
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, true);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, true, i);
+ }
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
@@ -1485,8 +1487,10 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
}
- if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_vcn(adev, false);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->pm.dpm_enabled)
+ amdgpu_dpm_enable_vcn(adev, false, i);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index b28aad3
[PATCH 07/29] drm/amdgpu: pass ip_block in set_powergating_state
From: Boyuan Zhang Pass ip_block instead of adev in set_powergating_state callback function. Modify set_powergating_state ip functions for all correspoding ip blocks. v2: fix a ip block index error. v3: remove type casting Signed-off-by: Boyuan Zhang Suggested-by: Christian König Acked-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c| 4 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +- drivers/gpu/drm/amd/amdgpu/cz_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 8 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c| 8 drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c| 8 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c| 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c| 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 drivers/gpu/drm/amd/amdgpu/navi10_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c| 2 +- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c| 2 +- drivers/gpu/drm/amd/amdgpu/soc21.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c| 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 13 +++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/vega20_ih.c| 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amd
[PATCH 24/29] drm/amdgpu: suspend for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_suspend(), and perform
suspend ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
v2: add vcn instance to amdgpu_vcn_save_vcpu_bo()
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 13
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 38 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 6 ++--
11 files changed, 59 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
index 24dae7cdbe95..4fc0ee01d56b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
@@ -42,13 +42,14 @@ static int amdgpu_reset_xgmi_reset_on_init_suspend(struct
amdgpu_device *adev)
/* XXX handle errors */
amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
adev->ip_blocks[i].status.hw = false;
- }
- /* VCN FW shared region is in frambuffer, there are some flags
-* initialized in that region during sw_init. Make sure the region is
-* backed up.
-*/
- amdgpu_vcn_save_vcpu_bo(adev);
+ /* VCN FW shared region is in frambuffer, there are some flags
+ * initialized in that region during sw_init. Make sure the
region is
+ * backed up.
+ */
+ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_VCN)
+ amdgpu_vcn_save_vcpu_bo(adev,
adev->ip_blocks[i].instance);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index d515cfd2da79..50047c636904 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -294,47 +294,45 @@ bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device
*adev, enum vcn_ring_type t
return ret;
}
-int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev)
+int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev, int inst)
{
unsigned int size;
void *ptr;
- int i, idx;
+ int idx;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->vcn.inst[i].vcpu_bo == NULL)
- return 0;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
- ptr = adev->vcn.inst[i].cpu_addr;
+ if (adev->vcn.inst[inst].vcpu_bo == NULL)
+ return 0;
- adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
- if (!adev->vcn.inst[i].saved_bo)
- return -ENOMEM;
+ size = amdgpu_bo_size(adev->vcn.inst[inst].vcpu_bo);
+ ptr = adev->vcn.inst[inst].cpu_addr;
- if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
- drm_dev_exit(idx);
- }
+ adev->vcn.inst[inst].saved_bo = kvmalloc(size, GFP_KERNEL);
+ if (!adev->vcn.inst[inst].saved_bo)
+ return -ENOMEM;
+
+ if (drm_dev_enter(adev_to_drm(adev), &idx)) {
+ memcpy_fromio(adev->vcn.inst[inst].saved_bo, ptr, size);
+ drm_dev_exit(idx);
}
return 0;
}
-int amdgpu_vcn_suspend(struct amdgpu_device *adev)
+int amdgpu_vcn_suspend(struct amdgpu_device *adev, int inst)
{
bool in_ras_intr = amdgpu_ras_intr_triggered();
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
- cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[inst].idle_work);
/* err_event_athub will corrupt VCPU buffer, so we need to
* restore fw data and clear buffer in amdgpu_vcn_resume() */
if (in_ras_intr)
return 0;
- return amdgpu_vcn_save_vcpu_bo(adev);
+ return amdgpu_vcn_save_vcpu_bo(adev, inst);
}
int amdgpu_vcn_resume(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ce8000ca11ef..be681bcab184 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -486,7 +486,7 @@ enum vcn_ring_type {
int amdgpu_vcn_early_init(struct amdgpu_device
[PATCH 27/29] drm/amdgpu: set funcs for each vcn instance
From: Boyuan Zhang
Pass instance parameter to set_dec_ring_funcs(), set_enc_ring_funcs(),
and set_irq_funcs(), and perform function setup ONLY for the given vcn
instance, instead of for all vcn instances. Modify each vcn generation
accordingly.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 59 +++
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 62 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 46 --
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 31 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 36 ++
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 36 ++
6 files changed, 112 insertions(+), 158 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 0d84cb4279e3..2e5888b905fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -92,9 +92,9 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[]
= {
SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE)
};
-static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
-static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev, int inst);
+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst);
static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
@@ -139,9 +139,9 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block
*ip_block)
adev->vcn.num_enc_rings = 2;
}
- vcn_v2_5_set_dec_ring_funcs(adev);
- vcn_v2_5_set_enc_ring_funcs(adev);
- vcn_v2_5_set_irq_funcs(adev);
+ vcn_v2_5_set_dec_ring_funcs(adev, inst);
+ vcn_v2_5_set_enc_ring_funcs(adev, inst);
+ vcn_v2_5_set_irq_funcs(adev, inst);
vcn_v2_5_set_ras_funcs(adev);
return amdgpu_vcn_early_init(adev, inst);
@@ -1737,29 +1737,25 @@ static const struct amdgpu_ring_funcs
vcn_v2_5_enc_ring_vm_funcs = {
.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
};
-static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
- adev->vcn.inst[i].ring_dec.me = i;
- }
+ adev->vcn.inst[inst].ring_dec.funcs =
&vcn_v2_5_dec_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_dec.me = inst;
}
-static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev, int inst)
{
- int i, j;
+ int i;
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- adev->vcn.inst[j].ring_enc[i].funcs =
&vcn_v2_5_enc_ring_vm_funcs;
- adev->vcn.inst[j].ring_enc[i].me = j;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ adev->vcn.inst[inst].ring_enc[i].funcs =
&vcn_v2_5_enc_ring_vm_funcs;
+ adev->vcn.inst[inst].ring_enc[i].me = inst;
}
}
@@ -1904,19 +1900,16 @@ static const struct amdgpu_irq_src_funcs
vcn_v2_6_ras_irq_funcs = {
.process = amdgpu_vcn_process_poison_irq,
};
-static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
+static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev, int inst)
{
- int i;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
+ adev->vcn.inst[inst].irq.num_types = adev->vcn.num_enc_rings + 1;
+ adev->vcn.inst[inst].irq.funcs = &vcn_v2_5_irq_funcs;
- adev->vcn.inst[i].ras_poison_irq.num_types =
adev->vcn.num_enc_rings + 1;
- adev->vcn.inst[i].ras_poison_irq.funcs =
&vcn_v2_6_ras_irq_funcs;
- }
+
[PATCH 29/29] drm/amdgpu: set_powergating for each vcn instance
From: Boyuan Zhang
Perform set_powergating_state only for the instance of the current vcn
IP block, instead of perform it for all vcn instances.
Signed-off-by: Boyuan Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 313
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 19 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 20 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 20 +-
6 files changed, 199 insertions(+), 213 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 34d94b09f04c..da3d55cc3ac1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -612,114 +612,111 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct
amdgpu_device *adev, int inst_idx
*
* Disable clock gating for VCN block
*/
-static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
+static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
{
uint32_t data;
- int i;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* UVD disable CGC */
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
- data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
- else
- data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
- data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
- data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE);
- data &= ~(UVD_CGC_GATE__SYS_MASK
- | UVD_CGC_GATE__UDEC_MASK
- | UVD_CGC_GATE__MPEG2_MASK
- | UVD_CGC_GATE__REGS_MASK
- | UVD_CGC_GATE__RBC_MASK
- | UVD_CGC_GATE__LMI_MC_MASK
- | UVD_CGC_GATE__LMI_UMC_MASK
- | UVD_CGC_GATE__IDCT_MASK
- | UVD_CGC_GATE__MPRD_MASK
- | UVD_CGC_GATE__MPC_MASK
- | UVD_CGC_GATE__LBSI_MASK
- | UVD_CGC_GATE__LRBBM_MASK
- | UVD_CGC_GATE__UDEC_RE_MASK
- | UVD_CGC_GATE__UDEC_CM_MASK
- | UVD_CGC_GATE__UDEC_IT_MASK
- | UVD_CGC_GATE__UDEC_DB_MASK
- | UVD_CGC_GATE__UDEC_MP_MASK
- | UVD_CGC_GATE__WCB_MASK
- | UVD_CGC_GATE__VCPU_MASK
- | UVD_CGC_GATE__MMSCH_MASK);
-
- WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data);
-
- SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0x);
-
- data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL);
- data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
- | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
- | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
- | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
- | UVD_CGC_CTRL__SYS_MODE_MASK
- | UVD_CGC_CTRL__UDEC_MODE_MASK
- | UVD_CGC_CTRL__MPEG2_MODE_MASK
- | UVD_CGC_CTRL__REGS_MODE_MASK
- | UVD_CGC_CTRL__RBC_MODE_MASK
- | UVD_CGC_CTRL__LMI_MC_MODE_MASK
- | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
- | UVD_CGC_CTRL__IDCT_MODE_MASK
- | UVD_CGC_CTRL__MPRD_MODE_MASK
- | UVD_CGC_CTRL__MPC_MODE_MASK
- | UVD_CGC_CTRL__LBSI_MODE_MASK
- | UVD_CGC_CTRL__LRBBM_MODE_MASK
- | UVD_CGC_CTRL__WCB_MODE_MASK
- | UVD_CGC_CTRL__VCPU_MODE_MASK
- | UVD_CGC_CTRL__MMSCH_MODE_MASK);
- WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data);
-
- /* turn on */
- data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE);
- data |= (UVD_SUVD_CGC_GATE__SRE_MASK
- | UVD_SUVD_CGC_GATE__SIT_MASK
- | UVD_SUVD_CGC_GATE__SMP_MASK
- | UVD_SUVD_CGC_GATE__SCM_MASK
- | UVD_SUVD_CGC_GATE__SDB_MASK
- | UVD_SUVD_CGC_GATE__SRE_H264_MASK
- | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SIT_H264_MASK
- | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
- | UVD_SUVD_CGC_GATE__SCM_H264_MASK
- | UVD_SUVD_CGC_GATE__SCM_H
[PATCH 23/29] drm/amdgpu: hw_init for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_hw_init(), and perform
hw init ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 39 +++--
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 73 -
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 37 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 67 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 21 ---
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 21 ---
6 files changed, 123 insertions(+), 135 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index d135e63e7301..8ce3cea6cf44 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -338,37 +338,36 @@ static int vcn_v2_5_hw_init(struct amdgpu_ip_block
*ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, j, r = 0;
+ int inst = ip_block->instance;
+ int i, r = 0;
if (amdgpu_sriov_vf(adev))
r = vcn_v2_5_sriov_start(adev);
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return r;
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.inst[j].ring_enc[0].sched.ready = true;
- adev->vcn.inst[j].ring_enc[1].sched.ready = false;
- adev->vcn.inst[j].ring_enc[2].sched.ready = false;
- adev->vcn.inst[j].ring_dec.sched.ready = true;
- } else {
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.inst[inst].ring_enc[0].sched.ready = true;
+ adev->vcn.inst[inst].ring_enc[1].sched.ready = false;
+ adev->vcn.inst[inst].ring_enc[2].sched.ready = false;
+ adev->vcn.inst[inst].ring_dec.sched.ready = true;
+ } else {
+
+ ring = &adev->vcn.inst[inst].ring_dec;
- ring = &adev->vcn.inst[j].ring_dec;
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ring->doorbell_index, inst);
- adev->nbio.funcs->vcn_doorbell_range(adev,
ring->use_doorbell,
-ring->doorbell_index, j);
+ r = amdgpu_ring_test_helper(ring);
+ if (r)
+ return r;
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ ring = &adev->vcn.inst[inst].ring_enc[i];
r = amdgpu_ring_test_helper(ring);
if (r)
return r;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- ring = &adev->vcn.inst[j].ring_enc[i];
- r = amdgpu_ring_test_helper(ring);
- if (r)
- return r;
- }
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index d00b7a7cbdce..36100c2612d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -345,8 +345,9 @@ static int vcn_v3_0_sw_fini(struct amdgpu_ip_block
*ip_block)
static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
struct amdgpu_ring *ring;
- int i, j, r;
+ int j, r;
if (amdgpu_sriov_vf(adev)) {
r = vcn_v3_0_start_sriov(adev);
@@ -354,57 +355,53 @@ static int vcn_v3_0_hw_init(struct amdgpu_ip_block
*ip_block)
return r;
/* initialize VCN dec and enc ring buffers */
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ if (amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, inst)) {
+ ring->sched.ready = false;
+ ring->no_scheduler = true;
+ dev_info(adev->dev, "ring %s is disabled by
hypervisor\n", ring->name);
+ } else {
+ ring->wptr = 0;
+ ring->wptr_old = 0;
+ vcn_v3_0_dec_ring_set_wptr(ring);
+ ring->sched.ready = true;
+ }
- ring = &adev->vcn
[PATCH 12/29] drm/amdgpu: power vcn 2_5 by instance
From: Boyuan Zhang
For vcn 2_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 565 +-
2 files changed, 281 insertions(+), 289 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index cce3f1a6f288..6bdd4055c192 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2278,6 +2278,8 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct
amdgpu_device *adev)
static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
{
+ int i;
+
if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
case IP_VERSION(7, 0, 0):
@@ -2321,7 +2323,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
case IP_VERSION(2, 0, 3):
break;
case IP_VERSION(2, 5, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v2_5_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
break;
case IP_VERSION(2, 6, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index a14b634c433c..010970faa5fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -158,35 +158,34 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block
*ip_block)
static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
uint32_t *ptr;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- /* VCN DEC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
&adev->vcn.inst[j].irq);
- if (r)
- return r;
-
- /* VCN ENC TRAP */
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[j].irq);
- if (r)
- return r;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto sw_init;
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT,
&adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_6__SRCID_UVD_POISON,
&adev->vcn.inst[j].ras_poison_irq);
+ /* VCN ENC TRAP */
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[inst].irq);
if (r)
return r;
}
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_6__SRCID_UVD_POISON,
&adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
+sw_init:
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -197,76 +196,74 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- adev->vcn.internal.context_id =
mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid =
mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev-
[PATCH 18/29] drm/amdgpu/vcn: separate idle work by instance
From: Boyuan Zhang
Previously idle working handling is for all VCN instances. As a result, when one
of the instance finishes its job, the idle work can't be triggered if the other
instance is still busy.
Now, move the idle_work from amdgpu_vcn to amdgpu_vcn_inst, in order to
track work by vcn instance. Add work_inst to track the instance number
that the work belongs to. As a result, the idle work can now be triggered
once the job is done on one of the vcn instance, and no need to consider
the work on the other vcn instance.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 66
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 14 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +-
17 files changed, 58 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 49802e66a358..3d2d2a0d98c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -118,7 +118,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
unsigned int fw_shared_size, log_offset;
int i, r;
- INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ adev->vcn.inst[i].adev = adev;
+ adev->vcn.inst[i].work_inst = i;
+ INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work,
amdgpu_vcn_idle_work_handler);
+ }
mutex_init(&adev->vcn.vcn_pg_lock);
mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
atomic_set(&adev->vcn.total_submission_cnt, 0);
@@ -326,7 +330,8 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
{
bool in_ras_intr = amdgpu_ras_intr_triggered();
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
/* err_event_athub will corrupt VCPU buffer, so we need to
* restore fw data and clear buffer in amdgpu_vcn_resume() */
@@ -382,46 +387,43 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
{
- struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
- unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
- unsigned int i, j;
+ struct amdgpu_vcn_inst *vcn_inst =
+ container_of(work, struct amdgpu_vcn_inst, idle_work.work);
+ struct amdgpu_device *adev = vcn_inst->adev;
+ unsigned int inst = vcn_inst->work_inst;
+ unsigned int fence = 0;
+ unsigned int i;
int r = 0;
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i)
- fence[j] +=
amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
-
- /* Only set DPG pause for VCN3 or below, VCN4 and above will be
handled by FW */
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
- !adev->vcn.using_unified_queue) {
- struct dpg_pause_state new_state;
-
- if (fence[j] ||
-
unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
- new_state.fw_based = VCN_DPG_STATE__PAUSE;
- else
- new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.pause_dpg_mode(adev, j, &new_state);
- }
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ fence +=
amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_enc[i]);
- fence[j] +=
amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
- fences += fence[j];
+ /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled
by FW */
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
+
[PATCH 16/29] drm/amdgpu: power vcn 4_0_5 by instance
From: Boyuan Zhang
For vcn 4_0_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 510 +-
2 files changed, 252 insertions(+), 261 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index ee10a9218df7..48160fa4d8ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2358,7 +2358,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
break;
case IP_VERSION(4, 0, 5):
case IP_VERSION(4, 0, 6):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v4_0_5_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 9c5257f370f2..0f3b25d3b9d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -132,7 +132,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block
*ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
uint32_t *ptr;
@@ -146,57 +146,55 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON,
&adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- i * (adev->vcn.num_enc_rings +
1) + 1;
- else
- ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0,
&adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 <<
1) +
+ inst * (adev->vcn.num_enc_rings + 1) +
1;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 <<
1) +
+ 2 + 8 * inst;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d",
[PATCH 20/29] drm/amdgpu: early_init for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_early_init(), and perform
early init ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 23 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 13 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 12 +---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 3 ++-
10 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index efd6c9eb3502..21701738030f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -91,22 +91,23 @@ MODULE_FIRMWARE(FIRMWARE_VCN5_0_0);
static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
-int amdgpu_vcn_early_init(struct amdgpu_device *adev)
+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst)
{
char ucode_prefix[25];
- int r, i;
+ int r;
amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix,
sizeof(ucode_prefix));
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (i == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) ==
IP_VERSION(4, 0, 6))
- r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
"amdgpu/%s_%d.bin", ucode_prefix, i);
- else
- r = amdgpu_ucode_request(adev, &adev->vcn.inst[i].fw,
"amdgpu/%s.bin", ucode_prefix);
- if (r) {
- amdgpu_ucode_release(&adev->vcn.inst[i].fw);
- return r;
- }
+
+ if (inst == 1 && amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4,
0, 6))
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[inst].fw,
"amdgpu/%s_%d.bin", ucode_prefix, inst);
+ else
+ r = amdgpu_ucode_request(adev, &adev->vcn.inst[inst].fw,
"amdgpu/%s.bin", ucode_prefix);
+
+ if (r) {
+ amdgpu_ucode_release(&adev->vcn.inst[inst].fw);
+ return r;
}
+
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2282c4d14ae7..58fbb87e5ec4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -483,7 +483,7 @@ enum vcn_ring_type {
VCN_UNIFIED_RING,
};
-int amdgpu_vcn_early_init(struct amdgpu_device *adev);
+int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 8b860db34584..6fd509e6744d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -104,6 +104,7 @@ static void vcn_v1_0_ring_begin_use(struct amdgpu_ring
*ring);
static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
adev->vcn.num_enc_rings = 2;
@@ -113,7 +114,7 @@ static int vcn_v1_0_early_init(struct amdgpu_ip_block
*ip_block)
jpeg_v1_0_early_init(ip_block);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 419ecba12c9b..8f7038190a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -108,6 +108,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
if (amdgpu_sriov_vf(adev))
adev->vcn.num_enc_rings = 1;
@@ -118,7 +119,7 @@ static int vcn_v2_0_early_init(struct amdgpu_ip_block
*ip_block)
vcn_v2_0_set_enc_ring_funcs(adev);
vcn_v2_0_set_irq_funcs(adev);
- return amdgpu_vcn_early_init(adev);
+ return amdgpu_vcn_early_init(adev, inst);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7e7ce00806cc..74814370ddc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -118,6 +118,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *a
[PATCH 15/29] drm/amdgpu: power vcn 4_0_3 by instance
From: Boyuan Zhang
For vcn 4_0_3, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 462 +-
2 files changed, 228 insertions(+), 237 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index aaa759765dba..ee10a9218df7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2352,7 +2352,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v4_0_3_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
break;
case IP_VERSION(4, 0, 5):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 8e7d7318cf58..db6f8d424777 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -127,7 +127,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r, vcn_inst;
+ int inst = ip_block->instance, r, vcn_inst;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
uint32_t *ptr;
@@ -147,38 +147,36 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- vcn_inst = GET_INST(VCN, i);
+ vcn_inst = GET_INST(VCN, inst);
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
-
- if (!amdgpu_sriov_vf(adev))
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst;
- else
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 32 * vcn_inst;
-
- ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
- sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
-AMDGPU_RING_PRIO_DEFAULT,
-&adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 =
cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = true;
+ if (!amdgpu_sriov_vf(adev))
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 9 * vcn_inst;
+ else
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 32 * vcn_inst;
+
+ ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[inst].aid_id);
+ sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[inst].aid_id);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
+AMDGPU_RING_PRIO_DEFAULT,
+&adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 =
cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = true;
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
@@ -1085,174 +1083,170 @@ s
[PATCH 11/29] drm/amdgpu/vcn: separate gating state by instance
From: Boyuan Zhang
vcn gating state should now be based on instance. For example, instance 0
can be gated while instance 1 is ungated, or vice versa.
Therefore, change the cur_state to be an array, so that it can track the
gating status for each vcn instance now.
v2: remove redundant codes in v1.
v3: move cur_state from amdgpu_vcn to amdgou_vcn_inst since it's a per
instance variable.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 7 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 ---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 28 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 25 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 31 ---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 24 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 24 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
10 files changed, 84 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ba58b4f07643..2b8c9b8d4494 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -298,6 +298,7 @@ struct amdgpu_vcn_inst {
struct amdgpu_vcn_fw_shared fw_shared;
uint8_t aid_id;
const struct firmware *fw; /* VCN firmware */
+ enum amd_powergating_state cur_state;
uint8_t vcn_config;
uint32_tvcn_codec_disable_mask;
};
@@ -310,7 +311,6 @@ struct amdgpu_vcn {
unsignedfw_version;
struct delayed_work idle_work;
unsignednum_enc_rings;
- enum amd_powergating_state cur_state;
boolindirect_sram;
uint8_t num_vcn_inst;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 5ea96c983517..c2eb187b0a27 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -280,7 +280,7 @@ static int vcn_v1_0_hw_fini(struct amdgpu_ip_block
*ip_block)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
@@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(struct
amdgpu_ip_block *ip_block,
int ret;
struct amdgpu_device *adev = ip_block->adev;
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1822,7 +1822,8 @@ static int vcn_v1_0_set_powergating_state(struct
amdgpu_ip_block *ip_block,
ret = vcn_v1_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[0].cur_state = state;
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index e42cfc731ad8..04edbb368903 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -316,7 +316,7 @@ static int vcn_v2_0_hw_fini(struct amdgpu_ip_block
*ip_block)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.inst[0].cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
@@ -1810,11 +1810,11 @@ static int vcn_v2_0_set_powergating_state(struct
amdgpu_ip_block *ip_block,
struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.inst[0].cur_state = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.inst[0].cur_state)
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1823,7 +1823,8 @@ static int vcn_v2_0_set_powergating_state(struct
amdgpu_ip_block *ip_block,
ret = vcn_v2_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.inst[0].cur_state = state;
+
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index b518202955ca..a14b634c433c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -38
[PATCH 28/29] drm/amdgpu: wait_for_idle for each vcn instance
From: Boyuan Zhang
Perform wait_for_idle only for the instance of the current vcn IP block,
instead of perform it for all vcn instances.
v2: remove unneeded local variable initialization.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 16 +++-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 15 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 15 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 11 ---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 15 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 15 ++-
6 files changed, 35 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 2e5888b905fb..34d94b09f04c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1777,16 +1777,14 @@ static bool vcn_v2_5_is_idle(void *handle)
static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 0d1c1534db40..451858f86272 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -2105,17 +2105,14 @@ static bool vcn_v3_0_is_idle(void *handle)
static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e9a8e027d5f9..fa7cf10e8900 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -1968,17 +1968,14 @@ static bool vcn_v4_0_is_idle(void *handle)
static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS,
UVD_STATUS__IDLE,
- UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE,
+ UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 716bc85141cb..d05dcadb3e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1566,14 +1566,11 @@ static bool vcn_v4_0_3_is_idle(void *handle)
static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
- int i, ret = 0;
+ int inst = ip_block->instance;
+ int ret;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS,
-UVD_STATUS__IDLE, UVD_STATUS__IDLE);
- if (ret)
- return ret;
- }
+ ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, inst), regUVD_STATUS,
+UVD_STATUS__IDLE, UVD_STATUS__IDLE);
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index b74b2c0942c9..307c8e204456 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1465,1
[PATCH 22/29] drm/amdgpu: sw_fini for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_sw_fini(), and perform
sw fini ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 36 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 17 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 20 +++---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 21 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 16 +--
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 21 +++
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 21 +++
10 files changed, 81 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 2c55166e27d9..d515cfd2da79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -248,33 +248,31 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int
inst)
return 0;
}
-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst)
{
- int i, j;
-
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
+ int i;
- amdgpu_bo_free_kernel(
- &adev->vcn.inst[j].dpg_sram_bo,
- &adev->vcn.inst[j].dpg_sram_gpu_addr,
- (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- kvfree(adev->vcn.inst[j].saved_bo);
+ amdgpu_bo_free_kernel(
+ &adev->vcn.inst[inst].dpg_sram_bo,
+ &adev->vcn.inst[inst].dpg_sram_gpu_addr,
+ (void **)&adev->vcn.inst[inst].dpg_sram_cpu_addr);
- amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
- &adev->vcn.inst[j].gpu_addr,
- (void **)&adev->vcn.inst[j].cpu_addr);
+ kvfree(adev->vcn.inst[inst].saved_bo);
- amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
+ amdgpu_bo_free_kernel(&adev->vcn.inst[inst].vcpu_bo,
+ &adev->vcn.inst[inst].gpu_addr,
+ (void **)&adev->vcn.inst[inst].cpu_addr);
- for (i = 0; i < adev->vcn.num_enc_rings; ++i)
- amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
+ amdgpu_ring_fini(&adev->vcn.inst[inst].ring_dec);
- amdgpu_ucode_release(&adev->vcn.inst[j].fw);
- }
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ amdgpu_ring_fini(&adev->vcn.inst[inst].ring_enc[i]);
+ amdgpu_ucode_release(&adev->vcn.inst[inst].fw);
+done:
mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
mutex_destroy(&adev->vcn.vcn_pg_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 4809da69bd1b..ce8000ca11ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -485,7 +485,7 @@ enum vcn_ring_type {
int amdgpu_vcn_early_init(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_sw_init(struct amdgpu_device *adev, int inst);
-int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
+int amdgpu_vcn_sw_fini(struct amdgpu_device *adev, int inst);
int amdgpu_vcn_suspend(struct amdgpu_device *adev);
int amdgpu_vcn_resume(struct amdgpu_device *adev);
void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 808d69ab0904..44370949fa57 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -222,8 +222,9 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block
*ip_block)
*/
static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block)
{
- int r;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
+ int r;
r = amdgpu_vcn_suspend(adev);
if (r)
@@ -231,7 +232,7 @@ static int vcn_v1_0_sw_fini(struct amdgpu_ip_block
*ip_block)
jpeg_v1_0_sw_fini(ip_block);
- r = amdgpu_vcn_sw_fini(adev);
+ r = amdgpu_vcn_sw_fini(adev, inst);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index a86cff00d761..7b5f2696e60d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -245,9 +245,10 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block
*ip_block)
*/
static int vcn_v2_0_sw_fini(struct amdgpu
[PATCH 25/29] drm/amdgpu: resume for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_resume(), and perform
resume ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 60 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 +-
10 files changed, 47 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 50047c636904..c4e1283aa9a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -335,47 +335,47 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev, int
inst)
return amdgpu_vcn_save_vcpu_bo(adev, inst);
}
-int amdgpu_vcn_resume(struct amdgpu_device *adev)
+int amdgpu_vcn_resume(struct amdgpu_device *adev, int inst)
{
unsigned int size;
void *ptr;
- int i, idx;
+ int idx;
+
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->vcn.inst[i].vcpu_bo == NULL)
- return -EINVAL;
+ if (adev->vcn.inst[inst].vcpu_bo == NULL)
+ return -EINVAL;
+
+ size = amdgpu_bo_size(adev->vcn.inst[inst].vcpu_bo);
+ ptr = adev->vcn.inst[inst].cpu_addr;
- size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
- ptr = adev->vcn.inst[i].cpu_addr;
+ if (adev->vcn.inst[inst].saved_bo != NULL) {
+ if (drm_dev_enter(adev_to_drm(adev), &idx)) {
+ memcpy_toio(ptr, adev->vcn.inst[inst].saved_bo, size);
+ drm_dev_exit(idx);
+ }
+ kvfree(adev->vcn.inst[inst].saved_bo);
+ adev->vcn.inst[inst].saved_bo = NULL;
+ } else {
+ const struct common_firmware_header *hdr;
+ unsigned int offset;
- if (adev->vcn.inst[i].saved_bo != NULL) {
+ hdr = (const struct common_firmware_header
*)adev->vcn.inst[inst].fw->data;
+ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
+ offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_toio(ptr, adev->vcn.inst[i].saved_bo,
size);
+ memcpy_toio(adev->vcn.inst[inst].cpu_addr,
+ adev->vcn.inst[inst].fw->data +
offset,
+
le32_to_cpu(hdr->ucode_size_bytes));
drm_dev_exit(idx);
}
- kvfree(adev->vcn.inst[i].saved_bo);
- adev->vcn.inst[i].saved_bo = NULL;
- } else {
- const struct common_firmware_header *hdr;
- unsigned int offset;
-
- hdr = (const struct common_firmware_header
*)adev->vcn.inst[i].fw->data;
- if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- offset =
le32_to_cpu(hdr->ucode_array_offset_bytes);
- if (drm_dev_enter(adev_to_drm(adev), &idx)) {
- memcpy_toio(adev->vcn.inst[i].cpu_addr,
- adev->vcn.inst[i].fw->data
+ offset,
-
le32_to_cpu(hdr->ucode_size_bytes));
- drm_dev_exit(idx);
- }
- size -= le32_to_cpu(hdr->ucode_size_bytes);
- ptr += le32_to_cpu(hdr->ucode_size_bytes);
- }
- memset_io(ptr, 0, size);
+ size -= le32_to_cpu(hdr->ucode_size_bytes);
+ ptr += le32_to_cpu(hdr->ucode_size_bytes);
}
+ memset_io(ptr, 0, size);
}
+
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index be681bcab184..75cfdb770672 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -487,7 +487,7 @@ int amdgpu_vcn_early_init(struct amdgpu_device *adev, int
inst);
int amdgpu_vcn_sw_init(stru
[PATCH 03/29] drm/amd/pm: add inst to smu_dpm_set_vcn_enable
From: Boyuan Zhang
First, add an instance parameter to smu_dpm_set_vcn_enable() function,
and calling dpm_set_vcn_enable() with this given instance.
Second, modify vcn_gated to be an array, to track the gating status
for each vcn instance separately.
With these 2 changes, smu_dpm_set_vcn_enable() will check and set the
gating status for the given vcn instance ONLY.
v2: remove duplicated functions.
remove for-loop in dpm_set_vcn_enable(), and temporarily move it to
to smu_dpm_set_power_gate(), in order to keep the exact same logic as
before, until further separation in next patch.
v3: add instance number in error message.
Signed-off-by: Boyuan Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 65 ---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
2 files changed, 42 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ccacba56159e..bb7980f48674 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -234,11 +234,11 @@ static bool is_vcn_enabled(struct amdgpu_device *adev)
}
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
- bool enable)
+ bool enable,
+ int inst)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- struct amdgpu_device *adev = smu->adev;
int ret = 0;
/*
@@ -250,14 +250,12 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (!smu->ppt_funcs->dpm_set_vcn_enable)
return 0;
- if (atomic_read(&power_gate->vcn_gated) ^ enable)
+ if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
return 0;
- for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i);
- if (ret)
- return ret;
- }
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, inst);
+ if (!ret)
+ atomic_set(&power_gate->vcn_gated[inst], !enable);
return ret;
}
@@ -359,6 +357,7 @@ static int smu_dpm_set_power_gate(void *handle,
bool gate)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
@@ -375,10 +374,12 @@ static int smu_dpm_set_power_gate(void *handle,
*/
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
- ret = smu_dpm_set_vcn_enable(smu, !gate);
- if (ret)
- dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
- gate ? "gate" : "ungate");
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, !gate, i);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VCN
instance %d!\n",
+ gate ? "gate" : "ungate", i);
+ }
break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
@@ -780,21 +781,25 @@ static int smu_set_default_dpm_table(struct smu_context
*smu)
struct amdgpu_device *adev = smu->adev;
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
- int vcn_gate, jpeg_gate;
+ int vcn_gate[AMDGPU_MAX_VCN_INSTANCES], jpeg_gate, i;
int ret = 0;
if (!smu->ppt_funcs->set_default_dpm_table)
return 0;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- vcn_gate = atomic_read(&power_gate->vcn_gated);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++)
+ vcn_gate[i] = atomic_read(&power_gate->vcn_gated[i]);
+ }
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
jpeg_gate = atomic_read(&power_gate->jpeg_gated);
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
- ret = smu_dpm_set_vcn_enable(smu, true);
- if (ret)
- return ret;
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu_dpm_set_vcn_enable(smu, true, i);
+ if (ret)
+ return ret;
+ }
}
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
@@ -811,8 +816,10 @@ static int smu_set_default_dpm_table(struct smu_context
*smu)
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
err_out:
- if
[PATCH 19/29] drm/amdgpu: set powergating state by vcn instance
From: Boyuan Zhang
Set powergating state by vcn instance in idle_work_handler() and
ring_begin_use() functions for vcn with multiple instances.
v2: Add instance parameter to amdgpu_device_ip_set_powergating_state(),
instead of creating new function.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 8
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c| 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c| 4 ++--
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 6 --
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 8
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 6 --
.../amd/pm/powerplay/hwmgr/smu7_clockpowergating.c | 12
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 12
.../gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c| 6 --
22 files changed, 65 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2e2c6a556cc8..03ae6f614969 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -357,7 +357,8 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
enum amd_clockgating_state state);
int amdgpu_device_ip_set_powergating_state(void *dev,
enum amd_ip_block_type block_type,
- enum amd_powergating_state state);
+ enum amd_powergating_state state,
+ int inst);
void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
u64 *flags);
int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 065463b5d6a9..7a44ceeb7ec9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2177,7 +2177,8 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
*/
int amdgpu_device_ip_set_powergating_state(void *dev,
enum amd_ip_block_type block_type,
- enum amd_powergating_state state)
+ enum amd_powergating_state state,
+ int inst)
{
struct amdgpu_device *adev = dev;
int i, r = 0;
@@ -2187,6 +2188,9 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
continue;
if (adev->ip_blocks[i].version->type != block_type)
continue;
+ if (block_type == AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].instance != inst)
+ continue;
if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
continue;
r = adev->ip_blocks[i].version->funcs->set_powergating_state(
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index 95e2796919fc..78fd1ff28a57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -119,7 +119,7 @@ static void amdgpu_jpeg_idle_work_handler(struct
work_struct *work)
if (!fences && !atomic_read(&adev->jpeg.total_submission_cnt))
amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_JPEG,
- AMD_PG_STATE_GATE);
+ AMD_PG_STATE_GATE, 0);
else
schedule_delayed_work(&adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT);
}
@@ -133,7 +133,7 @@ void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring)
mutex_lock(&adev->jpeg.jpeg_pg_lock);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG,
- AMD_PG_STATE_UNGAT
[PATCH 09/29] drm/amdgpu: track instances of the same IP block
From: Boyuan Zhang
Add a new function to count the number of instance of the same IP block
in the current ip_block list, then use the returned count value to set
the newly defined instance variable in ip_block, to track the instance
number of each ip_block.
Signed-off-by: Boyuan Zhang
Signed-off-by: Alex Deucher
Suggested-by: Christian König
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 25 +-
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fba10ad44be9..2e2c6a556cc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -390,6 +390,7 @@ struct amdgpu_ip_block {
struct amdgpu_ip_block_status status;
const struct amdgpu_ip_block_version *version;
struct amdgpu_device *adev;
+ unsigned int instance;
};
int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c06e3a9146c..065463b5d6a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2322,6 +2322,28 @@ int amdgpu_device_ip_block_version_cmp(struct
amdgpu_device *adev,
return 1;
}
+/**
+ * amdgpu_device_ip_get_num_instances - get number of instances of an IP block
+ *
+ * @adev: amdgpu_device pointer
+ * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
+ *
+ * Returns the count of the hardware IP blocks structure for that type.
+ */
+static unsigned int
+amdgpu_device_ip_get_num_instances(struct amdgpu_device *adev,
+ enum amd_ip_block_type type)
+{
+ unsigned int i, count = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (adev->ip_blocks[i].version->type == type)
+ count++;
+ }
+
+ return count;
+}
+
/**
* amdgpu_device_ip_block_add
*
@@ -2354,7 +2376,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
ip_block_version->funcs->name);
adev->ip_blocks[adev->num_ip_blocks].adev = adev;
-
+ adev->ip_blocks[adev->num_ip_blocks].instance =
+ amdgpu_device_ip_get_num_instances(adev,
ip_block_version->type);
adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
return 0;
--
2.34.1
[PATCH 02/29] drm/amd/pm: power up or down vcn by instance
From: Boyuan Zhang
For smu ip with multiple vcn instances (smu 11/13/14), remove all the
for loop in dpm_set_vcn_enable() functions. And use the instance
argument to power up/down vcn for the given instance only, instead
of powering up/down for all vcn instances.
v2: remove all duplicated functions in v1.
remove for-loop from each ip, and temporarily move to dpm_set_vcn_enable,
in order to keep the exact same logic as before, until further separation
in the next patch.
Signed-off-by: Boyuan Zhang
Acked-by: Christian König
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 +++--
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 20 +--
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 16 -
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c| 35 ---
4 files changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index fe2a740766a2..ccacba56159e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -238,6 +238,7 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
/*
@@ -252,9 +253,11 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (atomic_read(&power_gate->vcn_gated) ^ enable)
return 0;
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, 0xff);
- if (!ret)
- atomic_set(&power_gate->vcn_gated, !enable);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable, i);
+ if (ret)
+ return ret;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index a9cb28ce2133..24cf17e172f4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1157,19 +1157,15 @@ static int sienna_cichlid_dpm_set_vcn_enable(struct
smu_context *smu,
int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* vcn dpm on is a prerequisite for vcn power gate messages */
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT))
{
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
-
SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- 0x1 * i,
NULL);
- if (ret)
- return ret;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+SMU_MSG_PowerUpVcn :
SMU_MSG_PowerDownVcn,
+0x1 * inst, NULL);
}
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 2bfea740dace..bb506d15d787 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2108,18 +2108,14 @@ int smu_v13_0_set_vcn_enable(struct smu_context *smu,
int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn :
SMU_MSG_PowerDownVcn,
- i << 16U, NULL);
- if (ret)
- return ret;
- }
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn :
SMU_MSG_PowerDownVcn,
+ inst << 16U, NULL);
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index ecb0164d533e..5460f8e
[PATCH 17/29] drm/amdgpu: power vcn 5_0_0 by instance
From: Boyuan Zhang
For vcn 5_0_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
v2: rename "i"/"j" to "inst" for instance value.
Signed-off-by: Boyuan Zhang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 432 +-
2 files changed, 213 insertions(+), 222 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 48160fa4d8ef..3c85a692a34e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2363,7 +2363,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct
amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add(adev,
&vcn_v5_0_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 4ecf0aea156f..15620e111d04 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -116,7 +116,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block
*ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
uint32_t *ptr;
@@ -130,46 +130,44 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn5_fw_shared *fw_shared;
-
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ volatile struct amdgpu_vcn5_fw_shared *fw_shared;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[i].irq);
- if (r)
- return r;
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON,
&adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
&adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 <<
1) + 2 + 8 * i;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2
+ 8 * inst;
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0,
&adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 =
cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = 1;
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0,
&adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn
[PATCH 26/29] drm/amdgpu: setup_ucode for each vcn instance
From: Boyuan Zhang
Pass instance parameter to amdgpu_vcn_setup_ucode(), and perform
setup ucode ONLY for the given vcn instance, instead of for all
vcn instances. Modify each vcn generation accordingly.
Signed-off-by: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 37 -
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 2 +-
10 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index c4e1283aa9a4..29f6a2b76919 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1049,34 +1049,31 @@ enum amdgpu_ring_priority_level
amdgpu_vcn_get_enc_ring_prio(int ring)
}
}
-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int inst)
{
- int i;
unsigned int idx;
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
const struct common_firmware_header *hdr;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- hdr = (const struct common_firmware_header
*)adev->vcn.inst[i].fw->data;
- /* currently only support 2 FW instances */
- if (i >= 2) {
- dev_info(adev->dev, "More then 2 VCN FW
instances!\n");
- break;
- }
- idx = AMDGPU_UCODE_ID_VCN + i;
- adev->firmware.ucode[idx].ucode_id = idx;
- adev->firmware.ucode[idx].fw = adev->vcn.inst[i].fw;
- adev->firmware.fw_size +=
- ALIGN(le32_to_cpu(hdr->ucode_size_bytes),
PAGE_SIZE);
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(4, 0, 3))
- break;
+ hdr = (const struct common_firmware_header
*)adev->vcn.inst[inst].fw->data;
+ /* currently only support 2 FW instances */
+ if (inst >= 2) {
+ dev_info(adev->dev, "More then 2 VCN FW instances!\n");
+ return;
}
+ idx = AMDGPU_UCODE_ID_VCN + inst;
+ adev->firmware.ucode[idx].ucode_id = idx;
+ adev->firmware.ucode[idx].fw = adev->vcn.inst[inst].fw;
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(4, 0, 3))
+ return;
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 75cfdb770672..6cd094ee8218 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -505,7 +505,7 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring,
long timeout);
enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
-void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int inst);
void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn);
void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 77f9f34eaca8..7638ddeccec7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -154,7 +154,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block
*ip_block)
/* Override the work func */
adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, inst);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 87293bb777d4..a327c3bf84f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -159,7 +159,7 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
- amdgpu_vcn_setup_ucode(adev);
+ amdgpu_vcn_setup_ucode(adev, inst);
r = amdgpu_vcn_resume(adev, in
Re: [PATCH 2/2] drm: remove driver date from struct drm_driver and all drivers
On Thu, Oct 24, 2024 at 12:33 PM Jani Nikula wrote:
>
> We stopped using the driver initialized date in commit 7fb8af6798e8
> ("drm: deprecate driver date") and (eventually) started returning "0"
> for drm_version ioctl instead.
>
> Finish the job, and remove the unused date member from struct
> drm_driver, its initialization from drivers, along with the common
> DRIVER_DATE macros.
>
> Signed-off-by: Jani Nikula
Acked-by: Alex Deucher
>
> ---
>
> Cc: David Airlie
> Cc: Hamza Mahfooz
> Cc: Javier Martinez Canillas
> Cc: Maarten Lankhorst
> Cc: Maxime Ripard
> Cc: Oleksandr Andrushchenko
> Cc: Simon Ser
> Cc: Simona Vetter
> Cc: Thomas Zimmermann
> Cc: Ville Syrjälä
> Cc: amd-gfx@lists.freedesktop.org
> Cc: dri-de...@lists.freedesktop.org
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: nouv...@lists.freedesktop.org
> Cc: xen-de...@lists.xenproject.org
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h | 1 -
> drivers/gpu/drm/arm/display/komeda/komeda_kms.c | 1 -
> drivers/gpu/drm/arm/hdlcd_drv.c | 1 -
> drivers/gpu/drm/arm/malidp_drv.c | 1 -
> drivers/gpu/drm/armada/armada_drv.c | 1 -
> drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 1 -
> drivers/gpu/drm/ast/ast_drv.c| 1 -
> drivers/gpu/drm/ast/ast_drv.h| 1 -
> drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c | 1 -
> drivers/gpu/drm/etnaviv/etnaviv_drv.c| 1 -
> drivers/gpu/drm/exynos/exynos_drm_drv.c | 2 --
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c| 1 -
> drivers/gpu/drm/gma500/psb_drv.c | 1 -
> drivers/gpu/drm/gma500/psb_drv.h | 1 -
> drivers/gpu/drm/gud/gud_drv.c| 1 -
> drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 1 -
> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 1 -
> drivers/gpu/drm/hyperv/hyperv_drm_drv.c | 2 --
> drivers/gpu/drm/i915/i915_driver.c | 1 -
> drivers/gpu/drm/i915/i915_driver.h | 1 -
> drivers/gpu/drm/i915/i915_gpu_error.c| 1 -
> drivers/gpu/drm/imagination/pvr_drv.c| 1 -
> drivers/gpu/drm/imagination/pvr_drv.h| 1 -
> drivers/gpu/drm/imx/dcss/dcss-kms.c | 1 -
> drivers/gpu/drm/imx/ipuv3/imx-drm-core.c | 1 -
> drivers/gpu/drm/imx/lcdc/imx-lcdc.c | 1 -
> drivers/gpu/drm/ingenic/ingenic-drm-drv.c| 1 -
> drivers/gpu/drm/kmb/kmb_drv.c| 1 -
> drivers/gpu/drm/kmb/kmb_drv.h| 1 -
> drivers/gpu/drm/lima/lima_drv.c | 1 -
> drivers/gpu/drm/logicvc/logicvc_drm.c| 1 -
> drivers/gpu/drm/loongson/lsdc_drv.c | 2 --
> drivers/gpu/drm/mcde/mcde_drv.c | 1 -
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 --
> drivers/gpu/drm/meson/meson_drv.c| 1 -
> drivers/gpu/drm/mgag200/mgag200_drv.c| 1 -
> drivers/gpu/drm/mgag200/mgag200_drv.h| 1 -
> drivers/gpu/drm/msm/msm_drv.c| 1 -
> drivers/gpu/drm/mxsfb/lcdif_drv.c| 1 -
> drivers/gpu/drm/mxsfb/mxsfb_drv.c| 1 -
> drivers/gpu/drm/nouveau/nouveau_drm.c| 5 -
> drivers/gpu/drm/nouveau/nouveau_drv.h| 1 -
> drivers/gpu/drm/omapdrm/omap_drv.c | 2 --
> drivers/gpu/drm/panfrost/panfrost_drv.c | 1 -
> drivers/gpu/drm/panthor/panthor_drv.c| 1 -
> drivers/gpu/drm/pl111/pl111_drv.c| 1 -
> drivers/gpu/drm/qxl/qxl_drv.c| 1 -
> drivers/gpu/drm/qxl/qxl_drv.h| 1 -
> drivers/gpu/drm/radeon/radeon_drv.c | 1 -
> drivers/gpu/drm/radeon/radeon_drv.h | 1 -
> drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c| 1 -
> drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 1 -
> drivers/gpu/drm/renesas/shmobile/shmob_drm_drv.c | 1 -
> drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 --
> drivers/gpu/drm/solomon/ssd130x.c| 2 --
> drivers/gpu/drm/sprd/sprd_drm.c | 2 --
> drivers/gpu/drm/sti/sti_drv.c| 2 --
> drivers/gpu/drm/stm/drv.c| 1 -
> drivers/gpu/drm/sun4i/sun4i_drv.c| 1 -
> drivers/gpu/drm/tegra/drm.c | 2 --
> drivers/gpu/drm/tidss/tidss_drv.c| 1 -
> drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 -
> drivers/gpu/drm/tiny/arcpgu.c| 1 -
> drivers/gpu/drm/tiny/bochs.c | 1 -
> drivers/gpu/drm/tiny/cirrus.c| 2 --
> drivers/gpu/drm/tiny/gm12u320.c | 2 --
> drivers/gpu/drm/tiny/hx8357d.c | 1 -
> drivers/gpu/drm/tiny/ili9163.c | 1 -
> drivers/gpu/drm/tiny/ili9225.c | 1 -
> drivers/gpu/drm/tiny/ili9341.c
Re: [PATCH 08/32] drm/amdgpu: pass ip_block in set_clockgating_state
On 2024-10-22 03:58, Khatri, Sunil wrote: On 10/17/2024 6:50 PM, boyuan.zh...@amd.com wrote: From: Boyuan Zhang Pass ip_block instead of adev in set_clockgating_state() and is_idle() callback functions. Modify set_clockgating_state() and is_idle() ip functions for all correspoding ip blocks. Signed-off-by: Boyuan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 drivers/gpu/drm/amd/amdgpu/cz_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 10 +- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/nv.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/si.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +- drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/soc21.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/soc24.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 8 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 17 ++--- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 19 +++ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 14 +++--- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 11 ++- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 10 +- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 + drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vi.c |
[PATCH 00/29] Separating vcn power management by instance
From: Boyuan Zhang v5: revise patch #6, #28 based on Christian's comments. revise patch #7, #8 based on Sunil's comments. revise patch #24 due to Lijo's recent commit. remove patch #28, #29, #31 in v4 based on comments. add reviewed-by/acked-by to patch #1-#19, #27, #29 v4: code polishing and minor fixes. v3: move all of the per instance variables from struct amdgpu_vcn to struct amdgpu_vcn_inst. (patch 10 - 11) update amdgpu_device_ip_set_powergating_state() to take the instance as a new parameter, remove the duplicated function in v2. (patch 19) update all amdgpu_vcn_* helpers to handle vcn instance. All functions are now only handle the given vcn instance. (patch 20 - 26) update all vcn ip callback functions to handle vcn instance. All functions are now only handle the given vcn instance. (patch 27 - 32) v2: complete re-work for all PM changes as suggested-by Christian König and Alex Deucher. Adding instance to all existing functions, instead of create new functions. Remove all duplicated PM functions in previous patch set. Use a new logic to track instance for ip_block with same type as suggested by Alex. Also, fix wrong ip block index and remove redundant logic suggested by Christian. Finally rebase all patches based on Sunil's ip block changes. Previously, all vcn instance will be powered on/off at the same time even only one of the instance requests power status change. This patch set enables vcn to ONLY power on/off the instance that requires power status change. Other vcn instances will remain the original power status. Boyuan Zhang (29): drm/amd/pm: add inst to dpm_set_vcn_enable drm/amd/pm: power up or down vcn by instance drm/amd/pm: add inst to smu_dpm_set_vcn_enable drm/amd/pm: add inst to set_powergating_by_smu drm/amd/pm: add inst to dpm_set_powergating_by_smu drm/amdgpu: add inst to amdgpu_dpm_enable_vcn drm/amdgpu: pass ip_block in set_powergating_state drm/amdgpu: pass ip_block in set_clockgating_state drm/amdgpu: track instances of the same IP block drm/amdgpu: move per inst variables to amdgpu_vcn_inst drm/amdgpu/vcn: separate gating state by instance drm/amdgpu: power vcn 2_5 by instance drm/amdgpu: power vcn 3_0 by instance drm/amdgpu: power vcn 4_0 by instance drm/amdgpu: power vcn 4_0_3 by instance drm/amdgpu: power vcn 4_0_5 by instance drm/amdgpu: power vcn 5_0_0 by instance drm/amdgpu/vcn: separate idle work by instance drm/amdgpu: set powergating state by vcn instance drm/amdgpu: early_init for each vcn instance drm/amdgpu: sw_init for each vcn instance drm/amdgpu: sw_fini for each vcn instance drm/amdgpu: hw_init for each vcn instance drm/amdgpu: suspend for each vcn instance drm/amdgpu: resume for each vcn instance drm/amdgpu: setup_ucode for each vcn instance drm/amdgpu: set funcs for each vcn instance drm/amdgpu: wait_for_idle for each vcn instance drm/amdgpu: set_powergating for each vcn instance drivers/gpu/drm/amd/amdgpu/amdgpu.h |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 20 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c|4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 41 +- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 24 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 13 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 341 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 26 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c |4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 14 +- drivers/gpu/drm/amd/amdgpu/cik.c |4 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c |4 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c |6 +- drivers/gpu/drm/amd/amdgpu/cz_ih.c|4 +- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c|4 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c|4 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c |4 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c |4 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 12 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c|8 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c|8 +- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |8 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c |8 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |8 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c |6 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c|6 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c|6 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c|6 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
Re: [PATCH 00/32] Separating vcn power management by instance
On 2024-10-22 02:25, Christian König wrote: Patches #1-#5, #7, #8, #32 are Acked-by: Christian König Added Acked-by, and ready to be submitted. Patches #9 - #19, #27 are Reviewed-by: Christian König Added Reviewed-by, and ready to be submitted. Patch #6 the drm/amdgpu prefix is missing from the subject line, apart from that the patch is Reviewed-by: Christian König Fixed in new patch-set just submitted (patch 06/29), and added Reviewed-by. For patches #20-#26 I'm not sure if those won't break the driver in between. Alex what do you think? Need Alex's input. Patches #28 and #29 look good to me as well, but I leave the review to Sunil he wrote that code and should know it best. Patches #28 and #29 has been dropped in the new patch set based on discussion with Sunil, will be submitted later on once his work is done. Patch #30: + int ret = 0; ... + ret = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE, That will get you a warning for an unneeded local variable initialization from the automated checkers. The init was only necessary because we previously had the loop over all instances here. Fixed in new patch-set just submitted (patch 28/29) Patch #31: int inst = ip_block->instance; int ret = 1; if (adev->vcn.harvest_config & (1 << inst)) return ret; ret &= (RREG32_SOC15(VCN, inst, mmUVD_STATUS) == UVD_STATUS__IDLE); return ret; That code looks really strange now, maybe drop the local variable ret. Patch #31 has been dropped in the new patch set based on discussion with Sunil, will be submitted later on once his work is done. Regards, Christian Am 17.10.24 um 15:20 schrieb boyuan.zh...@amd.com: From: Boyuan Zhang Previously, all vcn instance will be powered on/off at the same time even only one of the instance requests power status change. This patch set enables vcn to ONLY power on/off the instance that requires power status change. Other vcn instances will remain the original power status. v4: code polishing and minor fixes. v3: move all of the per instance variables from struct amdgpu_vcn to struct amdgpu_vcn_inst. (patch 10 - 11) update amdgpu_device_ip_set_powergating_state() to take the instance as a new parameter, remove the duplicated function in v2. (patch 19) update all amdgpu_vcn_* helpers to handle vcn instance. All functions are now only handle the given vcn instance. (patch 20 - 26) update all vcn ip callback functions to handle vcn instance. All functions are now only handle the given vcn instance. (patch 27 - 32) v2: complete re-work for all PM changes as suggested-by Christian König and Alex Deucher. Adding instance to all existing functions, instead of create new functions. Remove all duplicated PM functions in previous patch set. Use a new logic to track instance for ip_block with same type as suggested by Alex. Also, fix wrong ip block index and remove redundant logic suggested by Christian. Finally rebase all patches based on Sunil's ip block changes. Patch 1-6 are SMU changes to only power ON/OFF given VCN instance. Patch 7-8 pass ip_block instead of adev pointer for set_powergating_state, set_clockgating_state, and is_idle Patch 9 is to track VCN instance in VCN ip_block. Patch 10 move all of the per instance variables from struct amdgpu_vcn to struct amdgpu_vcn_inst. Patch 11 VCN change to separate gating status for each VCN instance. Patch 12-17 are to handle ip callback functions separately for each VCN instance, so that only the given instance will be powered on/off. Patch 18 is VCN change to handle idle work separately for each VCN instance. Patch 19 is to set powergating state by VCN instance in amdgpu_vcn. Patch 20-26 update all amdgpu_vcn_* helpers to handle vcn instance. All functions are now only handle the given vcn instance. Patch 27-32 update all vcn ip callback functions to handle vcn instance. All functions are now only handle the given vcn instance. Boyuan Zhang (32): drm/amd/pm: add inst to dpm_set_vcn_enable drm/amd/pm: power up or down vcn by instance drm/amd/pm: add inst to smu_dpm_set_vcn_enable drm/amd/pm: add inst to set_powergating_by_smu drm/amd/pm: add inst to dpm_set_powergating_by_smu add inst to amdgpu_dpm_enable_vcn drm/amdgpu: pass ip_block in set_powergating_state drm/amdgpu: pass ip_block in set_clockgating_state drm/amdgpu: track instances of the same IP block drm/amdgpu: move per inst variables to amdgpu_vcn_inst drm/amdgpu/vcn: separate gating state by instance drm/amdgpu: power vcn 2_5 by instance drm/amdgpu: power vcn 3_0 by instance drm/amdgpu: power vcn 4_0 by instance drm/amdgpu: power vcn 4_0_3 by instance drm/amdgpu: power vcn 4_0_5 by instance drm/amdgpu: power vcn 5_0_0 by instance drm/amdgpu/vcn: separate idle work by instance drm/amdgpu: set powergating state by vcn instance drm/amdgpu: early_init for each vcn instance drm/amdgpu: sw_init
[PATCH V3 3/5] drm/amdgpu: Add sysfs interface for vcn reset mask
From: "jesse.zh...@amd.com"
Add the sysfs interface for vcn:
vcn_reset_mask
The interface is read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.
V2: the sysfs node returns a text string instead of some flags (Christian)
V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
and print the strings in the order they are applied (Christian)
check amdgpu_gpu_recovery before creating sysfs file itself,
and initialize supported_reset_types in IP version files (Lijo)
Signed-off-by: Jesse Zhang
Suggested-by:Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 35 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++
5 files changed, 65 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 43f44cc201cb..9bbae298189a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -1277,3 +1277,38 @@ int amdgpu_vcn_psp_update_sram(struct amdgpu_device
*adev, int inst_idx,
return psp_execute_ip_fw_load(&adev->psp, &ucode);
}
+
+static ssize_t amdgpu_get_vcn_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->vcn.supported_reset);
+}
+
+static DEVICE_ATTR(vcn_reset_mask, 0444,
+ amdgpu_get_vcn_reset_mask, NULL);
+
+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (adev->vcn.num_vcn_inst) {
+ r = device_create_file(adev->dev, &dev_attr_vcn_reset_mask);
+ if (r)
+ return r;
+ }
+
+ return r;
+}
+
+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev)
+{
+ if (adev->vcn.num_vcn_inst)
+ device_remove_file(adev->dev, &dev_attr_vcn_reset_mask);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2a1f3dbb14d3..904336ff0b39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -333,6 +333,8 @@ struct amdgpu_vcn {
/* IP reg dump */
uint32_t*ip_dump;
+
+ uint32_tsupported_reset;
};
struct amdgpu_fw_shared_rb_ptrs_struct {
@@ -518,5 +520,7 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
enum AMDGPU_UCODE_ID ucode_id);
+int amdgpu_vcn_sysfs_reset_mask_init(struct amdgpu_device *adev);
+void amdgpu_vcn_sysfs_reset_mask_fini(struct amdgpu_device *adev);
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index e7b7a8150ea7..9c84cfe9ea43 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -225,6 +225,10 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
vcn_v4_0_fw_shared_init(adev, i);
}
+ /* TODO: Check the version that supports queue reset */
+ adev->sdma.supported_reset |=
+
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]);
+
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -247,6 +251,10 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
adev->vcn.ip_dump = ptr;
}
+ r = amdgpu_vcn_sysfs_reset_mask_init(adev);
+ if (r)
+ return r;
+
return 0;
}
@@ -284,6 +292,7 @@ static int vcn_v4_0_sw_fini(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
+ amdgpu_vcn_sysfs_reset_mask_fini(adev);
r = amdgpu_vcn_sw_fini(adev);
kfree(adev->vcn.ip_dump);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 6dcae398b2dc..1887a15b7d69 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -180,6 +180,10 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
}
+ /* TODO: Check the version that supports queue reset ? */
+ adev->sdma.supported_reset |=
+
amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ri
[PATCH V3 4/5] drm/amdgpu: Add sysfs interface for vpe reset mask
From: "jesse.zh...@amd.com"
Add the sysfs interface for vpe:
vpe_reset_mask
The interface is read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.
V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
and print the strings in the order they are applied (Christian)
check amdgpu_gpu_recovery before creating sysfs file itself,
and initialize supported_reset_types in IP version files (Lijo)
Signed-off-by: Jesse Zhang
Suggested-by:Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 43 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h | 3 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index 6d96e1f21e20..44213634e236 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -377,6 +377,13 @@ static int vpe_sw_init(struct amdgpu_ip_block *ip_block)
ret = vpe_init_microcode(vpe);
if (ret)
goto out;
+
+ /* TODO: Check the version that supports queue reset */
+ adev->vpe.supported_reset |=
+amdgpu_get_soft_full_reset_mask(&adev->vpe.ring);
+ ret = amdgpu_vpe_sysfs_reset_mask_init(adev);
+ if (ret)
+ goto out;
out:
return ret;
}
@@ -389,6 +396,7 @@ static int vpe_sw_fini(struct amdgpu_ip_block *ip_block)
release_firmware(vpe->fw);
vpe->fw = NULL;
+ amdgpu_vpe_sysfs_reset_mask_fini(adev);
vpe_ring_fini(vpe);
amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,
@@ -865,6 +873,41 @@ static void vpe_ring_end_use(struct amdgpu_ring *ring)
schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
}
+static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset);
+}
+
+static DEVICE_ATTR(vpe_reset_mask, 0444,
+ amdgpu_get_vpe_reset_mask, NULL);
+
+int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (adev->vpe.num_instances) {
+ r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask);
+ if (r)
+ return r;
+ }
+
+ return r;
+}
+
+void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev)
+{
+ if (adev->vpe.num_instances)
+ device_remove_file(adev->dev, &dev_attr_vpe_reset_mask);
+}
+
static const struct amdgpu_ring_funcs vpe_ring_funcs = {
.type = AMDGPU_RING_TYPE_VPE,
.align_mask = 0xf,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
index 231d86d0953e..695da740a97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.h
@@ -79,6 +79,7 @@ struct amdgpu_vpe {
uint32_tnum_instances;
boolcollaborate_mode;
+ uint32_tsupported_reset;
};
int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev);
@@ -86,6 +87,8 @@ int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe);
int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe);
int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe);
int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe);
+void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev);
+int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev);
#define vpe_ring_init(vpe) ((vpe)->funcs->ring_init ?
(vpe)->funcs->ring_init((vpe)) : 0)
#define vpe_ring_start(vpe) ((vpe)->funcs->ring_start ?
(vpe)->funcs->ring_start((vpe)) : 0)
--
2.25.1
[PATCH v2] drm/amd/pm: correct the workload setting
Correct the workload setting in order not to mix the setting
with the end user. Update the workload mask accordingly.
v2: changes as below:
1. the end user can not erase the workload from driver except default workload.
2. always shows the real highest priority workoad to the end user.
3. the real workload mask is combined with driver workload mask and end user
workload mask.
Signed-off-by: Kenneth Feng
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 44 +--
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 5 ++-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 31 +++--
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 25 +--
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 28 +---
5 files changed, 106 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 8d4aee4e2287..1de576461a70 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1261,25 +1261,31 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
smu->watermarks_bitmap = 0;
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
+ smu->user_dpm_profile.user_workload_mask = 0;
+ smu->user_dpm_profile.prev_user_workload_mask = 0;
atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
- smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
- smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
- smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
- smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
- smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
- smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
- smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_VR] = 4;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
+ smu->workload_priority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
if (smu->is_apu ||
- !smu_is_workload_profile_available(smu,
PP_SMC_POWER_PROFILE_FULLSCREEN3D))
- smu->workload_mask = 1 <<
smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
- else
- smu->workload_mask = 1 <<
smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
+ !smu_is_workload_profile_available(smu,
PP_SMC_POWER_PROFILE_FULLSCREEN3D)) {
+ smu->workload_mask = 1 <<
smu->workload_priority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
+ } else {
+ smu->workload_mask = 1 <<
smu->workload_priority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
+ smu->default_power_profile_mode =
PP_SMC_POWER_PROFILE_FULLSCREEN3D;
+ }
+
+ smu->driver_workload_mask = smu->workload_mask;
smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
@@ -2354,12 +2360,14 @@ static int smu_switch_power_profile(void *handle,
return -EINVAL;
if (!en) {
- smu->workload_mask &= ~(1 << smu->workload_prority[type]);
+ smu->workload_mask &= ~(1 << smu->workload_priority[type]);
+ smu->driver_workload_mask &= ~(1 <<
smu->workload_priority[type]);
index = fls(smu->workload_mask);
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 :
0;
workload[0] = smu->workload_setting[index];
} else {
- smu->workload_mask |= (1 << smu->workload_prority[type]);
+ smu->workload_mask |= (1 << smu->workload_priority[type]);
+ smu->driver_workload_mask |= (1 <<
smu->workload_priority[type]);
index = fls(smu->workload_mask);
index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
workload[0] = smu->workload_setting[index];
@@ -3054,12 +3062,20 @@ static int smu_set_power_profile_mode(void *handle,
uint32_t param_size)
{
struct smu_context *smu = handle;
+ int ret;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
!smu->ppt_funcs->set_power_profile_mode)
return -EOPNOTSUPP;
- return smu_bump_power_profile_mode(smu, param, param_size);
+ smu->user_dpm_profile.prev_user_workload_mask
[RFC 4/4] drm/amdgpu: Expose special on chip memory pools in fdinfo
From: Tvrtko Ursulin
In the past these specialized on chip memory pools were reported as system
memory (aka 'cpu') which was not correct and misleading. That has since
been removed so lets make them visible as their own respective memory
regions.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Yunxiang Li
Cc: Alex Deucher
---
It is easy to do but is it worth it I leave to AMD experts to decide.
I gave it a quick spin and have only seen all zeros when running a Steam
game.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
index 7a9573958d87..df2cf5c33925 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c
@@ -66,6 +66,10 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct
drm_file *file)
[TTM_PL_VRAM] = "vram",
[TTM_PL_TT] = "gtt",
[TTM_PL_SYSTEM] = "cpu",
+ [AMDGPU_PL_GDS] = "gds",
+ [AMDGPU_PL_GWS] = "gws",
+ [AMDGPU_PL_OA] = "oa",
+ [AMDGPU_PL_DOORBELL] = "doorbell",
};
unsigned int hw_ip, i;
int ret;
@@ -87,12 +91,16 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct
drm_file *file)
drm_printf(p, "pasid:\t%u\n", fpriv->vm.pasid);
- for (i = 0; i < TTM_PL_PRIV; i++)
+ for (i = 0; i < ARRAY_SIZE(pl_name); i++) {
+ if (!pl_name[i])
+ continue;
+
drm_print_memory_stats(p,
&stats[i].drm,
DRM_GEM_OBJECT_RESIDENT |
DRM_GEM_OBJECT_PURGEABLE,
pl_name[i]);
+ }
/* Legacy amdgpu keys, alias to drm-resident-memory-: */
drm_printf(p, "drm-memory-vram:\t%llu KiB\n",
--
2.46.0
Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
On 10/24/2024 12:49 PM, Lazar, Lijo wrote:
>
>
> On 10/24/2024 12:23 PM, Liang, Prike wrote:
>> [AMD Official Use Only - AMD Internal Distribution Only]
>>
>>> From: Lazar, Lijo
>>> Sent: Thursday, October 24, 2024 11:39 AM
>>> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
>>> Cc: Deucher, Alexander
>>> Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
>>>
>>>
>>>
>>> On 10/24/2024 8:24 AM, Liang, Prike wrote:
[Public]
> From: Lazar, Lijo
> Sent: Wednesday, October 23, 2024 6:55 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
>
>
>
> On 10/14/2024 1:19 PM, Prike Liang wrote:
>> To check the status of S3 suspend completion, use the PM core
>> pm_suspend_global_flags bit(1) to detect S3 abort events. Therefore,
>> clean up the AMDGPU driver's private flag suspend_complete.
>>
>> Signed-off-by: Prike Liang
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
>> 5 files changed, 5 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 48c9b9b06905..9b35763ae0a7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -,8 +,6 @@ struct amdgpu_device {
>> boolin_s3;
>> boolin_s4;
>> boolin_s0ix;
>> - /* indicate amdgpu suspension status */
>> - boolsuspend_complete;
>>
>> enum pp_mp1_state mp1_state;
>> struct amdgpu_doorbell_index doorbell_index; diff --git
>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 680e44fdee6e..78972151b970 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -2501,7 +2501,6 @@ static int amdgpu_pmops_suspend(struct device
>>> *dev)
>> struct drm_device *drm_dev = dev_get_drvdata(dev);
>> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>>
>> - adev->suspend_complete = false;
>> if (amdgpu_acpi_is_s0ix_active(adev))
>> adev->in_s0ix = true;
>> else if (amdgpu_acpi_is_s3_active(adev)) @@ -2516,7 +2515,6 @@
>> static int amdgpu_pmops_suspend_noirq(struct device *dev)
>> struct drm_device *drm_dev = dev_get_drvdata(dev);
>> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>>
>> - adev->suspend_complete = true;
>> if (amdgpu_acpi_should_gpu_reset(adev))
>> return amdgpu_asic_reset(adev);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index be320d753507..ba8e66744376 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3276,8 +3276,8 @@ static int gfx_v9_0_cp_gfx_start(struct
>> amdgpu_device
> *adev)
>> * confirmed that the APU gfx10/gfx11 needn't such update.
>> */
>> if (adev->flags & AMD_IS_APU &&
>> - adev->in_s3 && !adev->suspend_complete) {
>> - DRM_INFO(" Will skip the CSB packet resubmit\n");
>> + adev->in_s3 && !pm_resume_via_firmware()) {
>> + DRM_INFO("Will skip the CSB packet resubmit\n");
>> return 0;
>> }
>> r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 +
>> 3); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index 12ff6cf568dc..d9d11131a744 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -584,13 +584,10 @@ static bool soc15_need_reset_on_resume(struct
> amdgpu_device *adev)
>> *performing pm core test.
>> */
>> if (adev->flags & AMD_IS_APU && adev->in_s3 &&
>> - !pm_resume_via_firmware()) {
>> - adev->suspend_complete = false;
>> + !pm_resume_via_firmware())
>> return true;
>> - } else {
>> - adev->suspend_complete = true;
>> + else
>> return false;
>> - }
>> }
>>
>> static int soc15_asic_reset(struct amdgpu_device *adev) diff --git
>> a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> index c4b950e75133..7a47a21ef00f 100644
>> --- a/drivers/
[PATCH v3 1/2] drm/amdgpu: correct the S3 abort check condition
In the normal S3 entry, the TOS cycle counter is not
reset during BIOS execution the _S3 method, so it doesn't
determine whether the _S3 method is executed exactly.
Howerver, the PM core performs the S3 suspend will set the
PM_SUSPEND_FLAG_FW_RESUME bit if all the devices suspend
successfully. Therefore, drivers can check the
pm_suspend_global_flags bit(1) to detect the S3 suspend
abort event.
Fixes: 4d58c599df75 ("drm/amdgpu: update suspend status
for aborting from deeper suspend")
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dd1c1aacdd8e..12ff6cf568dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -578,16 +578,13 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
{
- u32 sol_reg;
-
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-
/* Will reset for the following suspend abort cases.
-* 1) Only reset limit on APU side, dGPU hasn't checked yet.
-* 2) S3 suspend abort and TOS already launched.
+* 1) Only reset on APU side, dGPU hasn't checked yet.
+* 2) S3 suspend aborted in the normal S3 suspend or
+*performing pm core test.
*/
if (adev->flags & AMD_IS_APU && adev->in_s3 &&
- sol_reg) {
+ !pm_resume_via_firmware()) {
adev->suspend_complete = false;
return true;
} else {
@@ -603,11 +600,17 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
* successfully. So now, temporarily enable it for the
* S3 suspend abort case.
*/
- if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
- (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
- !soc15_need_reset_on_resume(adev))
+
+ if ((adev->apu_flags & AMD_APU_IS_PICASSO ||
+ !(adev->apu_flags & AMD_APU_IS_RAVEN)) &&
+ soc15_need_reset_on_resume(adev))
+ goto asic_reset;
+
+ if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
+ (adev->apu_flags & AMD_APU_IS_RAVEN2))
return 0;
+asic_reset:
switch (soc15_asic_reset_method(adev)) {
case AMD_RESET_METHOD_PCI:
dev_info(adev->dev, "PCI reset\n");
--
2.34.1
RE: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
[AMD Official Use Only - AMD Internal Distribution Only]
> From: Lazar, Lijo
> Sent: Thursday, October 24, 2024 3:30 PM
> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
>
>
>
> On 10/24/2024 12:49 PM, Lazar, Lijo wrote:
> >
> >
> > On 10/24/2024 12:23 PM, Liang, Prike wrote:
> >> [AMD Official Use Only - AMD Internal Distribution Only]
> >>
> >>> From: Lazar, Lijo
> >>> Sent: Thursday, October 24, 2024 11:39 AM
> >>> To: Liang, Prike ;
> >>> amd-gfx@lists.freedesktop.org
> >>> Cc: Deucher, Alexander
> >>> Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the
> >>> suspend_complete
> >>>
> >>>
> >>>
> >>> On 10/24/2024 8:24 AM, Liang, Prike wrote:
> [Public]
>
> > From: Lazar, Lijo
> > Sent: Wednesday, October 23, 2024 6:55 PM
> > To: Liang, Prike ;
> > amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander
> > Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the
> > suspend_complete
> >
> >
> >
> > On 10/14/2024 1:19 PM, Prike Liang wrote:
> >> To check the status of S3 suspend completion, use the PM core
> >> pm_suspend_global_flags bit(1) to detect S3 abort events.
> >> Therefore, clean up the AMDGPU driver's private flag suspend_complete.
> >>
> >> Signed-off-by: Prike Liang
> >> ---
> >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
> >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> >> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> >> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
> >> drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
> >> 5 files changed, 5 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> index 48c9b9b06905..9b35763ae0a7 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> >> @@ -,8 +,6 @@ struct amdgpu_device {
> >> boolin_s3;
> >> boolin_s4;
> >> boolin_s0ix;
> >> - /* indicate amdgpu suspension status */
> >> - boolsuspend_complete;
> >>
> >> enum pp_mp1_state mp1_state;
> >> struct amdgpu_doorbell_index doorbell_index; diff --git
> >> a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> index 680e44fdee6e..78972151b970 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> @@ -2501,7 +2501,6 @@ static int amdgpu_pmops_suspend(struct
> >> device
> >>> *dev)
> >> struct drm_device *drm_dev = dev_get_drvdata(dev);
> >> struct amdgpu_device *adev = drm_to_adev(drm_dev);
> >>
> >> - adev->suspend_complete = false;
> >> if (amdgpu_acpi_is_s0ix_active(adev))
> >> adev->in_s0ix = true;
> >> else if (amdgpu_acpi_is_s3_active(adev)) @@ -2516,7 +2515,6
> >> @@ static int amdgpu_pmops_suspend_noirq(struct device *dev)
> >> struct drm_device *drm_dev = dev_get_drvdata(dev);
> >> struct amdgpu_device *adev = drm_to_adev(drm_dev);
> >>
> >> - adev->suspend_complete = true;
> >> if (amdgpu_acpi_should_gpu_reset(adev))
> >> return amdgpu_asic_reset(adev);
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> index be320d753507..ba8e66744376 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >> @@ -3276,8 +3276,8 @@ static int gfx_v9_0_cp_gfx_start(struct
> >> amdgpu_device
> > *adev)
> >> * confirmed that the APU gfx10/gfx11 needn't such update.
> >> */
> >> if (adev->flags & AMD_IS_APU &&
> >> - adev->in_s3 && !adev->suspend_complete) {
> >> - DRM_INFO(" Will skip the CSB packet resubmit\n");
> >> + adev->in_s3 && !pm_resume_via_firmware()) {
> >> + DRM_INFO("Will skip the CSB packet resubmit\n");
> >> return 0;
> >> }
> >> r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 +
> >> 3); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> >> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> >> index 12ff6cf568dc..d9d11131a744 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> >> @@ -584,13 +584,10 @@ static bool
> >> soc15_need_reset_on_resume(struct
> > amdgpu_device *adev)
> >> *performing pm core test.
> >> */
> >> if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> >> - !pm_resume_via_firmw
[PATCH V3 5/5] drm/amdgpu: Add sysfs interface for jpeg reset mask
From: "jesse.zh...@amd.com"
Add the sysfs interface for jpeg:
jpeg_reset_mask
The interface is read-only and show the resets supported by the IP.
For example, full adapter reset (mode1/mode2/BACO/etc),
soft reset, queue reset, and pipe reset.
V2: the sysfs node returns a text string instead of some flags (Christian)
v3: add a generic helper which takes the ring as parameter
and print the strings in the order they are applied (Christian)
check amdgpu_gpu_recovery before creating sysfs file itself,
and initialize supported_reset_types in IP version files (Lijo)
Signed-off-by: Jesse Zhang
Suggested-by:Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 35
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 3 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 7 +
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 7 +
6 files changed, 68 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index 95e2796919fc..f971ffdffce9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -415,3 +415,38 @@ void amdgpu_debugfs_jpeg_sched_mask_init(struct
amdgpu_device *adev)
&amdgpu_debugfs_jpeg_sched_mask_fops);
#endif
}
+
+static ssize_t amdgpu_get_jpeg_reset_mask(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ if (!adev)
+ return -ENODEV;
+
+ return amdgpu_show_reset_mask(buf, adev->jpeg.supported_reset);
+}
+
+static DEVICE_ATTR(jpeg_reset_mask, 0444,
+ amdgpu_get_jpeg_reset_mask, NULL);
+
+int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev)
+{
+ int r = 0;
+
+ if (adev->jpeg.num_jpeg_inst) {
+ r = device_create_file(adev->dev, &dev_attr_jpeg_reset_mask);
+ if (r)
+ return r;
+ }
+
+ return r;
+}
+
+void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev)
+{
+ if (adev->jpeg.num_jpeg_inst)
+ device_remove_file(adev->dev, &dev_attr_jpeg_reset_mask);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index 819dc7a0af99..3eb4a4653fce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -128,6 +128,7 @@ struct amdgpu_jpeg {
uint16_t inst_mask;
uint8_t num_inst_per_aid;
boolindirect_sram;
+ uint32_t supported_reset;
};
int amdgpu_jpeg_sw_init(struct amdgpu_device *adev);
@@ -150,5 +151,7 @@ int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,
enum AMDGPU_UCODE_ID ucode_id);
void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);
+int amdgpu_jpeg_sysfs_reset_mask_init(struct amdgpu_device *adev);
+void amdgpu_jpeg_sysfs_reset_mask_fini(struct amdgpu_device *adev);
#endif /*__AMDGPU_JPEG_H__*/
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 20e1fe89c463..d1ee342d91e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -121,6 +121,12 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block
*ip_block)
adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0,
regUVD_JPEG_PITCH);
r = amdgpu_jpeg_ras_sw_init(adev);
+ if (r)
+ return r;
+ /* TODO: Check the version that supports queue reset */
+ adev->jpeg.supported_reset |=
+
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
+ r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
if (r)
return r;
@@ -143,6 +149,7 @@ static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block
*ip_block)
if (r)
return r;
+ amdgpu_jpeg_sysfs_reset_mask_fini(adev);
r = amdgpu_jpeg_sw_fini(adev);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 2a53537db135..8c673fe71e5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -159,6 +159,13 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block
*ip_block)
}
}
+ /* TODO: Check the version that supports queue reset */
+ adev->jpeg.supported_reset |=
+
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
+ r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
+ if (r)
+ retur
Re: [PATCH] drm/amdgpu: skip pci_restore_state under sriov during device init
On 10/24/2024 11:19 AM, Victor Zhao wrote: > during device init, under sriov, pci_restore_state happens after > fullaccess released, and it can have race condition with mmio protection > enable from host side. > > Since msix was toggled during pci_restore_state, if mmio protection > happens during this time, guest side msix will not be properly > programmed and leading to missing interrupts. > > So skip pci_restore_state during device init. > > Signed-off-by: Victor Zhao > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 6c0ff1c2ae4c..52803cd91ef5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -4524,7 +4524,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, > dev_err(adev->dev, "amdgpu_pmu_init failed\n"); > > /* Have stored pci confspace at hand for restore in sudden PCI error */ > - if (amdgpu_device_cache_pci_state(adev->pdev)) > + if (!amdgpu_sriov_vf(adev) && amdgpu_device_cache_pci_state(adev->pdev)) This also prevents caching the state. If the intention is that way, put the check inside amdgpu_device_cache_pci_state to make it explicit that VFs avoid caching config space. Thanks, Lijo > pci_restore_state(pdev); > > /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
On 10/24/2024 12:23 PM, Liang, Prike wrote:
> [AMD Official Use Only - AMD Internal Distribution Only]
>
>> From: Lazar, Lijo
>> Sent: Thursday, October 24, 2024 11:39 AM
>> To: Liang, Prike ; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander
>> Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
>>
>>
>>
>> On 10/24/2024 8:24 AM, Liang, Prike wrote:
>>> [Public]
>>>
From: Lazar, Lijo
Sent: Wednesday, October 23, 2024 6:55 PM
To: Liang, Prike ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH v2 2/2] drm/amdgpu: clean up the suspend_complete
On 10/14/2024 1:19 PM, Prike Liang wrote:
> To check the status of S3 suspend completion, use the PM core
> pm_suspend_global_flags bit(1) to detect S3 abort events. Therefore,
> clean up the AMDGPU driver's private flag suspend_complete.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 --
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++-
> drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +-
> 5 files changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 48c9b9b06905..9b35763ae0a7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -,8 +,6 @@ struct amdgpu_device {
> boolin_s3;
> boolin_s4;
> boolin_s0ix;
> - /* indicate amdgpu suspension status */
> - boolsuspend_complete;
>
> enum pp_mp1_state mp1_state;
> struct amdgpu_doorbell_index doorbell_index; diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 680e44fdee6e..78972151b970 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2501,7 +2501,6 @@ static int amdgpu_pmops_suspend(struct device
>> *dev)
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>
> - adev->suspend_complete = false;
> if (amdgpu_acpi_is_s0ix_active(adev))
> adev->in_s0ix = true;
> else if (amdgpu_acpi_is_s3_active(adev)) @@ -2516,7 +2515,6 @@
> static int amdgpu_pmops_suspend_noirq(struct device *dev)
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct amdgpu_device *adev = drm_to_adev(drm_dev);
>
> - adev->suspend_complete = true;
> if (amdgpu_acpi_should_gpu_reset(adev))
> return amdgpu_asic_reset(adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index be320d753507..ba8e66744376 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3276,8 +3276,8 @@ static int gfx_v9_0_cp_gfx_start(struct
> amdgpu_device
*adev)
> * confirmed that the APU gfx10/gfx11 needn't such update.
> */
> if (adev->flags & AMD_IS_APU &&
> - adev->in_s3 && !adev->suspend_complete) {
> - DRM_INFO(" Will skip the CSB packet resubmit\n");
> + adev->in_s3 && !pm_resume_via_firmware()) {
> + DRM_INFO("Will skip the CSB packet resubmit\n");
> return 0;
> }
> r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 +
> 3); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 12ff6cf568dc..d9d11131a744 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -584,13 +584,10 @@ static bool soc15_need_reset_on_resume(struct
amdgpu_device *adev)
> *performing pm core test.
> */
> if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> - !pm_resume_via_firmware()) {
> - adev->suspend_complete = false;
> + !pm_resume_via_firmware())
> return true;
> - } else {
> - adev->suspend_complete = true;
> + else
> return false;
> - }
> }
>
> static int soc15_asic_reset(struct amdgpu_device *adev) diff --git
> a/drivers/gpu/drm/amd/amdgpu/soc21.c
> b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index c4b950e75133..7a47a21ef00f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -904,7 +904,7 @@ static bool soc21_need_reset_on_resume(struct
amdgpu_device
