RE: [PATCH 1/4] drm/amd/pm: Use separate metric table for APU
[AMD Official Use Only - General]
Series is Reviewed-by: Le Ma
> -Original Message-
> From: Kamal, Asad
> Sent: Friday, December 22, 2023 11:27 PM
> To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
> Cc: Zhang, Hawking ; Ma, Le ;
> Zhang, Morris ; Oliveira, Daniel
> ; Cheung, Donald ;
> Khatir, Sepehr ; Kamal, Asad
> Subject: [PATCH 1/4] drm/amd/pm: Use separate metric table for APU
>
> Use separate metric table for APU and Non APU systems for smu_v_13_0_6 to
> get metric data
>
> Signed-off-by: Asad Kamal
> Reviewed-by: Lijo Lazar
> ---
> .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 90 -
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 124 ++
> 2 files changed, 156 insertions(+), 58 deletions(-)
>
> diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
> b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
> index fef2d290f3f2..8f166aa3043c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
> @@ -219,7 +219,95 @@ typedef struct __attribute__((packed, aligned(4))) {
>uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is
> accumulated
>uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is
> accumulated
>uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is
> accumulated
> -} MetricsTable_t;
> +} MetricsTableX_t;
> +
> +typedef struct __attribute__((packed, aligned(4))) {
> + uint32_t AccumulationCounter;
> +
> + //TEMPERATURE
> + uint32_t MaxSocketTemperature;
> + uint32_t MaxVrTemperature;
> + uint32_t MaxHbmTemperature;
> + uint64_t MaxSocketTemperatureAcc;
> + uint64_t MaxVrTemperatureAcc;
> + uint64_t MaxHbmTemperatureAcc;
> +
> + //POWER
> + uint32_t SocketPowerLimit;
> + uint32_t MaxSocketPowerLimit;
> + uint32_t SocketPower;
> +
> + //ENERGY
> + uint64_t Timestamp;
> + uint64_t SocketEnergyAcc;
> + uint64_t CcdEnergyAcc;
> + uint64_t XcdEnergyAcc;
> + uint64_t AidEnergyAcc;
> + uint64_t HbmEnergyAcc;
> +
> + //FREQUENCY
> + uint32_t CclkFrequencyLimit;
> + uint32_t GfxclkFrequencyLimit;
> + uint32_t FclkFrequency;
> + uint32_t UclkFrequency;
> + uint32_t SocclkFrequency[4];
> + uint32_t VclkFrequency[4];
> + uint32_t DclkFrequency[4];
> + uint32_t LclkFrequency[4];
> + uint64_t GfxclkFrequencyAcc[8];
> + uint64_t CclkFrequencyAcc[96];
> +
> + //FREQUENCY RANGE
> + uint32_t MaxCclkFrequency;
> + uint32_t MinCclkFrequency;
> + uint32_t MaxGfxclkFrequency;
> + uint32_t MinGfxclkFrequency;
> + uint32_t FclkFrequencyTable[4];
> + uint32_t UclkFrequencyTable[4];
> + uint32_t SocclkFrequencyTable[4];
> + uint32_t VclkFrequencyTable[4];
> + uint32_t DclkFrequencyTable[4];
> + uint32_t LclkFrequencyTable[4];
> + uint32_t MaxLclkDpmRange;
> + uint32_t MinLclkDpmRange;
> +
> + //XGMI
> + uint32_t XgmiWidth;
> + uint32_t XgmiBitrate;
> + uint64_t XgmiReadBandwidthAcc[8];
> + uint64_t XgmiWriteBandwidthAcc[8];
> +
> + //ACTIVITY
> + uint32_t SocketC0Residency;
> + uint32_t SocketGfxBusy;
> + uint32_t DramBandwidthUtilization;
> + uint64_t SocketC0ResidencyAcc;
> + uint64_t SocketGfxBusyAcc;
> + uint64_t DramBandwidthAcc;
> + uint32_t MaxDramBandwidth;
> + uint64_t DramBandwidthUtilizationAcc; uint64_t PcieBandwidthAcc[4];
> +
> + //THROTTLERS
> + uint32_t ProchotResidencyAcc;
> + uint32_t PptResidencyAcc;
> + uint32_t SocketThmResidencyAcc;
> + uint32_t VrThmResidencyAcc;
> + uint32_t HbmThmResidencyAcc;
> + uint32_t GfxLockXCDMak;
> +
> + // New Items at end to maintain driver compatibility uint32_t
> + GfxclkFrequency[8];
> +
> + //PSNs
> + uint64_t PublicSerialNumber_AID[4];
> + uint64_t PublicSerialNumber_XCD[8];
> + uint64_t PublicSerialNumber_CCD[12];
> +
> + //XGMI Data tranfser size
> + uint64_t XgmiReadDataSizeAcc[8];//in KByte
> + uint64_t XgmiWriteDataSizeAcc[8];//in KByte } MetricsTableA_t;
>
> #define SMU_VF_METRICS_TABLE_VERSION 0x3
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 81b217bbdebb..96777a365133 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -248,6 +248,8 @@ struct PPTable_t {
> #define SMUQ10_TO_UINT(x) ((x) >> 10)
> #define SMUQ10_FRAC(x) ((x) & 0x3ff)
> #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >=
> 0x200))
> +#define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\
> + (metrics_a->field) : (metrics_x->field))
>
> struct smu_v13_0_6_dpm_map {
> enum smu_clk_type clk_type;
> @@ -330,7 +332,8 @@ static int smu_v13_0_6_tables_init(struct smu_context
> *smu)
> SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG,
> SMU13_TOOL_SIZE,
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> - SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
> sizeof
Re: [PATCH] drm/amd/display: avoid stringop-overflow warnings for dp_decide_lane_settings()
On 11/22/23 14:13, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> gcc prints a warning about a possible array overflow for a couple of
> callers of dp_decide_lane_settings() after commit 1b56c90018f0 ("Makefile:
> Enable -Wstringop-overflow globally"):
>
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:
> In function 'dp_perform_fixed_vs_pe_training_sequence_legacy':
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25:
> error: 'dp_decide_lane_settings' accessing 4 bytes in a region of size 1
> [-Werror=stringop-overflow=]
> 426 | dp_decide_lane_settings(lt_settings,
> dpcd_lane_adjust,
> |
> ^~
> 427 |
> lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
> |
> ~~~
> drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25:
> note: referencing argument 4 of type 'union dpcd_training_lane[4]'
>
> I'm not entirely sure what caused this, but changing the prototype to expect
> a pointer instead of an array avoids the warnings.
>
> Fixes: 7727e7b60f82 ("drm/amd/display: Improve robustness of FIXED_VS link
> training at DP1 rates")
> Signed-off-by: Arnd Bergmann
Acked-by: Randy Dunlap
Tested-by: Randy Dunlap # build-tested
Thanks.
> ---
> .../gpu/drm/amd/display/dc/link/protocols/link_dp_training.c| 2 +-
> .../gpu/drm/amd/display/dc/link/protocols/link_dp_training.h| 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
> b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
> index 90339c2dfd84..5a0b04518956 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
> @@ -807,7 +807,7 @@ void dp_decide_lane_settings(
> const struct link_training_settings *lt_settings,
> const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
> struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
> - union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
> + union dpcd_training_lane *dpcd_lane_settings)
> {
> uint32_t lane;
>
> diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
> b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
> index 7d027bac8255..851bd17317a0 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
> +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h
> @@ -111,7 +111,7 @@ void dp_decide_lane_settings(
> const struct link_training_settings *lt_settings,
> const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
> struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
> - union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
> + union dpcd_training_lane *dpcd_lane_settings);
>
> enum dc_dp_training_pattern decide_cr_training_pattern(
> const struct dc_link_settings *link_settings);
--
#Randy
https://people.kernel.org/tglx/notes-about-netiquette
https://subspace.kernel.org/etiquette.html
[PATCH] drm/amd/pm/smu7: fix a memleak in smu7_hwmgr_backend_init
The hwmgr->backend, (i.e. data) allocated by kzalloc is not freed in
the error-handling paths of smu7_get_evv_voltages and
smu7_update_edc_leakage_table. However, it did be freed in the
error-handling of phm_initializa_dynamic_state_adjustment_rule_settings,
by smu7_hwmgr_backend_fini. So the lack of free in smu7_get_evv_voltages
and smu7_update_edc_leakage_table is considered a memleak in this patch.
Fixes: 599a7e9fe1b6 ("drm/amd/powerplay: implement smu7 hwmgr to manager asics
with smu ip version 7.")
Fixes: 8f0804c6b7d0 ("drm/amd/pm: add edc leakage controller setting")
Signed-off-by: Zhipeng Lu
---
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 11372fcc59c8..b1a8799e2dee 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -2974,6 +2974,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
result = smu7_get_evv_voltages(hwmgr);
if (result) {
pr_info("Get EVV Voltage Failed. Abort Driver
loading!\n");
+ kfree(hwmgr->backend);
+ hwmgr->backend = NULL;
return -EINVAL;
}
} else {
@@ -3019,8 +3021,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr
*hwmgr)
}
result = smu7_update_edc_leakage_table(hwmgr);
- if (result)
+ if (result) {
+ smu7_hwmgr_backend_fini(hwmgr);
return result;
+ }
return 0;
}
--
2.34.1
[PATCH AUTOSEL 6.6 32/39] drm/amdkfd: svm range always mapped flag not working on APU
From: Philip Yang
[ Upstream commit ebab8c3eb6a6515dc14cd93fc29dd287709da6d3 ]
On gfx943 APU there is no VRAM and page migration, queue CWSR area, svm
range with always mapped flag, is not mapped to GPU correctly. This
works fine if retry fault on CWSR area can be recovered, but could cause
deadlock if there is another retry fault recover waiting for CWSR to
finish.
Fix this by mapping svm range with always mapped flag to GPU with ACCESS
attribute if XNACK ON.
There is side effect, because all GPUs have ACCESS attribute by default
on new svm range with XNACK on, the CWSR area will be mapped to all GPUs
after this change. This side effect will be fixed with Thunk change to
set CWSR svm range with ACCESS_IN_PLACE attribute on the GPU that user
queue is created.
Signed-off-by: Philip Yang
Reviewed-by: Felix Kuehling
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index 63ce30ea68915..8e368e4659fd5 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1632,18 +1632,24 @@ static int svm_range_validate_and_map(struct mm_struct
*mm,
if (test_bit(gpuidx, prange->bitmap_access))
bitmap_set(ctx->bitmap, gpuidx, 1);
}
+
+ /*
+* If prange is already mapped or with always mapped flag,
+* update mapping on GPUs with ACCESS attribute
+*/
+ if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
+ if (prange->mapped_to_gpu ||
+ prange->flags &
KFD_IOCTL_SVM_FLAG_GPU_ALWAYS_MAPPED)
+ bitmap_copy(ctx->bitmap, prange->bitmap_access,
MAX_GPU_INSTANCE);
+ }
} else {
bitmap_or(ctx->bitmap, prange->bitmap_access,
prange->bitmap_aip, MAX_GPU_INSTANCE);
}
if (bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
- bitmap_copy(ctx->bitmap, prange->bitmap_access,
MAX_GPU_INSTANCE);
- if (!prange->mapped_to_gpu ||
- bitmap_empty(ctx->bitmap, MAX_GPU_INSTANCE)) {
- r = 0;
- goto free_ctx;
- }
+ r = 0;
+ goto free_ctx;
}
if (prange->actual_loc && !prange->ttm_res) {
--
2.43.0
[PATCH AUTOSEL 6.6 33/39] drm/amd/display: Add case for dcn35 to support usb4 dmub hpd event
From: Wayne Lin
[ Upstream commit 989824589f793120833bef13aa4e21f5a836a707 ]
[Why & how]
Refactor dc_is_dmub_outbox_supported() a bit and add case for dcn35 to
register dmub outbox notification irq to handle usb4 relevant hpd event.
Reviewed-by: Roman Li
Reviewed-by: Jun Lei
Signed-off-by: Wayne Lin
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 26
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index a1be93f6385c6..8cdf380bf3665 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -4865,18 +4865,28 @@ void
dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc)
*/
bool dc_is_dmub_outbox_supported(struct dc *dc)
{
- /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
- if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
- dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
- !dc->debug.dpia_debug.bits.disable_dpia)
- return true;
+ switch (dc->ctx->asic_id.chip_family) {
- if (dc->ctx->asic_id.chip_family == AMDGPU_FAMILY_GC_11_0_1 &&
- !dc->debug.dpia_debug.bits.disable_dpia)
- return true;
+ case FAMILY_YELLOW_CARP:
+ /* DCN31 B0 USB4 DPIA needs dmub notifications for interrupts */
+ if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
+ !dc->debug.dpia_debug.bits.disable_dpia)
+ return true;
+ break;
+
+ case AMDGPU_FAMILY_GC_11_0_1:
+ case AMDGPU_FAMILY_GC_11_5_0:
+ if (!dc->debug.dpia_debug.bits.disable_dpia)
+ return true;
+ break;
+
+ default:
+ break;
+ }
/* dmub aux needs dmub notifications to be enabled */
return dc->debug.enable_dmub_aux_for_legacy_ddc;
+
}
/**
--
2.43.0
[PATCH AUTOSEL 6.6 34/39] drm/amd/display: get dprefclk ss info from integration info table
From: Charlene Liu
[ Upstream commit 51e7b64690776a9981355428b537af9048308a95 ]
[why & how]
we have two SSC_En:
we get ssc_info from dce_info for MPLL_SSC_EN.
we used to call VBIOS cmdtbl's smu_info's SS persentage for DPRECLK SS info,
is used for DP AUDIO and VBIOS' smu_info table was from
systemIntegrationInfoTable.
since dcn35 VBIOS removed smu_info, driver need to use integrationInfotable
directly.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/display/dc/bios/bios_parser2.c| 19 ++-
.../display/include/grph_object_ctrl_defs.h | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 484d62bcf2c2e..518c5672d3848 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1015,13 +1015,20 @@ static enum bp_result get_ss_info_v4_5(
DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n",
ss_info->spread_spectrum_percentage);
break;
case AS_SIGNAL_TYPE_DISPLAY_PORT:
- ss_info->spread_spectrum_percentage =
+ if (bp->base.integrated_info) {
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001
percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
+ ss_info->spread_spectrum_percentage =
+
bp->base.integrated_info->gpuclk_ss_percentage;
+ ss_info->type.CENTER_MODE =
+
bp->base.integrated_info->gpuclk_ss_type;
+ } else {
+ ss_info->spread_spectrum_percentage =
disp_cntl_tbl->dp_ss_percentage;
- ss_info->spread_spectrum_range =
+ ss_info->spread_spectrum_range =
disp_cntl_tbl->dp_ss_rate_10hz * 10;
- if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
- ss_info->type.CENTER_MODE = true;
-
+ if (disp_cntl_tbl->dp_ss_mode &
ATOM_SS_CENTRE_SPREAD_MODE)
+ ss_info->type.CENTER_MODE = true;
+ }
DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n",
ss_info->spread_spectrum_percentage);
break;
case AS_SIGNAL_TYPE_GPU_PLL:
@@ -2826,6 +2833,8 @@ static enum bp_result get_integrated_info_v2_2(
info->ma_channel_number = info_v2_2->umachannelnumber;
info->dp_ss_control =
le16_to_cpu(info_v2_2->reserved1);
+ info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
+ info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
info->ext_disp_conn_info.gu_id[i] =
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index bc96d02113608..813463ffe15c5 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -417,6 +417,8 @@ struct integrated_info {
/* V2.1 */
struct edp_info edp1_info;
struct edp_info edp2_info;
+ uint32_t gpuclk_ss_percentage;
+ uint32_t gpuclk_ss_type;
};
/*
--
2.43.0
[PATCH AUTOSEL 6.1 20/24] drm/amd/display: get dprefclk ss info from integration info table
From: Charlene Liu
[ Upstream commit 51e7b64690776a9981355428b537af9048308a95 ]
[why & how]
we have two SSC_En:
we get ssc_info from dce_info for MPLL_SSC_EN.
we used to call VBIOS cmdtbl's smu_info's SS persentage for DPRECLK SS info,
is used for DP AUDIO and VBIOS' smu_info table was from
systemIntegrationInfoTable.
since dcn35 VBIOS removed smu_info, driver need to use integrationInfotable
directly.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Charlene Liu
Tested-by: Daniel Wheeler
Signed-off-by: Alex Deucher
Signed-off-by: Sasha Levin
---
.../drm/amd/display/dc/bios/bios_parser2.c| 19 ++-
.../display/include/grph_object_ctrl_defs.h | 2 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index e507d2e1410b7..93e40e0a15087 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1018,13 +1018,20 @@ static enum bp_result get_ss_info_v4_5(
DC_LOG_BIOS("AS_SIGNAL_TYPE_HDMI ss_percentage: %d\n",
ss_info->spread_spectrum_percentage);
break;
case AS_SIGNAL_TYPE_DISPLAY_PORT:
- ss_info->spread_spectrum_percentage =
+ if (bp->base.integrated_info) {
+ DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001
percent): %d\n", bp->base.integrated_info->gpuclk_ss_percentage);
+ ss_info->spread_spectrum_percentage =
+
bp->base.integrated_info->gpuclk_ss_percentage;
+ ss_info->type.CENTER_MODE =
+
bp->base.integrated_info->gpuclk_ss_type;
+ } else {
+ ss_info->spread_spectrum_percentage =
disp_cntl_tbl->dp_ss_percentage;
- ss_info->spread_spectrum_range =
+ ss_info->spread_spectrum_range =
disp_cntl_tbl->dp_ss_rate_10hz * 10;
- if (disp_cntl_tbl->dp_ss_mode & ATOM_SS_CENTRE_SPREAD_MODE)
- ss_info->type.CENTER_MODE = true;
-
+ if (disp_cntl_tbl->dp_ss_mode &
ATOM_SS_CENTRE_SPREAD_MODE)
+ ss_info->type.CENTER_MODE = true;
+ }
DC_LOG_BIOS("AS_SIGNAL_TYPE_DISPLAY_PORT ss_percentage: %d\n",
ss_info->spread_spectrum_percentage);
break;
case AS_SIGNAL_TYPE_GPU_PLL:
@@ -2830,6 +2837,8 @@ static enum bp_result get_integrated_info_v2_2(
info->ma_channel_number = info_v2_2->umachannelnumber;
info->dp_ss_control =
le16_to_cpu(info_v2_2->reserved1);
+ info->gpuclk_ss_percentage = info_v2_2->gpuclk_ss_percentage;
+ info->gpuclk_ss_type = info_v2_2->gpuclk_ss_type;
for (i = 0; i < NUMBER_OF_UCHAR_FOR_GUID; ++i) {
info->ext_disp_conn_info.gu_id[i] =
diff --git a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
index bc96d02113608..813463ffe15c5 100644
--- a/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
+++ b/drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h
@@ -417,6 +417,8 @@ struct integrated_info {
/* V2.1 */
struct edp_info edp1_info;
struct edp_info edp2_info;
+ uint32_t gpuclk_ss_percentage;
+ uint32_t gpuclk_ss_type;
};
/*
--
2.43.0
