[PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7

[Krunal Patel]

With this change it will add support for clock gating for sdma 5.2.7

- Additional changes are to re-arrange the chip version sequentially.

Signed-off-by: Krunal Patel 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 809eca54fc61..404b255cb4e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1647,12 +1647,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
 
switch (adev->ip_versions[SDMA0_HWIP][0]) {
case IP_VERSION(5, 2, 0):
-   case IP_VERSION(5, 2, 2):
case IP_VERSION(5, 2, 1):
+   case IP_VERSION(5, 2, 2):
+   case IP_VERSION(5, 2, 3):
case IP_VERSION(5, 2, 4):
case IP_VERSION(5, 2, 5):
case IP_VERSION(5, 2, 6):
-   case IP_VERSION(5, 2, 3):
+   case IP_VERSION(5, 2, 7):
sdma_v5_2_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
sdma_v5_2_update_medium_grain_light_sleep(adev,
-- 
2.25.1

[PATCH v3] drm/amdgpu: complete gfxoff allow signal during suspend without delay

[Harsh Jain]

change guarantees that gfxoff is allowed before moving further in
s2idle sequence to add more reliablity about gfxoff in amdgpu IP's
suspend flow

Signed-off-by: Harsh Jain 

---

v2: replaced flush_work with direct call to amdgpu_dpm_set_powergating_by_smu
and edited title
v3: added braces for readbility
---

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 9546adc8a76f..23692e5d4d13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -583,10 +583,14 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool 
enable)
if (adev->gfx.gfx_off_req_count == 0 &&
!adev->gfx.gfx_off_state) {
/* If going to s2idle, no need to wait */
-   if (adev->in_s0ix)
-   delay = GFX_OFF_NO_DELAY;
-   schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
+   if (adev->in_s0ix) {
+   if (!amdgpu_dpm_set_powergating_by_smu(adev,
+   AMD_IP_BLOCK_TYPE_GFX, true))
+   adev->gfx.gfx_off_state = true;
+   } else {
+   
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
  delay);
+   }
}
} else {
if (adev->gfx.gfx_off_req_count == 0) {
-- 
2.25.1

[PATCH] drm/amdgpu: disable BACO on special BEIGE_GOBY card

[Guchun Chen]

Still avoid intermittent failure.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 74996a8fb671..c9e0be9bb180 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -377,7 +377,9 @@ static void sienna_cichlid_check_bxco_support(struct 
smu_context *smu)
if (((adev->pdev->device == 0x73A1) &&
(adev->pdev->revision == 0x00)) ||
((adev->pdev->device == 0x73BF) &&
-   (adev->pdev->revision == 0xCF)))
+   (adev->pdev->revision == 0xCF)) ||
+   ((adev->pdev->device == 0x7422) &&
+(adev->pdev->revision == 0x00)))
smu_baco->platform_support = false;
 
}
-- 
2.25.1

RE: [PATCH v3] drm/amdgpu: complete gfxoff allow signal during suspend without delay

[Quan, Evan]

[AMD Official Use Only - General]

Reviewed-by: Evan Quan 

> -Original Message-
> From: Jain, Harsh 
> Sent: Monday, November 7, 2022 4:43 PM
> To: Deucher, Alexander ; Quan, Evan
> 
> Cc: amd-gfx@lists.freedesktop.org; Jain, Harsh 
> Subject: [PATCH v3] drm/amdgpu: complete gfxoff allow signal during
> suspend without delay
> 
> change guarantees that gfxoff is allowed before moving further in
> s2idle sequence to add more reliablity about gfxoff in amdgpu IP's
> suspend flow
> 
> Signed-off-by: Harsh Jain 
> 
> ---
> 
> v2: replaced flush_work with direct call to
> amdgpu_dpm_set_powergating_by_smu
> and edited title
> v3: added braces for readbility
> ---
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 9546adc8a76f..23692e5d4d13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -583,10 +583,14 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device
> *adev, bool enable)
>   if (adev->gfx.gfx_off_req_count == 0 &&
>   !adev->gfx.gfx_off_state) {
>   /* If going to s2idle, no need to wait */
> - if (adev->in_s0ix)
> - delay = GFX_OFF_NO_DELAY;
> - schedule_delayed_work(&adev-
> >gfx.gfx_off_delay_work,
> + if (adev->in_s0ix) {
> + if
> (!amdgpu_dpm_set_powergating_by_smu(adev,
> + AMD_IP_BLOCK_TYPE_GFX,
> true))
> + adev->gfx.gfx_off_state = true;
> + } else {
> + schedule_delayed_work(&adev-
> >gfx.gfx_off_delay_work,
> delay);
> + }
>   }
>   } else {
>   if (adev->gfx.gfx_off_req_count == 0) {
> --
> 2.25.1

RE: [PATCH] drm/amdgpu: disable BACO on special BEIGE_GOBY card

[Quan, Evan]

[AMD Official Use Only - General]

Acked-by: Evan Quan 

> -Original Message-
> From: Chen, Guchun 
> Sent: Monday, November 7, 2022 4:50 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> ; Lazar, Lijo ; Quan, Evan
> 
> Cc: Chen, Guchun 
> Subject: [PATCH] drm/amdgpu: disable BACO on special BEIGE_GOBY card
> 
> Still avoid intermittent failure.
> 
> Signed-off-by: Guchun Chen 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 74996a8fb671..c9e0be9bb180 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -377,7 +377,9 @@ static void sienna_cichlid_check_bxco_support(struct
> smu_context *smu)
>   if (((adev->pdev->device == 0x73A1) &&
>   (adev->pdev->revision == 0x00)) ||
>   ((adev->pdev->device == 0x73BF) &&
> - (adev->pdev->revision == 0xCF)))
> + (adev->pdev->revision == 0xCF)) ||
> + ((adev->pdev->device == 0x7422) &&
> +(adev->pdev->revision == 0x00)))
>   smu_baco->platform_support = false;
> 
>   }
> --
> 2.25.1

Re: [PATCH] drm/amdgpu: disable BACO on special BEIGE_GOBY card

[Lazar, Lijo]

On 11/7/2022 2:19 PM, Guchun Chen wrote:

Still avoid intermittent failure.

Signed-off-by: Guchun Chen 


Reviewed-by: Lijo Lazar 

Thanks,
Lijo


---
  drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 74996a8fb671..c9e0be9bb180 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -377,7 +377,9 @@ static void sienna_cichlid_check_bxco_support(struct 
smu_context *smu)
if (((adev->pdev->device == 0x73A1) &&
(adev->pdev->revision == 0x00)) ||
((adev->pdev->device == 0x73BF) &&
-   (adev->pdev->revision == 0xCF)))
+   (adev->pdev->revision == 0xCF)) ||
+   ((adev->pdev->device == 0x7422) &&
+(adev->pdev->revision == 0x00)))
smu_baco->platform_support = false;
  
  	}

dcn321_fpu.c:626: Array index check in wrong place ?

[David Binderman]

Hello there,

Static analyser cppcheck says:

linux-6.1-rc4/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c:626:27: 
style: Array index 'i' is used before limits check. [arrayIndexThenCheck]

Source code is

   if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < 
num_dcfclk_sta_targets) {

It might be wise to move the limits check to before use.

Regards

David Binderman

[PATCH] driver: gpu: add failure check for ftell

[SPeak Shen]

From: shenyanfeng 

add return-value check of ftell to improve robustness(and avoid abnormal 
behavior)

Signed-off-by: SPeak 
Signed-off-by: shenyanfeng 
---


Receive "Undelivered Mail Returned to Sender", so send again


 drivers/gpu/drm/radeon/mkregtable.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/mkregtable.c 
b/drivers/gpu/drm/radeon/mkregtable.c
index 52a7246fe..c31c58e5f 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -193,6 +193,7 @@ static int parser_auth(struct table *t, const char 
*filename)
regmatch_t match[4];
char buf[1024];
size_t end;
+   long pos;
int len;
int done = 0;
int r;
@@ -228,12 +229,12 @@ static int parser_auth(struct table *t, const char 
*filename)
last_reg = strtol(last_reg_s, NULL, 16);
 
do {
-   if (fgets(buf, 1024, file) == NULL) {
+   if ((fgets(buf, 1024, file) == NULL) || (pos = ftell(file)) < 
0) {
fclose(file);
return -1;
}
len = strlen(buf);
-   if (ftell(file) == end)
+   if (pos == end)
done = 1;
if (len) {
r = regexec(&mask_rex, buf, 4, match, 0);
-- 
2.25.1

RE: [PATCH] drm/amdgpu: add vram reservation logic based on vram_usagebyfirmware_v2_2

[Liu01, Tong (Esther)]

[AMD Official Use Only - General]

Hi @Koenig, Christian & @Wang, Yang(Kevin),

Refined patch based on your comments, please help review new patch below, 
thanks!

Kind regards,
Esther

-Original Message-
From: Tong Liu01  
Sent: 2022年11月7日星期一 上午11:33
To: amd-gfx@lists.freedesktop.org
Cc: Andrey Grodzovsky ; Quan, Evan 
; Chen, Horace ; Tuikov, Luben 
; Koenig, Christian ; Deucher, 
Alexander ; Xiao, Jack ; Zhang, 
Hawking ; Liu, Monk ; Xu, Feifei 
; Wang, Yang(Kevin) ; Liu01, Tong 
(Esther) 
Subject: [PATCH] drm/amdgpu: add vram reservation logic based on 
vram_usagebyfirmware_v2_2

Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR 
region firstly to make sure TMR can be allocated at 2MB

Signed-off-by: Tong Liu01 
---
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 106 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  51 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   5 +
 drivers/gpu/drm/amd/include/atomfirmware.h|  56 -
 4 files changed, 190 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b81b77a9efa6..239c621feb0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -101,39 +101,99 @@ void amdgpu_atomfirmware_scratch_regs_init(struct 
amdgpu_device *adev)
}
 }
 
+static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_1 *firmware_usage_v2_1,
+   int *usage_bytes)
+{
+   uint32_t start_addr, size;
+
+   DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
+   le32_to_cpu(firmware_usage_v2_1->start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb));
+
+   start_addr = le32_to_cpu(firmware_usage_v2_1->start_address_in_kb);
+   size = le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb);
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = size << 10;
+   /* Use the default scratch size */
+   *usage_bytes = 0;
+   } else {
+   *usage_bytes =
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb) 
<< 10;
+   }
+   return 0;
+}
+
+static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_2 *firmware_usage_v2_2,
+   int *usage_bytes)
+{
+   uint32_t fw_start_addr, fw_size, drv_start_addr, drv_size;
+
+   DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x 
%dkb\n",
+   le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb),
+   
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb),
+   le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb));
+
+   fw_start_addr = 
le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb);
+   fw_size = le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb);
+
+   drv_start_addr = 
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb);
+   drv_size = 
+le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb);
+
+   if ((uint32_t)(fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 
30)) == 0) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = fw_size << 10;
+   }
+
+   if ((uint32_t)(drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 
<< 30)) == 0) {
+   /* driver request VRAM reservation for SR-IOV */
+   adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.drv_vram_usage_size = drv_size << 10;
+   }
+
+   *usage_bytes = 0;
+   return 0;
+}
+
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)  {
struct atom_context *ctx = adev->mode_info.atom_context;
int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
-   struct vram_usagebyfirmware_v2_1 *firmware_usage;

[PATCH] [next] drm/amdgpu: Replace 1-element array with flexible-array member

[Paulo Miguel Almeida]

One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in structs _ATOM_GPIO_PIN_ASSIGNMENT,
_ATOM_DISPLAY_OBJECT_PATH, _ATOM_DISPLAY_OBJECT_PATH_TABLE,
_ATOM_OBJECT_TABLE and refactor the rest of the code accordingly.

Important to mention is that doing a build before/after this patch results
in no functional binary output differences.

This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
routines on memcpy() and help us make progress towards globally
enabling -fstrict-flex-arrays=3 [1].

Link: https://github.com/KSPP/linux/issues/79
Link: https://github.com/KSPP/linux/issues/238
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1]

Signed-off-by: Paulo Miguel Almeida 
---

Binary difference findings:

Some changes took more than a single line which changed the line
number parameter passed to the drm_dbg function (which leverages
kernel's dynamic debugging). Functionally-wise, nothing changed
after doing a before/after patch build.

Additional one-element arrays to be changed:

There are more instances of one-element arrays to be changed but
I will keep patches small so they are easy to review. [and I can
only dedicate a few hours per day on this :-) ]

---
 .../gpu/drm/amd/display/dc/bios/bios_parser.c | 23 ---
 drivers/gpu/drm/amd/include/atombios.h|  8 +++
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 9b8ea6e9a2b9..39dd8b2dc254 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -138,7 +138,9 @@ static uint8_t get_number_of_objects(struct bios_parser 
*bp, uint32_t offset)
 
uint32_t object_table_offset = bp->object_info_tbl_offset + offset;
 
-   table = GET_IMAGE(ATOM_OBJECT_TABLE, object_table_offset);
+   table = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base,
+   object_table_offset,
+   struct_size(table, asObjects, 1)));
 
if (!table)
return 0;
@@ -166,8 +168,9 @@ static struct graphics_object_id 
bios_parser_get_connector_id(
uint32_t connector_table_offset = bp->object_info_tbl_offset
+ 
le16_to_cpu(bp->object_info_tbl.v1_1->usConnectorObjectTableOffset);
 
-   ATOM_OBJECT_TABLE *tbl =
-   GET_IMAGE(ATOM_OBJECT_TABLE, connector_table_offset);
+   ATOM_OBJECT_TABLE *tbl = ((ATOM_OBJECT_TABLE *) 
bios_get_image(&bp->base,
+   connector_table_offset,
+   struct_size(tbl, asObjects, 1)));
 
if (!tbl) {
dm_error("Can't get connector table from atom bios.\n");
@@ -1789,11 +1792,13 @@ static enum bp_result bios_parser_get_gpio_pin_info(
if (!DATA_TABLES(GPIO_Pin_LUT))
return BP_RESULT_BADBIOSTABLE;
 
-   header = GET_IMAGE(ATOM_GPIO_PIN_LUT, DATA_TABLES(GPIO_Pin_LUT));
+   header = ((ATOM_GPIO_PIN_LUT *) bios_get_image(&bp->base,
+   DATA_TABLES(GPIO_Pin_LUT),
+   struct_size(header, asGPIO_Pin, 1)));
if (!header)
return BP_RESULT_BADBIOSTABLE;
 
-   if (sizeof(ATOM_COMMON_TABLE_HEADER) + sizeof(ATOM_GPIO_PIN_LUT)
+   if (sizeof(ATOM_COMMON_TABLE_HEADER) + struct_size(header, asGPIO_Pin, 
1)
> le16_to_cpu(header->sHeader.usStructureSize))
return BP_RESULT_BADBIOSTABLE;
 
@@ -1978,7 +1983,8 @@ static ATOM_OBJECT *get_bios_object(struct bios_parser 
*bp,
 
offset += bp->object_info_tbl_offset;
 
-   tbl = GET_IMAGE(ATOM_OBJECT_TABLE, offset);
+   tbl = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base, offset,
+   struct_size(tbl, asObjects, 1)));
if (!tbl)
return NULL;
 
@@ -2709,8 +2715,9 @@ static enum bp_result get_bracket_layout_record(
 
genericTableOffset = bp->object_info_tbl_offset +
bp->object_info_tbl.v1_3->usMiscObjectTableOffset;
-   object_table = (ATOM_OBJECT_TABLE *)
-   GET_IMAGE(ATOM_OBJECT_TABLE, genericTableOffset);
+   object_table = ((ATOM_OBJECT_TABLE *) bios_get_image(&bp->base,
+   genericTableOffset,
+   struct_size(object_table, asObjects, 1)));
if (!object_table)
return BP_RESULT_FAILURE;
 
diff --git a/drivers/gpu/drm/amd/include/atombios.h 
b/drivers/gpu/drm/amd/include/atombios.h
index b5b1d073f8e2..55ae93c1e365 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -4386,7 +4386,7 @@ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
 typedef struct _ATOM_GPIO_PIN_LUT
 {
   ATOM_

Re: [PATCH] drm/amdkfd: Fix the memory overrun

[Felix Kuehling]

Am 2022-11-07 um 02:08 schrieb Ma Jun:

Fix the memory overrun issue caused by wrong array size.

Signed-off-by: Ma Jun 
Reported-by: coverity-bot 
Addresses-Coverity-ID: 1527133 ("Memory - corruptions")
Fixes: 624693863 ("drm/amdkfd: Fix the warning of 
array-index-out-of-bounds")


Reviewed-by: Felix Kuehling 



---
  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 7029e3bdff3e..6e81f50ad912 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -,7 +,7 @@ static int kfd_parse_subtype_cache(struct 
crat_subtype_cache *cache,
props->cache_latency = cache->cache_latency;
  
  			memcpy(props->sibling_map, cache->sibling_map,

-   sizeof(props->sibling_map));
+   CRAT_SIBLINGMAP_SIZE);
  
  			/* set the sibling_map_size as 32 for CRAT from ACPI */

props->sibling_map_size = CRAT_SIBLINGMAP_SIZE;

[PATCH] drm/amd/display: Amend descriptions within enum pipe_split_policy

[Carlos Bilbao]

Correct descriptions of two last fields of enum pipe_split_policy, updating
comments with proper field names.

Signed-off-by: Carlos Bilbao 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index bfc5474c0f4c..277631a899d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -457,15 +457,16 @@ enum pipe_split_policy {
MPC_SPLIT_DYNAMIC = 0,
 
/**
-* @MPC_SPLIT_DYNAMIC: Avoid pipe split, which means that DC will not
+* @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
 * try any sort of split optimization.
 */
MPC_SPLIT_AVOID = 1,
 
/**
-* @MPC_SPLIT_DYNAMIC: With this option, DC will only try to optimize
-* the pipe utilization when using a single display; if the user
-* connects to a second display, DC will avoid pipe split.
+* @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try
+* to optimize the pipe utilization when using a single display;
+* if the user connects to a second display, DC will avoid pipe
+* split.
 */
MPC_SPLIT_AVOID_MULT_DISP = 2,
 };
-- 
2.34.1

[linux-next:master] BUILD REGRESSION d8e87774068af213ab5b058b1b114dc397b577aa

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: d8e87774068af213ab5b058b1b114dc397b577aa  Add linux-next specific 
files for 20221107

Error/Warning reports:

https://lore.kernel.org/linux-mm/202210090954.ptr6m6rj-...@intel.com
https://lore.kernel.org/linux-mm/202210111318.mbufyhps-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202211041320.coq8eelj-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202211071905.hjt4cwsk-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202211072023.hrrepgnj-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202211072213.ksrsyiue-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:4878: warning: This comment 
starts with '/**', but isn't a kernel-doc comment. Refer 
Documentation/doc-guide/kernel-doc.rst
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:5044:24: warning: 
implicit conversion from 'enum ' to 'enum dc_status' 
[-Wenum-conversion]
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c:75:8: error: call to 
undeclared function 'readl'; ISO C99 and later do not support implicit function 
declarations [-Wimplicit-function-declaration]
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c:80:2: error: call to 
undeclared function 'writel'; ISO C99 and later do not support implicit 
function declarations [-Wimplicit-function-declaration]
lib/test_maple_tree.c:453:12: warning: result of comparison of constant 
4398046511104 with expression of type 'unsigned long' is always false 
[-Wtautological-constant-out-of-range-compare]
lib/test_objpool.c:106:6: warning: no previous prototype for function 
'ot_vfree' [-Wmissing-prototypes]
lib/test_objpool.c:80:7: warning: no previous prototype for function 
'ot_kzalloc' [-Wmissing-prototypes]
lib/test_objpool.c:89:6: warning: no previous prototype for function 'ot_kfree' 
[-Wmissing-prototypes]
lib/test_objpool.c:97:7: warning: no previous prototype for function 
'ot_vmalloc' [-Wmissing-prototypes]
net/dcb/dcbnl.c:1230:1: warning: the frame size of 1244 bytes is larger than 
1024 bytes [-Wframe-larger-than=]

Unverified Error/Warning (likely false positive, please contact us if 
interested):

drivers/input/touchscreen/hynitron_cstxxx.c:238 cst3xx_bootloader_enter() 
error: uninitialized symbol 'tmp'.
lib/zstd/compress/huf_compress.c:460 HUF_getIndex() warn: the 
'RANK_POSITION_LOG_BUCKETS_BEGIN' macro might need parens
lib/zstd/decompress/zstd_decompress_block.c:1009 ZSTD_execSequence() warn: 
inconsistent indenting
lib/zstd/decompress/zstd_decompress_block.c:894 ZSTD_execSequenceEnd() warn: 
inconsistent indenting
lib/zstd/decompress/zstd_decompress_block.c:942 
ZSTD_execSequenceEndSplitLitBuffer() warn: inconsistent indenting
lib/zstd/decompress/zstd_decompress_internal.h:206 ZSTD_DCtx_get_bmi2() warn: 
inconsistent indenting

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:warning:implicit-conversion-from-enum-anonymous-to-enum-dc_status
|-- arc-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:warning:implicit-conversion-from-enum-anonymous-to-enum-dc_status
|-- arc-randconfig-r002-20221106
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:warning:implicit-conversion-from-enum-anonymous-to-enum-dc_status
|-- arm-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:warning:implicit-conversion-from-enum-anonymous-to-enum-dc_status
|-- arm64-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:warning:implicit-conversion-from-enum-anonymous-to-enum-dc_status
|-- i386-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc.c:warning:This-comment-starts-with-but-isn-t-a-kernel-doc-comment.-Refer-Documentation-doc-guide-kernel-doc.rst
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-core-dc_link_dp.c:

[PATCH] drm/amdgpu: Remove redundant I2C EEPROM address

[Luben Tuikov]

Remove redundant EEPROM_I2C_MADDR_54H address, since we already have it
represented (ARCTURUS), and since we don't include the I2C device type
identifier in EEPROM memory addresses, i.e. that high up in the device
abstraction--we only use EEPROM memory addresses, as memory is continuously
represented by EEPROM device(s) on the I2C bus.

Add a comment describing what these memory addresses are, how they come
about and how they're usually extracted from the device address byte.

Cc: Candice Li 
Cc: Tao Zhou 
Cc: Alex Deucher 
Fixes: 367a1ebddde5d0 ("drm/amdgpu: Add EEPROM I2C address support for ip 
discovery")
Signed-off-by: Luben Tuikov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c|  2 ++
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 24 ---
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
index 4d9eb0137f8c43..d6c4293829aab1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.c
@@ -79,6 +79,8 @@
  * That is, for an I2C EEPROM driver everything is controlled by
  * the "eeprom_addr".
  *
+ * See also top of amdgpu_ras_eeprom.c.
+ *
  * P.S. If you need to write, lock and read the Identification Page,
  * (M24M02-DR device only, which we do not use), change the "7" to
  * "0xF" in the macro below, and let the client set bit 20 to 1 in
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 7268ae65c140c1..1bb92a64f24afc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -33,12 +33,30 @@
 
 #include "amdgpu_reset.h"
 
+/* These are memory addresses as would be seen by one or more EEPROM
+ * chips strung on the I2C bus, usually by manipulating pins 1-3 of a
+ * set of EEPROM devices. They form a continuous memory space.
+ *
+ * The I2C device address includes the device type identifier, 1010b,
+ * which is a reserved value and indicates that this is an I2C EEPROM
+ * device. It also includes the top 3 bits of the 19 bit EEPROM memory
+ * address, namely bits 18, 17, and 16. This makes up the 7 bit
+ * address sent on the I2C bus with bit 0 being the direction bit,
+ * which is not represented here, and sent by the hardware directly.
+ *
+ * For instance,
+ *   50h = 101b => device type identifier 1010b, bits 18:16 = 000b, 
address 0.
+ *   54h = 1010100b => --"--, bits 18:16 = 100b, address 4h.
+ *   56h = 1010110b => --"--, bits 18:16 = 110b, address 6h.
+ * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
+ * address memory in a device or a device on the I2C bus, depending on
+ * the status of pins 1-3. See top of amdgpu_eeprom.c.
+ */
 #define EEPROM_I2C_MADDR_VEGA20 0x0
 #define EEPROM_I2C_MADDR_ARCTURUS   0x4
 #define EEPROM_I2C_MADDR_ARCTURUS_D342  0x0
 #define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
 #define EEPROM_I2C_MADDR_ALDEBARAN  0x0
-#define EEPROM_I2C_MADDR_54H(0x54UL << 16)
 
 /*
  * The 2 macros bellow represent the actual size in bytes that
@@ -130,7 +148,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct 
amdgpu_device *adev,
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 10):
-   control->i2c_address = EEPROM_I2C_MADDR_54H;
+   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
return true;
default:
return false;
@@ -185,7 +203,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device 
*adev,
 
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
-   control->i2c_address = EEPROM_I2C_MADDR_54H;
+   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
break;
 
default:

base-commit: 03b61a92efbaf17ac3d9f82ae81aa4cf8ed40608
-- 
2.38.1

Re: [PATCH v7 18/21] dma-buf: Move dma_buf_mmap() to dynamic locking specification

[Daniel Vetter]

On Mon, 17 Oct 2022 at 19:25, Dmitry Osipenko
 wrote:
>
> Move dma_buf_mmap() function to the dynamic locking specification by
> taking the reservation lock. Neither of the today's drivers take the
> reservation lock within the mmap() callback, hence it's safe to enforce
> the locking.
>
> Acked-by: Sumit Semwal 
> Acked-by: Christian König 
> Signed-off-by: Dmitry Osipenko 

Just noticed this while reading code ... this patch seems to have
missed dma_buf_mmap_internal()?

Might be good if at least some drivers gain a dma_resv_assert_held in
that path to make sure we're not quite this bad, together with fixing
this issue.
-Daniel

> ---
>  drivers/dma-buf/dma-buf.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index f54c649f922a..f149b384f4dd 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -1390,6 +1390,8 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_end_cpu_access, DMA_BUF);
>  int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma,
>  unsigned long pgoff)
>  {
> +   int ret;
> +
> if (WARN_ON(!dmabuf || !vma))
> return -EINVAL;
>
> @@ -1410,7 +1412,11 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct 
> vm_area_struct *vma,
> vma_set_file(vma, dmabuf->file);
> vma->vm_pgoff = pgoff;
>
> -   return dmabuf->ops->mmap(dmabuf, vma);
> +   dma_resv_lock(dmabuf->resv, NULL);
> +   ret = dmabuf->ops->mmap(dmabuf, vma);
> +   dma_resv_unlock(dmabuf->resv);
> +
> +   return ret;
>  }
>  EXPORT_SYMBOL_NS_GPL(dma_buf_mmap, DMA_BUF);
>
> --
> 2.37.3
>


-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

[PATCH] drm/amdgpu: Decouple RAS EEPROM addresses from chips

[Luben Tuikov]

Abstract RAS I2C EEPROM addresses from chip names, and set their macro
definition names to the address they set, not the chip they attach
to. Since most chips either use I2C EEPROM address 0 or 4h for the RAS
table start offset, this leaves with only two macro definitions as opposed
to five, and removes the redundancy of four.

Cc: Candice Li 
Cc: Tao Zhou 
Cc: Alex Deucher 
Signed-off-by: Luben Tuikov 
---
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c| 23 +--
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 1bb92a64f24afc..f63bd31e199c8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -51,12 +51,11 @@
  * Depending on the size of the I2C EEPROM device(s), bits 18:16 may
  * address memory in a device or a device on the I2C bus, depending on
  * the status of pins 1-3. See top of amdgpu_eeprom.c.
+ *
+ * The RAS table lives either at address 0 or address 4h of EEPROM.
  */
-#define EEPROM_I2C_MADDR_VEGA20 0x0
-#define EEPROM_I2C_MADDR_ARCTURUS   0x4
-#define EEPROM_I2C_MADDR_ARCTURUS_D342  0x0
-#define EEPROM_I2C_MADDR_SIENNA_CICHLID 0x0
-#define EEPROM_I2C_MADDR_ALDEBARAN  0x0
+#define EEPROM_I2C_MADDR_0  0x0
+#define EEPROM_I2C_MADDR_4  0x4
 
 /*
  * The 2 macros bellow represent the actual size in bytes that
@@ -135,9 +134,9 @@ static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device 
*adev,
if (strnstr(atom_ctx->vbios_version,
"D342",
sizeof(atom_ctx->vbios_version)))
-   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS_D342;
+   control->i2c_address = EEPROM_I2C_MADDR_0;
else
-   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
+   control->i2c_address = EEPROM_I2C_MADDR_4;
 
return true;
 }
@@ -148,7 +147,7 @@ static bool __get_eeprom_i2c_addr_ip_discovery(struct 
amdgpu_device *adev,
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 10):
-   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
+   control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
default:
return false;
@@ -180,18 +179,18 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device 
*adev,
 
switch (adev->asic_type) {
case CHIP_VEGA20:
-   control->i2c_address = EEPROM_I2C_MADDR_VEGA20;
+   control->i2c_address = EEPROM_I2C_MADDR_0;
break;
 
case CHIP_ARCTURUS:
return __get_eeprom_i2c_addr_arct(adev, control);
 
case CHIP_SIENNA_CICHLID:
-   control->i2c_address = EEPROM_I2C_MADDR_SIENNA_CICHLID;
+   control->i2c_address = EEPROM_I2C_MADDR_0;
break;
 
case CHIP_ALDEBARAN:
-   control->i2c_address = EEPROM_I2C_MADDR_ALDEBARAN;
+   control->i2c_address = EEPROM_I2C_MADDR_0;
break;
 
case CHIP_IP_DISCOVERY:
@@ -203,7 +202,7 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device 
*adev,
 
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
-   control->i2c_address = EEPROM_I2C_MADDR_ARCTURUS;
+   control->i2c_address = EEPROM_I2C_MADDR_4;
break;
 
default:

base-commit: 03b61a92efbaf17ac3d9f82ae81aa4cf8ed40608
prerequisite-patch-id: 6ba70460570b30bf3176058b399934e5e79b229e
-- 
2.38.1

Re: [PATCH] drm/amdgpu: add vram reservation logic based on vram_usagebyfirmware_v2_2

[Christian König]

Am 07.11.22 um 04:32 schrieb Tong Liu01:

Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR region
firstly to make sure TMR can be allocated at 2MB


At few coding style things below, but looks good to me from the 
technically side.


Please use the checkpatch.pl script, it should point out a couple of issues.



Signed-off-by: Tong Liu01 
---
  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 106 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  51 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   5 +
  drivers/gpu/drm/amd/include/atomfirmware.h|  56 -
  4 files changed, 190 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b81b77a9efa6..239c621feb0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -101,39 +101,99 @@ void amdgpu_atomfirmware_scratch_regs_init(struct 
amdgpu_device *adev)
}
  }
  
+static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,

+   struct vram_usagebyfirmware_v2_1 *firmware_usage_v2_1,
+   int *usage_bytes)


Could be that this is just my mail client, but of hand this doesn't 
looks like normal kernel function style (but I might be wrong).



+{
+   uint32_t start_addr, size;
+
+   DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
+   le32_to_cpu(firmware_usage_v2_1->start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb));
+
+   start_addr = le32_to_cpu(firmware_usage_v2_1->start_address_in_kb);
+   size = le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb);
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {


Here again, this isn't normal kernel coding style.


+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = size << 10;
+   /* Use the default scratch size */
+   *usage_bytes = 0;
+   } else {
+   *usage_bytes =
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb) 
<< 10;
+   }
+   return 0;
+}
+
+static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_2 *firmware_usage_v2_2,
+   int *usage_bytes)
+{
+   uint32_t fw_start_addr, fw_size, drv_start_addr, drv_size;
+
+   DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x 
%dkb\n",
+   le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb),
+   
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb),
+   le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb));


While at it maybe convert this from le to cpu only once.


+
+   fw_start_addr = 
le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb);
+   fw_size = le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb);
+
+   drv_start_addr = 
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb);
+   drv_size = 
le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb);


In other words use those local variable for printing.


+
+   if ((uint32_t)(fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 
30)) == 0) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = fw_size << 10;
+   }
+
+   if ((uint32_t)(drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 
<< 30)) == 0) {
+   /* driver request VRAM reservation for SR-IOV */
+   adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.drv_vram_usage_size = drv_size << 10;
+   }
+
+   *usage_bytes = 0;
+   return 0;
+}
+
  int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  {
struct atom_context *ctx = adev->mode_info.atom_context;
int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
-   struct vram_usagebyfirmware_v2_1 *firmware_usage;
-   uint32_t start_addr, size;
+   struct vram_usagebyfirmware

[PATCH v2 1/7] drm/amdgpu: Use drm_mode_init() for on-stack modes

[Ville Syrjala]

From: Ville Syrjälä 

Initialize on-stack modes with drm_mode_init() to guarantee
no stack garbage in the list head, or that we aren't copying
over another mode's list head.

Based on the following cocci script, with manual fixups:
@decl@
identifier M;
expression E;
@@
- struct drm_display_mode M = E;
+ struct drm_display_mode M;

@@
identifier decl.M;
expression decl.E;
statement S, S1;
@@
struct drm_display_mode M;
... when != S
+ drm_mode_init(&M, &E);
+
S1

@@
expression decl.E;
@@
- &*E
+ E

Cc: Harry Wentland 
Cc: Leo Li 
Cc: Rodrigo Siqueira 
Cc: Alex Deucher 
Cc: amd-gfx@lists.freedesktop.org
Reviewed-by: Harry Wentland 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d9940a3c64dd..7fa4b61bc5bf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5685,7 +5685,7 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
const struct drm_connector_state *con_state =
dm_state ? &dm_state->base : NULL;
struct dc_stream_state *stream = NULL;
-   struct drm_display_mode mode = *drm_mode;
+   struct drm_display_mode mode;
struct drm_display_mode saved_mode;
struct drm_display_mode *freesync_mode = NULL;
bool native_mode_found = false;
@@ -5699,6 +5699,7 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 
struct dc_sink *sink = NULL;
 
+   drm_mode_init(&mode, drm_mode);
memset(&saved_mode, 0, sizeof(saved_mode));
 
if (aconnector == NULL) {
-- 
2.37.4

[PATCH v2] drm/amd/pm: enable mode1 reset on smu_v13_0_10

[Kenneth Feng]

enable mode1 reset and prioritize debug port on msu_v13_0_10
as a more reliable message processing

v2 - move mode1 reset callback to smu_v13_0_0_ppt.c

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c|  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  4 ++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 53 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 18 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ++
 5 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 1d4013ed0d10..b258e9aa0558 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -322,6 +322,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
return AMD_RESET_METHOD_MODE1;
case IP_VERSION(13, 0, 4):
return AMD_RESET_METHOD_MODE2;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index e2fa3b066b96..1bc26e93a83c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -568,6 +568,10 @@ struct smu_context
u32 param_reg;
u32 msg_reg;
u32 resp_reg;
+
+   u32 debug_param_reg;
+   u32 debug_msg_reg;
+   u32 debug_resp_reg;
 };
 
 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 29529328152d..588527310188 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -70,6 +70,26 @@
 
 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE  0x4000
 
+#define mmMP1_SMN_C2PMSG_66
0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_82
0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_90
0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_75
0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_53
0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_54
0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX   
0
+
+#define DEBUGSMC_MSG_Mode1Reset2
+
 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
MSG_MAP(TestMessage,PPSMC_MSG_TestMessage,  
   1),
MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion,
   1),
@@ -1763,6 +1783,35 @@ static int smu_v13_0_0_set_df_cstate(struct smu_context 
*smu,
   NULL);
 }
 
+static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
+{
+   int ret = 0;
+   struct amdgpu_device *adev = smu->adev;
+
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))
+   ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
+   else
+   ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+
+   if (!ret)
+   msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
+
+   return ret;
+}
+
+static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+   smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+   smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+
+   smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);
+   smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);
+   smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);
+}
+
 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
.set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
@@ -1830,7 +1879,7 @@ stati

Re: [PATCH v2] drm/amd/pm: enable mode1 reset on smu_v13_0_10

[Wang, Yang(Kevin)]

[AMD Official Use Only - General]

a typo issue in commit message:  "msu",
and one comment inline.

Reviewed-by: Yang Wang 

Best Regards
Kevin

发件人: amd-gfx  代表 Kenneth Feng 

发送时间: 2022年11月8日星期二 上午8:36
收件人: amd-gfx@lists.freedesktop.org
抄送: Feng, Kenneth
主题: [PATCH v2] drm/amd/pm: enable mode1 reset on smu_v13_0_10

enable mode1 reset and prioritize debug port on msu_v13_0_10
as a more reliable message processing

v2 - move mode1 reset callback to smu_v13_0_0_ppt.c

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/soc21.c|  1 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  4 ++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 53 ++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c| 18 +++
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h|  3 ++
 5 files changed, 77 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 1d4013ed0d10..b258e9aa0558 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -322,6 +322,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev)
 switch (adev->ip_versions[MP1_HWIP][0]) {
 case IP_VERSION(13, 0, 0):
 case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
 return AMD_RESET_METHOD_MODE1;
 case IP_VERSION(13, 0, 4):
 return AMD_RESET_METHOD_MODE2;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index e2fa3b066b96..1bc26e93a83c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -568,6 +568,10 @@ struct smu_context
 u32 param_reg;
 u32 msg_reg;
 u32 resp_reg;
+
+   u32 debug_param_reg;
+   u32 debug_msg_reg;
+   u32 debug_resp_reg;
 };

 struct i2c_adapter;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 29529328152d..588527310188 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -70,6 +70,26 @@

 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE   0x4000

+#define mmMP1_SMN_C2PMSG_66
0x0282
+#define mmMP1_SMN_C2PMSG_66_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_82
0x0292
+#define mmMP1_SMN_C2PMSG_82_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_90
0x029a
+#define mmMP1_SMN_C2PMSG_90_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_75
0x028b
+#define mmMP1_SMN_C2PMSG_75_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_53
0x0275
+#define mmMP1_SMN_C2PMSG_53_BASE_IDX   
0
+
+#define mmMP1_SMN_C2PMSG_54
0x0276
+#define mmMP1_SMN_C2PMSG_54_BASE_IDX   
0
+
+#define DEBUGSMC_MSG_Mode1Reset2
+
 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] 
= {
 MSG_MAP(TestMessage,PPSMC_MSG_TestMessage, 
1),
 MSG_MAP(GetSmuVersion,  PPSMC_MSG_GetSmuVersion,   
1),
@@ -1763,6 +1783,35 @@ static int smu_v13_0_0_set_df_cstate(struct smu_context 
*smu,
NULL);
 }

+static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
+{
+   int ret = 0;
kevin:
No initialization required

+   struct amdgpu_device *adev = smu->adev;
+
+   if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 10))
+   ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
+   else
+   ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
+
+   if (!ret)
+   msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
+
+   return ret;
+}
+
+static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)
+{
+   struct amdgpu_device *adev = smu->adev;
+
+   smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
+   smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
+   smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
+
+   smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PM

[PATCH] drm/amdgpu: add vram reservation logic based on vram_usagebyfirmware_v2_2

[Tong Liu01]

Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR
region firstly to make sure TMR can be allocated at 2MB

Signed-off-by: Tong Liu01 
---
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 106 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  50 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   5 +
 drivers/gpu/drm/amd/include/atomfirmware.h|  62 --
 4 files changed, 192 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b81b77a9efa6..239c621feb0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -101,39 +101,99 @@ void amdgpu_atomfirmware_scratch_regs_init(struct 
amdgpu_device *adev)
}
 }
 
+static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_1 *firmware_usage_v2_1,
+   int *usage_bytes)
+{
+   uint32_t start_addr, size;
+
+   DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
+   le32_to_cpu(firmware_usage_v2_1->start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb));
+
+   start_addr = le32_to_cpu(firmware_usage_v2_1->start_address_in_kb);
+   size = le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb);
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = size << 10;
+   /* Use the default scratch size */
+   *usage_bytes = 0;
+   } else {
+   *usage_bytes =
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb) 
<< 10;
+   }
+   return 0;
+}
+
+static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_2 *firmware_usage_v2_2,
+   int *usage_bytes)
+{
+   uint32_t fw_start_addr, fw_size, drv_start_addr, drv_size;
+
+   DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x 
%dkb\n",
+   le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb),
+   
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb),
+   le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb));
+
+   fw_start_addr = 
le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb);
+   fw_size = le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb);
+
+   drv_start_addr = 
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb);
+   drv_size = 
le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb);
+
+   if ((uint32_t)(fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 
30)) == 0) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = fw_size << 10;
+   }
+
+   if ((uint32_t)(drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 
<< 30)) == 0) {
+   /* driver request VRAM reservation for SR-IOV */
+   adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.drv_vram_usage_size = drv_size << 10;
+   }
+
+   *usage_bytes = 0;
+   return 0;
+}
+
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 {
struct atom_context *ctx = adev->mode_info.atom_context;
int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
-   struct vram_usagebyfirmware_v2_1 *firmware_usage;
-   uint32_t start_addr, size;
+   struct vram_usagebyfirmware_v2_1 *firmware_usage_v2_1;
+   struct vram_usagebyfirmware_v2_2 *firmware_usage_v2_2;
uint16_t data_offset;
+   uint8_t frev, crev;
int usage_bytes = 0;
 
-   if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, 
&data_offset)) {
-   firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios 
+ data_offset);
-   DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
- le32_to_cpu(firmware_usage->start_address_in_kb),
- 

Re: [PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7

[Patel, Krunalkumar Mukeshkumar]

[AMD Official Use Only - General]

+Likun, Hawking

Hi,

Can you please help with the review of the patch?

Thanks and regards
Krunal

From: Patel, Krunalkumar Mukeshkumar 
Sent: Monday, November 7, 2022 1:35:01 PM
To: Deucher, Alexander ; Pan, Xinhui 
; Koenig, Christian 
Cc: amd-gfx@lists.freedesktop.org ; S, Shirish 
; Patel, Krunalkumar Mukeshkumar 

Subject: [PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7

With this change it will add support for clock gating for sdma 5.2.7

- Additional changes are to re-arrange the chip version sequentially.

Signed-off-by: Krunal Patel 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 809eca54fc61..404b255cb4e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1647,12 +1647,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,

 switch (adev->ip_versions[SDMA0_HWIP][0]) {
 case IP_VERSION(5, 2, 0):
-   case IP_VERSION(5, 2, 2):
 case IP_VERSION(5, 2, 1):
+   case IP_VERSION(5, 2, 2):
+   case IP_VERSION(5, 2, 3):
 case IP_VERSION(5, 2, 4):
 case IP_VERSION(5, 2, 5):
 case IP_VERSION(5, 2, 6):
-   case IP_VERSION(5, 2, 3):
+   case IP_VERSION(5, 2, 7):
 sdma_v5_2_update_medium_grain_clock_gating(adev,
 state == AMD_CG_STATE_GATE);
 sdma_v5_2_update_medium_grain_light_sleep(adev,
--
2.25.1

RE: [PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7

[Gao, Likun]

[AMD Official Use Only - General]

Looks good to me, this patch is Reviewed-by: Likun Gao 
mailto:likun@amd.com>>

Regards,
Likun

From: Patel, Krunalkumar Mukeshkumar 
Sent: Tuesday, November 8, 2022 11:46 AM
To: Deucher, Alexander ; Pan, Xinhui 
; Koenig, Christian ; Gao, Likun 
; Zhang, Hawking 
Cc: amd-gfx@lists.freedesktop.org; S, Shirish 
Subject: Re: [PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7


[AMD Official Use Only - General]

+Likun, Hawking

Hi,

Can you please help with the review of the patch?

Thanks and regards
Krunal

From: Patel, Krunalkumar Mukeshkumar 
mailto:krunalkumarmukeshkumar.pa...@amd.com>>
Sent: Monday, November 7, 2022 1:35:01 PM
To: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Pan, Xinhui 
mailto:xinhui@amd.com>>; Koenig, Christian 
mailto:christian.koe...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; S, 
Shirish mailto:shiris...@amd.com>>; Patel, Krunalkumar 
Mukeshkumar 
mailto:krunalkumarmukeshkumar.pa...@amd.com>>
Subject: [PATCH] drm/amdgpu: Add support to clock gating for sdma 5.2.7

With this change it will add support for clock gating for sdma 5.2.7

- Additional changes are to re-arrange the chip version sequentially.

Signed-off-by: Krunal Patel 
mailto:krunalkumarmukeshkumar.pa...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 809eca54fc61..404b255cb4e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1647,12 +1647,13 @@ static int sdma_v5_2_set_clockgating_state(void *handle,

 switch (adev->ip_versions[SDMA0_HWIP][0]) {
 case IP_VERSION(5, 2, 0):
-   case IP_VERSION(5, 2, 2):
 case IP_VERSION(5, 2, 1):
+   case IP_VERSION(5, 2, 2):
+   case IP_VERSION(5, 2, 3):
 case IP_VERSION(5, 2, 4):
 case IP_VERSION(5, 2, 5):
 case IP_VERSION(5, 2, 6):
-   case IP_VERSION(5, 2, 3):
+   case IP_VERSION(5, 2, 7):
 sdma_v5_2_update_medium_grain_clock_gating(adev,
 state == AMD_CG_STATE_GATE);
 sdma_v5_2_update_medium_grain_light_sleep(adev,
--
2.25.1

RE: [PATCH] drm/amdgpu: add vram reservation logic based on vram_usagebyfirmware_v2_2

[Liu01, Tong (Esther)]

[AMD Official Use Only - General]

Hi @Koenig, Christian,

Removed the code format style warning base on the checkpatch.pl script. Please 
help me review the new patch below, thanks!

Kind regards,
Esther

-Original Message-
From: Tong Liu01  
Sent: 2022年11月8日星期二 上午10:47
To: amd-gfx@lists.freedesktop.org
Cc: Andrey Grodzovsky ; Quan, Evan 
; Chen, Horace ; Tuikov, Luben 
; Koenig, Christian ; Deucher, 
Alexander ; Xiao, Jack ; Zhang, 
Hawking ; Liu, Monk ; Xu, Feifei 
; Wang, Yang(Kevin) ; Liu01, Tong 
(Esther) 
Subject: [PATCH] drm/amdgpu: add vram reservation logic based on 
vram_usagebyfirmware_v2_2

Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR 
region firstly to make sure TMR can be allocated at 2MB

Signed-off-by: Tong Liu01 
---
 .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 106 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   |  50 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |   5 +
 drivers/gpu/drm/amd/include/atomfirmware.h|  62 --
 4 files changed, 192 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
index b81b77a9efa6..239c621feb0a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -101,39 +101,99 @@ void amdgpu_atomfirmware_scratch_regs_init(struct 
amdgpu_device *adev)
}
 }
 
+static int amdgpu_atomfirmware_allocate_fb_v2_1(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_1 *firmware_usage_v2_1,
+   int *usage_bytes)
+{
+   uint32_t start_addr, size;
+
+   DRM_DEBUG("atom firmware v2_1 requested %08x %dkb fw %dkb drv\n",
+   le32_to_cpu(firmware_usage_v2_1->start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb),
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb));
+
+   start_addr = le32_to_cpu(firmware_usage_v2_1->start_address_in_kb);
+   size = le16_to_cpu(firmware_usage_v2_1->used_by_firmware_in_kb);
+
+   if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
+   (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
+   ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = size << 10;
+   /* Use the default scratch size */
+   *usage_bytes = 0;
+   } else {
+   *usage_bytes =
+   le16_to_cpu(firmware_usage_v2_1->used_by_driver_in_kb) 
<< 10;
+   }
+   return 0;
+}
+
+static int amdgpu_atomfirmware_allocate_fb_v2_2(struct amdgpu_device *adev,
+   struct vram_usagebyfirmware_v2_2 *firmware_usage_v2_2,
+   int *usage_bytes)
+{
+   uint32_t fw_start_addr, fw_size, drv_start_addr, drv_size;
+
+   DRM_DEBUG("atom requested fw start at %08x %dkb and drv start at %08x 
%dkb\n",
+   le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb),
+   le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb),
+   
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb),
+   le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb));
+
+   fw_start_addr = 
le32_to_cpu(firmware_usage_v2_2->fw_region_start_address_in_kb);
+   fw_size = le16_to_cpu(firmware_usage_v2_2->used_by_firmware_in_kb);
+
+   drv_start_addr = 
le32_to_cpu(firmware_usage_v2_2->driver_region0_start_address_in_kb);
+   drv_size = 
+le32_to_cpu(firmware_usage_v2_2->used_by_driver_region0_in_kb);
+
+   if ((uint32_t)(fw_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 
30)) == 0) {
+   /* Firmware request VRAM reservation for SR-IOV */
+   adev->mman.fw_vram_usage_start_offset = (fw_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.fw_vram_usage_size = fw_size << 10;
+   }
+
+   if ((uint32_t)(drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 
<< 30)) == 0) {
+   /* driver request VRAM reservation for SR-IOV */
+   adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
+   (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
+   adev->mman.drv_vram_usage_size = drv_size << 10;
+   }
+
+   *usage_bytes = 0;
+   return 0;
+}
+
 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)  {
struct atom_context *ctx = adev->mode_info.atom_context;
int index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
vram_usagebyfirmware);
-   struct vram_usagebyfirmware_v