[PATCH] drm/amd/pm: typo fix (CUSTOM -> COMPUTE)
The "COMPUTE" was wrongly spelled as "CUSTOM". Change-Id: I44a6c93ea8badec2af883eb5b39261789baba036 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 3fb70cac72ea..23d0dc31789f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -220,7 +220,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: Return -EINVAL when whole gpu reset happened
If CS init return -ECANCELED, UMD will free and create new context.
Job in this new context could conitnue exexcuting. In the case of
BACO or mode 1, we can't allow this happpen. Because VRAM has lost
after whole gpu reset, the job can't guarantee to succeed.
Signed-off-by: Liu ChengZhe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 85e48c29a57c..2a98f58134ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -120,6 +120,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
uint64_t *chunk_array;
unsigned size, num_ibs = 0;
uint32_t uf_offset = 0;
+ uint32_t vramlost_count = 0;
int i;
int ret;
@@ -140,7 +141,11 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
/* skip guilty context job */
if (atomic_read(&p->ctx->guilty) == 1) {
- ret = -ECANCELED;
+ vramlost_count = atomic_read(&p->adev->vram_lost_counter);
+ if (p->ctx->vram_lost_counter != vramlost_count)
+ ret = -EINVAL;
+ else
+ ret = -ECANCELED;
goto free_chunk;
}
@@ -246,7 +251,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
goto free_all_kdata;
if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
- ret = -ECANCELED;
+ ret = -EINVAL;
goto free_all_kdata;
}
--
2.25.1
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Re: [PATCH] drm/amdgpu: Return -EINVAL when whole gpu reset happened
Am 09.12.20 um 10:46 schrieb Liu ChengZhe:
If CS init return -ECANCELED, UMD will free and create new context.
Job in this new context could conitnue exexcuting. In the case of
BACO or mode 1, we can't allow this happpen. Because VRAM has lost
after whole gpu reset, the job can't guarantee to succeed.
NAK, this is intentional.
When ECANCELED is returned UMD should create new context after a GPU
reset to get back into an usable state and continue to submit jobs.
Regards,
Christian.
Signed-off-by: Liu ChengZhe
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 85e48c29a57c..2a98f58134ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -120,6 +120,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p, union drm_amdgpu_cs
uint64_t *chunk_array;
unsigned size, num_ibs = 0;
uint32_t uf_offset = 0;
+ uint32_t vramlost_count = 0;
int i;
int ret;
@@ -140,7 +141,11 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
/* skip guilty context job */
if (atomic_read(&p->ctx->guilty) == 1) {
- ret = -ECANCELED;
+ vramlost_count = atomic_read(&p->adev->vram_lost_counter);
+ if (p->ctx->vram_lost_counter != vramlost_count)
+ ret = -EINVAL;
+ else
+ ret = -ECANCELED;
goto free_chunk;
}
@@ -246,7 +251,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
goto free_all_kdata;
if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
- ret = -ECANCELED;
+ ret = -EINVAL;
goto free_all_kdata;
}
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Re: [PATCH v2] [PATCH] drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs
Am 08.12.20 um 21:16 schrieb Andrey Grodzovsky:
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs
was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation
and amdgpu_gem_object_funcs setting into single function called
from both code paths.
Fixes: d693def4fd1c ("drm: Remove obsolete GEM and PRIME callbacks
from struct drm_driver")
v2: Use use amdgpu_gem_object_create() directly
Signed-off-by: Andrey Grodzovsky
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 8 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 41 -
2 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index e5919ef..e42175e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -424,6 +424,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct
dma_buf *dma_buf)
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_bo *bo;
struct amdgpu_bo_param bp;
+ struct drm_gem_object *gobj;
int ret;
memset(&bp, 0, sizeof(bp));
@@ -434,17 +435,20 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct
dma_buf *dma_buf)
bp.type = ttm_bo_type_sg;
bp.resv = resv;
dma_resv_lock(resv, NULL);
- ret = amdgpu_bo_create(adev, &bp, &bo);
+ ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_CPU,
+ 0, ttm_bo_type_sg, resv, &gobj);
if (ret)
goto error;
+ bo = gem_to_amdgpu_bo(gobj);
bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
if (dma_buf->ops != &amdgpu_dmabuf_ops)
bo->prime_shared_count = 1;
dma_resv_unlock(resv);
- return &bo->tbo.base;
+ return gobj;
error:
dma_resv_unlock(resv);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index c9f94fb..ccf4d80 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -70,26 +70,12 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev,
unsigned long size,
bp.type = type;
bp.resv = resv;
bp.preferred_domain = initial_domain;
-retry:
bp.flags = flags;
bp.domain = initial_domain;
r = amdgpu_bo_create(adev, &bp, &bo);
- if (r) {
- if (r != -ERESTARTSYS) {
- if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
- flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
- goto retry;
- }
-
- if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
- initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
- goto retry;
- }
- DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u,
%d)\n",
- size, initial_domain, alignment, r);
- }
+ if (r)
return r;
- }
+
*obj = &bo->tbo.base;
(*obj)->funcs = &amdgpu_gem_object_funcs;
@@ -239,7 +225,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
uint64_t size = args->in.bo_size;
struct dma_resv *resv = NULL;
struct drm_gem_object *gobj;
- uint32_t handle;
+ uint32_t handle, initial_domain;
int r;
/* reject invalid gem flags */
@@ -283,9 +269,28 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void
*data,
resv = vm->root.base.bo->tbo.base.resv;
}
+retry:
+ initial_domain = (u32)(0x & args->in.domains);
r = amdgpu_gem_object_create(adev, size, args->in.alignment,
-(u32)(0x & args->in.domains),
+initial_domain,
flags, ttm_bo_type_device, resv, &gobj);
+ if (r) {
+ if (r != -ERESTARTSYS) {
+ if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
+ flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+ goto retry;
+ }
+
+ if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
+ initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
+ goto retry;
+ }
+ DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u,
%d)\n",
+ size, initial_domain, args->in.alignment, r);
+ }
+ return r;
+ }
+
if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
[PATCH] drm/amdkfd: correct pipe offset calculation
Correct pipe offset calculation in is_pipe_enabled function,
it should be done in queues.
Signed-off-by: Jiansong Chen
Change-Id: I826aa532ca1e5073e3329212a8096f8f5a0be057
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c579615451ba..c37e9c4b1fb4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -72,8 +72,8 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum
kfd_queue_type type)
static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int
pipe)
{
int i;
- int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
- + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
+ int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec
+ + pipe) * dqm->dev->shared_resources.num_queue_per_pipe;
/* queue is available for KFD usage if bit is 1 */
for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
--
2.25.1
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RE: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround
[AMD Public Use]
Nitpick - you may want to send the message only during enable workflow. Apart
from that,
Series is Reviewed-by: Lijo Lazar
-Original Message-
From: Quan, Evan
Sent: Wednesday, December 9, 2020 9:49 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port
workaround
Fulfill the 2nd usb2.0 port workaround for sienna cichlid.
Change-Id: Id5a89a468787846ed0050b56cd318a9574185567
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 38 ++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 47d4f92d5ead..74cf027e4a41 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3247,6 +3247,42 @@ static int sienna_cichlid_gpo_control(struct smu_context
*smu,
return ret;
}
+
+static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context
+*smu) {
+ uint32_t smu_version;
+ int ret = 0;
+
+ ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+ if (ret)
+ return ret;
+
+ /*
+* Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
+* onwards PMFWs.
+*/
+ if (smu_version < 0x003A2D00)
+ return 0;
+
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_Enable2ndUSB20Port,
+
smu->smu_table.boot_values.firmware_caps &
ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
+ 1 : 0,
+ NULL);
+}
+
+static int sienna_cichlid_system_features_control(struct smu_context *smu,
+ bool en)
+{
+ int ret = 0;
+
+ ret = sienna_cichlid_notify_2nd_usb20_port(smu);
+ if (ret)
+ return ret;
+
+ return smu_v11_0_system_features_control(smu, en); }
+
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -3287,7 +3323,7 @@ static const struct pptable_funcs
sienna_cichlid_ppt_funcs = {
.set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
- .system_features_control = smu_v11_0_system_features_control,
+ .system_features_control = sienna_cichlid_system_features_control,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
.send_smc_msg = smu_cmn_send_smc_msg,
.init_display_count = NULL,
--
2.29.0
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[PATCH v2 1/2] drm/amd/pm: update the smu v11.5 smc header for vangogh
Add new PMFW message to notify RLC engine status. Signed-off-by: Xiaomeng Hou Change-Id: I7d714f8f245835cacb25e7cc4b248ddf183aebc1 --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 2 +- drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index 4a6d1381df16..41a49c1c0302 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -178,7 +178,7 @@ __SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \ __SMU_DUMMY_MAP(GET_UMC_FW_WA), \ __SMU_DUMMY_MAP(Mode1Reset), \ - __SMU_DUMMY_MAP(Spare), \ + __SMU_DUMMY_MAP(RlcPowerNotify), \ __SMU_DUMMY_MAP(SetHardMinIspiclkByFreq),\ __SMU_DUMMY_MAP(SetHardMinIspxclkByFreq),\ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \ diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h index 7e69b3bd311b..55d7892e4e0e 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h @@ -41,7 +41,7 @@ #define PPSMC_MSG_PowerUpIspByTile 0x7 #define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default #define PPSMC_MSG_PowerUpVcn 0x9 -#define PPSMC_MSG_spare0xA +#define PPSMC_MSG_RlcPowerNotify 0xA #define PPSMC_MSG_SetHardMinVcn0xB // For wireless display #define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz #define PPSMC_MSG_ActiveProcessNotify 0xD -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH v2 2/2] drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangogh
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is
unaware of RLC being halted and will continue sending messages, which would
eventually cause an ACPI hang. Use the system_feature_control interface to
notify SMU the status of RLC thus enable/disable DPM feature.
Signed-off-by: Xiaomeng Hou
Change-Id: I2f1a7de23df7315a7b220ba6d0a4bcaa75c93fea
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c| 17 -
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h| 4
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index ddaa6a705fa6..fb16d94b4031 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -64,7 +64,7 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
0),
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
0),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
0),
- MSG_MAP(Spare, PPSMC_MSG_spare,
0),
+ MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify,
0),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
0),
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk,
0),
MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
0),
@@ -722,6 +722,20 @@ static int
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
return 0;
}
+static int vangogh_system_features_control(struct smu_context *smu, bool en)
+{
+ int ret = 0;
+
+ if (en)
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_RlcPowerNotify,
+
RLC_STATUS_NORMAL, NULL);
+ else
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_RlcPowerNotify,
+ RLC_STATUS_OFF,
NULL);
+
+ return ret;
+}
+
static const struct pptable_funcs vangogh_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status,
@@ -750,6 +764,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.print_clk_levels = vangogh_print_fine_grain_clk,
.set_default_dpm_table = vangogh_set_default_dpm_tables,
.set_fine_grain_gfx_freq_parameters =
vangogh_set_fine_grain_gfx_freq_parameters,
+ .system_features_control = vangogh_system_features_control,
};
void vangogh_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
index 8756766296cd..eab455493076 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
@@ -32,4 +32,8 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu);
#define VANGOGH_UMD_PSTATE_SOCCLK 678
#define VANGOGH_UMD_PSTATE_FCLK 800
+/* RLC Power Status */
+#define RLC_STATUS_OFF 0
+#define RLC_STATUS_NORMAL 1
+
#endif
--
2.17.1
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RE: [PATCH v2 2/2] drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangogh
[AMD Public Use]
Series is Reviewed-by: Lijo Lazar
-Original Message-
From: Hou, Xiaomeng (Matthew)
Sent: Wednesday, December 9, 2020 6:20 PM
To: amd-gfx@lists.freedesktop.org
Cc: Huang, Ray ; Lazar, Lijo ; Wang,
Kevin(Yang) ; Hou, Xiaomeng (Matthew)
Subject: [PATCH v2 2/2] drm/amd/pm: inform SMU RLC status thus enable/disable
DPM feature for vangogh
RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW
is unaware of RLC being halted and will continue sending messages, which would
eventually cause an ACPI hang. Use the system_feature_control interface to
notify SMU the status of RLC thus enable/disable DPM feature.
Signed-off-by: Xiaomeng Hou
Change-Id: I2f1a7de23df7315a7b220ba6d0a4bcaa75c93fea
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c| 17 -
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h| 4
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index ddaa6a705fa6..fb16d94b4031 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -64,7 +64,7 @@ static struct cmn2asic_msg_mapping
vangogh_message_map[SMU_MSG_MAX_COUNT] = {
MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
0),
MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
0),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
0),
- MSG_MAP(Spare, PPSMC_MSG_spare,
0),
+ MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify,
0),
MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
0),
MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk,
0),
MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
0),
@@ -722,6 +722,20 @@ static int
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
return 0;
}
+static int vangogh_system_features_control(struct smu_context *smu,
+bool en) {
+ int ret = 0;
+
+ if (en)
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_RlcPowerNotify,
+
RLC_STATUS_NORMAL, NULL);
+ else
+ ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_RlcPowerNotify,
+ RLC_STATUS_OFF,
NULL);
+
+ return ret;
+}
+
static const struct pptable_funcs vangogh_ppt_funcs = {
.check_fw_status = smu_v11_0_check_fw_status, @@ -750,6 +764,7 @@
static const struct pptable_funcs vangogh_ppt_funcs = {
.print_clk_levels = vangogh_print_fine_grain_clk,
.set_default_dpm_table = vangogh_set_default_dpm_tables,
.set_fine_grain_gfx_freq_parameters =
vangogh_set_fine_grain_gfx_freq_parameters,
+ .system_features_control = vangogh_system_features_control,
};
void vangogh_set_ppt_funcs(struct smu_context *smu) diff --git
a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
index 8756766296cd..eab455493076 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
@@ -32,4 +32,8 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu);
#define VANGOGH_UMD_PSTATE_SOCCLK 678
#define VANGOGH_UMD_PSTATE_FCLK 800
+/* RLC Power Status */
+#define RLC_STATUS_OFF 0
+#define RLC_STATUS_NORMAL 1
+
#endif
--
2.17.1
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Re: [PATCH v2 2/2] drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangogh
On Wed, Dec 09, 2020 at 08:49:38PM +0800, Hou, Xiaomeng (Matthew) wrote:
> RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW
> is
> unaware of RLC being halted and will continue sending messages, which would
> eventually cause an ACPI hang. Use the system_feature_control interface to
> notify SMU the status of RLC thus enable/disable DPM feature.
>
> Signed-off-by: Xiaomeng Hou
> Change-Id: I2f1a7de23df7315a7b220ba6d0a4bcaa75c93fea
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c| 17 -
> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h| 4
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index ddaa6a705fa6..fb16d94b4031 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -64,7 +64,7 @@ static struct cmn2asic_msg_mapping
> vangogh_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile,
> 0),
> MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn,
> 0),
> MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,
> 0),
> - MSG_MAP(Spare, PPSMC_MSG_spare,
> 0),
> + MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify,
> 0),
> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn,
> 0),
> MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk,
> 0),
> MSG_MAP(ActiveProcessNotify,PPSMC_MSG_ActiveProcessNotify,
> 0),
> @@ -722,6 +722,20 @@ static int
> vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
> return 0;
> }
>
> +static int vangogh_system_features_control(struct smu_context *smu, bool en)
> +{
> + int ret = 0;
> +
> + if (en)
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_RlcPowerNotify,
> +
> RLC_STATUS_NORMAL, NULL);
> + else
> + ret = smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_RlcPowerNotify,
> + RLC_STATUS_OFF,
> NULL);
I think we can simplify the codes as below:
return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF,
NULL);
With that update, series are Reviewed-by: Huang Rui
> +
> + return ret;
> +}
> +
> static const struct pptable_funcs vangogh_ppt_funcs = {
>
> .check_fw_status = smu_v11_0_check_fw_status,
> @@ -750,6 +764,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
> .print_clk_levels = vangogh_print_fine_grain_clk,
> .set_default_dpm_table = vangogh_set_default_dpm_tables,
> .set_fine_grain_gfx_freq_parameters =
> vangogh_set_fine_grain_gfx_freq_parameters,
> + .system_features_control = vangogh_system_features_control,
> };
>
> void vangogh_set_ppt_funcs(struct smu_context *smu)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
> index 8756766296cd..eab455493076 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
> @@ -32,4 +32,8 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu);
> #define VANGOGH_UMD_PSTATE_SOCCLK 678
> #define VANGOGH_UMD_PSTATE_FCLK 800
>
> +/* RLC Power Status */
> +#define RLC_STATUS_OFF 0
> +#define RLC_STATUS_NORMAL 1
> +
> #endif
> --
> 2.17.1
>
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Re: [PATCH v3 6/7] drm: Validate encoder->possible_crtcs
On Thu, Dec 3, 2020 at 10:31 PM Alex Deucher wrote:
>
> On Tue, Sep 29, 2020 at 4:04 PM Alex Deucher wrote:
> >
> > On Tue, Sep 29, 2020 at 8:31 AM Jan Kiszka wrote:
> > >
> > > On 10.09.20 20:18, Deucher, Alexander wrote:
> > > > [AMD Public Use]
> > > >
> > > >
> > > >
> > > >> -Original Message-
> > > >> From: amd-gfx On Behalf Of
> > > >> Daniel Vetter
> > > >> Sent: Monday, September 7, 2020 3:15 AM
> > > >> To: Jan Kiszka ; amd-gfx list > > >> g...@lists.freedesktop.org>; Wentland, Harry ;
> > > >> Kazlauskas, Nicholas
> > > >> Cc: dri-devel ; intel-gfx > > >> g...@lists.freedesktop.org>; Thomas Zimmermann
> > > >> ; Ville Syrjala
> > > >> Subject: Re: [PATCH v3 6/7] drm: Validate encoder->possible_crtcs
> > > >>
> > > >> On Sun, Sep 6, 2020 at 1:19 PM Jan Kiszka wrote:
> > > >>>
> > > >>> On 11.02.20 18:04, Daniel Vetter wrote:
> > > On Tue, Feb 11, 2020 at 06:22:07PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > WARN if the encoder possible_crtcs is effectively empty or contains
> > > > bits for non-existing crtcs.
> > > >
> > > > v2: Move to drm_mode_config_validate() (Daniel)
> > > > Make the docs say we WARN when this is wrong (Daniel)
> > > > Extract full_crtc_mask()
> > > >
> > > > Cc: Thomas Zimmermann
> > > > Cc: Daniel Vetter
> > > > Signed-off-by: Ville Syrjälä
> > >
> > > When pushing the fixup needs to be applied before the validation
> > > patch here, because we don't want to anger the bisect gods.
> > >
> > > Reviewed-by: Daniel Vetter
> > >
> > > I think with the fixup we should be good enough with the existing
> > > nonsense in drivers. Fingers crossed.
> > > -Daniel
> > >
> > >
> > > > ---
> > > > drivers/gpu/drm/drm_mode_config.c | 27
> > > >> ++-
> > > > include/drm/drm_encoder.h | 2 +-
> > > > 2 files changed, 27 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_mode_config.c
> > > > b/drivers/gpu/drm/drm_mode_config.c
> > > > index afc91447293a..4c1b350ddb95 100644
> > > > --- a/drivers/gpu/drm/drm_mode_config.c
> > > > +++ b/drivers/gpu/drm/drm_mode_config.c
> > > > @@ -581,6 +581,29 @@ static void
> > > >> validate_encoder_possible_clones(struct drm_encoder *encoder)
> > > > encoder->possible_clones, encoder_mask); }
> > > >
> > > > +static u32 full_crtc_mask(struct drm_device *dev) {
> > > > +struct drm_crtc *crtc;
> > > > +u32 crtc_mask = 0;
> > > > +
> > > > +drm_for_each_crtc(crtc, dev)
> > > > +crtc_mask |= drm_crtc_mask(crtc);
> > > > +
> > > > +return crtc_mask;
> > > > +}
> > > > +
> > > > +static void validate_encoder_possible_crtcs(struct drm_encoder
> > > > +*encoder) {
> > > > +u32 crtc_mask = full_crtc_mask(encoder->dev);
> > > > +
> > > > +WARN((encoder->possible_crtcs & crtc_mask) == 0 ||
> > > > + (encoder->possible_crtcs & ~crtc_mask) != 0,
> > > > + "Bogus possible_crtcs: "
> > > > + "[ENCODER:%d:%s] possible_crtcs=0x%x (full crtc
> > > > mask=0x%x)\n",
> > > > + encoder->base.id, encoder->name,
> > > > + encoder->possible_crtcs, crtc_mask); }
> > > > +
> > > > void drm_mode_config_validate(struct drm_device *dev) {
> > > > struct drm_encoder *encoder;
> > > > @@ -588,6 +611,8 @@ void drm_mode_config_validate(struct
> > > >> drm_device *dev)
> > > > drm_for_each_encoder(encoder, dev)
> > > > fixup_encoder_possible_clones(encoder);
> > > >
> > > > -drm_for_each_encoder(encoder, dev)
> > > > +drm_for_each_encoder(encoder, dev) {
> > > > validate_encoder_possible_clones(encoder);
> > > > +validate_encoder_possible_crtcs(encoder);
> > > > +}
> > > > }
> > > > diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h
> > > > index 3741963b9587..b236269f41ac 100644
> > > > --- a/include/drm/drm_encoder.h
> > > > +++ b/include/drm/drm_encoder.h
> > > > @@ -142,7 +142,7 @@ struct drm_encoder {
> > > > * the bits for all &drm_crtc objects this encoder can be
> > > > connected to
> > > > * before calling drm_dev_register().
> > > > *
> > > > - * In reality almost every driver gets this wrong.
> > > > + * You will get a WARN if you get this wrong in the driver.
> > > > *
> > > > * Note that since CRTC objects can't be hotplugged the
> > > > assigned
> > > >> indices
> > > > * are stable and hence known before registering all objects.
> > > > --
> > > > 2.24.1
> > > >
> > >
> > > >>>
> > > >>> Triggers on an Advantech AIMB-228 (R1505G, 3 DP outputs):
> > > >>
> > > >> Adding amdgpu di
RE: [PATCH] drm/amdkfd: correct pipe offset calculation
[AMD Public Use]
Good catch. I guess we are just lucky that we always need to specify the mec to
0 in real use case.
The patch is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Jiansong Chen
Sent: Wednesday, December 9, 2020 19:59
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Kuehling, Felix
; Chen, Jiansong (Simon)
Subject: [PATCH] drm/amdkfd: correct pipe offset calculation
Correct pipe offset calculation in is_pipe_enabled function, it should be done
in queues.
Signed-off-by: Jiansong Chen
Change-Id: I826aa532ca1e5073e3329212a8096f8f5a0be057
---
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index c579615451ba..c37e9c4b1fb4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -72,8 +72,8 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum
kfd_queue_type type) static bool is_pipe_enabled(struct device_queue_manager
*dqm, int mec, int pipe) {
int i;
- int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
- + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
+ int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec
+ + pipe) * dqm->dev->shared_resources.num_queue_per_pipe;
/* queue is available for KFD usage if bit is 1 */
for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
--
2.25.1
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Re: [PATCH] drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling clocks
[AMD Official Use Only - Internal Distribution Only]
Acked-by: Alex Deucher
From: Quan, Evan
Sent: Wednesday, December 9, 2020 1:35 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan
Subject: [PATCH] drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling
clocks
Fulfill the UMD PSTATE profiling clocks of sienna cichlid.
Change-Id: Ib9078c73d3fbd786080449255645ae8b9f879092
Signed-off-by: Evan Quan
---
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 ++
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 74cf027e4a41..3fb70cac72ea 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1341,12 +1341,18 @@ static int sienna_cichlid_populate_umd_state_clk(struct
smu_context *smu)
pstate_table->gfxclk_pstate.min = gfx_table->min;
pstate_table->gfxclk_pstate.peak = gfx_table->max;
+ if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
+ pstate_table->gfxclk_pstate.standard =
SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
pstate_table->uclk_pstate.min = mem_table->min;
pstate_table->uclk_pstate.peak = mem_table->max;
+ if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
+ pstate_table->uclk_pstate.standard =
SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
pstate_table->socclk_pstate.min = soc_table->min;
pstate_table->socclk_pstate.peak = soc_table->max;
+ if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
+ pstate_table->socclk_pstate.standard =
SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
index 57e120c440ea..38cd0ece24f6 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h
@@ -29,6 +29,10 @@ typedef enum {
POWER_SOURCE_COUNT,
} POWER_SOURCE_e;
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK1825
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK960
+#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK1000
+
extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu);
#endif
--
2.29.0
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Re: [PATCH] drm/amd/pm: typo fix (CUSTOM -> COMPUTE)
[AMD Public Use] Reviewed-by: Alex Deucher From: Quan, Evan Sent: Wednesday, December 9, 2020 3:37 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander ; Quan, Evan Subject: [PATCH] drm/amd/pm: typo fix (CUSTOM -> COMPUTE) The "COMPUTE" was wrongly spelled as "CUSTOM". Change-Id: I44a6c93ea8badec2af883eb5b39261789baba036 Signed-off-by: Evan Quan --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 3fb70cac72ea..23d0dc31789f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -220,7 +220,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; -- 2.29.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/amdgpu: check number of gfx ring before init cp gfx
Check number of gfx ring, rather than asic type,
before cp gfx engine initialization so driver just
need to make sure number of gfx ring is initialized
correctly in gfx early_init phase. No need to add
additional asic type check everywhere when there is
new asic with gfx pipe removed.
Signed-off-by: Hawking Zhang
Reviewed-by: Feifei Xu
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index fc9bb94eaaf4..ef430f285472 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1647,7 +1647,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device
*adev)
}
/* No CPG in Arcturus */
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
if (r)
return r;
@@ -3822,7 +3822,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
gfx_v9_0_enable_gui_idle_interrupt(adev, false);
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
/* legacy firmware loading */
r = gfx_v9_0_cp_gfx_load_microcode(adev);
if (r)
@@ -3838,7 +3838,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
if (r)
return r;
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
r = gfx_v9_0_cp_gfx_resume(adev);
if (r)
return r;
@@ -3848,7 +3848,7 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
if (r)
return r;
- if (adev->asic_type != CHIP_ARCTURUS) {
+ if (adev->gfx.num_gfx_rings) {
ring = &adev->gfx.gfx_ring[0];
r = amdgpu_ring_test_helper(ring);
if (r)
@@ -3884,7 +3884,7 @@ static void gfx_v9_0_init_tcp_config(struct amdgpu_device
*adev)
static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
{
- if (adev->asic_type != CHIP_ARCTURUS)
+ if (adev->gfx.num_gfx_rings)
gfx_v9_0_cp_gfx_enable(adev, enable);
gfx_v9_0_cp_compute_enable(adev, enable);
}
@@ -4025,7 +4025,7 @@ static int gfx_v9_0_soft_reset(void *handle)
/* stop the rlc */
adev->gfx.rlc.funcs->stop(adev);
- if (adev->asic_type != CHIP_ARCTURUS)
+ if (adev->gfx.num_gfx_rings)
/* Disable GFX parsing/prefetching */
gfx_v9_0_cp_gfx_enable(adev, false);
--
2.17.1
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[PATCH 2/3] drm/amdgpu: remove unnecessary asic type check
The number of crtc should be 0 for ASICs that don't
have display engine. Remove the unnecessary asic type
check then.
Signed-off-by: Hawking Zhang
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 07126b2b46c2..f34d39e43ea4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1579,13 +1579,10 @@ static int gmc_v9_0_hw_init(void *handle)
gmc_v9_0_init_golden_registers(adev);
if (adev->mode_info.num_crtc) {
- if (adev->asic_type != CHIP_ARCTURUS) {
- /* Lockout access through VGA aperture*/
- WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL,
VGA_MEMORY_DISABLE, 1);
-
- /* disable VGA render */
- WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL,
VGA_VSTATUS_CNTL, 0);
- }
+ /* Lockout access through VGA aperture*/
+ WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
+ /* disable VGA render */
+ WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
}
amdgpu_device_program_register_sequence(adev,
--
2.17.1
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[PATCH 3/3] drm/amdgpu: check gfx pipe availability before toggling its interrupts
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0
are only applicable to me0 pipe0.
For ASICs that have gfx pipe removed, don't toggle
those bits.
Signed-off-by: Hawking Zhang
Reviewed-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ef430f285472..5f4805e4d04a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2633,7 +2633,14 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct
amdgpu_device *adev)
static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
- u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
+ u32 tmp;
+
+ /* don't toggle interrupts that are only applicable
+* to me0 pipe0 on AISCs that have me0 removed */
+ if (!adev->gfx.num_gfx_rings)
+ return;
+
+ tmp= RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
enable ? 1 : 0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
enable ? 1 : 0);
--
2.17.1
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Re: [PATCH] drm/amdgpu: take runtime pm reference when we attach a buffer
On Fri, Dec 4, 2020 at 3:41 PM Alex Deucher wrote: > > And drop it when we detach. If the shared buffer is in vram, > we need to make sure we don't put the device into runtime > suspend. > > Signed-off-by: Alex Deucher Ping? Any thoughts on this? We really only need this for p2p since device memory in involved, but I'm not sure of the best way to handle that. Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 ++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c > index 5b465ab774d1..f63f182f37f9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c > @@ -40,6 +40,7 @@ > #include > #include > #include > +#include > > /** > * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation > @@ -187,9 +188,13 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, > if (attach->dev->driver == adev->dev->driver) > return 0; > > + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); > + if (r < 0) > + goto out; > + > r = amdgpu_bo_reserve(bo, false); > if (unlikely(r != 0)) > - return r; > + goto out; > > /* > * We only create shared fences for internal use, but importers > @@ -201,11 +206,15 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, > */ > r = __dma_resv_make_exclusive(bo->tbo.base.resv); > if (r) > - return r; > + goto out; > > bo->prime_shared_count++; > amdgpu_bo_unreserve(bo); > return 0; > + > +out: > + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); > + return r; > } > > /** > @@ -225,6 +234,9 @@ static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf, > > if (attach->dev->driver != adev->dev->driver && > bo->prime_shared_count) > bo->prime_shared_count--; > + > + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); > + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); > } > > /** > -- > 2.25.4 > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH v2 13/20] drm/nouveau: Remove references to struct drm_device.pdev
Hi,
On Tue, Dec 01, 2020 at 11:35:35AM +0100, Thomas Zimmermann wrote:
> Using struct drm_device.pdev is deprecated. Convert nouveau to struct
> drm_device.dev. No functional changes.
>
> Signed-off-by: Thomas Zimmermann
> Cc: Ben Skeggs
> ---
> drivers/gpu/drm/nouveau/dispnv04/arb.c | 12 +++-
> drivers/gpu/drm/nouveau/dispnv04/disp.h | 14 --
> drivers/gpu/drm/nouveau/dispnv04/hw.c | 10 ++
> drivers/gpu/drm/nouveau/nouveau_abi16.c | 7 ---
> drivers/gpu/drm/nouveau/nouveau_acpi.c | 2 +-
> drivers/gpu/drm/nouveau/nouveau_bios.c | 11 ---
> drivers/gpu/drm/nouveau/nouveau_connector.c | 10 ++
> drivers/gpu/drm/nouveau/nouveau_drm.c | 5 ++---
> drivers/gpu/drm/nouveau/nouveau_fbcon.c | 6 --
> drivers/gpu/drm/nouveau/nouveau_vga.c | 20
> 10 files changed, 58 insertions(+), 39 deletions(-)
>
I believe there's a use of drm_device.pdev in
drivers/gpu/drm/nouveau/dispnv04/dfp.c in the
nv04_dfp_update_backlight() function.
Other than that, this looks good to me.
> diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c
> b/drivers/gpu/drm/nouveau/dispnv04/arb.c
> index 9d4a2d97507e..1d3542d6006b 100644
> --- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
> +++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
> @@ -200,16 +200,17 @@ nv04_update_arb(struct drm_device *dev, int VClk, int
> bpp,
> int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
> int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
> uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1);
> + struct pci_dev *pdev = to_pci_dev(dev->dev);
>
> sim_data.pclk_khz = VClk;
> sim_data.mclk_khz = MClk;
> sim_data.nvclk_khz = NVClk;
> sim_data.bpp = bpp;
> sim_data.two_heads = nv_two_heads(dev);
> - if ((dev->pdev->device & 0x) == 0x01a0 /*CHIPSET_NFORCE*/ ||
> - (dev->pdev->device & 0x) == 0x01f0 /*CHIPSET_NFORCE2*/) {
> + if ((pdev->device & 0x) == 0x01a0 /*CHIPSET_NFORCE*/ ||
> + (pdev->device & 0x) == 0x01f0 /*CHIPSET_NFORCE2*/) {
> uint32_t type;
> - int domain = pci_domain_nr(dev->pdev->bus);
> + int domain = pci_domain_nr(pdev->bus);
>
> pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
> 0x7c, &type);
> @@ -251,11 +252,12 @@ void
> nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int
> *lwm)
> {
> struct nouveau_drm *drm = nouveau_drm(dev);
> + struct pci_dev *pdev = to_pci_dev(dev->dev);
>
> if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)
> nv04_update_arb(dev, vclk, bpp, burst, lwm);
> - else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
> - (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
> + else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
> + (pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
> *burst = 128;
> *lwm = 0x0480;
> } else
> diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h
> b/drivers/gpu/drm/nouveau/dispnv04/disp.h
> index 5ace5e906949..f0a24126641a 100644
> --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
> +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
> @@ -130,7 +130,7 @@ static inline bool
> nv_two_heads(struct drm_device *dev)
> {
> struct nouveau_drm *drm = nouveau_drm(dev);
> - const int impl = dev->pdev->device & 0x0ff0;
> + const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
>
> if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl
> != 0x0100 &&
> impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
> @@ -142,14 +142,14 @@ nv_two_heads(struct drm_device *dev)
> static inline bool
> nv_gf4_disp_arch(struct drm_device *dev)
> {
> - return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110;
> + return nv_two_heads(dev) && (to_pci_dev(dev->dev)->device & 0x0ff0) !=
> 0x0110;
> }
>
> static inline bool
> nv_two_reg_pll(struct drm_device *dev)
> {
> struct nouveau_drm *drm = nouveau_drm(dev);
> - const int impl = dev->pdev->device & 0x0ff0;
> + const int impl = to_pci_dev(dev->dev)->device & 0x0ff0;
>
> if (impl == 0x0310 || impl == 0x0340 || drm->client.device.info.family
> >= NV_DEVICE_INFO_V0_CURIE)
> return true;
> @@ -160,9 +160,11 @@ static inline bool
> nv_match_device(struct drm_device *dev, unsigned device,
> unsigned sub_vendor, unsigned sub_device)
> {
> - return dev->pdev->device == device &&
> - dev->pdev->subsystem_vendor == sub_vendor &&
> - dev->pdev->subsystem_device == sub_device;
> + struct pci_dev *pdev = to_pci_dev(dev->dev);
> +
> + return pdev->device == device &&
> + pdev->subsystem_vendor == sub_vendor &&
> + pdev->subsystem_dev
[PATCH] amdgpu: don't treat BAR resize failure due to unsupported requested size as an error
On the resize attempt failing with -EINVAL, instead report an informational
message indicating that the requested BAR size is not listed as supported by
the VBIOS.
Without this, as I have an RX 5600 XT which lists only 256MB, 512MB and
1024MB as supported, I see
[drm:amdgpu_device_resize_fb_bar] *ERROR* Problem resizing BAR0 (-22).
Signed-off-by: Darren Salt
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 355fa0057c26..d80ba03913a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1136,6 +1136,8 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device
*adev)
r = pci_resize_resource(adev->pdev, 0, rbar_size);
if (r == -ENOSPC)
DRM_INFO("Not enough PCI address space for a large BAR.");
+ else if (r == -EINVAL)
+ DRM_INFO("VBIOS does not support exposing all VRAM via a large
BAR.");
else if (r && r != -ENOTSUPP)
DRM_ERROR("Problem resizing BAR0 (%d).", r);
--
2.20.1
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[PATCH 0/1] Timeout handler now returns a value
The driver's timeout handler now returns a value back up to DRM. This patch doesn't change current behaviour. I request it'd be applied so that Andrey G. can take advantage of the value sent back up to DRM from the GPU driver. I'm still working on the last patch which takes advantage of this patch, and as such they are separate works. This patch can be applied safely without changing the current DRM behaviour. Luben Tuikov (1): drm/scheduler: Job timeout handler returns status (v2) drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++-- drivers/gpu/drm/etnaviv/etnaviv_sched.c | 10 +++- drivers/gpu/drm/lima/lima_sched.c | 4 +++- drivers/gpu/drm/panfrost/panfrost_job.c | 9 --- drivers/gpu/drm/scheduler/sched_main.c | 4 +--- drivers/gpu/drm/v3d/v3d_sched.c | 32 + include/drm/gpu_scheduler.h | 20 +--- 7 files changed, 57 insertions(+), 28 deletions(-) -- 2.29.2.404.ge67fbf927d ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/1] drm/scheduler: Job timeout handler returns status (v2)
This patch does not change current behaviour.
The driver's job timeout handler now returns
status indicating back to the DRM layer whether
the task (job) was successfully aborted or whether
more time should be given to the task to complete.
Default behaviour as of this patch, is preserved,
except in obvious-by-comment case in the Panfrost
driver, as documented below.
All drivers which make use of the
drm_sched_backend_ops' .timedout_job() callback
have been accordingly renamed and return the
would've-been default value of
DRM_TASK_STATUS_ALIVE to restart the task's
timeout timer--this is the old behaviour, and
is preserved by this patch.
In the case of the Panfrost driver, its timedout
callback correctly first checks if the job had
completed in due time and if so, it now returns
DRM_TASK_STATUS_COMPLETE to notify the DRM layer
that the task can be moved to the done list, to be
freed later. In the other two subsequent checks,
the value of DRM_TASK_STATUS_ALIVE is returned, as
per the default behaviour.
A more involved driver's solutions can be had
in subequent patches.
v2: Use enum as the status of a driver's job
timeout callback method.
Cc: Alexander Deucher
Cc: Andrey Grodzovsky
Cc: Christian König
Cc: Daniel Vetter
Cc: Lucas Stach
Cc: Russell King
Cc: Christian Gmeiner
Cc: Qiang Yu
Cc: Rob Herring
Cc: Tomeu Vizoso
Cc: Steven Price
Cc: Alyssa Rosenzweig
Cc: Eric Anholt
Reported-by: kernel test robot
Signed-off-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 6 +++--
drivers/gpu/drm/etnaviv/etnaviv_sched.c | 10 +++-
drivers/gpu/drm/lima/lima_sched.c | 4 +++-
drivers/gpu/drm/panfrost/panfrost_job.c | 9 ---
drivers/gpu/drm/scheduler/sched_main.c | 4 +---
drivers/gpu/drm/v3d/v3d_sched.c | 32 +
include/drm/gpu_scheduler.h | 20 +---
7 files changed, 57 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index ff48101bab55..a111326cbdde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -28,7 +28,7 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
-static void amdgpu_job_timedout(struct drm_sched_job *s_job)
+static enum drm_task_status amdgpu_job_timedout(struct drm_sched_job *s_job)
{
struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
struct amdgpu_job *job = to_amdgpu_job(s_job);
@@ -41,7 +41,7 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent))
{
DRM_ERROR("ring %s timeout, but soft recovered\n",
s_job->sched->name);
- return;
+ return DRM_TASK_STATUS_ALIVE;
}
amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
@@ -53,10 +53,12 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
if (amdgpu_device_should_recover_gpu(ring->adev)) {
amdgpu_device_gpu_recover(ring->adev, job);
+ return DRM_TASK_STATUS_ALIVE;
} else {
drm_sched_suspend_timeout(&ring->sched);
if (amdgpu_sriov_vf(adev))
adev->virt.tdr_debug = true;
+ return DRM_TASK_STATUS_ALIVE;
}
}
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
index cd46c882269c..c49516942328 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c
@@ -82,7 +82,8 @@ static struct dma_fence *etnaviv_sched_run_job(struct
drm_sched_job *sched_job)
return fence;
}
-static void etnaviv_sched_timedout_job(struct drm_sched_job *sched_job)
+static enum drm_task_status etnaviv_sched_timedout_job(struct drm_sched_job
+ *sched_job)
{
struct etnaviv_gem_submit *submit = to_etnaviv_submit(sched_job);
struct etnaviv_gpu *gpu = submit->gpu;
@@ -120,9 +121,16 @@ static void etnaviv_sched_timedout_job(struct
drm_sched_job *sched_job)
drm_sched_resubmit_jobs(&gpu->sched);
+ /* Tell the DRM scheduler that this task needs
+* more time.
+*/
+ drm_sched_start(&gpu->sched, true);
+ return DRM_TASK_STATUS_ALIVE;
+
out_no_timeout:
/* restart scheduler after GPU is usable again */
drm_sched_start(&gpu->sched, true);
+ return DRM_TASK_STATUS_ALIVE;
}
static void etnaviv_sched_free_job(struct drm_sched_job *sched_job)
diff --git a/drivers/gpu/drm/lima/lima_sched.c
b/drivers/gpu/drm/lima/lima_sched.c
index 63b4c5643f9c..66d9236b8760 100644
--- a/drivers/gpu/drm/lima/lima_sched.c
+++ b/drivers/gpu/drm/lima/lima_sched.c
@@ -415,7 +415,7 @@ static void lima_sched_build_error_task_list(struct
lima_sched_task *task)
mutex_unlock(&dev->error_task_list_lock);
}
-static v
RE: [PATCH] drm/amdgpu: Return -EINVAL when whole gpu reset happened
[AMD Public Use]
Yeah, we discussed this issue again. We think it's better UMD make some changes
instead of changing in KMD. If FLR happened, it's OK for UMD create new context
and continue to submit jobs.
However, if BACO or mode 1 reset happens, of course UMD could also submit jobs,
but these jobs can't use any resource create before the reset, including page
table.
Because all the contents in VRAM has lost after BACO or mode 1 reset, which
including APP's buffer.
-Original Message-
From: Koenig, Christian
Sent: Wednesday, December 9, 2020 6:06 PM
To: Liu, Cheng Zhe ; amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Deucher, Alexander
; Xiao, Jack ; Zhang, Hawking
; Xu, Feifei ; Wang, Kevin(Yang)
; Yuan, Xiaojie
Subject: Re: [PATCH] drm/amdgpu: Return -EINVAL when whole gpu reset happened
Am 09.12.20 um 10:46 schrieb Liu ChengZhe:
> If CS init return -ECANCELED, UMD will free and create new context.
> Job in this new context could conitnue exexcuting. In the case of BACO
> or mode 1, we can't allow this happpen. Because VRAM has lost after
> whole gpu reset, the job can't guarantee to succeed.
NAK, this is intentional.
When ECANCELED is returned UMD should create new context after a GPU reset to
get back into an usable state and continue to submit jobs.
Regards,
Christian.
>
> Signed-off-by: Liu ChengZhe
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 85e48c29a57c..2a98f58134ed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -120,6 +120,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
> *p, union drm_amdgpu_cs
> uint64_t *chunk_array;
> unsigned size, num_ibs = 0;
> uint32_t uf_offset = 0;
> + uint32_t vramlost_count = 0;
> int i;
> int ret;
>
> @@ -140,7 +141,11 @@ static int amdgpu_cs_parser_init(struct
> amdgpu_cs_parser *p, union drm_amdgpu_cs
>
> /* skip guilty context job */
> if (atomic_read(&p->ctx->guilty) == 1) {
> - ret = -ECANCELED;
> + vramlost_count = atomic_read(&p->adev->vram_lost_counter);
> + if (p->ctx->vram_lost_counter != vramlost_count)
> + ret = -EINVAL;
> + else
> + ret = -ECANCELED;
> goto free_chunk;
> }
>
> @@ -246,7 +251,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
> *p, union drm_amdgpu_cs
> goto free_all_kdata;
>
> if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
> - ret = -ECANCELED;
> + ret = -EINVAL;
> goto free_all_kdata;
> }
>
___
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RE: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround
[AMD Official Use Only - Internal Distribution Only]
Hi Evan,
Besides Navi21, other Navi2x Asics reuse sienna_cichlid_ppt.c and the
callbacks, have you taken their user cases into consideration?
Thanks!
Regards,
Jiansong
-Original Message-
From: amd-gfx On Behalf Of Evan Quan
Sent: Wednesday, December 9, 2020 12:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port
workaround
Fulfill the 2nd usb2.0 port workaround for sienna cichlid.
Change-Id: Id5a89a468787846ed0050b56cd318a9574185567
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 38 ++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 47d4f92d5ead..74cf027e4a41 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3247,6 +3247,42 @@ static int sienna_cichlid_gpo_control(struct smu_context
*smu,
return ret;
}
+
+static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context
+*smu) {
+uint32_t smu_version;
+int ret = 0;
+
+ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
+if (ret)
+return ret;
+
+/*
+ * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
+ * onwards PMFWs.
+ */
+if (smu_version < 0x003A2D00)
+return 0;
+
+return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_Enable2ndUSB20Port,
+ smu->smu_table.boot_values.firmware_caps &
ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
+ 1 : 0,
+ NULL);
+}
+
+static int sienna_cichlid_system_features_control(struct smu_context *smu,
+ bool en)
+{
+int ret = 0;
+
+ret = sienna_cichlid_notify_2nd_usb20_port(smu);
+if (ret)
+return ret;
+
+return smu_v11_0_system_features_control(smu, en); }
+
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
@@ -3287,7 +3323,7 @@ static const struct pptable_funcs
sienna_cichlid_ppt_funcs = {
.set_driver_table_location = smu_v11_0_set_driver_table_location,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
-.system_features_control = smu_v11_0_system_features_control,
+.system_features_control = sienna_cichlid_system_features_control,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
.send_smc_msg = smu_cmn_send_smc_msg,
.init_display_count = NULL,
--
2.29.0
___
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Recall: [PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround
Chen, Jiansong (Simon) would like to recall the message, "[PATCH 5/5] drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround". ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 1/3] drm/amd/display: Add module parameter for freesync video mode
[Why&How] Adds a module parameter to enable experimental freesync video mode modeset optimization. Enabling this mode allows the driver to skip a full modeset when freesync compatible modes are requested by the userspace. This paramters also adds some standard modes based on the connected monitor's VRR range. Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 83ac06a3ec05..efbfee93c359 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -177,6 +177,7 @@ extern int amdgpu_gpu_recovery; extern int amdgpu_emu_mode; extern uint amdgpu_smu_memory_pool_size; extern uint amdgpu_dc_feature_mask; +extern uint amdgpu_exp_freesync_vid_mode; extern uint amdgpu_dc_debug_mask; extern uint amdgpu_dm_abm_level; extern struct amdgpu_mgpu_info mgpu_info; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b2a1dd7581bf..ece51ecd53d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -158,6 +158,7 @@ int amdgpu_mes; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; int amdgpu_tmz; +uint amdgpu_exp_freesync_vid_mode; int amdgpu_reset_method = -1; /* auto */ int amdgpu_num_kcq = -1; @@ -786,6 +787,17 @@ module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto, 0 = off (default), 1 = on)"); module_param_named(tmz, amdgpu_tmz, int, 0444); +/** + * DOC: experimental_freesync_video (uint) + * Enabled the optimization to adjust front porch timing to achieve seamless mode change experience + * when setting a freesync supported mode for which full modeset is not needed. + * The default value: 0 (off). + */ +MODULE_PARM_DESC( + experimental_freesync_video, + "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); +module_param_named(experimental_freesync_video, amdgpu_exp_freesync_vid_mode, uint, 0444); + /** * DOC: reset_method (int) * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/3] Experimental freesync video mode optimization
This patchset enables freesync video mode usecase where the userspace can request a freesync compatible video mode such that switching to this mode does not trigger blanking. This feature is guarded by a module parameter which is disabled by default. Enabling this paramters adds additional modes to the driver modelist, and also enables the optimization to skip modeset when using one of these modes. -- Aurabindo Pillai (3): drm/amd/display: Add module parameter for freesync video mode drm/amd/display: Add freesync video modes based on preferred modes drm/amd/display: Skip modeset for front porch change drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 12 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 366 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + 4 files changed, 363 insertions(+), 17 deletions(-) -- 2.25.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/3] drm/amd/display: Add freesync video modes based on preferred modes
[Why&How]
If experimental freesync video mode module parameter is enabled, add
few extra display modes into the driver's mode list corresponding to common
video frame rates. When userspace sets these modes, no modeset will be
performed (if current mode was one of freesync modes or the base freesync mode
based off which timings have been generated for the rest of the freesync modes)
since these modes only differ from the base mode with front porch timing.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 197 ++
1 file changed, 197 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fbff8d693e03..f699a3d41cad 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5178,6 +5178,69 @@ static void dm_enable_per_frame_crtc_master_sync(struct
dc_state *context)
set_master_stream(context->streams, context->stream_count);
}
+static struct drm_display_mode *
+get_highest_freesync_mode(struct amdgpu_dm_connector *aconnector,
+ bool use_probed_modes)
+{
+ struct drm_display_mode *m, *m_high = NULL;
+ u16 current_refresh, highest_refresh, preferred_mode_h,
preferred_mode_w;
+ struct list_head *list_head = use_probed_modes ?
+
&aconnector->base.probed_modes :
+ &aconnector->base.modes;
+
+ /*
+* Find the preferred mode
+*/
+
+ list_for_each_entry (m, list_head, head) {
+ if (!(m->type & DRM_MODE_TYPE_PREFERRED))
+ continue;
+
+ m_high = m;
+ preferred_mode_h = m_high->hdisplay;
+ preferred_mode_w = m_high->vdisplay;
+ highest_refresh = drm_mode_vrefresh(m_high);
+ break;
+ }
+
+ if (!m_high) {
+
+ /*
+* Probably an EDID with no preferred mode.
+* Fallback to first entry;
+*/
+ m_high = list_first_entry_or_null(&aconnector->base.modes,
+ struct drm_display_mode,
head);
+ if (!m_high)
+ return NULL;
+ else {
+ preferred_mode_h = m_high->hdisplay;
+ preferred_mode_w = m_high->vdisplay;
+ highest_refresh = drm_mode_vrefresh(m_high);
+ }
+ }
+
+ /*
+* Find the mode with highest refresh rate with same resolution.
+* For some monitors, preferred mode is not the mode with highest
+* supported refresh rate.
+*/
+ list_for_each_entry (m, list_head, head) {
+ current_refresh = drm_mode_vrefresh(m);
+
+ if (m->hdisplay == preferred_mode_h &&
+ m->vdisplay == preferred_mode_w &&
+ highest_refresh < current_refresh) {
+ highest_refresh = current_refresh;
+ preferred_mode_h = m->hdisplay;
+ preferred_mode_w = m->vdisplay;
+ m_high = m;
+ }
+ }
+
+ return m_high;
+}
+
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
@@ -7006,6 +7069,139 @@ static void amdgpu_dm_connector_ddc_get_modes(struct
drm_connector *connector,
}
}
+static bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
+ struct drm_display_mode *mode)
+{
+ struct drm_display_mode *m;
+
+ list_for_each_entry (m, &aconnector->base.probed_modes, head) {
+ if (m->clock == mode->clock &&
+ m->htotal == mode->htotal &&
+ m->vtotal == mode->vtotal &&
+ m->hdisplay == mode->hdisplay &&
+ m->vdisplay == mode->vdisplay &&
+ m->hsync_start == mode->hsync_start &&
+ m->vsync_start == mode->vsync_start &&
+ m->vsync_end == mode->vsync_end &&
+ m->hsync_end == mode->hsync_end)
+ return true;
+ }
+
+ return false;
+}
+
+static uint add_fs_modes(struct amdgpu_dm_connector *aconnector,
+struct detailed_data_monitor_range *range)
+{
+ const struct drm_display_mode *m, *m_save;
+ struct drm_display_mode *new_mode;
+ uint i;
+ uint64_t target_vtotal, target_vtotal_diff;
+ uint32_t new_modes_count = 0;
+ uint64_t num, den;
+
+ /* Standard FPS values
+*
+* 23.976 - TV/NTSC
+* 24 - Cinema
+* 25 - TV/PAL
+* 29.97 - TV/NTSC
+* 30 - TV/NTSC
+
[PATCH 3/3] drm/amd/display: Skip modeset for front porch change
[Why&How]
Inorder to enable freesync video mode, driver adds extra
modes based on preferred modes for common freesync frame rates.
When commiting these mode changes, a full modeset is not needed.
If the change in only in the front porch timing value, skip full
modeset and continue using the same stream.
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 169 --
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 +
2 files changed, 153 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f699a3d41cad..c8c72887906a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -217,6 +217,9 @@ static bool amdgpu_dm_psr_disable_all(struct
amdgpu_display_manager *dm);
static const struct drm_format_info *
amd_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+static bool
+is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
+struct drm_crtc_state *new_crtc_state);
/*
* dm_vblank_get_counter
*
@@ -5096,8 +5099,11 @@ copy_crtc_timing_for_drm_display_mode(const struct
drm_display_mode *src_mode,
static void
decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
const struct drm_display_mode
*native_mode,
- bool scale_enabled)
+ bool scale_enabled, bool fs_mode)
{
+ if (fs_mode)
+ return;
+
if (scale_enabled) {
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
} else if (native_mode->clock == drm_mode->clock &&
@@ -5241,6 +5247,24 @@ get_highest_freesync_mode(struct amdgpu_dm_connector
*aconnector,
return m_high;
}
+static bool is_freesync_video_mode(struct drm_display_mode *mode,
+ struct amdgpu_dm_connector *aconnector)
+{
+ struct drm_display_mode *high_mode;
+
+ high_mode = get_highest_freesync_mode(aconnector, false);
+ if (!high_mode)
+ return false;
+
+ if (high_mode->clock == 0 ||
+ high_mode->hdisplay != mode->hdisplay ||
+ high_mode->clock != mode->clock ||
+ !mode)
+ return false;
+ else
+ return true;
+}
+
static struct dc_stream_state *
create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
const struct drm_display_mode *drm_mode,
@@ -5253,17 +5277,21 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
const struct drm_connector_state *con_state =
dm_state ? &dm_state->base : NULL;
struct dc_stream_state *stream = NULL;
- struct drm_display_mode mode = *drm_mode;
+ struct drm_display_mode saved_mode, mode = *drm_mode;
+ struct drm_display_mode *freesync_mode = NULL;
bool native_mode_found = false;
bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
int mode_refresh;
int preferred_refresh = 0;
+ bool is_fs_vid_mode = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN)
struct dsc_dec_dpcd_caps dsc_caps;
#endif
uint32_t link_bandwidth_kbps;
-
struct dc_sink *sink = NULL;
+
+ memset(&saved_mode, 0, sizeof(struct drm_display_mode));
+
if (aconnector == NULL) {
DRM_ERROR("aconnector is NULL!\n");
return stream;
@@ -5316,20 +5344,33 @@ create_stream_for_sink(struct amdgpu_dm_connector
*aconnector,
*/
DRM_DEBUG_DRIVER("No preferred mode found\n");
} else {
+ is_fs_vid_mode = is_freesync_video_mode(&mode, aconnector);
+ if (is_fs_vid_mode) {
+ freesync_mode = get_highest_freesync_mode(aconnector,
false);
+ if (freesync_mode) {
+ saved_mode = mode;
+ mode = *freesync_mode;
+ }
+ }
+
decide_crtc_timing_for_drm_display_mode(
&mode, preferred_mode,
- dm_state ? (dm_state->scaling != RMX_OFF) :
false);
+ dm_state ? (dm_state->scaling != RMX_OFF) :
false,
+ freesync_mode ? true : false);
preferred_refresh = drm_mode_vrefresh(preferred_mode);
}
if (!dm_state)
drm_mode_set_crtcinfo(&mode, 0);
- /*
+ if (dm_state && is_fs_vid_mode && freesync_mode)
+ drm_mode_set_crtcinfo(&saved_mode, 0);
+
+ /*
* If scaling is enabled and refresh rate didn't change
* we copy the vic and polarities of the old timings
*/
- if (!scale || mode_refresh != preferred
[pull] amdgpu, amdkfd drm-fixes-5.10
Hi Dave, Daniel, Fixes for 5.10. The following changes since commit 0477e92881850d44910a7e94fc2c46f96faa131f: Linux 5.10-rc7 (2020-12-06 14:25:12 -0800) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-fixes-5.10-2020-12-09 for you to fetch changes up to c5b58c8c860db330c0b8b891b69014ee9d470dab: drm/amd/pm: typo fix (CUSTOM -> COMPUTE) (2020-12-09 22:38:10 -0500) amd-drm-fixes-5.10-2020-12-09: amdgpu: - Fan fix for CI asics - Fix a warning in possible_crtcs - Build fix for when debugfs is disabled - Display overflow fix - Display watermark fixes for Renoir - SDMA 5.2 fix - Stolen vga memory regression fix - Power profile fixes - Fix a regression from removal of GEM and PRIME callbacks amdkfd: - Fix a memory leak in dmabuf import Alex Deucher (3): drm/amdgpu/powerplay: parse fan table for CI asics drm/amdgpu/disply: set num_crtc earlier drm/amdgpu: fix size calculation with stolen vga memory Andrey Grodzovsky (1): drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs Arnd Bergmann (1): drm/amdgpu: fix debugfs creation/removal, again Changfeng (1): drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven Chris Park (1): drm/amd/display: Prevent bandwidth overflow Evan Quan (1): drm/amd/pm: typo fix (CUSTOM -> COMPUTE) Felix Kuehling (1): drm/amdkfd: Fix leak in dmabuf import Stanley.Yang (1): drm/amdgpu: fix sdma instance fw version and feature version init Sung Lee (1): drm/amd/display: Add wm table for Renoir drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c| 8 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 41 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c| 13 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h| 6 -- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +- .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 93 ++- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +- drivers/gpu/drm/amd/pm/inc/smu10.h | 14 ++- .../drm/amd/pm/powerplay/hwmgr/processpptables.c | 103 - .../gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c | 9 +- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 2 +- 14 files changed, 250 insertions(+), 62 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: remove leftover function declaration
The function was removed, but the declaration was leftover leading to a warning. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ab92ce307731..877b2209c901 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -196,10 +196,6 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -static int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); - static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH] drm/amdgpu: remove leftover function declaration
[AMD Official Use Only - Internal Distribution Only] Reviewed-by: Evan Quan -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Thursday, December 10, 2020 12:01 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu: remove leftover function declaration The function was removed, but the declaration was leftover leading to a warning. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ab92ce307731..877b2209c901 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -196,10 +196,6 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -static int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); - static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, -- 2.25.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cevan.quan%40amd.com%7C241bee6623394473d63608d89cc030bb%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637431696556600762%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=fCRGYXh1dPdpb%2BXwD8XjR5H1pEI6iPdIcd%2FfbfKVjO4%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: take runtime pm reference when we attach a buffer
On 09/12/20 11:00 pm, Alex Deucher wrote: > On Fri, Dec 4, 2020 at 3:41 PM Alex Deucher wrote: >> And drop it when we detach. If the shared buffer is in vram, >> we need to make sure we don't put the device into runtime >> suspend. >> >> Signed-off-by: Alex Deucher > > Ping? Any thoughts on this? We really only need this for p2p since > device memory in involved, but I'm not sure of the best way to handle > that. > > Alex > > >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 ++-- >> 1 file changed, 14 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c >> index 5b465ab774d1..f63f182f37f9 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c >> @@ -40,6 +40,7 @@ >> #include >> #include >> #include >> +#include >> >> /** >> * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation >> @@ -187,9 +188,13 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, >> if (attach->dev->driver == adev->dev->driver) >> return 0; >> >> + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); >> + if (r < 0) >> + goto out; >> + I am a bit skeptical if we should fail the BO reserve if we don't get the sync ? I was hoping to continue with it, with a warning maybe, so that it doesn't block the existing functionality ? >> r = amdgpu_bo_reserve(bo, false); >> if (unlikely(r != 0)) >> - return r; >> + goto out; >> >> /* >> * We only create shared fences for internal use, but importers >> @@ -201,11 +206,15 @@ static int amdgpu_dma_buf_attach(struct dma_buf >> *dmabuf, >> */ >> r = __dma_resv_make_exclusive(bo->tbo.base.resv); >> if (r) >> - return r; >> + goto out; >> >> bo->prime_shared_count++; >> amdgpu_bo_unreserve(bo); >> return 0; >> + >> +out: >> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); Why not just pm_runtime_put_sync ? Why autosuspend ? - Shashank >> + return r; >> } >> >> /** >> @@ -225,6 +234,9 @@ static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf, >> >> if (attach->dev->driver != adev->dev->driver && >> bo->prime_shared_count) >> bo->prime_shared_count--; >> + >> + pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); >> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); >> } >> >> /** >> -- >> 2.25.4 >> > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=04%7C01%7Cshashank.sharma%40amd.com%7Cd5fccf427c34414ff4e708d89c682898%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637431318483043257%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=NpCTY%2FVKd%2FBDi1wsFC79qSUTmNHx3nBp0HUj3m0cFeM%3D&reserved=0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[pull] amdgpu drm-next-5.11
Hi Dave, Daniel, Fixes for 5.11. The following changes since commit beaff108e1bf1e38c9def60dd09f7a4ed7910481: drm/amd/powerplay: fix spelling mistake "smu_state_memroy_block" -> "smu_state_memory_block" (2020-11-24 12:09:54 -0500) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux tags/amd-drm-next-5.11-2020-12-09 for you to fetch changes up to f8aab60422c371425365d386dfd51e0c6c5b1041: drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs (2020-12-09 23:17:03 -0500) amd-drm-next-5.11-2020-12-09: amdgpu: - SR-IOV fixes - Navy Flounder updates - Sienna Cichlid updates - Dimgrey Cavefish updates - Vangogh updates - Misc SMU fixes - Misc display fixes - Last big hunk of W=1 warning fixes - Cursor validation fixes - CI BACO updates AMD\ramini (1): drm/amd/display: Set FixRate bit in VSIF V3 Alex Deucher (22): drm/amdgpu: default noretry=0 for navi1x and newer (v2) drm/amdgpu: enable AGP aperture on gmc10.x (v2) drm/amdgpu/swsmu/vangogh: return error if fetching metrics fails drm/amdgpu/powerplay/tonga: return an error if copying to smc fails drm/amdgpu/powerplay/ci: return an error if copying to smc fails drm/amdgpu/powerplay/iceland: return an error if copying to smc fails drm/amdgpu/powerplay/vega10: handle error in getting pptable drm/amdgpu/powerplay/psm: return an error in power state init drm/amdgpu/swsmu/navi1x: simplify sensor handling drm/amdgpu/swsmu/arcturus: simplify sensor handling drm/amdgpu/swsmu/sienna_cichlid: simplify sensor handling drm/amdgpu/swsmu: add metrics enums for voltage drm/amdgpu/swsmu/vangogh: simplify sensor handling drm/amdgpu/swsmu/vangogh: use metrics table for voltages (v2) drm/amdgpu/swsmu/renoir: simplify sensor handling (v2) drm/amdgpu/powerplay: parse fan table for CI asics drm/amdgpu/disply: set num_crtc earlier drm/amdgpu/cik: enable BACO reset on Bonaire drm/amdgpu: enable runtime pm using BACO on CI dGPUs drm/amdgpu: free the pre-OS console framebuffer after the first modeset drm/amdgpu: remove amdgpu_ttm_late_init and amdgpu_bo_late_init drm/amdgpu: fix size calculation with stolen vga memory Andrey Grodzovsky (1): drm/amdgpu: Initialise drm_gem_object_funcs for imported BOs Anthony Koo (2): drm/amd/display: [FW Promotion] Release 0.0.44 drm/amd/display: [FW Promotion] Release 0.0.45 Aric Cyr (2): drm/amd/display: DC Release 3.2.114 drm/amd/display: 3.2.115 Arnd Bergmann (2): drm/amdgpu: fix debugfs creation/removal, again drm/amdgpu: fw_attestation: fix unused function warning Arunpravin (1): drm/amdgpu/pm/smu11: Fix fan set speed bug Aurabindo Pillai (2): drm/amd/display: Clear dc remote sinks on MST disconnect drm/amd/display: turn DPMS off on connector unplug Boyuan Zhang (2): drm/amdgpu/vcn3.0: stall DPG when WPTR/RPTR reset drm/amdgpu/vcn3.0: remove old DPG workaround Brandon Syu (1): drm/amd/display: Init clock value by current vbios CLKs Changfeng (1): drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven Charlene Liu (1): drm/amd/display: Enable gpu_vm_support for dcn3.01 Chris Park (1): drm/amd/display: Prevent bandwidth overflow Dmytro Laktyushkin (1): drm/amd/display: Expose clk_mgr functions for reuse Eric Bernstein (1): drm/amd/display: Revert update clk_mgr for vg Eryk Brol (1): drm/amd/display: Do full modeset when DSC debugfs is changed Evan Quan (1): drm/amd/pm: invalidate hdp before CPU access the memory written by GPU Felix Kuehling (1): drm/amdkfd: Fix leak in dmabuf import Jacky Liao (2): drm/amd/display: Add HDR3DLUT and SHAPER memory shutdown support drm/amd/display: Add DSCL memory low power support James Zhu (1): drm/amdgpu/vcn3.0: fix compilation warning Jiansong Chen (1): drm/amd/pm: update driver if version for navy_flounder Jing Zhou (1): drm/amd/display: Set default bits per channel Jingwen Chen (1): drm/amdgpu: skip power profile switch in sriov Jinzhou Su (1): drm/amdgpu: Set doorbell range for gfx ring John Wu (1): drm/amd/display: Don't check seamless boot in power down HW by timeout Joshua Aberback (1): drm/amd/display: Check link_active instead of lane_settings != unknown Judy Cai (1): drm/amd/display: Change to IMMEDIATE mode from FRAME mode Kevin Wang (2): drm/amdgpu: change trace event parameter name from 'direct' to 'immediate' drm/amdgpu/pm: add smc v2_1 printer in amdgpu_ucode_print_smc_hdr() Lee Jones (69): drm/amd/amdgpu/gmc_v10_0: Suppy some missing function doc descriptions drm/amd/amdgpu/iceland_ih: Add missing function param descriptions for 'ih' and 'entry'
[PATCH] amdgpu: resize BAR0 to the maximum available size, even if it doesn't cover VRAM
This allows BAR0 resizing to be done for cards which don't advertise support
for a size large enough to cover the VRAM but which do advertise at least
one size larger than the default. For example, my RX 5600 XT, which
advertises 256MB, 512MB and 1GB.
Signed-off-by: Darren Salt
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 +-
1 file changed, 35 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 355fa0057c26..ec3610b4110b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1078,6 +1078,11 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev,
u32 wb)
__clear_bit(wb, adev->wb.used);
}
+static inline u32 bytes_to_size_pci(u64 bytes)
+{
+ return order_base_2(((bytes >> 20) | 1)) - 1;
+}
+
/**
* amdgpu_device_resize_fb_bar - try to resize FB BAR
*
@@ -1090,20 +1095,25 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev,
u32 wb)
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
{
u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size);
- u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
+ u32 rbar_size = bytes_to_size_pci(space_needed);
struct pci_bus *root;
struct resource *res;
+ u64 current_bytes;
+ u32 current_size;
unsigned i;
u16 cmd;
int r;
+ bool nospc = false;
/* Bypass for VF */
if (amdgpu_sriov_vf(adev))
return 0;
- /* skip if the bios has already enabled large BAR */
- if (adev->gmc.real_vram_size &&
- (pci_resource_len(adev->pdev, 0) >= adev->gmc.real_vram_size))
+ current_bytes = pci_resource_len(adev->pdev, 0);
+ current_size = bytes_to_size_pci(current_bytes);
+
+ /* Skip if the BIOS has already enabled large BAR, covering the VRAM */
+ if (current_size >= rbar_size)
return 0;
/* Check if the root BUS has 64bit memory resources */
@@ -1121,6 +1131,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device
*adev)
if (!res)
return 0;
+ dev_dbg(adev->dev, "BIOS-allocated BAR0 was %lluMB; trying to get
%lluMB",
+ current_bytes >> 20, space_needed >> 20);
+
/* Disable memory decoding while we change the BAR addresses and size */
pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
pci_write_config_word(adev->pdev, PCI_COMMAND,
@@ -1133,11 +1146,24 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device
*adev)
pci_release_resource(adev->pdev, 0);
- r = pci_resize_resource(adev->pdev, 0, rbar_size);
- if (r == -ENOSPC)
- DRM_INFO("Not enough PCI address space for a large BAR.");
- else if (r && r != -ENOTSUPP)
- DRM_ERROR("Problem resizing BAR0 (%d).", r);
+ while (rbar_size > current_size) {
+ r = pci_resize_resource(adev->pdev, 0, rbar_size);
+ if (r == 0 || r == -ENOTSUPP) {
+ break;
+ } else if (r == -ENOSPC) {
+ if (!nospc) {
+ /* Warn only the first time */
+ dev_info(adev->dev, "Not enough PCI address
space for a large BAR.");
+ nospc = true;
+ }
+ --rbar_size;
+ } else if (r == -EINVAL) {
+ --rbar_size;
+ } else {
+ dev_err(adev->dev, "Problem resizing BAR0 (%d).", r);
+ break;
+ }
+ }
pci_assign_unassigned_bus_resources(adev->pdev->bus);
--
2.20.1
___
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[PATCH 1/2] drm/amd/pm: correct the data structure for activity monitor coeff exchange
This is needed for Sienna Cichlid.
Change-Id: I205190978743ec3e5176d051fba2c742e7769821
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 125 +-
1 file changed, 65 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index a8792a738acb..acbf6e97ffd0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -524,7 +524,7 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
- sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
+ sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM);
smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
@@ -1438,7 +1438,9 @@ static int sienna_cichlid_get_fan_parameters(struct
smu_context *smu)
static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char
*buf)
{
- DpmActivityMonitorCoeffInt_t activity_monitor;
+ DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
+ DpmActivityMonitorCoeffInt_t *activity_monitor =
+ &(activity_monitor_external.DpmActivityMonitorCoeffInt);
uint32_t i, size = 0;
int16_t workload_type = 0;
static const char *profile_name[] = {
@@ -1480,7 +1482,7 @@ static int sienna_cichlid_get_power_profile_mode(struct
smu_context *smu, char *
result = smu_cmn_update_table(smu,
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
workload_type,
- (void *)(&activity_monitor), false);
+ (void *)(&activity_monitor_external),
false);
if (result) {
dev_err(smu->adev->dev, "[%s] Failed to get activity
monitor!", __func__);
return result;
@@ -1493,43 +1495,43 @@ static int sienna_cichlid_get_power_profile_mode(struct
smu_context *smu, char *
" ",
0,
"GFXCLK",
- activity_monitor.Gfx_FPS,
- activity_monitor.Gfx_MinFreqStep,
- activity_monitor.Gfx_MinActiveFreqType,
- activity_monitor.Gfx_MinActiveFreq,
- activity_monitor.Gfx_BoosterFreqType,
- activity_monitor.Gfx_BoosterFreq,
- activity_monitor.Gfx_PD_Data_limit_c,
- activity_monitor.Gfx_PD_Data_error_coeff,
- activity_monitor.Gfx_PD_Data_error_rate_coeff);
+ activity_monitor->Gfx_FPS,
+ activity_monitor->Gfx_MinFreqStep,
+ activity_monitor->Gfx_MinActiveFreqType,
+ activity_monitor->Gfx_MinActiveFreq,
+ activity_monitor->Gfx_BoosterFreqType,
+ activity_monitor->Gfx_BoosterFreq,
+ activity_monitor->Gfx_PD_Data_limit_c,
+ activity_monitor->Gfx_PD_Data_error_coeff,
+ activity_monitor->Gfx_PD_Data_error_rate_coeff);
size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d
%7d %7d %7d %7d\n",
" ",
1,
"SOCCLK",
- activity_monitor.Fclk_FPS,
- activity_monitor.Fclk_MinFreqStep,
- activity_monitor.Fclk_MinActiveFreqType,
- activity_monitor.Fclk_MinActiveFreq,
- activity_monitor.Fclk_BoosterFreqType,
- activity_monitor.Fclk_BoosterFreq,
- activity_monitor.Fclk_PD_Data_limit_c,
- activity_monitor.Fclk_PD_Data_error_coeff,
- activity_monitor.Fclk_PD_Data_error_rate_coeff);
+ activity_monitor->Fclk_FPS,
+ activity_monitor->Fclk_MinFreqStep,
+ activity_monitor->Fclk_MinActiveFreqType,
+ activity_monitor->Fclk_MinActiveFreq,
+ activity_monitor->Fclk_BoosterFreqType,
+ activity_monitor->Fclk_BoosterFreq,
+ activity_monitor->Fclk_PD_Data_limit_c,
+ activity_monitor->Fclk_PD_Data_error_coeff,
+ activity_monitor->Fclk_PD_Data_error_rate_coeff);
size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d
%7d %7d %7d %7d\n",
" ",
[PATCH 2/2] drm/amd/pm: update the data strucutre for SMU metrics exchange
This is needed for Sienna Cichlid.
Change-Id: I57aa099cd1b2020cf0c8b05d8463239ec33790cf
Signed-off-by: Evan Quan
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 75 ++-
1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index acbf6e97ffd0..0c4885273291 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -515,7 +515,7 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
- SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
+ SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
sizeof(SmuMetricsExternal_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
@@ -527,7 +527,7 @@ static int sienna_cichlid_tables_init(struct smu_context
*smu)
sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM);
- smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
+ smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t),
GFP_KERNEL);
if (!smu_table->metrics_table)
goto err0_out;
smu_table->metrics_time = 0;
@@ -556,7 +556,8 @@ static int sienna_cichlid_get_smu_metrics_data(struct
smu_context *smu,
uint32_t *value)
{
struct smu_table_context *smu_table= &smu->smu_table;
- SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+ SmuMetrics_t *metrics =
+ &(((SmuMetricsExternal_t
*)(smu_table->metrics_table))->SmuMetrics);
int ret = 0;
mutex_lock(&smu->metrics_lock);
@@ -3152,52 +3153,54 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct
smu_context *smu,
struct smu_table_context *smu_table = &smu->smu_table;
struct gpu_metrics_v1_0 *gpu_metrics =
(struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
- SmuMetrics_t metrics;
+ SmuMetricsExternal_t metrics_external;
+ SmuMetrics_t *metrics =
+ &(metrics_external.SmuMetrics);
int ret = 0;
ret = smu_cmn_get_metrics_table(smu,
- &metrics,
+ &metrics_external,
true);
if (ret)
return ret;
smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
- gpu_metrics->temperature_edge = metrics.TemperatureEdge;
- gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
- gpu_metrics->temperature_mem = metrics.TemperatureMem;
- gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
- gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
- gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
+ gpu_metrics->temperature_edge = metrics->TemperatureEdge;
+ gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot;
+ gpu_metrics->temperature_mem = metrics->TemperatureMem;
+ gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx;
+ gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc;
+ gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0;
- gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
- gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
- gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
+ gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
+ gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
+ gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage;
- gpu_metrics->average_socket_power = metrics.AverageSocketPower;
- gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
+ gpu_metrics->average_socket_power = metrics->AverageSocketPower;
+ gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
- if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
- gpu_metrics->average_gfxclk_frequency =
metrics.AverageGfxclkFrequencyPostDs;
+ if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
+ gpu_metrics->average_gfxclk_frequency =
metrics->AverageGfxclkFrequencyPostDs;
else
- gpu_metrics->average_gfxclk_frequency =
metrics.AverageGfxclkFrequencyPreDs;
- gpu_metrics->average_uclk_frequency =
metrics.AverageUclkFrequencyPostDs;
- gpu_metrics->average_vclk0_f
