improve use_mm / unuse_mm v2

[Christoph Hellwig]

Hi all,

this series improves the use_mm / unuse_mm interface by better
documenting the assumptions, and my taking the set_fs manipulations
spread over the callers into the core API.

Changes since v1:
 - drop a few patches
 - fix a comment typo
 - cover the newly merged use_mm/unuse_mm caller in vfio
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Re: [PATCH 2/3] kernel: better document the use_mm/unuse_mm API contract

[Greg KH]

On Thu, Apr 16, 2020 at 07:31:57AM +0200, Christoph Hellwig wrote:
> Switch the function documentation to kerneldoc comments, and add
> WARN_ON_ONCE asserts that the calling thread is a kernel thread and
> does not have ->mm set (or has ->mm set in the case of unuse_mm).
> 
> Also give the functions a kthread_ prefix to better document the
> use case.
> 
> Signed-off-by: Christoph Hellwig 
> Acked-by: Felix Kuehling 

Acked-by: Greg Kroah-Hartman  [usb]
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[PATCH 2/3] kernel: better document the use_mm/unuse_mm API contract

[Christoph Hellwig]

Switch the function documentation to kerneldoc comments, and add
WARN_ON_ONCE asserts that the calling thread is a kernel thread and
does not have ->mm set (or has ->mm set in the case of unuse_mm).

Also give the functions a kthread_ prefix to better document the
use case.

Signed-off-by: Christoph Hellwig 
Acked-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h |  4 +--
 drivers/gpu/drm/i915/gvt/kvmgt.c   |  4 +--
 drivers/usb/gadget/function/f_fs.c |  4 +--
 drivers/usb/gadget/legacy/inode.c  |  4 +--
 drivers/vfio/vfio_iommu_type1.c|  4 +--
 drivers/vhost/vhost.c  |  4 +--
 fs/io-wq.c |  6 ++--
 fs/io_uring.c  |  6 ++--
 include/linux/kthread.h|  4 +--
 kernel/kthread.c   | 33 +++---
 mm/oom_kill.c  |  6 ++--
 mm/vmacache.c  |  4 +--
 12 files changed, 41 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index b820c8fc689f..b063bd7f41d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -192,9 +192,9 @@ uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev 
*dst, struct kgd_dev *s
if ((mmptr) == current->mm) {   \
valid = !get_user((dst), (wptr));   \
} else if (current->mm == NULL) {   \
-   use_mm(mmptr);  \
+   kthread_use_mm(mmptr);  \
valid = !get_user((dst), (wptr));   \
-   unuse_mm(mmptr);\
+   kthread_unuse_mm(mmptr);\
}   \
pagefault_enable(); \
}   \
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index ca1dd6e6f395..f2927575b793 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -2048,7 +2048,7 @@ static int kvmgt_rw_gpa(unsigned long handle, unsigned 
long gpa,
if (kthread) {
if (!mmget_not_zero(kvm->mm))
return -EFAULT;
-   use_mm(kvm->mm);
+   kthread_use_mm(kvm->mm);
}
 
idx = srcu_read_lock(&kvm->srcu);
@@ -2057,7 +2057,7 @@ static int kvmgt_rw_gpa(unsigned long handle, unsigned 
long gpa,
srcu_read_unlock(&kvm->srcu, idx);
 
if (kthread) {
-   unuse_mm(kvm->mm);
+   kthread_unuse_mm(kvm->mm);
mmput(kvm->mm);
}
 
diff --git a/drivers/usb/gadget/function/f_fs.c 
b/drivers/usb/gadget/function/f_fs.c
index c57b1b2507c6..d9e48bd7c692 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -827,9 +827,9 @@ static void ffs_user_copy_worker(struct work_struct *work)
mm_segment_t oldfs = get_fs();
 
set_fs(USER_DS);
-   use_mm(io_data->mm);
+   kthread_use_mm(io_data->mm);
ret = ffs_copy_to_iter(io_data->buf, ret, &io_data->data);
-   unuse_mm(io_data->mm);
+   kthread_unuse_mm(io_data->mm);
set_fs(oldfs);
}
 
diff --git a/drivers/usb/gadget/legacy/inode.c 
b/drivers/usb/gadget/legacy/inode.c
index 8b5233888bf8..a05552bc2ff8 100644
--- a/drivers/usb/gadget/legacy/inode.c
+++ b/drivers/usb/gadget/legacy/inode.c
@@ -462,9 +462,9 @@ static void ep_user_copy_worker(struct work_struct *work)
struct kiocb *iocb = priv->iocb;
size_t ret;
 
-   use_mm(mm);
+   kthread_use_mm(mm);
ret = copy_to_iter(priv->buf, priv->actual, &priv->to);
-   unuse_mm(mm);
+   kthread_unuse_mm(mm);
if (!ret)
ret = -EFAULT;
 
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 5f50866a8b01..2eb105aa9723 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -2333,7 +2333,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct 
vfio_iommu *iommu,
return -EPERM;
 
if (kthread)
-   use_mm(mm);
+   kthread_use_mm(mm);
else if (current->mm != mm)
goto out;
 
@@ -2351,7 +2351,7 @@ static int vfio_iommu_type1_dma_rw_chunk(struct 
vfio_iommu *iommu,
*copied = __copy_from_user(data, (void __user *)vaddr,
   count) ? 0 : count;
if (kthread)
-   unuse_mm(mm);
+   kthread_unuse_mm

[PATCH 3/3] kernel: set USER_DS in kthread_use_mm

[Christoph Hellwig]

Some architectures like arm64 and s390 require USER_DS to be set for
kernel threads to access user address space, which is the whole purpose
of kthread_use_mm, but other like x86 don't.  That has lead to a huge
mess where some callers are fixed up once they are tested on said
architectures, while others linger around and yet other like io_uring
try to do "clever" optimizations for what usually is just a trivial
asignment to a member in the thread_struct for most architectures.

Make kthread_use_mm set USER_DS, and kthread_unuse_mm restore to the
previous value instead.

Signed-off-by: Christoph Hellwig 
Acked-by: Michael S. Tsirkin  [vhost]
---
 drivers/usb/gadget/function/f_fs.c | 4 
 drivers/vhost/vhost.c  | 3 ---
 fs/io-wq.c | 8 ++--
 fs/io_uring.c  | 4 
 kernel/kthread.c   | 6 ++
 5 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/usb/gadget/function/f_fs.c 
b/drivers/usb/gadget/function/f_fs.c
index d9e48bd7c692..a1198f4c527c 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -824,13 +824,9 @@ static void ffs_user_copy_worker(struct work_struct *work)
bool kiocb_has_eventfd = io_data->kiocb->ki_flags & IOCB_EVENTFD;
 
if (io_data->read && ret > 0) {
-   mm_segment_t oldfs = get_fs();
-
-   set_fs(USER_DS);
kthread_use_mm(io_data->mm);
ret = ffs_copy_to_iter(io_data->buf, ret, &io_data->data);
kthread_unuse_mm(io_data->mm);
-   set_fs(oldfs);
}
 
io_data->kiocb->ki_complete(io_data->kiocb, ret, ret);
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 17d598e74780..b2abfbdf3cb2 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -329,9 +329,7 @@ static int vhost_worker(void *data)
struct vhost_dev *dev = data;
struct vhost_work *work, *work_next;
struct llist_node *node;
-   mm_segment_t oldfs = get_fs();
 
-   set_fs(USER_DS);
kthread_use_mm(dev->mm);
 
for (;;) {
@@ -361,7 +359,6 @@ static int vhost_worker(void *data)
}
}
kthread_unuse_mm(dev->mm);
-   set_fs(oldfs);
return 0;
 }
 
diff --git a/fs/io-wq.c b/fs/io-wq.c
index 748621f7391e..a5e90ac39e4d 100644
--- a/fs/io-wq.c
+++ b/fs/io-wq.c
@@ -169,7 +169,6 @@ static bool __io_worker_unuse(struct io_wqe *wqe, struct 
io_worker *worker)
dropped_lock = true;
}
__set_current_state(TASK_RUNNING);
-   set_fs(KERNEL_DS);
kthread_unuse_mm(worker->mm);
mmput(worker->mm);
worker->mm = NULL;
@@ -421,14 +420,11 @@ static void io_wq_switch_mm(struct io_worker *worker, 
struct io_wq_work *work)
mmput(worker->mm);
worker->mm = NULL;
}
-   if (!work->mm) {
-   set_fs(KERNEL_DS);
+   if (!work->mm)
return;
-   }
+
if (mmget_not_zero(work->mm)) {
kthread_use_mm(work->mm);
-   if (!worker->mm)
-   set_fs(USER_DS);
worker->mm = work->mm;
/* hang on to this mm */
work->mm = NULL;
diff --git a/fs/io_uring.c b/fs/io_uring.c
index 8a8148512da7..40f90b98a18a 100644
--- a/fs/io_uring.c
+++ b/fs/io_uring.c
@@ -5908,15 +5908,12 @@ static int io_sq_thread(void *data)
struct io_ring_ctx *ctx = data;
struct mm_struct *cur_mm = NULL;
const struct cred *old_cred;
-   mm_segment_t old_fs;
DEFINE_WAIT(wait);
unsigned long timeout;
int ret = 0;
 
complete(&ctx->completions[1]);
 
-   old_fs = get_fs();
-   set_fs(USER_DS);
old_cred = override_creds(ctx->creds);
 
timeout = jiffies + ctx->sq_thread_idle;
@@ -6023,7 +6020,6 @@ static int io_sq_thread(void *data)
if (current->task_works)
task_work_run();
 
-   set_fs(old_fs);
if (cur_mm) {
kthread_unuse_mm(cur_mm);
mmput(cur_mm);
diff --git a/kernel/kthread.c b/kernel/kthread.c
index 8ed4b4fbec7c..86357cd38eb2 100644
--- a/kernel/kthread.c
+++ b/kernel/kthread.c
@@ -52,6 +52,7 @@ struct kthread {
unsigned long flags;
unsigned int cpu;
void *data;
+   mm_segment_t oldfs;
struct completion parked;
struct completion exited;
 #ifdef CONFIG_BLK_CGROUP
@@ -1235,6 +1236,9 @@ void kthread_use_mm(struct mm_struct *mm)
 
if (active_mm != mm)
mmdrop(active_mm);
+
+   to_kthread(tsk)->oldfs = get_fs();
+   set_fs(USER_DS);
 }
 EXPORT_SYMBOL_GPL(kthread_use_mm);
 
@@ -1249,6 +1253,8 @@ void kthread_unuse_mm(struct mm_struct *mm)
WARN_ON_ONCE(!(tsk->flags & PF_KTHREAD));
WARN_ON_ONCE(!tsk->mm);
 
+   set_fs(to_kthread(tsk)->oldfs);
+
  

Re: [PATCH 3/3] kernel: set USER_DS in kthread_use_mm

[Greg KH]

On Thu, Apr 16, 2020 at 07:31:58AM +0200, Christoph Hellwig wrote:
> Some architectures like arm64 and s390 require USER_DS to be set for
> kernel threads to access user address space, which is the whole purpose
> of kthread_use_mm, but other like x86 don't.  That has lead to a huge
> mess where some callers are fixed up once they are tested on said
> architectures, while others linger around and yet other like io_uring
> try to do "clever" optimizations for what usually is just a trivial
> asignment to a member in the thread_struct for most architectures.
> 
> Make kthread_use_mm set USER_DS, and kthread_unuse_mm restore to the
> previous value instead.
> 
> Signed-off-by: Christoph Hellwig 
> Acked-by: Michael S. Tsirkin  [vhost]
> ---

Acked-by: Greg Kroah-Hartman  [usb]
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[PATCH 1/3] kernel: move use_mm/unuse_mm to kthread.c

[Christoph Hellwig]

These helpers are only for use with kernel threads, and I will tie them
more into the kthread infrastructure going forward.  Also move the
prototypes to kthread.h - mmu_context.h was a little weird to start with
as it otherwise contains very low-level MM bits.

Signed-off-by: Christoph Hellwig 
Acked-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h|  1 +
 .../drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c   |  1 -
 .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c|  1 -
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c |  2 -
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |  2 -
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c |  2 -
 drivers/gpu/drm/i915/gvt/kvmgt.c  |  2 +-
 drivers/usb/gadget/function/f_fs.c|  2 +-
 drivers/usb/gadget/legacy/inode.c |  2 +-
 drivers/vfio/vfio_iommu_type1.c   |  2 +-
 drivers/vhost/vhost.c |  1 -
 fs/aio.c  |  1 -
 fs/io-wq.c|  1 -
 fs/io_uring.c |  1 -
 include/linux/kthread.h   |  5 ++
 include/linux/mmu_context.h   |  5 --
 kernel/kthread.c  | 56 
 mm/Makefile   |  2 +-
 mm/mmu_context.c  | 64 ---
 19 files changed, 67 insertions(+), 86 deletions(-)
 delete mode 100644 mm/mmu_context.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 13feb313e9b3..b820c8fc689f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -27,6 +27,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
index 6529caca88fe..35d4a5ab0228 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
@@ -22,7 +22,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 4ec6d0c03201..b1655054b919 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -19,7 +19,6 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
-#include 
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
 #include "gc/gc_10_1_0_offset.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 0b7e78748540..7d01420c0c85 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -20,8 +20,6 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include 
-
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
 #include "cikd.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index ccd635b812b5..635cd1a26bed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -20,8 +20,6 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include 
-
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
 #include "gfx_v8_0.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e7..c7fd0c47b254 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -19,8 +19,6 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  */
-#include 
-
 #include "amdgpu.h"
 #include "amdgpu_amdkfd.h"
 #include "gc/gc_9_0_offset.h"
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 074c4efb58eb..ca1dd6e6f395 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -31,7 +31,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/usb/gadget/function/f_fs.c 
b/drivers/usb/gadget/function/f_fs.c
index c81023b195c3..c57b1b2507c6 100644
--- a/drivers/usb/gadget/function/f_fs.c
+++ b/drivers/usb/gadget/function/f_fs.c
@@ -32,7 +32,7 @@
 #include 
 
 #include 
-#include 
+#include 
 #include 
 #include 
 
diff --git a/drivers/usb/gadget/legacy/inode.c 
b/drivers/usb/gadget/legacy/inode.c
index aa0de9e35afa..8b5233888bf8 100644
--- a/drivers/usb/gadget/legacy/inode.c
+++ b/drivers/usb/gadget/legacy/inode.c
@@ -21,7 +21,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio

Re: [PATCH] drm/amdgpu: change SH MEM alignment mode for gfx10

[Michel Dänzer]

On 2020-04-03 12:20 p.m., Likun Gao wrote:
> From: Likun Gao 
> 
> Change SH_MEM_CONFIG Alignment mode to Automatic, as:
> 1)OGL fn_amd_compute_shader will failed with unaligned mode.
> 2)The default alignment mode was defined to automatic on gfx10
> specification.
> 
> Signed-off-by: Likun Gao 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 5a67306..d8f0c0d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -279,7 +279,7 @@ static const struct soc15_reg_golden 
> golden_settings_gc_10_1_2_nv12[] =
>  
>  #define DEFAULT_SH_MEM_CONFIG \
>   ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
> -  (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
> +  (SH_MEM_ALIGNMENT_MODE_DWORD << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) 
> | \
>(SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
>(3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
>  
> 

I bisected a bunch of piglit regressions (mostly half-float related,
e.g. draw-vertices-half-float_gles2) with radeonsi on Navi 10 to this
change.

Does radeonsi/LLVM need corresponding changes?


-- 
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer
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[PATCH] drm/amdgpu: fix race between pstate and remote buffer map

[Jonathan Kim]

Vega20 arbitrates pstate at hive level and not device level. Last peer to
remote buffer unmap could drop P-State while another process is still
remote buffer mapped.

With this fix, P-States still needs to be disabled for now as SMU bug
was discovered on synchronous P2P transfers.  This should be fixed in the
next FW update.

Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h   |  4 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 66 
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h |  6 +++
 5 files changed, 43 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e1d4cfe7a9f..94dff899248d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -982,8 +982,6 @@ struct amdgpu_device {
uint64_tunique_id;
uint64_tdf_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
 
-   /* device pstate */
-   int pstate;
/* enable runtime pm on the device */
boolrunpm;
boolin_runpm;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index accbb34ea670..95560eea61c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2135,11 +2135,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct 
amdgpu_device *adev,
if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
(bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
bo_va->is_xgmi = true;
-   mutex_lock(&adev->vm_manager.lock_pstate);
/* Power up XGMI if it can be potentially used */
-   if (++adev->vm_manager.xgmi_map_counter == 1)
-   amdgpu_xgmi_set_pstate(adev, 1);
-   mutex_unlock(&adev->vm_manager.lock_pstate);
+   amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
}
 
return bo_va;
@@ -2562,12 +2559,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 
dma_fence_put(bo_va->last_pt_update);
 
-   if (bo && bo_va->is_xgmi) {
-   mutex_lock(&adev->vm_manager.lock_pstate);
-   if (--adev->vm_manager.xgmi_map_counter == 0)
-   amdgpu_xgmi_set_pstate(adev, 0);
-   mutex_unlock(&adev->vm_manager.lock_pstate);
-   }
+   if (bo && bo_va->is_xgmi)
+   amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
 
kfree(bo_va);
 }
@@ -3177,9 +3170,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
 
idr_init(&adev->vm_manager.pasid_idr);
spin_lock_init(&adev->vm_manager.pasid_lock);
-
-   adev->vm_manager.xgmi_map_counter = 0;
-   mutex_init(&adev->vm_manager.lock_pstate);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index ea771d84bf2b..c8e68d7890bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -357,10 +357,6 @@ struct amdgpu_vm_manager {
 */
struct idr  pasid_idr;
spinlock_t  pasid_lock;
-
-   /* counter of mapped memory through xgmi */
-   uint32_txgmi_map_counter;
-   struct mutexlock_pstate;
 };
 
 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) 
((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index 8c3215505e78..52f45b9fe271 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -373,7 +373,13 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct 
amdgpu_device *adev, int lo
 
if (lock)
mutex_lock(&tmp->hive_lock);
-   tmp->pstate = -1;
+   tmp->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
+   tmp->high_gpu = NULL;
+   /*
+* hive pstate on boot is high in vega20 so we have to go to low
+* pstate on after boot.
+*/
+   tmp->map_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
mutex_unlock(&xgmi_mutex);
 
return tmp;
@@ -383,50 +389,49 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, 
int pstate)
 {
int ret = 0;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, 0);
-   struct amdgpu_device *tmp_adev;
-   bool update_hive_pstate = true;
-   bool is_high_pstate = pstate && adev->asic_type == CHIP_VEGA20;
+   struct amdgpu_device *tar_adev = hive->high_gpu ?
+   hive->high_gpu : adev;
+   bool map = 

[PATCH] drm/amdgpu: Disable FRU read on Arcturus

[Kent Russell]

Update the list with supported Arcturus chips, but disable for now until
final list is confirmed.

Ideally we can poll atombios for FRU support, instead of maintaining
this list of chips, but this will enable serial number reading for
supported ASICs for the time-being.

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index c7e55fe170bd..815c072ac4da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -36,10 +36,11 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)
/* TODO: Gaming SKUs don't have the FRU EEPROM.
 * Use this hack to address hangs on modprobe on gaming SKUs
 * until a proper solution can be implemented by only supporting
-* it on Arcturus, and the explicit chip IDs for VG20 Server cards
+* the explicit chip IDs for VG20 Server cards
+*
+* TODO: Add list of supported Arcturus DIDs once confirmed
 */
-   if ((adev->asic_type == CHIP_ARCTURUS) ||
-   (adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) ||
+   if ((adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) ||
(adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a1) ||
(adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a4))
return true;
-- 
2.17.1

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[bug report] drm/amd/display: Add HDCP module

[Dan Carpenter]

Hello Bhawanpreet Lakha,

The patch 4c283fdac08a: "drm/amd/display: Add HDCP module" from Aug
6, 2019, leads to the following static checker warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/hdcp/hdcp_msg.c:132 
hdmi_14_process_transaction()
error: buffer overflow 'hdcp_i2c_offsets' 32 <= 32

drivers/gpu/drm/amd/amdgpu/../display/dc/hdcp/hdcp_msg.c
77  
78  static const uint8_t hdcp_i2c_offsets[] = {
79  [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
80  [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
81  [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
82  [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
83  [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
84  [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
85  [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
86  [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
87  [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
88  [HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
89  [HDCP_MESSAGE_ID_READ_VH_3] = 0x2C,
90  [HDCP_MESSAGE_ID_READ_VH_4] = 0x30,
91  [HDCP_MESSAGE_ID_READ_BCAPS] = 0x40,
92  [HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
93  [HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
94  [HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
95  [HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
96  [HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
97  [HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
98  [HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
99  [HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
   100  [HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
   101  [HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
   102  [HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
   103  [HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
   104  [HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
   105  [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 
0x80,
   106  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
   107  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
   108  [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
   109  [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70

HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE is missing.  This array should
have HDCP_MESSAGE_ID_MAX elements.

   110  };
   111  
   112  struct protection_properties {
   113  bool supported;
   114  bool (*process_transaction)(
   115  struct dc_link *link,
   116  struct hdcp_protection_message *message_info);
   117  };
   118  
   119  static const struct protection_properties non_supported_protection = {
   120  .supported = false
   121  };
   122  
   123  static bool hdmi_14_process_transaction(
   124  struct dc_link *link,
   125  struct hdcp_protection_message *message_info)
   126  {
   127  uint8_t *buff = NULL;
   128  bool result;
   129  const uint8_t hdcp_i2c_addr_link_primary = 0x3a; /* 0x74 >> 1*/
   130  const uint8_t hdcp_i2c_addr_link_secondary = 0x3b; /* 0x76 >> 
1*/
   131  struct i2c_command i2c_command;
   132  uint8_t offset = hdcp_i2c_offsets[message_info->msg_id];
 ^^
Potential out of bounds access.

   133  struct i2c_payload i2c_payloads[] = {
   134  { true, 0, 1, &offset },
   135  /* actual hdcp payload, will be filled later, zeroed 
for now*/
   136  { 0 }
   137  };
   138  

regards,
dan carpenter
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RE: [PATCH] drm/amdgpu: change SH MEM alignment mode for gfx10

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Michel Dänzer
> Sent: Thursday, April 16, 2020 5:57 AM
> To: Gao, Likun ; Marek Olšák ;
> Pierre-Eric Pelloux-Prayer 
> Cc: amd-gfx@lists.freedesktop.org; Zhang, Hawking
> 
> Subject: Re: [PATCH] drm/amdgpu: change SH MEM alignment mode for
> gfx10
> 
> On 2020-04-03 12:20 p.m., Likun Gao wrote:
> > From: Likun Gao 
> >
> > Change SH_MEM_CONFIG Alignment mode to Automatic, as:
> > 1)OGL fn_amd_compute_shader will failed with unaligned mode.
> > 2)The default alignment mode was defined to automatic on gfx10
> > specification.
> >
> > Signed-off-by: Likun Gao 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 5a67306..d8f0c0d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -279,7 +279,7 @@ static const struct soc15_reg_golden
> > golden_settings_gc_10_1_2_nv12[] =
> >
> >  #define DEFAULT_SH_MEM_CONFIG \
> > ((SH_MEM_ADDRESS_MODE_64 <<
> SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
> > -(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
> > +(SH_MEM_ALIGNMENT_MODE_DWORD <<
> > +SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
> >  (SH_MEM_RETRY_MODE_ALL <<
> SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
> >  (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
> >
> >
> 
> I bisected a bunch of piglit regressions (mostly half-float related, e.g. 
> draw-
> vertices-half-float_gles2) with radeonsi on Navi 10 to this change.
> 
> Does radeonsi/LLVM need corresponding changes?

This change was reverted.  The problem was in the Orca OpenGL shader compiler.

Alex
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Re: [PATCH] drm/amdgpu: Disable FRU read on Arcturus

[Deucher, Alexander]

[AMD Public Use]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Kent Russell 

Sent: Thursday, April 16, 2020 8:26 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Russell, Kent 
Subject: [PATCH] drm/amdgpu: Disable FRU read on Arcturus

Update the list with supported Arcturus chips, but disable for now until
final list is confirmed.

Ideally we can poll atombios for FRU support, instead of maintaining
this list of chips, but this will enable serial number reading for
supported ASICs for the time-being.

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index c7e55fe170bd..815c072ac4da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -36,10 +36,11 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)
 /* TODO: Gaming SKUs don't have the FRU EEPROM.
  * Use this hack to address hangs on modprobe on gaming SKUs
  * until a proper solution can be implemented by only supporting
-* it on Arcturus, and the explicit chip IDs for VG20 Server cards
+* the explicit chip IDs for VG20 Server cards
+*
+* TODO: Add list of supported Arcturus DIDs once confirmed
  */
-   if ((adev->asic_type == CHIP_ARCTURUS) ||
-   (adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) ||
+   if ((adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) ||
 (adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a1) ||
 (adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a4))
 return true;
--
2.17.1

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Re: [Intel-gfx] [PATCH 4/5] drm/amdgpu: utilize subconnector property for DP through atombios

[Alex Deucher]

On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula  wrote:
>
>
> Alex, Harry, Christian, can you please eyeball this series and see if it
> makes sense for you?
>

Patches 4, 5 are:
Acked-by: Alex Deucher 
Feel free to take them through whichever tree you want.

Alex


> Thanks,
> Jani.
>
>
> On Tue, 07 Apr 2020, Jeevan B  wrote:
> > From: Oleg Vasilev 
> >
> > Since DP-specific information is stored in driver's structures, every
> > driver needs to implement subconnector property by itself.
> >
> > v2: rebase
> >
> > Cc: Alex Deucher 
> > Cc: Christian König 
> > Cc: David (ChunMing) Zhou 
> > Cc: amd-gfx@lists.freedesktop.org
> > Signed-off-by: Jeevan B 
> > Signed-off-by: Oleg Vasilev 
> > Reviewed-by: Emil Velikov 
> > Link: 
> > https://patchwork.freedesktop.org/patch/msgid/20190829114854.1539-6-oleg.vasi...@intel.com
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |  1 +
> >  drivers/gpu/drm/amd/amdgpu/atombios_dp.c   | 18 +-
> >  3 files changed, 28 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > index f355d9a..71aade0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > @@ -26,6 +26,7 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include "amdgpu.h"
> > @@ -1405,6 +1406,10 @@ amdgpu_connector_dp_detect(struct drm_connector 
> > *connector, bool force)
> >   pm_runtime_put_autosuspend(connector->dev->dev);
> >   }
> >
> > + drm_dp_set_subconnector_property(&amdgpu_connector->base,
> > +  ret,
> > +  amdgpu_dig_connector->dpcd,
> > +  
> > amdgpu_dig_connector->downstream_ports);
> >   return ret;
> >  }
> >
> > @@ -1951,6 +1956,11 @@ amdgpu_connector_add(struct amdgpu_device *adev,
> >   if (has_aux)
> >   amdgpu_atombios_dp_aux_init(amdgpu_connector);
> >
> > + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
> > + connector_type == DRM_MODE_CONNECTOR_eDP) {
> > + 
> > drm_mode_add_dp_subconnector_property(&amdgpu_connector->base);
> > + }
> > +
> >   return;
> >
> >  failed:
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > index 37ba07e..04a430e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
> > @@ -469,6 +469,7 @@ struct amdgpu_encoder {
> >  struct amdgpu_connector_atom_dig {
> >   /* displayport */
> >   u8 dpcd[DP_RECEIVER_CAP_SIZE];
> > + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> >   u8 dp_sink_type;
> >   int dp_clock;
> >   int dp_lane_count;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c 
> > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > index 9b74cfd..900b272 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > @@ -328,6 +328,22 @@ static void amdgpu_atombios_dp_probe_oui(struct 
> > amdgpu_connector *amdgpu_connect
> > buf[0], buf[1], buf[2]);
> >  }
> >
> > +static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector 
> > *amdgpu_connector)
> > +{
> > + struct amdgpu_connector_atom_dig *dig_connector = 
> > amdgpu_connector->con_priv;
> > + int ret;
> > +
> > + if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
> > + ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux,
> > +DP_DOWNSTREAM_PORT_0,
> > +dig_connector->downstream_ports,
> > +DP_MAX_DOWNSTREAM_PORTS);
> > + if (ret)
> > + memset(dig_connector->downstream_ports, 0,
> > +DP_MAX_DOWNSTREAM_PORTS);
> > + }
> > +}
> > +
> >  int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
> >  {
> >   struct amdgpu_connector_atom_dig *dig_connector = 
> > amdgpu_connector->con_priv;
> > @@ -343,7 +359,7 @@ int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector 
> > *amdgpu_connector)
> > dig_connector->dpcd);
> >
> >   amdgpu_atombios_dp_probe_oui(amdgpu_connector);
> > -
> > + amdgpu_atombios_dp_ds_ports(amdgpu_connector);
> >   return 0;
> >   }
>
> --
> Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH] drm/amdgpu: change SH MEM alignment mode for gfx10

[Michel Dänzer]

On 2020-04-16 3:25 p.m., Deucher, Alexander wrote:
> [AMD Official Use Only - Internal Distribution Only]
> 
>> -Original Message-
>> From: amd-gfx  On Behalf Of
>> Michel Dänzer
>> Sent: Thursday, April 16, 2020 5:57 AM
>> To: Gao, Likun ; Marek Olšák ;
>> Pierre-Eric Pelloux-Prayer 
>> Cc: amd-gfx@lists.freedesktop.org; Zhang, Hawking
>> 
>> Subject: Re: [PATCH] drm/amdgpu: change SH MEM alignment mode for
>> gfx10
>>
>> On 2020-04-03 12:20 p.m., Likun Gao wrote:
>>> From: Likun Gao 
>>>
>>> Change SH_MEM_CONFIG Alignment mode to Automatic, as:
>>> 1)OGL fn_amd_compute_shader will failed with unaligned mode.
>>> 2)The default alignment mode was defined to automatic on gfx10
>>> specification.
>>>
>>> Signed-off-by: Likun Gao 
>>> ---
>>>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> index 5a67306..d8f0c0d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>>> @@ -279,7 +279,7 @@ static const struct soc15_reg_golden
>>> golden_settings_gc_10_1_2_nv12[] =
>>>
>>>  #define DEFAULT_SH_MEM_CONFIG \
>>> ((SH_MEM_ADDRESS_MODE_64 <<
>> SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
>>> -(SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
>> SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
>>> +(SH_MEM_ALIGNMENT_MODE_DWORD <<
>>> +SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
>>>  (SH_MEM_RETRY_MODE_ALL <<
>> SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
>>>  (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
>>>
>>>
>>
>> I bisected a bunch of piglit regressions (mostly half-float related, e.g. 
>> draw-
>> vertices-half-float_gles2) with radeonsi on Navi 10 to this change.
>>
>> Does radeonsi/LLVM need corresponding changes?
> 
> This change was reverted.  The problem was in the Orca OpenGL shader compiler.

Ah, I see the revert now, thanks.


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Libre software enthusiast | Mesa and X developer
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[PATCH] drm/amdgpu: fix kernel page fault issue by ras recovery on sGPU

[Guchun Chen]

When running ras uncorrectable error injection and trigger GPU
reset on sGPU, below issue is observed. It's caused by the list
uninitialized when accessing.

[   80.047227] BUG: unable to handle page fault for address: c0f4f750
[   80.047300] #PF: supervisor write access in kernel mode
[   80.047351] #PF: error_code(0x0003) - permissions violation
[   80.047404] PGD 12c20e067 P4D 12c20e067 PUD 12c210067 PMD 41c4ee067 PTE 
404316061
[   80.047477] Oops: 0003 [#1] SMP PTI
[   80.047516] CPU: 7 PID: 377 Comm: kworker/7:2 Tainted: G   OE 
5.4.0-rc7-guchchen #1
[   80.047594] Hardware name: System manufacturer System Product Name/TUF 
Z370-PLUS GAMING II, BIOS 0411 09/21/2018
[   80.047888] Workqueue: events amdgpu_ras_do_recovery [amdgpu]

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b27d9d62c9df..260b4a42e0ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1448,9 +1448,10 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);
 
/* Build list of devices to query RAS related errors */
-   if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
+   if  (hive && adev->gmc.xgmi.num_physical_nodes > 1)
device_list_handle = &hive->device_list;
-   } else {
+   else {
+   INIT_LIST_HEAD(&device_list);
list_add_tail(&adev->gmc.xgmi.head, &device_list);
device_list_handle = &device_list;
}
-- 
2.17.1

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RE: [PATCH] drm/amdgpu: fix kernel page fault issue by ras recovery on sGPU

[Clements, John]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: John Clements 

-Original Message-
From: Chen, Guchun  
Sent: Thursday, April 16, 2020 11:48 PM
To: amd-gfx@lists.freedesktop.org; Zhang, Hawking ; Li, 
Dennis ; Clements, John 
Cc: Chen, Guchun 
Subject: [PATCH] drm/amdgpu: fix kernel page fault issue by ras recovery on sGPU

When running ras uncorrectable error injection and trigger GPU reset on sGPU, 
below issue is observed. It's caused by the list uninitialized when accessing.

[   80.047227] BUG: unable to handle page fault for address: c0f4f750
[   80.047300] #PF: supervisor write access in kernel mode
[   80.047351] #PF: error_code(0x0003) - permissions violation
[   80.047404] PGD 12c20e067 P4D 12c20e067 PUD 12c210067 PMD 41c4ee067 PTE 
404316061
[   80.047477] Oops: 0003 [#1] SMP PTI
[   80.047516] CPU: 7 PID: 377 Comm: kworker/7:2 Tainted: G   OE 
5.4.0-rc7-guchchen #1
[   80.047594] Hardware name: System manufacturer System Product Name/TUF 
Z370-PLUS GAMING II, BIOS 0411 09/21/2018
[   80.047888] Workqueue: events amdgpu_ras_do_recovery [amdgpu]

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index b27d9d62c9df..260b4a42e0ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -1448,9 +1448,10 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false);
 
/* Build list of devices to query RAS related errors */
-   if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
+   if  (hive && adev->gmc.xgmi.num_physical_nodes > 1)
device_list_handle = &hive->device_list;
-   } else {
+   else {
+   INIT_LIST_HEAD(&device_list);
list_add_tail(&adev->gmc.xgmi.head, &device_list);
device_list_handle = &device_list;
}
--
2.17.1
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RE: [PATCH] Revert "drm/amdgpu: use the BAR if possible in amdgpu_device_vram_access v2"

[Kim, Jonathan]

[AMD Official Use Only - Internal Distribution Only]

Hi Felix,

You're probably right.

Passing Vega20 system:
[   56.683273] amdgpu: [vram dbg] addr 3e78, val deadbeef
[   56.683349] amdgpu: [vram dbg] addr 3efed000, val cafebabe 
<- potential misalign access

Failing Vega20 system:
[Apr16 12:00] amdgpu: [vram dbg] addr be78, val deadbeef
[  +0.82] amdgpu: [vram dbg] addr befed000, val  <- 
potential misalign access

Thanks,

Jon

From: Kuehling, Felix 
Sent: Wednesday, April 15, 2020 11:02 AM
To: Koenig, Christian ; Kim, Jonathan 
; Deucher, Alexander 
Cc: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] Revert "drm/amdgpu: use the BAR if possible in 
amdgpu_device_vram_access v2"


[AMD Official Use Only - Internal Distribution Only]

The test does not access outside of the allocated memory. But it deliberately 
crosses a boundary where memory can be allocated non-contiguously. This is 
meant to catch problems where the access function doesn't handle non-contiguous 
VRAM allocations correctly. However, the way that VRAM allocation has been 
optimized, I expect that most allocations are contiguous nowadays. However, the 
more interesting aspect of the test is, that it performs misaligned memory 
accesses. The MMIO method of accessing VRAM explicitly handles misaligned 
accesses and breaks them down into dword aligned accesses with proper masking 
and shifting.

Could the unaligned nature of the memory access have something to do with 
hitting RAS errors? That's something unique to this test that we wouldn't see 
on a normal page table update or memory eviction.

Regards,
  Felix


From: Koenig, Christian 
mailto:christian.koe...@amd.com>>
Sent: Wednesday, April 15, 2020 6:58 AM
To: Kim, Jonathan mailto:jonathan@amd.com>>; 
Kuehling, Felix mailto:felix.kuehl...@amd.com>>; 
Deucher, Alexander mailto:alexander.deuc...@amd.com>>
Cc: Russell, Kent mailto:kent.russ...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH] Revert "drm/amdgpu: use the BAR if possible in 
amdgpu_device_vram_access v2"


To elaborate on the PTRACE test, we PEEK 2 DWORDs inside thunk allocated mapped 
memory and 2 DWORDS outside that boundary (it's only about 4MB to the 
boundary).  Then we POKE to swap the DWORD positions across the boundary.  The 
RAS event on the single failing machine happens on the out of boundary PEEK.

Well when you access outside of an allocated buffer I would expect that we 
never get as far as even touching the hardware because the kernel should block 
the access with an -EPERM or -EFAULT. So sounds like I'm not understanding 
something correctly here.

Apart from that I completely agree that we need to sort out any other RAS event 
first to make sure that the system is simply not failing randomly.

Regards,
Christian.

Am 15.04.20 um 11:49 schrieb Kim, Jonathan:

[AMD Public Use]



Hi Christian,



That could potentially be it.  With additional testing, 2 of 3 Vega20 machines 
never hit error over BAR access with the PTRACE test.  3 of 3 machines (from 
the same pool) always hit error with CWSR.

To elaborate on the PTRACE test, we PEEK 2 DWORDs inside thunk allocated mapped 
memory and 2 DWORDS outside that boundary (it's only about 4MB to the 
boundary).  Then we POKE to swap the DWORD positions across the boundary.  The 
RAS event on the single failing machine happens on the out of boundary PEEK.



Felix mentioned we don't hit errors over general HDP access but that may not 
true.  An Arcturus failure sys logs posted (which wasn't tested by me) shows 
someone launched rocm bandwidth test, hit a VM fault and a RAS event ensued 
during evictions (I can point the internal ticket or log snippet offline if 
interested).  Whether the RAS event is BAR access triggered or the result of HW 
instability is beyond me since I don't have access to the machine.



Thanks,



Jon



From: Koenig, Christian 

Sent: Wednesday, April 15, 2020 4:11 AM
To: Kim, Jonathan ; 
Kuehling, Felix ; 
Deucher, Alexander 
Cc: Russell, Kent ; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] Revert "drm/amdgpu: use the BAR if possible in 
amdgpu_device_vram_access v2"



Hi Jon,

Also cwsr tests fail on Vega20 with or without the revert with the same RAS 
error.

That sounds like the system/setup has a more general problem.

Could it be that we are seeing RAS errors because there really is some hardware 
failure, but with the MM path we don't trigger a RAS interrupt?

Thanks,
Christian.

Am 14.04.20 um 22:30 schrieb Kim, Jonathan:

[AMD Official Use Only - Internal Distribution Only]



If we're passing the test on th

[PATCH] Revert "drm/amdgpu: Disable gfx off if VCN is busy"

[James Zhu]

This reverts commit 3fded222f4bf7f4c56ef4854872a39a4de08f7a8
This is work around for vcn1 only. Currently vcn1 has separate
begin_use and idle work handle.

Signed-off-by: James Zhu 
Tested-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index dab34f6..2de99b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -353,7 +353,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
}
 
if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
-   amdgpu_gfx_off_ctrl(adev, true);
amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_GATE);
} else {
@@ -369,7 +368,6 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
cancel_delayed_work_sync(&adev->vcn.idle_work);
 
mutex_lock(&adev->vcn.vcn_pg_lock);
-   amdgpu_gfx_off_ctrl(adev, false);
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
   AMD_PG_STATE_UNGATE);
 
-- 
2.7.4

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Re: [PATCH] Revert "drm/amdgpu: Disable gfx off if VCN is busy"

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Is this ok for navi1x gfxoff?

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of James Zhu 

Sent: Thursday, April 16, 2020 12:24 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Zhu, James ; Zhu, Changfeng 
Subject: [PATCH] Revert "drm/amdgpu: Disable gfx off if VCN is busy"

This reverts commit 3fded222f4bf7f4c56ef4854872a39a4de08f7a8
This is work around for vcn1 only. Currently vcn1 has separate
begin_use and idle work handle.

Signed-off-by: James Zhu 
Tested-by: changzhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index dab34f6..2de99b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -353,7 +353,6 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct 
*work)
 }

 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
-   amdgpu_gfx_off_ctrl(adev, true);
 amdgpu_device_ip_set_powergating_state(adev, 
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
 } else {
@@ -369,7 +368,6 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
 cancel_delayed_work_sync(&adev->vcn.idle_work);

 mutex_lock(&adev->vcn.vcn_pg_lock);
-   amdgpu_gfx_off_ctrl(adev, false);
 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);

--
2.7.4

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Re: [bug report] drm/amd/display: Add HDCP module

[Lakha, Bhawanpreet]

[AMD Official Use Only - Internal Distribution Only]

Hi,

I will look into it, thanks.

Bhawan

From: Dan Carpenter 
Sent: April 16, 2020 9:24 AM
To: Lakha, Bhawanpreet 
Cc: amd-gfx@lists.freedesktop.org 
Subject: [bug report] drm/amd/display: Add HDCP module

Hello Bhawanpreet Lakha,

The patch 4c283fdac08a: "drm/amd/display: Add HDCP module" from Aug
6, 2019, leads to the following static checker warning:

drivers/gpu/drm/amd/amdgpu/../display/dc/hdcp/hdcp_msg.c:132 
hdmi_14_process_transaction()
error: buffer overflow 'hdcp_i2c_offsets' 32 <= 32

drivers/gpu/drm/amd/amdgpu/../display/dc/hdcp/hdcp_msg.c
77
78  static const uint8_t hdcp_i2c_offsets[] = {
79  [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
80  [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
81  [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
82  [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
83  [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
84  [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
85  [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
86  [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
87  [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
88  [HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
89  [HDCP_MESSAGE_ID_READ_VH_3] = 0x2C,
90  [HDCP_MESSAGE_ID_READ_VH_4] = 0x30,
91  [HDCP_MESSAGE_ID_READ_BCAPS] = 0x40,
92  [HDCP_MESSAGE_ID_READ_BSTATUS] = 0x41,
93  [HDCP_MESSAGE_ID_READ_KSV_FIFO] = 0x43,
94  [HDCP_MESSAGE_ID_READ_BINFO] = 0xFF,
95  [HDCP_MESSAGE_ID_HDCP2VERSION] = 0x50,
96  [HDCP_MESSAGE_ID_WRITE_AKE_INIT] = 0x60,
97  [HDCP_MESSAGE_ID_READ_AKE_SEND_CERT] = 0x80,
98  [HDCP_MESSAGE_ID_WRITE_AKE_NO_STORED_KM] = 0x60,
99  [HDCP_MESSAGE_ID_WRITE_AKE_STORED_KM] = 0x60,
   100  [HDCP_MESSAGE_ID_READ_AKE_SEND_H_PRIME] = 0x80,
   101  [HDCP_MESSAGE_ID_READ_AKE_SEND_PAIRING_INFO] = 0x80,
   102  [HDCP_MESSAGE_ID_WRITE_LC_INIT] = 0x60,
   103  [HDCP_MESSAGE_ID_READ_LC_SEND_L_PRIME] = 0x80,
   104  [HDCP_MESSAGE_ID_WRITE_SKE_SEND_EKS] = 0x60,
   105  [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_SEND_RECEIVERID_LIST] = 
0x80,
   106  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_SEND_ACK] = 0x60,
   107  [HDCP_MESSAGE_ID_WRITE_REPEATER_AUTH_STREAM_MANAGE] = 0x60,
   108  [HDCP_MESSAGE_ID_READ_REPEATER_AUTH_STREAM_READY] = 0x80,
   109  [HDCP_MESSAGE_ID_READ_RXSTATUS] = 0x70

HDCP_MESSAGE_ID_WRITE_CONTENT_STREAM_TYPE is missing.  This array should
have HDCP_MESSAGE_ID_MAX elements.

   110  };
   111
   112  struct protection_properties {
   113  bool supported;
   114  bool (*process_transaction)(
   115  struct dc_link *link,
   116  struct hdcp_protection_message *message_info);
   117  };
   118
   119  static const struct protection_properties non_supported_protection = {
   120  .supported = false
   121  };
   122
   123  static bool hdmi_14_process_transaction(
   124  struct dc_link *link,
   125  struct hdcp_protection_message *message_info)
   126  {
   127  uint8_t *buff = NULL;
   128  bool result;
   129  const uint8_t hdcp_i2c_addr_link_primary = 0x3a; /* 0x74 >> 1*/
   130  const uint8_t hdcp_i2c_addr_link_secondary = 0x3b; /* 0x76 >> 
1*/
   131  struct i2c_command i2c_command;
   132  uint8_t offset = hdcp_i2c_offsets[message_info->msg_id];
 ^^
Potential out of bounds access.

   133  struct i2c_payload i2c_payloads[] = {
   134  { true, 0, 1, &offset },
   135  /* actual hdcp payload, will be filled later, zeroed 
for now*/
   136  { 0 }
   137  };
   138

regards,
dan carpenter
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Re: [Intel-gfx] [PATCH 4/5] drm/amdgpu: utilize subconnector property for DP through atombios

[Jani Nikula]

On Thu, 16 Apr 2020, Alex Deucher  wrote:
> On Wed, Apr 15, 2020 at 6:05 AM Jani Nikula  wrote:
>>
>>
>> Alex, Harry, Christian, can you please eyeball this series and see if it
>> makes sense for you?
>>
>
> Patches 4, 5 are:
> Acked-by: Alex Deucher 
> Feel free to take them through whichever tree you want.

Thanks a bunch! I'll let you know.

BR,
Jani.

>
> Alex
>
>
>> Thanks,
>> Jani.
>>
>>
>> On Tue, 07 Apr 2020, Jeevan B  wrote:
>> > From: Oleg Vasilev 
>> >
>> > Since DP-specific information is stored in driver's structures, every
>> > driver needs to implement subconnector property by itself.
>> >
>> > v2: rebase
>> >
>> > Cc: Alex Deucher 
>> > Cc: Christian König 
>> > Cc: David (ChunMing) Zhou 
>> > Cc: amd-gfx@lists.freedesktop.org
>> > Signed-off-by: Jeevan B 
>> > Signed-off-by: Oleg Vasilev 
>> > Reviewed-by: Emil Velikov 
>> > Link: 
>> > https://patchwork.freedesktop.org/patch/msgid/20190829114854.1539-6-oleg.vasi...@intel.com
>> > ---
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++
>> >  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h   |  1 +
>> >  drivers/gpu/drm/amd/amdgpu/atombios_dp.c   | 18 +-
>> >  3 files changed, 28 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
>> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > index f355d9a..71aade0 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
>> > @@ -26,6 +26,7 @@
>> >
>> >  #include 
>> >  #include 
>> > +#include 
>> >  #include 
>> >  #include 
>> >  #include "amdgpu.h"
>> > @@ -1405,6 +1406,10 @@ amdgpu_connector_dp_detect(struct drm_connector 
>> > *connector, bool force)
>> >   pm_runtime_put_autosuspend(connector->dev->dev);
>> >   }
>> >
>> > + drm_dp_set_subconnector_property(&amdgpu_connector->base,
>> > +  ret,
>> > +  amdgpu_dig_connector->dpcd,
>> > +  
>> > amdgpu_dig_connector->downstream_ports);
>> >   return ret;
>> >  }
>> >
>> > @@ -1951,6 +1956,11 @@ amdgpu_connector_add(struct amdgpu_device *adev,
>> >   if (has_aux)
>> >   amdgpu_atombios_dp_aux_init(amdgpu_connector);
>> >
>> > + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
>> > + connector_type == DRM_MODE_CONNECTOR_eDP) {
>> > + 
>> > drm_mode_add_dp_subconnector_property(&amdgpu_connector->base);
>> > + }
>> > +
>> >   return;
>> >
>> >  failed:
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
>> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > index 37ba07e..04a430e 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
>> > @@ -469,6 +469,7 @@ struct amdgpu_encoder {
>> >  struct amdgpu_connector_atom_dig {
>> >   /* displayport */
>> >   u8 dpcd[DP_RECEIVER_CAP_SIZE];
>> > + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>> >   u8 dp_sink_type;
>> >   int dp_clock;
>> >   int dp_lane_count;
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c 
>> > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > index 9b74cfd..900b272 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
>> > @@ -328,6 +328,22 @@ static void amdgpu_atombios_dp_probe_oui(struct 
>> > amdgpu_connector *amdgpu_connect
>> > buf[0], buf[1], buf[2]);
>> >  }
>> >
>> > +static void amdgpu_atombios_dp_ds_ports(struct amdgpu_connector 
>> > *amdgpu_connector)
>> > +{
>> > + struct amdgpu_connector_atom_dig *dig_connector = 
>> > amdgpu_connector->con_priv;
>> > + int ret;
>> > +
>> > + if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) {
>> > + ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux,
>> > +DP_DOWNSTREAM_PORT_0,
>> > +dig_connector->downstream_ports,
>> > +DP_MAX_DOWNSTREAM_PORTS);
>> > + if (ret)
>> > + memset(dig_connector->downstream_ports, 0,
>> > +DP_MAX_DOWNSTREAM_PORTS);
>> > + }
>> > +}
>> > +
>> >  int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
>> >  {
>> >   struct amdgpu_connector_atom_dig *dig_connector = 
>> > amdgpu_connector->con_priv;
>> > @@ -343,7 +359,7 @@ int amdgpu_atombios_dp_get_dpcd(struct 
>> > amdgpu_connector *amdgpu_connector)
>> > dig_connector->dpcd);
>> >
>> >   amdgpu_atombios_dp_probe_oui(amdgpu_connector);
>> > -
>> > + amdgpu_atombios_dp_ds_ports(amdgpu_connector);
>> >   return 0;
>> >   }
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
>> ___
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>> dri-de

[PATCH] drm/amd/display: Remove aconnector condition check for dpcd read

[Zhan Liu]

[Why]
Aconnector is not necessary to be NULL in order to read dpcd
successfully.

Actually if we rely on checking aconnector here, we won't be able
to turn off all displays before doing display detection. That will
cause some MST hubs not able to light up.

[How]
Remove aconnector check when turning off all displays at
hardware initialization stage.

Signed-off-by: Zhan Liu 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ---
 1 file changed, 14 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f41efddc9bc..6f33f3f0d023 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1332,31 +1332,23 @@ void dcn10_init_hw(struct dc *dc)
if (dc->links[i]->connector_signal != 
SIGNAL_TYPE_DISPLAY_PORT)
continue;
 
-   /*
-* core_link_read_dpcd() will invoke 
dm_helpers_dp_read_dpcd(),
-* which needs to read dpcd info with the help of 
aconnector.
-* If aconnector (dc->links[i]->prev) is NULL, then 
dpcd status
-* cannot be read.
-*/
-   if (dc->links[i]->priv) {
-   /* if any of the displays are lit up turn them 
off */
-   status = core_link_read_dpcd(dc->links[i], 
DP_SET_POWER,
-   
&dpcd_power_state, sizeof(dpcd_power_state));
-   if (status == DC_OK && dpcd_power_state == 
DP_POWER_STATE_D0) {
-   /* blank dp stream before power off 
receiver*/
-   if 
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
-   unsigned int fe = 
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
-
-   for (j = 0; j < 
dc->res_pool->stream_enc_count; j++) {
-   if (fe == 
dc->res_pool->stream_enc[j]->id) {
-   
dc->res_pool->stream_enc[j]->funcs->dp_blank(
-   
dc->res_pool->stream_enc[j]);
-   break;
-   }
+   /* if any of the displays are lit up turn them off */
+   status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+   &dpcd_power_state, 
sizeof(dpcd_power_state));
+   if (status == DC_OK && dpcd_power_state == 
DP_POWER_STATE_D0) {
+   /* blank dp stream before power off receiver*/
+   if 
(dc->links[i]->link_enc->funcs->get_dig_frontend) {
+   unsigned int fe = 
dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+
+   for (j = 0; j < 
dc->res_pool->stream_enc_count; j++) {
+   if (fe == 
dc->res_pool->stream_enc[j]->id) {
+   
dc->res_pool->stream_enc[j]->funcs->dp_blank(
+   
dc->res_pool->stream_enc[j]);
+   break;
}
}
-   dp_receiver_power_ctrl(dc->links[i], 
false);
}
+   dp_receiver_power_ctrl(dc->links[i], false);
}
}
}
-- 
2.17.1

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[PATCH 1/2] drm/amdgpu: Add KFD interface to get ASIC revision

[Joseph Greathouse]

KFD need sto surface the ASIC revision in certain circumstances.
amdgpu already has this floating around, so add in an
amdgpu_amdkfd interface function to pull it over to KFD.

Signed-off-by: Joseph Greathouse 
Change-Id: I745196129d65e1d0d4349f8d3b3f828df961a603
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index abfbe89e805e..ad59ac4423b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -564,6 +564,13 @@ uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
return adev->gds.gws_size;
 }
 
+uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
+{
+   struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+
+   return adev->rev_id;
+}
+
 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
uint32_t vmid, uint64_t gpu_addr,
uint32_t *ib_cmd, uint32_t ib_len)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 13feb313e9b3..d065c50582eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -175,6 +175,7 @@ uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
+uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev 
*src);
 
 /* Read user wptr from a specified user address space with page fault
-- 
2.20.1

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[PATCH 2/2] drm/amdkfd: Put ASIC revision into HSA capability

[Joseph Greathouse]

In order to surface the ASIC revision to user level, we want
to put it into the HSA topology. This can be because different
ASIC revisions may require user-level software to do different
things (e.g. patch code for things that are changed in later
hardware revisions).

The ASIC revision from the hardware is maximum of 4 bits at this
time, so put it into 4 of the open bits in the HSA capability.
Then user-level software can use this capability information to
know -- for each ASIC -- what revision-based things must be done.

Signed-off-by: Joseph Greathouse 
Change-Id: If46b3a1864d0a7a67b95fddfc1dcd93932ca81d6
---
 drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 
 drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 5 -
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
index 5db42814dd51..6e52c95ce8b0 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
@@ -1303,6 +1303,10 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
 
dev->node_props.vendor_id = gpu->pdev->vendor;
dev->node_props.device_id = gpu->pdev->device;
+   dev->node_props.capability |=
+   ((amdgpu_amdkfd_get_asic_rev_id(dev->gpu->kgd) <<
+   HSA_CAP_ASIC_REVISION_SHIFT) &
+   HSA_CAP_ASIC_REVISION_MASK);
dev->node_props.location_id = pci_dev_id(gpu->pdev);
dev->node_props.max_engine_clk_fcompute =
amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
index 46eeecaf1b68..0c51bd3dcd59 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
@@ -41,7 +41,6 @@
 #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT   8
 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK   0x3000
 #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT  12
-#define HSA_CAP_RESERVED   0xc000
 
 #define HSA_CAP_DOORBELL_TYPE_PRE_1_0  0x0
 #define HSA_CAP_DOORBELL_TYPE_1_0  0x1
@@ -51,6 +50,10 @@
 #define HSA_CAP_SRAM_EDCSUPPORTED  0x0008
 #define HSA_CAP_MEM_EDCSUPPORTED   0x0010
 #define HSA_CAP_RASEVENTNOTIFY 0x0020
+#define HSA_CAP_ASIC_REVISION_MASK 0x03c0
+#define HSA_CAP_ASIC_REVISION_SHIFT22
+
+#define HSA_CAP_RESERVED   0xfc078000
 
 struct kfd_node_properties {
uint64_t hive_id;
-- 
2.20.1

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[PATCH 2/2] drm/amdgpu/display: give aux i2c buses more meaningful names

[Alex Deucher]

Mirror what we do for i2c display buses.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 3 ++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 7 +--
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h| 3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c113b676218d..735c01171d90 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4679,6 +4679,7 @@ static void amdgpu_dm_connector_destroy(struct 
drm_connector *connector)
i2c_del_adapter(&aconnector->i2c->base);
kfree(aconnector->i2c);
}
+   kfree(aconnector->dm_dp_aux.aux.name);
 
kfree(connector);
 }
@@ -6118,7 +6119,7 @@ static int amdgpu_dm_connector_init(struct 
amdgpu_display_manager *dm,
 
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
|| connector_type == DRM_MODE_CONNECTOR_eDP)
-   amdgpu_dm_initialize_dp_connector(dm, aconnector);
+   amdgpu_dm_initialize_dp_connector(dm, aconnector, 
link->link_index);
 
 out_free:
if (res) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 7d28b0482127..69056660672d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -429,9 +429,12 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 };
 
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-  struct amdgpu_dm_connector *aconnector)
+  struct amdgpu_dm_connector *aconnector,
+  int link_index)
 {
-   aconnector->dm_dp_aux.aux.name = "dmdc";
+   aconnector->dm_dp_aux.aux.name =
+   kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
+ link_index);
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index d6813ce67bbd..d2c56579a2cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -32,7 +32,8 @@ struct amdgpu_dm_connector;
 int dm_mst_get_pbn_divider(struct dc_link *link);
 
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-  struct amdgpu_dm_connector *aconnector);
+  struct amdgpu_dm_connector *aconnector,
+  int link_index);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
-- 
2.25.2

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[PATCH 1/2] drm/amdgpu/display: fix aux registration

[Alex Deucher]

We were registering the aux device in the MST late_register
rather than the regular one.

Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration 
(v4)")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 10 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c|  8 
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 417925a0d739..c113b676218d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4738,10 +4738,18 @@ amdgpu_dm_connector_atomic_duplicate_state(struct 
drm_connector *connector)
 static int
 amdgpu_dm_connector_late_register(struct drm_connector *connector)
 {
-#if defined(CONFIG_DEBUG_FS)
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
+   int r;
 
+   if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+   amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
+   r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
+   if (r)
+   return r;
+   }
+
+#if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index cb49f13c1548..7d28b0482127 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -113,16 +113,16 @@ amdgpu_dm_mst_connector_late_register(struct 
drm_connector *connector)
to_amdgpu_dm_connector(connector);
int r;
 
-   amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
-   r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
-   if (r)
+   r = drm_dp_mst_connector_late_register(connector,
+  amdgpu_dm_connector->port);
+   if (r < 0)
return r;
 
 #if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
 #endif
 
-   return r;
+   return 0;
 }
 
 static void
-- 
2.25.2

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[PATCH 2/2] drm/amdgpu/display: give aux i2c buses more meaningful names

[Alex Deucher]

Mirror what we do for i2c display buses.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 3 ++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 7 +--
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h| 3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fc81788f24b4..4a85076c36ab 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4679,6 +4679,7 @@ static void amdgpu_dm_connector_destroy(struct 
drm_connector *connector)
i2c_del_adapter(&aconnector->i2c->base);
kfree(aconnector->i2c);
}
+   kfree(aconnector->dm_dp_aux.aux.name);
 
kfree(connector);
 }
@@ -6119,7 +6120,7 @@ static int amdgpu_dm_connector_init(struct 
amdgpu_display_manager *dm,
 
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
|| connector_type == DRM_MODE_CONNECTOR_eDP)
-   amdgpu_dm_initialize_dp_connector(dm, aconnector);
+   amdgpu_dm_initialize_dp_connector(dm, aconnector, 
link->link_index);
 
 out_free:
if (res) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 7d28b0482127..69056660672d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -429,9 +429,12 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
 };
 
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-  struct amdgpu_dm_connector *aconnector)
+  struct amdgpu_dm_connector *aconnector,
+  int link_index)
 {
-   aconnector->dm_dp_aux.aux.name = "dmdc";
+   aconnector->dm_dp_aux.aux.name =
+   kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
+ link_index);
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index d6813ce67bbd..d2c56579a2cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -32,7 +32,8 @@ struct amdgpu_dm_connector;
 int dm_mst_get_pbn_divider(struct dc_link *link);
 
 void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
-  struct amdgpu_dm_connector *aconnector);
+  struct amdgpu_dm_connector *aconnector,
+  int link_index);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
-- 
2.25.2

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[PATCH 1/2] drm/amdgpu/display: fix aux registration (v2)

[Alex Deucher]

We were registering the aux device in the MST late_register
rather than the regular one.

v2: handle eDP as well

Fixes: 405a1f9090d1ac ("drm/amdgpu/display: split dp connector registration 
(v4)")
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1100
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c   |  8 
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 417925a0d739..fc81788f24b4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4738,10 +4738,19 @@ amdgpu_dm_connector_atomic_duplicate_state(struct 
drm_connector *connector)
 static int
 amdgpu_dm_connector_late_register(struct drm_connector *connector)
 {
-#if defined(CONFIG_DEBUG_FS)
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
+   int r;
 
+   if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
+   (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
+   amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
+   r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
+   if (r)
+   return r;
+   }
+
+#if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
 #endif
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index cb49f13c1548..7d28b0482127 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -113,16 +113,16 @@ amdgpu_dm_mst_connector_late_register(struct 
drm_connector *connector)
to_amdgpu_dm_connector(connector);
int r;
 
-   amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
-   r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
-   if (r)
+   r = drm_dp_mst_connector_late_register(connector,
+  amdgpu_dm_connector->port);
+   if (r < 0)
return r;
 
 #if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
 #endif
 
-   return r;
+   return 0;
 }
 
 static void
-- 
2.25.2

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Re: [PATCH 2/2] drm/amdkfd: Put ASIC revision into HSA capability

[Felix Kuehling]

Thank you Joe.

You can squash the two patches into one. KFD and AMDGPU are really one
component, and separating changes into separate commits is not
necessary. I'd also make amdgpu_amdkfd_get_asic_rev_id a static inline
function in amdgpu_amdkfd.h, since it's just a one-liner.

Other than that, this looks good to me.

Regards,
  Felix

Am 2020-04-16 um 3:33 p.m. schrieb Joseph Greathouse:
> In order to surface the ASIC revision to user level, we want
> to put it into the HSA topology. This can be because different
> ASIC revisions may require user-level software to do different
> things (e.g. patch code for things that are changed in later
> hardware revisions).
>
> The ASIC revision from the hardware is maximum of 4 bits at this
> time, so put it into 4 of the open bits in the HSA capability.
> Then user-level software can use this capability information to
> know -- for each ASIC -- what revision-based things must be done.
>
> Signed-off-by: Joseph Greathouse 
> Change-Id: If46b3a1864d0a7a67b95fddfc1dcd93932ca81d6
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 5 -
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 5db42814dd51..6e52c95ce8b0 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1303,6 +1303,10 @@ int kfd_topology_add_device(struct kfd_dev *gpu)
>  
>   dev->node_props.vendor_id = gpu->pdev->vendor;
>   dev->node_props.device_id = gpu->pdev->device;
> + dev->node_props.capability |=
> + ((amdgpu_amdkfd_get_asic_rev_id(dev->gpu->kgd) <<
> + HSA_CAP_ASIC_REVISION_SHIFT) &
> + HSA_CAP_ASIC_REVISION_MASK);
>   dev->node_props.location_id = pci_dev_id(gpu->pdev);
>   dev->node_props.max_engine_clk_fcompute =
>   amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h 
> b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> index 46eeecaf1b68..0c51bd3dcd59 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h
> @@ -41,7 +41,6 @@
>  #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8
>  #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x3000
>  #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT12
> -#define HSA_CAP_RESERVED 0xc000
>  
>  #define HSA_CAP_DOORBELL_TYPE_PRE_1_00x0
>  #define HSA_CAP_DOORBELL_TYPE_1_00x1
> @@ -51,6 +50,10 @@
>  #define HSA_CAP_SRAM_EDCSUPPORTED0x0008
>  #define HSA_CAP_MEM_EDCSUPPORTED 0x0010
>  #define HSA_CAP_RASEVENTNOTIFY   0x0020
> +#define HSA_CAP_ASIC_REVISION_MASK   0x03c0
> +#define HSA_CAP_ASIC_REVISION_SHIFT  22
> +
> +#define HSA_CAP_RESERVED 0xfc078000
>  
>  struct kfd_node_properties {
>   uint64_t hive_id;
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Re: [PATCH 2/2] drm/amdgpu/display: give aux i2c buses more meaningful names

[Harry Wentland]

On 2020-04-16 3:43 p.m., Alex Deucher wrote:
> Mirror what we do for i2c display buses.
> 
> Signed-off-by: Alex Deucher 

Series is
Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  | 3 ++-
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c| 7 +--
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h| 3 ++-
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index fc81788f24b4..4a85076c36ab 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4679,6 +4679,7 @@ static void amdgpu_dm_connector_destroy(struct 
> drm_connector *connector)
>   i2c_del_adapter(&aconnector->i2c->base);
>   kfree(aconnector->i2c);
>   }
> + kfree(aconnector->dm_dp_aux.aux.name);
>  
>   kfree(connector);
>  }
> @@ -6119,7 +6120,7 @@ static int amdgpu_dm_connector_init(struct 
> amdgpu_display_manager *dm,
>  
>   if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
>   || connector_type == DRM_MODE_CONNECTOR_eDP)
> - amdgpu_dm_initialize_dp_connector(dm, aconnector);
> + amdgpu_dm_initialize_dp_connector(dm, aconnector, 
> link->link_index);
>  
>  out_free:
>   if (res) {
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 7d28b0482127..69056660672d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -429,9 +429,12 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = 
> {
>  };
>  
>  void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> -struct amdgpu_dm_connector *aconnector)
> +struct amdgpu_dm_connector *aconnector,
> +int link_index)
>  {
> - aconnector->dm_dp_aux.aux.name = "dmdc";
> + aconnector->dm_dp_aux.aux.name =
> + kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
> +   link_index);
>   aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
>   aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
>  
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> index d6813ce67bbd..d2c56579a2cc 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
> @@ -32,7 +32,8 @@ struct amdgpu_dm_connector;
>  int dm_mst_get_pbn_divider(struct dc_link *link);
>  
>  void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
> -struct amdgpu_dm_connector *aconnector);
> +struct amdgpu_dm_connector *aconnector,
> +int link_index);
>  
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
>  bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
> 
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[PATCH 01/35] drm/amd/display: Correct updating logic of dcn21's pipe VM flags

[Rodrigo Siqueira]

From: Dale Zhao 

[Why]:
Renoir's pipe VM flags are not correctly updated if pipe strategy has
changed during some scenarios. It will result in watermarks mistakenly
calculation, thus underflow and garbage appear.

[How]:
Correctly update pipe VM flags to pipes which have been populated.

Signed-off-by: Dale Zhao 
Signed-off-by: Sung Lee 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 0e638a77b5ee..babc966cdabd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1709,12 +1709,8 @@ static int dcn21_populate_dml_pipes_from_context(
 {
uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, 
pipes);
int i;
-   struct resource_context *res_ctx = &context->res_ctx;
 
-   for (i = 0; i < dc->res_pool->pipe_count; i++) {
-
-   if (!res_ctx->pipe_ctx[i].stream)
-   continue;
+   for (i = 0; i < pipe_cnt; i++) {
 
pipes[i].pipe.src.hostvm = 1;
pipes[i].pipe.src.gpuvm = 1;
-- 
2.26.0

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[PATCH 02/35] drm/amd/display: Add user backlight level reg write

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Porting abm from dmcu to dmcub missed one register write.

[How]
Add this register write in the SetBacklightLevel sequence.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 06435ecaf6a3..59b2f0b621bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -136,6 +136,8 @@ static void dmcub_set_backlight_level(
 
dmub_abm_set_pipe(&dce_abm->base, otg_inst);
 
+   REG_UPDATE(BL1_PWM_USER_LEVEL, BL1_PWM_USER_LEVEL, 
backlight_pwm_u16_16);
+
if (otg_inst == 0)
frame_ramp = 0;
 
-- 
2.26.0

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[PATCH 26/35] drm/amd/display: destroy panel on link destruct

[Rodrigo Siqueira]

From: Anthony Koo 

[Why]
without destroy it is causing a memory leak

[How]
destroy panel on link destruct

Signed-off-by: Anthony Koo 
Reviewed-by: Wyatt Wood 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2e5a97190ce3..b38abd0c362a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -88,6 +88,9 @@ static void dc_link_destruct(struct dc_link *link)
if (link->ddc)
dal_ddc_service_destroy(&link->ddc);
 
+   if (link->panel)
+   link->panel->funcs->destroy(&link->panel);
+
if (link->link_enc)
link->link_enc->funcs->destroy(&link->link_enc);
 
-- 
2.26.0

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[PATCH 20/35] drm/amd/display: 3.2.81

[Rodrigo Siqueira]

From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 89cce79c950d..f9a2069ea30f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.80"
+#define DC_VER "3.2.81"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.26.0

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[PATCH 09/35] drm/amd/display: Check ramp != NULL before applying lut1d for degamma

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
A NULL ramp is a valid configuration for passing into
mod_color_calculate_degamma_params but we'll hit a NULL pointer if we do
so.

We need this in order to get the right transfer function to do degamma
on NV12 formats where we aren't supplied with a custom user degamma.

[How]
Add the NULL check.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Zhan Liu 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index cac09d500fda..d47253cdcc4e 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1902,7 +1902,7 @@ bool mod_color_calculate_degamma_params(struct 
dc_transfer_func *input_tf,
 
 
 
-   if (ramp->type == GAMMA_CUSTOM)
+   if (ramp && ramp->type == GAMMA_CUSTOM)
apply_lut_1d(ramp, MAX_HW_POINTS, tf_pts);
 
ret = true;
-- 
2.26.0

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[PATCH 25/35] drm/amd/display: dmcu wait loop calculation is incorrect in RV

[Rodrigo Siqueira]

From: Paul Hsieh 

[Why]
Driver already get display clock from SMU base on MHz, but driver read
again and mutiple 1000 cause wait loop value is overflow.

[How]
remove coding error

Signed-off-by: Paul Hsieh 
Reviewed-by: Eric Yang 
Acked-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c   | 3 ---
 1 file changed, 3 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 97b7f32294fd..c320b7af7d34 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -97,9 +97,6 @@ int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal 
*clk_mgr, int requested_di
VBIOSSMC_MSG_SetDispclkFreq,
requested_dispclk_khz / 1000);
 
-   /* Actual dispclk set is returned in the parameter register */
-   actual_dispclk_set_mhz = REG_READ(MP1_SMN_C2PMSG_83) * 1000;
-
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
if (clk_mgr->dfs_bypass_disp_clk != 
actual_dispclk_set_mhz)
-- 
2.26.0

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[PATCH 06/35] drm/amd/display: Add SetBacklight call to abm on dmcub

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Set backlight calls to firmware are are being prevented by dmcu == null
check. Dmcu is expected to be null in this case.

[How]
Only prevent call if dmcu and abm are null.  Also rename variable
'use_smooth_brightness' to 'fw_set_brightness' as it's more appropriate.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 10 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |  4 ++--
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c |  2 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   |  2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 00f70e43ed76..ef8184296a7e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2455,16 +2455,16 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
struct abm *abm = dc->res_pool->abm;
struct dmcu *dmcu = dc->res_pool->dmcu;
unsigned int controller_id = 0;
-   bool use_smooth_brightness = true;
+   bool fw_set_brightness = true;
int i;
DC_LOGGER_INIT(link->ctx->logger);
 
-   if ((dmcu == NULL) ||
-   (abm == NULL) ||
+   if ((dmcu == NULL && abm == NULL) ||
(abm->funcs->set_backlight_level_pwm == NULL))
return false;
 
-   use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
+   if (dmcu)
+   fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
 
DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
backlight_pwm_u16_16, backlight_pwm_u16_16);
@@ -2496,7 +2496,7 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
backlight_pwm_u16_16,
frame_ramp,
controller_id,
-   use_smooth_brightness);
+   fw_set_brightness);
}
 
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index e345df621a6a..4dae9efebb6f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -420,7 +420,7 @@ static bool dce_abm_set_backlight_level_pwm(
unsigned int backlight_pwm_u16_16,
unsigned int frame_ramp,
unsigned int controller_id,
-   bool use_smooth_brightness)
+   bool fw_set_brightness)
 {
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
 
@@ -428,7 +428,7 @@ static bool dce_abm_set_backlight_level_pwm(
backlight_pwm_u16_16, backlight_pwm_u16_16);
 
/* If DMCU is in reset state, DMCU is uninitialized */
-   if (use_smooth_brightness)
+   if (fw_set_brightness)
dmcu_set_backlight_level(abm_dce,
backlight_pwm_u16_16,
frame_ramp,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 8baebb594de5..a19f359e45d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -338,7 +338,7 @@ static bool dmub_abm_set_backlight_level_pwm(
unsigned int backlight_pwm_u16_16,
unsigned int frame_ramp,
unsigned int otg_inst,
-   bool use_smooth_brightness)
+   bool fw_set_brightness)
 {
struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
index 0cae258a903e..0dd12c4fc23c 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h
@@ -56,7 +56,7 @@ struct abm_funcs {
unsigned int backlight_pwm_u16_16,
unsigned int frame_ramp,
unsigned int controller_id,
-   bool use_smooth_brightness);
+   bool fw_set_brightness);
 
unsigned int (*get_current_backlight)(struct abm *abm);
unsigned int (*get_target_backlight)(struct abm *abm);
-- 
2.26.0

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[PATCH 00/35] DC Patches April 16, 2020

[Rodrigo Siqueira]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Improvements on:
  - DM color management
  - Backlight panel
* Fixes on:
  - Suspend issues
  - Virtual signal dsc setup
  - HDR visual confirm


Anthony Koo (4):
  drm/amd/display: make all backlight calls link based
  drm/amd/display: move panel power seq to new panel struct
  drm/amd/display: destroy panel on link destruct
  drm/amd/display: change from panel to panel cntl

Aric Cyr (3):
  drm/amd/display: Fix HDR visual confirm
  drm/amd/display: Update MPCC if requested
  drm/amd/display: 3.2.81

Aurabindo Pillai (1):
  drm/amd/display: DispalyPort: Write OUI only if panel supports it

Dale Zhao (1):
  drm/amd/display: Correct updating logic of dcn21's pipe VM flags

Dmytro Laktyushkin (2):
  drm/amd/display: fix stream setting for diags on silicon
  drm/amd/display: fix virtual signal dsc setup

Haiyi Zhou (1):
  drm/amd/display: Change infopacket type programming

Jaehyun Chung (1):
  drm/amd/display: Add HW rotation cursor changes to dcn10

Jinze Xu (1):
  drm/amd/display: Workaround to disable YCbCr

Joshua Aberback (1):
  drm/amd/display: Force watermark value propagation

Nicholas Kazlauskas (4):
  drm/amd/display: Check ramp != NULL before applying lut1d for degamma
  drm/amd/display: Avoid NULL pointer in set_backlight when ABM is NULL
  drm/amd/display: Use the correct input TF for video formats
  drm/amd/display: Factor in immediate flip support into DLG
calculations

Paul Hsieh (1):
  drm/amd/display: dmcu wait loop calculation is incorrect in RV

Rodrigo Siqueira (1):
  drm/amd/display: Fix green screen issue after suspend

Stylon Wang (2):
  drm/amd/display: Support plane-level gamut remap in DM
  drm/amd/display: Adjust refactored dm for color management only

Sung Lee (3):
  drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in
DCN2.1
  drm/amd/display: Cast int to float before division
  drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

Wenjing Liu (1):
  drm/amd/display: add optc get crc support for timings with ODM/DSC

Wyatt Wood (6):
  drm/amd/display: Add user backlight level reg write
  drm/amd/display: Move enable fractional pwm call
  drm/amd/display: Remove byte swapping for dmcub abm config table
  drm/amd/display: Add SetBacklight call to abm on dmcub
  drm/amd/display: Unify psr feature flags
  drm/amd/display: Various fixes for PSR on DMCUB

Xiaodong Yan (1):
  drm/amd/display: blank dp stream before re-train the link

Yongqiang Sun (1):
  drm/amd/display: access ABM from stream resource.

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  99 +--
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |  25 +++-
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |  10 +-
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |   2 +-
 .../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c  |   3 -
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  28 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 104 
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  29 -
 .../drm/amd/display/dc/core/dc_link_hwss.c|   2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c |   1 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   9 +-
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |   6 +
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  24 +++-
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   2 -
 drivers/gpu/drm/amd/display/dc/dce/Makefile   |   2 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  |   4 +-
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|  65 +++---
 .../drm/amd/display/dc/dce/dce_panel_cntl.c   | 105 
 .../drm/amd/display/dc/dce/dce_panel_cntl.h   | 117 ++
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c |  38 +++---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |  58 +++--
 .../amd/display/dc/dce100/dce100_resource.c   |  31 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  43 ++-
 .../display/dc/dce110/dce110_hw_sequencer.h   |   4 -
 .../amd/display/dc/dce110/dce110_resource.c   |  31 +
 .../amd/display/dc/dce112/dce112_resource.c   |  31 +
 .../amd/display/dc/dce120/dce120_resource.c   |  31 +
 .../drm/amd/display/dc/dce80/dce80_resource.c |  31 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |  18 ++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  20 +--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   2 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   7 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  31 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   8 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   2 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c |  14 ++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h |   7 ++
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  33 -
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   2 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  38 +-

[PATCH 27/35] drm/amd/display: fix virtual signal dsc setup

[Rodrigo Siqueira]

From: Dmytro Laktyushkin 

This prevents dpcd access on virtual links.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 51e0ee6e7695..6590f51caefa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -400,7 +400,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, 
bool enable)
struct dc_stream_state *stream = pipe_ctx->stream;
bool result = false;
 
-   if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
+   if (dc_is_virtual_signal(stream->signal) || 
IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
result = true;
else
result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, 
enable);
-- 
2.26.0

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[PATCH 28/35] drm/amd/display: Factor in immediate flip support into DLG calculations

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
We expect to be able to perform immediate flipping without having to
recalculate and update all the watermarks.

There are certain usecases today (1080p @ 90deg, 2160p @ 90deg) such
that we get a urgency value of 0 for frac_urg_bw_flip because we're
explicitly passing in a value of "false" for requiring immediate
flip support into the DLG calculation.

[How]
Always pass in true into the calculation. With this we get a correct
non-zero value for frac_urg_bw_flip.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 219aaed6e06e..6472c3a2d270 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -3033,7 +3033,7 @@ void dcn20_calculate_dlg_params(
pipe_idx,
cstate_en,

context->bw_ctx.bw.dcn.clk.p_state_change_support,
-   false, false, false);
+   false, false, true);
 

context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
&context->res_ctx.pipe_ctx[i].rq_regs,
-- 
2.26.0

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[PATCH 23/35] drm/amd/display: make all backlight calls link based

[Rodrigo Siqueira]

From: Anthony Koo 

[Why]
Backlight adjustment is tied to a specific display.  So make the calls
target a link rather than making it a global state.

[How]
make all backlight calls link based

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 10 ---
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 21 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 30 +++
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 --
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  2 ++
 5 files changed, 33 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 4b695f6a80c6..b3b7efd973ca 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1228,8 +1228,9 @@ static int current_backlight_read(struct seq_file *m, 
void *data)
struct drm_info_node *node = (struct drm_info_node *)m->private;
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private;
-   struct dc *dc = adev->dm.dc;
-   unsigned int backlight = dc_get_current_backlight_pwm(dc);
+   struct amdgpu_display_manager *dm = &adev->dm;
+
+   unsigned int backlight = 
dc_link_get_backlight_level(dm->backlight_link);
 
seq_printf(m, "0x%x\n", backlight);
return 0;
@@ -1245,8 +1246,9 @@ static int target_backlight_read(struct seq_file *m, void 
*data)
struct drm_info_node *node = (struct drm_info_node *)m->private;
struct drm_device *dev = node->minor->dev;
struct amdgpu_device *adev = dev->dev_private;
-   struct dc *dc = adev->dm.dc;
-   unsigned int backlight = dc_get_target_backlight_pwm(dc);
+   struct amdgpu_display_manager *dm = &adev->dm;
+
+   unsigned int backlight = 
dc_link_get_target_backlight_pwm(dm->backlight_link);
 
seq_printf(m, "0x%x\n", backlight);
return 0;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d5ecf2031255..0f7810571be3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2646,33 +2646,12 @@ void dc_set_power_state(
 
 void dc_resume(struct dc *dc)
 {
-
uint32_t i;
 
for (i = 0; i < dc->link_count; i++)
core_link_resume(dc->links[i]);
 }
 
-unsigned int dc_get_current_backlight_pwm(struct dc *dc)
-{
-   struct abm *abm = dc->res_pool->abm;
-
-   if (abm)
-   return abm->funcs->get_current_backlight(abm);
-
-   return 0;
-}
-
-unsigned int dc_get_target_backlight_pwm(struct dc *dc)
-{
-   struct abm *abm = dc->res_pool->abm;
-
-   if (abm)
-   return abm->funcs->get_target_backlight(abm);
-
-   return 0;
-}
-
 bool dc_is_dmcu_initialized(struct dc *dc)
 {
struct dmcu *dmcu = dc->res_pool->dmcu;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a926c1c3f57d..a784fd2078a8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2450,6 +2450,16 @@ int dc_link_get_backlight_level(const struct dc_link 
*link)
return (int) abm->funcs->get_current_backlight(abm);
 }
 
+int dc_link_get_target_backlight_pwm(const struct dc_link *link)
+{
+   struct abm *abm = link->ctx->dc->res_pool->abm;
+
+   if (abm == NULL || abm->funcs->get_target_backlight == NULL)
+   return DC_ERROR_UNEXPECTED;
+
+   return (int) abm->funcs->get_target_backlight(abm);
+}
+
 bool dc_link_set_backlight_level(const struct dc_link *link,
uint32_t backlight_pwm_u16_16,
uint32_t frame_ramp)
@@ -2507,14 +2517,24 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
 bool dc_link_set_abm_disable(const struct dc_link *link)
 {
struct dc  *dc = link->ctx->dc;
-   struct abm *abm = dc->res_pool->abm;
+   struct abm *abm = NULL;
+   bool success = false;
+   int i;
 
-   if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL))
-   return false;
+   for (i = 0; i < MAX_PIPES; i++) {
+   struct pipe_ctx pipe_ctx = 
dc->current_state->res_ctx.pipe_ctx[i];
+   struct dc_stream_state *stream = pipe_ctx.stream;
+
+   if (stream && stream->link == link) {
+   abm = pipe_ctx.stream_res.abm;
+   break;
+   }
+   }
 
-   abm->funcs->set_abm_immediate_disable(abm);
+   if (abm)
+   success = abm->funcs->set_abm_immediate_disable(abm);
 
-   return true;
+   return success;
 }
 
 bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, 
bool wait)
diff --git a/drivers/gpu/drm/amd

[PATCH 21/35] drm/amd/display: Various fixes for PSR on DMCUB

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
- Driver does not recognize new definitions of psr states.
- Internal tool is required for checking if psr is active.

[How]
- Parse psr state correctly so that driver will recognize psr state.
- Add visual confirmation that psr is active using existing mechanisms.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 45 ++-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  6 +++
 3 files changed, 51 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f9a2069ea30f..c46d4f8d4fe8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -241,6 +241,7 @@ enum visual_confirm {
VISUAL_CONFIRM_SURFACE = 1,
VISUAL_CONFIRM_HDR = 2,
VISUAL_CONFIRM_MPCTREE = 4,
+   VISUAL_CONFIRM_PSR = 5,
 };
 
 enum dcc_option {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index ccd40cffc26c..3b8a49e8e665 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -32,6 +32,45 @@
 
 #define MAX_PIPES 6
 
+/**
+ * Convert dmcub psr state to dmcu psr state.
+ */
+static void convert_psr_state(uint32_t *psr_state)
+{
+   if (*psr_state == 0)
+   *psr_state = 0;
+   else if (*psr_state == 0x10)
+   *psr_state = 1;
+   else if (*psr_state == 0x11)
+   *psr_state = 2;
+   else if (*psr_state == 0x20)
+   *psr_state = 3;
+   else if (*psr_state == 0x21)
+   *psr_state = 4;
+   else if (*psr_state == 0x30)
+   *psr_state = 5;
+   else if (*psr_state == 0x31)
+   *psr_state = 6;
+   else if (*psr_state == 0x40)
+   *psr_state = 7;
+   else if (*psr_state == 0x41)
+   *psr_state = 8;
+   else if (*psr_state == 0x42)
+   *psr_state = 9;
+   else if (*psr_state == 0x43)
+   *psr_state = 10;
+   else if (*psr_state == 0x44)
+   *psr_state = 11;
+   else if (*psr_state == 0x50)
+   *psr_state = 12;
+   else if (*psr_state == 0x51)
+   *psr_state = 13;
+   else if (*psr_state == 0x52)
+   *psr_state = 14;
+   else if (*psr_state == 0x53)
+   *psr_state = 15;
+}
+
 /**
  * Get PSR state from firmware.
  */
@@ -43,6 +82,8 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, 
uint32_t *psr_state)
dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30);
 
dmub_srv_get_gpint_response(srv, psr_state);
+
+   convert_psr_state(psr_state);
 }
 
 /**
@@ -158,7 +199,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
cmd.psr_copy_settings.header.payload_bytes = sizeof(struct 
dmub_cmd_psr_copy_settings_data);
 
// Hw insts
-   copy_settings_data->dpphy_inst  = 
psr_context->phyType;
+   copy_settings_data->dpphy_inst  = 
psr_context->transmitterId;
copy_settings_data->aux_inst= 
psr_context->channel;
copy_settings_data->digfe_inst  = 
psr_context->engineId;
copy_settings_data->digbe_inst  = 
psr_context->transmitterId;
@@ -183,6 +224,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
copy_settings_data->smu_optimizations_en= 
psr_context->allow_smu_optimizations;
copy_settings_data->frame_delay = 
psr_context->frame_delay;
copy_settings_data->frame_cap_ind   = 
psr_context->psrFrameCaptureIndicationReq;
+   copy_settings_data->debug.visual_confirm= 
dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
+   true : 
false;
 
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header);
dc_dmub_srv_cmd_execute(dc->dmub_srv);
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 0a996e575b9f..7c7a3561b6aa 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -215,6 +215,11 @@ struct dmub_rb_cmd_dpphy_init {
uint8_t reserved[60];
 };
 
+struct dmub_psr_debug_flags {
+   uint8_t visual_confirm : 1;
+   uint8_t reserved : 7;
+};
+
 struct dmub_cmd_psr_copy_settings_data {
uint16_t psr_level;
uint8_t dpp_inst;
@@ -228,6 +233,7 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
+   struct dmub_psr_debug_flags debug;
 };
 
 struct

[PATCH 04/35] drm/amd/display: Force watermark value propagation

[Rodrigo Siqueira]

From: Joshua Aberback 

[Why]
The HUBBUB watermark registers are in an area that cannot be power
gated, but the HUBP copies of the watermark values are in areas that can
be power gated. When we power on a pipe, it will not automatically take
the HUBBUB values, we need to force propagation by writing to a
watermark register.

[How]
 - new HUBBUB function to re-write current value in a WM register
 - touch WM register after enabling the plane in program_pipe

Signed-off-by: Joshua Aberback 
Reviewed-by: Jun Lei 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 5 -
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h   | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 7e65c774c800..efc7fb4cf44d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1478,8 +1478,11 @@ static void dcn20_program_pipe(
if (pipe_ctx->update_flags.bits.odm)
hws->funcs.update_odm(dc, context, pipe_ctx);
 
-   if (pipe_ctx->update_flags.bits.enable)
+   if (pipe_ctx->update_flags.bits.enable) {
dcn20_enable_plane(dc, pipe_ctx, context);
+   if (dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes)
+   
dc->res_pool->hubbub->funcs->force_wm_propagate_to_pipes(dc->res_pool->hubbub);
+   }
 
if (pipe_ctx->update_flags.raw || 
pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index f5dd0cc73c63..47a566d82d6e 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -144,6 +144,8 @@ struct hubbub_funcs {
void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
 
void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
+
+   void (*force_wm_propagate_to_pipes)(struct hubbub *hubbub);
 };
 
 struct hubbub {
-- 
2.26.0

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[PATCH 22/35] drm/amd/display: Cap certain DML values for Low Pix Clk on DCN2.1

[Rodrigo Siqueira]

From: Sung Lee 

[WHY]
In certain conditions with low pixel clock, some values in DML may go
past the max due to margining for latency hiding. This causes assertions
to get hit.

[HOW]
If the pixel clock is low and some values are high, cap it to the max.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
---
 .../display/dc/dml/dcn21/display_rq_dlg_calc_21.c| 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index 5430ced02bac..193f31b8ac4a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1490,13 +1490,21 @@ static void dml_rq_dlg_get_dlg_params(
disp_dlg_regs->refcyc_per_pte_group_vblank_l =
(unsigned int) (dst_y_per_row_vblank * (double) htotal
* ref_freq_to_pix_freq / (double) 
dpte_groups_per_row_ub_l);
-   ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned 
int)dml_pow(2, 13));
+   if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&
+   disp_dlg_regs->refcyc_per_pte_group_vblank_l >= 
(unsigned int)dml_pow(2, 13))
+   disp_dlg_regs->refcyc_per_pte_group_vblank_l = (1 << 13) - 1;
+   else
+   ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned 
int)dml_pow(2, 13));
 
if (dual_plane) {
disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) 
(dst_y_per_row_vblank
* (double) htotal * ref_freq_to_pix_freq
/ (double) dpte_groups_per_row_ub_c);
-   ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
+   if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) &&
+   disp_dlg_regs->refcyc_per_pte_group_vblank_c >= 
(unsigned int)dml_pow(2, 13))
+   disp_dlg_regs->refcyc_per_pte_group_vblank_c = (1 << 
13) - 1;
+   else
+   ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
< (unsigned int)dml_pow(2, 13));
}
 
-- 
2.26.0

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[PATCH 29/35] drm/amd/display: Add HW rotation cursor changes to dcn10

[Rodrigo Siqueira]

From: Jaehyun Chung 

[Why]
HW rotation was enabled in DAL3 but hubp cursor calculations for HW roation
were only added to dcn20.

[How]
Add hubp cursor position calculation changes to dcn10.

Signed-off-by: Jaehyun Chung 
Reviewed-by: Yongqiang Sun 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  | 18 +-
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 31b64733d693..319366ebb44f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -1139,6 +1139,8 @@ void hubp1_cursor_set_position(
int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
int x_hotspot = pos->x_hotspot;
int y_hotspot = pos->y_hotspot;
+   int cursor_height = (int)hubp->curs_attr.height;
+   int cursor_width = (int)hubp->curs_attr.width;
uint32_t dst_x_offset;
uint32_t cur_en = pos->enable ? 1 : 0;
 
@@ -1152,10 +1154,16 @@ void hubp1_cursor_set_position(
if (hubp->curs_attr.address.quad_part == 0)
return;
 
+   // Rotated cursor width/height and hotspots tweaks for offset 
calculation
if (param->rotation == ROTATION_ANGLE_90 || param->rotation == 
ROTATION_ANGLE_270) {
-   src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
-   y_hotspot = pos->x_hotspot;
-   x_hotspot = pos->y_hotspot;
+   swap(cursor_height, cursor_width);
+   if (param->rotation == ROTATION_ANGLE_90) {
+   src_x_offset = pos->x - pos->y_hotspot - 
param->viewport.x;
+   src_y_offset = pos->y - pos->x_hotspot - 
param->viewport.y;
+   }
+   } else if (param->rotation == ROTATION_ANGLE_180) {
+   src_x_offset = pos->x - param->viewport.x;
+   src_y_offset = pos->y - param->viewport.y;
}
 
if (param->mirror) {
@@ -1177,13 +1185,13 @@ void hubp1_cursor_set_position(
if (src_x_offset >= (int)param->viewport.width)
cur_en = 0;  /* not visible beyond right edge*/
 
-   if (src_x_offset + (int)hubp->curs_attr.width <= 0)
+   if (src_x_offset + cursor_width <= 0)
cur_en = 0;  /* not visible beyond left edge*/
 
if (src_y_offset >= (int)param->viewport.height)
cur_en = 0;  /* not visible beyond bottom edge*/
 
-   if (src_y_offset + (int)hubp->curs_attr.height <= 0)
+   if (src_y_offset + cursor_height <= 0)
cur_en = 0;  /* not visible beyond top edge*/
 
if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
-- 
2.26.0

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[PATCH 35/35] drm/amd/display: Fix green screen issue after suspend

[Rodrigo Siqueira]

[why]
We have seen a green screen after resume from suspend in a Raven system
connected with two displays (HDMI and DP) on X based system. We noticed
that this issue is related to bad DCC metadata from user space which may
generate hangs and consequently an underflow on HUBP. After taking a
deep look at the code path we realized that after resume we try to
restore the commit with the DCC enabled framebuffer but the framebuffer
is no longer valid.

[how]
This problem was only reported on Raven based system and after suspend,
for this reason, this commit adds a new parameter on
fill_plane_dcc_attributes() to give the option of disabling DCC
programmatically. In summary, for disabling DCC we first verify if is a
Raven system and if it is in suspend; if both conditions are true we
disable DCC temporarily, otherwise, it is enabled.

Co-developed-by: Nicholas Kazlauskas 
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 ++-
 1 file changed, 29 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 209b9bf8bf11..04098b344ca3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3421,7 +3421,8 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
  const union dc_tiling_info *tiling_info,
  const uint64_t info,
  struct dc_plane_dcc_param *dcc,
- struct dc_plane_address *address)
+ struct dc_plane_address *address,
+ bool force_disable_dcc)
 {
struct dc *dc = adev->dm.dc;
struct dc_dcc_surface_param input;
@@ -3433,6 +3434,9 @@ fill_plane_dcc_attributes(struct amdgpu_device *adev,
memset(&input, 0, sizeof(input));
memset(&output, 0, sizeof(output));
 
+   if (force_disable_dcc)
+   return 0;
+
if (!offset)
return 0;
 
@@ -3483,7 +3487,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
 struct plane_size *plane_size,
 struct dc_plane_dcc_param *dcc,
 struct dc_plane_address *address,
-bool tmz_surface)
+bool tmz_surface,
+bool force_disable_dcc)
 {
const struct drm_framebuffer *fb = &afb->base;
int ret;
@@ -3591,7 +3596,8 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
 
ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
plane_size, tiling_info,
-   tiling_flags, dcc, address);
+   tiling_flags, dcc, address,
+   force_disable_dcc);
if (ret)
return ret;
}
@@ -3684,7 +3690,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
const uint64_t tiling_flags,
struct dc_plane_info *plane_info,
struct dc_plane_address *address,
-   bool tmz_surface)
+   bool tmz_surface,
+   bool force_disable_dcc)
 {
const struct drm_framebuffer *fb = plane_state->fb;
const struct amdgpu_framebuffer *afb =
@@ -3766,7 +3773,8 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
   plane_info->rotation, tiling_flags,
   &plane_info->tiling_info,
   &plane_info->plane_size,
-  &plane_info->dcc, address, 
tmz_surface);
+  &plane_info->dcc, address,
+  tmz_surface, force_disable_dcc);
if (ret)
return ret;
 
@@ -3790,6 +3798,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device 
*adev,
uint64_t tiling_flags;
int ret;
bool tmz_surface = false;
+   bool force_disable_dcc = false;
 
ret = fill_dc_scaling_info(plane_state, &scaling_info);
if (ret)
@@ -3804,10 +3813,12 @@ static int fill_dc_plane_attributes(struct 
amdgpu_device *adev,
if (ret)
return ret;
 
+   force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
  &plane_info,
  &dc_plane_state->address,
-   

[PATCH 32/35] drm/amd/display: blank dp stream before re-train the link

[Rodrigo Siqueira]

From: Xiaodong Yan 

[Why]
When link loss happened, monitor can not light up if only re-train the
link.

[How]
Blank all the DP streams on this link before re-train the link, and then
unblank the stream

Signed-off-by: Xiaodong Yan 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5d2ae2fb7e45..a87302f729c7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2899,6 +2899,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, 
union hpd_irq_data *out_hpd
sizeof(hpd_irq_dpcd_data),
"Status: ");
 
+   for (i = 0; i < MAX_PIPES; i++) {
+   pipe_ctx = 
&link->dc->current_state->res_ctx.pipe_ctx[i];
+   if (pipe_ctx && pipe_ctx->stream && 
pipe_ctx->stream->link == link)
+   link->dc->hwss.blank_stream(pipe_ctx);
+   }
+
for (i = 0; i < MAX_PIPES; i++) {
pipe_ctx = 
&link->dc->current_state->res_ctx.pipe_ctx[i];
if (pipe_ctx && pipe_ctx->stream && 
pipe_ctx->stream->link == link)
@@ -2918,6 +2924,12 @@ bool dc_link_handle_hpd_rx_irq(struct dc_link *link, 
union hpd_irq_data *out_hpd
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
dc_link_reallocate_mst_payload(link);
 
+   for (i = 0; i < MAX_PIPES; i++) {
+   pipe_ctx = 
&link->dc->current_state->res_ctx.pipe_ctx[i];
+   if (pipe_ctx && pipe_ctx->stream && 
pipe_ctx->stream->link == link)
+   link->dc->hwss.unblank_stream(pipe_ctx, 
&previous_link_settings);
+   }
+
status = false;
if (out_link_loss)
*out_link_loss = true;
-- 
2.26.0

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[PATCH 31/35] drm/amd/display: DispalyPort: Write OUI only if panel supports it

[Rodrigo Siqueira]

From: Aurabindo Pillai 

[why]
Organizational Unit Identifier register is optional, and its
presence is published via Down Stream Port Count register.
Writing this register when not available will result in errors

[how]
Read this register and continue writing OUI only if the panel
has the support advertised.

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Aric Cyr 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 3408c36ace48..5d2ae2fb7e45 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -4218,6 +4218,21 @@ void dp_set_fec_enable(struct dc_link *link, bool enable)
 void dpcd_set_source_specific_data(struct dc_link *link)
 {
const uint32_t post_oui_delay = 30; // 30ms
+   uint8_t dspc = 0;
+   enum dc_status ret = DC_ERROR_UNEXPECTED;
+
+   ret = core_link_read_dpcd(link, DP_DOWN_STREAM_PORT_COUNT, &dspc,
+ sizeof(dspc));
+
+   if (ret != DC_OK) {
+   DC_LOG_ERROR("Error in DP aux read transaction,"
+" not writing source specific data\n");
+   return;
+   }
+
+   /* Return if OUI unsupported */
+   if (!(dspc & DP_OUI_SUPPORT))
+   return;
 
if (!link->dc->vendor_signature.is_valid) {
struct dpcd_amd_signature amd_signature;
-- 
2.26.0

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[PATCH 11/35] drm/amd/display: add optc get crc support for timings with ODM/DSC

[Rodrigo Siqueira]

From: Wenjing Liu 

[why]
Optc needs to know if timing is enabled with ODM or DSC before computing
crc.  Otherwise value computed will be inaccurate. Before this change,
the CRC computed without ODM is not equal to the CRC computed with ODM
for the same timing. This is unexpected as we are driving the same
timing despite of the underlaying hardware setup to achieve it. This is
caused by missing hardware programming sequence to support it.

[how]
Add the new programming sequence based on hardware guide.

Signed-off-by: Wenjing Liu 
Reviewed-by: Nikola Cornij 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  5 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h  |  7 ++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c  | 14 +-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h  |  7 +++
 .../drm/amd/display/dc/inc/hw/timing_generator.h   |  3 +++
 5 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 9bde05547b30..d5ecf2031255 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -350,7 +350,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct 
dc_stream_state *stream,
 
for (i = 0; i < MAX_PIPES; i++) {
pipe = &dc->current_state->res_ctx.pipe_ctx[i];
-   if (pipe->stream == stream)
+   if (pipe->stream == stream && !pipe->top_pipe && 
!pipe->prev_odm_pipe)
break;
}
/* Stream not found */
@@ -367,6 +367,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct 
dc_stream_state *stream,
param.windowb_x_end = pipe->stream->timing.h_addressable;
param.windowb_y_end = pipe->stream->timing.v_addressable;
 
+   param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0;
+   param.odm_mode = pipe->next_odm_pipe ? 1:0;
+
/* Default to the union of both windows */
param.selection = UNION_WINDOW_A_B;
param.continuous_mode = continuous;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 9a459a8fe8a0..8d1e52fb0393 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -158,6 +158,7 @@ struct dcn_optc_registers {
uint32_t OTG_GSL_WINDOW_Y;
uint32_t OTG_VUPDATE_KEEPOUT;
uint32_t OTG_CRC_CNTL;
+   uint32_t OTG_CRC_CNTL2;
uint32_t OTG_CRC0_DATA_RG;
uint32_t OTG_CRC0_DATA_B;
uint32_t OTG_CRC0_WINDOWA_X_CONTROL;
@@ -475,7 +476,11 @@ struct dcn_optc_registers {
type OPTC_DSC_SLICE_WIDTH;\
type OPTC_SEGMENT_WIDTH;\
type OPTC_DWB0_SOURCE_SELECT;\
-   type OPTC_DWB1_SOURCE_SELECT;
+   type OPTC_DWB1_SOURCE_SELECT;\
+   type OTG_CRC_DSC_MODE;\
+   type OTG_CRC_DATA_STREAM_COMBINE_MODE;\
+   type OTG_CRC_DATA_STREAM_SPLIT_MODE;\
+   type OTG_CRC_DATA_FORMAT;
 
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index d875b0c38fde..8c16967fe018 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -409,6 +409,18 @@ void optc2_program_manual_trigger(struct timing_generator 
*optc)
OTG_TRIGA_MANUAL_TRIG, 1);
 }
 
+bool optc2_configure_crc(struct timing_generator *optc,
+ const struct crc_params *params)
+{
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+   REG_SET_2(OTG_CRC_CNTL2, 0,
+   OTG_CRC_DSC_MODE, params->dsc_mode,
+   OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode);
+
+   return optc1_configure_crc(optc, params);
+}
+
 static struct timing_generator_funcs dcn20_tg_funcs = {
.validate_timing = optc1_validate_timing,
.program_timing = optc1_program_timing,
@@ -452,7 +464,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.clear_optc_underflow = optc1_clear_optc_underflow,
.setup_global_swap_lock = NULL,
.get_crc = optc1_get_crc,
-   .configure_crc = optc1_configure_crc,
+   .configure_crc = optc2_configure_crc,
.set_dsc_config = optc2_set_dsc_config,
.set_dwb_source = optc2_set_dwb_source,
.set_odm_bypass = optc2_set_odm_bypass,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index 239cc40ae474..e0a0a8a8e2c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -36,6 +36,7 @@
SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
SRI(OTG_DSC_START_POSITION, OTG, inst),\
+   SR

[PATCH 12/35] drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1

[Rodrigo Siqueira]

From: Sung Lee 

[WHY]:
Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead
to a large number causing an assert to get hit. In VBA, this value is 0
when DCC is disabled.

[HOW]:
Set value to 0 to avoid hitting the assert.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
---
 .../drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c| 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
index a38baa73d484..5430ced02bac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c
@@ -1500,9 +1500,12 @@ static void dml_rq_dlg_get_dlg_params(
< (unsigned int)dml_pow(2, 13));
}
 
-   disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
+   if (src->dcc)
+   disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
(unsigned int) (dst_y_per_row_vblank * (double) htotal
* ref_freq_to_pix_freq / (double) 
meta_chunks_per_row_ub_l);
+   else
+   disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0;
ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned 
int)dml_pow(2, 13));
 
disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
-- 
2.26.0

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[PATCH 30/35] drm/amd/display: change from panel to panel cntl

[Rodrigo Siqueira]

From: Anthony Koo 

[Why]
it doesn't represent panel specifically, it's more like the control
logic for the panel

[How]
change from panel to panel cntl to make it a bit more clear

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 34 
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  2 +-
 drivers/gpu/drm/amd/display/dc/dce/Makefile   |  2 +-
 .../dc/dce/{dce_panel.c => dce_panel_cntl.c}  | 64 +++---
 .../dc/dce/{dce_panel.h => dce_panel_cntl.h}  | 86 +--
 .../amd/display/dc/dce100/dce100_resource.c   | 34 
 .../display/dc/dce110/dce110_hw_sequencer.c   | 10 ++-
 .../amd/display/dc/dce110/dce110_resource.c   | 34 
 .../amd/display/dc/dce112/dce112_resource.c   | 34 
 .../amd/display/dc/dce120/dce120_resource.c   | 34 
 .../drm/amd/display/dc/dce80/dce80_resource.c | 34 
 .../drm/amd/display/dc/dcn10/dcn10_resource.c | 34 
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 34 
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 34 
 .../gpu/drm/amd/display/dc/inc/core_types.h   |  6 +-
 .../dc/inc/hw/{panel.h => panel_cntl.h}   | 24 +++---
 16 files changed, 251 insertions(+), 249 deletions(-)
 rename drivers/gpu/drm/amd/display/dc/dce/{dce_panel.c => dce_panel_cntl.c} 
(55%)
 rename drivers/gpu/drm/amd/display/dc/dce/{dce_panel.h => dce_panel_cntl.h} 
(50%)
 rename drivers/gpu/drm/amd/display/dc/inc/hw/{panel.h => panel_cntl.h} (75%)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b38abd0c362a..0d8fae4e9441 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -47,7 +47,7 @@
 #include "hw/clk_mgr.h"
 #include "dce/dmub_psr.h"
 #include "dmub/inc/dmub_cmd_dal.h"
-#include "inc/hw/panel.h"
+#include "inc/hw/panel_cntl.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -88,8 +88,8 @@ static void dc_link_destruct(struct dc_link *link)
if (link->ddc)
dal_ddc_service_destroy(&link->ddc);
 
-   if (link->panel)
-   link->panel->funcs->destroy(&link->panel);
+   if (link->panel_cntl)
+   link->panel_cntl->funcs->destroy(&link->panel_cntl);
 
if (link->link_enc)
link->link_enc->funcs->destroy(&link->link_enc);
@@ -1359,7 +1359,7 @@ static bool dc_link_construct(struct dc_link *link,
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
-   struct panel_init_data panel_init_data = { 0 };
+   struct panel_cntl_init_data panel_cntl_init_data = { 0 };
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
@@ -1461,18 +1461,18 @@ static bool dc_link_construct(struct dc_link *link,
dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
 
 
-   if (link->dc->res_pool->funcs->panel_create &&
+   if (link->dc->res_pool->funcs->panel_cntl_create &&
(link->link_id.id == CONNECTOR_ID_EDP ||
link->link_id.id == CONNECTOR_ID_LVDS)) {
-   panel_init_data.ctx = dc_ctx;
-   panel_init_data.inst = 0;
-   link->panel =
-   link->dc->res_pool->funcs->panel_create(
-   
&panel_init_data);
-
-   if (link->panel == NULL) {
-   DC_ERROR("Failed to create link panel!\n");
-   goto panel_create_fail;
+   panel_cntl_init_data.ctx = dc_ctx;
+   panel_cntl_init_data.inst = 0;
+   link->panel_cntl =
+   link->dc->res_pool->funcs->panel_cntl_create(
+   
&panel_cntl_init_data);
+
+   if (link->panel_cntl == NULL) {
+   DC_ERROR("Failed to create link panel_cntl!\n");
+   goto panel_cntl_create_fail;
}
}
 
@@ -1558,9 +1558,9 @@ static bool dc_link_construct(struct dc_link *link,
 device_tag_fail:
link->link_enc->funcs->destroy(&link->link_enc);
 link_enc_create_fail:
-   if (link->panel != NULL)
-   link->panel->funcs->destroy(&link->panel);
-panel_create_fail:
+   if (link->panel_cntl != NULL)
+   link->panel_cntl->funcs->destroy(&link->panel_cntl);
+panel_cntl_create_fail:
dal_ddc_service_destroy(&link->ddc);
 ddc_create_fail:
 create_fail:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 31c9706f1b0b..80fb4149f36a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/d

[PATCH 19/35] drm/amd/display: Update MPCC if requested

[Rodrigo Siqueira]

From: Aric Cyr 

Don't skip MPCC tree updates if requested.

Signed-off-by: Aric Cyr 
Reviewed-by: Joshua Aberback 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index efc7fb4cf44d..6ad4ed7da629 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2175,7 +2175,8 @@ void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx 
*pipe_ctx)
mpcc_id = hubp->inst;
 
/* If there is no full update, don't need to touch MPC tree*/
-   if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
+   if (!pipe_ctx->plane_state->update_flags.bits.full_update &&
+   !pipe_ctx->update_flags.bits.mpcc) {
mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
return;
}
-- 
2.26.0

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[PATCH 16/35] drm/amd/display: Change infopacket type programming

[Rodrigo Siqueira]

From: Haiyi Zhou 

[Why]
Certain displays may experience blanking if infopacket max range does
not equal nominal refresh rate.

[How]
Add additional infopacket versions to program range to full or forced
range in freesync states.
This does not change the vrr logic.

Signed-off-by: Haiyi Zhou 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/modules/freesync/freesync.c   | 101 --
 .../amd/display/modules/inc/mod_freesync.h|   3 +
 .../drm/amd/display/modules/inc/mod_shared.h  |   5 +-
 3 files changed, 99 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c 
b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
index c33454a9e0b4..eb7421e83b86 100644
--- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
+++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
@@ -443,7 +443,7 @@ static bool vrr_settings_require_update(struct 
core_freesync *core_freesync,
return true;
} else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
in_vrr->fixed.target_refresh_in_uhz !=
-   in_config->min_refresh_in_uhz) {
+   in_config->fixed_refresh_in_uhz) {
return true;
} else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
return true;
@@ -491,7 +491,7 @@ bool mod_freesync_get_v_position(struct mod_freesync 
*mod_freesync,
return false;
 }
 
-static void build_vrr_infopacket_data(const struct mod_vrr_params *vrr,
+static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
struct dc_info_packet *infopacket)
 {
/* PB1 = 0x1A (24bit AMD IEEE OUI (0x1A) - Byte 0) */
@@ -523,14 +523,74 @@ static void build_vrr_infopacket_data(const struct 
mod_vrr_params *vrr,
vrr->state == VRR_STATE_ACTIVE_FIXED)
infopacket->sb[6] |= 0x04;
 
+   // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full 
range
/* PB7 = FreeSync Minimum refresh rate (Hz) */
-   infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 50) 
/ 100);
+   if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+   vrr->state == VRR_STATE_ACTIVE_FIXED) {
+   infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 
50) / 100);
+   } else {
+   infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 
50) / 100);
+   }
 
/* PB8 = FreeSync Maximum refresh rate (Hz)
 * Note: We should never go above the field rate of the mode timing set.
 */
infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 50) 
/ 100);
 
+   //FreeSync HDR
+   infopacket->sb[9] = 0;
+   infopacket->sb[10] = 0;
+}
+
+static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
+   struct dc_info_packet *infopacket)
+{
+   /* PB1 = 0x1A (24bit AMD IEEE OUI (0x1A) - Byte 0) */
+   infopacket->sb[1] = 0x1A;
+
+   /* PB2 = 0x00 (24bit AMD IEEE OUI (0x1A) - Byte 1) */
+   infopacket->sb[2] = 0x00;
+
+   /* PB3 = 0x00 (24bit AMD IEEE OUI (0x1A) - Byte 2) */
+   infopacket->sb[3] = 0x00;
+
+   /* PB4 = Reserved */
+
+   /* PB5 = Reserved */
+
+   /* PB6 = [Bits 7:3 = Reserved] */
+
+   /* PB6 = [Bit 0 = FreeSync Supported] */
+   if (vrr->state != VRR_STATE_UNSUPPORTED)
+   infopacket->sb[6] |= 0x01;
+
+   /* PB6 = [Bit 1 = FreeSync Enabled] */
+   if (vrr->state != VRR_STATE_DISABLED &&
+   vrr->state != VRR_STATE_UNSUPPORTED)
+   infopacket->sb[6] |= 0x02;
+
+   /* PB6 = [Bit 2 = FreeSync Active] */
+   if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
+   vrr->state == VRR_STATE_ACTIVE_FIXED)
+   infopacket->sb[6] |= 0x04;
+
+   if (vrr->state == VRR_STATE_ACTIVE_FIXED) {
+   /* PB7 = FreeSync Minimum refresh rate (Hz) */
+   infopacket->sb[7] = (unsigned char)((vrr->fixed_refresh_in_uhz 
+ 50) / 100);
+   /* PB8 = FreeSync Maximum refresh rate (Hz) */
+   infopacket->sb[8] = (unsigned char)((vrr->fixed_refresh_in_uhz 
+ 50) / 100);
+   } else if (vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
+   /* PB7 = FreeSync Minimum refresh rate (Hz) */
+   infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 
50) / 100);
+   /* PB8 = FreeSync Maximum refresh rate (Hz) */
+   infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 
50) / 100);
+   } else {
+   // Non-fs case, program nominal range
+   /* PB7 = FreeSync Minimum refresh rate (Hz) */
+   infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 
50) / 100

[PATCH 03/35] drm/amd/display: Move enable fractional pwm call

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Dmcu init fw call has some logic to initialize abm values.  Since this
doesn't exist on dmcub, must find a proper place for it in the abm
sequence.

[How]
Move enable fractional pwm call.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c | 34 +--
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
index 59b2f0b621bd..8baebb594de5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm.c
@@ -161,6 +161,21 @@ static void dmcub_set_backlight_level(
REG_WRITE(BIOS_SCRATCH_2, s2);
 }
 
+static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
+{
+   union dmub_rb_cmd cmd;
+   uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == 
false) ? 1 : 0;
+
+   cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
+   cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
+   cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = 
fractional_pwm;
+   cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct 
dmub_cmd_abm_set_pwm_frac_data);
+
+   dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.abm_set_pwm_frac.header);
+   dc_dmub_srv_cmd_execute(dc->dmub_srv);
+   dc_dmub_srv_wait_idle(dc->dmub_srv);
+}
+
 static void dmub_abm_init(struct abm *abm)
 {
struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
@@ -199,6 +214,8 @@ static void dmub_abm_init(struct abm *abm)
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, 1,
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, 1,
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, 1);
+
+   dmub_abm_enable_fractional_pwm(abm->ctx);
 }
 
 static unsigned int dmub_abm_get_current_backlight(struct abm *abm)
@@ -259,28 +276,11 @@ static bool dmub_abm_immediate_disable(struct abm *abm)
return true;
 }
 
-static void dmub_abm_enable_fractional_pwm(struct dc_context *dc)
-{
-   union dmub_rb_cmd cmd;
-   uint32_t fractional_pwm = (dc->dc->config.disable_fractional_pwm == 
false) ? 1 : 0;
-
-   cmd.abm_set_pwm_frac.header.type = DMUB_CMD__ABM;
-   cmd.abm_set_pwm_frac.header.sub_type = DMUB_CMD__ABM_SET_PWM_FRAC;
-   cmd.abm_set_pwm_frac.abm_set_pwm_frac_data.fractional_pwm = 
fractional_pwm;
-   cmd.abm_set_pwm_frac.header.payload_bytes = sizeof(struct 
dmub_cmd_abm_set_pwm_frac_data);
-
-   dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.abm_set_pwm_frac.header);
-   dc_dmub_srv_cmd_execute(dc->dmub_srv);
-   dc_dmub_srv_wait_idle(dc->dmub_srv);
-}
-
 static bool dmub_abm_init_backlight(struct abm *abm)
 {
struct dce_abm *dce_abm = TO_DMUB_ABM(abm);
uint32_t value;
 
-   dmub_abm_enable_fractional_pwm(abm->ctx);
-
/* It must not be 0, so we have to restore them
 * Bios bug w/a - period resets to zero,
 * restoring to cache values which is always correct
-- 
2.26.0

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[PATCH 14/35] drm/amd/display: fix stream setting for diags on silicon

[Rodrigo Siqueira]

From: Dmytro Laktyushkin 

We need to set up stream even with virtual displays when running
diags.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 44b8efa3510b..1c5c11d6347e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3067,7 +3067,7 @@ void core_link_enable_stream(
enum dc_status status;
DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
 
-   if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+   if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
 
@@ -3217,7 +3217,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
struct dc_stream_state *stream = pipe_ctx->stream;
struct dc_link *link = stream->sink->link;
 
-   if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) &&
+   if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
dc_is_virtual_signal(pipe_ctx->stream->signal))
return;
 
-- 
2.26.0

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[PATCH 07/35] drm/amd/display: Support plane-level gamut remap in DM

[Rodrigo Siqueira]

From: Stylon Wang 

[Why]
Plane-level gamut remap is not enabled in DM, which is necessary to
support CTM as a plane-level property.

[How]
Enable gamut remap in DM.

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c86b32d4274b..47d12c38bc71 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6728,6 +6728,7 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
if (new_pcrtc_state->color_mgmt_changed) {
bundle->surface_updates[planes_count].gamma = 
dc_plane->gamma_correction;
bundle->surface_updates[planes_count].in_transfer_func 
= dc_plane->in_transfer_func;
+   
bundle->surface_updates[planes_count].gamut_remap_matrix = 
&dc_plane->gamut_remap_matrix;
}
 
fill_dc_scaling_info(new_plane_state,
@@ -8173,6 +8174,8 @@ dm_determine_update_type_for_commit(struct 
amdgpu_display_manager *dm,

new_dm_plane_state->dc_state->gamma_correction;

bundle->surface_updates[num_plane].in_transfer_func =

new_dm_plane_state->dc_state->in_transfer_func;
+   
bundle->surface_updates[num_plane].gamut_remap_matrix =
+   
&new_dm_plane_state->dc_state->gamut_remap_matrix;
bundle->stream_update.gamut_remap =

&new_dm_crtc_state->stream->gamut_remap_matrix;
bundle->stream_update.output_csc_transform =
-- 
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[PATCH 13/35] drm/amd/display: Cast int to float before division

[Rodrigo Siqueira]

From: Sung Lee 

[Why]:
Some inputs to dml_ceil have it dividied by int which causes a
truncation. This loss of precision means the ceil function becomes
redundant and does not round up.

[How]:
Cast parameter to float before division.

Signed-off-by: Sung Lee 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c| 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index e6617c958bb8..5bc80b6084da 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -5944,7 +5944,7 @@ static void CalculateMetaAndPTETimes(
* PixelPTEReqHeightY[k];
}
dpte_groups_per_row_luma_ub = dml_ceil(
-   dpte_row_width_luma_ub[k] / 
dpte_group_width_luma,
+   (float) dpte_row_width_luma_ub[k] / 
dpte_group_width_luma,
1);
time_per_pte_group_nom_luma[k] = 
DST_Y_PER_PTE_ROW_NOM_L[k] * HTotal[k]
/ PixelClock[k] / 
dpte_groups_per_row_luma_ub;
@@ -5968,7 +5968,7 @@ static void CalculateMetaAndPTETimes(
* PixelPTEReqHeightC[k];
}
dpte_groups_per_row_chroma_ub = dml_ceil(
-   dpte_row_width_chroma_ub[k]
+   (float) 
dpte_row_width_chroma_ub[k]
/ 
dpte_group_width_chroma,
1);
time_per_pte_group_nom_chroma[k] = 
DST_Y_PER_PTE_ROW_NOM_C[k]
-- 
2.26.0

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[PATCH 08/35] drm/amd/display: Unify psr feature flags

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
As it stands, psr has feature flags in dm, stream, and link. Most are
not defined well enough, and different dm layers have different uses for
these same flags.

[How]
We define a new structure called psr_settings in dc_link that will hold
the following psr feature flags:

psr_feature_enable - psr is supported
psr_allow_active - psr is currently active
psr_version - internal psr version supported
psr_frame_capture_indication_req
psr_sdp_transmit_line_num_deadline
The last two flags were moved out of the power module
for the purposes of consolidating psr flags.
Their use is already well-defined.

Psr caps reported by sink will also be stored in dc_link,
in dpcd_caps.psr_caps.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 +++
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  2 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  2 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 drivers/gpu/drm/amd/display/dc/dc_dp_types.h  |  6 
 drivers/gpu/drm/amd/display/dc/dc_link.h  | 21 +--
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  2 --
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 13 ---
 .../display/dc/dce110/dce110_hw_sequencer.c   |  4 +--
 .../drm/amd/display/dmub/inc/dmub_cmd_dal.h   |  1 +
 .../display/modules/info_packet/info_packet.c |  3 +-
 13 files changed, 72 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 47d12c38bc71..671741713b04 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4412,14 +4412,10 @@ create_stream_for_sink(struct amdgpu_dm_connector 
*aconnector,
 
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket, 
false, false);
-   if (stream->link->psr_feature_enabled)  {
+   if (stream->link->psr_settings.psr_feature_enabled) {
struct dc  *core_dc = stream->link->ctx->dc;
 
if (dc_is_dmcu_initialized(core_dc)) {
-   struct dmcu *dmcu = core_dc->res_pool->dmcu;
-
-   stream->psr_version = dmcu->dmcu_version.psr_version;
-
//
// should decide stream support vsc sdp colorimetry 
capability
// before building vsc info packet
@@ -6919,7 +6915,7 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
}
mutex_lock(&dm->dc_lock);
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
-   acrtc_state->stream->link->psr_allow_active)
+   
acrtc_state->stream->link->psr_settings.psr_allow_active)
amdgpu_dm_psr_disable(acrtc_state->stream);
 
dc_commit_updates_for_stream(dm->dc,
@@ -6930,12 +6926,12 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
 dc_state);
 
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
-   
acrtc_state->stream->psr_version &&
-   
!acrtc_state->stream->link->psr_feature_enabled)
+   
acrtc_state->stream->link->psr_settings.psr_version != PSR_VERSION_UNSUPPORTED 
&&
+   
!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
amdgpu_dm_link_setup_psr(acrtc_state->stream);
else if ((acrtc_state->update_type == UPDATE_TYPE_FAST) &&
-   
acrtc_state->stream->link->psr_feature_enabled &&
-   
!acrtc_state->stream->link->psr_allow_active) {
+   
acrtc_state->stream->link->psr_settings.psr_feature_enabled &&
+   
!acrtc_state->stream->link->psr_settings.psr_allow_active) {
amdgpu_dm_psr_enable(acrtc_state->stream);
}
 
@@ -7249,7 +7245,7 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id 
%d:[%p]\n", acrtc->crtc_id, acrtc);
/* i.e. reset mode */
if (dm_old_crtc_state->stream) {
-   if 
(dm_old_crtc_state->stream->link->psr_allow_active)
+   if 
(dm_old_crtc_state->stream->link->psr_settings.psr_allow_active)

amdgpu_dm_psr_disable(dm_old_crtc_state

[PATCH 15/35] drm/amd/display: Avoid NULL pointer in set_backlight when ABM is NULL

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
On ASIC without ABM support (most dGPU) we run into a null pointer
dereference when attempting to set the backlight level.

[How]
This function requires ABM, so fix up the condition to only allow
DMCU to be optional.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Wyatt Wood 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1c5c11d6347e..a926c1c3f57d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2462,8 +2462,7 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
int i;
DC_LOGGER_INIT(link->ctx->logger);
 
-   if ((dmcu == NULL && abm == NULL) ||
-   (abm->funcs->set_backlight_level_pwm == NULL))
+   if (abm == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
return false;
 
if (dmcu)
-- 
2.26.0

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[PATCH 18/35] drm/amd/display: Fix HDR visual confirm

[Rodrigo Siqueira]

From: Aric Cyr 

Some cases were incorrectly reporting the wrong visual confirm, even
though they were working as expected.

Signed-off-by: Aric Cyr 
Reviewed-by: Krunoslav Kovac 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 20 +--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f41efddc9bc..80e9ac14e38f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2130,25 +2130,25 @@ void dcn10_get_surface_visual_confirm_color(
 
switch (pipe_ctx->plane_res.scl_data.format) {
case PIXEL_FORMAT_ARGB:
-   /* set boarder color to red */
+   /* set border color to red */
color->color_r_cr = color_value;
break;
 
case PIXEL_FORMAT_ARGB2101010:
-   /* set boarder color to blue */
+   /* set border color to blue */
color->color_b_cb = color_value;
break;
case PIXEL_FORMAT_420BPP8:
-   /* set boarder color to green */
+   /* set border color to green */
color->color_g_y = color_value;
break;
case PIXEL_FORMAT_420BPP10:
-   /* set boarder color to yellow */
+   /* set border color to yellow */
color->color_g_y = color_value;
color->color_r_cr = color_value;
break;
case PIXEL_FORMAT_FP16:
-   /* set boarder color to white */
+   /* set border color to white */
color->color_r_cr = color_value;
color->color_b_cb = color_value;
color->color_g_y = color_value;
@@ -2173,25 +2173,25 @@ void dcn10_get_hdr_visual_confirm_color(
switch (top_pipe_ctx->plane_res.scl_data.format) {
case PIXEL_FORMAT_ARGB2101010:
if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_PQ) {
-   /* HDR10, ARGB2101010 - set boarder color to red */
+   /* HDR10, ARGB2101010 - set border color to red */
color->color_r_cr = color_value;
} else if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_GAMMA22) {
-   /* FreeSync 2 ARGB2101010 - set boarder color to pink */
+   /* FreeSync 2 ARGB2101010 - set border color to pink */
color->color_r_cr = color_value;
color->color_b_cb = color_value;
}
break;
case PIXEL_FORMAT_FP16:
if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_PQ) {
-   /* HDR10, FP16 - set boarder color to blue */
+   /* HDR10, FP16 - set border color to blue */
color->color_b_cb = color_value;
} else if (top_pipe_ctx->stream->out_transfer_func->tf == 
TRANSFER_FUNCTION_GAMMA22) {
-   /* FreeSync 2 HDR - set boarder color to green */
+   /* FreeSync 2 HDR - set border color to green */
color->color_g_y = color_value;
}
break;
default:
-   /* SDR - set boarder color to Gray */
+   /* SDR - set border color to Gray */
color->color_r_cr = color_value/2;
color->color_b_cb = color_value/2;
color->color_g_y = color_value/2;
-- 
2.26.0

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[PATCH 10/35] drm/amd/display: Workaround to disable YCbCr

[Rodrigo Siqueira]

From: Jinze Xu 

[Why]
Some mst dock can't translate DP to HDMI properly.

[How]
Bypass YCbCr timings on specific MST device.

Signed-off-by: Jinze Xu 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 1 +
 drivers/gpu/drm/amd/display/dc/dc.h   | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
index a249a0e5edd0..9e16af22e4aa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c
@@ -54,6 +54,7 @@ static bool dc_sink_construct(struct dc_sink *sink, const 
struct dc_sink_init_da
sink->ctx = link->ctx;
sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk;
sink->converter_disable_audio = init_params->converter_disable_audio;
+   sink->is_mst_legacy = init_params->sink_is_legacy;
sink->dc_container_id = NULL;
sink->sink_id = init_params->link->ctx->dc_sink_id_count;
// increment dc_sink_id_count because we don't want two sinks with same 
ID
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 1b30804f56db..89cce79c950d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1079,7 +1079,7 @@ struct dc_sink {
void *priv;
struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
bool converter_disable_audio;
-
+   bool is_mst_legacy;
struct dc_sink_dsc_caps dsc_caps;
struct dc_sink_fec_caps fec_caps;
 
@@ -1106,6 +1106,7 @@ struct dc_sink_init_data {
struct dc_link *link;
uint32_t dongle_max_pix_clk;
bool converter_disable_audio;
+   bool sink_is_legacy;
 };
 
 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
-- 
2.26.0

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[PATCH 34/35] drm/amd/display: Adjust refactored dm for color management only

[Rodrigo Siqueira]

From: Stylon Wang 

[Why]
Commit 4ca3f1217e6106779aea9ebabdd09f695d42f2ff is causing regression
from changing the order of call sequence.

[How]
Keep the call sequence and take in extra dm state only if plane-level
color management is enabled.

Signed-off-by: Stylon Wang 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Rodrigo Siqueira 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |  3 +--
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 671741713b04..209b9bf8bf11 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3778,12 +3778,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
 }
 
 static int fill_dc_plane_attributes(struct amdgpu_device *adev,
-   struct dm_plane_state *dm_plane_state,
+   struct dc_plane_state *dc_plane_state,
struct drm_plane_state *plane_state,
struct drm_crtc_state *crtc_state)
 {
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
-   struct dc_plane_state *dc_plane_state = dm_plane_state->dc_state;
const struct amdgpu_framebuffer *amdgpu_fb =
to_amdgpu_framebuffer(plane_state->fb);
struct dc_scaling_info scaling_info;
@@ -3831,7 +3830,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device 
*adev,
 * Always set input transfer function, since plane state is refreshed
 * every time.
 */
-   ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dm_plane_state);
+   ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
if (ret)
return ret;
 
@@ -8037,6 +8036,16 @@ static int dm_update_plane_state(struct dc *dc,
DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n",
plane->base.id, new_plane_crtc->base.id);
 
+   ret = fill_dc_plane_attributes(
+   new_plane_crtc->dev->dev_private,
+   dc_new_plane_state,
+   new_plane_state,
+   new_crtc_state);
+   if (ret) {
+   dc_plane_state_release(dc_new_plane_state);
+   return ret;
+   }
+
ret = dm_atomic_get_state(state, &dm_state);
if (ret) {
dc_plane_state_release(dc_new_plane_state);
@@ -8062,14 +8071,6 @@ static int dm_update_plane_state(struct dc *dc,
 
dm_new_plane_state->dc_state = dc_new_plane_state;
 
-   ret = fill_dc_plane_attributes(
-   new_plane_crtc->dev->dev_private,
-   dm_new_plane_state,
-   new_plane_state,
-   new_crtc_state);
-   if (ret)
-   return ret;
-
/* Tell DC to do a full surface update every time there
 * is a plane change. Inefficient, but works for now.
 */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index f30dc004bf2b..3f0c6298b588 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -482,7 +482,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector 
*connector,
 void amdgpu_dm_init_color_mod(void);
 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
- struct dm_plane_state *plane);
+ struct dc_plane_state *dc_plane_state);
 
 void amdgpu_dm_update_connector_after_detect(
struct amdgpu_dm_connector *aconnector);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index d0554082f0dc..838f35668f12 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -416,10 +416,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state 
*crtc)
  * Returns 0 on success.
  */
 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
- struct dm_plane_state *plane)
+ struct dc_plane_state *dc_plane_state)
 {
const struct drm_color_lut *degamma_lut;
-   struct dc_plane_state *dc_plane_state = plane->dc_state;
enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
uint32_t degamma_size;
int r;

[PATCH 17/35] drm/amd/display: Use the correct input TF for video formats

[Rodrigo Siqueira]

From: Nicholas Kazlauskas 

[Why]
Color blending for NV12 formats is incorrect because we're using the
predefined SRGB degamma.

[How]
Calculate the correct input transfer function for degamma from the color
module depending on what the actual surface format is.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Zhan Liu 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 22 ---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 6b58761e4b04..d0554082f0dc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -420,9 +420,21 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state 
*crtc,
 {
const struct drm_color_lut *degamma_lut;
struct dc_plane_state *dc_plane_state = plane->dc_state;
+   enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB;
uint32_t degamma_size;
int r;
 
+   /* Get the correct base transfer function for implicit degamma. */
+   switch (dc_plane_state->format) {
+   case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
+   case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
+   /* DC doesn't have a transfer function for BT601 specifically. 
*/
+   tf = TRANSFER_FUNCTION_BT709;
+   break;
+   default:
+   break;
+   }
+
if (crtc->cm_has_degamma) {
degamma_lut = __extract_blob_lut(crtc->base.degamma_lut,
 °amma_size);
@@ -456,8 +468,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state 
*crtc,
 * map these to the atomic one instead.
 */
if (crtc->cm_is_degamma_srgb)
-   dc_plane_state->in_transfer_func->tf =
-   TRANSFER_FUNCTION_SRGB;
+   dc_plane_state->in_transfer_func->tf = tf;
else
dc_plane_state->in_transfer_func->tf =
TRANSFER_FUNCTION_LINEAR;
@@ -472,7 +483,12 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state 
*crtc,
 * in linear space. Assume that the input is sRGB.
 */
dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED;
-   dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
+   dc_plane_state->in_transfer_func->tf = tf;
+
+   if (tf != TRANSFER_FUNCTION_SRGB &&
+   !mod_color_calculate_degamma_params(
+   dc_plane_state->in_transfer_func, NULL, false))
+   return -ENOMEM;
} else {
/* ...Otherwise we can just bypass the DGM block. */
dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
-- 
2.26.0

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[PATCH 05/35] drm/amd/display: Remove byte swapping for dmcub abm config table

[Rodrigo Siqueira]

From: Wyatt Wood 

[Why]
Since x86 and dmcub are both little endian, byte swapping isn't
necessary. Dmcu requires byte swapping as it is big endian.

[How]
Add flag to function definitions to determine if byte swapping is
necessary.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/modules/power/power_helpers.c | 74 +--
 1 file changed, 36 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index dd1517684c90..edb446455f6b 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -240,7 +240,7 @@ static void fill_backlight_transform_table(struct 
dmcu_iram_parameters params,
 }
 
 static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters 
params,
-   struct iram_table_v_2_2 *table)
+   struct iram_table_v_2_2 *table, bool big_endian)
 {
unsigned int i;
unsigned int num_entries = NUM_BL_CURVE_SEGS;
@@ -264,10 +264,10 @@ static void fill_backlight_transform_table_v_2_2(struct 
dmcu_iram_parameters par
lut_index = (params.backlight_lut_array_size - 1) * i / 
(num_entries - 1);
ASSERT(lut_index < params.backlight_lut_array_size);
 
-   table->backlight_thresholds[i] =
-   cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries));
-   table->backlight_offsets[i] =
-   cpu_to_be16(params.backlight_lut_array[lut_index]);
+   table->backlight_thresholds[i] = (big_endian) ?
+   cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries)) : 
DIV_ROUNDUP((i * 65536), num_entries);
+   table->backlight_offsets[i] = (big_endian) ?
+   cpu_to_be16(params.backlight_lut_array[lut_index]) : 
params.backlight_lut_array[lut_index];
}
 }
 
@@ -587,18 +587,16 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
 
fill_backlight_transform_table_v_2_2(
-   params, ram_table);
+   params, ram_table, true);
 }
 
-void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct 
dmcu_iram_parameters params)
+void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct 
dmcu_iram_parameters params, bool big_endian)
 {
unsigned int i, j;
unsigned int set = params.set;
 
ram_table->flags = 0x0;
-
-   ram_table->min_abm_backlight =
-   cpu_to_be16(params.min_abm_backlight);
+   ram_table->min_abm_backlight = (big_endian) ? 
cpu_to_be16(params.min_abm_backlight) : params.min_abm_backlight;
 
for (i = 0; i < NUM_AGGR_LEVEL; i++) {
ram_table->hybrid_factor[i] = 
abm_settings[set][i].brightness_gain;
@@ -622,33 +620,33 @@ void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
ram_table->iir_curve[4] = 0x65;
 
//Gamma 2.2
-   ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
-   ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
-   ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
-   ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
-   ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
-   ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
-   ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
-   ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
-   ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
-   ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
-   ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
-   ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
-   ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
-   ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
-   ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
-   ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
-   ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
-   ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
-   ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
-   ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
-   ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
-   ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
-   ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
-   ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);
+   ram_table->crgb_thresh[0] = (big_endian) ? cpu_to_be16(0x127c) : 0x127c;
+   ram_table->crgb_thresh[1] = (big_endian) ? cpu_to_be16(0x151b) : 0x151b;
+   ram_table->crgb_thresh[2] = (big_endian) ? cpu_to_be16(0x17d5) : 0x17d5;
+   ram_table->crgb_thresh[3] = (big_endian) ? cpu_to_be16(0x1a56) : 0x1a56;
+   ram_table->crgb_thresh[4] = (big_endian) ? cpu_to_be16(0x1c83) : 0x1c83;
+   ram_table->crgb_thresh[5] = (big_endian) ? cpu_to_be16(0x1

[PATCH 24/35] drm/amd/display: move panel power seq to new panel struct

[Rodrigo Siqueira]

From: Anthony Koo 

[Why]
panel power sequencer is currently just sitting in hwseq but it really
it tied to internal panels

[How]
make a new panel struct to contain power sequencer code

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  22 
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dce/Makefile   |   2 +-
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|  65 +++---
 .../gpu/drm/amd/display/dc/dce/dce_panel.c| 105 
 .../gpu/drm/amd/display/dc/dce/dce_panel.h| 117 ++
 .../amd/display/dc/dce100/dce100_resource.c   |  31 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  37 +-
 .../display/dc/dce110/dce110_hw_sequencer.h   |   4 -
 .../amd/display/dc/dce110/dce110_resource.c   |  31 +
 .../amd/display/dc/dce112/dce112_resource.c   |  31 +
 .../amd/display/dc/dce120/dce120_resource.c   |  31 +
 .../drm/amd/display/dc/dce80/dce80_resource.c |  31 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_init.c |   2 -
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  31 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   2 -
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  31 +
 .../gpu/drm/amd/display/dc/dcn21/dcn21_init.c |   2 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  32 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   3 +
 drivers/gpu/drm/amd/display/dc/inc/hw/panel.h |  53 
 .../amd/display/dc/inc/hw_sequencer_private.h |   2 -
 22 files changed, 572 insertions(+), 94 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_panel.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dce/dce_panel.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/panel.h

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index a784fd2078a8..2e5a97190ce3 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -47,6 +47,7 @@
 #include "hw/clk_mgr.h"
 #include "dce/dmub_psr.h"
 #include "dmub/inc/dmub_cmd_dal.h"
+#include "inc/hw/panel.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -1355,6 +1356,7 @@ static bool dc_link_construct(struct dc_link *link,
struct ddc_service_init_data ddc_service_init_data = { { 0 } };
struct dc_context *dc_ctx = init_params->ctx;
struct encoder_init_data enc_init_data = { 0 };
+   struct panel_init_data panel_init_data = { 0 };
struct integrated_info info = {{{ 0 }}};
struct dc_bios *bios = init_params->dc->ctx->dc_bios;
const struct dc_vbios_funcs *bp_funcs = bios->funcs;
@@ -1425,6 +1427,7 @@ static bool dc_link_construct(struct dc_link *link,
link->irq_source_hpd_rx =
dal_irq_get_rx_source(link->hpd_gpio);
}
+
break;
case CONNECTOR_ID_LVDS:
link->connector_signal = SIGNAL_TYPE_LVDS;
@@ -1454,6 +1457,22 @@ static bool dc_link_construct(struct dc_link *link,
link->ddc_hw_inst =
dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
 
+
+   if (link->dc->res_pool->funcs->panel_create &&
+   (link->link_id.id == CONNECTOR_ID_EDP ||
+   link->link_id.id == CONNECTOR_ID_LVDS)) {
+   panel_init_data.ctx = dc_ctx;
+   panel_init_data.inst = 0;
+   link->panel =
+   link->dc->res_pool->funcs->panel_create(
+   
&panel_init_data);
+
+   if (link->panel == NULL) {
+   DC_ERROR("Failed to create link panel!\n");
+   goto panel_create_fail;
+   }
+   }
+
enc_init_data.ctx = dc_ctx;
bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
  &enc_init_data.encoder);
@@ -1536,6 +1555,9 @@ static bool dc_link_construct(struct dc_link *link,
 device_tag_fail:
link->link_enc->funcs->destroy(&link->link_enc);
 link_enc_create_fail:
+   if (link->panel != NULL)
+   link->panel->funcs->destroy(&link->panel);
+panel_create_fail:
dal_ddc_service_destroy(&link->ddc);
 ddc_create_fail:
 create_fail:
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h 
b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 72b22dd50f0d..31c9706f1b0b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -135,6 +135,7 @@ struct dc_link {
 
struct dc_context *ctx;
 
+   struct panel *panel;
struct link_encoder *link_enc;
struct graphics_object_id link_id;
union ddi_channel_mapping ddi_channel_mapping;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/Makefile 
b/drivers/gpu/drm/amd/display/dc/dce/Makefile
index b31a1b71dab0..1

[PATCH 33/35] drm/amd/display: access ABM from stream resource.

[Rodrigo Siqueira]

From: Yongqiang Sun 

[Why]
Since ABM resource is mapped to stream res, all the ABM access should
via stream res.

[How]
Get ABM instance from stream res instead of resource pool.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Rodrigo Siqueira 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 39 +++
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0d8fae4e9441..9c4686edcf3e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2465,9 +2465,28 @@ enum dc_status dc_link_validate_mode_timing(
return DC_OK;
 }
 
+static struct abm *get_abm_from_stream_res(const struct dc_link *link)
+{
+   int i;
+   struct dc *dc = link->ctx->dc;
+   struct abm *abm = NULL;
+
+   for (i = 0; i < MAX_PIPES; i++) {
+   struct pipe_ctx pipe_ctx = 
dc->current_state->res_ctx.pipe_ctx[i];
+   struct dc_stream_state *stream = pipe_ctx.stream;
+
+   if (stream && stream->link == link) {
+   abm = pipe_ctx.stream_res.abm;
+   break;
+   }
+   }
+   return abm;
+}
+
 int dc_link_get_backlight_level(const struct dc_link *link)
 {
-   struct abm *abm = link->ctx->dc->res_pool->abm;
+
+   struct abm *abm = get_abm_from_stream_res(link);
 
if (abm == NULL || abm->funcs->get_current_backlight == NULL)
return DC_ERROR_UNEXPECTED;
@@ -2477,7 +2496,7 @@ int dc_link_get_backlight_level(const struct dc_link 
*link)
 
 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
 {
-   struct abm *abm = link->ctx->dc->res_pool->abm;
+   struct abm *abm = get_abm_from_stream_res(link);
 
if (abm == NULL || abm->funcs->get_target_backlight == NULL)
return DC_ERROR_UNEXPECTED;
@@ -2490,7 +2509,7 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
uint32_t frame_ramp)
 {
struct dc  *dc = link->ctx->dc;
-   struct abm *abm = dc->res_pool->abm;
+   struct abm *abm = get_abm_from_stream_res(link);
struct dmcu *dmcu = dc->res_pool->dmcu;
unsigned int controller_id = 0;
bool fw_set_brightness = true;
@@ -2541,20 +2560,8 @@ bool dc_link_set_backlight_level(const struct dc_link 
*link,
 
 bool dc_link_set_abm_disable(const struct dc_link *link)
 {
-   struct dc  *dc = link->ctx->dc;
-   struct abm *abm = NULL;
+   struct abm *abm = get_abm_from_stream_res(link);
bool success = false;
-   int i;
-
-   for (i = 0; i < MAX_PIPES; i++) {
-   struct pipe_ctx pipe_ctx = 
dc->current_state->res_ctx.pipe_ctx[i];
-   struct dc_stream_state *stream = pipe_ctx.stream;
-
-   if (stream && stream->link == link) {
-   abm = pipe_ctx.stream_res.abm;
-   break;
-   }
-   }
 
if (abm)
success = abm->funcs->set_abm_immediate_disable(abm);
-- 
2.26.0

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Re: [PATCH] drm/amd/powerplay: fix resume failed as smu table initialize early exit

[Huang Rui]

On Wed, Apr 15, 2020 at 11:43:24PM +0800, Liang, Prike wrote:
> When the amdgpu in the suspend/resume loop need notify the dpm disabled,
> otherwise the smu table will be uninitialize and result in resume failed.
> 
> Signed-off-by: Prike Liang 
> Tested-by: Mengbing Wang 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 95eb445..7ddaea8 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -895,12 +895,17 @@ static int renoir_read_sensor(struct smu_context *smu,
>  
>  static bool renoir_is_dpm_running(struct smu_context *smu)
>  {
> + struct amdgpu_device *adev = smu->adev;
> +
>   /*
>* Until now, the pmfw hasn't exported the interface of SMU
>* feature mask to APU SKU so just force on all the feature
>* at early initial stage.
>*/
> - return true;
> + if (adev->in_suspend)
> + return false;
> + else
> + return true;
>  
>  }
>  
> -- 
> 2.7.4
> 
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Re: [PATCH 05/35] drm/amd/display: Remove byte swapping for dmcub abm config table

[Deucher, Alexander]

[AMD Public Use]

I would drop this patch unless it only applies to APUs.  On Linux, people may 
run the driver on big endian systems.

Alex

From: amd-gfx  on behalf of Rodrigo 
Siqueira 
Sent: Thursday, April 16, 2020 7:40 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Li, Sun peng (Leo) ; Wentland, Harry 
; Siqueira, Rodrigo ; Wood, 
Wyatt ; Lakha, Bhawanpreet ; 
Koo, Anthony 
Subject: [PATCH 05/35] drm/amd/display: Remove byte swapping for dmcub abm 
config table

From: Wyatt Wood 

[Why]
Since x86 and dmcub are both little endian, byte swapping isn't
necessary. Dmcu requires byte swapping as it is big endian.

[How]
Add flag to function definitions to determine if byte swapping is
necessary.

Signed-off-by: Wyatt Wood 
Reviewed-by: Anthony Koo 
Acked-by: Rodrigo Siqueira 
---
 .../amd/display/modules/power/power_helpers.c | 74 +--
 1 file changed, 36 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c 
b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index dd1517684c90..edb446455f6b 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -240,7 +240,7 @@ static void fill_backlight_transform_table(struct 
dmcu_iram_parameters params,
 }

 static void fill_backlight_transform_table_v_2_2(struct dmcu_iram_parameters 
params,
-   struct iram_table_v_2_2 *table)
+   struct iram_table_v_2_2 *table, bool big_endian)
 {
 unsigned int i;
 unsigned int num_entries = NUM_BL_CURVE_SEGS;
@@ -264,10 +264,10 @@ static void fill_backlight_transform_table_v_2_2(struct 
dmcu_iram_parameters par
 lut_index = (params.backlight_lut_array_size - 1) * i / 
(num_entries - 1);
 ASSERT(lut_index < params.backlight_lut_array_size);

-   table->backlight_thresholds[i] =
-   cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries));
-   table->backlight_offsets[i] =
-   cpu_to_be16(params.backlight_lut_array[lut_index]);
+   table->backlight_thresholds[i] = (big_endian) ?
+   cpu_to_be16(DIV_ROUNDUP((i * 65536), num_entries)) : 
DIV_ROUNDUP((i * 65536), num_entries);
+   table->backlight_offsets[i] = (big_endian) ?
+   cpu_to_be16(params.backlight_lut_array[lut_index]) : 
params.backlight_lut_array[lut_index];
 }
 }

@@ -587,18 +587,16 @@ void fill_iram_v_2_2(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
 ram_table->crgb_slope[7]  = cpu_to_be16(0x1910);

 fill_backlight_transform_table_v_2_2(
-   params, ram_table);
+   params, ram_table, true);
 }

-void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct 
dmcu_iram_parameters params)
+void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct 
dmcu_iram_parameters params, bool big_endian)
 {
 unsigned int i, j;
 unsigned int set = params.set;

 ram_table->flags = 0x0;
-
-   ram_table->min_abm_backlight =
-   cpu_to_be16(params.min_abm_backlight);
+   ram_table->min_abm_backlight = (big_endian) ? 
cpu_to_be16(params.min_abm_backlight) : params.min_abm_backlight;

 for (i = 0; i < NUM_AGGR_LEVEL; i++) {
 ram_table->hybrid_factor[i] = 
abm_settings[set][i].brightness_gain;
@@ -622,33 +620,33 @@ void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, 
struct dmcu_iram_parame
 ram_table->iir_curve[4] = 0x65;

 //Gamma 2.2
-   ram_table->crgb_thresh[0] = cpu_to_be16(0x127c);
-   ram_table->crgb_thresh[1] = cpu_to_be16(0x151b);
-   ram_table->crgb_thresh[2] = cpu_to_be16(0x17d5);
-   ram_table->crgb_thresh[3] = cpu_to_be16(0x1a56);
-   ram_table->crgb_thresh[4] = cpu_to_be16(0x1c83);
-   ram_table->crgb_thresh[5] = cpu_to_be16(0x1e72);
-   ram_table->crgb_thresh[6] = cpu_to_be16(0x20f0);
-   ram_table->crgb_thresh[7] = cpu_to_be16(0x232b);
-   ram_table->crgb_offset[0] = cpu_to_be16(0x2999);
-   ram_table->crgb_offset[1] = cpu_to_be16(0x3999);
-   ram_table->crgb_offset[2] = cpu_to_be16(0x4666);
-   ram_table->crgb_offset[3] = cpu_to_be16(0x5999);
-   ram_table->crgb_offset[4] = cpu_to_be16(0x6333);
-   ram_table->crgb_offset[5] = cpu_to_be16(0x7800);
-   ram_table->crgb_offset[6] = cpu_to_be16(0x8c00);
-   ram_table->crgb_offset[7] = cpu_to_be16(0xa000);
-   ram_table->crgb_slope[0]  = cpu_to_be16(0x3609);
-   ram_table->crgb_slope[1]  = cpu_to_be16(0x2dfa);
-   ram_table->crgb_slope[2]  = cpu_to_be16(0x27ea);
-   ram_table->crgb_slope[3]  = cpu_to_be16(0x235d);
-   ram_table->crgb_slope[4]  = cpu_to_be16(0x2042);
-   ram_table->crgb_slope[5]  = cpu_to_be16(0x1dc3);
-   ram_table->crgb_slope[6]  = cpu_to_be16(0x1b1a);
-   ram_table->crg

Re: [PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Huang Rui]

On Wed, Apr 15, 2020 at 07:20:31PM +0800, Yuxian Dai wrote:
> we should avoid to show the invalid level value when the
> DPM_LEVELS supported number changed
> 
> Signed-off-by: Yuxian Dai 
> Change-Id: Ib66d0cf34a866fa6f0cedd1d5fc642f59236787d

Please add comment in the commit message to explain some asic only have 2
level, and cause the invalid level as 0.

With that fixed, patch is

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 281b7b6cf1a4..e4e7a352d032 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context 
> *smu,
>  
>   for (i = 0; i < count; i++) {
>   GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> + if (!value)
> + continue;
>   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
>   cur_value == value ? "*" : "");
>   if (cur_value == value)
> -- 
> 2.17.1
> 
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[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Yuxian Dai]

for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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RE: [PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Dai, Yuxian (David)]

[AMD Official Use Only - Internal Distribution Only]

On Wed, Apr 15, 2020 at 07:20:31PM +0800, Yuxian Dai wrote:
> we should avoid to show the invalid level value when the DPM_LEVELS 
> supported number changed
> 
> Signed-off-by: Yuxian Dai 
> Change-Id: Ib66d0cf34a866fa6f0cedd1d5fc642f59236787d

Please add comment in the commit message to explain some asic only have 2 
level, and cause the invalid level as 0.

With that fixed, patch is
>ok

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 281b7b6cf1a4..e4e7a352d032 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct 
> smu_context *smu,
>  
>   for (i = 0; i < count; i++) {
>   GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> + if (!value)
> + continue;
>   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
>   cur_value == value ? "*" : "");
>   if (cur_value == value)
> --
> 2.17.1
> 
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RE: [PATCH] drm/amdgpu: Disable FRU read on Arcturus

[Quan, Evan]

Acked-by: Evan Quan 

-Original Message-
From: amd-gfx  On Behalf Of Kent Russell
Sent: Thursday, April 16, 2020 8:26 PM
To: amd-gfx@lists.freedesktop.org
Cc: Russell, Kent 
Subject: [PATCH] drm/amdgpu: Disable FRU read on Arcturus

Update the list with supported Arcturus chips, but disable for now until final 
list is confirmed.

Ideally we can poll atombios for FRU support, instead of maintaining this list 
of chips, but this will enable serial number reading for supported ASICs for 
the time-being.

Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index c7e55fe170bd..815c072ac4da 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -36,10 +36,11 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)
/* TODO: Gaming SKUs don't have the FRU EEPROM.
 * Use this hack to address hangs on modprobe on gaming SKUs
 * until a proper solution can be implemented by only supporting
-* it on Arcturus, and the explicit chip IDs for VG20 Server cards
+* the explicit chip IDs for VG20 Server cards
+*
+* TODO: Add list of supported Arcturus DIDs once confirmed
 */
-   if ((adev->asic_type == CHIP_ARCTURUS) ||
-   (adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) ||
+   if ((adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a0) 
+||
(adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a1) ||
(adev->asic_type == CHIP_VEGA20 && adev->pdev->device == 0x66a4))
return true;
--
2.17.1

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Re: [PATCH v5] drm/amdkfd: Provide SMI events watch

[Felix Kuehling]

There are still some concurrency issues. See comments inline.

Regards,
  Felix

Am 2020-04-15 um 10:01 p.m. schrieb Amber Lin:
> When the compute is malfunctioning or performance drops, the system admin
> will use SMI (System Management Interface) tool to monitor/diagnostic what
> went wrong. This patch provides an event watch interface for the user
> space to register devices and subscribe events they are interested. After
> registered, the user can use annoymous file descriptor's poll function
> with wait-time specified and wait for events to happen. Once an event
> happens, the user can use read() to retrieve information related to the
> event.
>
> VM fault event is done in this patch.
>
> v2: - remove UNREGISTER and add event ENABLE/DISABLE
> - correct kfifo usage
> - move event message API to kfd_ioctl.h
> v3: send the event msg in text than in binary
> v4: support multiple clients
> v5: move events enablement from ioctl to fd write
>
> Signed-off-by: Amber Lin 
> ---
>  drivers/gpu/drm/amd/amdkfd/Makefile  |   1 +
>  drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c |   2 +
>  drivers/gpu/drm/amd/amdkfd/kfd_chardev.c |  18 +++
>  drivers/gpu/drm/amd/amdkfd/kfd_device.c  |   7 +
>  drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c  |   2 +
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h|   4 +
>  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c  | 191 
> +++
>  drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h  |  29 
>  include/uapi/linux/kfd_ioctl.h   |  16 +-
>  9 files changed, 269 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c
>  create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_smi_events.h
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile 
> b/drivers/gpu/drm/amd/amdkfd/Makefile
> index 6147462..e1e4115 100644
> --- a/drivers/gpu/drm/amd/amdkfd/Makefile
> +++ b/drivers/gpu/drm/amd/amdkfd/Makefile
> @@ -53,6 +53,7 @@ AMDKFD_FILES:= $(AMDKFD_PATH)/kfd_module.o \
>   $(AMDKFD_PATH)/kfd_int_process_v9.o \
>   $(AMDKFD_PATH)/kfd_dbgdev.o \
>   $(AMDKFD_PATH)/kfd_dbgmgr.o \
> + $(AMDKFD_PATH)/kfd_smi_events.o \
>   $(AMDKFD_PATH)/kfd_crat.o
>  
>  ifneq ($(CONFIG_AMD_IOMMU_V2),)
> diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c 
> b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> index 9f59ba9..24b4717 100644
> --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
> @@ -24,6 +24,7 @@
>  #include "kfd_events.h"
>  #include "cik_int.h"
>  #include "amdgpu_amdkfd.h"
> +#include "kfd_smi_events.h"
>  
>  static bool cik_event_interrupt_isr(struct kfd_dev *dev,
>   const uint32_t *ih_ring_entry,
> @@ -107,6 +108,7 @@ static void cik_event_interrupt_wq(struct kfd_dev *dev,
>   ihre->source_id == CIK_INTSRC_GFX_MEM_PROT_FAULT) {
>   struct kfd_vm_fault_info info;
>  
> + kfd_smi_event_update_vmfault(dev, pasid);
>   kfd_process_vm_fault(dev->dqm, pasid);
>  
>   memset(&info, 0, sizeof(info));
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> index f8fa03a..2baaaec 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
> @@ -39,6 +39,7 @@
>  #include "kfd_device_queue_manager.h"
>  #include "kfd_dbgmgr.h"
>  #include "amdgpu_amdkfd.h"
> +#include "kfd_smi_events.h"
>  
>  static long kfd_ioctl(struct file *, unsigned int, unsigned long);
>  static int kfd_open(struct inode *, struct file *);
> @@ -1732,6 +1733,20 @@ static int kfd_ioctl_import_dmabuf(struct file *filep,
>   return r;
>  }
>  
> +/* Handle requests for watching SMI events */
> +static int kfd_ioctl_smi_events(struct file *filep,
> + struct kfd_process *p, void *data)
> +{
> + struct kfd_ioctl_smi_events_args *args = data;
> + struct kfd_dev *dev;
> +
> + dev = kfd_device_by_id(args->gpuid);
> + if (!dev)
> + return -EINVAL;
> +
> + return kfd_smi_event_open(dev, &args->anon_fd);
> +}
> +
>  #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
>   [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
>   .cmd_drv = 0, .name = #ioctl}
> @@ -1827,6 +1842,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = 
> {
>  
>   AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
>   kfd_ioctl_alloc_queue_gws, 0),
> +
> + AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
> + kfd_ioctl_smi_events, 0),
>  };
>  
>  #define AMDKFD_CORE_IOCTL_COUNT  ARRAY_SIZE(amdkfd_ioctls)
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c 
> b/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> index 0491ab2..2c030c2 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c
> +

Re: [PATCH] drm/amdgpu: fix race between pstate and remote buffer map

[Felix Kuehling]

Am 2020-04-16 um 7:59 a.m. schrieb Jonathan Kim:
> Vega20 arbitrates pstate at hive level and not device level. Last peer to
> remote buffer unmap could drop P-State while another process is still
> remote buffer mapped.
>
> With this fix, P-States still needs to be disabled for now as SMU bug
> was discovered on synchronous P2P transfers.  This should be fixed in the
> next FW update.
>
> Signed-off-by: Jonathan Kim 

This looks reasonable. I have some suggestions inline for some clearer
variable names. With that fixed the patch is

Reviewed-by: Felix Kuehling 

See inline ...


> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  2 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h   |  4 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 66 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h |  6 +++
>  5 files changed, 43 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 4e1d4cfe7a9f..94dff899248d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -982,8 +982,6 @@ struct amdgpu_device {
>   uint64_tunique_id;
>   uint64_tdf_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
>  
> - /* device pstate */
> - int pstate;
>   /* enable runtime pm on the device */
>   boolrunpm;
>   boolin_runpm;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index accbb34ea670..95560eea61c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2135,11 +2135,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct 
> amdgpu_device *adev,
>   if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
>   (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
>   bo_va->is_xgmi = true;
> - mutex_lock(&adev->vm_manager.lock_pstate);
>   /* Power up XGMI if it can be potentially used */
> - if (++adev->vm_manager.xgmi_map_counter == 1)
> - amdgpu_xgmi_set_pstate(adev, 1);
> - mutex_unlock(&adev->vm_manager.lock_pstate);
> + amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
>   }
>  
>   return bo_va;
> @@ -2562,12 +2559,8 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
>  
>   dma_fence_put(bo_va->last_pt_update);
>  
> - if (bo && bo_va->is_xgmi) {
> - mutex_lock(&adev->vm_manager.lock_pstate);
> - if (--adev->vm_manager.xgmi_map_counter == 0)
> - amdgpu_xgmi_set_pstate(adev, 0);
> - mutex_unlock(&adev->vm_manager.lock_pstate);
> - }
> + if (bo && bo_va->is_xgmi)
> + amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
>  
>   kfree(bo_va);
>  }
> @@ -3177,9 +3170,6 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
>  
>   idr_init(&adev->vm_manager.pasid_idr);
>   spin_lock_init(&adev->vm_manager.pasid_lock);
> -
> - adev->vm_manager.xgmi_map_counter = 0;
> - mutex_init(&adev->vm_manager.lock_pstate);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index ea771d84bf2b..c8e68d7890bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -357,10 +357,6 @@ struct amdgpu_vm_manager {
>*/
>   struct idr  pasid_idr;
>   spinlock_t  pasid_lock;
> -
> - /* counter of mapped memory through xgmi */
> - uint32_txgmi_map_counter;
> - struct mutexlock_pstate;
>  };
>  
>  #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) 
> ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> index 8c3215505e78..52f45b9fe271 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
> @@ -373,7 +373,13 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct 
> amdgpu_device *adev, int lo
>  
>   if (lock)
>   mutex_lock(&tmp->hive_lock);
> - tmp->pstate = -1;
> + tmp->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
> + tmp->high_gpu = NULL;
> + /*
> +  * hive pstate on boot is high in vega20 so we have to go to low
> +  * pstate on after boot.
> +  */
> + tmp->map_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
>   mutex_unlock(&xgmi_mutex);
>  
>   return tmp;
> @@ -383,50 +389,49 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, 
> int pstate)
>  {
>   int ret = 0;
>   struct amdgpu_hive_info *hiv

[PATCH] drm/amdgpu: load SMU IP for onevf mode on Navi1x V2

[Evan Quan]

SMU IP needs to be loaded for onevf mode. Otherwise, there
may be accesses without initialization.

V2: added SMU IP for all sriov cases since there is necessary
checks in IP operations(hw_init/fini)

Change-Id: I513aa4140f1169ca048b64985cafe9c7577afca7
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 995bdec9fa7d..15ad9f78344c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -474,8 +474,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
-   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
-   !amdgpu_sriov_vf(adev))
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -485,8 +484,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 #endif
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
-   if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
-   !amdgpu_sriov_vf(adev))
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
@@ -498,8 +496,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
-   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
-   !amdgpu_sriov_vf(adev))
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -509,8 +506,7 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
 #endif
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
-   if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
-   !amdgpu_sriov_vf(adev))
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
if (!amdgpu_sriov_vf(adev))
-- 
2.26.1

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Re: [PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Huang Rui]

On Fri, Apr 17, 2020 at 10:58:59AM +0800, Yuxian Dai wrote:
> for different ASIC support different the number of DPM levels,
> we should avoid to show the invalid level value.
> v1 -> v2:
>   follow the suggestion,clarifiy the description for this
> change
> Signed-off-by: Yuxian Dai 
> Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050

Reviewed-by: Huang Rui 

git format-patch --subject-prefix="PATCH v2" HEAD~

It's to indicate v2 patch in the subject.

Thanks,
Ray

> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 281b7b6cf1a4..e4e7a352d032 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context 
> *smu,
>  
>   for (i = 0; i < count; i++) {
>   GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> + if (!value)
> + continue;
>   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
>   cur_value == value ? "*" : "");
>   if (cur_value == value)
> -- 
> 2.17.1
> 
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[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Yuxian Dai]

for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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[PATCH] drm/amdgpu: refine kiq read register

[Yintian Tao]

According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
   get REG-1 value

Therefore, directly make kiq write the register value at
the ring buffer then there will be no race condition for
the wb buffer.

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  | 11 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  5 +++--
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 11 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 12 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 25 
 6 files changed, 32 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..1253dd1ba42c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 
spin_lock_init(&kiq->ring_lock);
 
-   r = amdgpu_device_wb_get(adev, &kiq->reg_val_offs);
-   if (r)
-   return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 
 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 {
-   amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
 }
 
@@ -675,12 +670,14 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, 
uint32_t reg)
uint32_t seq;
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct amdgpu_ring *ring = &kiq->ring;
+   uint64_t reg_val_offs = 0;
 
BUG_ON(!ring->funcs->emit_rreg);
 
spin_lock_irqsave(&kiq->ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
-   amdgpu_ring_emit_rreg(ring, reg);
+   reg_val_offs = (ring->wptr & ring->buf_mask) + 16;
+   amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, &seq);
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(&kiq->ring_lock, flags);
@@ -707,7 +704,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, 
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
 
-   return adev->wb.wb[kiq->reg_val_offs];
+   return ring->ring[reg_val_offs];
 
 failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring  ring;
struct amdgpu_irq_src   irq;
const struct kiq_pm4_funcs *pmf;
-   uint32_treg_val_offs;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..a3d88f2aa9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
-   void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+   void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint64_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
  uint32_t val, uint32_t mask);
@@ -265,7 +266,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
-#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
+#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), 
(d), (v), (m))
 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) 
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0a03e2ad5d95..5873e56341f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx

RE: [PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Dai, Yuxian (David)]

[AMD Official Use Only - Internal Distribution Only]

On Fri, Apr 17, 2020 at 10:58:59AM +0800, Yuxian Dai wrote:
> for different ASIC support different the number of DPM levels, we 
> should avoid to show the invalid level value.
> v1 -> v2:
>   follow the suggestion,clarifiy the description for this change
> Signed-off-by: Yuxian Dai 
> Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050

Reviewed-by: Huang Rui 

git format-patch --subject-prefix="PATCH v2" HEAD~

It's to indicate v2 patch in the subject.

Thanks,
Ray
 > got it. Thank for your help
> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 281b7b6cf1a4..e4e7a352d032 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct 
> smu_context *smu,
>  
>   for (i = 0; i < count; i++) {
>   GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
> + if (!value)
> + continue;
>   size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
>   cur_value == value ? "*" : "");
>   if (cur_value == value)
> --
> 2.17.1
> 
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[PATCH] drm/amdgpu: refine kiq read register

[Yintian Tao]

According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
   get REG-1 value

Therefore, directly make kiq write the register value at
the ring buffer then there will be no race condition for
the wb buffer.

v2: supply the read_clock and move the reg_val_offs back

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c  | 11 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  5 +++--
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 14 +---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 14 +---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 28 
 6 files changed, 33 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..4e1c0239e561 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 
spin_lock_init(&kiq->ring_lock);
 
-   r = amdgpu_device_wb_get(adev, &kiq->reg_val_offs);
-   if (r)
-   return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
 
 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
 {
-   amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
 }
 
@@ -675,12 +670,14 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, 
uint32_t reg)
uint32_t seq;
struct amdgpu_kiq *kiq = &adev->gfx.kiq;
struct amdgpu_ring *ring = &kiq->ring;
+   uint64_t reg_val_offs = 0;
 
BUG_ON(!ring->funcs->emit_rreg);
 
spin_lock_irqsave(&kiq->ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
-   amdgpu_ring_emit_rreg(ring, reg);
+   reg_val_offs = (ring->wptr & ring->buf_mask) + 30;
+   amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, &seq);
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(&kiq->ring_lock, flags);
@@ -707,7 +704,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, 
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
 
-   return adev->wb.wb[kiq->reg_val_offs];
+   return ring->ring[reg_val_offs];
 
 failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring  ring;
struct amdgpu_irq_src   irq;
const struct kiq_pm4_funcs *pmf;
-   uint32_treg_val_offs;
 };
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..a3d88f2aa9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
-   void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+   void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint64_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
  uint32_t val, uint32_t mask);
@@ -265,7 +266,7 @@ struct amdgpu_ring {
 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
-#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
+#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), 
(d), (v), (m))
 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) 
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0a03e2ad5d95

[PATCH] drm/amdgpu/powerplay:avoid to show invalid DPM table info

[Yuxian Dai]

for different ASIC support different the number of DPM levels,
we should avoid to show the invalid level value.
v1 -> v2:
follow the suggestion,clarifiy the description for this
change
Signed-off-by: Yuxian Dai 
Change-Id: I579ef417ddc8acb4a6cf15c60094743a72d9b050
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c 
b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 281b7b6cf1a4..e4e7a352d032 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -296,6 +296,8 @@ static int renoir_print_clk_levels(struct smu_context *smu,
 
for (i = 0; i < count; i++) {
GET_DPM_CUR_FREQ(clk_table, clk_type, i, value);
+   if (!value)
+   continue;
size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
cur_value == value ? "*" : "");
if (cur_value == value)
-- 
2.17.1

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