Re: kernel panic: stack is corrupted in pointer

[Dmitry Vyukov]

On Wed, Jul 17, 2019 at 10:58 AM syzbot
 wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:1438cde7 Add linux-next specific files for 20190716
> git tree:   linux-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=1398805860
> kernel config:  https://syzkaller.appspot.com/x/.config?x=3430a151e1452331
> dashboard link: https://syzkaller.appspot.com/bug?extid=79f5f028005a77ecb6bb
> compiler:   gcc (GCC) 9.0.0 20181231 (experimental)
> syz repro:  https://syzkaller.appspot.com/x/repro.syz?x=111fc8afa0

>From the repro it looks like the same bpf stack overflow bug. +John
We need to dup them onto some canonical report for this bug, or this
becomes unmanageable.

#syz dup: kernel panic: corrupted stack end in dput

> The bug was bisected to:
>
> commit 96a5d8d4915f3e241ebb48d5decdd110ab9c7dcf
> Author: Leo Liu 
> Date:   Fri Jul 13 15:26:28 2018 +
>
>  drm/amdgpu: Make sure IB tests flushed after IP resume
>
> bisection log:  https://syzkaller.appspot.com/x/bisect.txt?x=14a4620060
> final crash:https://syzkaller.appspot.com/x/report.txt?x=16a4620060
> console output: https://syzkaller.appspot.com/x/log.txt?x=12a4620060
>
> IMPORTANT: if you fix the bug, please add the following tag to the commit:
> Reported-by: syzbot+79f5f028005a77ecb...@syzkaller.appspotmail.com
> Fixes: 96a5d8d4915f ("drm/amdgpu: Make sure IB tests flushed after IP
> resume")
>
> Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in:
> pointer+0x702/0x750 lib/vsprintf.c:2187
> Shutting down cpus with NMI
> Kernel Offset: disabled
>
>
> ---
> This bug is generated by a bot. It may contain errors.
> See https://goo.gl/tpsmEJ for more information about syzbot.
> syzbot engineers can be reached at syzkal...@googlegroups.com.
>
> syzbot will keep track of this bug report. See:
> https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
> For information about bisection process see: https://goo.gl/tpsmEJ#bisection
> syzbot can test patches for this bug, for details see:
> https://goo.gl/tpsmEJ#testing-patches

[PATCH 1/2] drm/amd/powerplay: no pptable transfer and dpms enabled with "dpm=0"

[Evan Quan]

Honor the 'dpm' module parameter setting on SW SMU routine as what
we did on previous ASICs. SMU FW loading is still proceeded even
with "dpm=0".

Change-Id: I4e2bd434035c315391d0c0cbabb6ac8c6f23f239
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..266614e27392 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1037,6 +1037,9 @@ static int smu_hw_init(void *handle)
}
}
 
+   if (!smu->pm_enabled)
+   return 0;
+
ret = smu_feature_init_dpm(smu);
if (ret)
goto failed;
-- 
2.22.0

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[PATCH 2/2] drm/amd/powerplay: some cosmetic fixes

[Evan Quan]

Drop redundant check, duplicate check, duplicate setting
and fix the return value.

Change-Id: I04171bcac82f17152371d05e6958d4fc072c0f6b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 33 +++---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 30 
 2 files changed, 28 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..aad3e105901b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -367,13 +367,6 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
 
-   if (!amdgpu_sriov_vf(adev)) {
-   if (is_support_sw_smu(adev))
-   current_level = smu_get_performance_level(&adev->smu);
-   else if (adev->powerplay.pp_funcs->get_performance_level)
-   current_level = amdgpu_dpm_get_performance_level(adev);
-   }
-
if (strncmp("low", buf, strlen("low")) == 0) {
level = AMD_DPM_FORCED_LEVEL_LOW;
} else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -397,17 +390,23 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
goto fail;
}
 
-if (amdgpu_sriov_vf(adev)) {
-if (amdgim_is_hwperf(adev) &&
-adev->virt.ops->force_dpm_level) {
-mutex_lock(&adev->pm.mutex);
-adev->virt.ops->force_dpm_level(adev, level);
-mutex_unlock(&adev->pm.mutex);
-return count;
-} else {
-return -EINVAL;
+   /* handle sriov case here */
+   if (amdgpu_sriov_vf(adev)) {
+   if (amdgim_is_hwperf(adev) &&
+   adev->virt.ops->force_dpm_level) {
+   mutex_lock(&adev->pm.mutex);
+   adev->virt.ops->force_dpm_level(adev, level);
+   mutex_unlock(&adev->pm.mutex);
+   return count;
+   } else {
+   return -EINVAL;
}
-}
+   }
+
+   if (is_support_sw_smu(adev))
+   current_level = smu_get_performance_level(&adev->smu);
+   else if (adev->powerplay.pp_funcs->get_performance_level)
+   current_level = amdgpu_dpm_get_performance_level(adev);
 
if (current_level == level)
return count;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 266614e27392..a92d13b513da 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1398,6 +1398,7 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
 
if (!smu->pm_enabled)
return -EINVAL;
+
if (!skip_display_settings) {
ret = smu_display_config_changed(smu);
if (ret) {
@@ -1406,8 +1407,6 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
}
}
 
-   if (!smu->pm_enabled)
-   return -EINVAL;
ret = smu_apply_clocks_adjust_rules(smu);
if (ret) {
pr_err("Failed to apply clocks adjust rules!");
@@ -1426,9 +1425,14 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
ret = smu_asic_set_performance_level(smu, level);
if (ret) {
ret = smu_default_set_performance_level(smu, level);
+   if (ret) {
+   pr_err("Failed to set performance level!");
+   return ret;
+   }
}
-   if (!ret)
-   smu_dpm_ctx->dpm_level = level;
+
+   /* update the saved copy */
+   smu_dpm_ctx->dpm_level = level;
}
 
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
@@ -1487,28 +1491,18 @@ enum amd_dpm_forced_level 
smu_get_performance_level(struct smu_context *smu)
 
 int smu_force_performance_level(struct smu_context *smu, enum 
amd_dpm_forced_level level)
 {
-   int ret = 0;
-   int i;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+   int ret = 0;
 
if (!smu_dpm_ctx->dpm_context)
return -EINVAL;
 
-   for (i = 0; i < smu->adev->num_ip_blocks; i++) {
-   if (smu->adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_SMC)
-   break;
-   }
-
-
-   smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, &level);
-   ret = smu_handle_task(smu, level,
- AMD_PP_TASK_READJUST_POWER_STATE);
+   ret = smu_enable_umd_pstate(smu, &level);

[PATCH] drm/amd/display: Use dev_get_drvdata

[Chuhong Yuan]

Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.

Signed-off-by: Chuhong Yuan 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 4a29f72334d0..524e1e19017e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2428,8 +2428,7 @@ static ssize_t s3_debug_store(struct device *device,
 {
int ret;
int s3_state;
-   struct pci_dev *pdev = to_pci_dev(device);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(device);
struct amdgpu_device *adev = drm_dev->dev_private;
 
ret = kstrtoint(buf, 0, &s3_state);
-- 
2.20.1

[PATCH] drm/amdgpu: Use dev_get_drvdata where possible

[Chuhong Yuan]

Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.

Signed-off-by: Chuhong Yuan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 +
 1 file changed, 10 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index f2e8b4238efd..df82091a29d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1097,16 +1097,14 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
 
 static int amdgpu_pmops_suspend(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
return amdgpu_device_suspend(drm_dev, true, true);
 }
 
 static int amdgpu_pmops_resume(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
 
/* GPU comes up enabled by the bios on resume */
if (amdgpu_device_is_px(drm_dev)) {
@@ -1120,33 +1118,29 @@ static int amdgpu_pmops_resume(struct device *dev)
 
 static int amdgpu_pmops_freeze(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
+
return amdgpu_device_suspend(drm_dev, false, true);
 }
 
 static int amdgpu_pmops_thaw(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
+
return amdgpu_device_resume(drm_dev, false, true);
 }
 
 static int amdgpu_pmops_poweroff(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
+
return amdgpu_device_suspend(drm_dev, true, true);
 }
 
 static int amdgpu_pmops_restore(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
 
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
return amdgpu_device_resume(drm_dev, false, true);
 }
 
@@ -1205,8 +1199,7 @@ static int amdgpu_pmops_runtime_resume(struct device *dev)
 
 static int amdgpu_pmops_runtime_idle(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
struct drm_crtc *crtc;
 
if (!amdgpu_device_is_px(drm_dev)) {
-- 
2.20.1

Re: [PATCH v4 14/23] drm/tilcdc: Provide ddc symlink in connector sysfs directory

[Sam Ravnborg]

Hi Andrzej

On Thu, Jul 11, 2019 at 01:26:41PM +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c 
> b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> index 62d014c20988..c373edb95666 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> @@ -219,6 +219,7 @@ static struct drm_connector 
> *tfp410_connector_create(struct drm_device *dev,
>   tfp410_connector->mod = mod;
>  
>   connector = &tfp410_connector->base;
> + connector->ddc = mod->i2c;
>  
>   drm_connector_init(dev, connector, &tfp410_connector_funcs,
>   DRM_MODE_CONNECTOR_DVID);

When reading this code, it looks strange that we set connector->ddc
*before* the call to init the connector.
One could risk that drm_connector_init() used memset(..) to clear all
fields or so, and it would break this order.
As it is today the code works as I read it.

Sam
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Re: [PATCH v4 16/23] drm/mgag200: Provide ddc symlink in connector sysfs directory

[Sam Ravnborg]

Hi Andrzej.

On Thu, Jul 11, 2019 at 01:26:43PM +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/mgag200/mgag200_mode.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c 
> b/drivers/gpu/drm/mgag200/mgag200_mode.c
> index a25054015e8c..8fb9444b2142 100644
> --- a/drivers/gpu/drm/mgag200/mgag200_mode.c
> +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
> @@ -1703,6 +1703,11 @@ static struct drm_connector *mga_vga_init(struct 
> drm_device *dev)
>   return NULL;
>  
>   connector = &mga_connector->base;
> + mga_connector->i2c = mgag200_i2c_create(dev);
> + if (!mga_connector->i2c)
> + DRM_ERROR("failed to add ddc bus\n");
> +
> + connector->ddc = &mga_connector->i2c->adapter;
>  
>   drm_connector_init(dev, connector,
>  &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
Like on other patch, assigning connector->ddc before
drm_connector_init() looks wrong.

Sam
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Re: [PATCH v4 17/23] drm/ast: Provide ddc symlink in connector sysfs directory

[Sam Ravnborg]

Hi Andrzej.

On Thu, Jul 11, 2019 at 01:26:44PM +0200, Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
> 
> Signed-off-by: Andrzej Pietrasiewicz 
> ---
>  drivers/gpu/drm/ast/ast_mode.c | 9 +
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c
> index ffccbef962a4..1ca9bc4aa3bb 100644
> --- a/drivers/gpu/drm/ast/ast_mode.c
> +++ b/drivers/gpu/drm/ast/ast_mode.c
> @@ -890,6 +890,11 @@ static int ast_connector_init(struct drm_device *dev)
>   return -ENOMEM;
>  
>   connector = &ast_connector->base;
> + ast_connector->i2c = ast_i2c_create(dev);
> + if (!ast_connector->i2c)
> + DRM_ERROR("failed to add ddc bus for connector\n");
> +
> + connector->ddc = &ast_connector->i2c->adapter;
>   drm_connector_init(dev, connector, &ast_connector_funcs, 
> DRM_MODE_CONNECTOR_VGA);
>  
>   drm_connector_helper_add(connector, &ast_connector_helper_funcs);
Again, assigning before drm_connector_init().
I did not audit the remaining patches - you got the idea.

Sam
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[PATCH v2] drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu

[Wang, Kevin(Yang)]

v2: change function name to smu_clk_dpm_is_enabled.
add this helper function to check dpm clk feature is enabled.

Change-Id: I7f9949033c318fec618a9701df4a082d54a626c8
Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 69 ---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 +
 2 files changed, 47 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 787a293fde97..c16195e19078 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -69,6 +69,10 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum 
smu_clk_type clk_type,
if (min <= 0 && max <= 0)
return -EINVAL;
 
+   ret = smu_clk_dpm_is_enabled(smu, clk_type);
+   if (ret)
+   return ret;
+
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0)
return clk_id;
@@ -102,6 +106,10 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum 
smu_clk_type clk_type,
if (min <= 0 && max <= 0)
return -EINVAL;
 
+   ret = smu_clk_dpm_is_enabled(smu, clk_type);
+   if (ret)
+   return ret;
+
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0)
return clk_id;
@@ -135,29 +143,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum 
smu_clk_type clk_type,
if (!min && !max)
return -EINVAL;
 
-   switch (clk_type) {
-   case SMU_MCLK:
-   case SMU_UCLK:
-   if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
-   pr_warn("uclk dpm is not enabled\n");
-   return 0;
-   }
-   break;
-   case SMU_GFXCLK:
-   case SMU_SCLK:
-   if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
-   pr_warn("gfxclk dpm is not enabled\n");
-   return 0;
-   }
-   case SMU_SOCCLK:
-   if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
-   pr_warn("sockclk dpm is not enabled\n");
-   return 0;
-   }
-   break;
-   default:
-   break;
-   }
+   ret = smu_clk_dpm_is_enabled(smu, clk_type);
+   if (ret)
+   return ret;
 
mutex_lock(&smu->mutex);
clk_id = smu_clk_get_index(smu, clk_type);
@@ -200,6 +188,10 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, 
enum smu_clk_type clk_typ
if (!value)
return -EINVAL;
 
+   ret = smu_clk_dpm_is_enabled(smu, clk_type);
+   if (ret)
+   return ret;
+
clk_id = smu_clk_get_index(smu, clk_type);
if (clk_id < 0)
return clk_id;
@@ -228,6 +220,37 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum 
smu_clk_type clk_type,
return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 }
 
+int smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
+{
+   int ret = 0;
+   enum smu_feature_mask feature_id = 0;
+
+   switch (clk_type) {
+   case SMU_MCLK:
+   case SMU_UCLK:
+   feature_id = SMU_FEATURE_DPM_UCLK_BIT;
+   break;
+   case SMU_GFXCLK:
+   case SMU_SCLK:
+   feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
+   break;
+   case SMU_SOCCLK:
+   feature_id =  SMU_FEATURE_DPM_SOCCLK_BIT;
+   break;
+   default:
+   return 0;
+   }
+
+   ret = smu_feature_is_enabled(smu, feature_id);
+   if (ret) {
+   pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, 
feature_id);
+   return -EACCES;
+   }
+
+   return ret;
+}
+
+
 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
   bool gate)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c97324ef7db2..4629a64a90ed 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum 
smu_clk_type clk_type,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum 
amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
+int smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type 
clk_type);
 
 #endif
-- 
2.22.0

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[PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Wang, Kevin(Yang)]

1. the thermal temperature is asic related data, move the code logic to
xxx_ppt.c.
2. replace data structure PP_TemperatureRange with
smu_temperature_range.
3. change temperature uint from temp*1000 to temp (temperature uint).

Signed-off-by: Kevin Wang 
Signed-off-by: Kenneth Feng 
Acked-by: Huang Rui 
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
 4 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 34093ddca105..7105f8041088 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -439,7 +439,6 @@ struct smu_table_context
struct smu_table*tables;
uint32_ttable_count;
struct smu_tablememory_pool;
-   uint16_tsoftware_shutdown_temp;
uint8_t thermal_controller_type;
uint16_tTDPODLimit;
 
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 46e2913e4af4..a4c4d4997189 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct 
smu_context *smu, enum amd_dpm_fo
return ret;
 }
 
+static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+   struct smu_temperature_range 
*range)
+{
+   struct smu_table_context *table_context = &smu->smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
table_context->power_play_table;
+
+   if (!range || !powerplay_table)
+   return -EINVAL;
+
+   /* The unit is temperature */
+   range->min = 0;
+   range->max = powerplay_table->software_shutdown_temp;
+
+   return 0;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1674,6 +1690,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_ppfeature_status = navi10_get_ppfeature_status,
.set_ppfeature_status = navi10_set_ppfeature_status,
.set_performance_level = navi10_set_performance_level,
+   .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 76bc157525d0..4ad9e0c5a637 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct 
smu_context *smu,
   struct smu_temperature_range *range)
 {
struct amdgpu_device *adev = smu->adev;
-   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
uint32_t val;
 
if (!range)
@@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
if (high > range->max)
high = range->max;
 
+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
+
if (low > high)
return -EINVAL;
 
@@ -1169,8 +1170,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 
0xff));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 
0xff));
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
@@ -1209,7 +1210,10 @@ static int smu_v11_0_start_thermal_control(struct 
smu_context *smu)
 
if (!smu->pm_enabled)
return ret;
+
ret = smu_get_thermal_temperature_range(smu, &range);
+   if (ret)
+   return ret

撤回: [PATCH v2] drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu

[Wang, Kevin(Yang)]

Wang, Kevin(Yang) 将撤回邮件“[PATCH v2] drm/amd/powerplay: add helper of 
smu_clk_dpm_is_enabled for smu”。
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撤回: [PATCH v2] drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu

[Wang, Kevin(Yang)]

Wang, Kevin(Yang) 将撤回邮件“[PATCH v2] drm/amd/powerplay: add helper of 
smu_clk_dpm_is_enabled for smu”。
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撤回: [PATCH v2] drm/amd/powerplay: add helper of smu_clk_dpm_is_enabled for smu

[Wang, Kevin(Yang)]

Wang, Kevin(Yang) 将撤回邮件“[PATCH v2] drm/amd/powerplay: add helper of 
smu_clk_dpm_is_enabled for smu”。
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Re: [PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Wang, Kevin(Yang)]

@Feng, Kenneth


please help me review this patch, this patch is reveiwed before.

but this patch is missed from navi10 topic branch.


Best Regards,
Kevin


From: Wang, Kevin(Yang) 
Sent: Tuesday, July 23, 2019 5:31:47 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Feng, Kenneth ; Huang, Ray ; Wang, 
Kevin(Yang) ; Feng, Kenneth 
Subject: [PATCH] drm/amd/powerplay: add callback function of 
get_thermal_temperature_range

1. the thermal temperature is asic related data, move the code logic to
xxx_ppt.c.
2. replace data structure PP_TemperatureRange with
smu_temperature_range.
3. change temperature uint from temp*1000 to temp (temperature uint).

Signed-off-by: Kevin Wang 
Signed-off-by: Kenneth Feng 
Acked-by: Huang Rui 
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
 4 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 34093ddca105..7105f8041088 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -439,7 +439,6 @@ struct smu_table_context
 struct smu_table*tables;
 uint32_ttable_count;
 struct smu_tablememory_pool;
-   uint16_tsoftware_shutdown_temp;
 uint8_t thermal_controller_type;
 uint16_tTDPODLimit;

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 46e2913e4af4..a4c4d4997189 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct 
smu_context *smu, enum amd_dpm_fo
 return ret;
 }

+static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+   struct smu_temperature_range 
*range)
+{
+   struct smu_table_context *table_context = &smu->smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
table_context->power_play_table;
+
+   if (!range || !powerplay_table)
+   return -EINVAL;
+
+   /* The unit is temperature */
+   range->min = 0;
+   range->max = powerplay_table->software_shutdown_temp;
+
+   return 0;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
 .tables_init = navi10_tables_init,
 .alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1674,6 +1690,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 .get_ppfeature_status = navi10_get_ppfeature_status,
 .set_ppfeature_status = navi10_set_ppfeature_status,
 .set_performance_level = navi10_set_performance_level,
+   .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };

 void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 76bc157525d0..4ad9e0c5a637 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct 
smu_context *smu,
struct smu_temperature_range *range)
 {
 struct amdgpu_device *adev = smu->adev;
-   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
 uint32_t val;

 if (!range)
@@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
 if (high > range->max)
 high = range->max;

+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
+
 if (low > high)
 return -EINVAL;

@@ -1169,8 +1170,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INT

[PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

[Kenneth Feng]

change the smu_read_sensor sequence to:

asic specific sensor read -> smu v11 specific sensor read -> smu v11 common 
sensor read

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 8 
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 -
 5 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a8..8ff18c8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -315,6 +315,9 @@ int smu_common_read_sensor(struct smu_context *smu, enum 
amd_pp_sensors sensor,
 {
int ret = 0;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)data) = smu->pstate_sclk;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b702c9e..fabb373 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -819,9 +819,9 @@ struct smu_funcs
 #define smu_start_thermal_control(smu) \
((smu)->funcs->start_thermal_control? 
(smu)->funcs->start_thermal_control((smu)) : 0)
 #define smu_read_sensor(smu, sensor, data, size) \
-   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : 0)
-#define smu_asic_read_sensor(smu, sensor, data, size) \
((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), 
(sensor), (data), (size)) : 0)
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : -EINVAL)
 #define smu_get_power_profile_mode(smu, buf) \
((smu)->ppt_funcs->get_power_profile_mode ? 
(smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
 #define smu_set_power_profile_mode(smu, param, param_size) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bb..6409718 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1366,6 +1366,9 @@ static int navi10_read_sensor(struct smu_context *smu,
struct smu_table_context *table_context = &smu->smu_table;
PPTable_t *pptable = table_context->driver_pptable;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1387,7 +1390,7 @@ static int navi10_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
}
 
return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index e3a1784..5267b68 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1267,6 +1267,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 void *data, uint32_t *size)
 {
int ret = 0;
+
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_GFX_MCLK:
ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t *)data);
@@ -1289,10 +1293,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
break;
}
 
-   /* try get sensor data by asic */
-   if (ret)
-   ret = smu_asic_read_sensor(smu, sensor, data, size);
-
if (ret)
*size = 0;
 
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9ead361..e864a54 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3163,6 +3163,9 @@ static int vega20_read_sensor(struct smu_context *smu,
struct smu_table_context *table_context = &smu->smu_table;
PPTable_t *pptable = table_context->driver_pptable;
 
+   if(!data || !size)
+   return -EINVAL;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
*(uint32_t *)data = pptable->FanMaximumRpm;
@@ -3186,7 +3189,7 @@ static int vega20_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
}
 
return ret;
-- 
2.7.4

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RE: [PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Feng, Kenneth]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>


From: Wang, Kevin(Yang)
Sent: Tuesday, July 23, 2019 5:36 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth 
Cc: Huang, Ray 
Subject: Re: [PATCH] drm/amd/powerplay: add callback function of 
get_thermal_temperature_range


@Feng, Kenneth



please help me review this patch, this patch is reveiwed before.

but this patch is missed from navi10 topic branch.



Best Regards,
Kevin


From: Wang, Kevin(Yang) mailto:kevin1.w...@amd.com>>
Sent: Tuesday, July 23, 2019 5:31:47 PM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Feng, Kenneth mailto:kenneth.f...@amd.com>>; Huang, 
Ray mailto:ray.hu...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: [PATCH] drm/amd/powerplay: add callback function of 
get_thermal_temperature_range

1. the thermal temperature is asic related data, move the code logic to
xxx_ppt.c.
2. replace data structure PP_TemperatureRange with
smu_temperature_range.
3. change temperature uint from temp*1000 to temp (temperature uint).

Signed-off-by: Kevin Wang mailto:kevin1.w...@amd.com>>
Signed-off-by: Kenneth Feng mailto:kenneth.f...@amd.com>>
Acked-by: Huang Rui mailto:ray.hu...@amd.com>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
 4 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 34093ddca105..7105f8041088 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -439,7 +439,6 @@ struct smu_table_context
 struct smu_table*tables;
 uint32_ttable_count;
 struct smu_tablememory_pool;
-   uint16_tsoftware_shutdown_temp;
 uint8_t thermal_controller_type;
 uint16_tTDPODLimit;

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 46e2913e4af4..a4c4d4997189 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct 
smu_context *smu, enum amd_dpm_fo
 return ret;
 }

+static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+   struct smu_temperature_range 
*range)
+{
+   struct smu_table_context *table_context = &smu->smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
table_context->power_play_table;
+
+   if (!range || !powerplay_table)
+   return -EINVAL;
+
+   /* The unit is temperature */
+   range->min = 0;
+   range->max = powerplay_table->software_shutdown_temp;
+
+   return 0;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
 .tables_init = navi10_tables_init,
 .alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1674,6 +1690,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 .get_ppfeature_status = navi10_get_ppfeature_status,
 .set_ppfeature_status = navi10_set_ppfeature_status,
 .set_performance_level = navi10_set_performance_level,
+   .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };

 void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 76bc157525d0..4ad9e0c5a637 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct 
smu_context *smu,
struct smu_temperature_range *range)
 {
 struct amdgpu_device *adev = smu->adev;
-   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
 uint32_t val;

 if (!range)
@@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
 if (high > range->max)
 high = range->max;

+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
+
 if (low > high)
 return -EINVAL;

@@ -1169,8 +1170,8 @@ static int smu_v11

Re: [PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

[Wang, Kevin(Yang)]

it looks fine for me,

please @Deucher, Alexander double check 
confirm.

Reviewed-by: Kevin Wang 

Best Regards,
Kevin


From: amd-gfx  on behalf of Kenneth Feng 

Sent: Tuesday, July 23, 2019 5:39 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

change the smu_read_sensor sequence to:

asic specific sensor read -> smu v11 specific sensor read -> smu v11 common 
sensor read

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 8 
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 -
 5 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a8..8ff18c8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -315,6 +315,9 @@ int smu_common_read_sensor(struct smu_context *smu, enum 
amd_pp_sensors sensor,
 {
 int ret = 0;

+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 *((uint32_t *)data) = smu->pstate_sclk;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b702c9e..fabb373 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -819,9 +819,9 @@ struct smu_funcs
 #define smu_start_thermal_control(smu) \
 ((smu)->funcs->start_thermal_control? 
(smu)->funcs->start_thermal_control((smu)) : 0)
 #define smu_read_sensor(smu, sensor, data, size) \
-   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : 0)
-#define smu_asic_read_sensor(smu, sensor, data, size) \
 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), 
(sensor), (data), (size)) : 0)
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : -EINVAL)
 #define smu_get_power_profile_mode(smu, buf) \
 ((smu)->ppt_funcs->get_power_profile_mode ? 
(smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
 #define smu_set_power_profile_mode(smu, param, param_size) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bb..6409718 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1366,6 +1366,9 @@ static int navi10_read_sensor(struct smu_context *smu,
 struct smu_table_context *table_context = &smu->smu_table;
 PPTable_t *pptable = table_context->driver_pptable;

+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 *(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1387,7 +1390,7 @@ static int navi10_read_sensor(struct smu_context *smu,
 *size = 4;
 break;
 default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
 }

 return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index e3a1784..5267b68 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1267,6 +1267,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
  void *data, uint32_t *size)
 {
 int ret = 0;
+
+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_GFX_MCLK:
 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t 
*)data);
@@ -1289,10 +1293,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 break;
 }

-   /* try get sensor data by asic */
-   if (ret)
-   ret = smu_asic_read_sensor(smu, sensor, data, size);
-
 if (ret)
 *size = 0;

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9ead361..e864a54 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3163,6 +3163,9 @@ static int vega20_read_sensor(struct smu_context *smu,
 struct smu_table_context *table_context = &smu->smu_table;
 PPTable_t *pptable = table_context->driver_pptable;

+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 *(uint32_t *)data 

RE: [PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Kevin(Yang) 
Sent: Tuesday, July 23, 2019 5:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ; Wang, 
Kevin(Yang) ; Feng, Kenneth 
Subject: [PATCH] drm/amd/powerplay: add callback function of 
get_thermal_temperature_range

1. the thermal temperature is asic related data, move the code logic to 
xxx_ppt.c.
2. replace data structure PP_TemperatureRange with smu_temperature_range.
3. change temperature uint from temp*1000 to temp (temperature uint).

Signed-off-by: Kevin Wang 
Signed-off-by: Kenneth Feng 
Acked-by: Huang Rui 
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
 4 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 34093ddca105..7105f8041088 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -439,7 +439,6 @@ struct smu_table_context
struct smu_table*tables;
uint32_ttable_count;
struct smu_tablememory_pool;
-   uint16_tsoftware_shutdown_temp;
uint8_t thermal_controller_type;
uint16_tTDPODLimit;
 
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 46e2913e4af4..a4c4d4997189 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct 
smu_context *smu, enum amd_dpm_fo
return ret;
 }
 
+static int navi10_get_thermal_temperature_range(struct smu_context *smu,
+   struct smu_temperature_range 
*range) {
+   struct smu_table_context *table_context = &smu->smu_table;
+   struct smu_11_0_powerplay_table *powerplay_table = 
+table_context->power_play_table;
+
+   if (!range || !powerplay_table)
+   return -EINVAL;
+
+   /* The unit is temperature */
+   range->min = 0;
+   range->max = powerplay_table->software_shutdown_temp;
+
+   return 0;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context, @@ -1674,6 +1690,7 @@ 
static const struct pptable_funcs navi10_ppt_funcs = {
.get_ppfeature_status = navi10_get_ppfeature_status,
.set_ppfeature_status = navi10_set_ppfeature_status,
.set_performance_level = navi10_set_performance_level,
+   .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu) diff --git 
a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 76bc157525d0..4ad9e0c5a637 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct 
smu_context *smu,
   struct smu_temperature_range *range)  {
struct amdgpu_device *adev = smu->adev;
-   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
-   SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
uint32_t val;
 
if (!range)
@@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
if (high > range->max)
high = range->max;
 
+   low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP, range->min);
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, range->max);
+
if (low > high)
return -EINVAL;
 
@@ -1169,8 +1170,8 @@ static int smu_v11_0_set_thermal_range(struct smu_context 
*smu,
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 
0xff));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 
+0xff));
val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
 

[PATCH] drm/radeon: Use dev_get_drvdata where possible

[Chuhong Yuan]

Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.

Signed-off-by: Chuhong Yuan 
---
 drivers/gpu/drm/radeon/radeon_drv.c | 15 +--
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
b/drivers/gpu/drm/radeon/radeon_drv.c
index a6cbe11f79c6..b2bb74d5bffb 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -358,15 +358,13 @@ radeon_pci_shutdown(struct pci_dev *pdev)
 
 static int radeon_pmops_suspend(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
return radeon_suspend_kms(drm_dev, true, true, false);
 }
 
 static int radeon_pmops_resume(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
 
/* GPU comes up enabled by the bios on resume */
if (radeon_is_px(drm_dev)) {
@@ -380,15 +378,13 @@ static int radeon_pmops_resume(struct device *dev)
 
 static int radeon_pmops_freeze(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
return radeon_suspend_kms(drm_dev, false, true, true);
 }
 
 static int radeon_pmops_thaw(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
return radeon_resume_kms(drm_dev, false, true);
 }
 
@@ -447,8 +443,7 @@ static int radeon_pmops_runtime_resume(struct device *dev)
 
 static int radeon_pmops_runtime_idle(struct device *dev)
 {
-   struct pci_dev *pdev = to_pci_dev(dev);
-   struct drm_device *drm_dev = pci_get_drvdata(pdev);
+   struct drm_device *drm_dev = dev_get_drvdata(dev);
struct drm_crtc *crtc;
 
if (!radeon_is_px(drm_dev)) {
-- 
2.20.1

RE: [PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Quan, Evan]

Please do not change the output temperature granularity.
Although it seems a little weird. It's required by hwmon interfaces design  and 
has to be in millidegrees Celsius (@Deucher, Alexander, right?).

* hwmon interfaces for GPU temperature:
 *
 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
 *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_label: temperature channel label
 *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
 *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in 
millidegrees Celsius
 *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in 
millidegrees Celsius
 *   - these are supported on SOC15 dGPUs only

Regards,
Evan
> -Original Message-
> From: amd-gfx  On Behalf Of
> Wang, Kevin(Yang)
> Sent: Tuesday, July 23, 2019 5:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Feng, Kenneth
> ; Wang, Kevin(Yang) 
> Subject: [PATCH] drm/amd/powerplay: add callback function of
> get_thermal_temperature_range
> 
> 1. the thermal temperature is asic related data, move the code logic to
> xxx_ppt.c.
> 2. replace data structure PP_TemperatureRange with
> smu_temperature_range.
> 3. change temperature uint from temp*1000 to temp (temperature uint).
> 
> Signed-off-by: Kevin Wang 
> Signed-off-by: Kenneth Feng 
> Acked-by: Huang Rui 
> ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
>  4 files changed, 40 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 34093ddca105..7105f8041088 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -439,7 +439,6 @@ struct smu_table_context
>   struct smu_table*tables;
>   uint32_ttable_count;
>   struct smu_tablememory_pool;
> - uint16_tsoftware_shutdown_temp;
>   uint8_t thermal_controller_type;
>   uint16_tTDPODLimit;
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 46e2913e4af4..a4c4d4997189 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct
> smu_context *smu, enum amd_dpm_fo
>   return ret;
>  }
> 
> +static int navi10_get_thermal_temperature_range(struct smu_context
> *smu,
> + struct
> smu_temperature_range *range) {
> + struct smu_table_context *table_context = &smu->smu_table;
> + struct smu_11_0_powerplay_table *powerplay_table =
> +table_context->power_play_table;
> +
> + if (!range || !powerplay_table)
> + return -EINVAL;
> +
> + /* The unit is temperature */
> + range->min = 0;
> + range->max = powerplay_table->software_shutdown_temp;
> +
> + return 0;
> +}
> +
>  static const struct pptable_funcs navi10_ppt_funcs = {
>   .tables_init = navi10_tables_init,
>   .alloc_dpm_context = navi10_allocate_dpm_context, @@ -1674,6
> +1690,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
>   .get_ppfeature_status = navi10_get_ppfeature_status,
>   .set_ppfeature_status = navi10_set_ppfeature_status,
>   .set_performance_level = navi10_set_performance_level,
> + .get_thermal_temperature_range =
> navi10_get_thermal_temperature_range,
>  };
> 
>  void navi10_set_ppt_funcs(struct smu_context *smu) diff --git
> a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 76bc157525d0..4ad9e0c5a637 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1147,10 +1147,8 @@ static int smu_v11_0_set_thermal_range(struct
> smu_context *smu,
>  struct smu_temperature_range *range)  {
>   struct amdgpu_device *adev = smu->adev;
> - int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
> - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> - int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP *
> - SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + int low = SMU_THERMAL_MINIMUM_ALERT_TEMP;
> + int high = SMU_THERMAL_MAXIMUM_ALERT_TEMP;
>   uint32_t val;
> 
>   if (!range)
> @@ -1161,6 +1159,9 @@ static int smu_v11_0_set_thermal_range(st

Re: [PATCH] drm/amd/powerplay: add callback function of get_thermal_temperature_range

[Wang, Kevin(Yang)]

sure, i know it, this patch is from navi10 topic branch.

the final result don't change the temperature granularity.

please see below code.


but it seems miss other temperature type in this patch,

i will submit a new patch to fix it.


#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES (1000)

> + adev->pm.dpm.thermal.min_temp = range.min *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_temp = range.max *
> +SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>


Thanks.


Best Regards,

Kevin


From: Quan, Evan 
Sent: Tuesday, July 23, 2019 7:15:59 PM
To: Wang, Kevin(Yang) ; amd-gfx@lists.freedesktop.org 
; Deucher, Alexander 
Cc: Huang, Ray ; Feng, Kenneth ; Wang, 
Kevin(Yang) 
Subject: RE: [PATCH] drm/amd/powerplay: add callback function of 
get_thermal_temperature_range

Please do not change the output temperature granularity.
Although it seems a little weird. It's required by hwmon interfaces design  and 
has to be in millidegrees Celsius (@Deucher, Alexander, right?).

* hwmon interfaces for GPU temperature:
 *
 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
 *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_label: temperature channel label
 *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
 *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in 
millidegrees Celsius
 *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
 *
 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in 
millidegrees Celsius
 *   - these are supported on SOC15 dGPUs only

Regards,
Evan
> -Original Message-
> From: amd-gfx  On Behalf Of
> Wang, Kevin(Yang)
> Sent: Tuesday, July 23, 2019 5:32 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, Ray ; Feng, Kenneth
> ; Wang, Kevin(Yang) 
> Subject: [PATCH] drm/amd/powerplay: add callback function of
> get_thermal_temperature_range
>
> 1. the thermal temperature is asic related data, move the code logic to
> xxx_ppt.c.
> 2. replace data structure PP_TemperatureRange with
> smu_temperature_range.
> 3. change temperature uint from temp*1000 to temp (temperature uint).
>
> Signed-off-by: Kevin Wang 
> Signed-off-by: Kenneth Feng 
> Acked-by: Huang Rui 
> ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  1 -
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 17 ++
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 ++
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 34 ++-
>  4 files changed, 40 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 34093ddca105..7105f8041088 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -439,7 +439,6 @@ struct smu_table_context
>struct smu_table*tables;
>uint32_ttable_count;
>struct smu_tablememory_pool;
> - uint16_tsoftware_shutdown_temp;
>uint8_t thermal_controller_type;
>uint16_tTDPODLimit;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 46e2913e4af4..a4c4d4997189 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1638,6 +1638,22 @@ static int navi10_set_performance_level(struct
> smu_context *smu, enum amd_dpm_fo
>return ret;
>  }
>
> +static int navi10_get_thermal_temperature_range(struct smu_context
> *smu,
> + struct
> smu_temperature_range *range) {
> + struct smu_table_context *table_context = &smu->smu_table;
> + struct smu_11_0_powerplay_table *powerplay_table =
> +table_context->power_play_table;
> +
> + if (!range || !powerplay_table)
> + return -EINVAL;
> +
> + /* The unit is temperature */
> + range->min = 0;
> + range->max = powerplay_table->software_shutdown_temp;
> +
> + return 0;
> +}
> +
>  static const struct pptable_funcs navi10_ppt_funcs = {
>.tables_init = navi10_tables_init,
>.alloc_dpm_context = navi10_allocate_dpm_context, @@ -1674,6
> +1690,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
>.get_ppfeature_status = navi10_get_ppfeature_status,
>.set_ppfeature_status = navi10_set_ppfeature_status,
>.set_performance_level = navi10_set_performance_level,
> + .get_thermal_temperature_range =
> navi10_get_thermal_temperature_range,
>  };
>
>  void navi10_set_ppt_funcs(struct smu_context *smu) diff --git
> a/drivers/gpu/drm/amd/powerplay/smu

[PATCH] drm/amd/powerplay: fix temperature granularity error in smu11

[Wang, Kevin(Yang)]

in this patch,
drm/amd/powerplay: add callback function of get_thermal_temperature_range
the driver missed temperature granularity change on other temperature.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 745b35a1600d..735802bb07b9 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1229,15 +1229,15 @@ static int smu_v11_0_start_thermal_control(struct 
smu_context *smu)
return ret;
}
 
-   adev->pm.dpm.thermal.min_temp = range.min;
-   adev->pm.dpm.thermal.max_temp = range.max;
-   adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
-   adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
-   adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
-   adev->pm.dpm.thermal.max_hotspot_emergency_temp = 
range.hotspot_emergency_max;
-   adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
-   adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
-   adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
+   adev->pm.dpm.thermal.min_temp = range.min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_temp = range.max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max 
* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_hotspot_emergency_temp = 
range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.min_mem_temp = range.mem_min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
adev->pm.dpm.thermal.min_temp = range.min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
adev->pm.dpm.thermal.max_temp = range.max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 
-- 
2.22.0

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Re: [PATCH v4 14/23] drm/tilcdc: Provide ddc symlink in connector sysfs directory

[Andrzej Pietrasiewicz]

Hi Sam,

W dniu 23.07.2019 o 11:05, Sam Ravnborg pisze:

Hi Andrzej

On Thu, Jul 11, 2019 at 01:26:41PM +0200, Andrzej Pietrasiewicz wrote:

Use the ddc pointer provided by the generic connector.

Signed-off-by: Andrzej Pietrasiewicz 
---
  drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c 
b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
index 62d014c20988..c373edb95666 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
@@ -219,6 +219,7 @@ static struct drm_connector *tfp410_connector_create(struct 
drm_device *dev,
tfp410_connector->mod = mod;
  
  	connector = &tfp410_connector->base;

+   connector->ddc = mod->i2c;
  
  	drm_connector_init(dev, connector, &tfp410_connector_funcs,

DRM_MODE_CONNECTOR_DVID);


When reading this code, it looks strange that we set connector->ddc
*before* the call to init the connector.
One could risk that drm_connector_init() used memset(..) to clear all
fields or so, and it would break this order.


I verified the code of drm_connector_init() and cannot find any memset()
invocations there. What is your actual concern?

Andrzej
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[PATCH][next] drm/amd/display: remove duplicated comparison

[Colin King]

From: Colin Ian King 

The comparison of surface_pitch is duplicated and hence one of these
comparisons is redundant and can be removed.  Remove it.

Addresses-Coverity: ("Same on both sides")
Fixes: 12e2b2d4c65f ("drm/amd/display: add dcc programming for dual plane")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 94f126d2331c..168f4a7dffdf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1379,7 +1379,6 @@ static enum surface_update_type 
get_plane_info_update_type(const struct dc_surfa
}
 
if (u->plane_info->plane_size.surface_pitch != 
u->surface->plane_size.surface_pitch
-   || u->plane_info->plane_size.surface_pitch != 
u->surface->plane_size.surface_pitch
|| u->plane_info->plane_size.chroma_pitch != 
u->surface->plane_size.chroma_pitch) {
update_flags->bits.plane_size_change = 1;
elevate_update_type(&update_type, UPDATE_TYPE_MED);
-- 
2.20.1

[PATCH][next] drm/amdgpu: remove redundant assignment to pointer 'ring'

[Colin King]

From: Colin Ian King 

The pointer 'ring' is being assigned a value that is never
read, hence the assignment is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 93b3500e522b..a2a8ca942f34 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1331,7 +1331,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device 
*adev,
WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,

UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
 
-   ring = &adev->vcn.inst->ring_dec;
WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
   RREG32_SOC15(UVD, 0, 
mmUVD_SCRATCH2) & 0x7FFF);
SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
-- 
2.20.1

Re: [PATCH 07/10] drm/i915: Implement MST Aux device registration

[Li, Sun peng (Leo)]

On 2019-07-12 4:15 p.m., Ville Syrjälä wrote:
> On Fri, Jul 12, 2019 at 11:05:59PM +0300, Ville Syrjälä wrote:
>> On Fri, Jul 12, 2019 at 03:48:53PM -0400, Lyude Paul wrote:
>>> BTW, I just tried these patches on my T450s (using i915) and I'm seeing some
>>> kernel warnings with them when adding DP aux devices after connecting a new
>>> MST topology to the system: 
>>>
>>> [  367.742571] WARNING: CPU: 2 PID: 442 at 
>>> drivers/gpu/drm/drm_mode_object.c:45 __drm_mode_object_add+0xaa/0xb0 [drm]
>>
>> Looks like Daniel added that particular WARN in
>> commit 4f5368b5541a  ("drm/kms: Catch mode_object lifetime errors").
> 
> And I'm the one who added the max_bpc prop to the mst connectors, which
> is a per-connector property (ie. a new one gets created for every
> connecotor). So that could be a problem I suppose. I guess we may need
> to create just one of these for MST and reuse it for every connector.
> Could just point at the prop of the corresponding SST connector I
> suppose...
> 
> +   /* Reuse the prop because blah */
> +   connector->max_bpc_property =
> +   intel_dp->attached_connector->base.max_bpc_property;
> drm_connector_attach_max_bpc_property(connector, 6, 12);

I'd prefer to address this separately, if that's alright.
It isn't related to this series, and no new warnings are introduced by
this either.

Leo

> 
> 
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[PATCH] drm/amdkfd: Fix byte align on VegaM

[Russell, Kent]

This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
adev->asic_type != CHIP_FIJI &&
adev->asic_type != CHIP_POLARIS10 &&
adev->asic_type != CHIP_POLARIS11 &&
-   adev->asic_type != CHIP_POLARIS12) ?
+   adev->asic_type != CHIP_POLARIS12 &&
+   adev->asic_type != CHIP_VEGAM) ?
VI_BO_SIZE_ALIGN : 1;
 
mapping_flags = AMDGPU_VM_PAGE_READABLE;
-- 
2.17.1

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[PATCH][next] drm/amd/display: fix a missing null check on a failed kzalloc

[Colin King]

From: Colin Ian King 

Currently the allocation of config may fail and a null pointer
dereference on config can occur.  Fix this by added a null
check on a failed allocation of config.

Addresses-Coverity: ("Dereference null return")
Fixes: c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig 
programming to stereo control interface")
Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 168f4a7dffdf..7cce2baec2af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1259,6 +1259,8 @@ bool dc_set_generic_gpio_for_stereo(bool enable,
struct gpio_generic_mux_config *config = kzalloc(sizeof(struct 
gpio_generic_mux_config),
   GFP_KERNEL);
 
+   if (!config)
+   return false;
pin_info = dal_gpio_get_generic_pin_info(gpio_service, GPIO_ID_GENERIC, 
0);
 
if (pin_info.mask == 0x || pin_info.offset == 0x) {
-- 
2.20.1

[PATCH -next] drm/amd/display: Make pow_buffer_ptr static

[YueHaibing]

Fix sparse warning:

drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:62:5:
 warning: symbol 'pow_buffer_ptr' was not declared. Should it be static?

Reported-by: Hulk Robot 
Signed-off-by: YueHaibing 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index ed894cd..5332168 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -59,7 +59,7 @@ static struct translate_from_linear_space_args 
scratch_gamma_args;
  */
 static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
 static struct fixed31_32 gamma_of_2; // 2^gamma
-int pow_buffer_ptr = -1;
+static int pow_buffer_ptr = -1;
 
 static const int32_t gamma_numerator01[] = { 31308,18, 0};
 static const int32_t gamma_numerator02[] = { 12920,4500,   0};
-- 
2.7.4

Re: [PATCH 2/2] drm/amd/powerplay: some cosmetic fixes

[Deucher, Alexander]

Series is:
Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Evan Quan 

Sent: Tuesday, July 23, 2019 4:41 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Quan, Evan 
Subject: [PATCH 2/2] drm/amd/powerplay: some cosmetic fixes

Drop redundant check, duplicate check, duplicate setting
and fix the return value.

Change-Id: I04171bcac82f17152371d05e6958d4fc072c0f6b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 33 +++---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 30 
 2 files changed, 28 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..aad3e105901b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -367,13 +367,6 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
  (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 return -EINVAL;

-   if (!amdgpu_sriov_vf(adev)) {
-   if (is_support_sw_smu(adev))
-   current_level = smu_get_performance_level(&adev->smu);
-   else if (adev->powerplay.pp_funcs->get_performance_level)
-   current_level = amdgpu_dpm_get_performance_level(adev);
-   }
-
 if (strncmp("low", buf, strlen("low")) == 0) {
 level = AMD_DPM_FORCED_LEVEL_LOW;
 } else if (strncmp("high", buf, strlen("high")) == 0) {
@@ -397,17 +390,23 @@ static ssize_t 
amdgpu_set_dpm_forced_performance_level(struct device *dev,
 goto fail;
 }

-if (amdgpu_sriov_vf(adev)) {
-if (amdgim_is_hwperf(adev) &&
-adev->virt.ops->force_dpm_level) {
-mutex_lock(&adev->pm.mutex);
-adev->virt.ops->force_dpm_level(adev, level);
-mutex_unlock(&adev->pm.mutex);
-return count;
-} else {
-return -EINVAL;
+   /* handle sriov case here */
+   if (amdgpu_sriov_vf(adev)) {
+   if (amdgim_is_hwperf(adev) &&
+   adev->virt.ops->force_dpm_level) {
+   mutex_lock(&adev->pm.mutex);
+   adev->virt.ops->force_dpm_level(adev, level);
+   mutex_unlock(&adev->pm.mutex);
+   return count;
+   } else {
+   return -EINVAL;
 }
-}
+   }
+
+   if (is_support_sw_smu(adev))
+   current_level = smu_get_performance_level(&adev->smu);
+   else if (adev->powerplay.pp_funcs->get_performance_level)
+   current_level = amdgpu_dpm_get_performance_level(adev);

 if (current_level == level)
 return count;
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 266614e27392..a92d13b513da 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1398,6 +1398,7 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,

 if (!smu->pm_enabled)
 return -EINVAL;
+
 if (!skip_display_settings) {
 ret = smu_display_config_changed(smu);
 if (ret) {
@@ -1406,8 +1407,6 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
 }
 }

-   if (!smu->pm_enabled)
-   return -EINVAL;
 ret = smu_apply_clocks_adjust_rules(smu);
 if (ret) {
 pr_err("Failed to apply clocks adjust rules!");
@@ -1426,9 +1425,14 @@ int smu_adjust_power_state_dynamic(struct smu_context 
*smu,
 ret = smu_asic_set_performance_level(smu, level);
 if (ret) {
 ret = smu_default_set_performance_level(smu, level);
+   if (ret) {
+   pr_err("Failed to set performance level!");
+   return ret;
+   }
 }
-   if (!ret)
-   smu_dpm_ctx->dpm_level = level;
+
+   /* update the saved copy */
+   smu_dpm_ctx->dpm_level = level;
 }

 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
@@ -1487,28 +1491,18 @@ enum amd_dpm_forced_level 
smu_get_performance_level(struct smu_context *smu)

 int smu_force_performance_level(struct smu_context *smu, enum 
amd_dpm_forced_level level)
 {
-   int ret = 0;
-   int i;
 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+   int ret = 0;

 if (!smu_dpm_ctx->dpm_context)
 return -EINVAL;

-   for (i = 0; i < smu->adev->num_ip_blocks; i++) {
-   if (smu->adev->ip_blocks[i].version->type == 
AMD_IP_BLOCK_TYPE_SMC)
- 

Re: [PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

[Deucher, Alexander]

Looks good to me.

Acked-by: Alex Deucher 

From: Wang, Kevin(Yang) 
Sent: Tuesday, July 23, 2019 5:43 AM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org 
; Deucher, Alexander 
Subject: Re: [PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu


it looks fine for me,

please @Deucher, Alexander double check 
confirm.

Reviewed-by: Kevin Wang 

Best Regards,
Kevin


From: amd-gfx  on behalf of Kenneth Feng 

Sent: Tuesday, July 23, 2019 5:39 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/powerplay: change smu_read_sensor sequence in smu

change the smu_read_sensor sequence to:

asic specific sensor read -> smu v11 specific sensor read -> smu v11 common 
sensor read

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 8 
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 -
 5 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a8..8ff18c8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -315,6 +315,9 @@ int smu_common_read_sensor(struct smu_context *smu, enum 
amd_pp_sensors sensor,
 {
 int ret = 0;

+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
 *((uint32_t *)data) = smu->pstate_sclk;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b702c9e..fabb373 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -819,9 +819,9 @@ struct smu_funcs
 #define smu_start_thermal_control(smu) \
 ((smu)->funcs->start_thermal_control? 
(smu)->funcs->start_thermal_control((smu)) : 0)
 #define smu_read_sensor(smu, sensor, data, size) \
-   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : 0)
-#define smu_asic_read_sensor(smu, sensor, data, size) \
 ((smu)->ppt_funcs->read_sensor? (smu)->ppt_funcs->read_sensor((smu), 
(sensor), (data), (size)) : 0)
+#define smu_smc_read_sensor(smu, sensor, data, size) \
+   ((smu)->funcs->read_sensor? (smu)->funcs->read_sensor((smu), (sensor), 
(data), (size)) : -EINVAL)
 #define smu_get_power_profile_mode(smu, buf) \
 ((smu)->ppt_funcs->get_power_profile_mode ? 
(smu)->ppt_funcs->get_power_profile_mode((smu), buf) : 0)
 #define smu_set_power_profile_mode(smu, param, param_size) \
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bb..6409718 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1366,6 +1366,9 @@ static int navi10_read_sensor(struct smu_context *smu,
 struct smu_table_context *table_context = &smu->smu_table;
 PPTable_t *pptable = table_context->driver_pptable;

+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
 *(uint32_t *)data = pptable->FanMaximumRpm;
@@ -1387,7 +1390,7 @@ static int navi10_read_sensor(struct smu_context *smu,
 *size = 4;
 break;
 default:
-   return -EINVAL;
+   ret = smu_smc_read_sensor(smu, sensor, data, size);
 }

 return ret;
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index e3a1784..5267b68 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1267,6 +1267,10 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
  void *data, uint32_t *size)
 {
 int ret = 0;
+
+   if(!data || !size)
+   return -EINVAL;
+
 switch (sensor) {
 case AMDGPU_PP_SENSOR_GFX_MCLK:
 ret = smu_get_current_clk_freq(smu, SMU_UCLK, (uint32_t 
*)data);
@@ -1289,10 +1293,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
 break;
 }

-   /* try get sensor data by asic */
-   if (ret)
-   ret = smu_asic_read_sensor(smu, sensor, data, size);
-
 if (ret)
 *size = 0;

diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 9ead361..e864a54 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3163,6 +3163,9 @@ static int vega20_read_sensor(struct smu_context *smu,
 

Re: [PATCH] drm/amdkfd: Fix byte align on VegaM

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Tuesday, July 23, 2019 10:22 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Russell, Kent 
Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM

This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 adev->asic_type != CHIP_FIJI &&
 adev->asic_type != CHIP_POLARIS10 &&
 adev->asic_type != CHIP_POLARIS11 &&
-   adev->asic_type != CHIP_POLARIS12) ?
+   adev->asic_type != CHIP_POLARIS12 &&
+   adev->asic_type != CHIP_VEGAM) ?
 VI_BO_SIZE_ALIGN : 1;

 mapping_flags = AMDGPU_VM_PAGE_READABLE;
--
2.17.1

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RE: [PATCH] drm/amdkfd: Fix byte align on VegaM

[Russell, Kent]

I'll push this, I was just wondering if Felix could confirm if the TLB 
workaround was only for Tonga/Topaz, in which case we could check for that 
instead of having to expand the list in situations like this, to say "if 
FAMILY_VI && (TOPAZ || TONGA) then". That way it's explicitly applying the 
workaround to the affected ASICs instead of implicitly not-applying the 
workaround to unaffected ASICs.

Kent

From: Deucher, Alexander 
Sent: Tuesday, July 23, 2019 11:16 AM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM

Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Tuesday, July 23, 2019 10:22 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Russell, Kent mailto:kent.russ...@amd.com>>
Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM

This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell mailto:kent.russ...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 adev->asic_type != CHIP_FIJI &&
 adev->asic_type != CHIP_POLARIS10 &&
 adev->asic_type != CHIP_POLARIS11 &&
-   adev->asic_type != CHIP_POLARIS12) ?
+   adev->asic_type != CHIP_POLARIS12 &&
+   adev->asic_type != CHIP_VEGAM) ?
 VI_BO_SIZE_ALIGN : 1;

 mapping_flags = AMDGPU_VM_PAGE_READABLE;
--
2.17.1

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Re: [PATCH v4 14/23] drm/tilcdc: Provide ddc symlink in connector sysfs directory

[Sam Ravnborg]

Hi Andrej.

On Tue, Jul 23, 2019 at 02:44:50PM +0200, Andrzej Pietrasiewicz wrote:
> Hi Sam,
> 
> W dniu 23.07.2019 o 11:05, Sam Ravnborg pisze:
> > Hi Andrzej
> > 
> > On Thu, Jul 11, 2019 at 01:26:41PM +0200, Andrzej Pietrasiewicz wrote:
> > > Use the ddc pointer provided by the generic connector.
> > > 
> > > Signed-off-by: Andrzej Pietrasiewicz 
> > > ---
> > >   drivers/gpu/drm/tilcdc/tilcdc_tfp410.c | 1 +
> > >   1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c 
> > > b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> > > index 62d014c20988..c373edb95666 100644
> > > --- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> > > +++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
> > > @@ -219,6 +219,7 @@ static struct drm_connector 
> > > *tfp410_connector_create(struct drm_device *dev,
> > >   tfp410_connector->mod = mod;
> > >   connector = &tfp410_connector->base;
> > > + connector->ddc = mod->i2c;
> > >   drm_connector_init(dev, connector, &tfp410_connector_funcs,
> > >   DRM_MODE_CONNECTOR_DVID);
> > 
> > When reading this code, it looks strange that we set connector->ddc
> > *before* the call to init the connector.
> > One could risk that drm_connector_init() used memset(..) to clear all
> > fields or so, and it would break this order.
> 
> I verified the code of drm_connector_init() and cannot find any memset()
> invocations there. What is your actual concern?
My concern is that drm_connector_init() maybe sometime in the future
will init all fileds in drm_connector, so we loose any assingments
done to drm_connector from *before* we called the init function.

Moving the assignment to after drm_connector_init() would not
let us depend on the actual implmentation of drm_connector_init().

Sam
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[PATCH 0/3] Enable Scatter Gather for Picasso.

[Andrey Grodzovsky]

This series enables S/G for Picasso.
First 2 patches fix a hard hang introduced by placing the display
BO in GTT memory because of HW issues with cached mappings
and the third patch enables S/G.

Andrey Grodzovsky (2):
  drm/amdgpu: Fix hard hang for S/G display BOs.
  drm/amd/display: Only allow s/g when USWC flag is set.

Shirish S (1):
  drm/amd: enable S/G for RAVEN chip

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 14 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  4 +++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 ++--
 4 files changed, 17 insertions(+), 7 deletions(-)

-- 
2.7.4

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[PATCH 2/3] drm/amd/display: Only allow s/g when USWC flag is set.

[Andrey Grodzovsky]

This verifies we don't casue HW hang in case this flag is missing.

Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Alex Deucher 
Tested-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9ef7854..2d50eea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4413,7 +4413,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane 
*plane,
return r;
}
 
-   if (plane->type != DRM_PLANE_TYPE_CURSOR)
+   if (plane->type != DRM_PLANE_TYPE_CURSOR && (rbo->flags & 
AMDGPU_GEM_CREATE_CPU_GTT_USWC))
domain = amdgpu_display_supported_domains(adev);
else
domain = AMDGPU_GEM_DOMAIN_VRAM;
-- 
2.7.4

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[PATCH 1/3] drm/amdgpu: Fix hard hang for S/G display BOs.

[Andrey Grodzovsky]

HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.

Suggested-by: Alex Deucher 
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Alex Deucher 
Tested-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 14 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  4 +++-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index e476092..acc45125 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -137,14 +137,14 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
  fb_tiled);
domain = amdgpu_display_supported_domains(adev);
-
height = ALIGN(mode_cmd->height, 8);
size = mode_cmd->pitches[0] * height;
aligned_size = ALIGN(size, PAGE_SIZE);
ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-  AMDGPU_GEM_CREATE_VRAM_CLEARED,
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+  AMDGPU_GEM_CREATE_VRAM_CLEARED|
+  AMDGPU_GEM_CREATE_CPU_GTT_USWC,
   ttm_bo_type_kernel, NULL, &gobj);
if (ret) {
pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
@@ -166,6 +166,14 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
dev_err(adev->dev, "FB failed to set tiling flags\n");
}
 
+   /*
+* If the AMDGPU_GEM_CREATE_CPU_GTT_USWC flag was removed during BO
+* creation it means that USWC is not supported for this board and
+* so to avoid hang caused by placement of scanout BO in GTT on certain
+* APUs and still light up, force the BO placement to VRAM.
+*/
+   if (abo->flags & ~AMDGPU_GEM_CREATE_CPU_GTT_USWC)
+   domain  = AMDGPU_GEM_DOMAIN_VRAM;
 
ret = amdgpu_bo_pin(abo, domain);
if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 2cead5a..b3b3b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -743,7 +743,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+   AMDGPU_GEM_CREATE_CPU_GTT_USWC;
u32 domain;
int r;
 
@@ -761,6 +762,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
args->size = ALIGN(args->size, PAGE_SIZE);
domain = amdgpu_bo_get_preferred_pin_domain(adev,
amdgpu_display_supported_domains(adev));
+
r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
 ttm_bo_type_device, NULL, &gobj);
if (r)
-- 
2.7.4

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[PATCH 3/3] drm/amd: enable S/G for RAVEN chip

[Andrey Grodzovsky]

From: Shirish S 

enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain

Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 2 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 767ee699..3d04730 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -498,7 +498,7 @@ uint32_t amdgpu_display_supported_domains(struct 
amdgpu_device *adev)
uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 
 #if defined(CONFIG_DRM_AMD_DC)
-   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
+   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
adev->flags & AMD_IS_APU &&
amdgpu_device_asic_has_dc_support(adev->asic_type))
domain |= AMDGPU_GEM_DOMAIN_GTT;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2d50eea..a8224a7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -686,7 +686,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 */
if (adev->flags & AMD_IS_APU &&
adev->asic_type >= CHIP_CARRIZO &&
-   adev->asic_type < CHIP_RAVEN)
+   adev->asic_type <= CHIP_RAVEN)
init_data.flags.gpu_vm_support = true;
 
if (amdgpu_dc_feature_mask & DC_FBC_MASK)
-- 
2.7.4

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Re: [PATCH 0/3] Enable Scatter Gather for Picasso.

[Koenig, Christian]

Series is Reviewed-by: Christian König 

Am 23.07.19 um 18:04 schrieb Andrey Grodzovsky:
> This series enables S/G for Picasso.
> First 2 patches fix a hard hang introduced by placing the display
> BO in GTT memory because of HW issues with cached mappings
> and the third patch enables S/G.
>
> Andrey Grodzovsky (2):
>drm/amdgpu: Fix hard hang for S/G display BOs.
>drm/amd/display: Only allow s/g when USWC flag is set.
>
> Shirish S (1):
>drm/amd: enable S/G for RAVEN chip
>
>   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c| 14 +++---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  4 +++-
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  4 ++--
>   4 files changed, 17 insertions(+), 7 deletions(-)
>

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RE: [PATCH 2/3] drm/amdgpu: add perfmon and fica atomics for df

[Russell, Kent]

Reviewed-By: Kent Russell 

 Kent

-Original Message-
From: amd-gfx  On Behalf Of Kim, Jonathan
Sent: Tuesday, July 16, 2019 1:12 PM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 2/3] drm/amdgpu: add perfmon and fica atomics for df

Note patch 1 sent to internal amd mailing list for review.

-Original Message-
From: Kim, Jonathan 
Sent: Tuesday, July 16, 2019 1:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan ; Kim, Jonathan 
Subject: [PATCH 2/3] drm/amdgpu: add perfmon and fica atomics for df

adding perfmon and fica atomic operations to adhere to data fabrics finite 
state machine requirements for indirect register access.

Change-Id: I2ab17fd59d566b4251c9a9d0e67b897b8c221249
Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   3 +
 drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 202 +--
 2 files changed, 128 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2cdf46bbeddf..77ca194b13d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -708,6 +708,9 @@ struct amdgpu_df_funcs {
 int is_disable);
void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
 uint64_t *count);
+   uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
+   void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
+uint32_t ficadl_val, uint32_t ficadh_val);
 };
 /* Define the HW IP blocks will be used in driver , add more if necessary */  
enum amd_hw_ip_block_type { diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c 
b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
index ef6e91f9f51c..5850c8e34caa 100644
--- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
@@ -93,6 +93,96 @@ const struct attribute_group *df_v3_6_attr_groups[] = {
NULL
 };
 
+static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev,
+uint32_t ficaa_val)
+{
+   unsigned long flags, address, data;
+   uint32_t ficadl_val, ficadh_val;
+
+   address = adev->nbio_funcs->get_pcie_index_offset(adev);
+   data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+   spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+   WREG32(data, ficaa_val);
+
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
+   ficadl_val = RREG32(data);
+
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+   ficadh_val = RREG32(data);
+
+   spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+
+   return (((ficadh_val & 0x) << 32) | ficadl_val); }
+
+static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val,
+uint32_t ficadl_val, uint32_t ficadh_val) {
+   unsigned long flags, address, data;
+
+   address = adev->nbio_funcs->get_pcie_index_offset(adev);
+   data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+   spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3);
+   WREG32(data, ficaa_val);
+
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3);
+   WREG32(data, ficadl_val);
+
+   WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3);
+   WREG32(data, ficadh_val);
+
+   spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); }
+
+/*
+ * df_v3_6_perfmon_rreg - read perfmon lo and hi
+ *
+ * required to be atomic.  no mmio method provided so subsequent reads 
+for lo
+ * and hi require to preserve df finite state machine  */ static void 
+df_v3_6_perfmon_rreg(struct amdgpu_device *adev,
+   uint32_t lo_addr, uint32_t *lo_val,
+   uint32_t hi_addr, uint32_t *hi_val) {
+   unsigned long flags, address, data;
+
+   address = adev->nbio_funcs->get_pcie_index_offset(adev);
+   data = adev->nbio_funcs->get_pcie_data_offset(adev);
+
+   spin_lock_irqsave(&adev->pcie_idx_lock, flags);
+   WREG32(address, lo_addr);
+   *lo_val = RREG32(data);
+   WREG32(address, hi_addr);
+   *hi_val = RREG32(data);
+   spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); }
+
+/*
+ * df_v3_6_perfmon_wreg - write to perfmon lo and hi
+ *
+ * required to be atomic.  no mmio method provided so subsequent reads 
+after
+ * data writes cannot occur to preserve data fabrics finite state machine.
+ */
+static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr,
+   uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) 
{
+   unsigned long flags, address, data;
+
+   address = adev->nbio_funcs->get_pcie_index_offset(adev);
+   data = adev->nbi

Re: [PATCH 1/3] drm/amdgpu: Fix hard hang for S/G display BOs.

[Michel Dänzer]

On 2019-07-23 6:04 p.m., Andrey Grodzovsky wrote:
> HW requires for caching to be unset for scanout BO
> mappings when the BO placement is in GTT memory.
> Usually the flag to unset is passed from user mode
> but for FB mode this was missing.
> 
> Suggested-by: Alex Deucher 
> Signed-off-by: Andrey Grodzovsky 
> Reviewed-by: Alex Deucher 
> Tested-by: Shirish S 
> ---
>  [...]
> 
> @@ -166,6 +166,14 @@ static int amdgpufb_create_pinned_object(struct 
> amdgpu_fbdev *rfbdev,
>   dev_err(adev->dev, "FB failed to set tiling flags\n");
>   }
>  
> + /*
> +  * If the AMDGPU_GEM_CREATE_CPU_GTT_USWC flag was removed during BO
> +  * creation it means that USWC is not supported for this board and
> +  * so to avoid hang caused by placement of scanout BO in GTT on certain
> +  * APUs and still light up, force the BO placement to VRAM.
> +  */
> + if (abo->flags & ~AMDGPU_GEM_CREATE_CPU_GTT_USWC)
> + domain  = AMDGPU_GEM_DOMAIN_VRAM;

The comment sounds like you meant

if (!(abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC))
domain  = AMDGPU_GEM_DOMAIN_VRAM;

?

Anyway, this should be handled in amdgpu_display_supported_domains
instead (e.g. by not allowing GTT if CONFIG_X86_32 is defined),
otherwise the BO could still be pinned to GTT later.


> @@ -761,6 +762,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
>   args->size = ALIGN(args->size, PAGE_SIZE);
>   domain = amdgpu_bo_get_preferred_pin_domain(adev,
>   amdgpu_display_supported_domains(adev));
> +
>   r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
>ttm_bo_type_device, NULL, &gobj);
>   if (r)
> 

Drop this hunk with only whitespace changes.


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RE: [PATCH 3/3] drm/amdgpu: adding xgmi error monitoring

[Russell, Kent]

Reviewed-By: Kent Russell 

 Kent

-Original Message-
From: amd-gfx  On Behalf Of Kim, Jonathan
Sent: Tuesday, July 16, 2019 1:12 PM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH 3/3] drm/amdgpu: adding xgmi error monitoring

Note patch 1 sent to internal amd mailing list for review.

-Original Message-
From: Kim, Jonathan 
Sent: Tuesday, July 16, 2019 1:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Kim, Jonathan ; Kim, Jonathan 
Subject: [PATCH 3/3] drm/amdgpu: adding xgmi error monitoring

monitor xgmi errors via mc pie status through fica registers.

Change-Id: Id80b6c2f635a294afe343cf55a03902e9a1787a5
Signed-off-by: Jonathan Kim 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 38 ++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
index d11eba09eadd..4b87fda15ac5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
@@ -25,7 +25,7 @@
 #include "amdgpu.h"
 #include "amdgpu_xgmi.h"
 #include "amdgpu_smu.h"
-
+#include "df/df_3_6_offset.h"
 
 static DEFINE_MUTEX(xgmi_mutex);
 
@@ -131,9 +131,37 @@ static ssize_t amdgpu_xgmi_show_device_id(struct device 
*dev,
 
 }
 
+#define AMDGPU_XGMI_SET_FICAA(o)   ((o) | 0x456801)
+static ssize_t amdgpu_xgmi_show_error(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+   struct drm_device *ddev = dev_get_drvdata(dev);
+   struct amdgpu_device *adev = ddev->dev_private;
+   uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
+   uint64_t fica_out;
+   unsigned int error_count = 0;
+
+   ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
+   ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
 
-static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
+   fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_ctl_in);
+   if (fica_out != 0x1f)
+   pr_err("xGMI error counters not enabled!\n");
+
+   fica_out = adev->df_funcs->get_fica(adev, ficaa_pie_status_in);
+
+   if ((fica_out & 0x) == 2)
+   error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
 
+   adev->df_funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
+
+   return snprintf(buf, PAGE_SIZE, "%d\n", error_count); }
+
+
+static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, 
+NULL); static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, 
+NULL);
 
 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
 struct amdgpu_hive_info *hive)
@@ -148,6 +176,12 @@ static int amdgpu_xgmi_sysfs_add_dev_info(struct 
amdgpu_device *adev,
return ret;
}
 
+   /* Create xgmi error file */
+   ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
+   if (ret)
+   pr_err("failed to create xgmi_error\n");
+
+
/* Create sysfs link to hive info folder on the first device */
if (adev != hive->adev) {
ret = sysfs_create_link(&adev->dev->kobj, hive->kobj,
--
2.17.1

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Re: [PATCH 2/3] drm/amd/display: Only allow s/g when USWC flag is set.

[Michel Dänzer]

On 2019-07-23 6:04 p.m., Andrey Grodzovsky wrote:
> This verifies we don't casue HW hang in case this flag is missing.
> 
> Signed-off-by: Andrey Grodzovsky 
> Reviewed-by: Alex Deucher 
> Tested-by: Shirish S 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9ef7854..2d50eea 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4413,7 +4413,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane 
> *plane,
>   return r;
>   }
>  
> - if (plane->type != DRM_PLANE_TYPE_CURSOR)
> + if (plane->type != DRM_PLANE_TYPE_CURSOR && (rbo->flags & 
> AMDGPU_GEM_CREATE_CPU_GTT_USWC))
>   domain = amdgpu_display_supported_domains(adev);
>   else
>   domain = AMDGPU_GEM_DOMAIN_VRAM;
> 

amdgpu_display_supported_domains() is used in other places as well, so
this should be handled inside it instead.


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[PATCH 1/3] drm/amdgpu/powerplay/vega20: call PrepareMp1ForUnload in power_off_asic

[Alex Deucher]

Needed to make sure the smu is idle when resetting. This fixes
sporatic failures with GPU reset.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index f27c6fbb192e..e16d6654692f 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3764,6 +3764,11 @@ static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
);
data->water_marks_bitmap &= ~(WaterMarksLoaded);
 
+   PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
+   PPSMC_MSG_PrepareMp1ForUnload)) == 0,
+   "[PrepareMp1ForUnload] Failed!",
+   return result);
+
return result;
 }
 
-- 
2.20.1

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[PATCH 2/3] drm/amdgpu/powerplay/vega10: call PrepareMp1ForUnload in power_off_asic

[Alex Deucher]

Needed to make sure the smu is idle when resetting. This may fix
sporatic failures with GPU reset.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 1d9bb29adaef..a6066d92de78 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4740,6 +4740,11 @@ static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
);
data->water_marks_bitmap &= ~(WaterMarksLoaded);
 
+   PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
+   PPSMC_MSG_PrepareMp1ForUnload)) == 0,
+   "[PrepareMp1ForUnload] Failed!",
+   return result);
+
return result;
 }
 
-- 
2.20.1

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[PATCH 3/3] drm/amdgpu/powerplay/vega12: call PrepareMp1ForUnload in power_off_asic

[Alex Deucher]

Needed to make sure the smu is idle when resetting. This may fix
sporatic failures with GPU reset.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index efb6d3762feb..3d3504411b63 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2468,6 +2468,11 @@ static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
);
data->water_marks_bitmap &= ~(WaterMarksLoaded);
 
+   PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
+   PPSMC_MSG_PrepareMp1ForUnload)) == 0,
+   "[PrepareMp1ForUnload] Failed!",
+   return result);
+
return result;
 }
 
-- 
2.20.1

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Re: Re: kernel panic: stack is corrupted in pointer

[syzbot]

Dmitry Vyukov wrote:

On Wed, Jul 17, 2019 at 10:58 AM syzbot
 wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:1438cde7 Add linux-next specific files for 20190716
> git tree:   linux-next
> console output:  
https://syzkaller.appspot.com/x/log.txt?x=1398805860
> kernel config:   
https://syzkaller.appspot.com/x/.config?x=3430a151e1452331
> dashboard link:  
https://syzkaller.appspot.com/bug?extid=79f5f028005a77ecb6bb

> compiler:   gcc (GCC) 9.0.0 20181231 (experimental)
> syz repro:   
https://syzkaller.appspot.com/x/repro.syz?x=111fc8afa0



 From the repro it looks like the same bpf stack overflow bug. +John
We need to dup them onto some canonical report for this bug, or this
becomes unmanageable.


Fixes in bpf tree should fix this. Hopefully, we will squash this once  
fixes

percolate up.



#syz test: git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git


">" does not look like a valid git branch or commit.




#syz dup: kernel panic: corrupted stack end in dput



> The bug was bisected to:
>
> commit 96a5d8d4915f3e241ebb48d5decdd110ab9c7dcf
> Author: Leo Liu 
> Date:   Fri Jul 13 15:26:28 2018 +
>
>  drm/amdgpu: Make sure IB tests flushed after IP resume
>
> bisection log:   
https://syzkaller.appspot.com/x/bisect.txt?x=14a4620060
> final crash: 
https://syzkaller.appspot.com/x/report.txt?x=16a4620060
> console output:  
https://syzkaller.appspot.com/x/log.txt?x=12a4620060

>
> IMPORTANT: if you fix the bug, please add the following tag to the  
commit:

> Reported-by: syzbot+79f5f028005a77ecb...@syzkaller.appspotmail.com
> Fixes: 96a5d8d4915f ("drm/amdgpu: Make sure IB tests flushed after IP
> resume")
>
> Kernel panic - not syncing: stack-protector: Kernel stack is corrupted  
in:

> pointer+0x702/0x750 lib/vsprintf.c:2187
> Shutting down cpus with NMI
> Kernel Offset: disabled
>
>
> ---
> This bug is generated by a bot. It may contain errors.
> See https://goo.gl/tpsmEJ for more information about syzbot.
> syzbot engineers can be reached at syzkal...@googlegroups.com.
>
> syzbot will keep track of this bug report. See:
> https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
> For information about bisection process see:  
https://goo.gl/tpsmEJ#bisection

> syzbot can test patches for this bug, for details see:
> https://goo.gl/tpsmEJ#testing-patches

Re: [PATCH 1/3] drm/amdgpu: Fix hard hang for S/G display BOs.

[Grodzovsky, Andrey]

On 7/23/19 12:18 PM, Michel Dänzer wrote:
> On 2019-07-23 6:04 p.m., Andrey Grodzovsky wrote:
>> HW requires for caching to be unset for scanout BO
>> mappings when the BO placement is in GTT memory.
>> Usually the flag to unset is passed from user mode
>> but for FB mode this was missing.
>>
>> Suggested-by: Alex Deucher 
>> Signed-off-by: Andrey Grodzovsky 
>> Reviewed-by: Alex Deucher 
>> Tested-by: Shirish S 
>> ---
>>   [...]
>>
>> @@ -166,6 +166,14 @@ static int amdgpufb_create_pinned_object(struct 
>> amdgpu_fbdev *rfbdev,
>>  dev_err(adev->dev, "FB failed to set tiling flags\n");
>>  }
>>   
>> +/*
>> + * If the AMDGPU_GEM_CREATE_CPU_GTT_USWC flag was removed during BO
>> + * creation it means that USWC is not supported for this board and
>> + * so to avoid hang caused by placement of scanout BO in GTT on certain
>> + * APUs and still light up, force the BO placement to VRAM.
>> + */
>> +if (abo->flags & ~AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>> +domain  = AMDGPU_GEM_DOMAIN_VRAM;
> The comment sounds like you meant
>
>   if (!(abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC))
>   domain  = AMDGPU_GEM_DOMAIN_VRAM;
>
> ?


Yes, not sure how this happened to me...


>
> Anyway, this should be handled in amdgpu_display_supported_domains
> instead (e.g. by not allowing GTT if CONFIG_X86_32 is defined),


We have drm_arch_can_wc_memory function to cover all the cases when USWC 
mapping is not allowed, why the CONFIG_X86_32 here ?


> otherwise the BO could still be pinned to GTT later.

The only other later place I know is dm_plane_helper_prepare_fb of which 
I take care in patch 3. What other places you have in mind ?


Andrey


>
>
>> @@ -761,6 +762,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
>>  args->size = ALIGN(args->size, PAGE_SIZE);
>>  domain = amdgpu_bo_get_preferred_pin_domain(adev,
>>  amdgpu_display_supported_domains(adev));
>> +
>>  r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
>>   ttm_bo_type_device, NULL, &gobj);
>>  if (r)
>>
> Drop this hunk with only whitespace changes.
>
>
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Re: Re: kernel panic: stack is corrupted in pointer

[John Fastabend]

syzbot wrote:
> > Dmitry Vyukov wrote:
> >> On Wed, Jul 17, 2019 at 10:58 AM syzbot
> >>  wrote:
> >> >
> >> > Hello,
> >> >
> >> > syzbot found the following crash on:
> >> >
> >> > HEAD commit:1438cde7 Add linux-next specific files for 20190716
> >> > git tree:   linux-next
> >> > console output:  
> >> https://syzkaller.appspot.com/x/log.txt?x=1398805860
> >> > kernel config:   
> >> https://syzkaller.appspot.com/x/.config?x=3430a151e1452331
> >> > dashboard link:  
> >> https://syzkaller.appspot.com/bug?extid=79f5f028005a77ecb6bb
> >> > compiler:   gcc (GCC) 9.0.0 20181231 (experimental)
> >> > syz repro:   
> >> https://syzkaller.appspot.com/x/repro.syz?x=111fc8afa0
> 
> >>  From the repro it looks like the same bpf stack overflow bug. +John
> >> We need to dup them onto some canonical report for this bug, or this
> >> becomes unmanageable.
> 
> > Fixes in bpf tree should fix this. Hopefully, we will squash this once  
> > fixes
> > percolate up.
> 
> > #syz test: git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git
> 
> ">" does not look like a valid git branch or commit.
> 

try again,

#syz test: git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git master

[PATCH v19 01/15] arm64: untag user pointers in access_ok and __uaccess_mask_ptr

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

copy_from_user (and a few other similar functions) are used to copy data
from user memory into the kernel memory or vice versa. Since a user can
provided a tagged pointer to one of the syscalls that use copy_from_user,
we need to correctly handle such pointers.

Do this by untagging user pointers in access_ok and in __uaccess_mask_ptr,
before performing access validity checks.

Note, that this patch only temporarily untags the pointers to perform the
checks, but then passes them as is into the kernel internals.

Reviewed-by: Vincenzo Frascino 
Reviewed-by: Kees Cook 
Reviewed-by: Catalin Marinas 
Signed-off-by: Andrey Konovalov 
---
 arch/arm64/include/asm/uaccess.h | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 5a1c32260c1f..a138e3b4f717 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -62,6 +62,8 @@ static inline unsigned long __range_ok(const void __user 
*addr, unsigned long si
 {
unsigned long ret, limit = current_thread_info()->addr_limit;
 
+   addr = untagged_addr(addr);
+
__chk_user_ptr(addr);
asm volatile(
// A + B <= C + 1 for all A,B,C, in four easy steps:
@@ -215,7 +217,8 @@ static inline void uaccess_enable_not_uao(void)
 
 /*
  * Sanitise a uaccess pointer such that it becomes NULL if above the
- * current addr_limit.
+ * current addr_limit. In case the pointer is tagged (has the top byte set),
+ * untag the pointer before checking.
  */
 #define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
 static inline void __user *__uaccess_mask_ptr(const void __user *ptr)
@@ -223,10 +226,11 @@ static inline void __user *__uaccess_mask_ptr(const void 
__user *ptr)
void __user *safe_ptr;
 
asm volatile(
-   "   bicsxzr, %1, %2\n"
+   "   bicsxzr, %3, %2\n"
"   csel%0, %1, xzr, eq\n"
: "=&r" (safe_ptr)
-   : "r" (ptr), "r" (current_thread_info()->addr_limit)
+   : "r" (ptr), "r" (current_thread_info()->addr_limit),
+ "r" (untagged_addr(ptr))
: "cc");
 
csdb();
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 00/15] arm64: untag user pointers passed to the kernel

[Andrey Konovalov]

=== Overview

arm64 has a feature called Top Byte Ignore, which allows to embed pointer
tags into the top byte of each pointer. Userspace programs (such as
HWASan, a memory debugging tool [1]) might use this feature and pass
tagged user pointers to the kernel through syscalls or other interfaces.

Right now the kernel is already able to handle user faults with tagged
pointers, due to these patches:

1. 81cddd65 ("arm64: traps: fix userspace cache maintenance emulation on a
 tagged pointer")
2. 7dcd9dd8 ("arm64: hw_breakpoint: fix watchpoint matching for tagged
  pointers")
3. 276e9327 ("arm64: entry: improve data abort handling of tagged
  pointers")

This patchset extends tagged pointer support to syscall arguments.

As per the proposed ABI change [3], tagged pointers are only allowed to be
passed to syscalls when they point to memory ranges obtained by anonymous
mmap() or sbrk() (see the patchset [3] for more details).

For non-memory syscalls this is done by untaging user pointers when the
kernel performs pointer checking to find out whether the pointer comes
from userspace (most notably in access_ok). The untagging is done only
when the pointer is being checked, the tag is preserved as the pointer
makes its way through the kernel and stays tagged when the kernel
dereferences the pointer when perfoming user memory accesses.

The mmap and mremap (only new_addr) syscalls do not currently accept
tagged addresses. Architectures may interpret the tag as a background
colour for the corresponding vma.

Other memory syscalls (mprotect, etc.) don't do user memory accesses but
rather deal with memory ranges, and untagged pointers are better suited to
describe memory ranges internally. Thus for memory syscalls we untag
pointers completely when they enter the kernel.

=== Other approaches

One of the alternative approaches to untagging that was considered is to
completely strip the pointer tag as the pointer enters the kernel with
some kind of a syscall wrapper, but that won't work with the countless
number of different ioctl calls. With this approach we would need a custom
wrapper for each ioctl variation, which doesn't seem practical.

An alternative approach to untagging pointers in memory syscalls prologues
is to inspead allow tagged pointers to be passed to find_vma() (and other
vma related functions) and untag them there. Unfortunately, a lot of
find_vma() callers then compare or subtract the returned vma start and end
fields against the pointer that was being searched. Thus this approach
would still require changing all find_vma() callers.

=== Testing

The following testing approaches has been taken to find potential issues
with user pointer untagging:

1. Static testing (with sparse [2] and separately with a custom static
   analyzer based on Clang) to track casts of __user pointers to integer
   types to find places where untagging needs to be done.

2. Static testing with grep to find parts of the kernel that call
   find_vma() (and other similar functions) or directly compare against
   vm_start/vm_end fields of vma.

3. Static testing with grep to find parts of the kernel that compare
   user pointers with TASK_SIZE or other similar consts and macros.

4. Dynamic testing: adding BUG_ON(has_tag(addr)) to find_vma() and running
   a modified syzkaller version that passes tagged pointers to the kernel.

Based on the results of the testing the requried patches have been added
to the patchset.

=== Notes

This patchset is meant to be merged together with "arm64 relaxed ABI" [3].

This patchset is a prerequisite for ARM's memory tagging hardware feature
support [4].

This patchset has been merged into the Pixel 2 & 3 kernel trees and is
now being used to enable testing of Pixel phones with HWASan.

Thanks!

[1] http://clang.llvm.org/docs/HardwareAssistedAddressSanitizerDesign.html

[2] 
https://github.com/lucvoo/sparse-dev/commit/5f960cb10f56ec2017c128ef9d16060e0145f292

[3] https://lkml.org/lkml/2019/6/12/745

[4] 
https://community.arm.com/processors/b/blog/posts/arm-a-profile-architecture-2018-developments-armv85a

=== History

Changes in v19:
- Rebased onto 7b5cf701 (5.3-rc1+).

Changes in v18:
- Reverted the selftest back to not using the LD_PRELOAD approach.
- Added prctl(PR_SET_TAGGED_ADDR_CTRL) call to the selftest.
- Reworded the patch descriptions to make them less oriented on arm64
  only.
- Catalin's patch: "I added a Kconfig option and dropped the prctl args
  zero check. There is some minor clean-up as well".

Changes in v17:
- The "uaccess: add noop untagged_addr definition" patch is dropped, as it
  was merged into upstream named as "uaccess: add noop untagged_addr
  definition".
- Merged "mm, arm64: untag user pointers in do_pages_move" into
  "mm, arm64: untag user pointers passed to memory syscalls".
- Added "arm64: Introduce prctl() options to control the tagged user
  addresses ABI" patch from Catalin.
- Add tags_lib.so to tools/testing/selftests/arm64

[PATCH v19 09/15] drm/amdgpu: untag user pointers

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

In amdgpu_gem_userptr_ioctl() and amdgpu_amdkfd_gpuvm.c/init_user_pages()
an MMU notifier is set up with a (tagged) userspace pointer. The untagged
address should be used so that MMU notifiers for the untagged address get
correctly matched up with the right BO. This patch untag user pointers in
amdgpu_gem_userptr_ioctl() for the GEM case and in amdgpu_amdkfd_gpuvm_
alloc_memory_of_gpu() for the KFD case. This also makes sure that an
untagged pointer is passed to amdgpu_ttm_tt_get_user_pages(), which uses
it for vma lookups.

Reviewed-by: Kees Cook 
Suggested-by: Felix Kuehling 
Acked-by: Felix Kuehling 
Signed-off-by: Andrey Konovalov 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c  | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 1d3ee9c42f7e..00468ebf8b76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1103,7 +1103,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
alloc_flags = 0;
if (!offset || !*offset)
return -EINVAL;
-   user_addr = *offset;
+   user_addr = untagged_addr(*offset);
} else if (flags & (ALLOC_MEM_FLAGS_DOORBELL |
ALLOC_MEM_FLAGS_MMIO_REMAP)) {
domain = AMDGPU_GEM_DOMAIN_GTT;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 939f8305511b..d7855842fd51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -291,6 +291,8 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
uint32_t handle;
int r;
 
+   args->addr = untagged_addr(args->addr);
+
if (offset_in_page(args->addr | args->size))
return -EINVAL;
 
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 15/15] selftests, arm64: add a selftest for passing tagged pointers to kernel

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

This patch adds a simple test, that calls the uname syscall with a
tagged user pointer as an argument. Without the kernel accepting tagged
user pointers the test fails with EFAULT.

Reviewed-by: Catalin Marinas 
Acked-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 tools/testing/selftests/arm64/.gitignore  |  1 +
 tools/testing/selftests/arm64/Makefile| 11 +++
 .../testing/selftests/arm64/run_tags_test.sh  | 12 
 tools/testing/selftests/arm64/tags_test.c | 29 +++
 4 files changed, 53 insertions(+)
 create mode 100644 tools/testing/selftests/arm64/.gitignore
 create mode 100644 tools/testing/selftests/arm64/Makefile
 create mode 100755 tools/testing/selftests/arm64/run_tags_test.sh
 create mode 100644 tools/testing/selftests/arm64/tags_test.c

diff --git a/tools/testing/selftests/arm64/.gitignore 
b/tools/testing/selftests/arm64/.gitignore
new file mode 100644
index ..e8fae8d61ed6
--- /dev/null
+++ b/tools/testing/selftests/arm64/.gitignore
@@ -0,0 +1 @@
+tags_test
diff --git a/tools/testing/selftests/arm64/Makefile 
b/tools/testing/selftests/arm64/Makefile
new file mode 100644
index ..a61b2e743e99
--- /dev/null
+++ b/tools/testing/selftests/arm64/Makefile
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0
+
+# ARCH can be overridden by the user for cross compiling
+ARCH ?= $(shell uname -m 2>/dev/null || echo not)
+
+ifneq (,$(filter $(ARCH),aarch64 arm64))
+TEST_GEN_PROGS := tags_test
+TEST_PROGS := run_tags_test.sh
+endif
+
+include ../lib.mk
diff --git a/tools/testing/selftests/arm64/run_tags_test.sh 
b/tools/testing/selftests/arm64/run_tags_test.sh
new file mode 100755
index ..745f11379930
--- /dev/null
+++ b/tools/testing/selftests/arm64/run_tags_test.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0
+
+echo ""
+echo "running tags test"
+echo ""
+./tags_test
+if [ $? -ne 0 ]; then
+   echo "[FAIL]"
+else
+   echo "[PASS]"
+fi
diff --git a/tools/testing/selftests/arm64/tags_test.c 
b/tools/testing/selftests/arm64/tags_test.c
new file mode 100644
index ..22a1b266e373
--- /dev/null
+++ b/tools/testing/selftests/arm64/tags_test.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define SHIFT_TAG(tag) ((uint64_t)(tag) << 56)
+#define SET_TAG(ptr, tag)  (((uint64_t)(ptr) & ~SHIFT_TAG(0xff)) | \
+   SHIFT_TAG(tag))
+
+int main(void)
+{
+   static int tbi_enabled = 0;
+   struct utsname *ptr, *tagged_ptr;
+   int err;
+
+   if (prctl(PR_SET_TAGGED_ADDR_CTRL, PR_TAGGED_ADDR_ENABLE, 0, 0, 0) == 0)
+   tbi_enabled = 1;
+   ptr = (struct utsname *)malloc(sizeof(*ptr));
+   if (tbi_enabled)
+   tagged_ptr = (struct utsname *)SET_TAG(ptr, 0x42);
+   err = uname(tagged_ptr);
+   free(ptr);
+
+   return err;
+}
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 07/15] fs/namespace: untag user pointers in copy_mount_options

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

In copy_mount_options a user address is being subtracted from TASK_SIZE.
If the address is lower than TASK_SIZE, the size is calculated to not
allow the exact_copy_from_user() call to cross TASK_SIZE boundary.
However if the address is tagged, then the size will be calculated
incorrectly.

Untag the address before subtracting.

Reviewed-by: Khalid Aziz 
Reviewed-by: Vincenzo Frascino 
Reviewed-by: Kees Cook 
Reviewed-by: Catalin Marinas 
Signed-off-by: Andrey Konovalov 
---
 fs/namespace.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/namespace.c b/fs/namespace.c
index 6464ea4acba9..b32eb26af8bf 100644
--- a/fs/namespace.c
+++ b/fs/namespace.c
@@ -2994,7 +2994,7 @@ void *copy_mount_options(const void __user * data)
 * the remainder of the page.
 */
/* copy_from_user cannot cross TASK_SIZE ! */
-   size = TASK_SIZE - (unsigned long)data;
+   size = TASK_SIZE - (unsigned long)untagged_addr(data);
if (size > PAGE_SIZE)
size = PAGE_SIZE;
 
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 12/15] media/v4l2-core: untag user pointers in videobuf_dma_contig_user_get

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

videobuf_dma_contig_user_get() uses provided user pointers for vma
lookups, which can only by done with untagged pointers.

Untag the pointers in this function.

Reviewed-by: Khalid Aziz 
Reviewed-by: Kees Cook 
Acked-by: Mauro Carvalho Chehab 
Signed-off-by: Andrey Konovalov 
---
 drivers/media/v4l2-core/videobuf-dma-contig.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c 
b/drivers/media/v4l2-core/videobuf-dma-contig.c
index 76b4ac7b1678..aeb2f497c683 100644
--- a/drivers/media/v4l2-core/videobuf-dma-contig.c
+++ b/drivers/media/v4l2-core/videobuf-dma-contig.c
@@ -157,6 +157,7 @@ static void videobuf_dma_contig_user_put(struct 
videobuf_dma_contig_memory *mem)
 static int videobuf_dma_contig_user_get(struct videobuf_dma_contig_memory *mem,
struct videobuf_buffer *vb)
 {
+   unsigned long untagged_baddr = untagged_addr(vb->baddr);
struct mm_struct *mm = current->mm;
struct vm_area_struct *vma;
unsigned long prev_pfn, this_pfn;
@@ -164,22 +165,22 @@ static int videobuf_dma_contig_user_get(struct 
videobuf_dma_contig_memory *mem,
unsigned int offset;
int ret;
 
-   offset = vb->baddr & ~PAGE_MASK;
+   offset = untagged_baddr & ~PAGE_MASK;
mem->size = PAGE_ALIGN(vb->size + offset);
ret = -EINVAL;
 
down_read(&mm->mmap_sem);
 
-   vma = find_vma(mm, vb->baddr);
+   vma = find_vma(mm, untagged_baddr);
if (!vma)
goto out_up;
 
-   if ((vb->baddr + mem->size) > vma->vm_end)
+   if ((untagged_baddr + mem->size) > vma->vm_end)
goto out_up;
 
pages_done = 0;
prev_pfn = 0; /* kill warning */
-   user_address = vb->baddr;
+   user_address = untagged_baddr;
 
while (pages_done < (mem->size >> PAGE_SHIFT)) {
ret = follow_pfn(vma, user_address, &this_pfn);
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 08/15] userfaultfd: untag user pointers

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

userfaultfd code use provided user pointers for vma lookups, which can
only by done with untagged pointers.

Untag user pointers in validate_range().

Reviewed-by: Mike Rapoport 
Reviewed-by: Vincenzo Frascino 
Reviewed-by: Catalin Marinas 
Reviewed-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 fs/userfaultfd.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/fs/userfaultfd.c b/fs/userfaultfd.c
index ccbdbd62f0d8..6284a4e719cb 100644
--- a/fs/userfaultfd.c
+++ b/fs/userfaultfd.c
@@ -1271,21 +1271,23 @@ static __always_inline void wake_userfault(struct 
userfaultfd_ctx *ctx,
 }
 
 static __always_inline int validate_range(struct mm_struct *mm,
- __u64 start, __u64 len)
+ __u64 *start, __u64 len)
 {
__u64 task_size = mm->task_size;
 
-   if (start & ~PAGE_MASK)
+   *start = untagged_addr(*start);
+
+   if (*start & ~PAGE_MASK)
return -EINVAL;
if (len & ~PAGE_MASK)
return -EINVAL;
if (!len)
return -EINVAL;
-   if (start < mmap_min_addr)
+   if (*start < mmap_min_addr)
return -EINVAL;
-   if (start >= task_size)
+   if (*start >= task_size)
return -EINVAL;
-   if (len > task_size - start)
+   if (len > task_size - *start)
return -EINVAL;
return 0;
 }
@@ -1335,7 +1337,7 @@ static int userfaultfd_register(struct userfaultfd_ctx 
*ctx,
goto out;
}
 
-   ret = validate_range(mm, uffdio_register.range.start,
+   ret = validate_range(mm, &uffdio_register.range.start,
 uffdio_register.range.len);
if (ret)
goto out;
@@ -1524,7 +1526,7 @@ static int userfaultfd_unregister(struct userfaultfd_ctx 
*ctx,
if (copy_from_user(&uffdio_unregister, buf, sizeof(uffdio_unregister)))
goto out;
 
-   ret = validate_range(mm, uffdio_unregister.start,
+   ret = validate_range(mm, &uffdio_unregister.start,
 uffdio_unregister.len);
if (ret)
goto out;
@@ -1675,7 +1677,7 @@ static int userfaultfd_wake(struct userfaultfd_ctx *ctx,
if (copy_from_user(&uffdio_wake, buf, sizeof(uffdio_wake)))
goto out;
 
-   ret = validate_range(ctx->mm, uffdio_wake.start, uffdio_wake.len);
+   ret = validate_range(ctx->mm, &uffdio_wake.start, uffdio_wake.len);
if (ret)
goto out;
 
@@ -1715,7 +1717,7 @@ static int userfaultfd_copy(struct userfaultfd_ctx *ctx,
   sizeof(uffdio_copy)-sizeof(__s64)))
goto out;
 
-   ret = validate_range(ctx->mm, uffdio_copy.dst, uffdio_copy.len);
+   ret = validate_range(ctx->mm, &uffdio_copy.dst, uffdio_copy.len);
if (ret)
goto out;
/*
@@ -1771,7 +1773,7 @@ static int userfaultfd_zeropage(struct userfaultfd_ctx 
*ctx,
   sizeof(uffdio_zeropage)-sizeof(__s64)))
goto out;
 
-   ret = validate_range(ctx->mm, uffdio_zeropage.range.start,
+   ret = validate_range(ctx->mm, &uffdio_zeropage.range.start,
 uffdio_zeropage.range.len);
if (ret)
goto out;
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 10/15] drm/radeon: untag user pointers in radeon_gem_userptr_ioctl

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

In radeon_gem_userptr_ioctl() an MMU notifier is set up with a (tagged)
userspace pointer. The untagged address should be used so that MMU
notifiers for the untagged address get correctly matched up with the right
BO. This funcation also calls radeon_ttm_tt_pin_userptr(), which uses
provided user pointers for vma lookups, which can only by done with
untagged pointers.

This patch untags user pointers in radeon_gem_userptr_ioctl().

Reviewed-by: Khalid Aziz 
Reviewed-by: Kees Cook 
Suggested-by: Felix Kuehling 
Acked-by: Felix Kuehling 
Signed-off-by: Andrey Konovalov 
---
 drivers/gpu/drm/radeon/radeon_gem.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_gem.c 
b/drivers/gpu/drm/radeon/radeon_gem.c
index d8bc5d2dfd61..89353098b627 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -296,6 +296,8 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
uint32_t handle;
int r;
 
+   args->addr = untagged_addr(args->addr);
+
if (offset_in_page(args->addr | args->size))
return -EINVAL;
 
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 03/15] lib: untag user pointers in strn*_user

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

strncpy_from_user and strnlen_user accept user addresses as arguments, and
do not go through the same path as copy_from_user and others, so here we
need to handle the case of tagged user addresses separately.

Untag user pointers passed to these functions.

Note, that this patch only temporarily untags the pointers to perform
validity checks, but then uses them as is to perform user memory accesses.

Reviewed-by: Vincenzo Frascino 
Reviewed-by: Khalid Aziz 
Acked-by: Kees Cook 
Reviewed-by: Catalin Marinas 
Signed-off-by: Andrey Konovalov 
---
 lib/strncpy_from_user.c | 3 ++-
 lib/strnlen_user.c  | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/lib/strncpy_from_user.c b/lib/strncpy_from_user.c
index 023ba9f3b99f..dccb95af6003 100644
--- a/lib/strncpy_from_user.c
+++ b/lib/strncpy_from_user.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -108,7 +109,7 @@ long strncpy_from_user(char *dst, const char __user *src, 
long count)
return 0;
 
max_addr = user_addr_max();
-   src_addr = (unsigned long)src;
+   src_addr = (unsigned long)untagged_addr(src);
if (likely(src_addr < max_addr)) {
unsigned long max = max_addr - src_addr;
long retval;
diff --git a/lib/strnlen_user.c b/lib/strnlen_user.c
index 7f2db3fe311f..28ff554a1be8 100644
--- a/lib/strnlen_user.c
+++ b/lib/strnlen_user.c
@@ -2,6 +2,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -109,7 +110,7 @@ long strnlen_user(const char __user *str, long count)
return 0;
 
max_addr = user_addr_max();
-   src_addr = (unsigned long)str;
+   src_addr = (unsigned long)untagged_addr(str);
if (likely(src_addr < max_addr)) {
unsigned long max = max_addr - src_addr;
long retval;
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 04/15] mm: untag user pointers passed to memory syscalls

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

This patch allows tagged pointers to be passed to the following memory
syscalls: get_mempolicy, madvise, mbind, mincore, mlock, mlock2, mprotect,
mremap, msync, munlock, move_pages.

The mmap and mremap syscalls do not currently accept tagged addresses.
Architectures may interpret the tag as a background colour for the
corresponding vma.

Reviewed-by: Khalid Aziz 
Reviewed-by: Vincenzo Frascino 
Reviewed-by: Catalin Marinas 
Reviewed-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 mm/madvise.c   | 2 ++
 mm/mempolicy.c | 3 +++
 mm/migrate.c   | 2 +-
 mm/mincore.c   | 2 ++
 mm/mlock.c | 4 
 mm/mprotect.c  | 2 ++
 mm/mremap.c| 7 +++
 mm/msync.c | 2 ++
 8 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/mm/madvise.c b/mm/madvise.c
index 968df3aa069f..4b102a61bfbf 100644
--- a/mm/madvise.c
+++ b/mm/madvise.c
@@ -810,6 +810,8 @@ SYSCALL_DEFINE3(madvise, unsigned long, start, size_t, 
len_in, int, behavior)
size_t len;
struct blk_plug plug;
 
+   start = untagged_addr(start);
+
if (!madvise_behavior_valid(behavior))
return error;
 
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index f48693f75b37..74c134d0c84e 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -1360,6 +1360,7 @@ static long kernel_mbind(unsigned long start, unsigned 
long len,
int err;
unsigned short mode_flags;
 
+   start = untagged_addr(start);
mode_flags = mode & MPOL_MODE_FLAGS;
mode &= ~MPOL_MODE_FLAGS;
if (mode >= MPOL_MAX)
@@ -1517,6 +1518,8 @@ static int kernel_get_mempolicy(int __user *policy,
int uninitialized_var(pval);
nodemask_t nodes;
 
+   addr = untagged_addr(addr);
+
if (nmask != NULL && maxnode < nr_node_ids)
return -EINVAL;
 
diff --git a/mm/migrate.c b/mm/migrate.c
index 8992741f10aa..8f59c24cb141 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -1609,7 +1609,7 @@ static int do_pages_move(struct mm_struct *mm, nodemask_t 
task_nodes,
goto out_flush;
if (get_user(node, nodes + i))
goto out_flush;
-   addr = (unsigned long)p;
+   addr = (unsigned long)untagged_addr(p);
 
err = -ENODEV;
if (node < 0 || node >= MAX_NUMNODES)
diff --git a/mm/mincore.c b/mm/mincore.c
index 4fe91d497436..3cfa120ba0eb 100644
--- a/mm/mincore.c
+++ b/mm/mincore.c
@@ -257,6 +257,8 @@ SYSCALL_DEFINE3(mincore, unsigned long, start, size_t, len,
unsigned long pages;
unsigned char *tmp;
 
+   start = untagged_addr(start);
+
/* Check the start address: needs to be page-aligned.. */
if (start & ~PAGE_MASK)
return -EINVAL;
diff --git a/mm/mlock.c b/mm/mlock.c
index a90099da4fb4..a72c1eeded77 100644
--- a/mm/mlock.c
+++ b/mm/mlock.c
@@ -674,6 +674,8 @@ static __must_check int do_mlock(unsigned long start, 
size_t len, vm_flags_t fla
unsigned long lock_limit;
int error = -ENOMEM;
 
+   start = untagged_addr(start);
+
if (!can_do_mlock())
return -EPERM;
 
@@ -735,6 +737,8 @@ SYSCALL_DEFINE2(munlock, unsigned long, start, size_t, len)
 {
int ret;
 
+   start = untagged_addr(start);
+
len = PAGE_ALIGN(len + (offset_in_page(start)));
start &= PAGE_MASK;
 
diff --git a/mm/mprotect.c b/mm/mprotect.c
index bf38dfbbb4b4..19f981b733bc 100644
--- a/mm/mprotect.c
+++ b/mm/mprotect.c
@@ -465,6 +465,8 @@ static int do_mprotect_pkey(unsigned long start, size_t len,
const bool rier = (current->personality & READ_IMPLIES_EXEC) &&
(prot & PROT_READ);
 
+   start = untagged_addr(start);
+
prot &= ~(PROT_GROWSDOWN|PROT_GROWSUP);
if (grows == (PROT_GROWSDOWN|PROT_GROWSUP)) /* can't be both */
return -EINVAL;
diff --git a/mm/mremap.c b/mm/mremap.c
index fc241d23cd97..64c9a3b8be0a 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -606,6 +606,13 @@ SYSCALL_DEFINE5(mremap, unsigned long, addr, unsigned 
long, old_len,
LIST_HEAD(uf_unmap_early);
LIST_HEAD(uf_unmap);
 
+   /*
+* Architectures may interpret the tag passed to mmap as a background
+* colour for the corresponding vma. For mremap we don't allow tagged
+* new_addr to preserve similar behaviour to mmap.
+*/
+   addr = untagged_addr(addr);
+
if (flags & ~(MREMAP_FIXED | MREMAP_MAYMOVE))
return ret;
 
diff --git a/mm/msync.c b/mm/msync.c
index ef30a429623a..c3bd3e75f687 100644
--- a/mm/msync.c
+++ b/mm/msync.c
@@ -37,6 +37,8 @@ SYSCALL_DEFINE3(msync, unsigned long, start, size_t, len, 
int, flags)
int unmapped_error = 0;
int error = -EINVAL;
 
+   start = untagged_addr(start);
+
 

[PATCH v19 13/15] tee/shm: untag user pointers in tee_shm_register

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

tee_shm_register()->optee_shm_unregister()->check_mem_type() uses provided
user pointers for vma lookups (via __check_mem_type()), which can only by
done with untagged pointers.

Untag user pointers in this function.

Reviewed-by: Kees Cook 
Acked-by: Jens Wiklander 
Signed-off-by: Andrey Konovalov 
---
 drivers/tee/tee_shm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c
index 2da026fd12c9..09ddcd06c715 100644
--- a/drivers/tee/tee_shm.c
+++ b/drivers/tee/tee_shm.c
@@ -254,6 +254,7 @@ struct tee_shm *tee_shm_register(struct tee_context *ctx, 
unsigned long addr,
shm->teedev = teedev;
shm->ctx = ctx;
shm->id = -1;
+   addr = untagged_addr(addr);
start = rounddown(addr, PAGE_SIZE);
shm->offset = addr - start;
shm->size = length;
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 11/15] IB/mlx4: untag user pointers in mlx4_get_umem_mr

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

mlx4_get_umem_mr() uses provided user pointers for vma lookups, which can
only by done with untagged pointers.

Untag user pointers in this function.

Reviewed-by: Jason Gunthorpe 
Acked-by: Catalin Marinas 
Reviewed-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 drivers/infiniband/hw/mlx4/mr.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/mr.c
index 753479285ce9..6ae503cfc526 100644
--- a/drivers/infiniband/hw/mlx4/mr.c
+++ b/drivers/infiniband/hw/mlx4/mr.c
@@ -377,6 +377,7 @@ static struct ib_umem *mlx4_get_umem_mr(struct ib_udata 
*udata, u64 start,
 * again
 */
if (!ib_access_writable(access_flags)) {
+   unsigned long untagged_start = untagged_addr(start);
struct vm_area_struct *vma;
 
down_read(¤t->mm->mmap_sem);
@@ -385,9 +386,9 @@ static struct ib_umem *mlx4_get_umem_mr(struct ib_udata 
*udata, u64 start,
 * cover the memory, but for now it requires a single vma to
 * entirely cover the MR to support RO mappings.
 */
-   vma = find_vma(current->mm, start);
-   if (vma && vma->vm_end >= start + length &&
-   vma->vm_start <= start) {
+   vma = find_vma(current->mm, untagged_start);
+   if (vma && vma->vm_end >= untagged_start + length &&
+   vma->vm_start <= untagged_start) {
if (vma->vm_flags & VM_WRITE)
access_flags |= IB_ACCESS_LOCAL_WRITE;
} else {
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 14/15] vfio/type1: untag user pointers in vaddr_get_pfn

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

vaddr_get_pfn() uses provided user pointers for vma lookups, which can
only by done with untagged pointers.

Untag user pointers in this function.

Reviewed-by: Eric Auger 
Reviewed-by: Vincenzo Frascino 
Reviewed-by: Catalin Marinas 
Reviewed-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 drivers/vfio/vfio_iommu_type1.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 054391f30fa8..67a24b4d0fa4 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -368,6 +368,8 @@ static int vaddr_get_pfn(struct mm_struct *mm, unsigned 
long vaddr,
 
down_read(&mm->mmap_sem);
 
+   vaddr = untagged_addr(vaddr);
+
vma = find_vma_intersection(mm, vaddr, vaddr + 1);
 
if (vma && vma->vm_flags & VM_PFNMAP) {
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 06/15] mm: untag user pointers in get_vaddr_frames

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

get_vaddr_frames uses provided user pointers for vma lookups, which can
only by done with untagged pointers. Instead of locating and changing
all callers of this function, perform untagging in it.

Reviewed-by: Khalid Aziz 
Reviewed-by: Vincenzo Frascino 
Acked-by: Catalin Marinas 
Reviewed-by: Kees Cook 
Signed-off-by: Andrey Konovalov 
---
 mm/frame_vector.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/mm/frame_vector.c b/mm/frame_vector.c
index c64dca6e27c2..c431ca81dad5 100644
--- a/mm/frame_vector.c
+++ b/mm/frame_vector.c
@@ -46,6 +46,8 @@ int get_vaddr_frames(unsigned long start, unsigned int 
nr_frames,
if (WARN_ON_ONCE(nr_frames > vec->nr_allocated))
nr_frames = vec->nr_allocated;
 
+   start = untagged_addr(start);
+
down_read(&mm->mmap_sem);
locked = 1;
vma = find_vma_intersection(mm, start, start + 1);
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 05/15] mm: untag user pointers in mm/gup.c

[Andrey Konovalov]

This patch is a part of a series that extends kernel ABI to allow to pass
tagged user pointers (with the top byte set to something else other than
0x00) as syscall arguments.

mm/gup.c provides a kernel interface that accepts user addresses and
manipulates user pages directly (for example get_user_pages, that is used
by the futex syscall). Since a user can provided tagged addresses, we need
to handle this case.

Add untagging to gup.c functions that use user addresses for vma lookups.

Reviewed-by: Khalid Aziz 
Reviewed-by: Vincenzo Frascino 
Reviewed-by: Kees Cook 
Reviewed-by: Catalin Marinas 
Signed-off-by: Andrey Konovalov 
---
 mm/gup.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/mm/gup.c b/mm/gup.c
index 98f13ab37bac..1c1c97ec63df 100644
--- a/mm/gup.c
+++ b/mm/gup.c
@@ -799,6 +799,8 @@ static long __get_user_pages(struct task_struct *tsk, 
struct mm_struct *mm,
if (!nr_pages)
return 0;
 
+   start = untagged_addr(start);
+
VM_BUG_ON(!!pages != !!(gup_flags & FOLL_GET));
 
/*
@@ -961,6 +963,8 @@ int fixup_user_fault(struct task_struct *tsk, struct 
mm_struct *mm,
struct vm_area_struct *vma;
vm_fault_t ret, major = 0;
 
+   address = untagged_addr(address);
+
if (unlocked)
fault_flags |= FAULT_FLAG_ALLOW_RETRY;
 
-- 
2.22.0.709.g102302147b-goog

[PATCH v19 02/15] arm64: Introduce prctl() options to control the tagged user addresses ABI

[Andrey Konovalov]

From: Catalin Marinas 

It is not desirable to relax the ABI to allow tagged user addresses into
the kernel indiscriminately. This patch introduces a prctl() interface
for enabling or disabling the tagged ABI with a global sysctl control
for preventing applications from enabling the relaxed ABI (meant for
testing user-space prctl() return error checking without reconfiguring
the kernel). The ABI properties are inherited by threads of the same
application and fork()'ed children but cleared on execve(). A Kconfig
option allows the overall disabling of the relaxed ABI.

The PR_SET_TAGGED_ADDR_CTRL will be expanded in the future to handle
MTE-specific settings like imprecise vs precise exceptions.

Reviewed-by: Kees Cook 
Signed-off-by: Catalin Marinas 
Signed-off-by: Andrey Konovalov 
---
 arch/arm64/Kconfig   |  9 
 arch/arm64/include/asm/processor.h   |  8 +++
 arch/arm64/include/asm/thread_info.h |  1 +
 arch/arm64/include/asm/uaccess.h |  4 +-
 arch/arm64/kernel/process.c  | 73 
 include/uapi/linux/prctl.h   |  5 ++
 kernel/sys.c | 12 +
 7 files changed, 111 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3adcec05b1f6..5d254178b9ca 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1110,6 +1110,15 @@ config ARM64_SW_TTBR0_PAN
  zeroed area and reserved ASID. The user access routines
  restore the valid TTBR0_EL1 temporarily.
 
+config ARM64_TAGGED_ADDR_ABI
+   bool "Enable the tagged user addresses syscall ABI"
+   default y
+   help
+ When this option is enabled, user applications can opt in to a
+ relaxed ABI via prctl() allowing tagged addresses to be passed
+ to system calls as pointer arguments. For details, see
+ Documentation/arm64/tagged-address-abi.txt.
+
 menuconfig COMPAT
bool "Kernel support for 32-bit EL0"
depends on ARM64_4K_PAGES || EXPERT
diff --git a/arch/arm64/include/asm/processor.h 
b/arch/arm64/include/asm/processor.h
index fd5b1a4efc70..ee86070a28d4 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -296,6 +296,14 @@ extern void __init minsigstksz_setup(void);
 /* PR_PAC_RESET_KEYS prctl */
 #define PAC_RESET_KEYS(tsk, arg)   ptrauth_prctl_reset_keys(tsk, arg)
 
+#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
+/* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
+long set_tagged_addr_ctrl(unsigned long arg);
+long get_tagged_addr_ctrl(void);
+#define SET_TAGGED_ADDR_CTRL(arg)  set_tagged_addr_ctrl(arg)
+#define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl()
+#endif
+
 /*
  * For CONFIG_GCC_PLUGIN_STACKLEAK
  *
diff --git a/arch/arm64/include/asm/thread_info.h 
b/arch/arm64/include/asm/thread_info.h
index 180b34ec5965..012238d8e58d 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -90,6 +90,7 @@ void arch_release_task_struct(struct task_struct *tsk);
 #define TIF_SVE23  /* Scalable Vector Extension in 
use */
 #define TIF_SVE_VL_INHERIT 24  /* Inherit sve_vl_onexec across exec */
 #define TIF_SSBD   25  /* Wants SSB mitigation */
+#define TIF_TAGGED_ADDR26  /* Allow tagged user addresses 
*/
 
 #define _TIF_SIGPENDING(1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index a138e3b4f717..097d6bfac0b7 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -62,7 +62,9 @@ static inline unsigned long __range_ok(const void __user 
*addr, unsigned long si
 {
unsigned long ret, limit = current_thread_info()->addr_limit;
 
-   addr = untagged_addr(addr);
+   if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) &&
+   test_thread_flag(TIF_TAGGED_ADDR))
+   addr = untagged_addr(addr);
 
__chk_user_ptr(addr);
asm volatile(
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 6a869d9f304f..ef06a303bda0 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -38,6 +39,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -307,11 +309,18 @@ static void tls_thread_flush(void)
}
 }
 
+static void flush_tagged_addr_state(void)
+{
+   if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI))
+   clear_thread_flag(TIF_TAGGED_ADDR);
+}
+
 void flush_thread(void)
 {
fpsimd_flush_thread();
tls_thread_flush();
flush_ptrace_hw_breakpoint(current);
+   flush_tagged_addr_state();
 }
 
 void release_thread(struct task_struct *dead_task)
@@ -541,3 +550,67 @@ void arch_setup_new_exec(void)
 
ptrauth_thread_init_user(current);
 }
+
+#ifdef CON

Re: [PATCH v19 00/15] arm64: untag user pointers passed to the kernel

[Andrey Konovalov]

On Tue, Jul 23, 2019 at 7:59 PM Andrey Konovalov  wrote:
>
> === Overview
>
> arm64 has a feature called Top Byte Ignore, which allows to embed pointer
> tags into the top byte of each pointer. Userspace programs (such as
> HWASan, a memory debugging tool [1]) might use this feature and pass
> tagged user pointers to the kernel through syscalls or other interfaces.
>
> Right now the kernel is already able to handle user faults with tagged
> pointers, due to these patches:
>
> 1. 81cddd65 ("arm64: traps: fix userspace cache maintenance emulation on a
>  tagged pointer")
> 2. 7dcd9dd8 ("arm64: hw_breakpoint: fix watchpoint matching for tagged
>   pointers")
> 3. 276e9327 ("arm64: entry: improve data abort handling of tagged
>   pointers")
>
> This patchset extends tagged pointer support to syscall arguments.
>
> As per the proposed ABI change [3], tagged pointers are only allowed to be
> passed to syscalls when they point to memory ranges obtained by anonymous
> mmap() or sbrk() (see the patchset [3] for more details).
>
> For non-memory syscalls this is done by untaging user pointers when the
> kernel performs pointer checking to find out whether the pointer comes
> from userspace (most notably in access_ok). The untagging is done only
> when the pointer is being checked, the tag is preserved as the pointer
> makes its way through the kernel and stays tagged when the kernel
> dereferences the pointer when perfoming user memory accesses.
>
> The mmap and mremap (only new_addr) syscalls do not currently accept
> tagged addresses. Architectures may interpret the tag as a background
> colour for the corresponding vma.
>
> Other memory syscalls (mprotect, etc.) don't do user memory accesses but
> rather deal with memory ranges, and untagged pointers are better suited to
> describe memory ranges internally. Thus for memory syscalls we untag
> pointers completely when they enter the kernel.
>
> === Other approaches
>
> One of the alternative approaches to untagging that was considered is to
> completely strip the pointer tag as the pointer enters the kernel with
> some kind of a syscall wrapper, but that won't work with the countless
> number of different ioctl calls. With this approach we would need a custom
> wrapper for each ioctl variation, which doesn't seem practical.
>
> An alternative approach to untagging pointers in memory syscalls prologues
> is to inspead allow tagged pointers to be passed to find_vma() (and other
> vma related functions) and untag them there. Unfortunately, a lot of
> find_vma() callers then compare or subtract the returned vma start and end
> fields against the pointer that was being searched. Thus this approach
> would still require changing all find_vma() callers.
>
> === Testing
>
> The following testing approaches has been taken to find potential issues
> with user pointer untagging:
>
> 1. Static testing (with sparse [2] and separately with a custom static
>analyzer based on Clang) to track casts of __user pointers to integer
>types to find places where untagging needs to be done.
>
> 2. Static testing with grep to find parts of the kernel that call
>find_vma() (and other similar functions) or directly compare against
>vm_start/vm_end fields of vma.
>
> 3. Static testing with grep to find parts of the kernel that compare
>user pointers with TASK_SIZE or other similar consts and macros.
>
> 4. Dynamic testing: adding BUG_ON(has_tag(addr)) to find_vma() and running
>a modified syzkaller version that passes tagged pointers to the kernel.
>
> Based on the results of the testing the requried patches have been added
> to the patchset.
>
> === Notes
>
> This patchset is meant to be merged together with "arm64 relaxed ABI" [3].
>
> This patchset is a prerequisite for ARM's memory tagging hardware feature
> support [4].
>
> This patchset has been merged into the Pixel 2 & 3 kernel trees and is
> now being used to enable testing of Pixel phones with HWASan.
>
> Thanks!
>
> [1] http://clang.llvm.org/docs/HardwareAssistedAddressSanitizerDesign.html
>
> [2] 
> https://github.com/lucvoo/sparse-dev/commit/5f960cb10f56ec2017c128ef9d16060e0145f292
>
> [3] https://lkml.org/lkml/2019/6/12/745
>
> [4] 
> https://community.arm.com/processors/b/blog/posts/arm-a-profile-architecture-2018-developments-armv85a

Hi Andrew and Catalin,

Do you think this is ready to be merged?

Should this go through the mm or the arm tree?

Thanks!


>
> === History
>
> Changes in v19:
> - Rebased onto 7b5cf701 (5.3-rc1+).
>
> Changes in v18:
> - Reverted the selftest back to not using the LD_PRELOAD approach.
> - Added prctl(PR_SET_TAGGED_ADDR_CTRL) call to the selftest.
> - Reworded the patch descriptions to make them less oriented on arm64
>   only.
> - Catalin's patch: "I added a Kconfig option and dropped the prctl args
>   zero check. There is some minor clean-up as well".
>
> Changes in v17:
> - The "uaccess: add noop untagged_addr definition" patch is dr

Re: kernel panic: stack is corrupted in pointer

[John Fastabend]

Dmitry Vyukov wrote:
> On Wed, Jul 17, 2019 at 10:58 AM syzbot
>  wrote:
> >
> > Hello,
> >
> > syzbot found the following crash on:
> >
> > HEAD commit:1438cde7 Add linux-next specific files for 20190716
> > git tree:   linux-next
> > console output: https://syzkaller.appspot.com/x/log.txt?x=1398805860
> > kernel config:  https://syzkaller.appspot.com/x/.config?x=3430a151e1452331
> > dashboard link: https://syzkaller.appspot.com/bug?extid=79f5f028005a77ecb6bb
> > compiler:   gcc (GCC) 9.0.0 20181231 (experimental)
> > syz repro:  https://syzkaller.appspot.com/x/repro.syz?x=111fc8afa0
> 
> From the repro it looks like the same bpf stack overflow bug. +John
> We need to dup them onto some canonical report for this bug, or this
> becomes unmanageable.

Fixes in bpf tree should fix this. Hopefully, we will squash this once fixes
percolate up.

#syz test: git://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git

> 
> #syz dup: kernel panic: corrupted stack end in dput
> 
> > The bug was bisected to:
> >
> > commit 96a5d8d4915f3e241ebb48d5decdd110ab9c7dcf
> > Author: Leo Liu 
> > Date:   Fri Jul 13 15:26:28 2018 +
> >
> >  drm/amdgpu: Make sure IB tests flushed after IP resume
> >
> > bisection log:  https://syzkaller.appspot.com/x/bisect.txt?x=14a4620060
> > final crash:https://syzkaller.appspot.com/x/report.txt?x=16a4620060
> > console output: https://syzkaller.appspot.com/x/log.txt?x=12a4620060
> >
> > IMPORTANT: if you fix the bug, please add the following tag to the commit:
> > Reported-by: syzbot+79f5f028005a77ecb...@syzkaller.appspotmail.com
> > Fixes: 96a5d8d4915f ("drm/amdgpu: Make sure IB tests flushed after IP
> > resume")
> >
> > Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in:
> > pointer+0x702/0x750 lib/vsprintf.c:2187
> > Shutting down cpus with NMI
> > Kernel Offset: disabled
> >
> >
> > ---
> > This bug is generated by a bot. It may contain errors.
> > See https://goo.gl/tpsmEJ for more information about syzbot.
> > syzbot engineers can be reached at syzkal...@googlegroups.com.
> >
> > syzbot will keep track of this bug report. See:
> > https://goo.gl/tpsmEJ#status for how to communicate with syzbot.
> > For information about bisection process see: https://goo.gl/tpsmEJ#bisection
> > syzbot can test patches for this bug, for details see:
> > https://goo.gl/tpsmEJ#testing-patches


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[PATCH v2 0/2] This series enables S/G for Picasso.

[Andrey Grodzovsky]

First patch fix a hard hang introduced by placing the display
BO in GTT memory because of HW issues with cached mappings
and the second patch enables S/G.

Andrey Grodzovsky (1):
  drm/amdgpu: Fix hard hang for S/G display BOs.

Shirish S (1):
  drm/amd: enable S/G for RAVEN chip

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 13 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c|  7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  3 ++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 4 files changed, 17 insertions(+), 8 deletions(-)

-- 
2.7.4

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[PATCH v2 1/2] drm/amdgpu: Fix hard hang for S/G display BOs.

[Andrey Grodzovsky]

HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.

v2:
Move all BO placemnt logic to amdgpu_display_supported_domains

Suggested-by: Alex Deucher 
Signed-off-by: Andrey Grodzovsky 
Reviewed-by: Alex Deucher 
Tested-by: Shirish S 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index e476092..bf0c61b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -137,14 +137,14 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
  fb_tiled);
domain = amdgpu_display_supported_domains(adev);
-
height = ALIGN(mode_cmd->height, 8);
size = mode_cmd->pitches[0] * height;
aligned_size = ALIGN(size, PAGE_SIZE);
ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
-  AMDGPU_GEM_CREATE_VRAM_CLEARED,
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+  AMDGPU_GEM_CREATE_VRAM_CLEARED|
+  AMDGPU_GEM_CREATE_CPU_GTT_USWC,
   ttm_bo_type_kernel, NULL, &gobj);
if (ret) {
pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
@@ -166,7 +166,6 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
dev_err(adev->dev, "FB failed to set tiling flags\n");
}
 
-
ret = amdgpu_bo_pin(abo, domain);
if (ret) {
amdgpu_bo_unreserve(abo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 2cead5a..eeed089 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -743,7 +743,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
struct amdgpu_device *adev = dev->dev_private;
struct drm_gem_object *gobj;
uint32_t handle;
-   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+   AMDGPU_GEM_CREATE_CPU_GTT_USWC;
u32 domain;
int r;
 
-- 
2.7.4

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[PATCH v2 2/2] drm/amd: enable S/G for RAVEN chip

[Andrey Grodzovsky]

From: Shirish S 

enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain

v2:
Move BO placement logic into amdgpu_display_supported_domains

Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
Signed-off-by: Shirish S 
Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 13 +++--
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 767ee699..e34e2f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -37,6 +37,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static void amdgpu_display_flip_callback(struct dma_fence *f,
 struct dma_fence_cb *cb)
@@ -498,8 +499,16 @@ uint32_t amdgpu_display_supported_domains(struct 
amdgpu_device *adev)
uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
 
 #if defined(CONFIG_DRM_AMD_DC)
-   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN &&
-   adev->flags & AMD_IS_APU &&
+   /*
+* if drm_arch_can_wc_memory returns false in amdgpu_bo_do_create
+* AMDGPU_GEM_CREATE_CPU_GTT_USWC flag was unset meaning that USWC 
mappings
+* is not supported for this board. But this mapping is required
+* to avoid hang caused by placement of scanout BO in GTT on certain
+* APUs. So force the BO placement to VRAM in case this architecture
+* will not allow USWC mappings.
+*/
+   if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <= CHIP_RAVEN &&
+   adev->flags & AMD_IS_APU && drm_arch_can_wc_memory() &&
amdgpu_device_asic_has_dc_support(adev->asic_type))
domain |= AMDGPU_GEM_DOMAIN_GTT;
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9ef7854..d50f309 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -686,7 +686,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 */
if (adev->flags & AMD_IS_APU &&
adev->asic_type >= CHIP_CARRIZO &&
-   adev->asic_type < CHIP_RAVEN)
+   adev->asic_type <= CHIP_RAVEN)
init_data.flags.gpu_vm_support = true;
 
if (amdgpu_dc_feature_mask & DC_FBC_MASK)
-- 
2.7.4

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Re: [PATCH] drm/amd/display: readd -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines

[Alex Deucher]

On Tue, Jul 23, 2019 at 3:16 AM Nick Desaulniers
 wrote:
>
> arch/x86/Makefile disables SSE and SSE2 for the whole kernel.  The
> AMDGPU drivers modified in this patch re-enable SSE but not SSE2.  Turn
> on SSE2 to support emitting double precision floating point instructions
> rather than calls to non-existent (usually available from gcc_s or
> compiler_rt) floating point helper routines for Clang.
>
> This was originally landed in:
> commit 10117450735c ("drm/amd/display: add -msse2 to prevent Clang from 
> emitting libcalls to undefined SW FP routines")
> but reverted in:
> commit 193392ed9f69 ("Revert "drm/amd/display: add -msse2 to prevent Clang 
> from emitting libcalls to undefined SW FP routines"")
> due to bugreports from GCC builds. Add guards to only do so for Clang.
>
> Link: https://bugs.freedesktop.org/show_bug.cgi?id=109487
> Link: https://github.com/ClangBuiltLinux/linux/issues/327
>
> Suggested-by: Sedat Dilek 
> Suggested-by: Sami Tolvanen 
> Signed-off-by: Nick Desaulniers 

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile | 4 
>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 4 
>  drivers/gpu/drm/amd/display/dc/dml/Makefile   | 4 
>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   | 4 
>  4 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile 
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 95f332ee3e7e..16614d73a5fc 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -32,6 +32,10 @@ endif
>
>  calcs_ccflags := -mhard-float -msse $(cc_stack_align)
>
> +ifdef CONFIG_CC_IS_CLANG
> +calcs_ccflags += -msse2
> +endif
> +
>  CFLAGS_dcn_calcs.o := $(calcs_ccflags)
>  CFLAGS_dcn_calc_auto.o := $(calcs_ccflags)
>  CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> index e9721a906592..f57a3b281408 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
> @@ -18,6 +18,10 @@ endif
>
>  CFLAGS_dcn20_resource.o := -mhard-float -msse $(cc_stack_align)
>
> +ifdef CONFIG_CC_IS_CLANG
> +CFLAGS_dcn20_resource.o += -msse2
> +endif
> +
>  AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
>
>  AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> index 0bb7a20675c4..132ade1a234e 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
> @@ -32,6 +32,10 @@ endif
>
>  dml_ccflags := -mhard-float -msse $(cc_stack_align)
>
> +ifdef CONFIG_CC_IS_CLANG
> +dml_ccflags += -msse2
> +endif
> +
>  CFLAGS_display_mode_lib.o := $(dml_ccflags)
>
>  ifdef CONFIG_DRM_AMD_DC_DCN2_0
> diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile 
> b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> index e019cd9447e8..17db603f2d1f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
> @@ -9,6 +9,10 @@ endif
>
>  dsc_ccflags := -mhard-float -msse $(cc_stack_align)
>
> +ifdef CONFIG_CC_IS_CLANG
> +dsc_ccflags += -msse2
> +endif
> +
>  CFLAGS_rc_calc.o := $(dsc_ccflags)
>  CFLAGS_rc_calc_dpi.o := $(dsc_ccflags)
>  CFLAGS_codec_main_amd.o := $(dsc_ccflags)
> --
> 2.22.0.657.g960e92d24f-goog
>
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Re: [PATCH][next] drm/amdgpu: remove redundant assignment to pointer 'ring'

[Alex Deucher]

On Tue, Jul 23, 2019 at 9:41 AM Colin King  wrote:
>
> From: Colin Ian King 
>
> The pointer 'ring' is being assigned a value that is never
> read, hence the assignment is redundant and can be removed.
>
> Addresses-Coverity: ("Unused value")
> Signed-off-by: Colin Ian King 
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 93b3500e522b..a2a8ca942f34 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -1331,7 +1331,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device 
> *adev,
> WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
> 
> UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
>
> -   ring = &adev->vcn.inst->ring_dec;
> WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
>RREG32_SOC15(UVD, 0, 
> mmUVD_SCRATCH2) & 0x7FFF);
> SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,

While we don't use ring here, I think the assignment is useful to
delineate that we are no longer working with the jpeg ring, but rather
the decode ring.  The mmUVD_RBC_RB_WPTR register is part of the decode
ring, not jpeg.  We would normally use the ring->wptr like we do for
the other rings, but in this particular case, the value happens to be
shadowed to a scratch register due to the way the dynamic power gating
works on that ring.

Alex

> --
> 2.20.1
>
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Re: [PATCH] drm/amdgpu: Use dev_get_drvdata where possible

[Alex Deucher]

On Tue, Jul 23, 2019 at 9:36 AM Chuhong Yuan  wrote:
>
> Instead of using to_pci_dev + pci_get_drvdata,
> use dev_get_drvdata to make code simpler.
>
> Signed-off-by: Chuhong Yuan 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 27 +
>  1 file changed, 10 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index f2e8b4238efd..df82091a29d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1097,16 +1097,14 @@ amdgpu_pci_shutdown(struct pci_dev *pdev)
>
>  static int amdgpu_pmops_suspend(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
>
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> return amdgpu_device_suspend(drm_dev, true, true);
>  }
>
>  static int amdgpu_pmops_resume(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
>
> /* GPU comes up enabled by the bios on resume */
> if (amdgpu_device_is_px(drm_dev)) {
> @@ -1120,33 +1118,29 @@ static int amdgpu_pmops_resume(struct device *dev)
>
>  static int amdgpu_pmops_freeze(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> +
> return amdgpu_device_suspend(drm_dev, false, true);
>  }
>
>  static int amdgpu_pmops_thaw(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> +
> return amdgpu_device_resume(drm_dev, false, true);
>  }
>
>  static int amdgpu_pmops_poweroff(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> +
> return amdgpu_device_suspend(drm_dev, true, true);
>  }
>
>  static int amdgpu_pmops_restore(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
>
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> return amdgpu_device_resume(drm_dev, false, true);
>  }
>
> @@ -1205,8 +1199,7 @@ static int amdgpu_pmops_runtime_resume(struct device 
> *dev)
>
>  static int amdgpu_pmops_runtime_idle(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct drm_crtc *crtc;
>
> if (!amdgpu_device_is_px(drm_dev)) {
> --
> 2.20.1
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Re: [PATCH] drm/amd/display: Use dev_get_drvdata

[Alex Deucher]

On Tue, Jul 23, 2019 at 9:36 AM Chuhong Yuan  wrote:
>
> Instead of using to_pci_dev + pci_get_drvdata,
> use dev_get_drvdata to make code simpler.
>
> Signed-off-by: Chuhong Yuan 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 4a29f72334d0..524e1e19017e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2428,8 +2428,7 @@ static ssize_t s3_debug_store(struct device *device,
>  {
> int ret;
> int s3_state;
> -   struct pci_dev *pdev = to_pci_dev(device);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(device);
> struct amdgpu_device *adev = drm_dev->dev_private;
>
> ret = kstrtoint(buf, 0, &s3_state);
> --
> 2.20.1
>
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Re: [PATCH] drm/radeon: Use dev_get_drvdata where possible

[Alex Deucher]

On Tue, Jul 23, 2019 at 9:36 AM Chuhong Yuan  wrote:
>
> Instead of using to_pci_dev + pci_get_drvdata,
> use dev_get_drvdata to make code simpler.
>
> Signed-off-by: Chuhong Yuan 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/radeon_drv.c | 15 +--
>  1 file changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c 
> b/drivers/gpu/drm/radeon/radeon_drv.c
> index a6cbe11f79c6..b2bb74d5bffb 100644
> --- a/drivers/gpu/drm/radeon/radeon_drv.c
> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
> @@ -358,15 +358,13 @@ radeon_pci_shutdown(struct pci_dev *pdev)
>
>  static int radeon_pmops_suspend(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> return radeon_suspend_kms(drm_dev, true, true, false);
>  }
>
>  static int radeon_pmops_resume(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
>
> /* GPU comes up enabled by the bios on resume */
> if (radeon_is_px(drm_dev)) {
> @@ -380,15 +378,13 @@ static int radeon_pmops_resume(struct device *dev)
>
>  static int radeon_pmops_freeze(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> return radeon_suspend_kms(drm_dev, false, true, true);
>  }
>
>  static int radeon_pmops_thaw(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> return radeon_resume_kms(drm_dev, false, true);
>  }
>
> @@ -447,8 +443,7 @@ static int radeon_pmops_runtime_resume(struct device *dev)
>
>  static int radeon_pmops_runtime_idle(struct device *dev)
>  {
> -   struct pci_dev *pdev = to_pci_dev(dev);
> -   struct drm_device *drm_dev = pci_get_drvdata(pdev);
> +   struct drm_device *drm_dev = dev_get_drvdata(dev);
> struct drm_crtc *crtc;
>
> if (!radeon_is_px(drm_dev)) {
> --
> 2.20.1
>
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Re: [PATCH] drm/amdkfd: Fix byte align on VegaM

[Kuehling, Felix]

This was needed for VI chips before Fiji. I think that means Tonga, Topaz and 
Carrizo. As the list of supported ASICs keeps growing, we should change the 
condition to list only the chips that need the workaround, instead of adding 
every future chip to the list that don't.

Regards,
  Felix

--
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PMTS Software Development Engineer | Linux Compute Kernel
1 Commerce Valley Dr. East, Markham, ON L3T 7X6 Canada
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_ _   _   _   _
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From: amd-gfx  on behalf of Russell, 
Kent 
Sent: Tuesday, July 23, 2019 11:18:52 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org 
Subject: RE: [PATCH] drm/amdkfd: Fix byte align on VegaM


I’ll push this, I was just wondering if Felix could confirm if the TLB 
workaround was only for Tonga/Topaz, in which case we could check for that 
instead of having to expand the list in situations like this, to say “if 
FAMILY_VI && (TOPAZ || TONGA) then”. That way it’s explicitly applying the 
workaround to the affected ASICs instead of implicitly not-applying the 
workaround to unaffected ASICs.



Kent



From: Deucher, Alexander 
Sent: Tuesday, July 23, 2019 11:16 AM
To: Russell, Kent ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM



Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Tuesday, July 23, 2019 10:22 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Russell, Kent mailto:kent.russ...@amd.com>>
Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM



This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell mailto:kent.russ...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 adev->asic_type != CHIP_FIJI &&
 adev->asic_type != CHIP_POLARIS10 &&
 adev->asic_type != CHIP_POLARIS11 &&
-   adev->asic_type != CHIP_POLARIS12) ?
+   adev->asic_type != CHIP_POLARIS12 &&
+   adev->asic_type != CHIP_VEGAM) ?
 VI_BO_SIZE_ALIGN : 1;

 mapping_flags = AMDGPU_VM_PAGE_READABLE;
--
2.17.1

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Re: [PATCH][next] drm/amd/display: fix a missing null check on a failed kzalloc

[Alex Deucher]

On Tue, Jul 23, 2019 at 10:23 AM Colin King  wrote:
>
> From: Colin Ian King 
>
> Currently the allocation of config may fail and a null pointer
> dereference on config can occur.  Fix this by added a null
> check on a failed allocation of config.
>
> Addresses-Coverity: ("Dereference null return")
> Fixes: c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig 
> programming to stereo control interface")
> Signed-off-by: Colin Ian King 

Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
> b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 168f4a7dffdf..7cce2baec2af 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1259,6 +1259,8 @@ bool dc_set_generic_gpio_for_stereo(bool enable,
> struct gpio_generic_mux_config *config = kzalloc(sizeof(struct 
> gpio_generic_mux_config),
>GFP_KERNEL);
>
> +   if (!config)
> +   return false;
> pin_info = dal_gpio_get_generic_pin_info(gpio_service, 
> GPIO_ID_GENERIC, 0);
>
> if (pin_info.mask == 0x || pin_info.offset == 0x) {
> --
> 2.20.1
>
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RE: [PATCH] drm/amdkfd: Fix byte align on VegaM

[Russell, Kent]

That was my thought too. I'll do that as a future patch.

Kent

From: Kuehling, Felix 
Sent: Tuesday, July 23, 2019 2:51 PM
To: Russell, Kent ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM

This was needed for VI chips before Fiji. I think that means Tonga, Topaz and 
Carrizo. As the list of supported ASICs keeps growing, we should change the 
condition to list only the chips that need the workaround, instead of adding 
every future chip to the list that don't.

Regards,
  Felix

--
F e l i x   K u e h l i n g
PMTS Software Development Engineer | Linux Compute Kernel
1 Commerce Valley Dr. East, Markham, ON L3T 7X6 Canada
(O) +1(289)695-1597
_ _   _   _   _
   / \   | \ / | |  _  \  \ _  |
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From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Tuesday, July 23, 2019 11:18:52 AM
To: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: [PATCH] drm/amdkfd: Fix byte align on VegaM


I'll push this, I was just wondering if Felix could confirm if the TLB 
workaround was only for Tonga/Topaz, in which case we could check for that 
instead of having to expand the list in situations like this, to say "if 
FAMILY_VI && (TOPAZ || TONGA) then". That way it's explicitly applying the 
workaround to the affected ASICs instead of implicitly not-applying the 
workaround to unaffected ASICs.



Kent



From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: Tuesday, July 23, 2019 11:16 AM
To: Russell, Kent mailto:kent.russ...@amd.com>>; 
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM



Reviewed-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Russell, Kent mailto:kent.russ...@amd.com>>
Sent: Tuesday, July 23, 2019 10:22 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Russell, Kent mailto:kent.russ...@amd.com>>
Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM



This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell mailto:kent.russ...@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
 adev->asic_type != CHIP_FIJI &&
 adev->asic_type != CHIP_POLARIS10 &&
 adev->asic_type != CHIP_POLARIS11 &&
-   adev->asic_type != CHIP_POLARIS12) ?
+   adev->asic_type != CHIP_POLARIS12 &&
+   adev->asic_type != CHIP_VEGAM) ?
 VI_BO_SIZE_ALIGN : 1;

 mapping_flags = AMDGPU_VM_PAGE_READABLE;
--
2.17.1

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[PATCH 1/2] drm/amdkfd: Use SQC when TCP would fail in gfx9 context save.

[Cornwall, Jay]

When a wavefront raises TRAPSTS.XNACK_ERROR with STATUS.ALLOW_REPLAY=0
subsequent memory instructions have undefined behavior. In practice
SQC stores continue to work but TCP stores do not.

Context save is permitted to fail after XNACK error because the
wavefront will be halted and subsequently terminated. However the
debugger has an interest in retrieving the wavefront VGPR/LDS state.

Detect the out-of-spec case and use SQC stores during context save
in place of TCP stores.

Signed-off-by: Jay Cornwall 
---
 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 365 ++---
 .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm  |  81 +
 2 files changed, 320 insertions(+), 126 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index c45ba00..7274baf 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -274,7 +274,7 @@ static const uint32_t cwsr_trap_gfx8_hex[] = {
 
 
 static const uint32_t cwsr_trap_gfx9_hex[] = {
-   0xbf820001, 0xbf82015e,
+   0xbf820001, 0xbf820241,
0xb8f8f802, 0x89788678,
0xb8fbf803, 0x866eff7b,
0x0400, 0xbf85003b,
@@ -404,15 +404,57 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
0xbefe00c1, 0xbeff00c1,
0xbee80080, 0xbee90080,
0xbef600ff, 0x0100,
+   0x867aff78, 0x0040,
+   0xbf850003, 0xb8faf803,
+   0x897a7aff, 0x1000,
+   0xbf85004d, 0xbe840080,
+   0xd289, 0x0900,
+   0x80048104, 0xd2890001,
+   0x0900, 0x80048104,
+   0xd2890002, 0x0900,
+   0x80048104, 0xd2890003,
+   0x0900, 0x80048104,
+   0xc069003a, 0x0070,
+   0xbf8cc07f, 0x80709070,
+   0xbf06c004, 0xbf84ffee,
+   0xbe840080, 0xd289,
+   0x0901, 0x80048104,
+   0xd2890001, 0x0901,
+   0x80048104, 0xd2890002,
+   0x0901, 0x80048104,
+   0xd2890003, 0x0901,
+   0x80048104, 0xc069003a,
+   0x0070, 0xbf8cc07f,
+   0x80709070, 0xbf06c004,
+   0xbf84ffee, 0xbe840080,
+   0xd289, 0x0902,
+   0x80048104, 0xd2890001,
+   0x0902, 0x80048104,
+   0xd2890002, 0x0902,
+   0x80048104, 0xd2890003,
+   0x0902, 0x80048104,
+   0xc069003a, 0x0070,
+   0xbf8cc07f, 0x80709070,
+   0xbf06c004, 0xbf84ffee,
+   0xbe840080, 0xd289,
+   0x0903, 0x80048104,
+   0xd2890001, 0x0903,
+   0x80048104, 0xd2890002,
+   0x0903, 0x80048104,
+   0xd2890003, 0x0903,
+   0x80048104, 0xc069003a,
+   0x0070, 0xbf8cc07f,
+   0x80709070, 0xbf06c004,
+   0xbf84ffee, 0xbf820008,
0xe0724000, 0x701d,
0xe0724100, 0x701d0100,
0xe0724200, 0x701d0200,
0xe0724300, 0x701d0300,
0xbefe00c1, 0xbeff00c1,
0xb8fb4306, 0x867bc17b,
-   0xbf84002c, 0xbf8a,
+   0xbf840063, 0xbf8a,
0x867aff6f, 0x0400,
-   0xbf840028, 0x8e7b867b,
+   0xbf84005f, 0x8e7b867b,
0x8e7b827b, 0xbef6007b,
0xb8f02a05, 0x80708170,
0x8e708a70, 0xb8fa1605,
@@ -422,144 +464,215 @@ static const uint32_t cwsr_trap_gfx9_hex[] = {
0x0100, 0xbefc0080,
0xd28c0002, 0x000100c1,
0xd28d0003, 0x000204c1,
-   0xd1060002, 0x00011103,
-   0x7e0602ff, 0x0200,
-   0xbefc00ff, 0x0001,
-   0xbe800077, 0x8677ff77,
-   0xff7f, 0x8777ff77,
-   0x00058000, 0xd8ec,
-   0x0002, 0xbf8cc07f,
-   0xe0765000, 0x701d0002,
-   0x68040702, 0xd0c9006a,
-   0xf702, 0xbf87fff7,
-   0xbef7, 0xbef000ff,
-   0x0400, 0xbefe00c1,
-   0xbeff00c1, 0xb8fb2a05,
-   0x807b817b, 0x8e7b827b,
-   0x8e76887b, 0xbef600ff,
-   0x0100, 0xbefc0084,
-   0xbf0a7b7c, 0xbf840015,
-   0xbf11017c, 0x807bff7b,
-   0x1000, 0x7e000300,
-   0x7e020301, 0x7e040302,
-   0x7e060303, 0xe0724000,
-   0x701d, 0xe0724100,
-   0x701d0100, 0xe0724200,
-   0x701d0200, 0xe0724300,
-   0x701d0300, 0x807c847c,
-   0x8070ff70, 0x0400,
-   0xbf0a7b7c, 0xbf85ffef,
-   0xbf9c, 0xbf8200da,
-   0xbef4007e, 0x8675ff7f,
-   0x, 0x8775ff75,
-   0x0004, 0xbef60080,
-   0xbef700ff, 0x00807fac,
-   0x866eff7f, 0x0800,
-   0x8f6e836e, 0x87776e77,
-   0x866eff7f, 0x7000,
-   0x8f6e816e, 0x87776e77,
-   0x866eff7f, 0x0400,
-   0xbf84001e, 0xbefe00c1,
-   0xbeff00c1, 0xb8ef4306,
-   0x866fc16f, 0xbf840019,
-   0x8e6f866f, 0x8e6f826f,
-   0xbef6006f, 0xb8f82a05,
-   0x80788178, 0x8e788a78,
-   0xb8ee1605, 0x806e816e,
-   0x8e6e866e, 0x80786e78,
-   0x8078ff78, 0x0080,
-   0xbef600ff, 0x0100,
-   0xbefc0080, 0xe051,
-   0x781d, 0xe0510100,
-   0x781d, 0x807cff7c,
-   0x0200, 0x8078ff78,
-  

[PATCH 2/2] drm/amdkfd: Fix lost single step exceptions in gfx9 trap handler

[Cornwall, Jay]

If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised
concurrently the handler cannot identify the source of the exception.
This causes the debugger to lose single step exception notification
when a context save request arrives at the same time.

When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled)
jump to the second-level trap handler upon entering the trap. The
second-level trap will set STATUS.HALT=1 and return to the shader.
If SAVECTX was raised then control flow will return to the trap, which
will then handle the context save request.

Cc: Tony Tye 
Cc: Laurent Morichetti 
Cc: Qingchuan Shi 
Signed-off-by: Jay Cornwall 
---
 drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 1418 ++--
 .../gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm  |   20 +
 2 files changed, 733 insertions(+), 705 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h 
b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
index 7274baf..4275940 100644
--- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
+++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
@@ -274,405 +274,409 @@ static const uint32_t cwsr_trap_gfx8_hex[] = {
 
 
 static const uint32_t cwsr_trap_gfx9_hex[] = {
-   0xbf820001, 0xbf820241,
+   0xbf820001, 0xbf820248,
0xb8f8f802, 0x89788678,
-   0xb8fbf803, 0x866eff7b,
-   0x0400, 0xbf85003b,
-   0x866eff7b, 0x0800,
-   0xbf850003, 0x866eff7b,
-   0x0100, 0xbf84000c,
+   0xb8eef801, 0x866eff6e,
+   0x0800, 0xbf840003,
0x866eff78, 0x2000,
-   0xbf840005, 0xbf8e0010,
-   0xb8eef803, 0x866eff6e,
-   0x0400, 0xbf84fffb,
-   0x8778ff78, 0x2000,
-   0x80ec886c, 0x82ed806d,
-   0xb8eef807, 0x866fff6e,
-   0x001f8000, 0x8e6f8b6f,
-   0x8977ff77, 0xfc00,
-   0x87776f77, 0x896eff6e,
-   0x001f8000, 0xb96ef807,
-   0xb8faf812, 0xb8fbf813,
-   0x8efa887a, 0xc0071bbd,
-   0x, 0xbf8cc07f,
-   0xc0071ebd, 0x0008,
-   0xbf8cc07f, 0x86ee6e6e,
-   0xbf840001, 0xbe801d6e,
-   0xb8fbf803, 0x867bff7b,
-   0x01ff, 0xbf850002,
-   0x806c846c, 0x826d806d,
+   0xbf840016, 0xb8fbf803,
+   0x866eff7b, 0x0400,
+   0xbf85003b, 0x866eff7b,
+   0x0800, 0xbf850003,
+   0x866eff7b, 0x0100,
+   0xbf84000c, 0x866eff78,
+   0x2000, 0xbf840005,
+   0xbf8e0010, 0xb8eef803,
+   0x866eff6e, 0x0400,
+   0xbf84fffb, 0x8778ff78,
+   0x2000, 0x80ec886c,
+   0x82ed806d, 0xb8eef807,
+   0x866fff6e, 0x001f8000,
+   0x8e6f8b6f, 0x8977ff77,
+   0xfc00, 0x87776f77,
+   0x896eff6e, 0x001f8000,
+   0xb96ef807, 0xb8faf812,
+   0xb8fbf813, 0x8efa887a,
+   0xc0071bbd, 0x,
+   0xbf8cc07f, 0xc0071ebd,
+   0x0008, 0xbf8cc07f,
+   0x86ee6e6e, 0xbf840001,
+   0xbe801d6e, 0xb8fbf803,
+   0x867bff7b, 0x01ff,
+   0xbf850002, 0x806c846c,
+   0x826d806d, 0x866dff6d,
+   0x, 0x8f6e8b77,
+   0x866eff6e, 0x001f8000,
+   0xb96ef807, 0x86fe7e7e,
+   0x86ea6a6a, 0x8f6e8378,
+   0xb96ee0c2, 0xbf82,
+   0xb9780002, 0xbe801f6c,
0x866dff6d, 0x,
-   0x8f6e8b77, 0x866eff6e,
-   0x001f8000, 0xb96ef807,
-   0x86fe7e7e, 0x86ea6a6a,
-   0x8f6e8378, 0xb96ee0c2,
-   0xbf82, 0xb9780002,
-   0xbe801f6c, 0x866dff6d,
-   0x, 0xbefa0080,
-   0xb97a0283, 0xb8fa2407,
-   0x8e7a9b7a, 0x876d7a6d,
-   0xb8fa03c7, 0x8e7a9a7a,
-   0x876d7a6d, 0xb8faf807,
-   0x867aff7a, 0x7fff,
-   0xb97af807, 0xbeee007e,
-   0xbeef007f, 0xbefe0180,
-   0xbf94, 0x877a8478,
-   0xb97af802, 0xbf8e0002,
-   0xbf88fffe, 0xb8fa2a05,
-   0x807a817a, 0x8e7a8a7a,
-   0xb8fb1605, 0x807b817b,
-   0x8e7b867b, 0x807a7b7a,
-   0x807a7e7a, 0x827b807f,
-   0x867bff7b, 0x,
-   0xc04b1c3d, 0x0050,
-   0xbf8cc07f, 0xc04b1d3d,
-   0x0060, 0xbf8cc07f,
-   0xc0431e7d, 0x0074,
-   0xbf8cc07f, 0xbef4007e,
-   0x8675ff7f, 0x,
-   0x8775ff75, 0x0004,
-   0xbef60080, 0xbef700ff,
-   0x00807fac, 0x867aff7f,
-   0x0800, 0x8f7a837a,
-   0x8a77, 0x867aff7f,
-   0x7000, 0x8f7a817a,
-   0x8a77, 0xbef1007c,
-   0xbef00080, 0xb8f02a05,
-   0x80708170, 0x8e708a70,
-   0xb8fa1605, 0x807a817a,
-   0x8e7a867a, 0x80707a70,
-   0xbef60084, 0xbef600ff,
-   0x0100, 0xbefe007c,
-   0xbefc0070, 0xc0611c7a,
-   0x007c, 0xbf8cc07f,
-   0x80708470, 0xbefc007e,
+   0xbefa0080, 0xb97a0283,
+   0xb8fa2407, 0x8e7a9b7a,
+   0x876d7a6d, 0xb8fa03c7,
+   0x8e7a9a7a, 0x876d7a6d,
+   0xb8faf807, 0x867aff7a,
+   0x7fff, 0xb97af807,
+   0xbeee007e, 0xbeef007f,
+   0xbefe0180, 0xbf94,
+   0x877a8478, 0xb97af802,
+   0xbf8e0002, 0xbf88fffe,
+   0xb8fa2a05, 

Re: [PATCH 3/3] drm/amdgpu/powerplay/vega12: call PrepareMp1ForUnload in power_off_asic

[Grodzovsky, Andrey]

Series is Acked-by: Andrey Grodzovsky 

Andrey

On 7/23/19 1:00 PM, Alex Deucher wrote:
> Needed to make sure the smu is idle when resetting. This may fix
> sporatic failures with GPU reset.
>
> Signed-off-by: Alex Deucher 
> ---
>   drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 5 +
>   1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index efb6d3762feb..3d3504411b63 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -2468,6 +2468,11 @@ static int vega12_power_off_asic(struct pp_hwmgr 
> *hwmgr)
>   );
>   data->water_marks_bitmap &= ~(WaterMarksLoaded);
>   
> + PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
> + PPSMC_MSG_PrepareMp1ForUnload)) == 0,
> + "[PrepareMp1ForUnload] Failed!",
> + return result);
> +
>   return result;
>   }
>   
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Re: [PATCH v2 0/2] This series enables S/G for Picasso.

[Deucher, Alexander]

Series is: Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Andrey 
Grodzovsky 
Sent: Tuesday, July 23, 2019 2:25 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Grodzovsky, Andrey 
; Wu, Hersen ; Koenig, 
Christian ; S, Shirish 
Subject: [PATCH v2 0/2] This series enables S/G for Picasso.

First patch fix a hard hang introduced by placing the display
BO in GTT memory because of HW issues with cached mappings
and the second patch enables S/G.

Andrey Grodzovsky (1):
  drm/amdgpu: Fix hard hang for S/G display BOs.

Shirish S (1):
  drm/amd: enable S/G for RAVEN chip

 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c   | 13 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c|  7 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c   |  3 ++-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  2 +-
 4 files changed, 17 insertions(+), 8 deletions(-)

--
2.7.4

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[PATCH 1/9] drm/dp: Use non-cyclic idr

[sunpeng.li]

From: Leo Li 

In preparation for adding aux devices for DP MST, make the IDR
non-cyclic. That way, hotplug cycling MST devices won't needlessly
increment the minor version index.

Signed-off-by: Leo Li 
Reviewed-by: Lyude Paul 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/drm_dp_aux_dev.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 5be28e3295f3..26e38dacf654 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -82,8 +82,7 @@ static struct drm_dp_aux_dev *alloc_drm_dp_aux_dev(struct 
drm_dp_aux *aux)
kref_init(&aux_dev->refcount);
 
mutex_lock(&aux_idr_mutex);
-   index = idr_alloc_cyclic(&aux_idr, aux_dev, 0, DRM_AUX_MINORS,
-GFP_KERNEL);
+   index = idr_alloc(&aux_idr, aux_dev, 0, DRM_AUX_MINORS, GFP_KERNEL);
mutex_unlock(&aux_idr_mutex);
if (index < 0) {
kfree(aux_dev);
-- 
2.22.0

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[PATCH 2/9 v3] drm/dp_mst: Enable registration of AUX devices for MST ports

[sunpeng.li]

From: Ville Syrjälä 

All available downstream ports - physical and logical - are exposed for
each MST device. They are listed in /dev/, following the same naming
scheme as SST devices by appending an incremental ID.

Although all downstream ports are exposed, only some will work as
expected. Consider the following topology:

   +-+
   |  ASIC   |
   +-+
  Conn-0|
|
   +v+
  +| MST HUB |+
  |+-+|
  |   |
  |Port-1   Port-2|
+-v-+   +-v-+
|  MST  |   |  SST  |
|  Display  |   |  Display  |
+---+   +---+
  |Port-1
  x

 MST Path  | MST Device
 --+--
 sst:0 | MST Hub
 mst:0-1   | MST Display
 mst:0-1-1 | MST Display's disconnected DP out
 mst:0-1-8 | MST Display's internal sink
 mst:0-2   | SST Display

On certain MST displays, the upstream physical port will ACK DPCD reads.
However, reads on the local logical port to the internal sink will
*NAK*. i.e. reading mst:0-1 ACKs, but mst:0-1-8 NAKs.

There may also be duplicates. Some displays will return the same GUID
when reading DPCD from both mst:0-1 and mst:0-1-8.

There are some device-dependent behavior as well. The MST hub used
during testing will actually *ACK* read requests on a disconnected
physical port, whereas the MST displays will NAK.

In light of these discrepancies, it's simpler to expose all downstream
ports - both physical and logical - and let the user decide what to use.

v3 changes:
* Change WARN_ON_ONCE -> DRM_ERROR on dpcd read errors
* Docstring and cosmetic fixes

v2 changes:

Moved remote aux device (un)registration to new mst connector late
register and early unregister helpers. Drivers should call these from
their own mst connector function hooks.

This is to solve an issue during driver unload, where mst connector
devices are unregistered before the remote aux devices are. In a setup
where aux devices are created as children of connector devices, the aux
device would be removed too early, and uncleanly. Doing so in
early_unregister solves this issue, as that is called before connector
unregistration.

Signed-off-by: Ville Syrjälä 
Signed-off-by: Leo Li 
Reviewed-by: Lyude Paul 
---
 drivers/gpu/drm/drm_dp_aux_dev.c  |  15 ++-
 drivers/gpu/drm/drm_dp_mst_topology.c | 144 --
 include/drm/drm_dp_helper.h   |   4 +
 include/drm/drm_dp_mst_helper.h   |  11 ++
 4 files changed, 162 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/drm_dp_aux_dev.c b/drivers/gpu/drm/drm_dp_aux_dev.c
index 26e38dacf654..0cfb386754c3 100644
--- a/drivers/gpu/drm/drm_dp_aux_dev.c
+++ b/drivers/gpu/drm/drm_dp_aux_dev.c
@@ -37,6 +37,7 @@
 
 #include 
 #include 
+#include 
 #include 
 
 #include "drm_crtc_helper_internal.h"
@@ -162,7 +163,12 @@ static ssize_t auxdev_read_iter(struct kiocb *iocb, struct 
iov_iter *to)
break;
}
 
-   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+   if (aux_dev->aux->is_remote)
+   res = drm_dp_mst_dpcd_read(aux_dev->aux, pos, buf,
+  todo);
+   else
+   res = drm_dp_dpcd_read(aux_dev->aux, pos, buf, todo);
+
if (res <= 0)
break;
 
@@ -209,7 +215,12 @@ static ssize_t auxdev_write_iter(struct kiocb *iocb, 
struct iov_iter *from)
break;
}
 
-   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+   if (aux_dev->aux->is_remote)
+   res = drm_dp_mst_dpcd_write(aux_dev->aux, pos, buf,
+   todo);
+   else
+   res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
+
if (res <= 0)
break;
 
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c 
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 0984b9a34d55..4733d3350ede 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -36,6 +36,8 @@
 #include 
 #include 
 
+#include "drm_crtc_helper_internal.h"
+
 /**
  * DOC: dp mst helper
  *
@@ -53,6 +55,9 @@ static int drm_dp_dpcd_write_payload(struct 
drm_dp_mst_topology_mgr *mgr,
 int id,
 struct drm_dp_payload *payload);
 
+static int drm_dp_send_dpcd_read(struct drm_dp_mst_topology_mgr *mgr,
+struct drm_dp_mst_port *port,
+int offset, int size, u8 *bytes);
 static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr,
  struct drm_dp_mst_port *port,
  

[PATCH 3/9] drm/nouveau: Use connector kdev as aux device parent

[sunpeng.li]

From: Leo Li 

Set the connector's kernel device as the parent for the aux kernel
device. This allows udev rules to access connector attributes when
creating symlinks to aux devices.

Cc: Ben Skeggs 
Signed-off-by: Leo Li 
Reviewed-by: Lyude Paul 
---
 drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c 
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 8f15281faa79..330d7d29a6e3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -1349,7 +1349,7 @@ nouveau_connector_create(struct drm_device *dev,
break;
case DRM_MODE_CONNECTOR_DisplayPort:
case DRM_MODE_CONNECTOR_eDP:
-   nv_connector->aux.dev = dev->dev;
+   nv_connector->aux.dev = connector->kdev;
nv_connector->aux.transfer = nouveau_connector_aux_xfer;
snprintf(aux_name, sizeof(aux_name), "sor-%04x-%04x",
 dcbe->hasht, dcbe->hashm);
-- 
2.22.0

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[PATCH 5/9] drm/amd/display: Use connector kdev as aux device parent

[sunpeng.li]

From: Leo Li 

Set the connector's kernel device as the parent for the aux kernel
device. This allows udev rules to access connector attributes when
creating symlinks to aux devices.

For example, the following udev rule:

SUBSYSTEM=="drm_dp_aux_dev", SUBSYSTEMS=="drm", ATTRS{edid}=="*",
SYMLINK+="drm_dp_aux/by-name/$id"

Will create the following symlinks using the connector's name:

$ ls /dev/drm_dp_aux/by-name/
card0-DP-1  card0-DP-2  card0-DP-3

Cc: Nicholas Kazlauskas 
Cc: Jerry (Fangzhi) Zuo 
Cc: Harry Wentland 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 6e205ee36ac3..53d2cfe62e13 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -388,7 +388,7 @@ void amdgpu_dm_initialize_dp_connector(struct 
amdgpu_display_manager *dm,
   struct amdgpu_dm_connector *aconnector)
 {
aconnector->dm_dp_aux.aux.name = "dmdc";
-   aconnector->dm_dp_aux.aux.dev = dm->adev->dev;
+   aconnector->dm_dp_aux.aux.dev = aconnector->base.kdev;
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
 
-- 
2.22.0

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[PATCH 6/9 v2] drm/i915: Implement MST Aux device registration

[sunpeng.li]

From: Leo Li 

Implement late_register and early_unregister hooks for MST connectors.
Call drm helpers for MST connector registration, which registers the
AUX devices.

Signed-off-by: Leo Li 

v2 changes:
Unwind intel_connector_register on mst late register failure.
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 33 +++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 60652ebbdf61..0633ebf3f1bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -400,13 +400,42 @@ intel_dp_mst_detect(struct drm_connector *connector, bool 
force)
  intel_connector->port);
 }
 
+static int
+intel_dp_mst_connector_late_register(struct drm_connector *connector)
+{
+   struct intel_connector *intel_connector = to_intel_connector(connector);
+   struct drm_dp_mst_port *port = intel_connector->port;
+
+   int ret;
+
+   ret = intel_connector_register(connector);
+   if (ret)
+   return ret;
+
+   ret = drm_dp_mst_connector_late_register(connector, port);
+   if (ret)
+   intel_connector_unregister(connector);
+
+   return ret;
+}
+
+static void
+intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
+{
+   struct intel_connector *intel_connector = to_intel_connector(connector);
+   struct drm_dp_mst_port *port = intel_connector->port;
+
+   drm_dp_mst_connector_early_unregister(connector, port);
+   intel_connector_unregister(connector);
+}
+
 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
.detect = intel_dp_mst_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.atomic_get_property = intel_digital_connector_atomic_get_property,
.atomic_set_property = intel_digital_connector_atomic_set_property,
-   .late_register = intel_connector_register,
-   .early_unregister = intel_connector_unregister,
+   .late_register = intel_dp_mst_connector_late_register,
+   .early_unregister = intel_dp_mst_connector_early_unregister,
.destroy = intel_connector_destroy,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_duplicate_state = intel_digital_connector_duplicate_state,
-- 
2.22.0

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[PATCH 7/9] drm/nouveau/kms/nv50: Implement MST Aux device registration

[sunpeng.li]

From: Leo Li 

Implement late_register and early_unregister hooks for MST connectors.
Call drm helpers for MST connector registration, which registers the
AUX devices.

Cc: Ben Skeggs 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/nouveau/dispnv50/disp.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c 
b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 8497768f1b41..0d6e9350ba44 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -1024,6 +1024,24 @@ nv50_mstc_destroy(struct drm_connector *connector)
kfree(mstc);
 }
 
+static int
+nv50_mstc_late_register(struct drm_connector *connector)
+{
+   struct nv50_mstc *mstc = nv50_mstc(connector);
+   struct drm_dp_mst_port *port = mstc->port;
+
+   return drm_dp_mst_connector_late_register(connector, port);
+}
+
+static void
+nv50_mstc_early_unregister(struct drm_connector *connector)
+{
+   struct nv50_mstc *mstc = nv50_mstc(connector);
+   struct drm_dp_mst_port *port = mstc->port;
+
+   drm_dp_mst_connector_early_unregister(connector, port);
+}
+
 static const struct drm_connector_funcs
 nv50_mstc = {
.reset = nouveau_conn_reset,
@@ -1034,6 +1052,8 @@ nv50_mstc = {
.atomic_destroy_state = nouveau_conn_atomic_destroy_state,
.atomic_set_property = nouveau_conn_atomic_set_property,
.atomic_get_property = nouveau_conn_atomic_get_property,
+   .late_register = nv50_mstc_late_register,
+   .early_unregister = nv50_mstc_early_unregister,
 };
 
 static int
-- 
2.22.0

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[PATCH 0/9] MST AUX Devices (v3)

[sunpeng.li]

From: Leo Li 

Here's what changed in v3:

* Dropped patch to expose the mst-path device attribute, in lieu of
  ongoing discussion for defining a better connector path property
* Change WARN_ON_ONCE -> DRM_ERROR on MST dpcd read errors to avoid
  tainting the kernel
* Unwind intel_connector_register() on
  drm_dp_mst_connector_late_register() failure.
* Docstring and cosmetic fixes

Leo Li (8):
  drm/dp: Use non-cyclic idr
  drm/nouveau: Use connector kdev as aux device parent
  drm/bridge/analogix-anx78xx: Use connector kdev as aux device parent
  drm/amd/display: Use connector kdev as aux device parent
  drm/i915: Implement MST Aux device registration (v2)
  drm/nouveau/kms/nv50: Implement MST Aux device registration
  drm/radeon: Implement MST Aux device registration
  drm/amd/display: Implement MST Aux device registration

Ville Syrjälä (1):
  drm/dp_mst: Enable registration of AUX devices for MST ports

 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  26 +++-
 drivers/gpu/drm/bridge/analogix-anx78xx.c |  22 +--
 drivers/gpu/drm/drm_dp_aux_dev.c  |  18 ++-
 drivers/gpu/drm/drm_dp_mst_topology.c | 144 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  33 +++-
 drivers/gpu/drm/nouveau/dispnv50/disp.c   |  20 +++
 drivers/gpu/drm/nouveau/nouveau_connector.c   |   2 +-
 drivers/gpu/drm/radeon/radeon_dp_mst.c|  22 +++
 include/drm/drm_dp_helper.h   |   4 +
 include/drm/drm_dp_mst_helper.h   |  11 ++
 10 files changed, 272 insertions(+), 30 deletions(-)

-- 
2.22.0

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[PATCH 9/9] drm/amd/display: Implement MST Aux device registration

[sunpeng.li]

From: Leo Li 

Implement late_register and early_unregister hooks for MST connectors.
Call drm helpers for MST connector registration, which registers the
AUX devices.

Cc: Jerry Zuo 
Cc: Nicholas Kazlauskas 
Cc: Harry Wentland 
Signed-off-by: Leo Li 
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 24 ++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 53d2cfe62e13..16218a202b59 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -156,6 +156,26 @@ dm_dp_mst_connector_destroy(struct drm_connector 
*connector)
kfree(amdgpu_dm_connector);
 }
 
+static int
+amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
+{
+   struct amdgpu_dm_connector *amdgpu_dm_connector =
+   to_amdgpu_dm_connector(connector);
+   struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+
+   return drm_dp_mst_connector_late_register(connector, port);
+}
+
+static void
+amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
+{
+   struct amdgpu_dm_connector *amdgpu_dm_connector =
+   to_amdgpu_dm_connector(connector);
+   struct drm_dp_mst_port *port = amdgpu_dm_connector->port;
+
+   drm_dp_mst_connector_early_unregister(connector, port);
+}
+
 static const struct drm_connector_funcs dm_dp_mst_connector_funcs = {
.detect = dm_dp_mst_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -164,7 +184,9 @@ static const struct drm_connector_funcs 
dm_dp_mst_connector_funcs = {
.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
-   .atomic_get_property = amdgpu_dm_connector_atomic_get_property
+   .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
+   .late_register = amdgpu_dm_mst_connector_late_register,
+   .early_unregister = amdgpu_dm_mst_connector_early_unregister,
 };
 
 static int dm_dp_mst_get_modes(struct drm_connector *connector)
-- 
2.22.0

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[PATCH 4/9] drm/bridge/analogix-anx78xx: Use connector kdev as aux device parent

[sunpeng.li]

From: Leo Li 

Set the connector's kernel device as the parent for the aux kernel
device. This allows udev rules to access connector attributes when
creating symlinks to aux devices.

To do so, the connector needs to be registered beforehand. Therefore,
shift aux registration to be after connector registration.

Cc: Enric Balletbo i Serra 
Cc: Nicolas Boichat 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/bridge/analogix-anx78xx.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix-anx78xx.c 
b/drivers/gpu/drm/bridge/analogix-anx78xx.c
index 3c7cc5af735c..c2800cd3e2ee 100644
--- a/drivers/gpu/drm/bridge/analogix-anx78xx.c
+++ b/drivers/gpu/drm/bridge/analogix-anx78xx.c
@@ -1008,17 +1008,6 @@ static int anx78xx_bridge_attach(struct drm_bridge 
*bridge)
return -ENODEV;
}
 
-   /* Register aux channel */
-   anx78xx->aux.name = "DP-AUX";
-   anx78xx->aux.dev = &anx78xx->client->dev;
-   anx78xx->aux.transfer = anx78xx_aux_transfer;
-
-   err = drm_dp_aux_register(&anx78xx->aux);
-   if (err < 0) {
-   DRM_ERROR("Failed to register aux channel: %d\n", err);
-   return err;
-   }
-
err = drm_connector_init(bridge->dev, &anx78xx->connector,
 &anx78xx_connector_funcs,
 DRM_MODE_CONNECTOR_DisplayPort);
@@ -1038,6 +1027,17 @@ static int anx78xx_bridge_attach(struct drm_bridge 
*bridge)
 
anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
 
+   /* Register aux channel */
+   anx78xx->aux.name = "DP-AUX";
+   anx78xx->aux.dev = anx78xx->connector.kdev;
+   anx78xx->aux.transfer = anx78xx_aux_transfer;
+
+   err = drm_dp_aux_register(&anx78xx->aux);
+   if (err < 0) {
+   DRM_ERROR("Failed to register aux channel: %d\n", err);
+   return err;
+   }
+
err = drm_connector_attach_encoder(&anx78xx->connector,
   bridge->encoder);
if (err) {
-- 
2.22.0

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[PATCH 8/9] drm/radeon: Implement MST Aux device registration

[sunpeng.li]

From: Leo Li 

Implement late_register and early_unregister hooks for MST connectors.
Call drm helpers for MST connector registration, which registers the
AUX devices.

Cc: Alex Deucher 
Cc: Harry Wentland 
Signed-off-by: Leo Li 
---
 drivers/gpu/drm/radeon/radeon_dp_mst.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c 
b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index 2994f07fbad9..2d53699734fb 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -260,11 +260,33 @@ radeon_dp_mst_connector_destroy(struct drm_connector 
*connector)
kfree(radeon_connector);
 }
 
+static int
+radeon_dp_mst_connector_late_register(struct drm_connector *connector)
+{
+   struct radeon_connector *radeon_connector =
+   to_radeon_connector(connector);
+   struct drm_dp_mst_port *port = radeon_connector->port;
+
+   return drm_dp_mst_connector_late_register(connector, port);
+}
+
+static void
+radeon_dp_mst_connector_early_unregister(struct drm_connector *connector)
+{
+   struct radeon_connector *radeon_connector =
+   to_radeon_connector(connector);
+   struct drm_dp_mst_port *port = radeon_connector->port;
+
+   drm_dp_mst_connector_early_unregister(connector, port);
+}
+
 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
.dpms = drm_helper_connector_dpms,
.detect = radeon_dp_mst_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = radeon_dp_mst_connector_destroy,
+   .late_register = radeon_dp_mst_connector_late_register,
+   .early_unregister = radeon_dp_mst_connector_early_unregister,
 };
 
 static struct drm_connector *radeon_dp_add_mst_connector(struct 
drm_dp_mst_topology_mgr *mgr,
-- 
2.22.0

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RE: [PATCH 3/3] drm/amdgpu/powerplay/vega12: call PrepareMp1ForUnload in power_off_asic

[Quan, Evan]

No. Hold on. Let me discuss this internally.

Regards,
Evan
> -Original Message-
> From: amd-gfx  On Behalf Of
> Grodzovsky, Andrey
> Sent: Wednesday, July 24, 2019 4:01 AM
> To: Alex Deucher ; amd-
> g...@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH 3/3] drm/amdgpu/powerplay/vega12: call
> PrepareMp1ForUnload in power_off_asic
> 
> Series is Acked-by: Andrey Grodzovsky 
> 
> Andrey
> 
> On 7/23/19 1:00 PM, Alex Deucher wrote:
> > Needed to make sure the smu is idle when resetting. This may fix
> > sporatic failures with GPU reset.
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >   drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 5 +
> >   1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > index efb6d3762feb..3d3504411b63 100644
> > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> > @@ -2468,6 +2468,11 @@ static int vega12_power_off_asic(struct
> pp_hwmgr *hwmgr)
> > );
> > data->water_marks_bitmap &= ~(WaterMarksLoaded);
> >
> > +   PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
> > +   PPSMC_MSG_PrepareMp1ForUnload)) == 0,
> > +   "[PrepareMp1ForUnload] Failed!",
> > +   return result);
> > +
> > return result;
> >   }
> >
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Re: kernel panic: stack is corrupted in pointer

[syzbot]

Hello,

syzbot has tested the proposed patch and the reproducer did not trigger  
crash:


Reported-and-tested-by:  
syzbot+79f5f028005a77ecb...@syzkaller.appspotmail.com


Tested on:

commit: decb705e libbpf: fix using uninitialized ioctl results
git tree:   bpf
kernel config:  https://syzkaller.appspot.com/x/.config?x=87305c3ca9c25c70
compiler:   gcc (GCC) 9.0.0 20181231 (experimental)

Note: testing is done by a robot and is best-effort only.

RE: [PATCH] drm/amd/powerplay: fix temperature granularity error in smu11

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Kevin(Yang) 
Sent: Tuesday, July 23, 2019 8:08 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Huang, Ray ; Quan, 
Evan ; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amd/powerplay: fix temperature granularity error in smu11

in this patch,
drm/amd/powerplay: add callback function of get_thermal_temperature_range the 
driver missed temperature granularity change on other temperature.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 745b35a1600d..735802bb07b9 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1229,15 +1229,15 @@ static int smu_v11_0_start_thermal_control(struct 
smu_context *smu)
return ret;
}
 
-   adev->pm.dpm.thermal.min_temp = range.min;
-   adev->pm.dpm.thermal.max_temp = range.max;
-   adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max;
-   adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
-   adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max;
-   adev->pm.dpm.thermal.max_hotspot_emergency_temp = 
range.hotspot_emergency_max;
-   adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
-   adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max;
-   adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max;
+   adev->pm.dpm.thermal.min_temp = range.min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_temp = range.max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_edge_emergency_temp = range.edge_emergency_max 
* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_hotspot_crit_temp = range.hotspot_crit_max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_hotspot_emergency_temp = 
range.hotspot_emergency_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.min_mem_temp = range.mem_min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_mem_crit_temp = range.mem_crit_max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   adev->pm.dpm.thermal.max_mem_emergency_temp = range.mem_emergency_max 
+* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
adev->pm.dpm.thermal.min_temp = range.min * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
adev->pm.dpm.thermal.max_temp = range.max * 
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 
--
2.22.0

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RE: [PATCH] drm/amd/powerplay: fix temperature granularity error in smu11

[Quan, Evan]

Better to combine this with previous ptach(drm/amd/powerplay: add callback 
function of get_thermal_temperature_range) as one.
Since this issue to fix was actually introduced by that patch.
 
But if the original patch was already submitted, it's OK to commit this 
separately.

Either way, this way is Reviewed-by: Evan Quan 

Regards,
Evan
> -Original Message-
> From: Wang, Kevin(Yang) 
> Sent: Tuesday, July 23, 2019 8:08 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth ; Huang, Ray
> ; Quan, Evan ; Wang,
> Kevin(Yang) 
> Subject: [PATCH] drm/amd/powerplay: fix temperature granularity error in
> smu11
> 
> in this patch,
> drm/amd/powerplay: add callback function of
> get_thermal_temperature_range the driver missed temperature granularity
> change on other temperature.
> 
> Signed-off-by: Kevin Wang 
> ---
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index 745b35a1600d..735802bb07b9 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -1229,15 +1229,15 @@ static int
> smu_v11_0_start_thermal_control(struct smu_context *smu)
>   return ret;
>   }
> 
> - adev->pm.dpm.thermal.min_temp = range.min;
> - adev->pm.dpm.thermal.max_temp = range.max;
> - adev->pm.dpm.thermal.max_edge_emergency_temp =
> range.edge_emergency_max;
> - adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min;
> - adev->pm.dpm.thermal.max_hotspot_crit_temp =
> range.hotspot_crit_max;
> - adev->pm.dpm.thermal.max_hotspot_emergency_temp =
> range.hotspot_emergency_max;
> - adev->pm.dpm.thermal.min_mem_temp = range.mem_min;
> - adev->pm.dpm.thermal.max_mem_crit_temp =
> range.mem_crit_max;
> - adev->pm.dpm.thermal.max_mem_emergency_temp =
> range.mem_emergency_max;
> + adev->pm.dpm.thermal.min_temp = range.min *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_temp = range.max *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_edge_emergency_temp =
> range.edge_emergency_max *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.min_hotspot_temp = range.hotspot_min *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_hotspot_crit_temp =
> range.hotspot_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_hotspot_emergency_temp =
> range.hotspot_emergency_max *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.min_mem_temp = range.mem_min *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_mem_crit_temp =
> range.mem_crit_max * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> + adev->pm.dpm.thermal.max_mem_emergency_temp =
> range.mem_emergency_max
> +* SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>   adev->pm.dpm.thermal.min_temp = range.min *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
>   adev->pm.dpm.thermal.max_temp = range.max *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> 
> --
> 2.22.0

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[PATCH 2/9] drm/amdgpu: add reset_method asic callback for si

[Alex Deucher]

SI always uses the legacy pci based reset.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/si.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 4b1e0c16ac41..904361451650 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1185,6 +1185,12 @@ static int si_asic_reset(struct amdgpu_device *adev)
return 0;
 }
 
+static enum amd_reset_method
+si_asic_reset_method(struct amdgpu_device *adev)
+{
+   return AMD_RESET_METHOD_LEGACY;
+}
+
 static u32 si_get_config_memsize(struct amdgpu_device *adev)
 {
return RREG32(mmCONFIG_MEMSIZE);
@@ -1393,6 +1399,7 @@ static const struct amdgpu_asic_funcs si_asic_funcs =
.read_bios_from_rom = &si_read_bios_from_rom,
.read_register = &si_read_register,
.reset = &si_asic_reset,
+   .reset_method = &si_asic_reset_method,
.set_vga_state = &si_vga_set_state,
.get_xclk = &si_get_xclk,
.set_uvd_clocks = &si_set_uvd_clocks,
-- 
2.20.1

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[PATCH 3/9] drm/amdgpu: add reset_method asic callback for cik

[Alex Deucher]

CIK always uses the legacy pci based reset.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/cik.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 3a4f20766a39..7b63d7a8298a 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1290,6 +1290,12 @@ static int cik_asic_reset(struct amdgpu_device *adev)
return r;
 }
 
+static enum amd_reset_method
+cik_asic_reset_method(struct amdgpu_device *adev)
+{
+   return AMD_RESET_METHOD_LEGACY;
+}
+
 static u32 cik_get_config_memsize(struct amdgpu_device *adev)
 {
return RREG32(mmCONFIG_MEMSIZE);
@@ -1822,6 +1828,7 @@ static const struct amdgpu_asic_funcs cik_asic_funcs =
.read_bios_from_rom = &cik_read_bios_from_rom,
.read_register = &cik_read_register,
.reset = &cik_asic_reset,
+   .reset_method = &cik_asic_reset_method,
.set_vga_state = &cik_vga_set_state,
.get_xclk = &cik_get_xclk,
.set_uvd_clocks = &cik_set_uvd_clocks,
-- 
2.20.1

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[PATCH 1/9] drm/amdgpu: add an asic callback to determine the reset method

[Alex Deucher]

Sometimes the driver may have to behave differently depending
on the method we are using to reset the GPU.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4b514a44184c..6c49c23f9961 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -532,6 +532,14 @@ struct amdgpu_allowed_register_entry {
bool grbm_indexed;
 };
 
+enum amd_reset_method {
+   AMD_RESET_METHOD_LEGACY = 0,
+   AMD_RESET_METHOD_MODE0,
+   AMD_RESET_METHOD_MODE1,
+   AMD_RESET_METHOD_MODE2,
+   AMD_RESET_METHOD_BACO
+};
+
 /*
  * ASIC specific functions.
  */
@@ -543,6 +551,7 @@ struct amdgpu_asic_funcs {
 u32 sh_num, u32 reg_offset, u32 *value);
void (*set_vga_state)(struct amdgpu_device *adev, bool state);
int (*reset)(struct amdgpu_device *adev);
+   enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
/* get the reference clock */
u32 (*get_xclk)(struct amdgpu_device *adev);
/* MM block clocks */
@@ -1109,6 +1118,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
  */
 #define amdgpu_asic_set_vga_state(adev, state) 
(adev)->asic_funcs->set_vga_state((adev), (state))
 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
+#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
 #define amdgpu_asic_set_uvd_clocks(adev, v, d) 
(adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) 
(adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
-- 
2.20.1

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[PATCH 9/9] drm/amdgpu/powerplay/vega120: only use PrepareMp1ForUnload for mode1 reset

[Alex Deucher]

Use PrepareMp1ForUnload for mode1 reset and PrepareMp1ForShutdown for
baco reset.

Signed-off-by: Alex Deucher 
---
 .../gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index e16d6654692f..c3d2b32f0b66 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -3756,6 +3756,7 @@ static int vega20_disable_dpm_tasks(struct pp_hwmgr 
*hwmgr)
 static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
 {
struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+   struct amdgpu_device *adev = hwmgr->adev;
int result;
 
result = vega20_disable_dpm_tasks(hwmgr);
@@ -3764,10 +3765,19 @@ static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
);
data->water_marks_bitmap &= ~(WaterMarksLoaded);
 
-   PP_ASSERT_WITH_CODE((result = smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_PrepareMp1ForUnload)) == 0,
-   "[PrepareMp1ForUnload] Failed!",
-   return result);
+   if (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE1) {
+   PP_ASSERT_WITH_CODE((result =
+smum_send_msg_to_smc(hwmgr,
+ 
PPSMC_MSG_PrepareMp1ForUnload)) == 0,
+   "[PrepareMp1ForUnload] Failed!",
+   return result);
+   } else {
+   PP_ASSERT_WITH_CODE((result =
+smum_send_msg_to_smc(hwmgr,
+ 
PPSMC_MSG_PrepareMp1ForShutdown)) == 0,
+   "[PrepareMp1ForUnload] Failed!",
+   return result);
+   }
 
return result;
 }
-- 
2.20.1

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