[PATCH] drm/amdgpu: enable MGCG for PCO
From: Likun Gao
Enable MGCG for picasso.
Signed-off-by: Likun Gao
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a136632..4900e49 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -901,7 +901,8 @@ static int soc15_common_early_init(void *handle)
adev->pg_flags = AMD_PG_SUPPORT_SDMA |
AMD_PG_SUPPORT_VCN;
} else if (adev->pdev->device == 0x15d8) {
- adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
+ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+ AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS |
--
2.7.4
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RE: [PATCH] drm/amdgpu: enable MGCG for PCO
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of likun Gao
> Sent: Friday, April 19, 2019 3:21 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huan, Alvin ; Zhou, Hang
> ; Huang, Ray ; Gao, Likun
>
> Subject: [PATCH] drm/amdgpu: enable MGCG for PCO
>
> From: Likun Gao
>
> Enable MGCG for picasso.
>
> Signed-off-by: Likun Gao
Reviewed-by: Huang Rui
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index a136632..4900e49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -901,7 +901,8 @@ static int soc15_common_early_init(void *handle)
>
> adev->pg_flags = AMD_PG_SUPPORT_SDMA |
> AMD_PG_SUPPORT_VCN;
> } else if (adev->pdev->device == 0x15d8) {
> - adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
> + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
> + AMD_CG_SUPPORT_GFX_MGLS |
> AMD_CG_SUPPORT_GFX_CP_LS |
> AMD_CG_SUPPORT_GFX_3D_CGCG |
> AMD_CG_SUPPORT_GFX_3D_CGLS |
> --
> 2.7.4
>
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RE: DMA-buf P2P
Which test are you using? Can share? -David > -Original Message- > From: dri-devel On Behalf Of > Christian K?nig > Sent: Thursday, April 18, 2019 8:09 PM > To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org > Subject: DMA-buf P2P > > Hi guys, > > as promised this is the patch set which enables P2P buffer sharing with DMA- > buf. > > Basic idea is that importers can set a flag noting that they can deal with and > sgt which doesn't contains pages. > > This in turn is the signal to the exporter that we don't need to move a buffer > to system memory any more when a remote device wants to access it. > > Please review and/or comment, > Christian. > > > ___ > dri-devel mailing list > dri-de...@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/include: Add HUBPREQ_DEBUG register offsets
Acked-by: Alex Deucher From: sunpeng...@amd.com Sent: Thursday, April 18, 2019 1:13 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander; Cheng, Tony; Wentland, Harry; StDenis, Tom; Li, Sun peng (Leo) Subject: [PATCH] drm/amd/include: Add HUBPREQ_DEBUG register offsets From: Leo Li They will be used by DC when runing ASIC-specific HUBP initialization. Signed-off-by: Leo Li --- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h index 721c611..5a44e61 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_offset.h @@ -2347,6 +2347,8 @@ #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP0_HUBPREQ_DEBUG 0x056a +#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f @@ -2631,6 +2633,8 @@ #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP1_HUBPREQ_DEBUG 0x062e +#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633 @@ -2915,6 +2919,8 @@ #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP2_HUBPREQ_DEBUG 0x06f2 +#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7 @@ -3199,6 +3205,8 @@ #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define mmHUBP3_HUBPREQ_DEBUG 0x07b6 +#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: Change VRAM lost print from ERR to INF
Maybe change the message to:
VRAM is lost due to GPU reset!
Either way,
Reviewed-by: Alex Deucher
From: amd-gfx on behalf of Andrey
Grodzovsky
Sent: Thursday, April 18, 2019 6:48 PM
To: amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey; Kuehling, Felix
Subject: [PATCH] drm/amdgpu: Change VRAM lost print from ERR to INF
It's normal for VRAM to lost during GPU reset and so change
the log level to INFO to avoid confusing users.
Signed-off-by: Andrey Grodzovsky
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1ecdaeb..69ecbe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3435,7 +3435,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info
*hive,
vram_lost =
amdgpu_device_check_vram_lost(tmp_adev);
if (vram_lost) {
- DRM_ERROR("VRAM is lost!\n");
+ DRM_INFO("VRAM is lost!\n");
atomic_inc(&tmp_adev->vram_lost_counter);
}
--
2.7.4
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Re: [PATCH] drm/amd/amdgpu: fix spelling mistake "recieve" -> "receive"
On 4/18/2019 3:55 PM, Colin King wrote:
From: Colin Ian King
There is a spelling mistake in a pr_err message. Fix it.
Signed-off-by: Colin Ian King
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 6a0fcd67662a..aef9d059ae52 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -515,7 +515,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct
*work)
/* wait until RCV_MSG become 3 */
if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
- pr_err("failed to recieve FLR_CMPL\n");
+ pr_err("failed to receive FLR_CMPL\n");
return;
}
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[PATCH] drm/amd/amdgpu: fix spelling mistake "recieve" -> "receive"
From: Colin Ian King
There is a spelling mistake in a pr_err message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 6a0fcd67662a..aef9d059ae52 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -515,7 +515,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct
*work)
/* wait until RCV_MSG become 3 */
if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
- pr_err("failed to recieve FLR_CMPL\n");
+ pr_err("failed to receive FLR_CMPL\n");
return;
}
--
2.20.1
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Re: [PATCH] drm/amdgpu: Check if smu.ppt_funcs is initialized before accessing
On Thu, Apr 18, 2019 at 12:01 PM wrote:
>
> From: Leo Li
>
> smu.ppt_funcs is only initialized for specific SMU versions.
>
> On a Hawaii ASIC, attempting to access the udev attribute
> ATTRS{power_dpm_state} will cause a null pointer deref in
> amdgpu_get_dpm_state() because of this.
>
> Fix by checking that ppt_funcs is initialized first.
>
> CC: Chengming Gui
> Signed-off-by: Leo Li
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 4b7a076..7993623 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -144,7 +144,7 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
> struct amdgpu_device *adev = ddev->dev_private;
> enum amd_pm_state_type pm;
>
> - if (adev->smu.ppt_funcs->get_current_power_state)
> + if (adev->smu.ppt_funcs &&
> adev->smu.ppt_funcs->get_current_power_state)
For consistency, I think we probably want something like:
if (is_support_sw_smu(adev) && adev->smu.ppt_funcs->get_current_power_state)
Either way:
Reviewed-by: Alex Deucher
> pm = amdgpu_smu_get_current_power_state(adev);
> else if (adev->powerplay.pp_funcs->get_current_power_state)
> pm = amdgpu_dpm_get_current_power_state(adev);
> --
> 2.7.4
>
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[pull] amdgpu drm-next-5.2
Hi Dave, Daniel, More updates for 5.2: - Add the amdgpu specific bits for timeline support - Add internal interfaces for xgmi pstate support - DC Z ordering fixes for planes - Add support for NV12 planes in DC - Add colorspace properties for planes in DC - eDP optimizations if the GOP driver already initialized eDP - DC bandwidth validation tracing support The following changes since commit ecc4946f11a07884f230450a6d5a92337bc21375: Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux into drm-next (2019-04-12 14:46:58 +1000) are available in the Git repository at: git://people.freedesktop.org/~agd5f/linux drm-next-5.2 for you to fetch changes up to f55be0be5b7296e73f1634e2839a1953dc12d11e: drm/amd/display: Add profiling tools for bandwidth validation (2019-04-15 00:22:19 -0500) Anthony Koo (2): drm/amd/display: Add switch for Fractional PWM on or off drm/amd/display: Read eDP link settings on detection Aric Cyr (1): drm/amd/display: 3.2.26 Christian König (1): drm/amdgpu: fix old fence check in amdgpu_fence_emit Chunming Zhou (2): drm/amdgpu: add timeline support in amdgpu CS v3 drm/amdgpu: update version for timeline syncobj support in amdgpu v2 David Francis (1): drm/amd/display: Handle get crtc position error Joshua Aberback (2): drm/amd/display: Add fast_validate parameter drm/amd/display: Add profiling tools for bandwidth validation Jun Lei (1): drm/amd/display: expand plane caps to include fp16 and scaling capability Nicholas Kazlauskas (11): drm/amd/display: Expose support for NV12 on suitable planes drm/amd/display: Add DRM color properties for primary planes drm/amd/display: Update plane scaling parameters for fast updates drm/amd/display: Maintain z-ordering when creating planes drm/amd/display: Recalculate pitch when buffers change drm/amd/display: Rework DC plane filling and surface updates drm/amd/display: Add basic downscale and upscale valdiation drm/amd/display: Use surface directly when checking update type drm/amd/display: Don't warn when DC update type > DM guess drm/amd/display: Check scaling info when determing update type drm/amd/display: Relax requirements for CRTCs to be enabled Samson Tam (1): drm/amd/display: change name from dc_link_get_verified_link_cap to dc_link_get_link_cap Yongqiang Sun (1): drm/amd/display: define HUBP_MASK_SH_LIST_DCN for Raven shaoyunl (2): drm/powerplay: Add smu set xgmi pstate interface drm/amdgpu: Set proper function to set xgmi pstate drivers/gpu/drm/amd/amdgpu/amdgpu.h| 10 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 152 - drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 24 +- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 13 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 745 + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 24 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 33 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc_stream.c| 3 +- drivers/gpu/drm/amd/display/dc/dc.h| 85 ++- drivers/gpu/drm/amd/display/dc/dc_link.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 18 + .../drm/amd/display/dc/dce100/dce100_resource.c| 22 +- .../drm/amd/display/dc/dce110/dce110_resource.c| 41 +- .../drm/amd/display/dc/dce112/dce112_resource.c| 22 +- .../drm/amd/display/dc/dce112/dce112_resource.h| 3 +- .../drm/amd/display/dc/dce120/dce120_resource.c| 19 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 22 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 9 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 20 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h| 3 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 3 +- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 + drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 9 +- include/uapi/drm/amdgpu_drm.h | 8 + 27 files changed, 944 insertions(+), 361 deletions(-) ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: fix spelling mistake "gateing" -> "gating"
On Wed, Apr 17, 2019 at 3:04 AM Mukesh Ojha wrote:
>
>
> On 4/16/2019 5:29 PM, Colin King wrote:
> > From: Colin Ian King
> >
> > There is a spelling mistake in a DRM_INFO message. Fix it.
> >
> > Signed-off-by: Colin Ian King
> Reviewed-by: Mukesh Ojha
Applied. thanks!
Alex
>
> Cheers,
> -Mukesh
> > ---
> > drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> > b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> > index bed78a778e3f..40363ca6c5f1 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> > @@ -283,7 +283,7 @@ static int vce_v2_0_stop(struct amdgpu_device *adev)
> > }
> >
> > if (vce_v2_0_wait_for_idle(adev)) {
> > - DRM_INFO("VCE is busy, Can't set clock gateing");
> > + DRM_INFO("VCE is busy, Can't set clock gating");
> > return 0;
> > }
> >
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Re: [PATCH] drm/amd/amdgpu: fix spelling mistake "recieve" -> "receive"
On Thu, Apr 18, 2019 at 1:58 PM Mukesh Ojha wrote:
>
>
> On 4/18/2019 3:55 PM, Colin King wrote:
> > From: Colin Ian King
> >
> > There is a spelling mistake in a pr_err message. Fix it.
> >
> > Signed-off-by: Colin Ian King
> Reviewed-by: Mukesh Ojha
Applied. thanks!
Alex
>
> Cheers,
> -Mukesh
> > ---
> > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > index 6a0fcd67662a..aef9d059ae52 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > @@ -515,7 +515,7 @@ static void xgpu_vi_mailbox_flr_work(struct work_struct
> > *work)
> >
> > /* wait until RCV_MSG become 3 */
> > if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
> > - pr_err("failed to recieve FLR_CMPL\n");
> > + pr_err("failed to receive FLR_CMPL\n");
> > return;
> > }
> >
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Re: [PATCH 1/6] drm/amd/powerplay: support hwmon temperature channel labels
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
>
> Expose temp[1-3]_label hwmon interfaces. While temp2_label
> and temp3_label are visible for SOC15 dGPUs only.
>
> Change-Id: I7f1e10c52ec21d272027554cdf6da97103e0be58
> Signed-off-by: Evan Quan
I'd suggest making this one last in the series since otherwise we'll
have labels without temps for a few commits.
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 40 +++
> .../gpu/drm/amd/include/kgd_pp_interface.h| 7
> 2 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 552127b74f78..c17eb228417e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -120,6 +120,15 @@ static const struct cg_flag_name clocks[] = {
> {0, NULL},
> };
>
> +static const struct hwmon_temp_label {
> + enum PP_HWMON_TEMP channel;
> + const char *label;
> +} temp_label[] = {
> + {PP_TEMP_JUNCTION, "junction"},
> + {PP_TEMP_EDGE, "edge"},
> + {PP_TEMP_MEM, "mem"},
> +};
> +
> void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
> {
> if (adev->pm.dpm_enabled) {
> @@ -1457,6 +1466,20 @@ static ssize_t amdgpu_hwmon_show_temp_thresh(struct
> device *dev,
> return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> }
>
> +
> +static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
> +struct device_attribute *attr,
> +char *buf)
> +{
> + struct amdgpu_device *adev = dev_get_drvdata(dev);
> + int channel = to_sensor_dev_attr(attr)->index;
> +
> + if (channel >= PP_TEMP_MAX)
> + return -EINVAL;
> +
> + return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
> +}
> +
> static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2026,6 +2049,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> *
> * hwmon interfaces for GPU temperature:
> *
> + * - temp[1-3]_label: temperature channel label
> + * - temp2_label and temp3_label are supported on SOC15 dGPUs only
> + *
> * - temp1_input: the on die GPU temperature in millidegrees Celsius
> *
> * - temp1_crit: temperature critical max value in millidegrees Celsius
> @@ -2081,6 +2107,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 1);
> +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO,
> amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
> +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO,
> amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
> +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO,
> amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
> static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1,
> amdgpu_hwmon_set_pwm1, 0);
> static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
> amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
> static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min,
> NULL, 0);
> @@ -2107,6 +2136,9 @@ static struct attribute *hwmon_attributes[] = {
> &sensor_dev_attr_temp1_input.dev_attr.attr,
> &sensor_dev_attr_temp1_crit.dev_attr.attr,
> &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
> + &sensor_dev_attr_temp1_label.dev_attr.attr,
> + &sensor_dev_attr_temp2_label.dev_attr.attr,
> + &sensor_dev_attr_temp3_label.dev_attr.attr,
> &sensor_dev_attr_pwm1.dev_attr.attr,
> &sensor_dev_attr_pwm1_enable.dev_attr.attr,
> &sensor_dev_attr_pwm1_min.dev_attr.attr,
> @@ -2229,6 +2261,14 @@ static umode_t hwmon_attributes_visible(struct kobject
> *kobj,
> attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
> return 0;
>
> + /* only SOC15 dGPUs support edge and mem temperatures */
> + if (((adev->flags & AMD_IS_APU) ||
> +adev->asic_type < CHIP_VEGA10) &&
> + (attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
> +attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
> + return 0;
> +
> +
> return effective_mode;
> }
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 2b579ba9b685..17324c0d503e 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -159,6 +159,13 @@ struct pp_states_info {
> uint32
Re: [PATCH 2/6] drm/amd/powerplay: support edge/memory critical limit values
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
>
> These new interfaces(temp2_crit, temp2_crit_hyst, temp3_crit,
> temp3_crit_hyst) are supported on SOC15 dGPUs only.
>
> Change-Id: Ia87e3f6ad816b51d6680eb74c8f755d6c2b0a6ae
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 8 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 51 +--
> .../drm/amd/powerplay/hwmgr/hardwaremanager.c | 12 -
> .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 6 +++
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 7 +++
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 7 +++
> .../gpu/drm/amd/powerplay/inc/power_state.h | 4 ++
> .../gpu/drm/amd/powerplay/inc/pp_thermal.h| 8 +--
> 8 files changed, 95 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index dca35407879d..e1492438ae7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -75,6 +75,14 @@ struct amdgpu_dpm_thermal {
> intmin_temp;
> /* high temperature threshold */
> intmax_temp;
> + /* edge low temperature threshold */
> + intmin_edge_temp;
> + /* edge high temperature critical threshold */
> + intmax_edge_crit_temp;
> + /* memory low temperature threshold */
> + intmin_mem_temp;
> + /* memory high temperature critical threshold */
> + intmax_mem_crit_temp;
> /* was last interrupt low to high or high to low */
> bool high_to_low;
> /* interrupt source */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index c17eb228417e..3f6b5b5bb0c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1466,6 +1466,37 @@ static ssize_t amdgpu_hwmon_show_temp_thresh(struct
> device *dev,
> return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> }
>
> +static ssize_t amdgpu_hwmon_show_edge_temp_thresh(struct device *dev,
> +struct device_attribute *attr,
> +char *buf)
> +{
> + struct amdgpu_device *adev = dev_get_drvdata(dev);
> + int hyst = to_sensor_dev_attr(attr)->index;
> + int temp;
> +
> + if (hyst)
> + temp = adev->pm.dpm.thermal.min_edge_temp;
> + else
> + temp = adev->pm.dpm.thermal.max_edge_crit_temp;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> +}
> +
> +static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
> +struct device_attribute *attr,
> +char *buf)
> +{
> + struct amdgpu_device *adev = dev_get_drvdata(dev);
> + int hyst = to_sensor_dev_attr(attr)->index;
> + int temp;
> +
> + if (hyst)
> + temp = adev->pm.dpm.thermal.min_mem_temp;
> + else
> + temp = adev->pm.dpm.thermal.max_mem_crit_temp;
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> +}
>
> static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
> struct device_attribute *attr,
> @@ -2054,9 +2085,11 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> *
> * - temp1_input: the on die GPU temperature in millidegrees Celsius
> *
> - * - temp1_crit: temperature critical max value in millidegrees Celsius
> + * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
> + * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
> *
> - * - temp1_crit_hyst: temperature hysteresis for critical limit in
> millidegrees Celsius
> + * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in
> millidegrees Celsius
> + * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
> *
> * hwmon interfaces for GPU voltage:
> *
> @@ -2107,6 +2140,10 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 1);
> +static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 0);
> +static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 1);
> +static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO,
> amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
> +static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
> static SENSOR_DEVICE_
Re: [PATCH 3/6] drm/amd/powerplay: support temperature emergency max values
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
>
> These new interfaces(temp1_emergency, temp2_emergency,
> temp3_emergency) are supported on SOC15 dGPUs only.
>
> Change-Id: I2552df63f9c8c50294b3940bb2a402217673c2bc
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 6 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 40 ++-
> .../drm/amd/powerplay/hwmgr/hardwaremanager.c | 6 +++
> .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 6 +++
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 6 +++
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 6 +++
> .../gpu/drm/amd/powerplay/inc/power_state.h | 3 ++
> .../gpu/drm/amd/powerplay/inc/pp_thermal.h| 12 --
> 8 files changed, 80 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index e1492438ae7b..32e2def42f30 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -75,14 +75,20 @@ struct amdgpu_dpm_thermal {
> intmin_temp;
> /* high temperature threshold */
> intmax_temp;
> + /* hotspot max emergency(shutdown) temp */
> + intmax_hotspot_emergency_temp;
> /* edge low temperature threshold */
> intmin_edge_temp;
> /* edge high temperature critical threshold */
> intmax_edge_crit_temp;
> + /* edge max emergency(shutdown) temp */
> + intmax_edge_emergency_temp;
> /* memory low temperature threshold */
> intmin_mem_temp;
> /* memory high temperature critical threshold */
> intmax_mem_crit_temp;
> + /* memory max emergency(shutdown) temp */
> + intmax_mem_emergency_temp;
> /* was last interrupt low to high or high to low */
> bool high_to_low;
> /* interrupt source */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 3f6b5b5bb0c6..be33144e2dca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1511,6 +1511,32 @@ static ssize_t amdgpu_hwmon_show_temp_label(struct
> device *dev,
> return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
> }
>
> +static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
> +struct device_attribute *attr,
> +char *buf)
> +{
> + struct amdgpu_device *adev = dev_get_drvdata(dev);
> + int channel = to_sensor_dev_attr(attr)->index;
> + int temp;
> +
> + if (channel >= PP_TEMP_MAX)
> + return -EINVAL;
> +
> + switch (channel) {
> + case PP_TEMP_JUNCTION:
> + temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
> + break;
> + case PP_TEMP_EDGE:
> + temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
> + break;
> + case PP_TEMP_MEM:
> + temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
> + break;
> + }
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> +}
> +
> static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2091,6 +2117,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in
> millidegrees Celsius
> * - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
> *
> + * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in
> millidegrees Celsius
> + * - these are supported on SOC15 dGPUs only
> + *
> * hwmon interfaces for GPU voltage:
> *
> * - in0_input: the voltage on the GPU in millivolts
> @@ -2140,10 +2169,13 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 1);
> +static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO,
> amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
> static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 1);
> +static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO,
> amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
> static SENSOR_DEVICE_ATTR(temp3_crit, S
Re: [PATCH 4/6] drm/amd/powerplay: support SMU metrics table on Vega12
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
>
> That should provide some necessary sensor information.
>
> Change-Id: I898371cef06795c5369a14c4dd3fe8717959d81a
> Signed-off-by: Evan Quan
Reviewed-by: Alex Deucher
> ---
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 21 +++
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.h| 3 +++
> .../drm/amd/powerplay/smumgr/vega12_smumgr.c | 21 +++
> 3 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index a283046347c9..695ac2875540 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1237,6 +1237,27 @@ static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr
> *hwmgr, bool low)
> return (mem_clk * 100);
> }
>
> +static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t
> *metrics_table)
> +{
> + struct vega12_hwmgr *data =
> + (struct vega12_hwmgr *)(hwmgr->backend);
> + int ret = 0;
> +
> + if (!data->metrics_time || time_after(jiffies, data->metrics_time +
> HZ / 2)) {
> + ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
> + TABLE_SMU_METRICS, true);
> + if (ret) {
> + pr_info("Failed to export SMU metrics table!\n");
> + return ret;
> + }
> + memcpy(&data->metrics_table, metrics_table,
> sizeof(SmuMetrics_t));
> + data->metrics_time = jiffies;
> + } else
> + memcpy(metrics_table, &data->metrics_table,
> sizeof(SmuMetrics_t));
> +
> + return ret;
> +}
> +
> static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
> {
> #if 0
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> index b3e424d28994..73875399666a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h
> @@ -396,6 +396,9 @@ struct vega12_hwmgr {
>
> /* Gfxoff */
> bool gfxoff_controlled_by_driver;
> +
> + unsigned long metrics_time;
> + SmuMetrics_t metrics_table;
> };
>
> #define VEGA12_DPM2_NEAR_TDP_DEC 10
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
> b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
> index ddb801517667..1eaf0fa28ef7 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c
> @@ -287,8 +287,26 @@ static int vega12_smu_init(struct pp_hwmgr *hwmgr)
> priv->smu_tables.entry[TABLE_OVERDRIVE].version = 0x01;
> priv->smu_tables.entry[TABLE_OVERDRIVE].size =
> sizeof(OverDriveTable_t);
>
> + /* allocate space for SMU_METRICS table */
> + ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
> + sizeof(SmuMetrics_t),
> + PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_VRAM,
> +
> &priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
> +
> &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
> +
> &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
> + if (ret)
> + goto err4;
> +
> + priv->smu_tables.entry[TABLE_SMU_METRICS].version = 0x01;
> + priv->smu_tables.entry[TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t);
> +
> return 0;
>
> +err4:
> + amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
> +
> &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
> +
> &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
> err3:
>
> amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].handle,
>
> &priv->smu_tables.entry[TABLE_AVFS_FUSE_OVERRIDE].mc_addr,
> @@ -334,6 +352,9 @@ static int vega12_smu_fini(struct pp_hwmgr *hwmgr)
>
> amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_OVERDRIVE].handle,
>
> &priv->smu_tables.entry[TABLE_OVERDRIVE].mc_addr,
>
> &priv->smu_tables.entry[TABLE_OVERDRIVE].table);
> +
> amdgpu_bo_free_kernel(&priv->smu_tables.entry[TABLE_SMU_METRICS].handle,
> +
> &priv->smu_tables.entry[TABLE_SMU_METRICS].mc_addr,
> +
> &priv->smu_tables.entry[TABLE_SMU_METRICS].table);
> kfree(hwmgr->smu_backend);
> hwmgr
Re: [PATCH 5/6] drm/amd/powerplay: expose current edge and memory temperatures
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
>
> Two new hwmon interfaces(temp2_input and temp3_input) are added.
> They are supported on SOC15 dGPUs only.
>
> Change-Id: I935c512bd38e080fb8b6e3164c5e5294baff4e91
> Signed-off-by: Evan Quan
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 45 +++
> .../gpu/drm/amd/include/kgd_pp_interface.h| 2 +
> .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 12 +
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 19
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 18
> 5 files changed, 88 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index be33144e2dca..1007307845d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1434,6 +1434,7 @@ static ssize_t amdgpu_hwmon_show_temp(struct device
> *dev,
> {
> struct amdgpu_device *adev = dev_get_drvdata(dev);
> struct drm_device *ddev = adev->ddev;
> + int channel = to_sensor_dev_attr(attr)->index;
> int r, temp, size = sizeof(temp);
>
> /* Can't get temperature when the card is off */
> @@ -1441,11 +1442,32 @@ static ssize_t amdgpu_hwmon_show_temp(struct device
> *dev,
> (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
> return -EINVAL;
>
> - /* get the temperature */
> - r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
> - (void *)&temp, &size);
> - if (r)
> - return r;
> + if (channel >= PP_TEMP_MAX)
> + return -EINVAL;
> +
> + switch (channel) {
> + case PP_TEMP_JUNCTION:
> + /* get current junction temperature */
> + r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP,
> + (void *)&temp, &size);
> + if (r)
> + return r;
> + break;
> + case PP_TEMP_EDGE:
> + /* get current edge temperature */
> + r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
> + (void *)&temp, &size);
> + if (r)
> + return r;
> + break;
> + case PP_TEMP_MEM:
> + /* get current memory temperature */
> + r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
> + (void *)&temp, &size);
> + if (r)
> + return r;
> + break;
> + }
>
> return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> }
> @@ -2109,7 +2131,8 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> * - temp[1-3]_label: temperature channel label
> * - temp2_label and temp3_label are supported on SOC15 dGPUs only
> *
> - * - temp1_input: the on die GPU temperature in millidegrees Celsius
> + * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
> + * - temp2_input and temp3_input are supported on SOC15 dGPUs only
> *
> * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
> * - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
> @@ -2166,13 +2189,15 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> device *dev,
> *
> */
>
> -static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, 0);
> +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, PP_TEMP_JUNCTION);
> static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_temp_thresh, NULL, 1);
> static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO,
> amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
> +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, PP_TEMP_EDGE);
> static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_edge_temp_thresh, NULL, 1);
> static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO,
> amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
> +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp,
> NULL, PP_TEMP_MEM);
> static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO,
> amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
> static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO,
> amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
> static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO,
> amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
> @@ -2205,8 +2230,10 @@ static struct attribute *hwmon_attributes[] = {
> &sensor_dev_attr_temp1_input.dev_attr.attr,
> &sensor_dev_attr_temp1_crit.dev_attr.attr,
> &sensor_dev_attr_temp1_crit_
Re: [PATCH 1/6] drm/amd/powerplay: support hwmon temperature channel labels
On Fri, Apr 19, 2019 at 11:08 AM Alex Deucher wrote:
>
> On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote:
> >
> > Expose temp[1-3]_label hwmon interfaces. While temp2_label
> > and temp3_label are visible for SOC15 dGPUs only.
> >
> > Change-Id: I7f1e10c52ec21d272027554cdf6da97103e0be58
> > Signed-off-by: Evan Quan
>
> I'd suggest making this one last in the series since otherwise we'll
> have labels without temps for a few commits.
> Reviewed-by: Alex Deucher
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 40 +++
> > .../gpu/drm/amd/include/kgd_pp_interface.h| 7
> > 2 files changed, 47 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > index 552127b74f78..c17eb228417e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > @@ -120,6 +120,15 @@ static const struct cg_flag_name clocks[] = {
> > {0, NULL},
> > };
> >
> > +static const struct hwmon_temp_label {
> > + enum PP_HWMON_TEMP channel;
> > + const char *label;
> > +} temp_label[] = {
> > + {PP_TEMP_JUNCTION, "junction"},
> > + {PP_TEMP_EDGE, "edge"},
Actually switch the order here. Other than vega20, existing asics
expose edge today, so lets make temp1 be edge and then temp2 be
junction and temp3 be memory.
Alex
> > + {PP_TEMP_MEM, "mem"},
> > +};
> > +
> > void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
> > {
> > if (adev->pm.dpm_enabled) {
> > @@ -1457,6 +1466,20 @@ static ssize_t amdgpu_hwmon_show_temp_thresh(struct
> > device *dev,
> > return snprintf(buf, PAGE_SIZE, "%d\n", temp);
> > }
> >
> > +
> > +static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
> > +struct device_attribute *attr,
> > +char *buf)
> > +{
> > + struct amdgpu_device *adev = dev_get_drvdata(dev);
> > + int channel = to_sensor_dev_attr(attr)->index;
> > +
> > + if (channel >= PP_TEMP_MAX)
> > + return -EINVAL;
> > +
> > + return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
> > +}
> > +
> > static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
> > struct device_attribute *attr,
> > char *buf)
> > @@ -2026,6 +2049,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> > device *dev,
> > *
> > * hwmon interfaces for GPU temperature:
> > *
> > + * - temp[1-3]_label: temperature channel label
> > + * - temp2_label and temp3_label are supported on SOC15 dGPUs only
> > + *
> > * - temp1_input: the on die GPU temperature in millidegrees Celsius
> > *
> > * - temp1_crit: temperature critical max value in millidegrees Celsius
> > @@ -2081,6 +2107,9 @@ static ssize_t amdgpu_hwmon_show_mclk_label(struct
> > device *dev,
> > static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp,
> > NULL, 0);
> > static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO,
> > amdgpu_hwmon_show_temp_thresh, NULL, 0);
> > static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
> > amdgpu_hwmon_show_temp_thresh, NULL, 1);
> > +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO,
> > amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
> > +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO,
> > amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
> > +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO,
> > amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
> > static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1,
> > amdgpu_hwmon_set_pwm1, 0);
> > static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
> > amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
> > static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min,
> > NULL, 0);
> > @@ -2107,6 +2136,9 @@ static struct attribute *hwmon_attributes[] = {
> > &sensor_dev_attr_temp1_input.dev_attr.attr,
> > &sensor_dev_attr_temp1_crit.dev_attr.attr,
> > &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
> > + &sensor_dev_attr_temp1_label.dev_attr.attr,
> > + &sensor_dev_attr_temp2_label.dev_attr.attr,
> > + &sensor_dev_attr_temp3_label.dev_attr.attr,
> > &sensor_dev_attr_pwm1.dev_attr.attr,
> > &sensor_dev_attr_pwm1_enable.dev_attr.attr,
> > &sensor_dev_attr_pwm1_min.dev_attr.attr,
> > @@ -2229,6 +2261,14 @@ static umode_t hwmon_attributes_visible(struct
> > kobject *kobj,
> > attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
> > return 0;
> >
> > + /* only SOC15 dGPUs support edge and mem temperatures */
> > + if (((adev->flags & AMD_IS_APU) ||
> > +adev->asic_type < CHIP_VEGA10) &&
> > + (attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
> > +attr == &sens
Re: [PATCH 6/6] drm/amd/powerplay: correct SOC15 hotspot temperature critical max
On Thu, Apr 18, 2019 at 5:03 AM Evan Quan wrote: > > Correct Vega10, Vega12 and Vega20 hotspot temperature critical max > values. > > Change-Id: I77bb77761e8530066ec4f3225f8555cf8f672348 > Signed-off-by: Evan Quan Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +- > drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +- > drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > index f4ecbbe854ee..efd9947eb723 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c > @@ -4871,7 +4871,7 @@ static int vega10_get_thermal_temperature_range(struct > pp_hwmgr *hwmgr, > > memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct > PP_TemperatureRange)); > > - thermal_data->max = table_info->tdp_table->usSoftwareShutdownTemp * > + thermal_data->max = pp_table->ThotspotLimit * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + > CTF_OFFSET_HOTSPOT) * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > index 86c48cb56f6c..ba35118a35b8 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c > @@ -2574,7 +2574,7 @@ static int vega12_get_thermal_temperature_range(struct > pp_hwmgr *hwmgr, > > memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct > PP_TemperatureRange)); > > - thermal_data->max = pptable_information->us_software_shutdown_temp * > + thermal_data->max = pp_table->ThotspotLimit * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + > CTF_OFFSET_HOTSPOT) * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > index 72a71a002f0b..8dcd04561e8f 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c > @@ -3989,7 +3989,7 @@ static int vega20_get_thermal_temperature_range(struct > pp_hwmgr *hwmgr, > > memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct > PP_TemperatureRange)); > > - thermal_data->max = pptable_information->us_software_shutdown_temp * > + thermal_data->max = pp_table->ThotspotLimit * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + > CTF_OFFSET_HOTSPOT) * > PP_TEMPERATURE_UNITS_PER_CENTIGRADES; > -- > 2.21.0 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 2/2] drm/amd/powerplay: expose Vega12 current gpu activity
On Thu, Apr 18, 2019 at 5:04 AM Evan Quan wrote:
>
> Provide the real sensor information for current gpu activity.
>
> Change-Id: I8449672a6fdabb4287e12e36a4f95e08e2d65e47
> Signed-off-by: Evan Quan
Series is:
Reviewed-by: Alex Deucher
> ---
> .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 21 ++-
> 1 file changed, 6 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index ad63372d9d0c..6f4bd15421e5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1310,23 +1310,14 @@ static int vega12_get_current_activity_percent(
> struct pp_hwmgr *hwmgr,
> uint32_t *activity_percent)
> {
> + SmuMetrics_t metrics_table;
> int ret = 0;
> - uint32_t current_activity = 50;
>
> -#if 0
> - ret = smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_GetAverageGfxActivity, 0);
> - if (!ret) {
> - current_activity = smum_get_argument(hwmgr);
> - if (current_activity > 100) {
> - PP_ASSERT(false,
> - "[GetCurrentActivityPercent] Activity
> Percentage Exceeds 100!");
> - current_activity = 100;
> - }
> - } else
> - PP_ASSERT(false,
> - "[GetCurrentActivityPercent] Attempt To Send Get
> Average Graphics Activity to SMU Failed!");
> -#endif
> - *activity_percent = current_activity;
> + ret = vega12_get_metrics_table(hwmgr, &metrics_table);
> + if (ret)
> + return ret;
> +
> + *activity_percent = metrics_table.AverageGfxActivity;
>
> return ret;
> }
> --
> 2.21.0
>
> ___
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 2/6] PCI/P2PDMA: start with a whitelist for root complexes
On Thu, Apr 18, 2019 at 8:09 AM Christian König
wrote:
>
> A lot of root complexes can still do P2P even when PCI devices
> don't share a common upstream bridge.
>
> Start adding a whitelist and allow P2P if both participants are
> attached to known good root complex.
>
> Signed-off-by: Christian König
> ---
> drivers/pci/p2pdma.c | 38 +++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
> index c52298d76e64..212baaa7f93b 100644
> --- a/drivers/pci/p2pdma.c
> +++ b/drivers/pci/p2pdma.c
> @@ -274,6 +274,31 @@ static void seq_buf_print_bus_devfn(struct seq_buf *buf,
> struct pci_dev *pdev)
> seq_buf_printf(buf, "%s;", pci_name(pdev));
> }
>
> +/*
> + * If we can't find a common upstream bridge take a look at the root complex
> and
> + * compare it to a whitelist of known good hardware.
> + */
> +static bool root_complex_whitelist(struct pci_dev *dev)
> +{
> + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
> + struct pci_dev *root = pci_get_slot(host->bus, PCI_DEVFN(0, 0));
> + unsigned short vendor, device;
> +
> + if (!root)
> + return false;
> +
> + vendor = root->vendor;
> + device = root->device;
> + pci_dev_put(root);
> +
> + /* AMD ZEN host bridges can do peer to peer */
> + if (vendor == PCI_VENDOR_ID_AMD && device == 0x1450)
We should also add:
(vendor == PCI_VENDOR_ID_AMD && device == 0x1576) // Carrizo
(vendor == PCI_VENDOR_ID_AMD && device == 0x1536) // Kaveri/kabini/mullins
Alex
> + return true;
> +
> + /* TODO: Extend that to a proper whitelist */
> + return false;
> +}
> +
> /*
> * Find the distance through the nearest common upstream bridge between
> * two PCI devices.
> @@ -317,13 +342,13 @@ static void seq_buf_print_bus_devfn(struct seq_buf
> *buf, struct pci_dev *pdev)
> * In this case, a list of all infringing bridge addresses will be
> * populated in acs_list (assuming it's non-null) for printk purposes.
> */
> -static int upstream_bridge_distance(struct pci_dev *a,
> - struct pci_dev *b,
> +static int upstream_bridge_distance(struct pci_dev *provider,
> + struct pci_dev *client,
> struct seq_buf *acs_list)
> {
> + struct pci_dev *a = provider, *b = client, *bb;
> int dist_a = 0;
> int dist_b = 0;
> - struct pci_dev *bb = NULL;
> int acs_cnt = 0;
>
> /*
> @@ -354,6 +379,13 @@ static int upstream_bridge_distance(struct pci_dev *a,
> dist_a++;
> }
>
> + /* Allow the connection if both devices are on a whitelisted root
> +* complex, but add an arbitary large value to the distance.
> +*/
> + if (root_complex_whitelist(provider) &&
> + root_complex_whitelist(client))
> + return 0x1000 + dist_a + dist_b;
> +
> return -1;
>
> check_b_path_acs:
> --
> 2.17.1
>
> ___
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 05/12] dma-buf: add explicit buffer pinning
On Tue, Apr 16, 2019 at 2:39 PM Christian König
wrote:
>
> Add optional explicit pinning callbacks instead of implicitly assume the
> exporter pins the buffer when a mapping is created.
>
> Signed-off-by: Christian König
> ---
> drivers/dma-buf/dma-buf.c | 39 +++
> include/linux/dma-buf.h | 37 +++--
> 2 files changed, 70 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
> index a3738fab3927..f23ff8355505 100644
> --- a/drivers/dma-buf/dma-buf.c
> +++ b/drivers/dma-buf/dma-buf.c
> @@ -630,6 +630,41 @@ void dma_buf_detach(struct dma_buf *dmabuf, struct
> dma_buf_attachment *attach)
> }
> EXPORT_SYMBOL_GPL(dma_buf_detach);
>
> +/**
> + * dma_buf_pin - Lock down the DMA-buf
> + *
> + * @dmabuf:[in]DMA-buf to lock down.
> + *
> + * Returns:
> + * 0 on success, negative error code on failure.
> + */
> +int dma_buf_pin(struct dma_buf *dmabuf)
> +{
> + int ret = 0;
> +
> + reservation_object_assert_held(dmabuf->resv);
> +
> + if (dmabuf->ops->pin)
> + ret = dmabuf->ops->pin(dmabuf);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(dma_buf_pin);
> +
> +/**
> + * dma_buf_unpin - Remove lock from DMA-buf
> + *
> + * @dmabuf:[in]DMA-buf to unlock.
> + */
> +void dma_buf_unpin(struct dma_buf *dmabuf)
> +{
> + reservation_object_assert_held(dmabuf->resv);
> +
> + if (dmabuf->ops->unpin)
> + dmabuf->ops->unpin(dmabuf);
> +}
> +EXPORT_SYMBOL_GPL(dma_buf_unpin);
> +
> /**
> * dma_buf_map_attachment_locked - Maps the buffer into _device_ address
> space
> * with the reservation lock held. Is a wrapper for map_dma_buf() of the
> @@ -666,6 +701,8 @@ dma_buf_map_attachment_locked(struct dma_buf_attachment
> *attach,
> */
> if (attach->invalidate)
> list_del(&attach->node);
> + else
> + dma_buf_pin(attach->dmabuf);
> sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction);
> if (attach->invalidate)
> list_add(&attach->node, &attach->dmabuf->attachments);
> @@ -735,6 +772,8 @@ void dma_buf_unmap_attachment_locked(struct
> dma_buf_attachment *attach,
>
> attach->dmabuf->ops->unmap_dma_buf(attach, sg_table,
> direction);
> + if (!attach->invalidate)
> + dma_buf_unpin(attach->dmabuf);
> }
> EXPORT_SYMBOL_GPL(dma_buf_unmap_attachment_locked);
>
> diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
> index ece4638359a8..a615b74e5894 100644
> --- a/include/linux/dma-buf.h
> +++ b/include/linux/dma-buf.h
> @@ -100,14 +100,40 @@ struct dma_buf_ops {
> */
> void (*detach)(struct dma_buf *, struct dma_buf_attachment *);
>
> + /**
> +* @pin_dma_buf:
> +*
> +* This is called by dma_buf_pin and lets the exporter know that an
> +* importer assumes that the DMA-buf can't be invalidated any more.
> +*
> +* This is called with the dmabuf->resv object locked.
> +*
> +* This callback is optional.
> +*
> +* Returns:
> +*
> +* 0 on success, negative error code on failure.
> +*/
> + int (*pin)(struct dma_buf *);
> +
> + /**
> +* @unpin_dma_buf:
> +*
> +* This is called by dma_buf_unpin and lets the exporter know that an
> + * importer doesn't need to the DMA-buf to stay were it is any more.
This should read:
* importer doesn't need the DMA-buf to stay were it is anymore.
> +*
> +* This is called with the dmabuf->resv object locked.
> +*
> +* This callback is optional.
> +*/
> + void (*unpin)(struct dma_buf *);
> +
> /**
> * @map_dma_buf:
> *
> * This is called by dma_buf_map_attachment() and is used to map a
> * shared &dma_buf into device address space, and it is mandatory. It
> -* can only be called if @attach has been called successfully. This
> -* essentially pins the DMA buffer into place, and it cannot be moved
> -* any more
> +* can only be called if @attach has been called successfully.
> *
> * This call may sleep, e.g. when the backing storage first needs to
> be
> * allocated, or moved to a location suitable for all currently
> attached
> @@ -148,9 +174,6 @@ struct dma_buf_ops {
> *
> * This is called by dma_buf_unmap_attachment() and should unmap and
> * release the &sg_table allocated in @map_dma_buf, and it is
> mandatory.
> -* It should also unpin the backing storage if this is the last
> mapping
> -* of the DMA buffer, it the exporter supports backing storage
> -* migration.
> *
> * This is always called with the dmabuf->resv object locked when
> * no_sg
Re: [PATCH 6/6] drm/amdgpu: add support for exporting VRAM using DMA-buf v2
On Thu, Apr 18, 2019 at 8:09 AM Christian König
wrote:
>
> We should be able to do this now after checking all the prerequisites.
>
> v2: fix entrie count in the sgt
>
> Signed-off-by: Christian König
Series is:
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c| 46 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 9 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 96
> 3 files changed, 142 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> index a290ae830b11..55bb39281c5d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
> @@ -318,22 +318,45 @@ amdgpu_gem_map_dma_buf(struct dma_buf_attachment
> *attach,
> }
>
> if (attach->invalidate) {
> - /* move buffer into GTT */
> + /* move buffer into GTT or VRAM */
> struct ttm_operation_ctx ctx = { false, false };
> + unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
>
> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
> + if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
> + attach->peer2peer) {
> + bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> + domains |= AMDGPU_GEM_DOMAIN_VRAM;
> + }
> + amdgpu_bo_placement_from_domain(bo, domains);
> r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> if (r)
> return ERR_PTR(r);
> }
>
> - sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages, bo->tbo.num_pages);
> - if (IS_ERR(sgt))
> - return sgt;
> + switch (bo->tbo.mem.mem_type) {
> + case TTM_PL_TT:
> + sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages,
> + bo->tbo.num_pages);
> + if (IS_ERR(sgt))
> + return sgt;
> +
> + if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
> + DMA_ATTR_SKIP_CPU_SYNC)) {
> + r = -EINVAL;
> + goto error_free;
> + }
> + break;
>
> - if (!dma_map_sg_attrs(attach->dev, sgt->sgl, sgt->nents, dir,
> - DMA_ATTR_SKIP_CPU_SYNC))
> + case TTM_PL_VRAM:
> + r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, attach->dev,
> + dir, &sgt);
> + if (r)
> + goto error_free;
> + break;
> + default:
> + r = -EINVAL;
> goto error_free;
> + }
>
> if (attach->dev->driver != adev->dev->driver)
> bo->prime_shared_count++;
> @@ -343,7 +366,7 @@ amdgpu_gem_map_dma_buf(struct dma_buf_attachment *attach,
> error_free:
> sg_free_table(sgt);
> kfree(sgt);
> - return ERR_PTR(-ENOMEM);
> + return ERR_PTR(r);
> }
>
> /**
> @@ -367,10 +390,15 @@ static void amdgpu_gem_unmap_dma_buf(struct
> dma_buf_attachment *attach,
> if (attach->dev->driver != adev->dev->driver &&
> bo->prime_shared_count)
> bo->prime_shared_count--;
>
> - if (sgt) {
> + if (!sgt)
> + return;
> +
> + if (sgt->sgl->page_link) {
> dma_unmap_sg(attach->dev, sgt->sgl, sgt->nents, dir);
> sg_free_table(sgt);
> kfree(sgt);
> + } else {
> + amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index c2b7669004ba..0b4cdbe867e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -72,6 +72,15 @@ uint64_t amdgpu_gtt_mgr_usage(struct ttm_mem_type_manager
> *man);
> int amdgpu_gtt_mgr_recover(struct ttm_mem_type_manager *man);
>
> u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
> +int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
> + struct ttm_mem_reg *mem,
> + struct device *dev,
> + enum dma_data_direction dir,
> + struct sg_table **sgt);
> +void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
> + struct device *dev,
> + enum dma_data_direction dir,
> + struct sg_table *sgt);
> uint64_t amdgpu_vram_mgr_usage(struct ttm_mem_type_manager *man);
> uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_mem_type_manager *man);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> i
