https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/107210
None
>From 8296e727435492d4a5b49deea76c098d6f54081f Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 4 Sep 2024 11:05:17 +0100
Subject: [PATCH] Add frontend for search
---
graphite-demo/frontend.jsx
SamTebbs33 wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/107210?utm_source=stack-comment-downstack-mergeability-warnin
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/107210
>From 4dae516fc2be004f79362b455b835754eeda953d Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 4 Sep 2024 11:05:17 +0100
Subject: [PATCH] Add frontend for search
---
graphite-demo/frontend.jsx | 56 +
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/107211
None
>From e99c4dca4bfb7bed5c3069e056fb566b9c655eaa Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 4 Sep 2024 11:07:55 +0100
Subject: [PATCH] Add user search
---
graphite-demo/frontend.jsx | 23 +++
SamTebbs33 wrote:
> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is
> open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/107211?utm_source=stack-comment-downstack-mergeability-warnin
https://github.com/SamTebbs33 closed
https://github.com/llvm/llvm-project/pull/107211
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Author: Sam Tebbs
Date: 2021-01-13T17:23:00Z
New Revision: 60fda8ebb6dc4e2ac1cc181c0ab8019c4309cb22
URL:
https://github.com/llvm/llvm-project/commit/60fda8ebb6dc4e2ac1cc181c0ab8019c4309cb22
DIFF:
https://github.com/llvm/llvm-project/commit/60fda8ebb6dc4e2ac1cc181c0ab8019c4309cb22.diff
LOG: [AR
Author: Sam Tebbs
Date: 2021-01-15T13:59:29Z
New Revision: 5e4480b6c0f02beef5ca7f62c3427031872fcd52
URL:
https://github.com/llvm/llvm-project/commit/5e4480b6c0f02beef5ca7f62c3427031872fcd52
DIFF:
https://github.com/llvm/llvm-project/commit/5e4480b6c0f02beef5ca7f62c3427031872fcd52.diff
LOG: [AR
Author: Sam Tebbs
Date: 2021-01-15T15:45:13Z
New Revision: 1a497ae9b83653682d6d20f1ec131394e523375d
URL:
https://github.com/llvm/llvm-project/commit/1a497ae9b83653682d6d20f1ec131394e523375d
DIFF:
https://github.com/llvm/llvm-project/commit/1a497ae9b83653682d6d20f1ec131394e523375d.diff
LOG: [AR
SamTebbs33 wrote:
I've rebased this on top of my PR that adds an intrinsic since that's less
fragile to match in the backend. So this should now be ready to have a look at.
https://github.com/llvm/llvm-project/pull/100579
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https://github.com/SamTebbs33 edited
https://github.com/llvm/llvm-project/pull/125252
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https://github.com/llvm/llvm-project/pull/125252
error: too big or took too long to generate
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https://github.com/SamTebbs33 approved this pull request.
It makes sense to merge this as it fixes a micompilation.
https://github.com/llvm/llvm-project/pull/126263
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@@ -5026,10 +5026,24 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
@@ -3177,6 +3177,420 @@ for.exit:; preds = %for.body
ret i32 %add
}
+define dso_local void @dotp_high_register_pressure(ptr %a, ptr %b, ptr %sum,
i32 %n) #1 {
SamTebbs33 wrote:
Added.
https://github.com/llvm/llvm-project/pull/13309
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/133090
This PR accounts for scaled reductions in `calculateRegisterUsage` to reflect
the fact that the number of lanes in their output is smaller than the VF.
>From 6193c2c846710472c7e604ef33a15cda18771328 Mon Sep
@@ -7772,12 +7551,23 @@ VectorizationFactor
LoopVectorizationPlanner::computeBestVF() {
InstructionCost Cost = cost(*P, VF);
VectorizationFactor CurrentFactor(VF, Cost, ScalarCost);
- if (isMoreProfitable(CurrentFactor, BestFactor))
-BestFactor = Curr
@@ -7759,7 +7535,10 @@ VectorizationFactor
LoopVectorizationPlanner::computeBestVF() {
}
for (auto &P : VPlans) {
-for (ElementCount VF : P->vectorFactors()) {
+SmallVector VFs(P->vectorFactors());
+auto RUs = ::calculateRegisterUsage(*P, VFs, TTI);
+for (
Valentin Clement =?utf-8?b?KOODkOODrOODsw==?=,zcfh <1412805...@qq.com>,Alexey
Bataev ,Florian Hahn ,Alexey Bataev
,Hristo Hristov ,Mircea
Trofin ,Florian Hahn ,Jonas Devlieghere
,Henry Jiang ,Alexander
Yermolovich <43973793+ayerm...@users.noreply.github.com>,Andy Kaylor
,Andy Kaylor ,Florian
Valentin Clement =?utf-8?b?KOODkOODrOODsw==?=,zcfh <1412805...@qq.com>,Alexey
Bataev ,Florian Hahn ,Alexey Bataev
,Hristo Hristov ,Mircea
Trofin ,Florian Hahn ,Jonas Devlieghere
,Henry Jiang ,Alexander
Yermolovich <43973793+ayerm...@users.noreply.github.com>,Andy Kaylor
,Andy Kaylor ,Florian
https://github.com/SamTebbs33 edited
https://github.com/llvm/llvm-project/pull/133090
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https://github.com/llvm/llvm-project/pull/132190
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@@ -253,38 +253,38 @@ define i64 @not_dotp_i8_to_i64_has_neon_dotprod(ptr
readonly %a, ptr readonly %b
; CHECK-MAXBW-SAME: ptr readonly [[A:%.*]], ptr readonly [[B:%.*]])
#[[ATTR1:[0-9]+]] {
; CHECK-MAXBW-NEXT: entry:
; CHECK-MAXBW-NEXT:[[TMP0:%.*]] = call i64 @llvm.vsca
@@ -2376,6 +2327,59 @@ class VPReductionRecipe : public VPRecipeWithIRFlags {
}
};
+/// A recipe for forming partial reductions. In the loop, an accumulator and
+/// vector operand are added together and passed to the next iteration as the
+/// next accumulator. After the lo
@@ -219,6 +219,8 @@ class TargetTransformInfo {
/// Get the kind of extension that an instruction represents.
static PartialReductionExtendKind
getPartialReductionExtendKind(Instruction *I);
+ static PartialReductionExtendKind
+ getPartialReductionExtendKind(Instruction
@@ -2056,55 +2056,6 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe,
}
};
-/// A recipe for forming partial reductions. In the loop, an accumulator and
SamTebbs33 wrote:
I don't think I could make it an NFC change, since to conform to
`VPReduction
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/136997
This PR adds support for extensions of different signedness to
VPMulAccumulateReductionRecipe and allows such partial reductions to be bundled
into that class.
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2
@@ -986,11 +986,23 @@ InstructionCost TargetTransformInfo::getShuffleCost(
TargetTransformInfo::PartialReductionExtendKind
TargetTransformInfo::getPartialReductionExtendKind(Instruction *I) {
- if (isa(I))
-return PR_SignExtend;
- if (isa(I))
+ auto *Cast = dyn_cast(I);
@@ -986,11 +986,23 @@ InstructionCost TargetTransformInfo::getShuffleCost(
TargetTransformInfo::PartialReductionExtendKind
TargetTransformInfo::getPartialReductionExtendKind(Instruction *I) {
- if (isa(I))
-return PR_SignExtend;
- if (isa(I))
+ auto *Cast = dyn_cast(I);
@@ -2432,12 +2437,40 @@ static void
tryToCreateAbstractReductionRecipe(VPReductionRecipe *Red,
Red->replaceAllUsesWith(AbstractR);
}
+/// This function tries to create an abstract recipe from a partial reduction
to
+/// hide its mul and extends from cost estimation.
+stati
@@ -2432,12 +2437,40 @@ static void
tryToCreateAbstractReductionRecipe(VPReductionRecipe *Red,
Red->replaceAllUsesWith(AbstractR);
}
+/// This function tries to create an abstract recipe from a partial reduction
to
+/// hide its mul and extends from cost estimation.
+stati
@@ -2056,55 +2056,6 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe,
}
};
-/// A recipe for forming partial reductions. In the loop, an accumulator and
SamTebbs33 wrote:
I've pre-committed the NFC but rebasing Elvis's changes on top of that has bee
@@ -4923,9 +4923,7 @@ InstructionCost AArch64TTIImpl::getPartialReductionCost(
return Invalid;
break;
case 16:
- if (AccumEVT == MVT::i64)
-Cost *= 2;
- else if (AccumEVT != MVT::i32)
+ if (AccumEVT != MVT::i32)
SamTebbs
@@ -2493,11 +2493,13 @@ class VPExtendedReductionRecipe : public
VPReductionRecipe {
/// recipe is abstract and needs to be lowered to concrete recipes before
/// codegen. The Operands are {ChainOp, VecOp1, VecOp2, [Condition]}.
class VPMulAccumulateReductionRecipe : public VP
@@ -2438,14 +2438,14 @@
VPMulAccumulateReductionRecipe::computeCost(ElementCount VF,
return Ctx.TTI.getPartialReductionCost(
Instruction::Add, Ctx.Types.inferScalarType(getVecOp0()),
Ctx.Types.inferScalarType(getVecOp1()), getResultType(), VF,
-TTI:
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/136997
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 23 Apr 2025 13:16:38 +0100
Subject: [PATCH 1/2] [LoopVectorizer] Bundle partial reductions with different
SamTebbs33 wrote:
Yeah that's the case :). Let me know if you have any issues applying it after
applying 113903 too.
https://github.com/llvm/llvm-project/pull/136173
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@@ -427,6 +428,29 @@ Value *VPInstruction::generate(VPTransformState &State) {
{PredTy, ScalarTC->getType()},
{VIVElem0, ScalarTC}, nullptr, Name);
}
+ // Count the number of bits set in each lane and redu
@@ -418,7 +418,13 @@ class LoopVectorizationPlanner {
/// Build VPlans for the specified \p UserVF and \p UserIC if they are
/// non-zero or all applicable candidate VFs otherwise. If vectorization and
/// interleaving should be avoided up-front, no plans are generated.
-
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/136997
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 23 Apr 2025 13:16:38 +0100
Subject: [PATCH 1/3] [LoopVectorizer] Bundle partial reductions with different
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/133090
>From 6193c2c846710472c7e604ef33a15cda18771328 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 26 Mar 2025 14:01:59 +
Subject: [PATCH 1/3] [LV] Reduce register usage for scaled reductions
---
...
@@ -5026,10 +5026,23 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
https://github.com/SamTebbs33 edited
https://github.com/llvm/llvm-project/pull/133090
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@@ -2031,17 +2033,19 @@ class VPReductionPHIRecipe : public VPHeaderPHIRecipe,
/// scalar value.
class VPPartialReductionRecipe : public VPSingleDefRecipe {
unsigned Opcode;
+ unsigned ScaleFactor;
SamTebbs33 wrote:
Done.
https://github.com/llvm/llvm-proje
@@ -5026,10 +5026,23 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/133090
>From d0a9e1c7e89abc5890d7303a2e22a9a56e2f022b Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 26 Mar 2025 14:01:59 +
Subject: [PATCH 1/6] [LV] Reduce register usage for scaled reductions
---
...
https://github.com/SamTebbs33 commented:
Apologies for the review requesting noise.
https://github.com/llvm/llvm-project/pull/133090
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https://github.com/llvm/llvm-project/pull/133090
>From 9a9164fce2a7fe1d602fd24cf9a9026b06190f31 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 26 Mar 2025 14:01:59 +
Subject: [PATCH 1/5] [LV] Reduce register usage for scaled reductions
---
...
SamTebbs33 wrote:
Good idea, done.
https://github.com/llvm/llvm-project/pull/133090
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@@ -5026,10 +5026,24 @@ calculateRegisterUsage(VPlan &Plan,
ArrayRef VFs,
// even in the scalar case.
RegUsage[ClassID] += 1;
} else {
+// The output from scaled phis and scaled reductions actually have
+// fewer lanes
@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
@@ -195,6 +195,13 @@ enum class TailFoldingStyle {
DataWithEVL,
};
+enum class RTCheckStyle {
+ /// Branch to scalar loop if checks fails at runtime.
+ ScalarFallback,
+ /// Form a mask based on elements which won't be a WAR or RAW hazard
SamTebbs33 wrote
@@ -3235,6 +3263,36 @@ void VPWidenPointerInductionRecipe::print(raw_ostream
&O, const Twine &Indent,
}
#endif
+void VPAliasLaneMaskRecipe::execute(VPTransformState &State) {
+ IRBuilderBase Builder = State.Builder;
+ Value *SinkValue = State.get(getSinkValue(), true);
+ V
@@ -3073,6 +3075,56 @@ struct VPWidenStoreEVLRecipe final : public
VPWidenMemoryRecipe {
}
};
+// Given a pointer A that is being stored to, and pointer B that is being
+// read from, both with unknown lengths, create a mask that disables
+// elements which could overlap ac
@@ -1416,14 +1466,14 @@ void VPlanTransforms::addActiveLaneMask(
auto *FoundWidenCanonicalIVUser =
find_if(Plan.getCanonicalIV()->users(),
[](VPUser *U) { return isa(U); });
- assert(FoundWidenCanonicalIVUser &&
+ assert(FoundWidenCanonicalIVUser && *Fou
@@ -1300,14 +1301,38 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
cast(CanonicalIVPHI->getBackedgeValue());
// TODO: Check if dropping the flags is needed if
// !DataAndControlFlowWithoutRuntimeCheck.
+ VPValue *IncVal = CanonicalIVIncre
@@ -3073,6 +3075,56 @@ struct VPWidenStoreEVLRecipe final : public
VPWidenMemoryRecipe {
}
};
+// Given a pointer A that is being stored to, and pointer B that is being
+// read from, both with unknown lengths, create a mask that disables
+// elements which could overlap ac
@@ -77,9 +77,13 @@ struct VPlanTransforms {
/// creation) and instead it is handled using active-lane-mask. \p
/// DataAndControlFlowWithoutRuntimeCheck implies \p
/// UseActiveLaneMaskForControlFlow.
+ /// RTChecks refers to the pointer pairs that need aliasing elements
@@ -1331,14 +1356,37 @@ static VPActiveLaneMaskPHIRecipe
*addVPLaneMaskPhiAndUpdateExitBranch(
"index.part.next");
// Create the active lane mask instruction in the VPlan preheader.
- auto *EntryALM =
+ VPValue *Mask =
Builder.createNaryOp(VPInstruction::Acti
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/136997
>From 10c4727074a7f5b4502ad08dc655be8fa5ffa3d2 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Wed, 23 Apr 2025 13:16:38 +0100
Subject: [PATCH 1/5] [LoopVectorizer] Bundle partial reductions with different
@@ -2586,22 +2590,21 @@ class VPMulAccumulateReductionRecipe : public
VPReductionRecipe {
VPValue *getVecOp1() const { return getOperand(2); }
/// Return if this MulAcc recipe contains extend instructions.
- bool isExtended() const { return ExtOp != Instruction::CastOps:
SamTebbs33 wrote:
Ping :)
https://github.com/llvm/llvm-project/pull/136173
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SamTebbs33 wrote:
Superseded by https://github.com/llvm/llvm-project/pull/144908
https://github.com/llvm/llvm-project/pull/136997
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https://github.com/SamTebbs33 closed
https://github.com/llvm/llvm-project/pull/136997
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SamTebbs33 wrote:
Really sorry for the spam again, I pushed to the user branch in my fork rather
than the base branch in llvm :facepalm:
https://github.com/llvm/llvm-project/pull/136997
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https://github.com/SamTebbs33 closed
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SamTebbs33 wrote:
Closed in favour of a PR based on top of
https://github.com/llvm/llvm-project/pull/147302
https://github.com/llvm/llvm-project/pull/146073
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@@ -2744,6 +2702,12 @@ class VPSingleDefBundleRecipe : public VPSingleDefRecipe
{
/// vector operands, performing a reduction.add on the result, and adding
/// the scalar result to a chain.
MulAccumulateReduction,
+/// Represent an inloop multiply-accumulate re
https://github.com/SamTebbs33 created
https://github.com/llvm/llvm-project/pull/147255
This PR bundles sub reductions into the VPExpressionRecipe class and adjusts
the cost functions to take the negation into account.
>From 1a5f4e42e4f9d1eae0222302dcabdf08492f67c3 Mon Sep 17 00:00:00 2001
From
https://github.com/SamTebbs33 updated
https://github.com/llvm/llvm-project/pull/147255
>From 1a5f4e42e4f9d1eae0222302dcabdf08492f67c3 Mon Sep 17 00:00:00 2001
From: Samuel Tebbs
Date: Mon, 30 Jun 2025 14:29:54 +0100
Subject: [PATCH 1/2] [LV] Bundle sub reductions into VPExpressionRecipe
This P
@@ -2725,6 +2729,31 @@ void VPExpressionRecipe::print(raw_ostream &O, const
Twine &Indent,
O << ")";
break;
}
+ case ExpressionTypes::ExtNegatedMulAccReduction: {
SamTebbs33 wrote:
That was my initial approach but it required checking the number of
@@ -1645,8 +1645,10 @@ class TargetTransformInfo {
/// extensions. This is the cost of as:
/// ResTy vecreduce.add(mul (A, B)).
/// ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)).
+ /// The multiply can optionally be negated, which signifies that it is a sub
+ /// reduct
@@ -5538,7 +5538,7 @@
LoopVectorizationCostModel::getReductionPatternCost(Instruction *I,
TTI::CastContextHint::None, CostKind, RedOp);
InstructionCost RedCost = TTI.getMulAccReductionCost(
-IsUnsigned, RdxDesc.getRecurrenceType(), Ext
@@ -3116,7 +3116,10 @@ class BasicTTIImplBase : public
TargetTransformInfoImplCRTPBase {
InstructionCost
getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty,
+ bool Negated,
TTI::TargetCostKind CostKind) co
@@ -2757,6 +2757,12 @@ class VPExpressionRecipe : public VPSingleDefRecipe {
/// vector operands, performing a reduction.add on the result, and adding
/// the scalar result to a chain.
MulAccReduction,
+/// Represent an inloop multiply-accumulate reduction, mult
@@ -1401,8 +1401,8 @@ static void analyzeCostOfVecReduction(const IntrinsicInst
&II,
TTI::CastContextHint::None, CostKind, RedOp);
CostBeforeReduction = ExtCost * 2 + MulCost + Ext2Cost;
-CostAfterReduction =
-TTI.getMulAccReductio
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